drm/msm: update generated headers
authorRob Clark <robdclark@gmail.com>
Mon, 8 Dec 2014 16:30:02 +0000 (11:30 -0500)
committerRob Clark <robdclark@gmail.com>
Sun, 1 Feb 2015 20:30:33 +0000 (15:30 -0500)
Resync from rnndb database, to pull in register defines for:
 * eDP
 * HDMI/HDCP
 * mdp4/mdp5 YUV support
 * mdp5 hw cursor support

Signed-off-by: Rob Clark <robdclark@gmail.com>
14 files changed:
drivers/gpu/drm/msm/adreno/a2xx.xml.h
drivers/gpu/drm/msm/adreno/a3xx.xml.h
drivers/gpu/drm/msm/adreno/a4xx.xml.h
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
drivers/gpu/drm/msm/dsi/dsi.xml.h
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
drivers/gpu/drm/msm/dsi/sfpb.xml.h
drivers/gpu/drm/msm/edp/edp.xml.h [new file with mode: 0644]
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
drivers/gpu/drm/msm/mdp/mdp_common.xml.h

index 22882cc0a5731c396e7a27075d42116e04193a8a..edc845fffdf4e4574501952ca3fd290c4b3fb028 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index 109e9a263daf6ac8e6d352e0791635e3a76e9ffa..e91a739452d7309653728991f8526197e38bd3b7 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -58,111 +58,130 @@ enum a3xx_cache_opcode {
 };
 
 enum a3xx_vtx_fmt {
-       VFMT_FLOAT_32 = 0,
-       VFMT_FLOAT_32_32 = 1,
-       VFMT_FLOAT_32_32_32 = 2,
-       VFMT_FLOAT_32_32_32_32 = 3,
-       VFMT_FLOAT_16 = 4,
-       VFMT_FLOAT_16_16 = 5,
-       VFMT_FLOAT_16_16_16 = 6,
-       VFMT_FLOAT_16_16_16_16 = 7,
-       VFMT_FIXED_32 = 8,
-       VFMT_FIXED_32_32 = 9,
-       VFMT_FIXED_32_32_32 = 10,
-       VFMT_FIXED_32_32_32_32 = 11,
-       VFMT_SHORT_16 = 16,
-       VFMT_SHORT_16_16 = 17,
-       VFMT_SHORT_16_16_16 = 18,
-       VFMT_SHORT_16_16_16_16 = 19,
-       VFMT_USHORT_16 = 20,
-       VFMT_USHORT_16_16 = 21,
-       VFMT_USHORT_16_16_16 = 22,
-       VFMT_USHORT_16_16_16_16 = 23,
-       VFMT_NORM_SHORT_16 = 24,
-       VFMT_NORM_SHORT_16_16 = 25,
-       VFMT_NORM_SHORT_16_16_16 = 26,
-       VFMT_NORM_SHORT_16_16_16_16 = 27,
-       VFMT_NORM_USHORT_16 = 28,
-       VFMT_NORM_USHORT_16_16 = 29,
-       VFMT_NORM_USHORT_16_16_16 = 30,
-       VFMT_NORM_USHORT_16_16_16_16 = 31,
-       VFMT_UINT_32 = 32,
-       VFMT_UINT_32_32 = 33,
-       VFMT_UINT_32_32_32 = 34,
-       VFMT_UINT_32_32_32_32 = 35,
-       VFMT_INT_32 = 36,
-       VFMT_INT_32_32 = 37,
-       VFMT_INT_32_32_32 = 38,
-       VFMT_INT_32_32_32_32 = 39,
-       VFMT_UBYTE_8 = 40,
-       VFMT_UBYTE_8_8 = 41,
-       VFMT_UBYTE_8_8_8 = 42,
-       VFMT_UBYTE_8_8_8_8 = 43,
-       VFMT_NORM_UBYTE_8 = 44,
-       VFMT_NORM_UBYTE_8_8 = 45,
-       VFMT_NORM_UBYTE_8_8_8 = 46,
-       VFMT_NORM_UBYTE_8_8_8_8 = 47,
-       VFMT_BYTE_8 = 48,
-       VFMT_BYTE_8_8 = 49,
-       VFMT_BYTE_8_8_8 = 50,
-       VFMT_BYTE_8_8_8_8 = 51,
-       VFMT_NORM_BYTE_8 = 52,
-       VFMT_NORM_BYTE_8_8 = 53,
-       VFMT_NORM_BYTE_8_8_8 = 54,
-       VFMT_NORM_BYTE_8_8_8_8 = 55,
-       VFMT_UINT_10_10_10_2 = 60,
-       VFMT_NORM_UINT_10_10_10_2 = 61,
-       VFMT_INT_10_10_10_2 = 62,
-       VFMT_NORM_INT_10_10_10_2 = 63,
+       VFMT_32_FLOAT = 0,
+       VFMT_32_32_FLOAT = 1,
+       VFMT_32_32_32_FLOAT = 2,
+       VFMT_32_32_32_32_FLOAT = 3,
+       VFMT_16_FLOAT = 4,
+       VFMT_16_16_FLOAT = 5,
+       VFMT_16_16_16_FLOAT = 6,
+       VFMT_16_16_16_16_FLOAT = 7,
+       VFMT_32_FIXED = 8,
+       VFMT_32_32_FIXED = 9,
+       VFMT_32_32_32_FIXED = 10,
+       VFMT_32_32_32_32_FIXED = 11,
+       VFMT_16_SINT = 16,
+       VFMT_16_16_SINT = 17,
+       VFMT_16_16_16_SINT = 18,
+       VFMT_16_16_16_16_SINT = 19,
+       VFMT_16_UINT = 20,
+       VFMT_16_16_UINT = 21,
+       VFMT_16_16_16_UINT = 22,
+       VFMT_16_16_16_16_UINT = 23,
+       VFMT_16_SNORM = 24,
+       VFMT_16_16_SNORM = 25,
+       VFMT_16_16_16_SNORM = 26,
+       VFMT_16_16_16_16_SNORM = 27,
+       VFMT_16_UNORM = 28,
+       VFMT_16_16_UNORM = 29,
+       VFMT_16_16_16_UNORM = 30,
+       VFMT_16_16_16_16_UNORM = 31,
+       VFMT_32_UINT = 32,
+       VFMT_32_32_UINT = 33,
+       VFMT_32_32_32_UINT = 34,
+       VFMT_32_32_32_32_UINT = 35,
+       VFMT_32_SINT = 36,
+       VFMT_32_32_SINT = 37,
+       VFMT_32_32_32_SINT = 38,
+       VFMT_32_32_32_32_SINT = 39,
+       VFMT_8_UINT = 40,
+       VFMT_8_8_UINT = 41,
+       VFMT_8_8_8_UINT = 42,
+       VFMT_8_8_8_8_UINT = 43,
+       VFMT_8_UNORM = 44,
+       VFMT_8_8_UNORM = 45,
+       VFMT_8_8_8_UNORM = 46,
+       VFMT_8_8_8_8_UNORM = 47,
+       VFMT_8_SINT = 48,
+       VFMT_8_8_SINT = 49,
+       VFMT_8_8_8_SINT = 50,
+       VFMT_8_8_8_8_SINT = 51,
+       VFMT_8_SNORM = 52,
+       VFMT_8_8_SNORM = 53,
+       VFMT_8_8_8_SNORM = 54,
+       VFMT_8_8_8_8_SNORM = 55,
+       VFMT_10_10_10_2_UINT = 60,
+       VFMT_10_10_10_2_UNORM = 61,
+       VFMT_10_10_10_2_SINT = 62,
+       VFMT_10_10_10_2_SNORM = 63,
 };
 
 enum a3xx_tex_fmt {
-       TFMT_NORM_USHORT_565 = 4,
-       TFMT_NORM_USHORT_5551 = 6,
-       TFMT_NORM_USHORT_4444 = 7,
-       TFMT_NORM_USHORT_Z16 = 9,
-       TFMT_NORM_UINT_X8Z24 = 10,
-       TFMT_FLOAT_Z32 = 11,
-       TFMT_NORM_UINT_NV12_UV_TILED = 17,
-       TFMT_NORM_UINT_NV12_Y_TILED = 19,
-       TFMT_NORM_UINT_NV12_UV = 21,
-       TFMT_NORM_UINT_NV12_Y = 23,
-       TFMT_NORM_UINT_I420_Y = 24,
-       TFMT_NORM_UINT_I420_U = 26,
-       TFMT_NORM_UINT_I420_V = 27,
-       TFMT_NORM_UINT_2_10_10_10 = 41,
-       TFMT_FLOAT_9_9_9_E5 = 42,
-       TFMT_FLOAT_10_11_11 = 43,
-       TFMT_NORM_UINT_A8 = 44,
-       TFMT_NORM_UINT_L8_A8 = 47,
-       TFMT_NORM_UINT_8 = 48,
-       TFMT_NORM_UINT_8_8 = 49,
-       TFMT_NORM_UINT_8_8_8 = 50,
-       TFMT_NORM_UINT_8_8_8_8 = 51,
-       TFMT_NORM_SINT_8_8 = 53,
-       TFMT_NORM_SINT_8_8_8_8 = 55,
-       TFMT_UINT_8_8 = 57,
-       TFMT_UINT_8_8_8_8 = 59,
-       TFMT_SINT_8_8 = 61,
-       TFMT_SINT_8_8_8_8 = 63,
-       TFMT_FLOAT_16 = 64,
-       TFMT_FLOAT_16_16 = 65,
-       TFMT_FLOAT_16_16_16_16 = 67,
-       TFMT_UINT_16 = 68,
-       TFMT_UINT_16_16 = 69,
-       TFMT_UINT_16_16_16_16 = 71,
-       TFMT_SINT_16 = 72,
-       TFMT_SINT_16_16 = 73,
-       TFMT_SINT_16_16_16_16 = 75,
-       TFMT_FLOAT_32 = 84,
-       TFMT_FLOAT_32_32 = 85,
-       TFMT_FLOAT_32_32_32_32 = 87,
-       TFMT_UINT_32 = 88,
-       TFMT_UINT_32_32 = 89,
-       TFMT_UINT_32_32_32_32 = 91,
-       TFMT_SINT_32 = 92,
-       TFMT_SINT_32_32 = 93,
-       TFMT_SINT_32_32_32_32 = 95,
+       TFMT_5_6_5_UNORM = 4,
+       TFMT_5_5_5_1_UNORM = 5,
+       TFMT_4_4_4_4_UNORM = 7,
+       TFMT_Z16_UNORM = 9,
+       TFMT_X8Z24_UNORM = 10,
+       TFMT_Z32_FLOAT = 11,
+       TFMT_NV12_UV_TILED = 17,
+       TFMT_NV12_Y_TILED = 19,
+       TFMT_NV12_UV = 21,
+       TFMT_NV12_Y = 23,
+       TFMT_I420_Y = 24,
+       TFMT_I420_U = 26,
+       TFMT_I420_V = 27,
+       TFMT_DXT1 = 36,
+       TFMT_DXT3 = 37,
+       TFMT_DXT5 = 38,
+       TFMT_10_10_10_2_UNORM = 41,
+       TFMT_9_9_9_E5_FLOAT = 42,
+       TFMT_11_11_10_FLOAT = 43,
+       TFMT_A8_UNORM = 44,
+       TFMT_L8_A8_UNORM = 47,
+       TFMT_8_UNORM = 48,
+       TFMT_8_8_UNORM = 49,
+       TFMT_8_8_8_UNORM = 50,
+       TFMT_8_8_8_8_UNORM = 51,
+       TFMT_8_SNORM = 52,
+       TFMT_8_8_SNORM = 53,
+       TFMT_8_8_8_SNORM = 54,
+       TFMT_8_8_8_8_SNORM = 55,
+       TFMT_8_UINT = 56,
+       TFMT_8_8_UINT = 57,
+       TFMT_8_8_8_UINT = 58,
+       TFMT_8_8_8_8_UINT = 59,
+       TFMT_8_SINT = 60,
+       TFMT_8_8_SINT = 61,
+       TFMT_8_8_8_SINT = 62,
+       TFMT_8_8_8_8_SINT = 63,
+       TFMT_16_FLOAT = 64,
+       TFMT_16_16_FLOAT = 65,
+       TFMT_16_16_16_16_FLOAT = 67,
+       TFMT_16_UINT = 68,
+       TFMT_16_16_UINT = 69,
+       TFMT_16_16_16_16_UINT = 71,
+       TFMT_16_SINT = 72,
+       TFMT_16_16_SINT = 73,
+       TFMT_16_16_16_16_SINT = 75,
+       TFMT_16_UNORM = 76,
+       TFMT_16_16_UNORM = 77,
+       TFMT_16_16_16_16_UNORM = 79,
+       TFMT_16_SNORM = 80,
+       TFMT_16_16_SNORM = 81,
+       TFMT_16_16_16_16_SNORM = 83,
+       TFMT_32_FLOAT = 84,
+       TFMT_32_32_FLOAT = 85,
+       TFMT_32_32_32_32_FLOAT = 87,
+       TFMT_32_UINT = 88,
+       TFMT_32_32_UINT = 89,
+       TFMT_32_32_32_32_UINT = 91,
+       TFMT_32_SINT = 92,
+       TFMT_32_32_SINT = 93,
+       TFMT_32_32_32_32_SINT = 95,
+       TFMT_RGTC2_SNORM = 112,
+       TFMT_RGTC2_UNORM = 113,
+       TFMT_RGTC1_SNORM = 114,
+       TFMT_RGTC1_UNORM = 115,
 };
 
 enum a3xx_tex_fetchsize {
@@ -180,9 +199,11 @@ enum a3xx_color_fmt {
        RB_R4G4B4A4_UNORM = 3,
        RB_R8G8B8_UNORM = 4,
        RB_R8G8B8A8_UNORM = 8,
+       RB_R8G8B8A8_SNORM = 9,
        RB_R8G8B8A8_UINT = 10,
        RB_R8G8B8A8_SINT = 11,
        RB_R8G8_UNORM = 12,
+       RB_R8G8_SNORM = 13,
        RB_R8_UINT = 14,
        RB_R8_SINT = 15,
        RB_R10G10B10A2_UNORM = 16,
@@ -258,6 +279,14 @@ enum a3xx_tex_clamp {
        A3XX_TEX_MIRROR_CLAMP = 4,
 };
 
+enum a3xx_tex_aniso {
+       A3XX_TEX_ANISO_1 = 0,
+       A3XX_TEX_ANISO_2 = 1,
+       A3XX_TEX_ANISO_4 = 2,
+       A3XX_TEX_ANISO_8 = 3,
+       A3XX_TEX_ANISO_16 = 4,
+};
+
 enum a3xx_tex_swiz {
        A3XX_TEX_X = 0,
        A3XX_TEX_Y = 1,
@@ -1563,12 +1592,13 @@ static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
 {
        return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
 }
-#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                 0x0001ff80
+#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                 0x0000ff80
 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                        7
 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
 {
        return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
 }
+#define A3XX_VFD_FETCH_INSTR_0_INSTANCED                       0x00010000
 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT                      0x00020000
 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK                 0x00fc0000
 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT                        18
@@ -2509,6 +2539,12 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
 {
        return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
 }
+#define A3XX_TEX_SAMP_0_ANISO__MASK                            0x00038000
+#define A3XX_TEX_SAMP_0_ANISO__SHIFT                           15
+static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
+{
+       return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
+}
 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK                     0x00700000
 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT                    20
 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
index 5a24c416d2dd1d864033a2652e72c1e6baebb262..755723fd8ba5472473bee61b3153af2ecf5af069 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -63,72 +63,82 @@ enum a4xx_rb_blend_opcode {
 };
 
 enum a4xx_vtx_fmt {
-       VFMT4_FLOAT_32 = 1,
-       VFMT4_FLOAT_32_32 = 2,
-       VFMT4_FLOAT_32_32_32 = 3,
-       VFMT4_FLOAT_32_32_32_32 = 4,
-       VFMT4_FLOAT_16 = 5,
-       VFMT4_FLOAT_16_16 = 6,
-       VFMT4_FLOAT_16_16_16 = 7,
-       VFMT4_FLOAT_16_16_16_16 = 8,
-       VFMT4_FIXED_32 = 9,
-       VFMT4_FIXED_32_32 = 10,
-       VFMT4_FIXED_32_32_32 = 11,
-       VFMT4_FIXED_32_32_32_32 = 12,
-       VFMT4_SHORT_16 = 16,
-       VFMT4_SHORT_16_16 = 17,
-       VFMT4_SHORT_16_16_16 = 18,
-       VFMT4_SHORT_16_16_16_16 = 19,
-       VFMT4_USHORT_16 = 20,
-       VFMT4_USHORT_16_16 = 21,
-       VFMT4_USHORT_16_16_16 = 22,
-       VFMT4_USHORT_16_16_16_16 = 23,
-       VFMT4_NORM_SHORT_16 = 24,
-       VFMT4_NORM_SHORT_16_16 = 25,
-       VFMT4_NORM_SHORT_16_16_16 = 26,
-       VFMT4_NORM_SHORT_16_16_16_16 = 27,
-       VFMT4_NORM_USHORT_16 = 28,
-       VFMT4_NORM_USHORT_16_16 = 29,
-       VFMT4_NORM_USHORT_16_16_16 = 30,
-       VFMT4_NORM_USHORT_16_16_16_16 = 31,
-       VFMT4_UBYTE_8 = 40,
-       VFMT4_UBYTE_8_8 = 41,
-       VFMT4_UBYTE_8_8_8 = 42,
-       VFMT4_UBYTE_8_8_8_8 = 43,
-       VFMT4_NORM_UBYTE_8 = 44,
-       VFMT4_NORM_UBYTE_8_8 = 45,
-       VFMT4_NORM_UBYTE_8_8_8 = 46,
-       VFMT4_NORM_UBYTE_8_8_8_8 = 47,
-       VFMT4_BYTE_8 = 48,
-       VFMT4_BYTE_8_8 = 49,
-       VFMT4_BYTE_8_8_8 = 50,
-       VFMT4_BYTE_8_8_8_8 = 51,
-       VFMT4_NORM_BYTE_8 = 52,
-       VFMT4_NORM_BYTE_8_8 = 53,
-       VFMT4_NORM_BYTE_8_8_8 = 54,
-       VFMT4_NORM_BYTE_8_8_8_8 = 55,
-       VFMT4_UINT_10_10_10_2 = 60,
-       VFMT4_NORM_UINT_10_10_10_2 = 61,
-       VFMT4_INT_10_10_10_2 = 62,
-       VFMT4_NORM_INT_10_10_10_2 = 63,
+       VFMT4_32_FLOAT = 1,
+       VFMT4_32_32_FLOAT = 2,
+       VFMT4_32_32_32_FLOAT = 3,
+       VFMT4_32_32_32_32_FLOAT = 4,
+       VFMT4_16_FLOAT = 5,
+       VFMT4_16_16_FLOAT = 6,
+       VFMT4_16_16_16_FLOAT = 7,
+       VFMT4_16_16_16_16_FLOAT = 8,
+       VFMT4_32_FIXED = 9,
+       VFMT4_32_32_FIXED = 10,
+       VFMT4_32_32_32_FIXED = 11,
+       VFMT4_32_32_32_32_FIXED = 12,
+       VFMT4_16_SINT = 16,
+       VFMT4_16_16_SINT = 17,
+       VFMT4_16_16_16_SINT = 18,
+       VFMT4_16_16_16_16_SINT = 19,
+       VFMT4_16_UINT = 20,
+       VFMT4_16_16_UINT = 21,
+       VFMT4_16_16_16_UINT = 22,
+       VFMT4_16_16_16_16_UINT = 23,
+       VFMT4_16_SNORM = 24,
+       VFMT4_16_16_SNORM = 25,
+       VFMT4_16_16_16_SNORM = 26,
+       VFMT4_16_16_16_16_SNORM = 27,
+       VFMT4_16_UNORM = 28,
+       VFMT4_16_16_UNORM = 29,
+       VFMT4_16_16_16_UNORM = 30,
+       VFMT4_16_16_16_16_UNORM = 31,
+       VFMT4_32_32_SINT = 37,
+       VFMT4_8_UINT = 40,
+       VFMT4_8_8_UINT = 41,
+       VFMT4_8_8_8_UINT = 42,
+       VFMT4_8_8_8_8_UINT = 43,
+       VFMT4_8_UNORM = 44,
+       VFMT4_8_8_UNORM = 45,
+       VFMT4_8_8_8_UNORM = 46,
+       VFMT4_8_8_8_8_UNORM = 47,
+       VFMT4_8_SINT = 48,
+       VFMT4_8_8_SINT = 49,
+       VFMT4_8_8_8_SINT = 50,
+       VFMT4_8_8_8_8_SINT = 51,
+       VFMT4_8_SNORM = 52,
+       VFMT4_8_8_SNORM = 53,
+       VFMT4_8_8_8_SNORM = 54,
+       VFMT4_8_8_8_8_SNORM = 55,
+       VFMT4_10_10_10_2_UINT = 60,
+       VFMT4_10_10_10_2_UNORM = 61,
+       VFMT4_10_10_10_2_SINT = 62,
+       VFMT4_10_10_10_2_SNORM = 63,
 };
 
 enum a4xx_tex_fmt {
-       TFMT4_NORM_USHORT_565 = 11,
-       TFMT4_NORM_USHORT_5551 = 10,
-       TFMT4_NORM_USHORT_4444 = 8,
-       TFMT4_NORM_UINT_X8Z24 = 71,
-       TFMT4_NORM_UINT_2_10_10_10 = 33,
-       TFMT4_NORM_UINT_A8 = 3,
-       TFMT4_NORM_UINT_L8_A8 = 13,
-       TFMT4_NORM_UINT_8 = 4,
-       TFMT4_NORM_UINT_8_8_8_8 = 28,
-       TFMT4_FLOAT_16 = 20,
-       TFMT4_FLOAT_16_16 = 40,
-       TFMT4_FLOAT_16_16_16_16 = 53,
-       TFMT4_FLOAT_32 = 43,
-       TFMT4_FLOAT_32_32 = 56,
-       TFMT4_FLOAT_32_32_32_32 = 63,
+       TFMT4_5_6_5_UNORM = 11,
+       TFMT4_5_5_5_1_UNORM = 10,
+       TFMT4_4_4_4_4_UNORM = 8,
+       TFMT4_X8Z24_UNORM = 71,
+       TFMT4_10_10_10_2_UNORM = 33,
+       TFMT4_A8_UNORM = 3,
+       TFMT4_L8_A8_UNORM = 13,
+       TFMT4_8_UNORM = 4,
+       TFMT4_8_8_UNORM = 14,
+       TFMT4_8_8_8_8_UNORM = 28,
+       TFMT4_16_FLOAT = 20,
+       TFMT4_16_16_FLOAT = 40,
+       TFMT4_16_16_16_16_FLOAT = 53,
+       TFMT4_32_FLOAT = 43,
+       TFMT4_32_32_FLOAT = 56,
+       TFMT4_32_32_32_32_FLOAT = 63,
+};
+
+enum a4xx_tex_fetchsize {
+       TFETCH4_1_BYTE = 0,
+       TFETCH4_2_BYTE = 1,
+       TFETCH4_4_BYTE = 2,
+       TFETCH4_8_BYTE = 3,
+       TFETCH4_16_BYTE = 4,
 };
 
 enum a4xx_depth_format {
@@ -264,14 +274,19 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
        return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
 }
 
-#define REG_A4XX_RB_MSAA_CONTROL2                              0x000020a3
-#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK               0x00000380
-#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT              7
-static inline uint32_t A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(uint32_t val)
+#define REG_A4XX_RB_RENDER_CONTROL2                            0x000020a3
+#define A4XX_RB_RENDER_CONTROL2_XCOORD                         0x00000001
+#define A4XX_RB_RENDER_CONTROL2_YCOORD                         0x00000002
+#define A4XX_RB_RENDER_CONTROL2_ZCOORD                         0x00000004
+#define A4XX_RB_RENDER_CONTROL2_WCOORD                         0x00000008
+#define A4XX_RB_RENDER_CONTROL2_FACENESS                       0x00000020
+#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK             0x00000380
+#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT            7
+static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
 {
-       return ((val) << A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK;
+       return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
 }
-#define A4XX_RB_MSAA_CONTROL2_VARYING                          0x00001000
+#define A4XX_RB_RENDER_CONTROL2_VARYING                                0x00001000
 
 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
 
@@ -362,7 +377,69 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
        return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
 }
 
+#define REG_A4XX_RB_BLEND_RED                                  0x000020f3
+#define A4XX_RB_BLEND_RED_UINT__MASK                           0x00007fff
+#define A4XX_RB_BLEND_RED_UINT__SHIFT                          0
+static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
+{
+       return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
+}
+#define A4XX_RB_BLEND_RED_FLOAT__MASK                          0xffff0000
+#define A4XX_RB_BLEND_RED_FLOAT__SHIFT                         16
+static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
+{
+       return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
+}
+
+#define REG_A4XX_RB_BLEND_GREEN                                        0x000020f4
+#define A4XX_RB_BLEND_GREEN_UINT__MASK                         0x00007fff
+#define A4XX_RB_BLEND_GREEN_UINT__SHIFT                                0
+static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
+{
+       return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
+}
+#define A4XX_RB_BLEND_GREEN_FLOAT__MASK                                0xffff0000
+#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT                       16
+static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
+{
+       return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
+}
+
+#define REG_A4XX_RB_BLEND_BLUE                                 0x000020f5
+#define A4XX_RB_BLEND_BLUE_UINT__MASK                          0x00007fff
+#define A4XX_RB_BLEND_BLUE_UINT__SHIFT                         0
+static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
+{
+       return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
+}
+#define A4XX_RB_BLEND_BLUE_FLOAT__MASK                         0xffff0000
+#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT                                16
+static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
+{
+       return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
+}
+
+#define REG_A4XX_RB_BLEND_ALPHA                                        0x000020f6
+#define A4XX_RB_BLEND_ALPHA_UINT__MASK                         0x00007fff
+#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT                                0
+static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
+{
+       return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
+}
+#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK                                0xffff0000
+#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT                       16
+static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
+{
+       return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
+}
+
 #define REG_A4XX_RB_ALPHA_CONTROL                              0x000020f8
+#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK                  0x000000ff
+#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT                 0
+static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
+{
+       return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
+}
 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST                       0x00000100
 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK            0x00000e00
 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT           9
@@ -372,7 +449,7 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare
 }
 
 #define REG_A4XX_RB_FS_OUTPUT                                  0x000020f9
-#define A4XX_RB_FS_OUTPUT_ENABLE_COLOR_PIPE                    0x00000001
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND                         0x00000001
 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR                           0x00000100
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK                    0xffff0000
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT                   16
@@ -416,11 +493,11 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
 }
 
 #define REG_A4XX_RB_COPY_DEST_BASE                             0x000020fd
-#define A4XX_RB_COPY_DEST_BASE_BASE__MASK                      0xfffffff0
-#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT                     4
+#define A4XX_RB_COPY_DEST_BASE_BASE__MASK                      0xffffffe0
+#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT                     5
 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
 {
-       return ((val >> 4) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
+       return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
 }
 
 #define REG_A4XX_RB_COPY_DEST_PITCH                            0x000020fe
@@ -508,7 +585,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 #define A4XX_RB_DEPTH_PITCH__SHIFT                             0
 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
 {
-       return ((val >> 4) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
+       return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
 }
 
 #define REG_A4XX_RB_DEPTH_PITCH2                               0x00002105
@@ -516,7 +593,7 @@ static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
 #define A4XX_RB_DEPTH_PITCH2__SHIFT                            0
 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
 {
-       return ((val >> 4) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
+       return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
 }
 
 #define REG_A4XX_RB_STENCIL_CONTROL                            0x00002106
@@ -630,7 +707,11 @@ static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
        return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
 }
 
-#define REG_A4XX_RB_VPORT_Z_CLAMP_MAX_15                       0x0000213f
+static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
+
+static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
+
+static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
 
 #define REG_A4XX_RBBM_HW_VERSION                               0x00000000
 
@@ -1121,7 +1202,9 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
 {
        return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
 }
+#define A4XX_SP_FS_CTRL_REG1_FACENESS                          0x00080000
 #define A4XX_SP_FS_CTRL_REG1_VARYING                           0x00100000
+#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD                         0x00200000
 
 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG                          0x000022ea
 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK      0x01ff0000
@@ -1384,6 +1467,12 @@ static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
 #define REG_A4XX_VFD_CONTROL_2                                 0x00002202
 
 #define REG_A4XX_VFD_CONTROL_3                                 0x00002203
+#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK                  0x0000ff00
+#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT                 8
+static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
+{
+       return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
+}
 
 #define REG_A4XX_VFD_CONTROL_4                                 0x00002204
 
@@ -1405,12 +1494,7 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
        return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
 }
 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT                      0x00080000
-#define A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK                  0xff000000
-#define A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT                 24
-static inline uint32_t A4XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
-{
-       return ((val) << A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
-}
+#define A4XX_VFD_FETCH_INSTR_0_INSTANCED                       0x00100000
 
 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
 
@@ -1423,6 +1507,12 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
 }
 
 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
+#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK                  0x000001ff
+#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT                 0
+static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
+{
+       return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
+}
 
 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
 
@@ -1446,6 +1536,7 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
 {
        return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
 }
+#define A4XX_VFD_DECODE_INSTR_INT                              0x00100000
 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK                       0x00c00000
 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT                      22
 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
@@ -1585,7 +1676,47 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
        return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
-#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL                      0x0000209f
+#define REG_A4XX_GRAS_DEPTH_CONTROL                            0x00002077
+#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                   0x00000003
+#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                  0
+static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
+{
+       return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
+}
+
+#define REG_A4XX_GRAS_SU_MODE_CONTROL                          0x00002078
+#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                   0x00000001
+#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK                    0x00000002
+#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW                     0x00000004
+#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK          0x000007f8
+#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT         3
+static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
+{
+       return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
+}
+#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                  0x00000800
+#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS               0x00100000
+
+#define REG_A4XX_GRAS_SC_CONTROL                               0x0000207b
+#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                 0x0000000c
+#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                        2
+static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
+{
+       return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
+}
+#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                        0x00000380
+#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT               7
+static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
+{
+       return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
+}
+#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE                      0x00000800
+#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                 0x0000f000
+#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                        12
+static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
+{
+       return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
+}
 
 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL                     0x0000207c
 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE   0x80000000
@@ -1647,46 +1778,34 @@ static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
        return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
 }
 
-#define REG_A4XX_GRAS_DEPTH_CONTROL                            0x00002077
-#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                   0x00000003
-#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                  0
-static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
+#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR                      0x0000209e
+#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE    0x80000000
+#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK                  0x00007fff
+#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT                 0
+static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
 {
-       return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
+       return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
 }
-
-#define REG_A4XX_GRAS_SU_MODE_CONTROL                          0x00002078
-#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                   0x00000001
-#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK                    0x00000002
-#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW                     0x00000004
-#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK          0x000007f8
-#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT         3
-static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
+#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK                  0x7fff0000
+#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT                 16
+static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
 {
-       return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
+       return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
 }
-#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                  0x00000800
-#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS               0x00100000
 
-#define REG_A4XX_GRAS_SC_CONTROL                               0x0000207b
-#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                 0x0000000c
-#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                        2
-static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
-{
-       return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
-}
-#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                        0x00000380
-#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT               7
-static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
+#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL                      0x0000209f
+#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE    0x80000000
+#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK                  0x00007fff
+#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT                 0
+static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
 {
-       return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
+       return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
 }
-#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE                      0x00000800
-#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                 0x0000f000
-#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                        12
-static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
+#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK                  0x7fff0000
+#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT                 16
+static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
 {
-       return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
+       return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
 }
 
 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL                       0x00000e80
@@ -1742,6 +1861,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize
 }
 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE            0x00000100
 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1                      0x00000200
+#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK               0x00ff0000
+#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT              16
+static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
+}
 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD                                0x02000000
 
 #define REG_A4XX_HLSQ_CONTROL_2_REG                            0x000023c2
@@ -1751,6 +1876,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
 }
+#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK                        0x000003fc
+#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT               2
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
+}
 
 #define REG_A4XX_HLSQ_CONTROL_3_REG                            0x000023c3
 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK                    0x000000ff
@@ -1965,15 +2096,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 
 #define REG_A4XX_UNKNOWN_20F2                                  0x000020f2
 
-#define REG_A4XX_UNKNOWN_20F3                                  0x000020f3
-
-#define REG_A4XX_UNKNOWN_20F4                                  0x000020f4
-
-#define REG_A4XX_UNKNOWN_20F5                                  0x000020f5
-
-#define REG_A4XX_UNKNOWN_20F6                                  0x000020f6
-
 #define REG_A4XX_UNKNOWN_20F7                                  0x000020f7
+#define A4XX_UNKNOWN_20F7__MASK                                        0xffffffff
+#define A4XX_UNKNOWN_20F7__SHIFT                               0
+static inline uint32_t A4XX_UNKNOWN_20F7(float val)
+{
+       return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK;
+}
 
 #define REG_A4XX_UNKNOWN_2152                                  0x00002152
 
@@ -2000,6 +2129,7 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 #define REG_A4XX_UNKNOWN_23A0                                  0x000023a0
 
 #define REG_A4XX_TEX_SAMP_0                                    0x00000000
+#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                  0x00000001
 #define A4XX_TEX_SAMP_0_XY_MAG__MASK                           0x00000006
 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT                          1
 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
@@ -2038,17 +2168,19 @@ static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val
 {
        return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
 }
+#define A4XX_TEX_SAMP_1_UNNORM_COORDS                          0x00000020
+#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR                   0x00000040
 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK                          0x000fff00
 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT                         8
 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
 {
-       return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
+       return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
 }
 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK                          0xfff00000
 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT                         20
 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
 {
-       return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
+       return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
 }
 
 #define REG_A4XX_TEX_CONST_0                                   0x00000000
@@ -2077,6 +2209,12 @@ static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
 {
        return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
 }
+#define A4XX_TEX_CONST_0_MIPLVLS__MASK                         0x000f0000
+#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT                                16
+static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
+{
+       return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
+}
 #define A4XX_TEX_CONST_0_FMT__MASK                             0x1fc00000
 #define A4XX_TEX_CONST_0_FMT__SHIFT                            22
 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
@@ -2105,6 +2243,12 @@ static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
 }
 
 #define REG_A4XX_TEX_CONST_2                                   0x00000002
+#define A4XX_TEX_CONST_2_FETCHSIZE__MASK                       0x0000000f
+#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT                      0
+static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
+{
+       return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
+}
 #define A4XX_TEX_CONST_2_PITCH__MASK                           0x3ffffe00
 #define A4XX_TEX_CONST_2_PITCH__SHIFT                          9
 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
@@ -2119,19 +2263,31 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
 }
 
 #define REG_A4XX_TEX_CONST_3                                   0x00000003
-#define A4XX_TEX_CONST_3_LAYERSZ__MASK                         0x0000000f
+#define A4XX_TEX_CONST_3_LAYERSZ__MASK                         0x00003fff
 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT                                0
 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
 {
        return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
 }
+#define A4XX_TEX_CONST_3_DEPTH__MASK                           0x7ffc0000
+#define A4XX_TEX_CONST_3_DEPTH__SHIFT                          18
+static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
+{
+       return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
+}
 
 #define REG_A4XX_TEX_CONST_4                                   0x00000004
-#define A4XX_TEX_CONST_4_BASE__MASK                            0xffffffff
-#define A4XX_TEX_CONST_4_BASE__SHIFT                           0
+#define A4XX_TEX_CONST_4_LAYERSZ__MASK                         0x0000000f
+#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT                                0
+static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
+{
+       return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
+}
+#define A4XX_TEX_CONST_4_BASE__MASK                            0xffffffe0
+#define A4XX_TEX_CONST_4_BASE__SHIFT                           5
 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
 {
-       return ((val) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
+       return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
 }
 
 #define REG_A4XX_TEX_CONST_5                                   0x00000005
index a4b33af9338daedd4ebd7345987326c416188be4..8531beb982e778d3d4b0051050281920856d19b1 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index 6a75cee94d811fdb12285e131e3187e113624096..6ffc4f6c8af13d6b3fc4b049b8a715a6dbb0aec6 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -172,7 +172,9 @@ enum adreno_pm4_type3_packets {
        CP_DRAW_INDIRECT = 40,
        CP_DRAW_INDX_INDIRECT = 41,
        CP_DRAW_AUTO = 36,
+       CP_UNKNOWN_19 = 25,
        CP_UNKNOWN_1A = 26,
+       CP_UNKNOWN_4E = 78,
        CP_WIDE_REG_WRITE = 116,
        IN_IB_PREFETCH_END = 23,
        IN_SUBBLK_PREFETCH = 31,
@@ -203,6 +205,12 @@ enum adreno_state_src {
        SS_INDIRECT = 4,
 };
 
+enum a4xx_index_size {
+       INDEX4_SIZE_8_BIT = 0,
+       INDEX4_SIZE_16_BIT = 1,
+       INDEX4_SIZE_32_BIT = 2,
+};
+
 #define REG_CP_LOAD_STATE_0                                    0x00000000
 #define CP_LOAD_STATE_0_DST_OFF__MASK                          0x0000ffff
 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                         0
@@ -374,29 +382,20 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 }
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK                   0x00000700
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT                  8
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
-       return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                 0x00000800
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                        11
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                 0x00000c00
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                        10
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 }
-#define CP_DRAW_INDX_OFFSET_0_NOT_EOP                          0x00001000
-#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX                      0x00002000
-#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE                0x00004000
-#define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__MASK              0xffff0000
-#define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__SHIFT             16
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES(uint32_t val)
-{
-       return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__MASK;
-}
 
 #define REG_CP_DRAW_INDX_OFFSET_1                              0x00000001
+#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK              0xffffffff
+#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT             0
+static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
+{
+       return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
+}
 
 #define REG_CP_DRAW_INDX_OFFSET_2                              0x00000002
 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                        0xffffffff
index 448438b759b4eeb41af628913c09ecca4f1e0f2a..abf1bba520bf25d24ba27b078cc55a44890f0037 100644 (file)
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index c102a7f074acdd5936cc99b9c46fbddffffbaa5a..695f99d4bec27a34557490c68923982a15236510 100644 (file)
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index a900134bdf3300b38ac911805b825f3e683b5923..50ff9851d73d138b119cfcf938485712465ecee7 100644 (file)
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h
new file mode 100644 (file)
index 0000000..a29f1df
--- /dev/null
@@ -0,0 +1,292 @@
+#ifndef EDP_XML
+#define EDP_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+
+Copyright (C) 2013-2014 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum edp_color_depth {
+       EDP_6BIT = 0,
+       EDP_8BIT = 1,
+       EDP_10BIT = 2,
+       EDP_12BIT = 3,
+       EDP_16BIT = 4,
+};
+
+enum edp_component_format {
+       EDP_RGB = 0,
+       EDP_YUV422 = 1,
+       EDP_YUV444 = 2,
+};
+
+#define REG_EDP_MAINLINK_CTRL                                  0x00000004
+#define EDP_MAINLINK_CTRL_ENABLE                               0x00000001
+#define EDP_MAINLINK_CTRL_RESET                                        0x00000002
+
+#define REG_EDP_STATE_CTRL                                     0x00000008
+#define EDP_STATE_CTRL_TRAIN_PATTERN_1                         0x00000001
+#define EDP_STATE_CTRL_TRAIN_PATTERN_2                         0x00000002
+#define EDP_STATE_CTRL_TRAIN_PATTERN_3                         0x00000004
+#define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS                    0x00000008
+#define EDP_STATE_CTRL_PRBS7                                   0x00000010
+#define EDP_STATE_CTRL_CUSTOM_80_BIT_PATTERN                   0x00000020
+#define EDP_STATE_CTRL_SEND_VIDEO                              0x00000040
+#define EDP_STATE_CTRL_PUSH_IDLE                               0x00000080
+
+#define REG_EDP_CONFIGURATION_CTRL                             0x0000000c
+#define EDP_CONFIGURATION_CTRL_SYNC_CLK                                0x00000001
+#define EDP_CONFIGURATION_CTRL_STATIC_MVID                     0x00000002
+#define EDP_CONFIGURATION_CTRL_PROGRESSIVE                     0x00000004
+#define EDP_CONFIGURATION_CTRL_LANES__MASK                     0x00000030
+#define EDP_CONFIGURATION_CTRL_LANES__SHIFT                    4
+static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val)
+{
+       return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK;
+}
+#define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING                        0x00000040
+#define EDP_CONFIGURATION_CTRL_COLOR__MASK                     0x00000100
+#define EDP_CONFIGURATION_CTRL_COLOR__SHIFT                    8
+static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val)
+{
+       return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK;
+}
+
+#define REG_EDP_SOFTWARE_MVID                                  0x00000014
+
+#define REG_EDP_SOFTWARE_NVID                                  0x00000018
+
+#define REG_EDP_TOTAL_HOR_VER                                  0x0000001c
+#define EDP_TOTAL_HOR_VER_HORIZ__MASK                          0x0000ffff
+#define EDP_TOTAL_HOR_VER_HORIZ__SHIFT                         0
+static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val)
+{
+       return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK;
+}
+#define EDP_TOTAL_HOR_VER_VERT__MASK                           0xffff0000
+#define EDP_TOTAL_HOR_VER_VERT__SHIFT                          16
+static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val)
+{
+       return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK;
+}
+
+#define REG_EDP_START_HOR_VER_FROM_SYNC                                0x00000020
+#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK                        0x0000ffff
+#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT               0
+static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val)
+{
+       return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK;
+}
+#define EDP_START_HOR_VER_FROM_SYNC_VERT__MASK                 0xffff0000
+#define EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT                        16
+static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val)
+{
+       return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK;
+}
+
+#define REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY                     0x00000024
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK             0x00007fff
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT            0
+static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val)
+{
+       return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK;
+}
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC                  0x00008000
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK              0x7fff0000
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT             16
+static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val)
+{
+       return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK;
+}
+#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC                  0x80000000
+
+#define REG_EDP_ACTIVE_HOR_VER                                 0x00000028
+#define EDP_ACTIVE_HOR_VER_HORIZ__MASK                         0x0000ffff
+#define EDP_ACTIVE_HOR_VER_HORIZ__SHIFT                                0
+static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val)
+{
+       return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK;
+}
+#define EDP_ACTIVE_HOR_VER_VERT__MASK                          0xffff0000
+#define EDP_ACTIVE_HOR_VER_VERT__SHIFT                         16
+static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val)
+{
+       return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK;
+}
+
+#define REG_EDP_MISC1_MISC0                                    0x0000002c
+#define EDP_MISC1_MISC0_MISC0__MASK                            0x000000ff
+#define EDP_MISC1_MISC0_MISC0__SHIFT                           0
+static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val)
+{
+       return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK;
+}
+#define EDP_MISC1_MISC0_SYNC                                   0x00000001
+#define EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK                 0x00000006
+#define EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT                        1
+static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val)
+{
+       return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK;
+}
+#define EDP_MISC1_MISC0_CEA                                    0x00000008
+#define EDP_MISC1_MISC0_BT709_5                                        0x00000010
+#define EDP_MISC1_MISC0_COLOR__MASK                            0x000000e0
+#define EDP_MISC1_MISC0_COLOR__SHIFT                           5
+static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val)
+{
+       return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK;
+}
+#define EDP_MISC1_MISC0_MISC1__MASK                            0x0000ff00
+#define EDP_MISC1_MISC0_MISC1__SHIFT                           8
+static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val)
+{
+       return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK;
+}
+#define EDP_MISC1_MISC0_INTERLACED_ODD                         0x00000100
+#define EDP_MISC1_MISC0_STEREO__MASK                           0x00000600
+#define EDP_MISC1_MISC0_STEREO__SHIFT                          9
+static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val)
+{
+       return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK;
+}
+
+#define REG_EDP_PHY_CTRL                                       0x00000074
+#define EDP_PHY_CTRL_SW_RESET_PLL                              0x00000001
+#define EDP_PHY_CTRL_SW_RESET                                  0x00000004
+
+#define REG_EDP_MAINLINK_READY                                 0x00000084
+#define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY               0x00000008
+#define EDP_MAINLINK_READY_TRAIN_PATTERN_2_READY               0x00000010
+#define EDP_MAINLINK_READY_TRAIN_PATTERN_3_READY               0x00000020
+
+#define REG_EDP_AUX_CTRL                                       0x00000300
+#define EDP_AUX_CTRL_ENABLE                                    0x00000001
+#define EDP_AUX_CTRL_RESET                                     0x00000002
+
+#define REG_EDP_INTERRUPT_REG_1                                        0x00000308
+#define EDP_INTERRUPT_REG_1_HPD                                        0x00000001
+#define EDP_INTERRUPT_REG_1_HPD_ACK                            0x00000002
+#define EDP_INTERRUPT_REG_1_HPD_EN                             0x00000004
+#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE                       0x00000008
+#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_ACK                   0x00000010
+#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_EN                    0x00000020
+#define EDP_INTERRUPT_REG_1_WRONG_ADDR                         0x00000040
+#define EDP_INTERRUPT_REG_1_WRONG_ADDR_ACK                     0x00000080
+#define EDP_INTERRUPT_REG_1_WRONG_ADDR_EN                      0x00000100
+#define EDP_INTERRUPT_REG_1_TIMEOUT                            0x00000200
+#define EDP_INTERRUPT_REG_1_TIMEOUT_ACK                                0x00000400
+#define EDP_INTERRUPT_REG_1_TIMEOUT_EN                         0x00000800
+#define EDP_INTERRUPT_REG_1_NACK_DEFER                         0x00001000
+#define EDP_INTERRUPT_REG_1_NACK_DEFER_ACK                     0x00002000
+#define EDP_INTERRUPT_REG_1_NACK_DEFER_EN                      0x00004000
+#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT                     0x00008000
+#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_ACK                 0x00010000
+#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_EN                  0x00020000
+#define EDP_INTERRUPT_REG_1_I2C_NACK                           0x00040000
+#define EDP_INTERRUPT_REG_1_I2C_NACK_ACK                       0x00080000
+#define EDP_INTERRUPT_REG_1_I2C_NACK_EN                                0x00100000
+#define EDP_INTERRUPT_REG_1_I2C_DEFER                          0x00200000
+#define EDP_INTERRUPT_REG_1_I2C_DEFER_ACK                      0x00400000
+#define EDP_INTERRUPT_REG_1_I2C_DEFER_EN                       0x00800000
+#define EDP_INTERRUPT_REG_1_PLL_UNLOCK                         0x01000000
+#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_ACK                     0x02000000
+#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_EN                      0x04000000
+#define EDP_INTERRUPT_REG_1_AUX_ERROR                          0x08000000
+#define EDP_INTERRUPT_REG_1_AUX_ERROR_ACK                      0x10000000
+#define EDP_INTERRUPT_REG_1_AUX_ERROR_EN                       0x20000000
+
+#define REG_EDP_INTERRUPT_REG_2                                        0x0000030c
+#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO                    0x00000001
+#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_ACK                        0x00000002
+#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_EN                 0x00000004
+#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT                 0x00000008
+#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_ACK             0x00000010
+#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_EN              0x00000020
+#define EDP_INTERRUPT_REG_2_FRAME_END                          0x00000200
+#define EDP_INTERRUPT_REG_2_FRAME_END_ACK                      0x00000080
+#define EDP_INTERRUPT_REG_2_FRAME_END_EN                       0x00000100
+#define EDP_INTERRUPT_REG_2_CRC_UPDATED                                0x00000200
+#define EDP_INTERRUPT_REG_2_CRC_UPDATED_ACK                    0x00000400
+#define EDP_INTERRUPT_REG_2_CRC_UPDATED_EN                     0x00000800
+
+#define REG_EDP_INTERRUPT_TRANS_NUM                            0x00000310
+
+#define REG_EDP_AUX_DATA                                       0x00000314
+#define EDP_AUX_DATA_READ                                      0x00000001
+#define EDP_AUX_DATA_DATA__MASK                                        0x0000ff00
+#define EDP_AUX_DATA_DATA__SHIFT                               8
+static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val)
+{
+       return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK;
+}
+#define EDP_AUX_DATA_INDEX__MASK                               0x00ff0000
+#define EDP_AUX_DATA_INDEX__SHIFT                              16
+static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val)
+{
+       return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK;
+}
+#define EDP_AUX_DATA_INDEX_WRITE                               0x80000000
+
+#define REG_EDP_AUX_TRANS_CTRL                                 0x00000318
+#define EDP_AUX_TRANS_CTRL_I2C                                 0x00000100
+#define EDP_AUX_TRANS_CTRL_GO                                  0x00000200
+
+#define REG_EDP_AUX_STATUS                                     0x00000324
+
+static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; }
+
+static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; }
+
+#define REG_EDP_PHY_GLB_VM_CFG0                                        0x00000510
+
+#define REG_EDP_PHY_GLB_VM_CFG1                                        0x00000514
+
+#define REG_EDP_PHY_GLB_MISC9                                  0x00000518
+
+#define REG_EDP_PHY_GLB_CFG                                    0x00000528
+
+#define REG_EDP_PHY_GLB_PD_CTL                                 0x0000052c
+
+#define REG_EDP_PHY_GLB_PHY_STATUS                             0x00000598
+
+
+#endif /* EDP_XML */
index 5b0844befbab6b42b268dad38f8d864138adec01..350988740e9fd2f21701e243489f002e8e7d1743 100644 (file)
@@ -8,18 +8,19 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -45,12 +46,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 enum hdmi_hdcp_key_state {
-       NO_KEYS = 0,
-       NOT_CHECKED = 1,
-       CHECKING = 2,
-       KEYS_VALID = 3,
-       AKSV_INVALID = 4,
-       CHECKSUM_MISMATCH = 5,
+       HDCP_KEYS_STATE_NO_KEYS = 0,
+       HDCP_KEYS_STATE_NOT_CHECKED = 1,
+       HDCP_KEYS_STATE_CHECKING = 2,
+       HDCP_KEYS_STATE_VALID = 3,
+       HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
+       HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
+       HDCP_KEYS_STATE_PROD_AKSV = 6,
+       HDCP_KEYS_STATE_RESERVED = 7,
 };
 
 enum hdmi_ddc_read_write {
@@ -199,11 +202,29 @@ static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
 #define HDMI_HDCP_CTRL_ENABLE                                  0x00000001
 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE                       0x00000100
 
+#define REG_HDMI_HDCP_DEBUG_CTRL                               0x00000114
+#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER                                0x00000004
+
 #define REG_HDMI_HDCP_INT_CTRL                                 0x00000118
+#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT                    0x00000001
+#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK                    0x00000002
+#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK                   0x00000004
+#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT                       0x00000010
+#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK                       0x00000020
+#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK                      0x00000040
+#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK                  0x00000080
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT                   0x00000100
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK                   0x00000200
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK                  0x00000400
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT                  0x00001000
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK                  0x00002000
+#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK                 0x00004000
 
 #define REG_HDMI_HDCP_LINK0_STATUS                             0x0000011c
 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY                      0x00000100
 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY                      0x00000200
+#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES                      0x00001000
+#define HDMI_HDCP_LINK0_STATUS_V_MATCHES                       0x00100000
 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK                 0x70000000
 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT                        28
 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
@@ -211,9 +232,56 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state
        return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
 }
 
+#define REG_HDMI_HDCP_DDC_CTRL_0                               0x00000120
+#define HDMI_HDCP_DDC_CTRL_0_DISABLE                           0x00000001
+
+#define REG_HDMI_HDCP_DDC_CTRL_1                               0x00000124
+#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK                                0x00000001
+
+#define REG_HDMI_HDCP_DDC_STATUS                               0x00000128
+#define HDMI_HDCP_DDC_STATUS_XFER_REQ                          0x00000010
+#define HDMI_HDCP_DDC_STATUS_XFER_DONE                         0x00000400
+#define HDMI_HDCP_DDC_STATUS_ABORTED                           0x00001000
+#define HDMI_HDCP_DDC_STATUS_TIMEOUT                           0x00002000
+#define HDMI_HDCP_DDC_STATUS_NACK0                             0x00004000
+#define HDMI_HDCP_DDC_STATUS_NACK1                             0x00008000
+#define HDMI_HDCP_DDC_STATUS_FAILED                            0x00010000
+
+#define REG_HDMI_HDCP_ENTROPY_CTRL0                            0x0000012c
+
+#define REG_HDMI_HDCP_ENTROPY_CTRL1                            0x0000025c
+
 #define REG_HDMI_HDCP_RESET                                    0x00000130
 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE                   0x00000001
 
+#define REG_HDMI_HDCP_RCVPORT_DATA0                            0x00000134
+
+#define REG_HDMI_HDCP_RCVPORT_DATA1                            0x00000138
+
+#define REG_HDMI_HDCP_RCVPORT_DATA2_0                          0x0000013c
+
+#define REG_HDMI_HDCP_RCVPORT_DATA2_1                          0x00000140
+
+#define REG_HDMI_HDCP_RCVPORT_DATA3                            0x00000144
+
+#define REG_HDMI_HDCP_RCVPORT_DATA4                            0x00000148
+
+#define REG_HDMI_HDCP_RCVPORT_DATA5                            0x0000014c
+
+#define REG_HDMI_HDCP_RCVPORT_DATA6                            0x00000150
+
+#define REG_HDMI_HDCP_RCVPORT_DATA7                            0x00000154
+
+#define REG_HDMI_HDCP_RCVPORT_DATA8                            0x00000158
+
+#define REG_HDMI_HDCP_RCVPORT_DATA9                            0x0000015c
+
+#define REG_HDMI_HDCP_RCVPORT_DATA10                           0x00000160
+
+#define REG_HDMI_HDCP_RCVPORT_DATA11                           0x00000164
+
+#define REG_HDMI_HDCP_RCVPORT_DATA12                           0x00000168
+
 #define REG_HDMI_VENSPEC_INFO0                                 0x0000016c
 
 #define REG_HDMI_VENSPEC_INFO1                                 0x00000170
@@ -266,6 +334,7 @@ static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
 #define HDMI_DDC_SW_STATUS_NACK3                               0x00008000
 
 #define REG_HDMI_DDC_HW_STATUS                                 0x0000021c
+#define HDMI_DDC_HW_STATUS_DONE                                        0x00000008
 
 #define REG_HDMI_DDC_SPEED                                     0x00000220
 #define HDMI_DDC_SPEED_THRESHOLD__MASK                         0x00000003
@@ -329,6 +398,15 @@ static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
 }
 #define HDMI_DDC_DATA_INDEX_WRITE                              0x80000000
 
+#define REG_HDMI_HDCP_SHA_CTRL                                 0x0000023c
+
+#define REG_HDMI_HDCP_SHA_STATUS                               0x00000240
+#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE                                0x00000001
+#define HDMI_HDCP_SHA_STATUS_COMP_DONE                         0x00000010
+
+#define REG_HDMI_HDCP_SHA_DATA                                 0x00000244
+#define HDMI_HDCP_SHA_DATA_DONE                                        0x00000001
+
 #define REG_HDMI_HPD_INT_STATUS                                        0x00000250
 #define HDMI_HPD_INT_STATUS_INT                                        0x00000001
 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED                     0x00000002
@@ -359,6 +437,10 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
        return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
 }
 
+#define REG_HDMI_HDCP_SW_UPPER_AKSV                            0x00000284
+
+#define REG_HDMI_HDCP_SW_LOWER_AKSV                            0x00000288
+
 #define REG_HDMI_CEC_STATUS                                    0x00000298
 
 #define REG_HDMI_CEC_INT                                       0x0000029c
index 29bd796797de6e240d4749fd2b6d8623b1a592d9..43bb54a9afbf1c5503bec3896df4887fa402e6bf 100644 (file)
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index a4a7f8c7122acfcb93a9a68b52af9ab4847fa023..1d39174d91fba3455b03a5a0c4654ff7bc779750 100644 (file)
@@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -72,6 +73,18 @@ enum mdp4_cursor_format {
        CURSOR_XRGB = 2,
 };
 
+enum mdp4_frame_format {
+       FRAME_LINEAR = 0,
+       FRAME_TILE_ARGB_4X4 = 1,
+       FRAME_TILE_YCBCR_420 = 2,
+};
+
+enum mdp4_scale_unit {
+       SCALE_FIR = 0,
+       SCALE_MN_PHASE = 1,
+       SCALE_PIXEL_RPT = 2,
+};
+
 enum mdp4_dma {
        DMA_P = 0,
        DMA_S = 1,
@@ -637,6 +650,8 @@ static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00
 
 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
 
+static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
+
 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK                                0x0000ffff
 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT                       0
@@ -720,7 +735,25 @@ static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 }
 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT                      0x00020000
 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                  0x00040000
+#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK                        0x00180000
+#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT               19
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
+{
+       return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
+}
 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL                                0x00400000
+#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK                 0x0c000000
+#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT                        26
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
+{
+       return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK                        0x60000000
+#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT               29
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
+{
+       return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
+}
 
 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK                       0x000000ff
@@ -751,6 +784,18 @@ static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
 #define MDP4_PIPE_OP_MODE_SCALEX_EN                            0x00000001
 #define MDP4_PIPE_OP_MODE_SCALEY_EN                            0x00000002
+#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK                        0x0000000c
+#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT               2
+static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
+{
+       return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
+}
+#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK                        0x00000030
+#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT               4
+static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
+{
+       return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
+}
 #define MDP4_PIPE_OP_MODE_SRC_YCBCR                            0x00000200
 #define MDP4_PIPE_OP_MODE_DST_YCBCR                            0x00000400
 #define MDP4_PIPE_OP_MODE_CSC_EN                               0x00000800
index e87ef5512cb0ade999f44d7c2169069d7022cdc6..09b4a25eb553fa9cad7f68ad8a61afa13a8d90a0 100644 (file)
@@ -8,18 +8,19 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20136 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1940 bytes, from 2014-10-31 16:51:39)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  23963 bytes, from 2014-10-31 16:51:46)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-07-17 15:33:30)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -88,13 +89,6 @@ enum mdp5_pack_3d {
        PACK_3D_COL_INT = 3,
 };
 
-enum mdp5_chroma_samp_type {
-       CHROMA_RGB = 0,
-       CHROMA_H2V1 = 1,
-       CHROMA_H1V2 = 2,
-       CHROMA_420 = 3,
-};
-
 enum mdp5_scale_filter {
        SCALE_FILTER_NEAREST = 0,
        SCALE_FILTER_BIL = 1,
@@ -135,6 +129,17 @@ enum mdp5_client_id {
        CID_MAX = 23,
 };
 
+enum mdp5_cursor_format {
+       CURSOR_FMT_ARGB8888 = 0,
+       CURSOR_FMT_ARGB1555 = 2,
+       CURSOR_FMT_ARGB4444 = 4,
+};
+
+enum mdp5_cursor_alpha {
+       CURSOR_ALPHA_CONST = 0,
+       CURSOR_ALPHA_PER_PIXEL = 2,
+};
+
 enum mdp5_igc_type {
        IGC_VIG = 0,
        IGC_RGB = 1,
@@ -142,6 +147,11 @@ enum mdp5_igc_type {
        IGC_DSPP = 3,
 };
 
+enum mdp5_data_format {
+       DATA_FORMAT_RGB = 0,
+       DATA_FORMAT_YUV = 1,
+};
+
 #define MDP5_IRQ_INTF0_WB_ROT_COMP                             0x00000001
 #define MDP5_IRQ_INTF1_WB_ROT_COMP                             0x00000002
 #define MDP5_IRQ_INTF2_WB_ROT_COMP                             0x00000004
@@ -463,12 +473,143 @@ static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
 }
 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
 
+static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
+#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK            0x00080000
+#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT           19
+static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
+{
+       return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
+}
+#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK            0x00040000
+#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT           18
+static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
+{
+       return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
+}
+#define MDP5_PIPE_OP_MODE_CSC_1_EN                             0x00020000
+
 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
 
 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
 
 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
 
+static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK          0x00001fff
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT         0
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
+}
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK          0x1fff0000
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT         16
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK          0x00001fff
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT         0
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
+}
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK          0x1fff0000
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT         16
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK          0x00001fff
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT         0
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
+}
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK          0x1fff0000
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT         16
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK          0x00001fff
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT         0
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
+}
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK          0x1fff0000
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT         16
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK          0x00001fff
+#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT         0
+static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
+#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK               0x000000ff
+#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT              0
+static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
+}
+#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK                        0x0000ff00
+#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT               8
+static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
+#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK              0x000000ff
+#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT             0
+static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
+}
+#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK               0x0000ff00
+#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT              8
+static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
+#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK               0x000001ff
+#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT              0
+static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
+#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK              0x000001ff
+#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT             0
+static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
+{
+       return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
+}
+
 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK                                0xffff0000
 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT                       16
@@ -618,15 +759,15 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 }
 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT                      0x00020000
 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                  0x00040000
-#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK                  0x00780000
+#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK                  0x00180000
 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT                 19
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val)
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
 {
        return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
 }
 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK                 0x01800000
 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT                        23
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val)
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
 {
        return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
 }
@@ -753,6 +894,10 @@ static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { ret
 
 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
 
+static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
+
 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
 
 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
@@ -839,20 +984,88 @@ static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i
 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
 
 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK                    0x0000ffff
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT                   0
+static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
+}
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK                    0xffff0000
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT                   16
+static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK                                0x0000ffff
+#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT                       0
+static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
+}
+#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK                                0xffff0000
+#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT                       16
+static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_XY_SRC_X__MASK                          0x0000ffff
+#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT                         0
+static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
+}
+#define MDP5_LM_CURSOR_XY_SRC_Y__MASK                          0xffff0000
+#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT                         16
+static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK                     0x0000ffff
+#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT                    0
+static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK                     0x00000007
+#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT                    0
+static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
+{
+       return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
 
 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_START_XY_X_START__MASK                  0x0000ffff
+#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT                 0
+static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
+}
+#define MDP5_LM_CURSOR_START_XY_Y_START__MASK                  0xffff0000
+#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT                 16
+static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
+{
+       return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
+}
 
 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN                   0x00000001
+#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK      0x00000006
+#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT     1
+static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
+{
+       return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
+}
+#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN            0x00000008
 
 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
 
index 64c1afd6030a78220da059287df22c1bd44b3433..a1d35f162c7f85d0ad827e9fe967a871e9accb44 100644 (file)
@@ -8,18 +8,19 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2014-06-25 12:55:02)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  23613 bytes, from 2014-06-25 12:53:44)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
 
-Copyright (C) 2013 by the following authors:
+Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -44,6 +45,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
 
+enum mdp_chroma_samp_type {
+       CHROMA_RGB = 0,
+       CHROMA_H2V1 = 1,
+       CHROMA_H1V2 = 2,
+       CHROMA_420 = 3,
+};
+
+enum mdp_sspp_fetch_type {
+       MDP_PLANE_INTERLEAVED = 0,
+       MDP_PLANE_PLANAR = 1,
+       MDP_PLANE_PSEUDO_PLANAR = 2,
+};
+
 enum mdp_mixer_stage_id {
        STAGE_UNUSED = 0,
        STAGE_BASE = 1,