drm/amdgpu: refine set clock gating for tonga/polaris

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 9bf6b6218f32b9b7348da6dd979af30a965a2515..d0ec00986f3826c32957ab432c677c53c24091c2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5785,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
                                          enum amd_clockgating_state state)
 {
-       uint32_t msg_id, pp_state;
+       uint32_t msg_id, pp_state = 0;
+       uint32_t pp_support_state = 0;
        void *pp_handle = adev->powerplay.pp_handle;
 
-       if (state == AMD_CG_STATE_UNGATE)
-               pp_state = 0;
-       else
-               pp_state = PP_STATE_CG | PP_STATE_LS;
+       if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+                       pp_support_state = PP_STATE_SUPPORT_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
+                       pp_support_state |= PP_STATE_SUPPORT_CG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_CG,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_CG,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+       if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+                       pp_support_state = PP_STATE_SUPPORT_LS;
+                       pp_state = PP_STATE_LS;
+               }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_MG,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                       pp_support_state |= PP_STATE_SUPPORT_CG;
+                       pp_state |= PP_STATE_CG;
+               }
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_MG,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
        return 0;
 }
@@ -5811,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
                                          enum amd_clockgating_state state)
 {
-       uint32_t msg_id, pp_state;
+
+       uint32_t msg_id, pp_state = 0;
+       uint32_t pp_support_state = 0;
        void *pp_handle = adev->powerplay.pp_handle;
 
-       if (state == AMD_CG_STATE_UNGATE)
-               pp_state = 0;
-       else
-               pp_state = PP_STATE_CG | PP_STATE_LS;
+       if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+                       pp_support_state = PP_STATE_SUPPORT_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
+                       pp_support_state |= PP_STATE_SUPPORT_CG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_CG,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_CG,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+       if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
+                       pp_support_state = PP_STATE_SUPPORT_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
+                       pp_support_state |= PP_STATE_SUPPORT_CG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_3D,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_3D,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+       if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+                       pp_support_state = PP_STATE_SUPPORT_LS;
+                       pp_state = PP_STATE_LS;
+               }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_MG,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+                       pp_support_state |= PP_STATE_SUPPORT_CG;
+                       pp_state |= PP_STATE_CG;
+               }
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-                       PP_BLOCK_GFX_RLC,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                       pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
 
-       msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_MG,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
+               pp_support_state = PP_STATE_SUPPORT_LS;
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+                               PP_BLOCK_GFX_RLC,
+                               pp_support_state,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
+               pp_support_state = PP_STATE_SUPPORT_LS;
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
                        PP_BLOCK_GFX_CP,
-                       PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+                       pp_support_state,
                        pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 33a2badf586aff89d7d04ad4715a2b956c28ef7b..bf088d6d9bf1f96430d7afda1ec3fbeae6e82768 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1203,57 +1203,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 static int vi_common_set_clockgating_state_by_smu(void *handle,
                                           enum amd_clockgating_state state)
 {
-       uint32_t msg_id, pp_state;
+       uint32_t msg_id, pp_state = 0;
+       uint32_t pp_support_state = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        void *pp_handle = adev->powerplay.pp_handle;
 
-       if (state == AMD_CG_STATE_UNGATE)
-               pp_state = 0;
-       else
-               pp_state = PP_STATE_CG | PP_STATE_LS;
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_MC,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_SDMA,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_HDP,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_BIF,
-                      PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_BIF,
-                      PP_STATE_SUPPORT_CG,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_DRM,
-                      PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_ROM,
-                      PP_STATE_SUPPORT_CG,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+       if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_MC_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_MC,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_SDMA,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_HDP_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_HDP,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
 
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_BIF,
+                              PP_STATE_SUPPORT_LS,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+       if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_CG;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_BIF,
+                              PP_STATE_SUPPORT_CG,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_DRM,
+                              PP_STATE_SUPPORT_LS,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_CG;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_ROM,
+                              PP_STATE_SUPPORT_CG,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
        return 0;
 }