NULL,
};
+static int power9_generic_events_dd1[] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL,
+ [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
+ [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
+};
+
static int power9_generic_events[] = {
[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
.get_alternatives = power9_get_alternatives,
.disable_pmc = isa207_disable_pmc,
.flags = PPMU_NO_SIAR | PPMU_ARCH_207S,
- .n_generic = ARRAY_SIZE(power9_generic_events),
- .generic_events = power9_generic_events,
+ .n_generic = ARRAY_SIZE(power9_generic_events_dd1),
+ .generic_events = power9_generic_events_dd1,
.cache_events = &power9_cache_events,
.attr_groups = power9_isa207_pmu_attr_groups,
.bhrb_nr = 32,
return -ENODEV;
if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+ /*
+ * Since PM_INST_CMPL may not provide right counts in all
+ * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
+ */
+ EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
rc = register_power_pmu(&power9_isa207_pmu);
} else {
rc = register_power_pmu(&power9_pmu);