[SCSI] ipr: Increase max concurrent oustanding commands
authorBrian King <brking@linux.vnet.ibm.com>
Thu, 15 Mar 2012 02:20:10 +0000 (21:20 -0500)
committerJames Bottomley <JBottomley@Parallels.com>
Wed, 28 Mar 2012 14:04:47 +0000 (15:04 +0100)
Increase the total number of max concurrent outstanding commands
for the most recent family of adapters in order to improve overall
adapter performance.

Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
drivers/scsi/ipr.c
drivers/scsi/ipr.h

index 590997961a933f880dba9037a01af486d573fff4..ada0af745a086bd0dba0f3476a1f1ddbf91e554f 100644 (file)
@@ -104,6 +104,7 @@ static DEFINE_SPINLOCK(ipr_driver_lock);
 static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
        { /* Gemstone, Citrine, Obsidian, and Obsidian-E */
                .mailbox = 0x0042C,
+               .max_cmds = 100,
                .cache_line_size = 0x20,
                .clear_isr = 1,
                {
@@ -127,6 +128,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
        },
        { /* Snipe and Scamp */
                .mailbox = 0x0052C,
+               .max_cmds = 100,
                .cache_line_size = 0x20,
                .clear_isr = 1,
                {
@@ -150,6 +152,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
        },
        { /* CRoC */
                .mailbox = 0x00044,
+               .max_cmds = 1000,
                .cache_line_size = 0x20,
                .clear_isr = 0,
                {
@@ -8278,6 +8281,10 @@ static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
        if (ioa_cfg->ipr_cmd_pool)
                pci_pool_destroy (ioa_cfg->ipr_cmd_pool);
 
+       kfree(ioa_cfg->ipr_cmnd_list);
+       kfree(ioa_cfg->ipr_cmnd_list_dma);
+       ioa_cfg->ipr_cmnd_list = NULL;
+       ioa_cfg->ipr_cmnd_list_dma = NULL;
        ioa_cfg->ipr_cmd_pool = NULL;
 }
 
@@ -8358,6 +8365,14 @@ static int __devinit ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
        if (!ioa_cfg->ipr_cmd_pool)
                return -ENOMEM;
 
+       ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
+       ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
+
+       if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
+               ipr_free_cmd_blks(ioa_cfg);
+               return -ENOMEM;
+       }
+
        for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
                ipr_cmd = pci_pool_alloc (ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
 
@@ -8585,6 +8600,7 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
        host->max_channel = IPR_MAX_BUS_TO_SCAN;
        host->unique_id = host->host_no;
        host->max_cmd_len = IPR_MAX_CDB_LEN;
+       host->can_queue = ioa_cfg->max_cmds;
        pci_set_drvdata(pdev, ioa_cfg);
 
        p = &ioa_cfg->chip_cfg->regs;
@@ -8770,6 +8786,7 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev,
        ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
        ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
        ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
+       ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
 
        if (ipr_transop_timeout)
                ioa_cfg->transop_timeout = ipr_transop_timeout;
index 40cbee72b83ce4286547395f62c9e6a2e622b901..a79de2aab469e881271dc8cd6734e66f747e3cab 100644 (file)
@@ -53,7 +53,7 @@
  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  *     ops the mid-layer can send to the adapter.
  */
-#define IPR_NUM_BASE_CMD_BLKS                          100
+#define IPR_NUM_BASE_CMD_BLKS                  (ioa_cfg->max_cmds)
 
 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E   0x0339
 
 #define IPR_NUM_INTERNAL_CMD_BLKS      (IPR_NUM_HCAMS + \
                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 
-#define IPR_MAX_COMMANDS               IPR_NUM_BASE_CMD_BLKS
+#define IPR_MAX_COMMANDS               100
 #define IPR_NUM_CMD_BLKS               (IPR_NUM_BASE_CMD_BLKS + \
                                                IPR_NUM_INTERNAL_CMD_BLKS)
 
@@ -1305,6 +1305,7 @@ struct ipr_interrupts {
 
 struct ipr_chip_cfg_t {
        u32 mailbox;
+       u16 max_cmds;
        u8 cache_line_size;
        u8 clear_isr;
        struct ipr_interrupt_offsets regs;
@@ -1503,8 +1504,9 @@ struct ipr_ioa_cfg {
        struct ata_host ata_host;
        char ipr_cmd_label[8];
 #define IPR_CMD_LABEL          "ipr_cmd"
-       struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
-       dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
+       u32 max_cmds;
+       struct ipr_cmnd **ipr_cmnd_list;
+       dma_addr_t *ipr_cmnd_list_dma;
 }; /* struct ipr_ioa_cfg */
 
 struct ipr_cmnd {