[MIPS] cevt-txx9: Reset timer counter on initialization

The txx9_tmr_init() will not clear a timer counter register in a certain
case.  The counter register is cleared on 1->0 transition of TCE bit if
CRE=1.  So just clearing the TCE bit is not enough.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8fb0d740b6de17b17de1d12b61c7036d80c..b5fc4eb412d2e53b3544f0d67f032cecf4933095 100644 (file)
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
        struct txx9_tmr_reg __iomem *tmrptr;
 
        tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
+       /* Start once to make CounterResetEnable effective */
+       __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
+       /* Stop and reset the counter */
        __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
        __raw_writel(0, &tmrptr->tisr);
        __raw_writel(0xffffffff, &tmrptr->cpra);