ASoC/ARM: Davinci: McASP: split asp header into platform and audio specific
authorHebbar, Gururaja <gururaja.hebbar@ti.com>
Mon, 27 Aug 2012 13:26:41 +0000 (18:56 +0530)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Mon, 27 Aug 2012 18:12:09 +0000 (11:12 -0700)
Davinci McASP header & driver are shared by few OMAP platforms (like
TI81xx, AM335x). Splitting asp header into Davinci platform specific
header and Audio specific header helps to share them across platforms.

Audio specific defines is moved to to common
<linux/platform_data/davinci_asp.h> so that the header can be
accessed by all related platforms.

While here, correct the header usage (remove multiple header
re-definitions and unused headers) and remove platform names from
structures comments and enum. Also some some coding style errors.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
15 files changed:
arch/arm/mach-davinci/asp.h [new file with mode: 0644]
arch/arm/mach-davinci/davinci.h
arch/arm/mach-davinci/devices-da8xx.c
arch/arm/mach-davinci/dm355.c
arch/arm/mach-davinci/dm365.c
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c
arch/arm/mach-davinci/include/mach/asp.h [deleted file]
arch/arm/mach-davinci/include/mach/da8xx.h
include/linux/platform_data/davinci_asp.h [new file with mode: 0644]
sound/soc/davinci/davinci-evm.c
sound/soc/davinci/davinci-i2s.c
sound/soc/davinci/davinci-mcasp.h
sound/soc/davinci/davinci-pcm.c
sound/soc/davinci/davinci-pcm.h

diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
new file mode 100644 (file)
index 0000000..d9b2acd
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * TI DaVinci Audio definitions
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE      0x01E02000
+#define DAVINCI_ASP1_BASE      0x01E04000
+
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE        0x01D02000
+
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE         0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE         0x01D01800
+
+/* Bases of da850/da830 McASP0  register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE  0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE  0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX    2
+#define DAVINCI_DMA_ASP0_RX    3
+#define DAVINCI_DMA_ASP1_TX    8
+#define DAVINCI_DMA_ASP1_RX    9
+
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0       6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0       9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1       12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
+
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT    IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT    IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT    IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT    IRQ_MBXINT
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
index 8db0fc6809ddd11c6874dbdf709044fad84ee06f..8661b2013527f12b33e6c9d081ccea3314ba47af 100644 (file)
 #include <linux/davinci_emac.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/hardware.h>
+#include <mach/edma.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
index 4735d64fd6f223cca02a10021c6ed702437bc397..bd2f72b414bce03c87b4921e2962ff709cf815e4 100644 (file)
@@ -24,6 +24,7 @@
 #include <mach/cpuidle.h>
 
 #include "clock.h"
+#include "asp.h"
 
 #define DA8XX_TPCC_BASE                        0x01c00000
 #define DA8XX_TPTC0_BASE               0x01c08000
index 678cd99b7336151b474580ccbb7eb1fe2ccfead5..e47a3f0e8ac48643a2c47867ae523855c04329ca 100644 (file)
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM355_UART2_BASE       (IO_PHYS + 0x206000)
 
index a50d49de1883394e5cc29ba317becb0ee5e6ceb7..f473745d6e3cbe5ca940ca6694eabe00f6e41207 100644 (file)
@@ -29,7 +29,6 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
@@ -37,6 +36,7 @@
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM365_REF_FREQ         24000000        /* 24 MHz on the DM365 EVM */
 
index c8b866657fcbf1a2d240c3711fce4bba1093c775..0755d466221a6aad1b3c93056f5e39e314cfc034 100644 (file)
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 /*
  * Device specific clocks
index 9eb87c1d1edd1e1deacefc64d240469987e2f0d6..97c0f8e555bd454edb83c4612bf31153816fa9e0 100644 (file)
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
 
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
deleted file mode 100644 (file)
index 9aa2409..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * <mach/asp.h> - DaVinci Audio Serial Port support
- */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
-
-#include <mach/irqs.h>
-#include <mach/edma.h>
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE      0x01E02000
-#define DAVINCI_ASP1_BASE      0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE        0x01D02000
-
-/* Bases of dm646x register banks */
-#define        DAVINCI_DM646X_MCASP0_REG_BASE          0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE         0x01D01800
-
-/* Bases of da850/da830 McASP0  register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE  0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE  0x01D04000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX    2
-#define DAVINCI_DMA_ASP0_RX    3
-#define DAVINCI_DMA_ASP1_TX    8
-#define DAVINCI_DMA_ASP1_RX    9
-
-/* EDMA channels of dm646x */
-#define        DAVINCI_DM646X_DMA_MCASP0_AXEVT0        6
-#define        DAVINCI_DM646X_DMA_MCASP0_AREVT0        9
-#define        DAVINCI_DM646X_DMA_MCASP1_AXEVT1        12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define        DAVINCI_DA8XX_DMA_MCASP0_AREVT  0
-#define        DAVINCI_DA8XX_DMA_MCASP0_AXEVT  1
-
-/* EDMA channels of da830 McASP1 */
-#define        DAVINCI_DA830_DMA_MCASP1_AREVT  2
-#define        DAVINCI_DA830_DMA_MCASP1_AXEVT  3
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT    IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT    IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT    IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT    IRQ_MBXINT
-
-struct snd_platform_data {
-       u32 tx_dma_offset;
-       u32 rx_dma_offset;
-       enum dma_event_q asp_chan_q;    /* event queue number for ASP channel */
-       enum dma_event_q ram_chan_q;    /* event queue number for RAM channel */
-       unsigned int codec_fmt;
-       /*
-        * Allowing this is more efficient and eliminates left and right swaps
-        * caused by underruns, but will swap the left and right channels
-        * when compared to previous behavior.
-        */
-       unsigned enable_channel_combine:1;
-       unsigned sram_size_playback;
-       unsigned sram_size_capture;
-
-       /*
-        * If McBSP peripheral gets the clock from an external pin,
-        * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
-        * and MCBSP_CLKS.
-        * Depending on different hardware connections it is possible
-        * to use this setting to change the behaviour of McBSP
-        * driver. The dm365_clk_input_pin enum is available for dm365
-        */
-       int clk_input_pin;
-
-       /*
-        * This flag works when both clock and FS are outputs for the cpu
-        * and makes clock more accurate (FS is not symmetrical and the
-        * clock is very fast.
-        * The clock becoming faster is named
-        * i2s continuous serial clock (I2S_SCK) and it is an externally
-        * visible bit clock.
-        *
-        * first line : WordSelect
-        * second line : ContinuousSerialClock
-        * third line: SerialData
-        *
-        * SYMMETRICAL APPROACH:
-        *   _______________________          LEFT
-        * _|         RIGHT         |______________________|
-        *     _   _         _   _   _   _         _   _
-        *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
-        *     _   _         _   _   _   _         _   _
-        *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
-        *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
-        *
-        * ACCURATE CLOCK APPROACH:
-        *   ______________          LEFT
-        * _|     RIGHT    |_______________________________|
-        *     _         _   _         _   _   _   _   _   _
-        *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
-        *     _         _   _          _      dummy cycles
-        *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
-        *    \_/       \_/ \_/        \_/
-        *
-        */
-       bool i2s_accurate_sck;
-
-       /* McASP specific fields */
-       int tdm_slots;
-       u8 op_mode;
-       u8 num_serializer;
-       u8 *serial_dir;
-       u8 version;
-       u8 txnumevt;
-       u8 rxnumevt;
-};
-
-enum {
-       MCASP_VERSION_1 = 0,    /* DM646x */
-       MCASP_VERSION_2,        /* DA8xx/OMAPL1x */
-};
-
-enum dm365_clk_input_pin {
-       MCBSP_CLKR = 0,         /* DM365 */
-       MCBSP_CLKS,
-};
-
-#define INACTIVE_MODE  0
-#define TX_MODE                1
-#define RX_MODE                2
-
-#define DAVINCI_MCASP_IIS_MODE 0
-#define DAVINCI_MCASP_DIT_MODE 1
-
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
index a2f1f274f1897f40bf4ae85f5f1bfc91063cf8e3..c74a6abef187f9c7e7bf7b61e0e4c81034fb58bb 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
-#include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 #include <mach/pm.h>
diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h
new file mode 100644 (file)
index 0000000..79c26aa
--- /dev/null
@@ -0,0 +1,104 @@
+/*
+ * TI DaVinci Audio Serial Port support
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DAVINCI_ASP_H
+#define __DAVINCI_ASP_H
+
+struct snd_platform_data {
+       u32 tx_dma_offset;
+       u32 rx_dma_offset;
+       int asp_chan_q; /* event queue number for ASP channel */
+       int ram_chan_q; /* event queue number for RAM channel */
+       unsigned int codec_fmt;
+       /*
+        * Allowing this is more efficient and eliminates left and right swaps
+        * caused by underruns, but will swap the left and right channels
+        * when compared to previous behavior.
+        */
+       unsigned enable_channel_combine:1;
+       unsigned sram_size_playback;
+       unsigned sram_size_capture;
+
+       /*
+        * If McBSP peripheral gets the clock from an external pin,
+        * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+        * and MCBSP_CLKS.
+        * Depending on different hardware connections it is possible
+        * to use this setting to change the behaviour of McBSP
+        * driver.
+        */
+       int clk_input_pin;
+
+       /*
+        * This flag works when both clock and FS are outputs for the cpu
+        * and makes clock more accurate (FS is not symmetrical and the
+        * clock is very fast.
+        * The clock becoming faster is named
+        * i2s continuous serial clock (I2S_SCK) and it is an externally
+        * visible bit clock.
+        *
+        * first line : WordSelect
+        * second line : ContinuousSerialClock
+        * third line: SerialData
+        *
+        * SYMMETRICAL APPROACH:
+        *   _______________________          LEFT
+        * _|         RIGHT         |______________________|
+        *     _   _         _   _   _   _         _   _
+        *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+        *     _   _         _   _   _   _         _   _
+        *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+        *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
+        *
+        * ACCURATE CLOCK APPROACH:
+        *   ______________          LEFT
+        * _|     RIGHT    |_______________________________|
+        *     _         _   _         _   _   _   _   _   _
+        *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+        *     _         _   _          _      dummy cycles
+        *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
+        *    \_/       \_/ \_/        \_/
+        *
+        */
+       bool i2s_accurate_sck;
+
+       /* McASP specific fields */
+       int tdm_slots;
+       u8 op_mode;
+       u8 num_serializer;
+       u8 *serial_dir;
+       u8 version;
+       u8 txnumevt;
+       u8 rxnumevt;
+};
+
+enum {
+       MCASP_VERSION_1 = 0,    /* DM646x */
+       MCASP_VERSION_2,        /* DA8xx/OMAPL1x */
+};
+
+enum mcbsp_clk_input_pin {
+       MCBSP_CLKR = 0,         /* as in DM365 */
+       MCBSP_CLKS,
+};
+
+#define INACTIVE_MODE  0
+#define TX_MODE                1
+#define RX_MODE                2
+
+#define DAVINCI_MCASP_IIS_MODE 0
+#define DAVINCI_MCASP_DIT_MODE 1
+
+#endif
index 4b37e2ac4685d4e7e8977889eabbf968b157ea88..ab0ad4591b083dc1c4a8d8ba3f24a8d2405852db 100644 (file)
@@ -22,9 +22,6 @@
 #include <asm/dma.h>
 #include <asm/mach-types.h>
 
-#include <mach/asp.h>
-#include <mach/edma.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 #include "davinci-mcasp.h"
index 407df7233d6d2afd1bcc94f2c95678dfb340cdb7..8218312071801bcafe3031fd308d70edd3bbd870 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -23,8 +24,6 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <mach/asp.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 
index 51479f9ee9094eed3c722412692389f42d0aaef6..0de9ed6ce038a8472aeb762d403fbf26d579bc24 100644 (file)
@@ -19,7 +19,8 @@
 #define DAVINCI_MCASP_H
 
 #include <linux/io.h>
-#include <mach/asp.h>
+#include <linux/platform_data/davinci_asp.h>
+
 #include "davinci-pcm.h"
 
 #define DAVINCI_MCASP_RATES    SNDRV_PCM_RATE_8000_96000
index 4b70828beedba4f0a43db709a86c9b5e2a801b03..93ea3bf567e1fd1835ff643ff4e73d67fecdce12 100644 (file)
@@ -23,7 +23,6 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
-#include <mach/edma.h>
 #include <mach/sram.h>
 
 #include "davinci-pcm.h"
index 5e5516460461a53863239781762807c5c2548ff1..fc4d01cdd8c95c92b11694faece56d77fc648bd9 100644 (file)
@@ -12,9 +12,8 @@
 #ifndef _DAVINCI_PCM_H
 #define _DAVINCI_PCM_H
 
+#include <linux/platform_data/davinci_asp.h>
 #include <mach/edma.h>
-#include <mach/asp.h>
-
 
 struct davinci_pcm_dma_params {
        int channel;                    /* sync dma channel ID */