dev_name = "aml_sha_dma";
};
+* Content based crypto engine
+This feature is only supported on devices that has key table integrated
+
+Required properties:
+- compatible : Should be "amlogic,crypto_sc2" for sc2
+- dev_name : Should be "aml_crypto_dev"
+
+Example:
+crypto {
+ compatible = "amlogic,crypto_sc2";
+ dev_name = "aml_crypto_dev";
+ status = "okay";
+ thread = /bits/ 5 <0x0>;
+ interrupts = <0 29 1>;
+}
-----------
This system call opens a named audio device (e.g.
-/dev/dvb/adapter0/audio0) for subsequent use. When an open() call has
+/dev/dvb0.audio0) for subsequent use. When an open() call has
succeeded, the device will be ready for use. The significance of
blocking or non-blocking mode is described in the documentation for
functions where there is a difference. It does not affect the semantics
DVB Audio Device
################
The DVB audio device controls the MPEG2 audio decoder of the DVB
-hardware. It can be accessed through ``/dev/dvb/adapter?/audio?``. Data
+hardware. It can be accessed through ``/dev/dvb?.audio?``. Data
types and and ioctl definitions can be accessed by including
``linux/dvb/audio.h`` in your application.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _CA_SC2_SET_DESCR_EX:
+
+============
+CA_SC2_SET_DESCR_EX
+============
+
+Name
+----
+
+CA_SC2_SET_DESCR_EX
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, CA_SC2_SET_DESCR, struct ca_sc2_descr_ex *desc)
+ :name: CA_SC2_SET_DESCR_EX
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by a previous call to :c:func:`open() <cec-open>`.
+
+``msg``
+ Pointer to struct :c:type:`ca_sc2_descr_ex`. the cmd it include
+ CA_ALLOC/CA_FREE/CA_KEY/CA_GET_STATUS/CA_SET_SCB/CA_SET_ALGO
+
+
+Description
+-----------
+
+ this extend for amlogic sc2 chip, support DSC setting.
+
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
.. -*- coding: utf-8; mode: rst -*-
-.. _CA_SET_DESCR_EX:
+.. _CA_SC2_SET_DESCR_EX:
-============
-CA_SET_DESCR_EX
-============
+===================
+CA_SC2_SET_DESCR_EX
+===================
Name
----
-CA_SET_DESCR_EX
+CA_SC2_SET_DESCR_EX
Synopsis
--------
-.. c:function:: int ioctl(fd, CA_SET_DESCR, struct ca_descr_ex *desc)
- :name: CA_SET_DESCR_EX
+.. c:function:: int ioctl(fd, CA_SC2_SET_DESCR, struct ca_sc2_descr_ex *desc)
+ :name: CA_SC2_SET_DESCR_EX
Arguments
File descriptor returned by a previous call to :c:func:`open() <cec-open>`.
``msg``
- Pointer to struct :c:type:`ca_descr_ex`.
+ Pointer to struct :c:type:`ca_sc2_descr_ex`.
Description
*************
-.. c:type:: ca_slot_info
-
ca_slot_info_t
==============
+.. c:type:: ca_slot_info
.. code-block:: c
#define CA_CI_MODULE_READY 2
} ca_slot_info_t;
-
-.. c:type:: ca_descr_info
-
ca_descr_info_t
===============
+.. c:type:: ca_descr_info
.. code-block:: c
#define CA_DSS 4
} ca_descr_info_t;
-
-.. c:type:: ca_caps
-
ca_caps_t
=========
+.. c:type:: ca_caps
.. code-block:: c
} ca_cap_t;
-.. c:type:: ca_msg
-
ca_msg_t
========
+.. c:type:: ca_msg
.. code-block:: c
unsigned char msg[256];
} ca_msg_t;
-
-.. c:type:: ca_descr
-
ca_descr_t
==========
+.. c:type:: ca_descr
.. code-block:: c
} ca_descr_t;
-.. c:type:: ca_pid
-
-ca-pid
-======
+ca_pid_t
+========
+.. c:type:: ca_pid
.. code-block:: c
int index; /* -1 == disable*/
} ca_pid_t;
-ca_descr_ex
+ca_sc2_algo_type
+================
+
+.. c:type:: ca_sc2_algo_type
+
+.. code-block:: c
+
+ enum ca_sc2_algo_type {
+ CA_ALGO_AES_ECB_CLR_END,
+ CA_ALGO_AES_ECB_CLR_FRONT,
+ CA_ALGO_AES_CBC_CLR_END,
+ CA_ALGO_AES_CBC_IDSA,
+ CA_ALGO_CSA2,
+ CA_ALGO_DES_SCTE41,
+ CA_ALGO_DES_SCTE52,
+ CA_ALGO_TDES_ECB_CLR_END,
+ CA_ALGO_CPCM_LSA_MDI_CBC,
+ CA_ALGO_CPCM_LSA_MDD_CBC,
+ CA_ALGO_CSA3,
+ CA_ALGO_ASA,
+ CA_ALGO_ASA_LIGHT,
+ CA_ALGO_UNKNOWN
+ };
+
+ca_sc2_dsc_type
+===============
+
+.. c:type:: ca_sc2_dsc_type
+
+.. code-block:: c
+
+ /*Hardware descrmalber module type.*/
+ enum ca_sc2_dsc_type {
+ CA_DSC_COMMON_TYPE, /*TSN*/
+ CA_DSC_TSD_TYPE, /*TSD*/
+ CA_DSC_TSE_TYPE /*TSE*/
+ };
+
+ca_sc2_alloc
+============
+
+.. c:type:: ca_sc2_alloc
+
+.. code-block:: c
+
+ /*Descrambler allocation parameters.*/
+ struct ca_sc2_alloc {
+ unsigned int pid; /*PID*/
+ enum ca_sc2_algo_type algo; /*Crypto algorithm*/
+ enum ca_sc2_dsc_type dsc_type; /*Hardware module*/
+ unsigned int ca_index; /*Return the descrambler slot's index*/
+ };
+
+ca_sc2_free
+===========
+
+.. c:type:: ca_sc2_free
+
+.. code-block:: c
+
+ /*Descrambler free parameters.*/
+ struct ca_sc2_free {
+ unsigned int ca_index; /*The descramlber slot's index to be freed*/
+ };
+
+ca_sc2_key_type
+===============
+
+.. c:type:: ca_sc2_key_type
+
+.. code-block:: c
+
+ /*Key type*/
+ enum ca_sc2_key_type {
+ CA_KEY_EVEN_TYPE, /*Even key*/
+ CA_KEY_EVEN_IV_TYPE, /*IV data for even key*/
+ CA_KEY_ODD_TYPE, /*Odd key*/
+ CA_KEY_ODD_IV_TYPE, /*IV data for odd key*/
+ CA_KEY_00_TYPE, /*Key for packets scrambling control == 0*/
+ CA_KEY_00_IV_TYPE /*IV data for CA_KEY_00_TYPE*/
+ };
+
+ca_sc2_key
+==========
+
+.. c:type:: ca_sc2_key
+
+.. code-block:: c
+
+ /*Key setting parameters.*/
+ struct ca_sc2_key {
+ unsigned int ca_index; /*The descrambler slot's index*/
+ enum ca_sc2_key_type parity; /*The key's type*/
+ unsigned int key_index; /*The key's index in the key table*/
+ };
+
+ca_sc2_cmd_type
===========
+.. c:type:: ca_sc2_cmd_type
+
+.. code-block:: c
+
+ /* add for support sc2 ca*/
+ enum ca_sc2_cmd_type {
+ CA_ALLOC, /*Allocate a new descrambler slot.*/
+ CA_FREE, /*Free a descrambler slot*/
+ CA_KEY, /*Set a descrambler slot's key*/
+ CA_GET_STATUS, /*get ca pid status*/
+ CA_SET_SCB, /*control the scb bit*/
+ CA_SET_ALGO /*control algo independently*/
+ };
+
+ca_sc2_scb
+===========
+
+.. c:type:: ca_sc2_scb
+
+.. code-block:: c
+
+ struct ca_sc2_scb {
+ unsigned int ca_index;
+ unsigned char ca_scb; /*ca_scb (2bit)*/
+ unsigned char ca_scb_as_is; /*if 1, scb use orignal; if 0, use ca_scb*/
+ };
+
+ca_sc2_algo
+===========
+
+.. c:type:: ca_sc2_algo
+
+.. code-block:: c
+
+ struct ca_sc2_algo {
+ unsigned int ca_index;
+ enum ca_sc2_algo_type algo;
+ };
+
+ca_sc2_descr_ex
+===========
+
+.. c:type:: ca_sc2_descr_ex
.. code-block:: c
-struct ca_descr_ex {
- enum ca_cmd_type cmd;
- union {
- struct ca_alloc_t alloc_params;
- struct ca_free_t free_params;
- struct ca_key_t key_params;
- } params;
-};
+ struct ca_sc2_descr_ex {
+ enum ca_sc2_cmd_type cmd;
+ union {
+ struct ca_sc2_alloc alloc_params;
+ struct ca_sc2_free free_params;
+ struct ca_sc2_key key_params;
+ struct ca_sc2_scb scb_params;
+ struct ca_sc2_algo algo_params;
+ } params;
+ };
####################
The Digital TV class node for extend the function
- for example:
- demux_buf_status: get demux buf status, it will use when inject data to dvr.
- tuner_setting: it can dynamically config tuner.
- ts_setting: get/config ts setting.
+
+- dmx_setting: get dmx source info.
+
+- dsc_setting: get dsc source info
+
+- ts_setting: get/configure ts setting.
+
+- get_pcr: get pcr info
+
+- tsn_source: get/set tsn source
Description
-----------
-This system call, used with a device name of /dev/dvb/adapter0/demux0,
+This system call, used with a device name of /dev/dvb0.demux0,
allocates a new filter and returns a handle which can be used for
subsequent control of that filter. This call has to be made for each
filter to be used, i.e. every returned file descriptor is a reference to
-a single filter. /dev/dvb/adapter0/dvr0 is a logical device to be used
+a single filter. /dev/dvb0.dvr0 is a logical device to be used
for retrieving Transport Streams for digital video recording. When
reading from this device a transport stream containing the packets from
all PES filters set in the corresponding demux device
-(/dev/dvb/adapter0/demux0) having the output set to DMX_OUT_TS_TAP. A
+(/dev/dvb0.demux0) having the output set to DMX_OUT_TS_TAP. A
recorded Transport Stream is replayed by writing to this device.
The significance of blocking or non-blocking mode is described in the
``fd``
File descriptor returned by a previous call to :c:func:`open() <dvb-ca-open>`.
- ``buf``
+``buf``
Buffer to be filled
``count``
circular buffer to buf. The maximum amount of data to be transferred is
implied by count.
+If the filter is a PES filter with flag DMX_OUTPUT_RAW_MODE,
+"read" return the data as :c:type:`dmx_sec_es_data`.
+
+If the filter is a PES filter without flag DMX_OUTPUT_RAW_MODE and DMX_MEM_SEC_LEVEL,
+"read" return the data with a prefixed header :c:type:`dmx_non_sec_es_header` and
+followed with the real ES data.
+
Return Value
------------
-----------
This system call is only provided by the logical device
-/dev/dvb/adapter0/dvr0, associated with the physical demux device that
+/dev/dvb0.dvr0, associated with the physical demux device that
provides the actual DVR functionality. It is used for replay of a
digitally recorded Transport Stream. Matching filters have to be defined
-in the corresponding physical demux device, /dev/dvb/adapter0/demux0.
+in the corresponding physical demux device, /dev/dvb0.demux0.
The amount of data to be transferred is implied by count.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_GET_DVR_MEM:
+
+==============
+DMX_GET_DVR_MEM
+==============
+
+Name
+----
+
+DMX_GET_DVR_MEM
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_GET_DVR_MEM, &mem_info)
+ :name: DMX_GET_DVR_MEM
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``mem_info``
+ mem_info is struct dvr_mem_info, it will get wp_offset in dvr mem.
+
+
+Description
+-----------
+
+This ioctl call allows to get dvr mem offset in dvr phy mem.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_GET_FILTER_MEM_INFO:
+
+==============
+DMX_GET_FILTER_MEM_INFO
+==============
+
+Name
+----
+
+DMX_GET_FILTER_MEM_INFO
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_GET_FILTER_MEM_INFO, &mem_info)
+ :name: DMX_GET_FILTER_MEM_INFO
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``mem_info``
+ mem_info is struct dmx_filter_mem_info that all filter mem info in dmx.
+
+
+Description
+-----------
+
+This ioctl call allows to get all filter mem info in one dmx device.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_GET_HW_SOURCE:
+
+==============
+DMX_GET_HW_SOURCE
+==============
+
+Name
+----
+
+DMX_GET_HW_SOURCE
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_GET_HW_SOURCE, &source)
+ :name: DMX_GET_HW_SOURCE
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``source``
+ source is DMA0~7/FRONTEND0~7
+
+
+Description
+-----------
+
+This ioctl call allows to get dmx source, this source is one stream id.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_GET_MEM_INFO:
+
+==============
+DMX_GET_MEM_INFO
+==============
+
+Name
+----
+
+DMX_GET_MEM_INFO
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_GET_MEM_INFO, &mem_info)
+ :name: DMX_GET_MEM_INFO
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``mem_info``
+ mem_info is struct dmx_mem_info
+
+
+Description
+-----------
+
+This ioctl call allows to get dmx mem_info for one filter.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_SET_HW_SOURCE:
+
+==============
+DMX_SET_HW_SOURCE
+==============
+
+Name
+----
+
+DMX_SET_HW_SOURCE
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_SET_HW_SOURCE, source)
+ :name: DMX_SET_HW_SOURCE
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``source``
+ source is DMA0~7/FRONTEND_TS0~7.
+
+
+Description
+-----------
+
+This ioctl call allows to set dmx input source. it connect to one stream.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _DMX_SET_SEC_MEM:
+
+==============
+DMX_SET_SEC_MEM
+==============
+
+Name
+----
+
+DMX_SET_SEC_MEM
+
+
+Synopsis
+--------
+
+.. c:function:: int ioctl(fd, DMX_SET_SEC_MEM, &dvr_mem)
+ :name: DMX_SET_SEC_MEM
+
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by :c:func:`open() <dvb-dmx-open>`.
+
+``dvr_mem``
+ dvr_mem is struct dmx_sec_mem for filter mem, it will receive dvr data, this mem is phy mem
+
+
+Description
+-----------
+
+This ioctl call allows to set dvr phy mem for get dvr data.
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
#define DMX_KERNEL_CLIENT 0x8000
};
+dmx_audio_format
+==============
+
+.. c:type:: dmx_audio_format
+
+.. code-block:: c
+
+ enum dmx_audio_format {
+ AUDIO_UNKNOWN = 0, /* unknown media */
+ AUDIO_MPX = 1, /* mpeg audio MP2/MP3 */
+ AUDIO_AC3 = 2, /* Dolby AC3/EAC3 */
+ AUDIO_AAC_ADTS = 3, /* AAC-ADTS */
+ AUDIO_AAC_LOAS = 4, /* AAC-LOAS */
+ AUDIO_DTS = 5, /* DTS */
+ AUDIO_MAX
+ };
+
struct dmx_pes_filter_params
============================
dmx_output_t output;
dmx_pes_type_t pes_type;
__u32 flags;
-#ifdef CONFIG_AMLOGIC_DVB_COMPAT
-/*bit 8~15 for mem sec_level*/
-#define DMX_MEM_SEC_LEVEL1 (1 << 10)
-#define DMX_MEM_SEC_LEVEL2 (1 << 11)
-#define DMX_MEM_SEC_LEVEL3 (1 << 12)
-
-/*bit 16~23 for output */
-#define DMX_ES_OUTPUT (1 << 16)
-/*set raw mode, it will send the struct dmx_sec_es_data, not es data*/
-#define DMX_OUTPUT_RAW_MODE (1 << 17)
-
-/*24~31 one byte for audio type, dmx_audio_format_t*/
-#define DMX_AUDIO_FORMAT_BIT 24
-#endif
+ #ifdef CONFIG_AMLOGIC_DVB_COMPAT
+ /*bit 8~15 for mem sec_level*/
+ #define DMX_MEM_SEC_LEVEL1 (1 << 10)
+ #define DMX_MEM_SEC_LEVEL2 (1 << 11)
+ #define DMX_MEM_SEC_LEVEL3 (1 << 12)
+
+ /*bit 16~23 for output */
+ #define DMX_ES_OUTPUT (1 << 16)
+ /*set raw mode, it will send the struct dmx_sec_es_data, not es data*/
+ #define DMX_OUTPUT_RAW_MODE (1 << 17)
+
+ /*24~31 one byte for audio type, dmx_audio_format*/
+ #define DMX_AUDIO_FORMAT_BIT 24
+ #endif
};
.. code-block:: c
struct dmx_stc {
- unsigned int num; /* input : which STC? 0..N */
- unsigned int base; /* output: divisor for stc to get 90 kHz clock */
- __u64 stc; /* output: stc in 'base'*90 kHz units */
+ unsigned int num; /* input : which STC? 0..N */
+ unsigned int base; /* output: divisor for stc to get 90 kHz clock */
+ __u64 stc; /* output: stc in 'base'*90 kHz units */
};
.. code-block:: c
-typedef enum dmx_input_source {
- INPUT_DEMOD,
- INPUT_LOCAL,
- INPUT_LOCAL_SEC
-} dmx_input_source_t;
+ typedef enum dmx_input_source {
+ INPUT_DEMOD, /* ts from demod */
+ INPUT_LOCAL, /* ts from dma, input normal memory */
+ INPUT_LOCAL_SEC /* ts from dma, input security memory */
+ } dmx_input_source_t;
struct dmx_non_sec_es_header
============================
.. code-block:: c
-struct dmx_non_sec_es_header {
- __u8 pts_dts_flag;
+ struct dmx_non_sec_es_header {
+ __u8 pts_dts_flag; /* pts & dts flags */
__u64 pts;
__u64 dts;
- __u32 len;
-};
+ __u32 len; /* one frame es data len*/
+ };
struct dmx_sec_es_data
======================
.. code-block:: c
-struct dmx_sec_es_data {
+ struct dmx_sec_es_data {
__u8 pts_dts_flag;
__u64 pts;
__u64 dts;
- __u32 buf_start;
- __u32 buf_end;
- __u32 data_start;
- __u32 data_end;
-};
+ __u32 buf_start; /* start physic buf of received buf */
+ __u32 buf_end; /* end physic buf of received buf */
+ __u32 data_start; /* data start physic addr */
+ __u32 data_end; /* data end physic addr */
+ };
+
+struct dmx_sec_ts_data
+=====================
+.. c:type:: dmx_sec_ts_data
+
+.. code-block:: c
+
+ /*it return in dvr device when use secure memory */
+ struct dmx_sec_ts_data {
+ __u32 buf_start;
+ __u32 buf_end;
+ __u32 data_start;
+ __u32 data_end;
+ };
+
+struct dmx_mem_info
+====================
+.. c:type:: dmx_mem_info
+
+.. code-block:: c
+
+ struct dmx_mem_info {
+ __u32 dmx_total_size; /* total size of physic received memory */
+ __u32 dmx_buf_phy_start; /* start addr of physic received memory */
+ __u32 dmx_free_size; /* free size physic received memory */
+ __u32 dvb_core_total_size; /* dvb core use total size*/
+ __u32 dvb_core_free_size;
+ __u32 wp_offset; /* write pointer that's offset in physic received memory */
+ __u64 newest_pts; /* lates the pts have got*/
+ };
+
+struct dmx_sec_mem
+======================
+.. c:type:: dmx_sec_mem
+
+.. code-block:: c
+
+ /* set secure memory for dvr */
+ struct dmx_sec_mem {
+ __u32 buff;
+ __u32 size;
+ };
+
+struct filter_mem_info
+======================
+.. c:type:: filter_mem_info
+
+.. code-block:: c
+
+ struct filter_mem_info {
+ __u32 type;
+ __u32 pid;
+ struct dmx_mem_info filter_info;
+ };
+
+struct dmx_filter_mem_info
+=========================
+.. c:type:: dmx_filter_mem_info
+
+.. code-block:: c
+
+ struct dmx_filter_mem_info {
+ __u32 filter_num; /* all filters in one demux */
+ struct filter_mem_info info[40];
+ };
+
+struct dvr_mem_info
+======================
+.. c:type:: dvr_mem_info
+
+.. code-block:: c
+
+ struct dvr_mem_info {
+ __u32 wp_offset; /* wp in received memory for dvr */
+ };
or arch/arm64/boot/dts/amlogic/, it can configure the dmx/ca/dvr/net
device num. at same time configure the external demod according to
different hardware platform
- for example:
- dvb {
- compatible = "amlogic, dvb";
- dev_name = "dvb";
- status = "ok";
+for example:
- // using dmxdev num, max num is 32
- dmxdev_num = <4>;
+.. code-block:: c
- /*single demod setting */
- /*ts will bind with dmx device*/
- ts0_dmx = <0>;
- ts1_dmx = <1>;
- /*set pass tse or not, default is 1*/
+ demux {
+ compatible = "amlogic sc2, dvb-demux";
+ dev_name = "dvb-demux";
+ status = "okay";
+
+ reg = <0x0 0xfe000000 0x0 0x480000>;
+ // using dmxdev num, max num is 32
+ dmxdev_num = <4>;
+
+ /*single demod setting */
+ /*ts will bind with dmx device*/
+ ts0_dmx = <0>;
+ ts1_dmx = <1>;
+
+ /*set pass tse or not, default is 1*/
tse_enable = <0>;
- /*multi demod setting, such as maxlinear demod*/
- /*attention: ts how to bind to dmx device
- it should set sid in maxlinear driver
- sid list:
- dmx0 sid:0x20
- dmx1 sid:0x21
- ...
- dmx31 sid:0x2F
- */
- ts2_header_len = <4>;
+ /*multi demod setting, such as maxlinear demod*/
+ /*attention: ts how to bind to dmx device
+ it should set sid in maxlinear driver
+ sid list:
+ dmx0 sid:0x20
+ dmx1 sid:0x21
+ ...
+ dmx31 sid:0x2F
+ */
+ ts2_header_len = <4>;
ts2_header = <0x4b>;
ts2_sid_offset = <1>;
- ts2 = "serial-3wire";
- ts2_control = <0x0>;
-
- fe0_mode = "external";
- fe0_demod = "cxd2856";
- fe0_i2c_adap_id = <&i2c3>;
- fe0_demod_i2c_addr = <0xD8>;
- fe0_ts = <0>;
- fe0_reset_value = <0>;
- fe0_reset_gpio = <&gpio GPIOZ_10 GPIO_ACTIVE_HIGH>;
- fe0_ant_poweron_value = <0>;
- fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ ts2 = "serial-4wire";
+ ts2_control = <0x0>;
- pinctrl-names = "s3_ts0";
- pinctrl-0 = <&dvb_s_ts0_pins>;
- };
+ pinctrl-names = "s3_ts0";
+ pinctrl-0 = <&dvb_s_ts0_pins>;
+ };
.. note::
- dmxdev_num:if no define this variable, default the dmxdev_num is 32. and sid from 32 to 63
- it should according to the project and hardware to config.
- fex_xxx: it define the demod hardware configure.
- pinctrl-xxx: it define the demod pin mask.
- tsx_xxx: it define the ts configure with fex.
+ - dmxdev_num: default value is 32. and sid should be from 32 to 63. it should be set according to the hardware.
+
+ - fex_xxx: it define the demod hardware configure.
+
+ - pinctrl-xxx: it define the demod's pinmux.
+
+ - tsx_xxx: it define the ts configure with fex.
.. _dvbapi:
########################
-Part II - Digital TV API
+Digital TV API
########################
.. note::
frontend
demux
ca
+ key
net
- legacy_dvb_apis
examples
- audio_h
ca_h
+ key_h
dmx_h
frontend_h
net_h
- video_h
dts
class_node
-
**********************
Revision and Copyright
**********************
int main(void)
{
- int fd = open("/dev/dvb/adapter0/frontend0", O_RDWR);
+ int fd = open("/dev/dvb0.frontend0", O_RDWR);
if (!fd) {
perror ("open");
Example: Tuning
===============
-We will start with a generic tuning subroutine that uses the frontend
-and SEC, as well as the demux devices. The example is given for QPSK
+We will start with a generic tuning subroutine that uses the frontend,
+as well as the demux devices. The example is given for QPSK
tuners, but can easily be adjusted for QAM.
#include <linux/dvb/dmx.h>
#include <linux/dvb/frontend.h>
- #include <linux/dvb/sec.h>
#include <sys/poll.h>
- #define DMX "/dev/dvb/adapter0/demux1"
- #define FRONT "/dev/dvb/adapter0/frontend1"
- #define SEC "/dev/dvb/adapter0/sec1"
+ #define DMX "/dev/dvb0.demux1"
+ #define FRONT "/dev/dvb0.frontend1"
/* routine for checking if we have a signal and other status information*/
int FEReadStatus(int fd, fe_status_t *stat)
int diseqc, int pol, int srate, int fec, int lnb_lof1,
int lnb_lof2, int lnb_slof)
{
- struct secCommand scmd;
- struct secCmdSequence scmds;
struct dmx_pes_filter_params pesFilterParams;
FrontendParameters frp;
struct pollfd pfd[1];
return -1;
}
- if((sec = open(SEC,O_RDWR)) < 0){
- perror("SEC DEVICE: ");
- return -1;
- }
-
if (demux1 < 0){
if ((demux1=open(DMX, O_RDWR|O_NONBLOCK))
< 0){
if (freq < lnb_slof) {
frp.Frequency = (freq - lnb_lof1);
- scmds.continuousTone = SEC_TONE_OFF;
} else {
frp.Frequency = (freq - lnb_lof2);
- scmds.continuousTone = SEC_TONE_ON;
- }
- frp.Inversion = INVERSION_AUTO;
- if (pol) scmds.voltage = SEC_VOLTAGE_18;
- else scmds.voltage = SEC_VOLTAGE_13;
-
- scmd.type=0;
- scmd.u.diseqc.addr=0x10;
- scmd.u.diseqc.cmd=0x38;
- scmd.u.diseqc.numParams=1;
- scmd.u.diseqc.params[0] = 0xF0 | ((diseqc * 4) & 0x0F) |
- (scmds.continuousTone == SEC_TONE_ON ? 1 : 0) |
- (scmds.voltage==SEC_VOLTAGE_18 ? 2 : 0);
-
- scmds.miniCommand=SEC_MINI_NONE;
- scmds.numCommands=1;
- scmds.commands=&scmd;
- if (ioctl(sec, SEC_SEND_SEQUENCE, &scmds) < 0){
- perror("SEC SEND: ");
- return -1;
}
-
- if (ioctl(sec, SEC_SEND_SEQUENCE, &scmds) < 0){
- perror("SEC SEND: ");
- return -1;
- }
-
+ frp.inversion = INVERSION_AUTO;
frp.u.qpsk.SymbolRate = srate;
frp.u.qpsk.FEC_inner = fec;
#include <linux/dvb/dmx.h>
#include <linux/dvb/video.h>
#include <sys/poll.h>
- #define DVR "/dev/dvb/adapter0/dvr1"
- #define AUDIO "/dev/dvb/adapter0/audio1"
- #define VIDEO "/dev/dvb/adapter0/video1"
+ #define DVR "/dev/dvb0.dvr1"
#define BUFFY (188*20)
#define MAX_LENGTH (1024*1024*5) /* record 5MB */
===========
This system call opens a named frontend device
-(``/dev/dvb/adapter?/frontend?``) for subsequent use. Usually the first
+(``/dev/dvb?.frontend?``) for subsequent use. Usually the first
thing to do after a successful open is to find out the frontend type
with :ref:`FE_GET_INFO`.
- ``/dev/dvbN.caM``,
+- ``/dev/key``,
where N enumerates the DVB PCI cards in a system starting from 0, and M
enumerates the devices of each type within each adapter, starting
-from 0, too. We will omit the “ ``/dev/dvb/adapterN/``\ ” in the further
+from 0, too. We will omit the “ ``/dev/dvbN/``\ ” in the further
discussion of these devices.
More details about the data structures and function calls of all the
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _KEY_ALLOC:
+
+==============
+KEY_ALLOC
+==============
+
+Name
+----
+
+KEY_ALLOC
+
+
+Synopsis
+--------
+.. code-block:: c
+
+ int ioctl(int fd, KEY_ALLOC, struct key_alloc *params)
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by open /dev/key device.
+
+``params``
+
+ Pointer to structure containing filter parameters.
+
+
+Description
+-----------
+
+This ioctl call alloc the key index according to is_iv
+parameters provided. the key index return from parameter .
+
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _KEY_CONFIG:
+
+==============
+KEY_CONFIG
+==============
+
+Name
+----
+
+KEY_CONFIG
+
+
+Synopsis
+--------
+.. code-block:: c
+
+ int ioctl( int fd, KEY_CONFIG, struct key_config *config)
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by open /dev/key.
+
+``config``
+
+ Pointer to structure containing key config.
+
+
+Description
+-----------
+
+This ioctl call config used which descramble modue & algo.
+
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _KEY_FREE:
+
+==============
+KEY_FREE
+==============
+
+Name
+----
+
+KEY_FREE
+
+
+Synopsis
+--------
+.. code-block:: c
+
+ int ioctl(int fd, KEY_FREE, int key_index)
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by open /dev/key.
+
+``key_index``
+
+ key_index that come from the key_alloc.
+
+
+Description
+-----------
+ this ioctl will free the key index
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _KEY_GET_FLAG:
+
+==============
+KEY_GET_FLAG
+==============
+
+Name
+----
+
+KEY_GET_FLAG
+
+
+Synopsis
+--------
+.. code-block:: c
+
+ int ioctl( int fd, KEY_GET_FLAG, struct key_desc *params)
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by open /dev/key.
+
+``params``
+
+ Pointer to structure containing key desc parameters.
+ key[0] will return the flag
+
+
+Description
+-----------
+
+This ioctl call return the key status for debug
+the key status return from the key[0] in the struct key_descr
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _KEY_SET:
+
+==============
+KEY_SET
+==============
+
+Name
+----
+
+KEY_SET
+
+
+Synopsis
+--------
+.. code-block:: c
+
+ int ioctl( int fd, KEY_SET, struct key_descr *key)
+
+Arguments
+---------
+
+``fd``
+ File descriptor returned by open /dev/key.
+
+``key``
+
+ Pointer to structure containing key parameters.
+
+
+Description
+-----------
+
+This ioctl call update the key contents according to the key index.
+if update the odd/even key, you can call this ioctl to update key to
+key_table, but this just for ree mode, not ta mode.
+
+
+Return Value
+------------
+
+On success 0 is returned, on error -1 and the ``errno`` variable is set
+appropriately. The generic error codes are described at the
+:ref:`Generic Error Codes <gen-errors>` chapter.
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _dvb_key:
+
+################
+key Device
+################
+The DVB key device controls the key.
+It can be accessed through ``/dev/key``. Data types and and
+ioctl definitions can be accessed by including ``linux/amlogic/aml_key.h`` in
+your application.
+
+
+.. toctree::
+ :maxdepth: 1
+
+ key_types
+ key_fcalls
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _key_fcalls:
+
+********************
+Key Function Calls
+********************
+
+.. toctree::
+ :maxdepth: 1
+
+ key-alloc
+ key-free
+ key-set
+ key-config
+ key-get-flag
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _key_h:
+
+*********************
+DVB key Header File
+*********************
+
+.. kernel-include:: $BUILDDIR/key.h.rst
--- /dev/null
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _key_types:
+
+****************
+Key Types
+****************
+
+user_id
+===========
+
+.. c:type:: user_id
+
+.. code-block:: c
+
+ enum user_id {
+ DSC_LOC_DEC, /* local descramble module */
+ DSC_NETWORK, /* network descramble module */
+ DSC_LOC_ENC, /* local cramble module */
+
+ CRYPTO_T0 = 0x100, /* m2m en/decrypt */
+ };
+
+
+key_algo
+==============
+
+.. c:type:: key_algo
+
+
+.. code-block:: c
+
+ enum key_algo {
+ KEY_ALGO_AES,
+ KEY_ALGO_TDES,
+ KEY_ALGO_DES,
+ KEY_ALGO_CSA2,
+ KEY_ALGO_CSA3,
+ KEY_ALGO_NDL,
+ KEY_ALGO_ND
+ };
+
+struct key_descr
+=================
+
+.. c:type:: key_descr
+
+.. code-block:: c
+
+ struct key_descr {
+ unsigned int key_index; /*key_index, from the key_alloc*/
+ unsigned int key_len; /*key_len, 8/16/32 in general*/
+ unsigned char key[32];
+ };
+
+
+struct key_config
+============================
+
+.. c:type:: key_config
+
+.. code-block:: c
+
+ struct key_config {
+ unsigned int key_index; /* key_index, from the key_alloc*/
+ int key_userid; /* use descramble/enscramble module*/
+ int key_algo; /* algo*/
+ };
+
+struct key_alloc
+==============
+
+.. c:type:: key_alloc
+
+.. code-block:: c
+
+ struct key_alloc {
+ int is_iv; /*1: iv, 0: even/odd key */
+ unsigned int key_index; /*return key_index */
+ };
+
In order to create the Linux virtual network interfaces, an application
needs to tell to the Kernel what are the PIDs and the encapsulation
types that are present on the transport stream. This is done through
-``/dev/dvb/adapter?/net?`` device node. The data will be available via
+``/dev/dvb?.net?`` device node. The data will be available via
virtual ``dvb?_?`` network interfaces, and will be controlled/routed via
the standard ip tools (like ip, route, netstat, ifconfig, etc).
-----------
This system call opens a named video device (e.g.
-/dev/dvb/adapter0/video0) for subsequent use.
+/dev/dvb0.video0) for subsequent use.
When an open() call has succeeded, the device will be ready for use. The
significance of blocking or non-blocking mode is described in the
DVB Video Device
################
The DVB video device controls the MPEG2 video decoder of the DVB
-hardware. It can be accessed through **/dev/dvb/adapter0/video0**. Data
+hardware. It can be accessed through **/dev/dvb0.video0**. Data
types and and ioctl definitions can be accessed by including
**linux/dvb/video.h** in your application.
scripts_basic:
$(Q)$(MAKE) $(build)=scripts/basic
$(Q)rm -f .tmp_quiet_recordmcount
- $(Q)mkdir -p $(srctree)/.git/hooks
- $(Q)cp $(srctree)/scripts/amlogic/pre-commit $(srctree)/.git/hooks/
- $(Q)chmod +x $(srctree)/.git/hooks/pre-commit
+ $(Q)if [ -d $(srctree)/.git/hooks ]; then \
+ cp $(srctree)/scripts/amlogic/pre-commit $(srctree)/.git/hooks/; \
+ chmod +x $(srctree)/.git/hooks/pre-commit; \
+ fi
+#$(Q)mkdir -p $(srctree)/.git/hooks
# To avoid any implicit rule to kick in, define an empty command.
scripts/basic/%: scripts_basic ;
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
- parts = "vbmeta,boot,system,vendor";
+ parts = "vbmeta,boot,system,vendor,oem";
by_name_prefix="/dev/block";
};
- fstab {
- compatible = "android,fstab";
- system {
- compatible = "android,system";
- dev = "system";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
- };
-
- vendor {
- compatible = "android,vendor";
- dev = "vendor";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb,logical,first_stage_mount";
- };
- odm {
- compatible = "android,odm";
- dev = "odm";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb,logical,first_stage_mount";
- };
- product {
- compatible = "android,product";
- dev = "product";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb,logical,first_stage_mount";
- };
- metadata {
- compatible = "android,metadata";
- dev = "/dev/block/metadata";
- type = "ext4";
- mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
- fsmgr_flags = "wait,check,formattable,first_stage_mount";
- };
- };
};
};
};/* end of / */
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
- parts = "vbmeta,boot,system,vendor";
+ parts = "vbmeta,boot,system,vendor,oem";
by_name_prefix="/dev/block";
};
- fstab {
- compatible = "android,fstab";
- system {
- compatible = "android,system";
- dev = "system";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
- };
-
- vendor {
- compatible = "android,vendor";
- dev = "vendor";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
- };
- odm {
- compatible = "android,odm";
- dev = "odm";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
- };
- product {
- compatible = "android,product";
- dev = "product";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
- };
- metadata {
- compatible = "android,metadata";
- dev = "/dev/block/by-name/metadata";
- type = "ext4";
- mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
- fsmgr_flags = "wait,check,formattable,first_stage_mount";
- };
- };
};
};
};/* end of / */
--- /dev/null
+/*
+ * Amlogic partition set for normal
+ *
+ * Copyright (c) 2017-2017 Amlogic Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+/ {
+ firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor";
+ by_name_prefix="/dev/block";
+ };
+ fstab {
+ compatible = "android,fstab";
+ system {
+ compatible = "android,system";
+ dev = "system";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
+ };
+
+ vendor {
+ compatible = "android,vendor";
+ dev = "vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb,logical,first_stage_mount";
+ };
+ odm {
+ compatible = "android,odm";
+ dev = "odm";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb,logical,first_stage_mount";
+ };
+ product {
+ compatible = "android,product";
+ dev = "product";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb,logical,first_stage_mount";
+ };
+ metadata {
+ compatible = "android,metadata";
+ dev = "/dev/block/metadata";
+ type = "ext4";
+ mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
+ fsmgr_flags = "wait,check,formattable,first_stage_mount";
+ };
+ };
+ };
+ };
+};/* end of / */
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
amlvideo2_id = <1>;
cma_mode = <1>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
&clkc CLKID_DOS_PARSER>;
clock-names = "demux", "ahbarb0", "parser_top";
};
-
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <19>;
+ unifykey-num = <18>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
- unifykey-index-18= <&keysn_18>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_18:key_18{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
key_val = <143 266 389>; //val=voltage/1800mV*1023
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "okay";
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
status = "okay";
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
demux {
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <17>;
+ unifykey-num = <16>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-13= <&keysn_13>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
- unifykey-index-16= <&keysn_16>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_16:key_16{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <19>;
+ unifykey-num = <18>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
- unifykey-index-18= <&keysn_18>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_18:key_18{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
demux {
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
/*1:enabel osd lut 100 table;0:disable*/
- cfg_en_osd_100 = <1>;
+ cfg_en_osd_100 = <3>;
/*0: 709/601 1: bt2020*/
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
/*1:enabel osd lut 100 table;0:disable*/
- cfg_en_osd_100 = <1>;
+ cfg_en_osd_100 = <3>;
/*0: 709/601 1: bt2020*/
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-permit = "read","write","del";
};
keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
+ key-name = "oemkey";
+ key-device = "normal";
+ key-permit = "read","write","del";
};
keysn_18:key_18{
key-name = "attestationdevidbox";// attest dev id box
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "oemkey";
- key-device = "normal";
- key-permit = "read","write","del";
- };
};//End unifykey
demux {
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-permit = "read","write","del";
};
keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
+ key-name = "oemkey";
+ key-device = "normal";
+ key-permit = "read","write","del";
};
keysn_18:key_18{
key-name = "attestationdevidbox";// attest dev id box
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "oemkey";
- key-device = "normal";
- key-permit = "read","write","del";
- };
};//End unifykey
demux {
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
cm_en = <0>;/*1:enabel ;0:disable*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
cm_en = <0>;/*1:enabel ;0:disable*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B
storage_version = <0x8200006C>;
};
+ ddr-scrambler@0xfe02e030 {
+ compatible = "amlogic, ddr-scrambler-preserve";
+ reg = <0xfe02e030 0x4>;
+ };
+
mailbox_mhu_fifo: mhu@fe006000 {
status = "okay";
compatible = "amlogic, meson_mhu_fifo";
status = "disabled";
};
+ amaudio: amaudio {
+ compatible = "amlogic, amaudio";
+ reg = <0xfe440000 0x10000>;
+ reg-names = "otp_tee_base";
+ status = "okay";
+ };
+
dwc3: dwc3@fde00000 {
compatible = "synopsys, dwc3";
status = "disable";
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <14>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* refer to sc2-system-registers.docx */
- interrupts = <0 204 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 204 1
+ 0 197 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* refer to hdmi_tx_module.h */
ic_type = <15>;
vend_data: vend_data{ /* Should modified by Customer */
pinctrl-names = "sd_all_pins",
"sd_clk_cmd_pins",
- "sd_1bit_pins";
+ "sd_1bit_pins",
+ "sd_clk_cmd_uart_pins",
+ "sd_1bit_uart_pins",
+ "sd_to_ao_uart_pins",
+ "ao_to_sd_uart_pins",
+ "sd_to_ao_jtag_pins",
+ "ao_to_sd_jtag_pins",
+ "sd_all_pd_pins";
pinctrl-0 = <&sd_all_pins>;
pinctrl-1 = <&sd_clk_cmd_pins>;
pinctrl-2 = <&sd_1bit_pins>;
+ pinctrl-3 = <&sd_to_ao_uart_clr_pins
+ &sd_clk_cmd_pins &ao_to_sd_uart_pins>;
+ pinctrl-4 = <&sd_to_ao_uart_clr_pins
+ &sd_1bit_pins &ao_to_sd_uart_pins>;
+ pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>;
+ pinctrl-6 = <&sd_to_ao_uart_clr_pins
+ &ao_to_sd_uart_pins>;
+ pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>;
+ pinctrl-8 = <&sd_to_ao_uart_clr_pins
+ &ao_to_sd_uart_pins>;
+ pinctrl-9 = <&sd_all_pd_pins>;
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK_COMP>,
vol_switch = <&gpio GPIOD_2 GPIO_ACTIVE_HIGH>;
vol_switch_18 = <1>; /* 1 = high, 0 = low */
vol_switch_delay = <150>; /* Uint: ms*/
+ no_sduart = <1>;
card_type = <5>;
/* 3:sdio device(ie:sdio-wifi),
* 4:SD combo (IO+mem) card
dev_name = "aml_sha_dma";
status = "okay";
};
+
+ crypto {
+ compatible = "amlogic,crypto_sc2";
+ dev_name = "aml_crypto_dev";
+ status = "okay";
+ thread = /bits/ 8 <0x5>;
+ interrupts = <0 29 1>;
+ };
};
rng {
ao_to_sd_uart_pins:ao_to_sd_uart_pins {
mux {
- groups = "uart_ao_tx_a_c3",
- "uart_ao_rx_a_c2";
- function = "uart_ao_a_ee";
+ groups = "uart_b_rx_c",
+ "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
+ mux {
+ groups = "GPIOD_0",
+ "GPIOD_1";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+
+ sd_to_ao_uart_pins:sd_to_ao_uart_pins {
+ mux {
+ groups = "uart_b_rx_d",
+ "uart_b_tx_d";
+ function = "uart_b";
bias-pull-up;
input-enable;
};
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B 12:SM1
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
compatible = "amlogic, vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2: vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vdac {
num-lanes = <1>;
pcie-num = <1>;
- clocks = <&clkc CLKID_PCIE0_GATE
- &clkc CLKID_PCIE1
- &clkc CLKID_PCIE0PHY>;
+ clocks = <&clkc CLKID_PCIE_PLL
+ &clkc CLKID_PCIE0
+ &clkc CLKID_PCIE0PHY
+ &clkc CLKID_PCIE0_GATE>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
num-lanes = <1>;
pcie-num = <1>;
- clocks = <&clkc CLKID_PCIE1_GATE
+ clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE1
- &clkc CLKID_PCIE1PHY>;
+ &clkc CLKID_PCIE1PHY
+ &clkc CLKID_PCIE1_GATE>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <30>;
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
- interrupts = <0 7 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 7 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B 12:SM1 13:TM2
compatible = "amlogic, vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2: vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vdac {
*
*/
-#include "firmware_avb_Q.dtsi"
+#include "firmware_avb_deadpool.dtsi"
/ {
partitions: partitions{
/ {
partitions: partitions{
- parts = <15>;
+ parts = <17>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&tee>;
part-6 = <&cri_data>;
part-7 = <¶m>;
part-8 = <&boot>;
- part-9 = <&rsv>;
- part-10 = <&metadata>;
- part-11 = <&vbmeta>;
- part-12 = <&super>;
- part-13 = <&cache>;
- part-14 = <&data>;
+ part-9 = <&oem>;
+ part-10 = <&odm_ext>;
+ part-11 = <&rsv>;
+ part-12 = <&metadata>;
+ part-13 = <&vbmeta>;
+ part-14 = <&super>;
+ part-15 = <&cache>;
+ part-16 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <2>;
};
+ oem:oem{
+ pname = "oem";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext:odm_ext
+ {
+ pname = "odm_ext";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
rsv:rsv{
pname = "rsv";
size = <0x0 0x1000000>;
/ {
partitions: partitions{
- parts = <19>;
+ parts = <22>;
part-0 = <&logo>;
part-1 = <&recovery_a>;
part-2 = <&recovery_b>;
part-9 = <¶m>;
part-10 = <&boot_a>;
part-11 = <&boot_b>;
- part-12 = <&rsv>;
+ part-12 = <&oem_a>;
part-13 = <&metadata>;
- part-14 = <&rsv2>;
- part-15 = <&vbmeta_a>;
- part-16 = <&vbmeta_b>;
- part-17 = <&super>;
- part-18 = <&data>;
+ part-14 = <&oem_b>;
+ part-15 = <&odm_ext_a>;
+ part-16 = <&odm_ext_b>;
+ part-17 = <&rsv>;
+ part-18 = <&vbmeta_a>;
+ part-19 = <&vbmeta_b>;
+ part-20 = <&super>;
+ part-21 = <&userdata>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <2>;
};
- rsv:rsv{
- pname = "rsv";
+ oem_a:oem_a{
+ pname = "oem_a";
size = <0x0 0x1000000>;
mask = <1>;
};
size = <0x0 0x1000000>;
mask = <1>;
};
- rsv2:rsv2{
- pname = "rsv2";
+ oem_b:oem_b{
+ pname = "oem_b";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext_a:odm_ext_a
+ {
+ pname = "odm_ext_a";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext_b:odm_ext_b
+ {
+ pname = "odm_ext_b";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ rsv:rsv{
+ pname = "rsv";
size = <0x0 0x1000000>;
mask = <1>;
};
size = <0x0 0xC8800000>;
mask = <1>;
};
- data:data
+ userdata:userdata
{
- pname = "data";
+ pname = "userdata";
size = <0xffffffff 0xffffffff>;
mask = <4>;
};
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x00800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x00800000>;
- };
};
cma_shrinker {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
/* mode 0~4, defalut:1 */
filter_mode = <1>;
-
+ /* lane-mask-in = <0 1 0 0>; */
train_sample_count = <0xe>;
status = "okay";
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x00800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x00800000>;
- };
};
amlogic_battery:dummy-battery {
};
partitions: partitions{
- parts = <14>;
+ parts = <15>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&misc>;
part-6 = <&boot>;
part-7 = <&rsv>;
part-8 = <&tee>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&system>;
- part-12 = <&cache>;
- part-13 = <&data>;
+ part-9 = <&factory>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&system>;
+ part-13 = <&cache>;
+ part-14 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x2000000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
vendor:vendor{
pname = "vendor";
size = <0x0 0x10000000>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x00800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x00800000>;
- };
};
cma_shrinker {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x00800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x00800000>;
- };
};
amlogic_battery:dummy-battery {
};
partitions: partitions{
- parts = <14>;
+ parts = <15>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&misc>;
part-6 = <&boot>;
part-7 = <&rsv>;
part-8 = <&tee>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&system>;
- part-12 = <&cache>;
- part-13 = <&data>;
+ part-9 = <&factory>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&system>;
+ part-13 = <&cache>;
+ part-14 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x2000000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
vendor:vendor{
pname = "vendor";
size = <0x0 0x20000000>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_mode = "external";
fe1_demod = "cxd2856";
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x00800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x00800000>;
- };
};
cma_shrinker {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x800000>;
- };
};
cma_shrinker {
status = "okay";
fe_num = <1>;
- fe0_mode = "external";
fe0_demod = "cxd2856";
fe0_i2c_adap_id = <&i2c2>;
fe0_demod_i2c_addr = <0xD8>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
/* mode 0~4, defalut:1 */
filter_mode = <1>;
-
+ /* lane-mask-in = <0 1 0 0>; */
train_sample_count = <0xe>;
status = "okay";
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x800000>;
- };
};
amlogic_battery:dummy-battery {
};
partitions: partitions{
- parts = <14>;
+ parts = <15>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&misc>;
part-6 = <&boot>;
part-7 = <&rsv>;
part-8 = <&tee>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&system>;
- part-12 = <&cache>;
- part-13 = <&data>;
+ part-9 = <&factory>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&system>;
+ part-13 = <&cache>;
+ part-14 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x2000000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
vendor:vendor{
pname = "vendor";
size = <0x0 0x10000000>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
compatible = "amlogic, tm2-revb-snd-tdmb";
#sound-dai-cells = <0>;
dai-tdm-lane-slot-mask-in = <0 1 0 0>;
- dai-tdm-lane-slot-mask-out = <1 0 0 0>;
+ dai-tdm-lane-slot-mask-out = <1 1 1 1>;
dai-tdm-clk-sel = <1>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_B
&clkaudio CLKID_AUDIO_MCLK_PAD0
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x400000>;
alloc-ranges = <0x7f800000 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x800000>;
+ alignment = <0x400000>;
+ alloc-ranges = <0x30000000 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x2000000>;
alignment = <0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x800000>;
- alignment = <0x400000>;
- alloc-ranges = <0x3400000 0x800000>;
- };
};
amlogic_battery:dummy-battery {
};
partitions: partitions{
- parts = <14>;
+ parts = <15>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&misc>;
part-6 = <&boot>;
part-7 = <&rsv>;
part-8 = <&tee>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&system>;
- part-12 = <&cache>;
- part-13 = <&data>;
+ part-9 = <&factory>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&system>;
+ part-13 = <&cache>;
+ part-14 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x2000000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
vendor:vendor{
pname = "vendor";
size = <0x0 0x20000000>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
clock-names = "demux", "ahbarb0", "parser_top";
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
clock-names = "demux", "ahbarb0", "parser_top";
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <32>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
- unifykey-index-20= <&keysn_20>;
- unifykey-index-21= <&keysn_21>;
- unifykey-index-22= <&keysn_22>;
- unifykey-index-23= <&keysn_23>;
- unifykey-index-24= <&keysn_24>;
- unifykey-index-25= <&keysn_25>;
- unifykey-index-26= <&keysn_26>;
- unifykey-index-27= <&keysn_27>;
- unifykey-index-28= <&keysn_28>;
- unifykey-index-29= <&keysn_29>;
- unifykey-index-30= <&keysn_30>;
- unifykey-index-31= <&keysn_31>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_WIDEVINE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_20:key_20{
- key-name = "KEY_PLAYREADY_PRIVATE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_21:key_21{
- key-name = "KEY_PLAYREADY_PUBLIC";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_22:key_22{
- key-name = "KEY_HDCP_TX14";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_23:key_23{
- key-name = "KEY_HDCP_TX22";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_24:key_24{
- key-name = "KEY_HDCP_RX14";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_25:key_25{
- key-name = "KEY_HDCP_RX22";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_26:key_26{
- key-name = "KEY_HDCP_RX22_FW";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_27:key_27{
- key-name = "KEY_HDCP_RX22_FW_PRIVATE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_28:key_28{
- key-name = "KEY_KEYMASTER3";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_29:key_29{
- key-name = "PROVISION_FIELD_ID";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_30:key_30{
- key-name = "PROVISION_FIELD_PROTECT_KEY";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_31:key_31{
- key-name = "KEY_KM3_ATTEST_DEV_ID_BOX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
cma_mode = <1>;
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
mask = <4>;
};
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
clock-names = "demux", "ahbarb0", "parser_top";
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_reset_gpio = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
mask = <4>;
};
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
clock-names = "demux", "ahbarb0", "parser_top";
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
clock-names = "demux", "ahbarb0", "parser_top";
};
+
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
CONFIG_RFKILL=y
CONFIG_AMLOGIC_DRIVER=y
CONFIG_AMLOGIC_MODIFY=y
+CONFIG_AMLOGIC_SYNC_20210524=y
CONFIG_AMLOGIC_CPUFREQ=y
CONFIG_AMLOGIC_MESON_CPUFREQ=y
CONFIG_AMLOGIC_INPUT_BOOST=y
CONFIG_AMLOGIC_CPU_INFO=y
CONFIG_AMLOGIC_REG_ACCESS=y
CONFIG_AMLOGIC_TIMER=y
-CONFIG_AMLOGIC_BC_TIMER=y
CONFIG_AMLOGIC_CLK=y
CONFIG_AMLOGIC_COMMON_CLK_SCPI=y
CONFIG_AMLOGIC_GX_CLK=y
CONFIG_AMLOGIC_ATV_DEMOD=y
CONFIG_AMLOGIC_DEBUG=y
CONFIG_AMLOGIC_DEBUG_LOCKUP=y
+CONFIG_AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS=y
CONFIG_AMLOGIC_DEFENDKEY=y
CONFIG_AMLOGIC_BATTERY_DUMMY=y
CONFIG_AMLOGIC_CHARGER_DUMMY=y
CONFIG_AMLOGIC_CPU_INFO=y
CONFIG_AMLOGIC_REG_ACCESS=y
CONFIG_AMLOGIC_TIMER=y
-CONFIG_AMLOGIC_BC_TIMER=y
CONFIG_AMLOGIC_CLK=y
CONFIG_AMLOGIC_COMMON_CLK_SCPI=y
CONFIG_AMLOGIC_GX_CLK=y
if (!access_ok(VERIFY_READ, (void *)addr, nbytes))
return;
+#ifdef CONFIG_AMLOGIC_MODIFY
+ /*
+ * Treating data in general purpose register as an address
+ * and dereferencing it is quite a dangerous behaviour,
+ * especially when it is an address belonging to secure
+ * region or ioremap region, which can lead to external
+ * abort on non-linefetch and can not be protected by
+ * probe_kernel_address.
+ * We need more strict filtering rules
+ */
+
+#ifdef CONFIG_AMLOGIC_SEC
+ /*
+ * filter out secure monitor region
+ */
+ if (addr <= (unsigned long)high_memory)
+ if (within_secmon_region(addr)) {
+ pr_info("\n%s: %#lx S\n", name, addr);
+ return;
+ }
+#endif
+
+ /*
+ * filter out ioremap region
+ */
+ if ((addr >= VMALLOC_START) && (addr <= VMALLOC_END))
+ if (!pfn_valid(vmalloc_to_pfn((void *)addr))) {
+ pr_info("\n%s: %#lx V\n", name, addr);
+ return;
+ }
+#endif
+
pr_info("\n%s: %#lx:\n", name, addr);
/*
* This file contains the ARM-specific time handling details:
* reading the RTC at bootup, etc...
*/
+#include <linux/clockchips.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
#endif
clocksource_probe();
}
+
+#ifdef CONFIG_AMLOGIC_MODIFY
+ tick_setup_hrtimer_broadcast();
+#endif
}
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
- parts = "vbmeta,boot,system,vendor";
+ parts = "vbmeta,boot,system,vendor,oem";
by_name_prefix="/dev/block";
};
- fstab {
- compatible = "android,fstab";
- system {
- compatible = "android,system";
- dev = "system";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
- };
-
- vendor {
- compatible = "android,vendor";
- dev = "vendor";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,avb,logical,first_stage_mount";
- };
- odm {
- compatible = "android,odm";
- dev = "odm";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,logical,first_stage_mount";
- };
- product {
- compatible = "android,product";
- dev = "product";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,logical,first_stage_mount";
- };
- metadata {
- compatible = "android,metadata";
- dev = "/dev/block/metadata";
- type = "ext4";
- mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
- fsmgr_flags = "wait,check,formattable,first_stage_mount";
- };
- };
};
};
};/* end of / */
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
- parts = "vbmeta,boot,system,vendor";
+ parts = "vbmeta,boot,system,vendor,oem";
by_name_prefix="/dev/block";
};
- fstab {
- compatible = "android,fstab";
- system {
- compatible = "android,system";
- dev = "system";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
- };
-
- vendor {
- compatible = "android,vendor";
- dev = "vendor";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
- };
- odm {
- compatible = "android,odm";
- dev = "odm";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,logical,first_stage_mount";
- };
- product {
- compatible = "android,product";
- dev = "product";
- type = "ext4";
- mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
- fsmgr_flags = "wait,slotselect,logical,first_stage_mount";
- };
- metadata {
- compatible = "android,metadata";
- dev = "/dev/block/by-name/metadata";
- type = "ext4";
- mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
- fsmgr_flags = "wait,check,formattable,first_stage_mount";
- };
- };
};
};
};/* end of / */
--- /dev/null
+/*
+ * Amlogic partition set for normal
+ *
+ * Copyright (c) 2017-2017 Amlogic Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+/ {
+ firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor";
+ by_name_prefix="/dev/block";
+ };
+ fstab {
+ compatible = "android,fstab";
+ system {
+ compatible = "android,system";
+ dev = "system";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb=vbmeta,logical,first_stage_mount,avb_keys=/avb/q-gsi.avbpubkey:/avb/r-gsi.avbpubkey:/avb/s-gsi.avbpubkey";
+ };
+
+ vendor {
+ compatible = "android,vendor";
+ dev = "vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,avb,logical,first_stage_mount";
+ };
+ odm {
+ compatible = "android,odm";
+ dev = "odm";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,logical,first_stage_mount";
+ };
+ product {
+ compatible = "android,product";
+ dev = "product";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
+ fsmgr_flags = "wait,logical,first_stage_mount";
+ };
+ metadata {
+ compatible = "android,metadata";
+ dev = "/dev/block/metadata";
+ type = "ext4";
+ mnt_flags = "noatime,nosuid,nodev,nodelalloc,nomblk_io_submit,errors=panic";
+ fsmgr_flags = "wait,check,formattable,first_stage_mount";
+ };
+ };
+ };
+ };
+};/* end of / */
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
ts2_control = <0>;
ts2_invert = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
amlvideo2_id = <1>;
cma_mode = <1>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
amlvideo2_id = <1>;
cma_mode = <1>;
};
-
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
mask = <4>;
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <19>;
+ unifykey-num = <18>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
- unifykey-index-18= <&keysn_18>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_18:key_18{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
compatible = "shared-dma-pool";
reusable;
/* 1920x1080x2x4 =16+4 M */
- size = <0x0 0x04000000>;
+ size = <0x0 0x0>;
alignment = <0x0 0x400000>;
};
/* vdin1 CMA pool */
compatible = "shared-dma-pool";
reusable;
/* 1920x1080x2x4 =16 M */
- size = <0x0 0x04000000>;
+ size = <0x0 0x02000000>;
alignment = <0x0 0x400000>;
};
};
key_val = <143 266 389>; //val=voltage/1800mV*1023
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "okay";
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
status = "okay";
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <17>;
+ unifykey-num = <16>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-13= <&keysn_13>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
- unifykey-index-16= <&keysn_16>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_16:key_16{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <19>;
+ unifykey-num = <18>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
- unifykey-index-18= <&keysn_18>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_18:key_18{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
&efuse {
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
/*1:enabel osd lut 100 table;0:disable*/
- cfg_en_osd_100 = <1>;
+ cfg_en_osd_100 = <3>;
/*0: 709/601 1: bt2020*/
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
/*1:enabel osd lut 100 table;0:disable*/
- cfg_en_osd_100 = <1>;
+ cfg_en_osd_100 = <3>;
/*0: 709/601 1: bt2020*/
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-permit = "read","write","del";
};
keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
+ key-name = "oemkey";
+ key-device = "normal";
+ key-permit = "read","write","del";
};
keysn_18:key_18{
key-name = "attestationdevidbox";// attest dev id box
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "oemkey";
- key-device = "normal";
- key-permit = "read","write","del";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-permit = "read","write","del";
};
keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "write";
+ key-name = "oemkey";
+ key-device = "normal";
+ key-permit = "read","write","del";
};
keysn_18:key_18{
key-name = "attestationdevidbox";// attest dev id box
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "oemkey";
- key-device = "normal";
- key-permit = "read","write","del";
- };
};//End unifykey
};
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
tx_op_color_primary = <0>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
};
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
cm_en = <0>;/*1:enabel ;0:disable*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
cm_en = <0>;/*1:enabel ;0:disable*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B
storage_version = <0x8200006C>;
};
+ ddr-scrambler@0xfe02e030 {
+ compatible = "amlogic, ddr-scrambler-preserve";
+ reg = <0x0 0xfe02e030 0x0 0x4>;
+ };
+
mailbox_mhu_fifo: mhu@0 {
status = "okay";
compatible = "amlogic, meson_mhu_fifo";
cpuinfo_cmd = <0x82000044>;
};
+ soc_info {
+ compatible = "amlogic, socdata";
+ reg= <0x0 0xfe010000 0x0 0x8 0x0 0xfe010180 0x0 0x4>;
+ read_nocsdata_cmd =<0x82000039>;
+ write_nocsdata_cmd=<0x82000038>;
+ };
+
aml_reboot{
compatible = "aml, reboot";
sys_reset = <0x84000009>;
status = "disabled";
};
+ amaudio: amaudio {
+ compatible = "amlogic, amaudio";
+ reg = <0x0 0xfe440000 0x0 0x10000>;
+ reg-names = "otp_tee_base";
+ status = "okay";
+ };
+
dwc3: dwc3@fde00000 {
compatible = "synopsys, dwc3";
status = "disable";
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <14>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* refer to sc2-system-registers.docx */
- interrupts = <0 204 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 204 1
+ 0 197 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* refer to hdmi_tx_module.h */
ic_type = <15>;
vend_data: vend_data{ /* Should modified by Customer */
pinctrl-names = "sd_all_pins",
"sd_clk_cmd_pins",
- "sd_1bit_pins";
+ "sd_1bit_pins",
+ "sd_clk_cmd_uart_pins",
+ "sd_1bit_uart_pins",
+ "sd_to_ao_uart_pins",
+ "ao_to_sd_uart_pins",
+ "sd_to_ao_jtag_pins",
+ "ao_to_sd_jtag_pins",
+ "sd_all_pd_pins";
pinctrl-0 = <&sd_all_pins>;
pinctrl-1 = <&sd_clk_cmd_pins>;
pinctrl-2 = <&sd_1bit_pins>;
+ pinctrl-3 = <&sd_to_ao_uart_clr_pins
+ &sd_clk_cmd_pins &ao_to_sd_uart_pins>;
+ pinctrl-4 = <&sd_to_ao_uart_clr_pins
+ &sd_1bit_pins &ao_to_sd_uart_pins>;
+ pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>;
+ pinctrl-6 = <&sd_to_ao_uart_clr_pins
+ &ao_to_sd_uart_pins>;
+ pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>;
+ pinctrl-8 = <&sd_to_ao_uart_clr_pins
+ &ao_to_sd_uart_pins>;
+ pinctrl-9 = <&sd_all_pd_pins>;
+
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK_COMP>,
vol_switch = <&gpio GPIOD_2 GPIO_ACTIVE_HIGH>;
vol_switch_18 = <1>; /* 1 = high, 0 = low */
vol_switch_delay = <150>; /* Uint: ms*/
+ no_sduart = <1>;
card_type = <5>;
/* 3:sdio device(ie:sdio-wifi),
* 4:SD combo (IO+mem) card
dev_name = "aml_sha_dma";
status = "okay";
};
+
+ crypto {
+ compatible = "amlogic,crypto_sc2";
+ dev_name = "aml_crypto_dev";
+ status = "okay";
+ thread = /bits/ 8 <0x5>;
+ interrupts = <0 29 1>;
+ };
};
rng {
ao_to_sd_uart_pins:ao_to_sd_uart_pins {
mux {
- groups = "uart_ao_tx_a_c3",
- "uart_ao_rx_a_c2";
- function = "uart_ao_a_ee";
+ groups = "uart_b_rx_c",
+ "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
+ mux {
+ groups = "GPIOD_0",
+ "GPIOD_1";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+
+ sd_to_ao_uart_pins:sd_to_ao_uart_pins {
+ mux {
+ groups = "uart_b_rx_d",
+ "uart_b_tx_d";
+ function = "uart_b";
bias-pull-up;
input-enable;
};
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PHY>;
+ &clkc CLKID_PCIE_PHY
+ &clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
- interrupts = <0 57 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 57 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B 12:SM1
dev_name = "vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
dummy_venc: dummy_venc {
compatible = "amlogic, vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2: vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vdac {
num-lanes = <1>;
pcie-num = <1>;
- clocks = <&clkc CLKID_PCIE0_GATE
- &clkc CLKID_PCIE1
- &clkc CLKID_PCIE0PHY>;
+ clocks = <&clkc CLKID_PCIE_PLL
+ &clkc CLKID_PCIE0
+ &clkc CLKID_PCIE0PHY
+ &clkc CLKID_PCIE0_GATE>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
num-lanes = <1>;
pcie-num = <1>;
- clocks = <&clkc CLKID_PCIE1_GATE
+ clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE1
- &clkc CLKID_PCIE1PHY>;
+ &clkc CLKID_PCIE1PHY
+ &clkc CLKID_PCIE1_GATE>;
clock-names = "pcie_refpll",
"pcie",
- "pcie_phy";
+ "pcie_phy",
+ "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <30>;
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
- interrupts = <0 7 1>;
- interrupt-names = "hdmitx_hpd";
+ interrupts = <0 7 1
+ 0 3 1>;
+ interrupt-names = "hdmitx_hpd", "viu1_vsync";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
compatible = "amlogic, vout";
status = "okay";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vout2: vout2 {
clock-names = "vpu_clkc0",
"vpu_clkc";
- /* fr_policy:
- * 0: disable
- * 1: nearby (only for 60->59.94 and 30->29.97)
- * 2: force (60/50/30/24/59.94/23.97)
- */
- fr_policy = <2>;
+ fr_policy = <0>;
};
vdac {
*
*/
-#include "firmware_avb_Q.dtsi"
+#include "firmware_avb_deadpool.dtsi"
/ {
partitions: partitions{
/ {
partitions: partitions{
- parts = <15>;
+ parts = <17>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&tee>;
part-6 = <&cri_data>;
part-7 = <¶m>;
part-8 = <&boot>;
- part-9 = <&rsv>;
- part-10 = <&metadata>;
- part-11 = <&vbmeta>;
- part-12 = <&super>;
- part-13 = <&cache>;
- part-14 = <&data>;
+ part-9 = <&oem>;
+ part-10 = <&odm_ext>;
+ part-11 = <&rsv>;
+ part-12 = <&metadata>;
+ part-13 = <&vbmeta>;
+ part-14 = <&super>;
+ part-15 = <&cache>;
+ part-16 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <2>;
};
+ oem:oem{
+ pname = "oem";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext:odm_ext
+ {
+ pname = "odm_ext";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
rsv:rsv{
pname = "rsv";
size = <0x0 0x1000000>;
/ {
partitions: partitions{
- parts = <19>;
+ parts = <22>;
part-0 = <&logo>;
part-1 = <&recovery_a>;
part-2 = <&recovery_b>;
part-9 = <¶m>;
part-10 = <&boot_a>;
part-11 = <&boot_b>;
- part-12 = <&rsv>;
+ part-12 = <&oem_a>;
part-13 = <&metadata>;
- part-14 = <&rsv2>;
- part-15 = <&vbmeta_a>;
- part-16 = <&vbmeta_b>;
- part-17 = <&super>;
- part-18 = <&data>;
+ part-14 = <&oem_b>;
+ part-15 = <&odm_ext_a>;
+ part-16 = <&odm_ext_b>;
+ part-17 = <&rsv>;
+ part-18 = <&vbmeta_a>;
+ part-19 = <&vbmeta_b>;
+ part-20 = <&super>;
+ part-21 = <&userdata>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <2>;
};
- rsv:rsv{
- pname = "rsv";
+ oem_a:oem_a{
+ pname = "oem_a";
size = <0x0 0x1000000>;
mask = <1>;
};
size = <0x0 0x1000000>;
mask = <1>;
};
- rsv2:rsv2{
- pname = "rsv2";
+ oem_b:oem_b{
+ pname = "oem_b";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext_a:odm_ext_a
+ {
+ pname = "odm_ext_a";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ odm_ext_b:odm_ext_b
+ {
+ pname = "odm_ext_b";
+ size = <0x0 0x1000000>;
+ mask = <1>;
+ };
+ rsv:rsv{
+ pname = "rsv";
size = <0x0 0x1000000>;
mask = <1>;
};
size = <0x0 0xC8800000>;
mask = <1>;
};
- data:data
+ userdata:userdata
{
- pname = "data";
+ pname = "userdata";
size = <0xffffffff 0xffffffff>;
mask = <4>;
};
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x00800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x00800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x00800000>;
- };
};
cma_shrinker {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
/* mode 0~4, defalut:1 */
filter_mode = <1>;
-
+ /* lane-mask-in = <0 1 0 0>; */
train_sample_count = <0xe>;
status = "okay";
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x00800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x00800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x00800000>;
- };
};
cma_shrinker {
};
partitions: partitions{
- parts = <12>;
+ parts = <13>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&rsv>;
part-3 = <&tee>;
- part-4 = <&crypt>;
- part-5 = <&misc>;
- part-6 = <&boot>;
- part-7 = <&system>;
- part-8 = <&cache>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&data>;
+ part-4 = <&factory>;
+ part-5 = <&crypt>;
+ part-6 = <&misc>;
+ part-7 = <&boot>;
+ part-8 = <&system>;
+ part-9 = <&cache>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
crypt:crypt{
pname = "crypt";
size = <0x0 0x2000000>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x00800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x00800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x00800000>;
- };
};
cma_shrinker {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x00800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x00800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x00800000>;
- };
};
cma_shrinker {
};
partitions: partitions{
- parts = <12>;
+ parts = <13>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&rsv>;
part-3 = <&tee>;
- part-4 = <&crypt>;
- part-5 = <&misc>;
- part-6 = <&boot>;
- part-7 = <&system>;
- part-8 = <&cache>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&data>;
+ part-4 = <&factory>;
+ part-5 = <&crypt>;
+ part-6 = <&misc>;
+ part-7 = <&boot>;
+ part-8 = <&system>;
+ part-9 = <&cache>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
crypt:crypt{
pname = "crypt";
size = <0x0 0x2000000>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_mode = "external";
fe1_demod = "cxd2856";
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x00800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x00800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x00800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x00800000>;
- };
};
cma_shrinker {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x800000>;
- };
};
cma_shrinker {
status = "okay";
fe_num = <1>;
- fe0_mode = "external";
fe0_demod = "cxd2856";
fe0_i2c_adap_id = <&i2c2>;
fe0_demod_i2c_addr = <0xD8>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
/* mode 0~4, defalut:1 */
filter_mode = <1>;
-
+ /* lane-mask-in = <0 1 0 0>; */
train_sample_count = <0xe>;
status = "okay";
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x800000>;
- };
};
cma_shrinker {
};
partitions: partitions{
- parts = <12>;
+ parts = <13>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&rsv>;
part-3 = <&tee>;
- part-4 = <&crypt>;
- part-5 = <&misc>;
- part-6 = <&boot>;
- part-7 = <&system>;
- part-8 = <&cache>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&data>;
+ part-4 = <&factory>;
+ part-5 = <&crypt>;
+ part-6 = <&misc>;
+ part-7 = <&boot>;
+ part-8 = <&system>;
+ part-9 = <&cache>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
crypt:crypt{
pname = "crypt";
size = <0x0 0x2000000>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp10 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <969000>;
+ opp-microvolt = <959000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
compatible = "amlogic, tm2-revb-snd-tdmb";
#sound-dai-cells = <0>;
dai-tdm-lane-slot-mask-in = <0 1 0 0>;
- dai-tdm-lane-slot-mask-out = <1 0 0 0>;
+ dai-tdm-lane-slot-mask-out = <1 1 1 1>;
dai-tdm-clk-sel = <1>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_B
&clkaudio CLKID_AUDIO_MCLK_PAD0
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
};
+ dsp_fw_reserved:linux,dsp_fw {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x800000>;
+ alignment = <0x0 0x00400000>;
+ alloc-ranges = <0x0 0x30000000 0x0 0x800000>;
+ };
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
alignment = <0x0 0x400000>;
};
- dsp_fw_reserved:linux,dsp_fw {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x800000>;
- alignment = <0x0 0x00400000>;
- alloc-ranges = <0x0 0x3400000 0x0 0x800000>;
- };
};
cma_shrinker {
};
partitions: partitions{
- parts = <12>;
+ parts = <13>;
part-0 = <&logo>;
part-1 = <&recovery>;
part-2 = <&rsv>;
part-3 = <&tee>;
- part-4 = <&crypt>;
- part-5 = <&misc>;
- part-6 = <&boot>;
- part-7 = <&system>;
- part-8 = <&cache>;
- part-9 = <&vendor>;
- part-10 = <&odm>;
- part-11 = <&data>;
+ part-4 = <&factory>;
+ part-5 = <&crypt>;
+ part-6 = <&misc>;
+ part-7 = <&boot>;
+ part-8 = <&system>;
+ part-9 = <&cache>;
+ part-10 = <&vendor>;
+ part-11 = <&odm>;
+ part-12 = <&data>;
logo:logo{
pname = "logo";
size = <0x0 0x800000>;
mask = <1>;
};
+ factory:factory{
+ pname = "factory";
+ size = <0x0 0x800000>;
+ mask = <0x11>;
+ };
crypt:crypt{
pname = "crypt";
size = <0x0 0x2000000>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
};
opp04 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <819000>;
+ opp-microvolt = <799000>;
};
opp05 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <829000>;
+ opp-microvolt = <809000>;
};
opp06 {
opp-hz = /bits/ 64 <1404000000>;
};
opp11 {
opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1019000>;
+ opp-microvolt = <989000>;
};
opp12 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1049000>;
+ opp-microvolt = <1019000>;
};
};
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_audio {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <18>;
+ unifykey-num = <17>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-14= <&keysn_14>;
unifykey-index-15= <&keysn_15>;
unifykey-index-16= <&keysn_16>;
- unifykey-index-17= <&keysn_17>;
keysn_0: key_0{
key-name = "usid";
key-device = "secure";
key-permit = "read","write","del";
};
- keysn_17:key_17{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
+
/*
* arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
*
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
detect_mode = <0>;/*0:polling mode, 1:irq mode*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <32>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
- unifykey-index-20= <&keysn_20>;
- unifykey-index-21= <&keysn_21>;
- unifykey-index-22= <&keysn_22>;
- unifykey-index-23= <&keysn_23>;
- unifykey-index-24= <&keysn_24>;
- unifykey-index-25= <&keysn_25>;
- unifykey-index-26= <&keysn_26>;
- unifykey-index-27= <&keysn_27>;
- unifykey-index-28= <&keysn_28>;
- unifykey-index-29= <&keysn_29>;
- unifykey-index-30= <&keysn_30>;
- unifykey-index-31= <&keysn_31>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_WIDEVINE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_20:key_20{
- key-name = "KEY_PLAYREADY_PRIVATE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_21:key_21{
- key-name = "KEY_PLAYREADY_PUBLIC";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_22:key_22{
- key-name = "KEY_HDCP_TX14";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_23:key_23{
- key-name = "KEY_HDCP_TX22";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_24:key_24{
- key-name = "KEY_HDCP_RX14";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_25:key_25{
- key-name = "KEY_HDCP_RX22";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_26:key_26{
- key-name = "KEY_HDCP_RX22_FW";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_27:key_27{
- key-name = "KEY_HDCP_RX22_FW_PRIVATE";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_28:key_28{
- key-name = "KEY_KEYMASTER3";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_29:key_29{
- key-name = "PROVISION_FIELD_ID";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_30:key_30{
- key-name = "PROVISION_FIELD_PROTECT_KEY";
- key-device = "provision";
- key-permit = "read","write","del";
- };
- keysn_31:key_31{
- key-name = "KEY_KM3_ATTEST_DEV_ID_BOX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
detect_mode = <0>;/*0:polling mode, 1:irq mode*/
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
detect_mode = <0>;/*0:polling mode, 1:irq mode*/
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_reset_gpio = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
unifykey-num = <17>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_reset_gpio = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
unifykey-num = <17>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
fe0_ant_poweron_value = <0>;
fe0_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe0_ts = <0>;
+ fe0_tuner0 = <0>; /* T/C */
+ fe0_tuner1 = <1>; /* S */
fe1_demod = "cxd2856";
fe1_i2c_adap_id = <&i2c2>;
fe1_ant_poweron_value = <0>;
fe1_ant_power_gpio = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
fe1_ts = <1>;
+ fe1_tuner0 = <0>; /* T/C */
+ fe1_tuner1 = <1>; /* S */
+
+ tuner_num = <2>; /* for extern demod use tuner */
+ tuner0_name = "r836_tuner";
+ tuner1_name = "av2018_tuner";
};
demux {
key_tolerance = <40 40 40>;
};
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
unifykey{
compatible = "amlogic, unifykey";
status = "ok";
- unifykey-num = <20>;
+ unifykey-num = <19>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-16= <&keysn_16>;
unifykey-index-17= <&keysn_17>;
unifykey-index-18= <&keysn_18>;
- unifykey-index-19= <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
key-permit = "read","write","del";
};
- keysn_19:key_19{
- key-name = "KEY_PROVISION_XXX";
- key-device = "provision";
- key-permit = "read","write","del";
- };
};//End unifykey
efusekey:efusekey{
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
detect_mode = <0>;/*0:polling mode, 1:irq mode*/
};
- unifykey{
+ provisionkey {
+ compatible = "amlogic, provisionkey";
+ status = "okay";
+ key-permit-default = "write";
+ //new key not need add dts if started with KEY_PROVISION_
+ KEY_PROVISION_XXX { };
+ //test_my_added_keyname { };
+ };//End provisionkey
+
+unifykey{
compatible = "amlogic, unifykey";
status = "ok";
unifykey-num = <17>;
sound-dai = <&dummy_codec>;
};
};
+#if 0
aml-audio-card,dai-link@6 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
sound-dai = <&dummy_codec>;
};
};
-
+#if 0
aml-audio-card,dai-link@7 {
mclk-fs = <256>;
suffix-name = "alsaPORT-earc";
sound-dai = <&dummy_codec>;
};
};
-
+#endif
aml-audio-card,dai-link@8 {
mclk-fs = <256>;
continuous-clock;
}; /* end of audiobus */
&earc {
- status = "okay";
+ status = "disabled";
};
&pinctrl_periphs {
CONFIG_RFKILL=y
CONFIG_AMLOGIC_DRIVER=y
CONFIG_AMLOGIC_MODIFY=y
+CONFIG_AMLOGIC_SYNC_20210524=y
CONFIG_AMLOGIC_CPUFREQ=y
CONFIG_AMLOGIC_MESON_CPUFREQ=y
CONFIG_AMLOGIC_INPUT_BOOST=y
CONFIG_AMLOGIC_CPU_INFO=y
CONFIG_AMLOGIC_REG_ACCESS=y
CONFIG_AMLOGIC_TIMER=y
-CONFIG_AMLOGIC_BC_TIMER=y
CONFIG_AMLOGIC_CLK=y
CONFIG_AMLOGIC_COMMON_CLK_SCPI=y
CONFIG_AMLOGIC_GX_CLK=y
CONFIG_AMLOGIC_ATV_DEMOD=y
CONFIG_AMLOGIC_DEBUG=y
CONFIG_AMLOGIC_DEBUG_LOCKUP=y
+CONFIG_AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS=y
CONFIG_AMLOGIC_DEFENDKEY=y
CONFIG_AMLOGIC_BATTERY_DUMMY=y
CONFIG_AMLOGIC_CHARGER_DUMMY=y
CONFIG_AMLOGIC_PIXEL_PROBE=y
CONFIG_AMLOGIC_FIRMWARE=y
CONFIG_AMLOGIC_RESET_MESON=y
+CONFIG_AMLOGIC_SOC_INFO=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_HID_A4TECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_NINTENDO=y
+CONFIG_HID_PLAYSTATION=y
+CONFIG_PLAYSTATION_FF=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_USB_HIDDEV=y
CONFIG_USB_CONFIGFS_F_PTP=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_MMC=y
CONFIG_AMLOGIC_CPU_INFO=y
CONFIG_AMLOGIC_REG_ACCESS=y
CONFIG_AMLOGIC_TIMER=y
-CONFIG_AMLOGIC_BC_TIMER=y
CONFIG_AMLOGIC_CLK=y
CONFIG_AMLOGIC_COMMON_CLK_SCPI=y
CONFIG_AMLOGIC_GX_CLK=y
if (!access_ok(VERIFY_READ, (void *)addr, nbytes))
return;
+#ifdef CONFIG_AMLOGIC_MODIFY
+ /*
+ * Treating data in general purpose register as an address
+ * and dereferencing it is quite a dangerous behaviour,
+ * especially when it belongs to secure monotor region or
+ * ioremap region(for arm64 vmalloc region is already filtered
+ * out), which can lead to external abort on non-linefetch and
+ * can not be protected by probe_kernel_address.
+ * We need more strict filtering rules
+ */
+
+#ifdef CONFIG_AMLOGIC_SEC
+ /*
+ * filter out secure monitor region
+ */
+ if (within_secmon_region(addr)) {
+ pr_info("\n%s: %#lx S\n", name, addr);
+ return;
+ }
+#endif
+#endif
pr_info("\n%s: %#lx:\n", name, addr);
/*
mrs x8, mdscr_el1
mrs x9, oslsr_el1
mrs x10, sctlr_el1
+#ifdef CONFIG_AMLOGIC_MODIFY
+ mrs x11, tpidr_el1
+#else
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
mrs x11, tpidr_el1
alternative_else
mrs x11, tpidr_el2
alternative_endif
+#endif
mrs x12, sp_el0
stp x2, x3, [x0]
stp x4, xzr, [x0, #16]
msr mdscr_el1, x10
msr sctlr_el1, x12
+#ifdef CONFIG_AMLOGIC_MODIFY
+ msr tpidr_el1, x13
+#else
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
msr tpidr_el1, x13
alternative_else
msr tpidr_el2, x13
alternative_endif
+#endif
msr sp_el0, x14
/*
* Restore oslsr_el1 by writing oslar_el1
standard kernel source code. All modify of kernel
standard code should be wrapped by this config
+config AMLOGIC_SYNC_20210524
+ bool "Amlogic sync android-4.9-q 20210524"
+ default n
+ help
+ this represents sync from android-4.9-q 20210524
+
if AMLOGIC_DRIVER
menu "Amlogic Device Drivers"
source "drivers/amlogic/dvb/Kconfig"
+source "drivers/amlogic/soc_info/Kconfig"
+
endmenu
endif
obj-$(CONFIG_AMLOGIC_DVB) += dvb/
obj-$(CONFIG_AMLOGIC_DVB_DMX) += dvb/
+
+obj-$(CONFIG_AMLOGIC_SOC_INFO) += soc_info/
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
+#include <linux/of_address.h>
#include <linux/uaccess.h>
#ifdef CONFIG_COMPAT
#include <linux/compat.h>
static const char * const audio_format[] = {"PCM", "CUSTOM_1", "CUSTOM_2",
"CUSTOM_3", "DD", "AUTO"};
static int hdmi_format;
+static void __iomem *base;
+
static const struct file_operations amaudio_ctl_fops = {
.owner = THIS_MODULE,
{
unsigned int val;
- val = aml_read_aobus(0x228);
- val = (val>>14)&1;
-
+ if (!base) {
+ val = aml_read_aobus(0x228);
+ val = (val >> 14) & 1;
+ } else {
+ val = readl(base + 0x48);
+ val = (val >> 16) & 1;
+ val = !val;
+ }
return sprintf(buf, "0x%x\n", val);
}
static ssize_t dolby_enable_show(struct class *class,
struct class_attribute *attr, char *buf)
{
unsigned int val;
-
- val = aml_read_aobus(0x228);
- val = (val>>16)&1;
-
+ if (!base) {
+ val = aml_read_aobus(0x228);
+ val = (val >> 16) & 1;
+ } else {
+ val = readl(base + 0x48);
+ val = (val >> 17) & 1;
+ val = !val;
+ }
return sprintf(buf, "0x%x\n", val);
}
.class_attrs = amaudio_attrs,
};
+static int amaudio_probe(struct platform_device *pdev)
+{
+ struct resource res;
+
+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
+ pr_err("found resource failed\n");
+ return -1;
+ }
+
+ if (res.start != 0) {
+ base = ioremap_nocache(res.start, resource_size(&res));
+ if (!base) {
+ pr_err("cannot map otp_tee registers\n");
+ return -ENOMEM;
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id amlogic_amaudio_dt_match[] = {
+ { .compatible = "amlogic, amaudio",
+ },
+ {},
+};
+
+static struct platform_driver amlogic_amaudio_driver = {
+ .probe = amaudio_probe,
+ .driver = {
+ .name = "amaudio",
+ .of_match_table = amlogic_amaudio_dt_match,
+ .owner = THIS_MODULE,
+ },
+};
+
static int __init amaudio_init(void)
{
int ret = 0;
pr_info("%s - amaudio: driver %s succuess!\n",
__func__, AMAUDIO_DRIVER_NAME);
- return 0;
+ return platform_driver_register(&amlogic_amaudio_driver);
err4:
device_destroy(&amaudio_class, MKDEV(AMAUDIO_MAJOR, 10));
device_destroy(amaudio_classp, MKDEV(AMAUDIO_MAJOR, i));
class_destroy(amaudio_classp);
unregister_chrdev(AMAUDIO_MAJOR, AMAUDIO_DRIVER_NAME);
+
+ platform_driver_unregister(&amlogic_amaudio_driver);
}
module_init(amaudio_init);
.read = debugfs_read,
.write = debugfs_write,
};
-#else
-DEBUG_FS_CREATE_NODES(NULL);
-DEBUG_FS_CREATE_FILES(NULL, NULL);
#endif
int aml_atvdemod_create_debugfs(const char *name)
+++ /dev/null
-/*
- * drivers/amlogic/cec/m8_ao_cec.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/input.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/major.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/cdev.h>
-#include <asm/irq.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/spinlock_types.h>
-#include <linux/workqueue.h>
-#include <linux/timer.h>
-
-#include <linux/uaccess.h>
-#include <linux/delay.h>
-
-#include <linux/amlogic/pm.h>
-#include <linux/of.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/of_irq.h>
-#include "hdmi_ao_cec.h"
-#include <linux/notifier.h>
-#include <linux/reboot.h>
-#include <linux/of_address.h>
-#include <linux/random.h>
-#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
-#include <linux/amlogic/pm.h>
-#endif
-#include <linux/amlogic/cpu_version.h>
-#include <linux/amlogic/cec_common.h>
-#include <linux/notifier.h>
-
-#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
-
-#define DEFAULT_DEBUG_EN 0
-
-#define DBG_BUF_SIZE 80
-#define MAX_INT 0x7ffffff
-
-/* global struct for tx and rx */
-struct ao_cec_dev {
- unsigned char rx_msg[MAX_MSG];
- /* bit filed for flags */
- struct {
- unsigned char my_log_addr : 4;
- unsigned char port_num : 4; /* first bytes */
- unsigned char cec_tx_result : 2;
- unsigned char power_status : 2;
- unsigned char rx_len : 4; /* second bytes */
- #ifdef CONFIG_PM
- unsigned char cec_suspend : 2;
- #endif
- unsigned char dev_type : 3;
- unsigned char cec_version : 3; /* third bytes */
- /* remaining bool flags */
- bool new_msg : 1;
- bool phy_addr_test : 1;
- bool wake_ok : 1;
- bool cec_msg_dbg_en : 1;
- bool hal_control : 1;
- /*
- * pin_status: tv support cec check, for box
- * hpd_state: hdmi cable connected status
- *
- * hpd_state pin_status | TV support cec
- * 0 x | N/A
- * 1 0 | 0
- * 1 1 | 1
- */
- bool pin_status : 1;
- bool hpd_state : 1;
- };
-
- /* hardware config */
- unsigned short arc_port;
- unsigned short phy_addr;
- unsigned short irq_cec;
- unsigned short cec_line_cnt;
- unsigned short hal_flag;
- unsigned int port_seq;
-
- /* miscellaneous */
- unsigned int menu_lang;
- unsigned int open_count;
- dev_t dev_no;
-
- /* vendor related */
- unsigned int vendor_id;
- char *osd_name;
- char *product;
- const char *pin_name;
-
- /* resource of register */
- void __iomem *cec_reg;
-
- /* kernel resource */
- struct input_dev *remote_cec_dev;
- struct notifier_block hdmitx_nb;
- struct workqueue_struct *cec_thread;
- struct device *dbg_dev;
- struct delayed_work cec_work;
- struct completion rx_ok;
- struct completion tx_ok;
- spinlock_t cec_reg_lock;
- struct mutex cec_mutex;
- struct hrtimer start_bit_check;
-};
-
-static struct ao_cec_dev *cec_dev;
-
-#define CEC_ERR(format, args...) \
- {if (cec_dev->dbg_dev) \
- dev_err(cec_dev->dbg_dev, format, ##args); \
- }
-
-#define CEC_INFO(format, args...) \
- {if (cec_dev->cec_msg_dbg_en && cec_dev->dbg_dev) \
- dev_info(cec_dev->dbg_dev, format, ##args); \
- }
-
-
-#define waiting_aocec_free() \
- do {\
- unsigned long cnt = 0;\
- while (readl(cec_dev->cec_reg + AO_CEC_RW_REG) & (1<<23)) {\
- if (cnt++ >= 3500) { \
- pr_info("waiting aocec free time out.\n");\
- break;\
- } \
- } \
- } while (0)
-
-static void cec_set_reg_bits(unsigned int addr, unsigned int value,
- unsigned int offset, unsigned int len)
-{
- unsigned int data32 = 0;
-
- data32 = readl(cec_dev->cec_reg + addr);
- data32 &= ~(((1 << len) - 1) << offset);
- data32 |= (value & ((1 << len) - 1)) << offset;
- writel(data32, cec_dev->cec_reg + addr);
-}
-
-static unsigned int aocec_rd_reg(unsigned long addr)
-{
- unsigned int data32;
- unsigned long flags;
-
- waiting_aocec_free();
- spin_lock_irqsave(&cec_dev->cec_reg_lock, flags);
- data32 = 0;
- data32 |= 0 << 16; /* [16] cec_reg_wr */
- data32 |= 0 << 8; /* [15:8] cec_reg_wrdata */
- data32 |= addr << 0; /* [7:0] cec_reg_addr */
- writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG);
-
- waiting_aocec_free();
- data32 = ((readl(cec_dev->cec_reg + AO_CEC_RW_REG)) >> 24) & 0xff;
- spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags);
- return data32;
-} /* aocec_rd_reg */
-
-static void aocec_wr_reg(unsigned long addr, unsigned long data)
-{
- unsigned long data32;
- unsigned long flags;
-
- waiting_aocec_free();
- spin_lock_irqsave(&cec_dev->cec_reg_lock, flags);
- data32 = 0;
- data32 |= 1 << 16; /* [16] cec_reg_wr */
- data32 |= data << 8; /* [15:8] cec_reg_wrdata */
- data32 |= addr << 0; /* [7:0] cec_reg_addr */
- writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG);
- spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags);
-} /* aocec_wr_only_reg */
-
-static void cec_hw_buf_clear(void)
-{
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_DISABLE);
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
- aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
- aocec_wr_reg(CEC_TX_CLEAR_BUF, 1);
- udelay(100);
- aocec_wr_reg(CEC_RX_CLEAR_BUF, 0);
- aocec_wr_reg(CEC_TX_CLEAR_BUF, 0);
- udelay(100);
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
-}
-
-static void cec_logicaddr_set(int l_add)
-{
- /* save logical address for suspend/wake up */
- cec_set_reg_bits(AO_DEBUG_REG1, l_add, 16, 4);
- aocec_wr_reg(CEC_LOGICAL_ADDR0, 0);
- cec_hw_buf_clear();
- aocec_wr_reg(CEC_LOGICAL_ADDR0, (l_add & 0xf));
- udelay(100);
- aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | (l_add & 0xf));
- if (cec_dev->cec_msg_dbg_en)
- CEC_INFO("set logical addr:0x%x\n",
- aocec_rd_reg(CEC_LOGICAL_ADDR0));
-}
-
-static void cec_enable_irq(void)
-{
- cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3);
- CEC_INFO("enable:int mask:0x%x\n",
- readl(cec_dev->cec_reg + AO_CEC_INTR_MASKN));
-}
-
-static void cec_arbit_bit_time_set(unsigned int bit_set,
- unsigned int time_set, unsigned int flag)
-{ /* 11bit:bit[10:0] */
- if (flag) {
- CEC_INFO("bit_set:0x%x;time_set:0x%x\n",
- bit_set, time_set);
- }
-
- switch (bit_set) {
- case 3:
- /* 3 bit */
- if (flag) {
- CEC_INFO("read 3 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0));
- }
- aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT7_0, time_set & 0xff);
- aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT10_8, (time_set >> 8) & 0x7);
- if (flag) {
- CEC_INFO("write 3 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0));
- }
- break;
- /* 5 bit */
- case 5:
- if (flag) {
- CEC_INFO("read 5 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0));
- }
- aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT7_0, time_set & 0xff);
- aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT10_8, (time_set >> 8) & 0x7);
- if (flag) {
- CEC_INFO("write 5 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0));
- }
- break;
- /* 7 bit */
- case 7:
- if (flag) {
- CEC_INFO("read 7 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0));
- }
- aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT7_0, time_set & 0xff);
- aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT10_8, (time_set >> 8) & 0x7);
- if (flag) {
- CEC_INFO("write 7 bit:0x%x%x\n",
- aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8),
- aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0));
- }
- break;
- default:
- break;
- }
-}
-
-static void ceca_hw_reset(void)
-{
- writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
- /* Enable gated clock (Normal mode). */
- cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1);
- /* Release SW reset */
- udelay(100);
- cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1);
-
- /* Enable all AO_CEC interrupt sources */
- cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3);
-
- cec_logicaddr_set(cec_dev->my_log_addr);
-
- /* Cec arbitration 3/5/7 bit time set. */
- cec_arbit_bit_time_set(3, 0x118, 0);
- cec_arbit_bit_time_set(5, 0x000, 0);
- cec_arbit_bit_time_set(7, 0x2aa, 0);
-
- CEC_INFO("hw reset :logical addr:0x%x\n",
- aocec_rd_reg(CEC_LOGICAL_ADDR0));
-}
-
-static void cec_rx_buf_clear(void)
-{
- aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x1);
- aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x0);
-}
-
-static int cec_rx_buf_check(void)
-{
- unsigned int rx_num_msg;
-
- rx_num_msg = aocec_rd_reg(CEC_RX_NUM_MSG);
- if (rx_num_msg)
- CEC_INFO("rx msg num:0x%02x\n", rx_num_msg);
-
- return rx_num_msg;
-}
-
-static void format_msg_str(const char *msg, char len, char *prefix, char *buf)
-{
- int size = 0, i;
-
- size = sprintf(buf + size, "%s %2d:", prefix, len);
- for (i = 0; i < len; i++)
- size += sprintf(buf + size, " %02x", msg[i]);
- buf[size] = '\0';
- WARN_ON(size >= DBG_BUF_SIZE);
-}
-
-int cec_ll_rx(unsigned char *msg)
-{
- int i;
- int ret = -1;
- int rx_stat;
- int len;
-
- rx_stat = aocec_rd_reg(CEC_RX_MSG_STATUS);
- if ((rx_stat != RX_DONE) || (aocec_rd_reg(CEC_RX_NUM_MSG) != 1)) {
- CEC_INFO("rx status:%x\n", rx_stat);
- writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR);
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
- cec_rx_buf_clear();
- return ret;
- }
-
- len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
- cec_dev->rx_len = len;
-
- for (i = 0; i < len && i < MAX_MSG; i++)
- msg[i] = aocec_rd_reg(CEC_RX_MSG_0_HEADER + i);
-
- ret = rx_stat;
-
- if (cec_dev->cec_msg_dbg_en) {
- char buf[DBG_BUF_SIZE] = {};
-
- format_msg_str(msg, len, "CEC rx msg", buf);
- pr_info("%s\n", buf);
- }
-
- writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR);
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
- aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
- cec_rx_buf_clear();
- cec_dev->pin_status = 1;
- return ret;
-}
-
-/************************ cec arbitration cts code **************************/
-/* using the cec pin as fiq gpi to assist the bus arbitration */
-
-/* return value: 1: successful 0: error */
-static int cec_ll_trigle_tx(const unsigned char *msg, int len)
-{
- int i;
- int reg;
- unsigned int j = 40;
- unsigned int tx_stat;
- int cec_timeout_cnt = 1;
-
- while (1) {
- tx_stat = aocec_rd_reg(CEC_TX_MSG_STATUS);
- if (tx_stat != TX_BUSY)
- break;
-
- if (!(j--)) {
- CEC_INFO("waiting busy timeout\n");
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
- cec_timeout_cnt++;
- if (cec_timeout_cnt > 0x08)
- ceca_hw_reset();
- break;
- }
- msleep(20);
- }
-
- reg = aocec_rd_reg(CEC_TX_MSG_STATUS);
- if (reg == TX_IDLE || reg == TX_DONE) {
- for (i = 0; i < len; i++)
- aocec_wr_reg(CEC_TX_MSG_0_HEADER + i, msg[i]);
-
- aocec_wr_reg(CEC_TX_MSG_LENGTH, len-1);
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_REQ_CURRENT);
- if (cec_dev->cec_msg_dbg_en) {
- char buf[DBG_BUF_SIZE] = {};
-
- format_msg_str(msg, len, "CEC tx msg", buf);
- pr_info("%s\n", buf);
- }
- return 0;
- }
- return -1;
-}
-
-static void tx_irq_handle(void)
-{
- unsigned int tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
-
- switch (tx_status) {
- case TX_DONE:
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
- cec_dev->cec_tx_result = CEC_FAIL_NONE;
- break;
-
- case TX_BUSY:
- CEC_ERR("TX_BUSY\n");
- cec_dev->cec_tx_result = CEC_FAIL_BUSY;
- break;
-
- case TX_ERROR:
- if (cec_dev->cec_msg_dbg_en == 1)
- CEC_ERR("TX ERROR!!!\n");
- if (aocec_rd_reg(CEC_RX_MSG_STATUS) == RX_ERROR)
- ceca_hw_reset();
- else
- aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
- cec_dev->cec_tx_result = CEC_FAIL_NACK;
- break;
-
- case TX_IDLE:
- CEC_ERR("TX_IDLE\n");
- cec_dev->cec_tx_result = CEC_FAIL_OTHER;
- break;
- default:
- cec_dev->cec_tx_result = CEC_FAIL_OTHER;
- break;
- }
- writel((1 << 1), cec_dev->cec_reg + AO_CEC_INTR_CLR);
- complete(&cec_dev->tx_ok);
-}
-
-static int get_line(void)
-{
- int reg, cpu_type, ret = -EINVAL;
-
- reg = readl(cec_dev->cec_reg + AO_GPIO_I);
- cpu_type = get_cpu_type();
- if (cpu_type <= MESON_CPU_MAJOR_ID_GXBB)
- ret = (reg & (1 << 12));
- else
- ret = 1;
- return ret;
-}
-
-static enum hrtimer_restart cec_line_check(struct hrtimer *timer)
-{
- if (get_line() == 0)
- cec_dev->cec_line_cnt++;
- hrtimer_forward_now(timer, HR_DELAY(1));
- return HRTIMER_RESTART;
-}
-
-static int check_confilct(void)
-{
- int i;
-
- for (i = 0; i < 50; i++) {
- /*
- * sleep 20ms and using hrtimer to check cec line every 1ms
- */
- cec_dev->cec_line_cnt = 0;
- hrtimer_start(&cec_dev->start_bit_check,
- HR_DELAY(1), HRTIMER_MODE_REL);
- msleep(20);
- hrtimer_cancel(&cec_dev->start_bit_check);
- if (cec_dev->cec_line_cnt == 0)
- break;
- CEC_INFO("line busy:%d\n", cec_dev->cec_line_cnt);
- }
- if (i >= 50)
- return -EBUSY;
- else
- return 0;
-}
-
-static inline bool physical_addr_valid(void)
-{
- if (cec_dev->dev_type == DEV_TYPE_TV)
- return 1;
- if (cec_dev->phy_addr_test)
- return 1;
- if (cec_dev->phy_addr == INVALID_PHY_ADDR)
- return 0;
- return 1;
-}
-
-static int cec_hdmi_tx_notify_handler(struct notifier_block *nb,
- unsigned long value, void *p)
-{
- int ret = 0;
- int phy_addr = 0;
-
- switch (value) {
- case HDMITX_PLUG:
- cec_dev->hpd_state = 1;
- CEC_INFO("%s, HDMITX_PLUG\n", __func__);
- break;
-
- case HDMITX_UNPLUG:
- cec_dev->hpd_state = 0;
- CEC_INFO("%s, HDMITX_UNPLUG\n", __func__);
- break;
-
- case HDMITX_PHY_ADDR_VALID:
- phy_addr = *((int *)p);
- cec_dev->phy_addr = phy_addr & 0xffff;
- cec_dev->hpd_state = 1;
- CEC_INFO("%s, phy_addr %x ok\n", __func__, cec_dev->phy_addr);
- break;
-
- default:
- CEC_INFO("unsupported hdmitx notify:%ld, arg:%p\n", value, p);
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-static bool check_physical_addr_valid(int timeout)
-{
- while (timeout > 0) {
- if (!physical_addr_valid()) {
- msleep(100);
- timeout--;
- } else
- break;
- }
- if (timeout <= 0)
- return false;
- return true;
-}
-
-/* Return value: < 0: fail, > 0: success */
-int cec_ll_tx(const unsigned char *msg, unsigned char len)
-{
- int ret = -1;
- int t = msecs_to_jiffies(2000);
- int retry = 2;
-
- if (len == 0)
- return CEC_FAIL_NONE;
-
- mutex_lock(&cec_dev->cec_mutex);
- /* make sure physical address is valid before send */
- if (len >= 2 && msg[1] == CEC_OC_REPORT_PHYSICAL_ADDRESS)
- check_physical_addr_valid(20);
-
-try_again:
- reinit_completion(&cec_dev->tx_ok);
- /*
- * CEC controller won't ack message if it is going to send
- * state. If we detect cec line is low during waiting signal
- * free time, that means a send is already started by other
- * device, we should wait it finished.
- */
- if (check_confilct()) {
- CEC_ERR("bus confilct too long\n");
- mutex_unlock(&cec_dev->cec_mutex);
- return CEC_FAIL_BUSY;
- }
-
- ret = cec_ll_trigle_tx(msg, len);
- if (ret < 0) {
- /* we should increase send idx if busy */
- CEC_INFO("tx busy\n");
- if (retry > 0) {
- retry--;
- msleep(100 + (prandom_u32() & 0x07) * 10);
- goto try_again;
- }
- mutex_unlock(&cec_dev->cec_mutex);
- return CEC_FAIL_BUSY;
- }
- cec_dev->cec_tx_result = CEC_FAIL_OTHER;
- ret = wait_for_completion_timeout(&cec_dev->tx_ok, t);
- if (ret <= 0) {
- /* timeout or interrupt */
- if (ret == 0) {
- CEC_ERR("tx timeout\n");
- ceca_hw_reset();
- }
- ret = CEC_FAIL_OTHER;
- } else {
- ret = cec_dev->cec_tx_result;
- }
- if (ret != CEC_FAIL_NONE && ret != CEC_FAIL_NACK) {
- if (retry > 0) {
- retry--;
- msleep(100 + (prandom_u32() & 0x07) * 10);
- goto try_again;
- }
- }
- mutex_unlock(&cec_dev->cec_mutex);
-
- return ret;
-}
-
-/* -------------------------------------------------------------------------- */
-/* AO CEC0 config */
-/* -------------------------------------------------------------------------- */
-static void ao_cec_init(void)
-{
- unsigned long data32;
-
- data32 = 0;
- data32 |= 0 << 1; /* [2:1] cntl_clk: */
- /* 0=Disable clk (Power-off mode); */
- /* 1=Enable gated clock (Normal mode); */
- /* 2=Enable free-run clk (Debug mode). */
- data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */
- writel(data32, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
- /* Enable gated clock (Normal mode). */
- cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1);
- /* Release SW reset */
- cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1);
-
- /* Enable all AO_CEC interrupt sources */
- cec_enable_irq();
-}
-
-static unsigned int ao_cec_intr_stat(void)
-{
- return readl(cec_dev->cec_reg + AO_CEC_INTR_STAT);
-}
-
-static unsigned int cec_intr_stat(void)
-{
- return ao_cec_intr_stat();
-}
-
-/*
- *wr_flag: 1 write; value valid
- * 0 read; value invalid
- */
-static unsigned int cec_config(unsigned int value, bool wr_flag)
-{
- if (wr_flag)
- cec_set_reg_bits(AO_DEBUG_REG0, value, 0, 8);
-
- return readl(cec_dev->cec_reg + AO_DEBUG_REG0) & 0xff;
-}
-
-/*
- *wr_flag:1 write; value valid
- * 0 read; value invalid
- */
-static unsigned int cec_phyaddr_config(unsigned int value, bool wr_flag)
-{
- if (wr_flag)
- cec_set_reg_bits(AO_DEBUG_REG1, value, 0, 16);
-
- return readl(cec_dev->cec_reg + AO_DEBUG_REG1);
-}
-
-static void cec_keep_reset(void)
-{
- writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
-}
-/*
- * cec hw module init before allocate logical address
- */
-static void cec_pre_init(void)
-{
- unsigned int reg = readl(cec_dev->cec_reg + AO_RTI_STATUS_REG1);
-
- ao_cec_init();
-
- cec_arbit_bit_time_set(3, 0x118, 0);
- cec_arbit_bit_time_set(5, 0x000, 0);
- cec_arbit_bit_time_set(7, 0x2aa, 0);
- reg &= 0xfffff;
- if ((reg & 0xffff) == 0xffff)
- cec_dev->wake_ok = 0;
- pr_info("cec: wake up flag:%x\n", reg);
-}
-
-static int cec_late_check_rx_buffer(void)
-{
- int ret;
- struct delayed_work *dwork = &cec_dev->cec_work;
-
- ret = cec_rx_buf_check();
- if (!ret)
- return 0;
- /*
- * start another check if rx buffer is full
- */
- if ((-1) == cec_ll_rx(cec_dev->rx_msg)) {
- CEC_INFO("buffer got unrecorgnized msg\n");
- cec_rx_buf_clear();
- ret = 0;
- } else {
- mod_delayed_work(cec_dev->cec_thread, dwork, 0);
- ret = 1;
- }
- return ret;
-}
-
-static void cec_key_report(int suspend)
-{
- input_event(cec_dev->remote_cec_dev, EV_KEY, KEY_POWER, 1);
- input_sync(cec_dev->remote_cec_dev);
- input_event(cec_dev->remote_cec_dev, EV_KEY, KEY_POWER, 0);
- input_sync(cec_dev->remote_cec_dev);
- pm_wakeup_event(cec_dev->dbg_dev, 2000);
- if (!suspend)
- CEC_INFO("== WAKE UP BY CEC ==\n")
- else
- CEC_INFO("== SLEEP by CEC==\n")
-}
-
-static void cec_give_version(unsigned int dest)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char msg[3];
-
- if (dest != 0xf) {
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_CEC_VERSION;
- msg[2] = cec_dev->cec_version;
- cec_ll_tx(msg, 3);
- }
-}
-
-static void cec_report_physical_address_smp(void)
-{
- unsigned char msg[5];
- unsigned char index = cec_dev->my_log_addr;
- unsigned char phy_addr_ab, phy_addr_cd;
-
- phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
- phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
- msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
- msg[1] = CEC_OC_REPORT_PHYSICAL_ADDRESS;
- msg[2] = phy_addr_ab;
- msg[3] = phy_addr_cd;
- msg[4] = cec_dev->dev_type;
-
- cec_ll_tx(msg, 5);
-}
-
-static void cec_device_vendor_id(void)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char msg[5];
- unsigned int vendor_id;
-
- vendor_id = cec_dev->vendor_id;
- msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
- msg[1] = CEC_OC_DEVICE_VENDOR_ID;
- msg[2] = (vendor_id >> 16) & 0xff;
- msg[3] = (vendor_id >> 8) & 0xff;
- msg[4] = (vendor_id >> 0) & 0xff;
-
- cec_ll_tx(msg, 5);
-}
-
-static void cec_give_deck_status(unsigned int dest)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char msg[3];
-
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_DECK_STATUS;
- msg[2] = 0x1a;
- cec_ll_tx(msg, 3);
-}
-
-static void cec_menu_status_smp(int dest, int status)
-{
- unsigned char msg[3];
- unsigned char index = cec_dev->my_log_addr;
-
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_MENU_STATUS;
- if (status == DEVICE_MENU_ACTIVE)
- msg[2] = DEVICE_MENU_ACTIVE;
- else
- msg[2] = DEVICE_MENU_INACTIVE;
- cec_ll_tx(msg, 3);
-}
-
-static void cec_inactive_source(int dest)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char msg[4];
- unsigned char phy_addr_ab, phy_addr_cd;
-
- phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
- phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_INACTIVE_SOURCE;
- msg[2] = phy_addr_ab;
- msg[3] = phy_addr_cd;
-
- cec_ll_tx(msg, 4);
-}
-
-static void cec_set_osd_name(int dest)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char osd_len = strlen(cec_dev->osd_name);
- unsigned char msg[16];
-
- if (dest != 0xf) {
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_SET_OSD_NAME;
- memcpy(&msg[2], cec_dev->osd_name, osd_len);
-
- cec_ll_tx(msg, 2 + osd_len);
- }
-}
-
-static void cec_active_source_smp(void)
-{
- unsigned char msg[4];
- unsigned char index = cec_dev->my_log_addr;
- unsigned char phy_addr_ab;
- unsigned char phy_addr_cd;
-
- phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
- phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
- msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
- msg[1] = CEC_OC_ACTIVE_SOURCE;
- msg[2] = phy_addr_ab;
- msg[3] = phy_addr_cd;
- cec_ll_tx(msg, 4);
-}
-
-static void cec_request_active_source(void)
-{
- unsigned char msg[2];
- unsigned char index = cec_dev->my_log_addr;
-
- msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
- msg[1] = CEC_OC_REQUEST_ACTIVE_SOURCE;
- cec_ll_tx(msg, 2);
-}
-
-static void cec_set_stream_path(unsigned char *msg)
-{
- unsigned int phy_addr_active;
-
- phy_addr_active = (unsigned int)(msg[2] << 8 | msg[3]);
- if (phy_addr_active == cec_dev->phy_addr) {
- cec_active_source_smp();
- /*
- * some types of TV such as panasonic need to send menu status,
- * otherwise it will not send remote key event to control
- * device's menu
- */
- cec_menu_status_smp(msg[0] >> 4, DEVICE_MENU_ACTIVE);
- }
-}
-
-static void cec_report_power_status(int dest, int status)
-{
- unsigned char index = cec_dev->my_log_addr;
- unsigned char msg[3];
-
- msg[0] = ((index & 0xf) << 4) | dest;
- msg[1] = CEC_OC_REPORT_POWER_STATUS;
- msg[2] = status;
- cec_ll_tx(msg, 3);
-}
-
-static void cec_rx_process(void)
-{
- int len = cec_dev->rx_len;
- int initiator, follower;
- int opcode;
- unsigned char msg[MAX_MSG] = {};
- int dest_phy_addr;
-
- if (len < 2 || !cec_dev->new_msg) /* ignore ping message */
- return;
-
- memcpy(msg, cec_dev->rx_msg, len);
- initiator = ((msg[0] >> 4) & 0xf);
- follower = msg[0] & 0xf;
- if (follower != 0xf && follower != cec_dev->my_log_addr) {
- CEC_ERR("wrong rx message of bad follower:%x", follower);
- return;
- }
- opcode = msg[1];
- switch (opcode) {
- case CEC_OC_ACTIVE_SOURCE:
- if (cec_dev->wake_ok == 0) {
- int phy_addr = msg[2] << 8 | msg[3];
-
- if (phy_addr == INVALID_PHY_ADDR)
- break;
- cec_dev->wake_ok = 1;
- phy_addr |= (initiator << 16);
- writel(phy_addr, cec_dev->cec_reg + AO_RTI_STATUS_REG1);
- CEC_INFO("found wake up source:%x", phy_addr);
- }
- break;
-
- case CEC_OC_ROUTING_CHANGE:
- dest_phy_addr = msg[4] << 8 | msg[5];
- if (dest_phy_addr == cec_dev->phy_addr) {
- CEC_INFO("wake up by ROUTING_CHANGE\n");
- cec_key_report(0);
- }
- break;
-
- case CEC_OC_GET_CEC_VERSION:
- cec_give_version(initiator);
- break;
-
- case CEC_OC_GIVE_DECK_STATUS:
- cec_give_deck_status(initiator);
- break;
-
- case CEC_OC_GIVE_PHYSICAL_ADDRESS:
- cec_report_physical_address_smp();
- break;
-
- case CEC_OC_GIVE_DEVICE_VENDOR_ID:
- cec_device_vendor_id();
- break;
-
- case CEC_OC_GIVE_OSD_NAME:
- cec_set_osd_name(initiator);
- break;
-
- case CEC_OC_STANDBY:
- cec_inactive_source(initiator);
- cec_menu_status_smp(initiator, DEVICE_MENU_INACTIVE);
- break;
-
- case CEC_OC_SET_STREAM_PATH:
- cec_set_stream_path(msg);
- /* wake up if in early suspend */
- if (cec_dev->cec_suspend == CEC_EARLY_SUSPEND)
- cec_key_report(0);
- break;
-
- case CEC_OC_REQUEST_ACTIVE_SOURCE:
- if (!cec_dev->cec_suspend)
- cec_active_source_smp();
- break;
-
- case CEC_OC_GIVE_DEVICE_POWER_STATUS:
- if (cec_dev->cec_suspend)
- cec_report_power_status(initiator, POWER_STANDBY);
- else
- cec_report_power_status(initiator, POWER_ON);
- break;
-
- case CEC_OC_USER_CONTROL_PRESSED:
- /* wake up by key function */
- if (cec_dev->cec_suspend == CEC_EARLY_SUSPEND) {
- if (msg[2] == 0x40 || msg[2] == 0x6d)
- cec_key_report(0);
- }
- break;
-
- case CEC_OC_MENU_REQUEST:
- if (cec_dev->cec_suspend)
- cec_menu_status_smp(initiator, DEVICE_MENU_INACTIVE);
- else
- cec_menu_status_smp(initiator, DEVICE_MENU_ACTIVE);
- break;
-
- default:
- CEC_ERR("unsupported command:%x\n", opcode);
- break;
- }
- cec_dev->new_msg = 0;
-}
-
-static bool cec_service_suspended(void)
-{
- /* service is not enabled */
- if (!(cec_dev->hal_flag & (1 << HDMI_OPTION_SERVICE_FLAG)))
- return false;
- if (!(cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL)))
- return true;
- return false;
-}
-
-static void cec_task(struct work_struct *work)
-{
- struct delayed_work *dwork;
-
- dwork = &cec_dev->cec_work;
- if (cec_dev && (!cec_dev->wake_ok || cec_service_suspended()))
- cec_rx_process();
-
- if (!cec_late_check_rx_buffer())
- queue_delayed_work(cec_dev->cec_thread, dwork, CEC_FRAME_DELAY);
-}
-
-static irqreturn_t cec_isr_handler(int irq, void *dev_instance)
-{
- unsigned int intr_stat = 0;
- struct delayed_work *dwork;
-
- dwork = &cec_dev->cec_work;
- intr_stat = cec_intr_stat();
- if (intr_stat & (1<<1)) { /* aocec tx intr */
- tx_irq_handle();
- return IRQ_HANDLED;
- }
- if ((-1) == cec_ll_rx(cec_dev->rx_msg))
- return IRQ_HANDLED;
-
- complete(&cec_dev->rx_ok);
- /* check rx buffer is full */
- cec_dev->new_msg = 1;
- mod_delayed_work(cec_dev->cec_thread, dwork, 0);
- return IRQ_HANDLED;
-}
-
-static void check_wake_up(void)
-{
- if (cec_dev->wake_ok == 0)
- cec_request_active_source();
-}
-
-/******************** cec class interface *************************/
-static ssize_t device_type_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", cec_dev->dev_type);
-}
-
-static ssize_t device_type_store(struct class *cla,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- unsigned long type;
-
- if (kstrtol(buf, 10, &type))
- return -EINVAL;
-
- cec_dev->dev_type = type;
- CEC_ERR("set dev_type to %ld\n", type);
- return count;
-}
-
-static ssize_t menu_language_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- char a, b, c;
-
- a = ((cec_dev->menu_lang >> 16) & 0xff);
- b = ((cec_dev->menu_lang >> 8) & 0xff);
- c = ((cec_dev->menu_lang >> 0) & 0xff);
- return sprintf(buf, "%c%c%c\n", a, b, c);
-}
-
-static ssize_t menu_language_store(struct class *cla,
- struct class_attribute *attr, const char *buf, size_t count)
-{
- char a, b, c;
-
- if (sscanf(buf, "%c%c%c", &a, &b, &c) != 3)
- return -EINVAL;
-
- cec_dev->menu_lang = (a << 16) | (b << 8) | c;
- CEC_ERR("set menu_language to %s\n", buf);
- return count;
-}
-
-static ssize_t vendor_id_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%x\n", cec_dev->vendor_id);
-}
-
-static ssize_t vendor_id_store(struct class *cla, struct class_attribute *attr,
- const char *buf, size_t count)
-{
- int id;
-
- if (kstrtoint(buf, 16, &id))
- return -EINVAL;
- cec_dev->vendor_id = id;
- return count;
-}
-
-static ssize_t port_num_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", cec_dev->port_num);
-}
-
-static const char * const cec_reg_name1[] = {
- "CEC_TX_MSG_LENGTH",
- "CEC_TX_MSG_CMD",
- "CEC_TX_WRITE_BUF",
- "CEC_TX_CLEAR_BUF",
- "CEC_RX_MSG_CMD",
- "CEC_RX_CLEAR_BUF",
- "CEC_LOGICAL_ADDR0",
- "CEC_LOGICAL_ADDR1",
- "CEC_LOGICAL_ADDR2",
- "CEC_LOGICAL_ADDR3",
- "CEC_LOGICAL_ADDR4",
- "CEC_CLOCK_DIV_H",
- "CEC_CLOCK_DIV_L"
-};
-
-static const char * const cec_reg_name2[] = {
- "CEC_RX_MSG_LENGTH",
- "CEC_RX_MSG_STATUS",
- "CEC_RX_NUM_MSG",
- "CEC_TX_MSG_STATUS",
- "CEC_TX_NUM_MSG"
-};
-
-static ssize_t dump_reg_show(struct class *cla,
- struct class_attribute *attr, char *b)
-{
- int i, s = 0;
-
- s += sprintf(b + s, "TX buffer:\n");
- for (i = 0; i <= CEC_TX_MSG_F_OP14; i++)
- s += sprintf(b + s, "%2d:%2x\n", i, aocec_rd_reg(i));
-
- for (i = 0; i < ARRAY_SIZE(cec_reg_name1); i++) {
- s += sprintf(b + s, "%s:%2x\n",
- cec_reg_name1[i], aocec_rd_reg(i + 0x10));
- }
-
- s += sprintf(b + s, "RX buffer:\n");
- for (i = 0; i <= CEC_TX_MSG_F_OP14; i++)
- s += sprintf(b + s, "%2d:%2x\n", i, aocec_rd_reg(i + 0x80));
-
- for (i = 0; i < ARRAY_SIZE(cec_reg_name2); i++) {
- s += sprintf(b + s, "%s:%2x\n",
- cec_reg_name2[i], aocec_rd_reg(i + 0x90));
- }
- return s;
-}
-
-static ssize_t arc_port_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%x\n", cec_dev->arc_port);
-}
-
-static ssize_t osd_name_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%s\n", cec_dev->osd_name);
-}
-
-static ssize_t port_seq_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%x\n", cec_dev->port_seq);
-}
-
-static ssize_t port_status_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- unsigned int tmp;
- unsigned int tx_hpd;
-
- tx_hpd = cec_dev->hpd_state;
- if (cec_dev->dev_type == DEV_TYPE_PLAYBACK) {
- tmp = tx_hpd;
- return sprintf(buf, "%x\n", tmp);
- }
-
- tmp = hdmirx_rd_top(TOP_HPD_PWR5V);
- CEC_INFO("TOP_HPD_PWR5V:%x\n", tmp);
- tmp >>= 20;
- tmp &= 0xf;
- tmp |= (tx_hpd << 16);
- return sprintf(buf, "%x\n", tmp);
-}
-
-static ssize_t pin_status_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- unsigned int tx_hpd = 0;
- char p;
-
- tx_hpd = cec_dev->hpd_state;
- if (cec_dev->dev_type == DEV_TYPE_PLAYBACK) {
- if (!tx_hpd) {
- cec_dev->pin_status = 0;
- return sprintf(buf, "%s\n", "disconnected");
- }
- if (cec_dev->pin_status == 0) {
- p = (cec_dev->my_log_addr << 4) | CEC_TV_ADDR;
- if (cec_ll_tx(&p, 1) == CEC_FAIL_NONE)
- return sprintf(buf, "%s\n", "ok");
- else
- return sprintf(buf, "%s\n", "fail");
- } else
- return sprintf(buf, "%s\n", "ok");
- } else {
- return sprintf(buf, "%s\n",
- cec_dev->pin_status ? "ok" : "fail");
- }
-}
-
-static ssize_t physical_addr_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- unsigned int tmp = cec_dev->phy_addr;
-
- return sprintf(buf, "%04x\n", tmp);
-}
-
-static ssize_t physical_addr_store(struct class *cla,
- struct class_attribute *attr,
- const char *buf, size_t count)
-{
- int addr;
-
- if (kstrtoint(buf, 16, &addr))
- return -EINVAL;
-
- if (addr > INVALID_PHY_ADDR || addr < 0) {
- CEC_ERR("invalid input:%s\n", buf);
- cec_dev->phy_addr_test = 0;
- return -EINVAL;
- }
- cec_dev->phy_addr = addr;
- cec_dev->phy_addr_test = 1;
- return count;
-}
-
-static ssize_t dbg_en_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "%x\n", cec_dev->cec_msg_dbg_en);
-}
-
-static ssize_t dbg_en_store(struct class *cla, struct class_attribute *attr,
- const char *buf, size_t count)
-{
- int en;
-
- if (kstrtoint(buf, 10, &en))
- return -EINVAL;
-
- cec_dev->cec_msg_dbg_en = en ? 1 : 0;
- return count;
-}
-
-static ssize_t cmd_store(struct class *cla, struct class_attribute *attr,
- const char *bu, size_t count)
-{
- char buf[16] = {};
- int cnt;
-
- cnt = sscanf(bu, "%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
- (int *)&buf[0], (int *)&buf[1], (int *)&buf[2],
- (int *)&buf[3], (int *)&buf[4], (int *)&buf[5],
- (int *)&buf[6], (int *)&buf[7], (int *)&buf[8],
- (int *)&buf[9], (int *)&buf[10], (int *)&buf[11],
- (int *)&buf[12], (int *)&buf[13], (int *)&buf[14],
- (int *)&buf[15]);
- if (cnt < 0)
- return -EINVAL;
- cec_ll_tx(buf, cnt);
- return count;
-}
-
-static ssize_t wake_up_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- unsigned int reg = readl(cec_dev->cec_reg + AO_RTI_STATUS_REG1);
-
- return sprintf(buf, "%x\n", reg & 0xfffff);
-}
-
-static ssize_t fun_cfg_store(struct class *cla, struct class_attribute *attr,
- const char *bu, size_t count)
-{
- int cnt, val;
-
- cnt = kstrtoint(bu, 16, &val);
- if (cnt < 0 || val > 0xff)
- return -EINVAL;
- cec_config(val, 1);
- if (val == 0)
- cec_keep_reset();
- else
- cec_pre_init();
- return count;
-}
-
-static ssize_t fun_cfg_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- unsigned int reg = cec_config(0, 0);
-
- return sprintf(buf, "0x%x\n", reg & 0xff);
-}
-
-static ssize_t log_addr_store(struct class *cla, struct class_attribute *attr,
- const char *bu, size_t count)
-{
- int cnt, val;
-
- cnt = kstrtoint(bu, 16, &val);
- if (cnt < 0 || val > 0xf)
- return -EINVAL;
- cec_logicaddr_set(val);
- /* add by hal, to init some data structure */
- cec_dev->my_log_addr = val;
- cec_dev->power_status = POWER_ON;
-
- return count;
-}
-
-static ssize_t log_addr_show(struct class *cla,
- struct class_attribute *attr, char *buf)
-{
- return sprintf(buf, "0x%x\n", cec_dev->my_log_addr);
-}
-
-static struct class_attribute aocec_class_attr[] = {
- __ATTR_WO(cmd),
- __ATTR_RO(port_num),
- __ATTR_RO(port_seq),
- __ATTR_RO(osd_name),
- __ATTR_RO(dump_reg),
- __ATTR_RO(port_status),
- __ATTR_RO(pin_status),
- __ATTR_RO(arc_port),
- __ATTR_RO(wake_up),
- __ATTR(physical_addr, 0664, physical_addr_show, physical_addr_store),
- __ATTR(vendor_id, 0664, vendor_id_show, vendor_id_store),
- __ATTR(menu_language, 0664, menu_language_show, menu_language_store),
- __ATTR(device_type, 0664, device_type_show, device_type_store),
- __ATTR(dbg_en, 0664, dbg_en_show, dbg_en_store),
- __ATTR(fun_cfg, 0664, fun_cfg_show, fun_cfg_store),
- __ATTR(log_addr, 0664, log_addr_show, log_addr_store),
- __ATTR_NULL
-};
-
-/******************** cec hal interface ***************************/
-static int hdmitx_cec_open(struct inode *inode, struct file *file)
-{
- cec_dev->open_count++;
- if (cec_dev->open_count) {
- cec_dev->hal_control = 1;
- /* set default logical addr flag for uboot */
- cec_set_reg_bits(AO_DEBUG_REG1, 0xf, 16, 4);
- }
- return 0;
-}
-
-static int hdmitx_cec_release(struct inode *inode, struct file *file)
-{
- cec_dev->open_count--;
- if (!cec_dev->open_count)
- cec_dev->hal_control = 0;
- return 0;
-}
-
-static ssize_t hdmitx_cec_read(struct file *f, char __user *buf,
- size_t size, loff_t *p)
-{
- int ret;
-
- if ((cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL)))
- cec_dev->rx_len = 0;
- ret = wait_for_completion_timeout(&cec_dev->rx_ok, CEC_FRAME_DELAY);
- if (ret <= 0)
- return ret;
- if (cec_dev->rx_len == 0)
- return 0;
-
- if (copy_to_user(buf, cec_dev->rx_msg, cec_dev->rx_len))
- return -EINVAL;
- return cec_dev->rx_len;
-}
-
-static ssize_t hdmitx_cec_write(struct file *f, const char __user *buf,
- size_t size, loff_t *p)
-{
- unsigned char tempbuf[16] = {};
- int ret;
-
- if (size > 16)
- size = 16;
- if (size <= 0)
- return -EINVAL;
-
- if (copy_from_user(tempbuf, buf, size))
- return -EINVAL;
-
- ret = cec_ll_tx(tempbuf, size);
- return ret;
-}
-
-static void init_cec_port_info(struct hdmi_port_info *port,
- struct ao_cec_dev *cec_dev)
-{
- unsigned int a, b, c;
- unsigned int phy_head = 0xf000, phy_app = 0x1000, phy_addr;
-
- /* physical address for TV or repeator */
- if (cec_dev->dev_type == DEV_TYPE_TV)
- phy_addr = 0;
- else if (cec_dev->phy_addr != INVALID_PHY_ADDR)
- phy_addr = cec_dev->phy_addr;
- else
- phy_addr = 0;
-
- /* found physical address append for repeator */
- for (a = 0; a < 4; a++) {
- if (phy_addr & phy_head) {
- phy_head >>= 4;
- phy_app >>= 4;
- } else
- break;
- }
- if (cec_dev->dev_type == DEV_TYPE_TUNER)
- b = cec_dev->port_num - 1;
- else
- b = cec_dev->port_num;
-
- /* init for port info */
- for (a = 0; a < b; a++) {
- port[a].type = HDMI_INPUT;
- port[a].port_id = a + 1;
- port[a].cec_supported = 1;
- /* set ARC feature according mask */
- if (cec_dev->arc_port & (1 << a))
- port[a].arc_supported = 1;
- else
- port[a].arc_supported = 0;
-
- /* set port physical address according port sequence */
- if (cec_dev->port_seq) {
- c = (cec_dev->port_seq >> (4 * a)) & 0xf;
- port[a].physical_address = (c + 1) * phy_app + phy_addr;
- } else {
- /* asending order if port_seq is not set */
- port[a].physical_address = (a + 1) * phy_app + phy_addr;
- }
- }
-
- if (cec_dev->dev_type == DEV_TYPE_TUNER) {
- /* last port is for tx in mixed tx/rx */
- port[a].type = HDMI_OUTPUT;
- port[a].port_id = a + 1;
- port[a].cec_supported = 1;
- port[a].arc_supported = 0;
- port[a].physical_address = phy_addr;
- }
-}
-
-static long hdmitx_cec_ioctl(struct file *f,
- unsigned int cmd, unsigned long arg)
-{
- void __user *argp = (void __user *)arg;
- unsigned long tmp = 0, i;
- struct hdmi_port_info *port;
- int tx_hpd = 0;
-
- switch (cmd) {
- case CEC_IOC_GET_PHYSICAL_ADDR:
- check_physical_addr_valid(20);
- if (cec_dev->dev_type == DEV_TYPE_PLAYBACK &&
- !cec_dev->phy_addr_test) {
- /* physical address for mbox */
- if (cec_dev->phy_addr == INVALID_PHY_ADDR)
- return -EINVAL;
- tmp = cec_dev->phy_addr;
- } else {
- if (cec_dev->dev_type == DEV_TYPE_TV)
- tmp = 0;
- /* for repeator */
- else if (cec_dev->phy_addr != INVALID_PHY_ADDR)
- tmp = cec_dev->phy_addr;
- else
- tmp = 0;
- }
- if (!cec_dev->phy_addr_test) {
- cec_dev->phy_addr = tmp;
- cec_phyaddr_config(tmp, 1);
- } else
- tmp = cec_dev->phy_addr;
-
- if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd)))
- return -EINVAL;
- break;
-
- case CEC_IOC_GET_VERSION:
- tmp = cec_dev->cec_version;
- if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd)))
- return -EINVAL;
- break;
-
- case CEC_IOC_GET_VENDOR_ID:
- tmp = cec_dev->vendor_id;
- if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd)))
- return -EINVAL;
- break;
-
- case CEC_IOC_GET_PORT_NUM:
- tmp = cec_dev->port_num;
- if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd)))
- return -EINVAL;
- break;
-
- case CEC_IOC_GET_PORT_INFO:
- port = kcalloc(cec_dev->port_num, sizeof(*port), GFP_KERNEL);
- if (!port) {
- CEC_ERR("no memory\n");
- return -EINVAL;
- }
- if (cec_dev->dev_type == DEV_TYPE_PLAYBACK) {
- /* for tx only 1 port */
- tmp = cec_dev->phy_addr;
- port->type = HDMI_OUTPUT;
- port->port_id = 1;
- port->cec_supported = 1;
- /* not support arc for tx */
- port->arc_supported = 0;
- port->physical_address = tmp & INVALID_PHY_ADDR;
- if (copy_to_user(argp, port, sizeof(*port))) {
- kfree(port);
- return -EINVAL;
- }
- } else {
- tmp = cec_dev->port_num;
- init_cec_port_info(port, cec_dev);
- if (copy_to_user(argp, port, sizeof(*port) * tmp)) {
- kfree(port);
- return -EINVAL;
- }
- }
- kfree(port);
- break;
-
- case CEC_IOC_SET_OPTION_WAKEUP:
- tmp = cec_config(0, 0);
- tmp &= ~(1 << AUTO_POWER_ON_MASK);
- tmp |= (arg << AUTO_POWER_ON_MASK);
- cec_config(tmp, 1);
- break;
-
- case CEC_IOC_SET_AUTO_DEVICE_OFF:
- tmp = cec_config(0, 0);
- tmp &= ~(1 << ONE_TOUCH_STANDBY_MASK);
- tmp |= (arg << ONE_TOUCH_STANDBY_MASK);
- cec_config(tmp, 1);
- break;
-
- case CEC_IOC_SET_OPTION_ENALBE_CEC:
- tmp = (1 << HDMI_OPTION_ENABLE_CEC);
- if (arg) {
- cec_dev->hal_flag |= tmp;
- cec_config(0x2f, 1);
- cec_pre_init();
- } else {
- cec_dev->hal_flag &= ~(tmp);
- CEC_INFO("disable CEC\n");
- cec_config(0x0, 1);
- cec_keep_reset();
- }
- break;
-
- case CEC_IOC_SET_OPTION_SYS_CTRL:
- tmp = (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL);
- if (arg) {
- cec_dev->hal_flag |= tmp;
- cec_config(0x2f, 1);
- } else
- cec_dev->hal_flag &= ~(tmp);
- cec_dev->hal_flag |= (1 << HDMI_OPTION_SERVICE_FLAG);
- break;
-
- case CEC_IOC_SET_OPTION_SET_LANG:
- cec_dev->menu_lang = arg;
- break;
-
- case CEC_IOC_GET_CONNECT_STATUS:
- tx_hpd = cec_dev->hpd_state;
- if (cec_dev->dev_type == DEV_TYPE_PLAYBACK)
- tmp = tx_hpd;
- else {
- if (copy_from_user(&i, argp, _IOC_SIZE(cmd)))
- return -EINVAL;
- if (cec_dev->port_num == i &&
- cec_dev->dev_type == DEV_TYPE_TUNER)
- tmp = tx_hpd;
- else { /* mixed for rx */
- tmp = (hdmirx_rd_top(TOP_HPD_PWR5V) >> 20);
- if (tmp & (1 << (i - 1)))
- tmp = 1;
- else
- tmp = 0;
- }
- }
- if (copy_to_user(argp, &tmp, _IOC_SIZE(cmd)))
- return -EINVAL;
- break;
-
- case CEC_IOC_ADD_LOGICAL_ADDR:
- tmp = arg & 0xf;
- cec_logicaddr_set(tmp);
- /* add by hal, to init some data structure */
- cec_dev->my_log_addr = tmp;
- if (cec_dev->dev_type != DEV_TYPE_PLAYBACK)
- check_wake_up();
- break;
-
- case CEC_IOC_CLR_LOGICAL_ADDR:
- /* TODO: clear global info */
- break;
-
- case CEC_IOC_SET_DEV_TYPE:
- if (arg < DEV_TYPE_TV && arg > DEV_TYPE_VIDEO_PROCESSOR)
- return -EINVAL;
- cec_dev->dev_type = arg;
- break;
-
- case CEC_IOC_SET_ARC_ENABLE:
- /* select arc according arg */
- if (arg)
- hdmirx_wr_top(TOP_ARCTX_CNTL, 0x03);
- else
- hdmirx_wr_top(TOP_ARCTX_CNTL, 0x00);
- CEC_INFO("set arc en:%ld, reg:%lx\n",
- arg, hdmirx_rd_top(TOP_ARCTX_CNTL));
- break;
-
- default:
- break;
- }
- return 0;
-}
-
-#ifdef CONFIG_COMPAT
-static long hdmitx_cec_compat_ioctl(struct file *f,
- unsigned int cmd, unsigned long arg)
-{
- arg = (unsigned long)compat_ptr(arg);
- return hdmitx_cec_ioctl(f, cmd, arg);
-}
-#endif
-
-/* for improve rw permission */
-static char *aml_cec_class_devnode(struct device *dev, umode_t *mode)
-{
- if (mode)
- *mode = 0666;
- CEC_INFO("mode is %x\n", *mode);
- return NULL;
-}
-
-static struct class aocec_class = {
- .name = CEC_DEV_NAME,
- .class_attrs = aocec_class_attr,
- .devnode = aml_cec_class_devnode,
-};
-
-
-static const struct file_operations hdmitx_cec_fops = {
- .owner = THIS_MODULE,
- .open = hdmitx_cec_open,
- .read = hdmitx_cec_read,
- .write = hdmitx_cec_write,
- .release = hdmitx_cec_release,
- .unlocked_ioctl = hdmitx_cec_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = hdmitx_cec_compat_ioctl,
-#endif
-};
-
-/************************ cec high level code *****************************/
-#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
-struct early_suspend aocec_suspend_handler;
-static void aocec_early_suspend(struct early_suspend *h)
-{
- cec_dev->cec_suspend = CEC_EARLY_SUSPEND;
- CEC_INFO("%s, suspend:%d\n", __func__, cec_dev->cec_suspend);
-}
-
-static void aocec_late_resume(struct early_suspend *h)
-{
- cec_dev->cec_suspend = 0;
- CEC_INFO("%s, suspend:%d\n", __func__, cec_dev->cec_suspend);
-
-}
-#endif
-
-static int aml_cec_probe(struct platform_device *pdev)
-{
- struct device *cdev;
-#ifdef CONFIG_OF
- struct device_node *node = pdev->dev.of_node;
- unsigned int tmp;
- int irq_idx = 0, r, num;
- const char *irq_name = NULL;
- struct pinctrl *p;
- struct resource *res;
- resource_size_t *base;
-#endif
-
- cec_dev = kzalloc(sizeof(struct ao_cec_dev), GFP_KERNEL);
- if (!cec_dev)
- return -ENOMEM;
- cec_dev->cec_msg_dbg_en = DEFAULT_DEBUG_EN;
- cec_dev->dev_type = DEV_TYPE_PLAYBACK;
- cec_dev->dbg_dev = &pdev->dev;
- cec_dev->wake_ok = 1;
- cec_dev->phy_addr = INVALID_PHY_ADDR;
-
- /* cdev registe */
- r = class_register(&aocec_class);
- if (r) {
- CEC_ERR("regist class failed\n");
- return -EINVAL;
- }
- pdev->dev.class = &aocec_class;
- cec_dev->dev_no = register_chrdev(0, CEC_DEV_NAME,
- &hdmitx_cec_fops);
- if (cec_dev->dev_no < 0) {
- CEC_ERR("alloc chrdev failed\n");
- return -EINVAL;
- }
- CEC_INFO("alloc chrdev %x\n", cec_dev->dev_no);
- cdev = device_create(&aocec_class, &pdev->dev,
- MKDEV(cec_dev->dev_no, 0),
- NULL, CEC_DEV_NAME);
- if (IS_ERR(cdev)) {
- CEC_ERR("create chrdev failed, dev:%p\n", cdev);
- unregister_chrdev(cec_dev->dev_no,
- CEC_DEV_NAME);
- return -EINVAL;
- }
-
- init_completion(&cec_dev->rx_ok);
- init_completion(&cec_dev->tx_ok);
- mutex_init(&cec_dev->cec_mutex);
- spin_lock_init(&cec_dev->cec_reg_lock);
- cec_dev->cec_thread = create_workqueue("cec_work");
- if (cec_dev->cec_thread == NULL) {
- CEC_INFO("create work queue failed\n");
- return -EFAULT;
- }
- INIT_DELAYED_WORK(&cec_dev->cec_work, cec_task);
- cec_dev->remote_cec_dev = input_allocate_device();
- if (!cec_dev->remote_cec_dev)
- CEC_INFO("No enough memory\n");
-
- cec_dev->remote_cec_dev->name = "cec_input";
-
- cec_dev->remote_cec_dev->evbit[0] = BIT_MASK(EV_KEY);
- cec_dev->remote_cec_dev->keybit[BIT_WORD(BTN_0)] =
- BIT_MASK(BTN_0);
- cec_dev->remote_cec_dev->id.bustype = BUS_ISA;
- cec_dev->remote_cec_dev->id.vendor = 0x1b8e;
- cec_dev->remote_cec_dev->id.product = 0x0cec;
- cec_dev->remote_cec_dev->id.version = 0x0001;
-
- set_bit(KEY_POWER, cec_dev->remote_cec_dev->keybit);
-
- if (input_register_device(cec_dev->remote_cec_dev)) {
- CEC_INFO("Failed to register device\n");
- input_free_device(cec_dev->remote_cec_dev);
- }
-
-#ifdef CONFIG_OF
- /* pinmux set */
- if (of_get_property(node, "pinctrl-names", NULL)) {
- r = of_property_read_string(node,
- "pinctrl-names",
- &cec_dev->pin_name);
- if (!r)
- p = devm_pinctrl_get_select(&pdev->dev,
- cec_dev->pin_name);
- }
-
- /* irq set */
- irq_idx = of_irq_get(node, 0);
- cec_dev->irq_cec = irq_idx;
- if (of_get_property(node, "interrupt-names", NULL)) {
- r = of_property_read_string(node, "interrupt-names", &irq_name);
- if (!r) {
- r = request_irq(irq_idx, &cec_isr_handler, IRQF_SHARED,
- irq_name, (void *)cec_dev);
- }
- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res) {
- base = ioremap(res->start, res->end - res->start);
- cec_dev->cec_reg = (void *)base;
- } else {
- CEC_ERR("no CEC reg resource\n");
- cec_dev->cec_reg = NULL;
- }
-
- r = of_property_read_u32(node, "port_num", &num);
- if (r) {
- CEC_ERR("not find 'port_num'\n");
- cec_dev->port_num = 1;
- } else
- cec_dev->port_num = num;
- r = of_property_read_u32(node, "arc_port_mask", &num);
- if (r) {
- CEC_ERR("not find 'arc_port_mask'\n");
- cec_dev->arc_port = 0;
- } else
- cec_dev->arc_port = num;
-
- r = of_property_read_u32(node, "vendor_id", &(cec_dev->vendor_id));
- if (r)
- CEC_INFO("not find vendor id\n");
-
- r = of_property_read_string(node, "cec_osd_string",
- (const char **)&(cec_dev->osd_name));
- if (r) {
- CEC_INFO("not find cec osd string\n");
- cec_dev->osd_name = "Amlogic";
- }
-
- r = of_property_read_u32(node, "cec_version",
- &(tmp));
- if (r) {
- /* default set to 2.0 */
- CEC_INFO("not find cec_version\n");
- cec_dev->cec_version = CEC_VERSION_20;
- } else
- cec_dev->cec_version = tmp;
-
- /* get port sequence */
- node = of_find_node_by_path("/hdmirx");
- if (node == NULL) {
- CEC_ERR("can't find hdmirx\n");
- cec_dev->port_seq = 0;
- } else {
- r = of_property_read_u32(node, "rx_port_maps",
- &(cec_dev->port_seq));
- if (r)
- CEC_INFO("not find rx_port_maps\n");
- }
-#endif
-
-#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
- aocec_suspend_handler.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
- aocec_suspend_handler.suspend = aocec_early_suspend;
- aocec_suspend_handler.resume = aocec_late_resume;
- aocec_suspend_handler.param = cec_dev;
- register_early_suspend(&aocec_suspend_handler);
-#endif
- device_init_wakeup(cec_dev->dbg_dev, 1);
-
- hrtimer_init(&cec_dev->start_bit_check,
- CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- cec_dev->start_bit_check.function = cec_line_check;
- cec_dev->hdmitx_nb.notifier_call = cec_hdmi_tx_notify_handler;
- hdmitx_event_notifier_regist(&cec_dev->hdmitx_nb);
- /* for init */
- cec_pre_init();
- queue_delayed_work(cec_dev->cec_thread, &cec_dev->cec_work, 0);
- return 0;
-}
-
-static __exit int aml_cec_remove(struct platform_device *pdev)
-{
- CEC_INFO("cec uninit!\n");
- free_irq(cec_dev->irq_cec, (void *)cec_dev);
-
- hdmitx_event_notifier_unregist(&cec_dev->hdmitx_nb);
- if (cec_dev->cec_thread) {
- cancel_delayed_work_sync(&cec_dev->cec_work);
- destroy_workqueue(cec_dev->cec_thread);
- }
- input_unregister_device(cec_dev->remote_cec_dev);
- unregister_chrdev(cec_dev->dev_no, CEC_DEV_NAME);
- class_unregister(&aocec_class);
- kfree(cec_dev);
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int aml_cec_pm_prepare(struct device *dev)
-{
- cec_dev->cec_suspend = CEC_DEEP_SUSPEND;
- CEC_INFO("%s, cec_suspend:%d\n", __func__, cec_dev->cec_suspend);
- return 0;
-}
-static const struct dev_pm_ops aml_cec_pm = {
- .prepare = aml_cec_pm_prepare,
-};
-#endif
-
-#ifdef CONFIG_OF
-static const struct of_device_id aml_cec_dt_match[] = {
- {
- .compatible = "amlogic, amlogic-aocec",
- },
- {},
-};
-#endif
-
-static struct platform_driver aml_cec_driver = {
- .driver = {
- .name = "cectx",
- .owner = THIS_MODULE,
- #ifdef CONFIG_PM
- .pm = &aml_cec_pm,
- #endif
- #ifdef CONFIG_OF
- .of_match_table = aml_cec_dt_match,
- #endif
- },
- .probe = aml_cec_probe,
- .remove = aml_cec_remove,
-};
-
-static int __init cec_init(void)
-{
- int ret;
-
- ret = platform_driver_register(&aml_cec_driver);
- return ret;
-}
-
-static void __exit cec_uninit(void)
-{
- platform_driver_unregister(&aml_cec_driver);
-}
-
-
-module_init(cec_init);
-module_exit(cec_uninit);
-MODULE_DESCRIPTION("AMLOGIC HDMI TX CEC driver");
-MODULE_LICENSE("GPL");
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_HIFI_PLL_CNTL1,
+ .shift = 0,
+ .width = 19,
+ },
.rate_table = g12a_hifi_pll_rate_table,
.rate_count = ARRAY_SIZE(g12a_hifi_pll_rate_table),
.lock = &clk_lock,
},
};
+static struct clk_gate g12a_pcie_hcsl = {
+ .reg = (void *)HHI_PCIE_PLL_CNTL5,
+ .bit_idx = 3,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_hcsl",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "pcie_pll" },
+ .num_parents = 1,
+ .flags = (CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
+ },
+};
+
static struct clk_fixed_factor g12a_fclk_div2 = {
.mult = 1,
.div = 2,
[CLKID_GEN_CLK_SEL] = &g12a_gen_clk_sel.hw,
[CLKID_GEN_CLK_DIV] = &g12a_gen_clk_div.hw,
[CLKID_GEN_CLK] = &g12a_gen_clk.hw,
+ [CLKID_PCIE_HCSL] = &g12a_pcie_hcsl.hw,
};
/* Convenience tables to populate base addresses in .probe */
&g12a_24m,
&g12a_12m_gate,
&g12a_gen_clk,
+ &g12a_pcie_hcsl
};
static int g12a_cpu_clk_notifier_cb(struct notifier_block *nb,
#define HHI_PCIE_PLL_CNTL0 0x98 /* 0x26 offset in data sheet */
#define HHI_PCIE_PLL_CNTL1 0x9c /* 0x27 offset in data sheet */
+#define HHI_PCIE_PLL_CNTL5 0xac /* 0x2b offset in data sheet */
#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
//#define HHI_PCIE_PLL_CNTL6 0xf0 /* 0x3c offset in data sheet */
#define HHI_HIFI_PLL_CNTL0 0xD8 /* 0x36 offset in data sheet */
+#define HHI_HIFI_PLL_CNTL1 0xDc /* 0x36 offset in data sheet */
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
/*PCIE clk_out = 24M*m/2/2/OD*/
static const struct pll_rate_table g12a_pcie_pll_rate_table[] = {
- PLL_RATE(100000000, 150, 0, 9),
+ PLL_RATE(100000000, 100, 1, 9),
{ /* sentinel */ },
};
static const struct pll_rate_table g12a_hifi_pll_rate_table[] = {
- PLL_RATE(666000000ULL, 222, 1, 3), /*DCO=5328M*/
+ PLL_RATE(589824000ULL, 196, 1, 3), /*DCO=4718.592M*/
};
#endif /* __G12A_H */
#define G12A_PCIE_PLL_CNTL3 0x10058e00
#define G12A_PCIE_PLL_CNTL4 0x000100c0
#define G12A_PCIE_PLL_CNTL4_ 0x008100c0
-#define G12A_PCIE_PLL_CNTL5 0x68000048
-#define G12A_PCIE_PLL_CNTL5_ 0x68000068
+#define G12A_PCIE_PLL_CNTL5 0x68000040
+#define G12A_PCIE_PLL_CNTL5_ 0x68000060
#define G12A_SYS_PLL_CNTL1 0x00000000
#define G12A_SYS_PLL_CNTL2 0x00000000
#define G12A_GP0_PLL_CNTL4 0x33771290
#define G12A_GP0_PLL_CNTL5 0x39272000
-#define G12A_HIFI_PLL_CNTL1 0x00000000
+#define G12A_HIFI_PLL_CNTL1 0x0001374c
#define G12A_HIFI_PLL_CNTL2 0x00000000
#define G12A_HIFI_PLL_CNTL3 0x6a285c00
#define G12A_HIFI_PLL_CNTL4 0x65771290
+++ /dev/null
-/*
- * drivers/amlogic/clk/rstc.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/reset-controller.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-
-/*
- * Modules and submodules within the chip can be reset by disabling the
- * clock and enabling it again.
- * The modules in the AO (Always-On) domain are controlled by a different
- * register mapped in a different memory region accessed by the ao_base.
- *
- */
-#define BITS_PER_REG 32
-
-struct meson_rstc {
- struct reset_controller_dev rcdev;
- void __iomem *membase;
- spinlock_t lock;
-};
-
-static int meson_rstc_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct meson_rstc *rstc = container_of(rcdev,
- struct meson_rstc,
- rcdev);
- int bank = id / BITS_PER_REG;
- int offset = id % BITS_PER_REG;
- void __iomem *rstc_mem;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&rstc->lock, flags);
-
- rstc_mem = rstc->membase + (bank << 2);
- reg = readl(rstc_mem);
- writel(reg & ~BIT(offset), rstc_mem);
- spin_unlock_irqrestore(&rstc->lock, flags);
-
- return 0;
-}
-
-static int meson_rstc_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct meson_rstc *rstc = container_of(rcdev,
- struct meson_rstc,
- rcdev);
- int bank = id / BITS_PER_REG;
- int offset = id % BITS_PER_REG;
- void __iomem *rstc_mem;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&rstc->lock, flags);
-
- rstc_mem = rstc->membase + (bank << 2);
- reg = readl(rstc_mem);
- writel(reg | BIT(offset), rstc_mem);
- spin_unlock_irqrestore(&rstc->lock, flags);
-
- return 0;
-
-}
-
-static int meson_rstc_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- int err;
-
- err = meson_rstc_assert(rcdev, id);
- if (err)
- return err;
-
- return meson_rstc_deassert(rcdev, id);
-}
-
-static struct reset_control_ops meson_rstc_ops = {
- .assert = meson_rstc_assert,
- .deassert = meson_rstc_deassert,
- .reset = meson_rstc_reset,
-};
-
-static int meson_reset_probe(struct platform_device *pdev)
-{
- struct meson_rstc *rstc;
- struct resource *res;
- int ret;
-
- rstc = devm_kzalloc(&pdev->dev, sizeof(*rstc), GFP_KERNEL);
- if (!rstc)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rstc->membase = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(rstc->membase))
- return PTR_ERR(rstc->membase);
-
- spin_lock_init(&rstc->lock);
-
- rstc->rcdev.owner = THIS_MODULE;
- rstc->rcdev.nr_resets = resource_size(res) * BITS_PER_REG;
- rstc->rcdev.of_node = pdev->dev.of_node;
- rstc->rcdev.ops = &meson_rstc_ops;
-
- ret = reset_controller_register(&rstc->rcdev);
- if (ret) {
- dev_err(&pdev->dev, "%s: could not register reset controller: %d\n",
- __func__, ret);
- }
-
- dev_info(&pdev->dev, "%s: register reset controller ok,ret: %d\n",
- __func__, ret);
- return ret;
-}
-static const struct of_device_id meson_reset_dt_ids[] = {
- { .compatible = "amlogic,reset", },
- { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
-
-static struct platform_driver meson_reset_driver = {
- .probe = meson_reset_probe,
- .driver = {
- .name = "meson_reset",
- .of_match_table = meson_reset_dt_ids,
- },
-};
-
-module_platform_driver(meson_reset_driver);
-
-MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
-MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
-MODULE_LICENSE("GPL");
},
};
+static struct clk_gate sc2_pcie_hcsl = {
+ .reg = (void *)ANACTRL_PCIEPLL_CTRL5,
+ .bit_idx = 3,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_hcsl",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "pcie_pll" },
+ .num_parents = 1,
+ .flags = (CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
+ },
+};
+
static struct clk_fixed_factor sc2_fclk_div2 = {
.mult = 1,
.div = 2,
[CLKID_GP1_PLL] = &sc2_gp1_pll.hw,
[CLKID_HIFI_PLL] = &sc2_hifi_pll.hw,
[CLKID_PCIE_PLL] = &sc2_pcie_pll.hw,
+ [CLKID_PCIE_HCSL] = &sc2_pcie_hcsl.hw,
[CLKID_FCLK_DIV2] = &sc2_fclk_div2.hw,
[CLKID_FCLK_DIV3] = &sc2_fclk_div3.hw,
[CLKID_FCLK_DIV4] = &sc2_fclk_div4.hw,
for (i = 0; i < ARRAY_SIZE(sc2_clk_mplls); i++)
sc2_clk_mplls[i]->base = pll_base;
+ sc2_pcie_hcsl.reg = pll_base + (unsigned long)sc2_pcie_hcsl.reg;
+
/* Populate the base address for CPU clk */
sc2_cpu_fclk_p.reg = cpu_clk_base + (unsigned long)sc2_cpu_fclk_p.reg;
sc2_cpu_clk.reg = cpu_clk_base + (unsigned long)sc2_cpu_clk.reg;
/*PCIE clk_out = 24M*m/2/2/OD*/
static const struct pll_rate_table sc2_pcie_pll_rate_table[] = {
- PLL_RATE(100000000, 150, 0, 9),
+ PLL_RATE(100000000, 200, 1, 12),
{ /* sentinel */ }
};
#define SC2_PCIE_PLL_CNTL2 0x00001100
#define SC2_PCIE_PLL_CNTL3 0x10058e00
#define SC2_PCIE_PLL_CNTL4 0x000100c0
-#define SC2_PCIE_PLL_CNTL5 0x68000048
-#define SC2_PCIE_PLL_CNTL5_ 0x68000068
+#define SC2_PCIE_PLL_CNTL5 0x68000040
+#define SC2_PCIE_PLL_CNTL5_ 0x68000060
#define SC2_PCIE_PLL_CNTL4_ 0x008100c0
#define SC2_PCIE_PLL_CNTL0_2 0x340c04c8
#define SC2_PCIE_PLL_CNTL0_3 0x140c04c8
u32 reg = 0x8000000, reg1 = 0;
unsigned long flags = 0;
void *cntlbase;
+ int i = 10;
+retry:
/*pr_info("%s: %d, %s\n", __func__, __LINE__, clk_hw_get_name(hw));*/
if (parent_rate == 0 || rate == 0)
return -EINVAL;
cntlbase + (unsigned long)(5 * 4));
writel(SC2_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5 * 4));
- udelay(20);
+ udelay(20 + 10 * i);
writel(SC2_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4 * 4));
- udelay(100);
+ udelay(100 + 5 * i);
/*set pcie_apll_afc_start bit*/
writel(SC2_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0 * 4));
goto OUT;
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
writel(reg, cntlbase);
- udelay(20);
+ udelay(20 + 10 * i);
writel(reg | MESON_PLL_ENABLE | MESON_PLL_RESET, cntlbase);
+ udelay(10 + 10 * i);
writel(SC2_GP0_PLL_CNTL1,
cntlbase + (unsigned long)(1 * 4));
writel(SC2_GP0_PLL_CNTL2,
cntlbase + (unsigned long)(5 * 4));
writel(SC2_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
- udelay(10);
+ udelay(80 + 10 * i);
writel(reg | MESON_PLL_ENABLE, cntlbase);
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel(reg, cntlbase);
- udelay(20);
+ udelay(20 + 10 * i);
writel(reg | MESON_PLL_ENABLE | MESON_PLL_RESET, cntlbase);
if (!reg1)
writel(SC2_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(5 * 4));
writel(SC2_PLL_CNTL6,
cntlbase + (unsigned long)(6 * 4));
- udelay(10);
+ udelay(80 + 10 * i);
writel(reg | MESON_PLL_ENABLE, cntlbase);
} else {
pr_err("%s: %s pll not found!!!\n",
if (ret) {
pr_info("%s: %s pll did not lock, trying to lock rate %lu again\n",
__func__, clk_hw_get_name(hw), rate);
- meson_sc2_pll_set_rate(hw, rate, parent_rate);
+ if (i--)
+ goto retry;
}
return ret;
int ret = 0;
unsigned long flags = 0;
struct arm_smccc_res res;
+ int i = 10;
- if (parent_rate == 0 || rate == 0)
- return -EINVAL;
if (!strcmp(clk_hw_get_name(hw), "sys_pll"))
rate *= 1000;
+retry:
+ if (parent_rate == 0 || rate == 0)
+ return -EINVAL;
+
p = &pll->n;
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
return -EINVAL;
}
/* waiting for 10us to rewrite */
- udelay(10);
+ udelay(10 + 5 * i);
if (!strcmp(clk_hw_get_name(hw), "sys_pll"))
arm_smccc_smc(CLK_SECURE_RW, SYS_PLL_STEP1,
arm_smccc_smc(CLK_SECURE_RW, GP1_PLL_STEP1,
0, 0, 0, 0, 0, 0, &res);
- udelay(20);
+ udelay(20 + 5 * i);
ret = meson_sc2_pll_wait_lock(pll, p);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
if (ret) {
pr_info("%s: %s did not lock, trying to lock rate %lu again\n",
__func__, clk_hw_get_name(hw), rate);
- meson_sc2_secure_pll_set_rate(hw, rate, parent_rate);
+ if (i--)
+ goto retry;
}
return ret;
}
#define TM2_PCIE_PLL_CNTL0_2 0x3c0c0464
#define TM2_PCIE_PLL_CNTL0_3 0x1c0c0464
#define TM2_PCIE_PLL_CNTL0_4 0x140c04c8
-#define TM2_PCIE_PLL_CNTL1 0x30000000
+#define TM2_PCIE_PLL_CNTL1 0x20000000
#define TM2_PCIE_PLL_CNTL2 0x00001100
#define TM2_PCIE_PLL_CNTL2_ 0x00001000
#define TM2_PCIE_PLL_CNTL3 0x10058e00
#define TM2_PCIE_PLL_CNTL4 0x000100c0
#define TM2_PCIE_PLL_CNTL4_ 0x008100c0
-#define TM2_PCIE_PLL_CNTL5 0x68000048
-#define TM2_PCIE_PLL_CNTL5_ 0x68000068
+#define TM2_PCIE_PLL_CNTL5 0x68000040
+#define TM2_PCIE_PLL_CNTL5_ 0x68000060
#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
obj-$(CONFIG_AMLOGIC_CRYPTO_DMA) += aml-aes-dma.o
obj-$(CONFIG_AMLOGIC_CRYPTO_DMA) += aml-tdes-dma.o
obj-$(CONFIG_AMLOGIC_CRYPTO_DMA) += aml-sha-dma.o
+obj-$(CONFIG_AMLOGIC_CRYPTO_DMA) += aml-crypto-device.o
obj-$(CONFIG_AMLOGIC_CRYPTO_BLKMV) += aml-aes-blkmv.o
obj-$(CONFIG_AMLOGIC_CRYPTO_BLKMV) += aml-tdes-blkmv.o
obj-$(CONFIG_AMLOGIC_CRYPTO_BLKMV) += aml-crypto-blkmv.o
.cra_priority = 200,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
- .cra_blocksize = 1,
+ .cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct aml_aes_ctx),
.cra_alignmask = 0xf,
.cra_type = &crypto_ablkcipher_type,
.cra_priority = 100,
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
- .cra_blocksize = 1,
+ .cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct aml_aes_ctx),
.cra_alignmask = 0xf,
.cra_type = &crypto_ablkcipher_type,
return; /* DMA started. Not fininishing. */
}
+ if (dd->ctx->kte < 0)
+ err = set_aes_key_iv(dd, NULL, 0, NULL, 0);
+
aml_aes_finish_req(dd, err);
aml_aes_handle_queue(dd, NULL);
}
--- /dev/null
+/*
+ * drivers/amlogic/crypto/aml-crypto-device.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/* A part of the code is taken from crypto dev
+ * https://github.com/cryptodev-linux/cryptodev-linux.git
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/random.h>
+#include <linux/crypto.h>
+#include <crypto/aes.h>
+#include <crypto/des.h>
+#include <linux/miscdevice.h>
+#include <linux/of_platform.h>
+#include <linux/aml_crypto.h>
+#include "aml-crypto-dma.h"
+
+#define USE_BUSY_POLLING (0)
+
+#define TEST_PHYSICAL_PROCESS (0)
+#if TEST_PHYSICAL_PROCESS
+dma_addr_t g_src_dma[MAX_CRYPTO_BUFFERS];
+u8 *g_src[MAX_CRYPTO_BUFFERS];
+u8 *g_tmp_src_addr[MAX_CRYPTO_BUFFERS];
+dma_addr_t g_dst_dma[MAX_CRYPTO_BUFFERS];
+u8 *g_dst[MAX_CRYPTO_BUFFERS];
+u8 *g_tmp_dst_addr[MAX_CRYPTO_BUFFERS];
+#endif
+
+struct aml_crypto_dev {
+ struct device *dev;
+ int irq;
+ u32 err;
+ u32 dma_busy;
+ struct mutex lock; /* lock to protect crypto device */
+
+ u32 thread;
+ u32 status;
+
+ wait_queue_head_t waiter;
+ struct task_struct *processing;
+};
+
+struct aml_crypto_dev *crypto_dd;
+
+struct meson_crypto_dev_data {
+ u32 status;
+};
+
+struct meson_crypto_dev_data meson_sc2_data = {
+ .status = TXLX_DMA_STS0,
+};
+
+struct cipher_data {
+ int init; /* 0 if uninitialized */
+ int cipher;
+ int blocksize;
+ int ivsize;
+ int kte;
+ int keylen;
+ int op_mode;
+ int crypt_mode;
+};
+
+struct crypto_session {
+ struct list_head entry;
+ struct mutex sem; /* lock to protect crypto session */
+ u32 sid;
+ struct cipher_data cdata;
+};
+
+struct fcrypt {
+ struct list_head list;
+ struct mutex sem; /* lock to protect fcrypt list */
+};
+
+struct crypt_priv {
+ struct fcrypt fcrypt;
+};
+
+#ifdef CONFIG_COMPAT
+struct compat_crypt_mem {
+ __u32 length;
+ compat_uptr_t addr;
+};
+
+struct compat_crypt_op {
+ __u32 ses; /* session identifier */
+ __u8 op; /* OP_ENCRYPT or OP_DECRYPT */
+ __u8 src_phys; /* set if src is in physical addr */
+ __u8 dst_phys; /* set if dst is in physical addr */
+ __u8 ivlen; /* length of IV */
+ compat_uptr_t __user iv;
+ __u8 num_src_bufs;
+ __u8 num_dst_bufs;
+ __u16 reserved; /* reserved */
+ struct compat_crypt_mem src[MAX_CRYPTO_BUFFERS]; /* source data */
+ struct compat_crypt_mem dst[MAX_CRYPTO_BUFFERS]; /* output data */
+};
+
+#define DO_CRYPTO_COMPAT _IOWR('a', 2, struct compat_crypt_op)
+#endif
+
+struct kernel_crypt_op {
+ struct crypt_op cop;
+
+ int ivlen;
+ __u8 iv[16];
+};
+
+#if !USE_BUSY_POLLING
+static irqreturn_t aml_crypto_dev_irq(int irq, void *dev_id)
+{
+ struct aml_crypto_dev *dd = dev_id;
+ struct device *dev = dd->dev;
+ u8 status = aml_read_crypto_reg(dd->status);
+
+ if (status) {
+ if (status == 0x1)
+ dev_err(dev, "irq overwrite\n");
+ if (dd->dma_busy) {
+ if (status & DMA_STATUS_KEY_ERROR) {
+ dev_err(dev, "crypto device failed to fetch key\n");
+ dd->err = DMA_STATUS_KEY_ERROR;
+ } else {
+ dd->err = 0;
+ }
+ aml_write_crypto_reg(dd->status, 0xf);
+ wake_up_process(dd->processing);
+ return IRQ_HANDLED;
+ } else {
+ return IRQ_NONE;
+ }
+ }
+
+ return IRQ_NONE;
+}
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id aml_crypto_dev_dt_match[] = {
+ { .compatible = "amlogic,crypto_sc2",
+ .data = &meson_sc2_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, aml_crypto_dev_dt_match);
+#else
+#define aml_crypto_dev_dt_match NULL
+#endif
+
+static int crypto_create_session(struct fcrypt *fcr, struct session_op *sop)
+{
+ struct crypto_session *ses_new = NULL;
+ struct crypto_session *ses_ptr = NULL;
+ u32 retry = 0;
+ int done = 0;
+ int rc = 0;
+
+ if (sop->cipher >= CRYPTO_OP_MAX || sop->cipher == CRYPTO_OP_INVALID)
+ return -EINVAL;
+ if (sop->keylen > AES_MAX_KEY_SIZE)
+ return -EINVAL;
+
+ ses_new = kzalloc(sizeof(*ses_new), GFP_KERNEL);
+ if (!ses_new)
+ return -ENOMEM;
+
+ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid));
+ mutex_init(&ses_new->sem);
+
+ ses_new->cdata.cipher = sop->cipher;
+ switch (ses_new->cdata.cipher) {
+ case CRYPTO_OP_DES_ECB:
+ ses_new->cdata.op_mode = OP_MODE_ECB;
+ break;
+ case CRYPTO_OP_DES_CBC:
+ ses_new->cdata.op_mode = OP_MODE_CBC;
+ break;
+ case CRYPTO_OP_TDES_ECB:
+ ses_new->cdata.op_mode = OP_MODE_ECB;
+ break;
+ case CRYPTO_OP_TDES_CBC:
+ ses_new->cdata.op_mode = OP_MODE_CBC;
+ break;
+ case CRYPTO_OP_AES_ECB:
+ ses_new->cdata.op_mode = OP_MODE_ECB;
+ break;
+ case CRYPTO_OP_AES_CBC:
+ ses_new->cdata.op_mode = OP_MODE_CBC;
+ break;
+ case CRYPTO_OP_AES_CTR: /* fall through */
+ ses_new->cdata.op_mode = OP_MODE_CTR;
+ break;
+ default:
+ goto error;
+ }
+
+ switch (ses_new->cdata.cipher) {
+ case CRYPTO_OP_DES_ECB: /* fall through */
+ case CRYPTO_OP_DES_CBC:
+ ses_new->cdata.blocksize = DES_BLOCK_SIZE;
+ ses_new->cdata.ivsize = DES_BLOCK_SIZE;
+ if (sop->keylen != DES_BLOCK_SIZE) {
+ dbgp(2, "invalid keysize: %d\n", sop->keylen);
+ goto error;
+ } else {
+ ses_new->cdata.keylen = sop->keylen;
+ }
+ ses_new->cdata.crypt_mode = MODE_DES;
+ break;
+ case CRYPTO_OP_TDES_ECB: /* fall through */
+ case CRYPTO_OP_TDES_CBC:
+ ses_new->cdata.blocksize = DES_BLOCK_SIZE;
+ ses_new->cdata.ivsize = DES_BLOCK_SIZE;
+ if (sop->keylen != DES_BLOCK_SIZE * 2 &&
+ sop->keylen != DES_BLOCK_SIZE * 3) {
+ dbgp(2, "invalid keysize: %d\n", sop->keylen);
+ goto error;
+ } else {
+ ses_new->cdata.keylen = sop->keylen;
+ }
+ ses_new->cdata.crypt_mode =
+ (ses_new->cdata.keylen == DES_BLOCK_SIZE * 2) ?
+ MODE_TDES_2K : MODE_TDES_3K;
+ break;
+ case CRYPTO_OP_AES_ECB: /* fall through */
+ case CRYPTO_OP_AES_CBC: /* fall through */
+ case CRYPTO_OP_AES_CTR: /* fall through */
+ ses_new->cdata.blocksize = AES_BLOCK_SIZE;
+ ses_new->cdata.ivsize = AES_BLOCK_SIZE;
+ /* HW only supports AES-128 and AES-256 */
+ if (sop->keylen != AES_BLOCK_SIZE &&
+ sop->keylen != AES_BLOCK_SIZE * 2) {
+ dbgp(2, "invalid keysize: %d\n", sop->keylen);
+ goto error;
+ } else {
+ ses_new->cdata.keylen = sop->keylen;
+ }
+ ses_new->cdata.crypt_mode = (ses_new->cdata.keylen ==
+ AES_BLOCK_SIZE) ? MODE_AES128 :
+ MODE_AES256;
+ break;
+ default:
+ goto error;
+ }
+ ses_new->cdata.kte = sop->kte;
+ ses_new->cdata.init = 1;
+
+ mutex_lock(&fcr->sem);
+
+ do {
+ list_for_each_entry(ses_ptr, &fcr->list, entry) {
+ /* Check for duplicate SID */
+ if (unlikely(ses_new->sid == ses_ptr->sid)) {
+ get_random_bytes(&ses_new->sid,
+ sizeof(ses_new->sid));
+ retry++;
+ break;
+ }
+ }
+ done = 1;
+ } while (retry < 20 && !done);
+
+ if (!done) {
+ dbgp(2, "failed to find a good session ID\n");
+ rc = -EINVAL;
+ }
+
+ list_add(&ses_new->entry, &fcr->list);
+ mutex_unlock(&fcr->sem);
+
+ /* Fill in some values for the user. */
+ sop->ses = ses_new->sid;
+ return 0;
+
+error:
+ kfree(ses_new);
+ return rc;
+}
+
+static int crypto_finish_session(struct fcrypt *fcr, u32 sid)
+{
+ struct crypto_session *tmp, *ses_ptr;
+ struct list_head *head;
+ int ret = 0;
+
+ mutex_lock(&fcr->sem);
+ head = &fcr->list;
+ list_for_each_entry_safe(ses_ptr, tmp, head, entry) {
+ if (ses_ptr->sid == sid) {
+ list_del(&ses_ptr->entry);
+ mutex_destroy(&ses_ptr->sem);
+ kfree(ses_ptr);
+ break;
+ }
+ }
+
+ if (unlikely(!ses_ptr)) {
+ dbgp(2, "Session with sid=0x%08X not found!", sid);
+ ret = -EINVAL;
+ }
+ mutex_unlock(&fcr->sem);
+
+ return ret;
+}
+
+static inline void crypto_put_session(struct crypto_session *ses_ptr)
+{
+ mutex_unlock(&ses_ptr->sem);
+}
+
+/* Look up session by session ID. The returned session is locked. */
+struct crypto_session *crypto_get_session_by_sid(struct fcrypt *fcr,
+ u32 sid)
+{
+ struct crypto_session *ses_ptr, *retval = NULL;
+
+ if (unlikely(!fcr))
+ return NULL;
+
+ mutex_lock(&fcr->sem);
+ list_for_each_entry(ses_ptr, &fcr->list, entry) {
+ if (ses_ptr->sid == sid) {
+ mutex_lock(&ses_ptr->sem);
+ retval = ses_ptr;
+ break;
+ }
+ }
+ mutex_unlock(&fcr->sem);
+
+ return retval;
+}
+
+static int fill_kcop_from_cop(struct kernel_crypt_op *kcop, struct fcrypt *fcr)
+{
+ struct crypt_op *cop = &kcop->cop;
+ struct crypto_session *ses_ptr;
+ int rc;
+
+ /* this also enters ses_ptr->sem */
+ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses);
+ if (unlikely(!ses_ptr)) {
+ dbgp(2, "invalid session ID=0x%08X", cop->ses);
+ return -EINVAL;
+ }
+
+ if (unlikely(cop->iv && cop->ivlen < ses_ptr->cdata.ivsize)) {
+ dbgp(2, "invalid ivlen = %d", cop->ivlen);
+ return -EINVAL;
+ }
+
+ kcop->ivlen = cop->iv ? ses_ptr->cdata.ivsize : 0;
+
+ crypto_put_session(ses_ptr);
+
+ if (cop->iv) {
+ rc = copy_from_user(kcop->iv, cop->iv, kcop->ivlen);
+ if (unlikely(rc)) {
+ dbgp(2, "error copying IV (%d bytes), returned %d",
+ kcop->ivlen, rc);
+ return -EFAULT;
+ }
+ }
+
+ return 0;
+}
+
+static int fill_cop_from_kcop(struct kernel_crypt_op *kcop, struct fcrypt *fcr)
+{
+ int ret;
+
+ if (kcop->ivlen) {
+ ret = copy_to_user(kcop->cop.iv,
+ kcop->iv, kcop->ivlen);
+ if (unlikely(ret))
+ return -EFAULT;
+ }
+ return 0;
+}
+
+static int kcop_from_user(struct kernel_crypt_op *kcop,
+ struct fcrypt *fcr, void __user *arg)
+{
+ if (unlikely(copy_from_user(&kcop->cop, arg, sizeof(kcop->cop))))
+ return -EFAULT;
+
+ if (kcop->cop.num_src_bufs > MAX_CRYPTO_BUFFERS ||
+ kcop->cop.num_dst_bufs > MAX_CRYPTO_BUFFERS) {
+ dbgp(2, "too many buffers, src: %d, dst: %d\n",
+ kcop->cop.num_src_bufs, kcop->cop.num_dst_bufs);
+ return -EINVAL;
+ }
+ return fill_kcop_from_cop(kcop, fcr);
+}
+
+static int kcop_to_user(struct kernel_crypt_op *kcop,
+ struct fcrypt *fcr, void __user *arg)
+{
+ int ret;
+
+ ret = fill_cop_from_kcop(kcop, fcr);
+ if (unlikely(ret)) {
+ dbgp(2, "Error in fill_cop_from_kcop");
+ return ret;
+ }
+
+ if (unlikely(copy_to_user(arg, &kcop->cop, sizeof(kcop->cop)))) {
+ dbgp(2, "Cannot copy to userspace");
+ return -EFAULT;
+ }
+ return 0;
+}
+
+static int hw_restriction_check(u32 nbufs, struct crypt_mem *buf,
+ struct crypto_session *ses_ptr)
+{
+ int i = 0;
+ u32 length = 0, dma_length = 0;
+ int rc = 0;
+
+ for (i = 0; i < nbufs; i++) {
+ length = buf[i].length;
+ if (!(length % DMA_BLOCK_MODE_SIZE))
+ dma_length = length / DMA_BLOCK_MODE_SIZE;
+ else
+ dma_length = length;
+ if (dma_length >> 18) {
+ /* length too large for byte mode */
+ rc = -EINVAL;
+ dbgp(2, "size too large: %d\n", dma_length);
+ return rc;
+ }
+
+ if (length % ses_ptr->cdata.blocksize) {
+ if (ses_ptr->cdata.cipher == CRYPTO_OP_AES_CTR) {
+ if (i != (nbufs - 1)) {
+ dbgp(2, "unaligned buffer size: %d\n",
+ length);
+ return -EINVAL;
+ }
+ } else {
+ dbgp(2, "unaligned buffer size: %d\n",
+ length);
+ return -EINVAL;
+ }
+ }
+ }
+
+ return rc;
+}
+
+/* Increment 128-bit counter */
+static void ctr_update_iv(unsigned char *val, unsigned int value)
+{
+ int i;
+
+ while (value > 0) {
+ for (i = 15; i >= 0; i--) {
+ val[i] = (val[i] + 1) & 0xff;
+ if (val[i])
+ break;
+ }
+ value--;
+ }
+}
+
+int __crypto_run_physical(struct crypto_session *ses_ptr,
+ struct kernel_crypt_op *kcop)
+{
+ int i = 0;
+ dma_addr_t dsc_addr = 0;
+ dma_addr_t dma_iv_addr = 0;
+ dma_addr_t cleanup_addr = 0;
+ struct dma_dsc *dsc = NULL;
+ u8 *iv = NULL;
+ u8 *key_clean = NULL;
+ struct device *dev = NULL;
+ int s = 0;
+ int nbufs = 0;
+ int rc = 0;
+ int block_mode = 0;
+ u32 src_bufsz = 0;
+ int err = 0;
+
+ if (unlikely(!ses_ptr || !kcop)) {
+ dbgp(2, "no ses_ptr or no kcop\n");
+ return -EINVAL;
+ }
+
+ dev = crypto_dd->dev;
+
+ /* data sanity check for HW restrictions */
+ if (kcop->cop.num_src_bufs != kcop->cop.num_dst_bufs) {
+ dbgp(2, "incompatible number of buffers, src: %d, dst: %d\n",
+ kcop->cop.num_src_bufs, kcop->cop.num_dst_bufs);
+ return -EINVAL;
+ }
+
+ nbufs = kcop->cop.num_src_bufs;
+ for (i = 0; i < nbufs; i++) {
+ if (kcop->cop.src[i].length != kcop->cop.dst[i].length) {
+ dbgp(2, "incompatible buffer size\n");
+ dbgp(2, "buffer: %d, src: %d, dst: %d\n",
+ i, kcop->cop.src[i].length,
+ kcop->cop.src[i].length);
+ return -EINVAL;
+ }
+ }
+ if (hw_restriction_check(nbufs, kcop->cop.src, ses_ptr)) {
+ dbgp(2, "checked fail in src\n");
+ return -EINVAL;
+ }
+ if (hw_restriction_check(nbufs, kcop->cop.dst, ses_ptr)) {
+ dbgp(2, "checked fail in dst\n");
+ return -EINVAL;
+ }
+ for (i = 0; i < nbufs; i++)
+ src_bufsz += kcop->cop.src[i].length;
+
+ /* extra three descriptor for key and IV and cleanup */
+ dsc = dma_alloc_coherent(dev, (nbufs + 3) * sizeof(struct dma_dsc),
+ &dsc_addr, GFP_KERNEL | GFP_DMA);
+ if (!dsc) {
+ dbgp(2, "cannot allocate dsc\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ dsc[0].src_addr = (u32)(0xffffff00 | ses_ptr->cdata.kte);
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = ses_ptr->cdata.keylen;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 0;
+ dsc[0].dsc_cfg.b.owner = 1;
+ s++;
+
+ if (kcop->ivlen) {
+ iv = dma_alloc_coherent(dev, kcop->ivlen,
+ &dma_iv_addr, GFP_KERNEL | GFP_DMA);
+ if (!iv) {
+ dbgp(2, "cannot allocate iv\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memcpy(iv, kcop->iv, kcop->ivlen);
+ dsc[1].src_addr = (u32)dma_iv_addr;
+ dsc[1].tgt_addr = 32;
+ dsc[1].dsc_cfg.d32 = 0;
+ /* HW bug, iv length needs to stay at 16 */
+ dsc[1].dsc_cfg.b.length = 16;
+ dsc[1].dsc_cfg.b.mode = MODE_KEY;
+ dsc[1].dsc_cfg.b.eoc = 0;
+ dsc[1].dsc_cfg.b.owner = 1;
+ s++;
+ }
+
+ /* Do nothing for IV: We do not know IV in encrypt */
+
+ for (i = 0; i < nbufs; i++) {
+ u32 length = kcop->cop.src[i].length;
+
+ if (!(length % DMA_BLOCK_MODE_SIZE))
+ block_mode = 1;
+ else
+ block_mode = 0;
+
+ dsc[s + i].src_addr = (uintptr_t)kcop->cop.src[i].addr;
+ dsc[s + i].tgt_addr = (uintptr_t)kcop->cop.dst[i].addr;
+ dsc[s + i].dsc_cfg.d32 = 0;
+ dsc[s + i].dsc_cfg.b.enc_sha_only = (kcop->cop.op ==
+ CRYPTO_OP_ENCRYPT);
+ dsc[s + i].dsc_cfg.b.block = block_mode;
+ if (block_mode)
+ dsc[s + i].dsc_cfg.b.length =
+ length / DMA_BLOCK_MODE_SIZE;
+ else
+ dsc[s + i].dsc_cfg.b.length = length;
+ dsc[s + i].dsc_cfg.b.op_mode = ses_ptr->cdata.op_mode;
+ dsc[s + i].dsc_cfg.b.mode = ses_ptr->cdata.crypt_mode;
+ dsc[s + i].dsc_cfg.b.eoc = 0;
+ dsc[s + i].dsc_cfg.b.owner = 1;
+ }
+ key_clean = dma_alloc_coherent(dev, DMA_KEY_IV_BUF_SIZE, &cleanup_addr,
+ GFP_KERNEL | GFP_DMA);
+ if (!key_clean) {
+ dbgp(2, "cannot allocate key_clean\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memset(key_clean, 0, DMA_KEY_IV_BUF_SIZE);
+ dsc[s + i].src_addr = cleanup_addr;
+ dsc[s + i].tgt_addr = 0;
+ dsc[s + i].dsc_cfg.d32 = 0;
+ dsc[s + i].dsc_cfg.b.length = DMA_KEY_IV_BUF_SIZE;
+ dsc[s + i].dsc_cfg.b.mode = MODE_KEY;
+ dsc[s + i].dsc_cfg.b.eoc = 1;
+ dsc[s + i].dsc_cfg.b.owner = 1;
+
+ aml_dma_debug(dsc, s + i + 1, __func__,
+ crypto_dd->thread, crypto_dd->status);
+
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 1;
+ crypto_dd->processing = current;
+ mutex_unlock(&crypto_dd->lock);
+
+#if !USE_BUSY_POLLING
+ set_current_state(TASK_INTERRUPTIBLE);
+#endif
+
+ aml_write_crypto_reg(crypto_dd->thread, (uintptr_t)dsc_addr | 2);
+
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC) {
+ /* Do nothing for IV: We do not know IV in decrypt */
+ } else if (ses_ptr->cdata.op_mode == OP_MODE_CTR) {
+ u32 dma_nblock =
+ (src_bufsz + ses_ptr->cdata.blocksize - 1)
+ / ses_ptr->cdata.blocksize;
+ ctr_update_iv(kcop->iv, dma_nblock);
+ }
+
+error:
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 0;
+ mutex_unlock(&crypto_dd->lock);
+
+ if (iv)
+ dma_free_coherent(dev, kcop->ivlen, iv, dma_iv_addr);
+ if (dsc)
+ dma_free_coherent(dev, (nbufs + 3) * sizeof(struct dma_dsc),
+ dsc, dsc_addr);
+ if (key_clean)
+ dma_free_coherent(dev, DMA_KEY_IV_BUF_SIZE,
+ key_clean, cleanup_addr);
+ return rc;
+}
+
+static int __copy_buffers_in(struct crypt_mem **src, u32 total, u32 *offset,
+ u8 *buf, int buflen)
+{
+ int rc = 0;
+ int count, lvl = 0;
+
+ while (total && buflen) {
+ count = min((*src)->length - *offset, total);
+ count = min(count, buflen);
+
+ if (!count)
+ return lvl;
+
+ rc = copy_from_user(buf + lvl, (*src)->addr + *offset, count);
+ if (unlikely(rc)) {
+ dbgp(2, "error copying src (%d bytes)\n", count);
+ dbgp(2, "copy_from_user returned %d", rc);
+ return -1;
+ }
+
+ lvl += count;
+ buflen -= count;
+ *offset += count;
+ total -= count;
+
+ if (*offset == (*src)->length) {
+ (*src)++;
+ *offset = 0;
+ }
+ }
+
+ return lvl;
+}
+
+static int __copy_buffers_out(struct crypt_mem **dst, u32 total,
+ u32 *offset, u8 *buf)
+{
+ int rc = 0;
+ int count, lvl = 0;
+
+ while (total) {
+ count = min((*dst)->length - *offset, total);
+
+ if (!count)
+ return lvl;
+
+ rc = copy_to_user((*dst)->addr + *offset, buf + lvl, count);
+ if (unlikely(rc)) {
+ dbgp(2, "error copying src (%d bytes)\n", count);
+ dbgp(2, "copy_from_user returned %d\n", rc);
+ return -1;
+ }
+
+ lvl += count;
+ *offset += count;
+ total -= count;
+
+ if (*offset == (*dst)->length) {
+ (*dst)++;
+ *offset = 0;
+ }
+ }
+
+ return lvl;
+}
+
+int __crypto_run_virt_to_phys(struct crypto_session *ses_ptr,
+ struct kernel_crypt_op *kcop)
+{
+ int i = 0;
+ dma_addr_t dsc_addr = 0;
+ dma_addr_t dma_iv_addr = 0;
+ dma_addr_t dma_buf = 0;
+ dma_addr_t cleanup_addr = 0;
+ struct dma_dsc *dsc = NULL;
+ u8 *iv = NULL;
+ u8 *key_clean = NULL;
+ struct device *dev = NULL;
+ int s = 0;
+ int nbufs = 0;
+ int rc = 0;
+ int block_mode = 0;
+ u8 *tmp_buf = NULL, *tmp_buf2 = NULL;
+ struct crypt_mem *src = kcop->cop.src;
+ u32 length = 0;
+ u32 offset = 0;
+ int count = 0;
+ u32 src_bufsz = 0;
+ int err = 0;
+
+ if (unlikely(!ses_ptr || !kcop)) {
+ dbgp(2, "no ses_ptr or no kcop\n");
+ return -EINVAL;
+ }
+
+ dev = crypto_dd->dev;
+
+ /* data sanity check for HW restrictions */
+ nbufs = kcop->cop.num_dst_bufs;
+ for (i = 0; i < nbufs; i++)
+ src_bufsz += kcop->cop.src[i].length;
+ if (hw_restriction_check(nbufs, kcop->cop.dst, ses_ptr)) {
+ dbgp(2, "checked fail in dst\n");
+ return -EINVAL;
+ }
+
+ /* three descriptor for key, IV and data */
+ dsc = dma_alloc_coherent(dev, 3 * sizeof(struct dma_dsc),
+ &dsc_addr, GFP_KERNEL | GFP_DMA);
+ if (!dsc) {
+ dbgp(2, "cannot allocate dsc\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ dsc[0].src_addr = (u32)(0xffffff00 | ses_ptr->cdata.kte);
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = ses_ptr->cdata.keylen;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 0;
+ dsc[0].dsc_cfg.b.owner = 1;
+ s++;
+
+ if (kcop->ivlen) {
+ iv = dma_alloc_coherent(dev, kcop->ivlen,
+ &dma_iv_addr, GFP_KERNEL | GFP_DMA);
+ if (!iv) {
+ dbgp(2, "cannot allocate iv\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memcpy(iv, kcop->iv, kcop->ivlen);
+ dsc[1].src_addr = (u32)dma_iv_addr;
+ dsc[1].tgt_addr = 32;
+ dsc[1].dsc_cfg.d32 = 0;
+ /* HW bug, iv length needs to stay at 16 */
+ dsc[1].dsc_cfg.b.length = 16;
+ dsc[1].dsc_cfg.b.mode = MODE_KEY;
+ dsc[1].dsc_cfg.b.eoc = 0;
+ dsc[1].dsc_cfg.b.owner = 1;
+ s++;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC &&
+ kcop->cop.op != CRYPTO_OP_ENCRYPT) {
+ uintptr_t s_end = (uintptr_t)kcop->cop.src[nbufs - 1].addr +
+ kcop->cop.src[nbufs - 1].length;
+ rc = copy_from_user(kcop->iv,
+ (void *)(s_end - ses_ptr->cdata.blocksize),
+ ses_ptr->cdata.blocksize);
+ if (unlikely(rc)) {
+ dbgp(2, "failed to get next IV\n");
+ rc = -EPERM;
+ goto error;
+ }
+ }
+
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 1;
+ crypto_dd->processing = current;
+ mutex_unlock(&crypto_dd->lock);
+
+ for (i = 0; i < nbufs; i++) {
+ length = kcop->cop.dst[i].length;
+ tmp_buf2 = krealloc(tmp_buf, length, GFP_KERNEL | GFP_DMA);
+ if (!tmp_buf2) {
+ dbgp(2, "cannot allocate memory, size: %d\n", length);
+ rc = -ENOMEM;
+ goto error;
+ }
+ tmp_buf = tmp_buf2;
+ count = __copy_buffers_in(&src, length, &offset,
+ tmp_buf, length);
+ if (unlikely(count != length)) {
+ dbgp(2, "incompatible num %d %d read\n", count, length);
+ goto error;
+ }
+
+ if (!(length % DMA_BLOCK_MODE_SIZE))
+ block_mode = 1;
+ else
+ block_mode = 0;
+
+ dma_buf = dma_map_single(dev, tmp_buf, length, DMA_TO_DEVICE);
+
+ dsc[s].src_addr = dma_buf;
+ dsc[s].tgt_addr = (uintptr_t)kcop->cop.dst[i].addr;
+ dsc[s].dsc_cfg.d32 = 0;
+ dsc[s].dsc_cfg.b.enc_sha_only = (kcop->cop.op
+ == CRYPTO_OP_ENCRYPT);
+ dsc[s].dsc_cfg.b.block = block_mode;
+ if (block_mode)
+ dsc[s].dsc_cfg.b.length =
+ length / DMA_BLOCK_MODE_SIZE;
+ else
+ dsc[s].dsc_cfg.b.length = length;
+ dsc[s].dsc_cfg.b.op_mode = ses_ptr->cdata.op_mode;
+ dsc[s].dsc_cfg.b.mode = ses_ptr->cdata.crypt_mode;
+ dsc[s].dsc_cfg.b.eoc = 1;
+ dsc[s].dsc_cfg.b.owner = 1;
+
+#if !USE_BUSY_POLLING
+ set_current_state(TASK_INTERRUPTIBLE);
+#endif
+
+ aml_dma_debug(dsc, s + 1, __func__,
+ crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread,
+ (uintptr_t)dsc_addr | 2);
+
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ dma_unmap_single(dev, dma_buf, length, DMA_TO_DEVICE);
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+ s = 0;
+ }
+
+ key_clean = dma_alloc_coherent(dev, DMA_KEY_IV_BUF_SIZE, &cleanup_addr,
+ GFP_KERNEL | GFP_DMA);
+ if (!key_clean) {
+ dbgp(2, "cannot allocate key_clean\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memset(key_clean, 0, DMA_KEY_IV_BUF_SIZE);
+ dsc[0].src_addr = cleanup_addr;
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = DMA_KEY_IV_BUF_SIZE;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 1;
+ dsc[0].dsc_cfg.b.owner = 1;
+
+ aml_dma_debug(dsc, 1, __func__, crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread, (uintptr_t)dsc_addr | 2);
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC) {
+ /* Do nothing for IV: We do not know IV in decrypt */
+ } else if (ses_ptr->cdata.op_mode == OP_MODE_CTR) {
+ u32 dma_nblock =
+ (src_bufsz + ses_ptr->cdata.blocksize - 1)
+ / ses_ptr->cdata.blocksize;
+ ctr_update_iv(kcop->iv, dma_nblock);
+ }
+
+error:
+
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 0;
+ mutex_unlock(&crypto_dd->lock);
+
+ if (iv)
+ dma_free_coherent(dev, kcop->ivlen, iv, dma_iv_addr);
+ if (dsc)
+ dma_free_coherent(dev, 3 * sizeof(struct dma_dsc),
+ dsc, dsc_addr);
+ if (key_clean)
+ dma_free_coherent(dev, DMA_KEY_IV_BUF_SIZE,
+ key_clean, cleanup_addr);
+ kfree(tmp_buf);
+
+ return rc;
+}
+
+int __crypto_run_phys_to_virt(struct crypto_session *ses_ptr,
+ struct kernel_crypt_op *kcop)
+{
+ int i = 0;
+ dma_addr_t dsc_addr = 0;
+ dma_addr_t dma_iv_addr = 0;
+ dma_addr_t dma_buf = 0;
+ dma_addr_t cleanup_addr = 0;
+ struct dma_dsc *dsc = NULL;
+ u8 *iv = NULL;
+ u8 *key_clean = NULL;
+ struct device *dev = NULL;
+ int s = 0;
+ int nbufs = 0;
+ int rc = 0;
+ int block_mode = 0;
+ u8 *tmp_buf = NULL, *tmp_buf2 = NULL;
+ u32 length = 0;
+ u32 offset_dst = 0;
+ struct crypt_mem *dst = kcop->cop.dst;
+ int count_dst = 0;
+ u32 src_bufsz = 0;
+ int err = 0;
+
+ if (unlikely(!ses_ptr || !kcop)) {
+ dbgp(2, "no ses_ptr or no kcop\n");
+ return -EINVAL;
+ }
+
+ dev = crypto_dd->dev;
+
+ /* data sanity check for HW restrictions */
+ nbufs = kcop->cop.num_src_bufs;
+ if (hw_restriction_check(nbufs, kcop->cop.src, ses_ptr)) {
+ dbgp(2, "checked fail in dst\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < nbufs; i++)
+ src_bufsz += kcop->cop.src[i].length;
+
+ /* three descriptor for key, IV and data */
+ dsc = dma_alloc_coherent(dev, 3 * sizeof(struct dma_dsc),
+ &dsc_addr, GFP_KERNEL | GFP_DMA);
+ if (!dsc) {
+ dbgp(2, "cannot allocate dsc\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ dsc[0].src_addr = (u32)(0xffffff00 | ses_ptr->cdata.kte);
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = ses_ptr->cdata.keylen;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 0;
+ dsc[0].dsc_cfg.b.owner = 1;
+ s++;
+
+ if (kcop->ivlen) {
+ iv = dma_alloc_coherent(dev, kcop->ivlen,
+ &dma_iv_addr, GFP_KERNEL | GFP_DMA);
+ if (!iv) {
+ dbgp(2, "cannot allocate iv\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memcpy(iv, kcop->iv, kcop->ivlen);
+ dsc[1].src_addr = (u32)dma_iv_addr;
+ dsc[1].tgt_addr = 32;
+ dsc[1].dsc_cfg.d32 = 0;
+ /* HW bug, iv length needs to stay at 16 */
+ dsc[1].dsc_cfg.b.length = 16;
+ dsc[1].dsc_cfg.b.mode = MODE_KEY;
+ dsc[1].dsc_cfg.b.eoc = 0;
+ dsc[1].dsc_cfg.b.owner = 1;
+ s++;
+ }
+
+ /* Do nothing for IV: We do not know IV in encrypt */
+
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 1;
+ crypto_dd->processing = current;
+ mutex_unlock(&crypto_dd->lock);
+
+ for (i = 0; i < nbufs; i++) {
+ length = kcop->cop.src[i].length;
+ tmp_buf2 = krealloc(tmp_buf, length, GFP_KERNEL | GFP_DMA);
+ if (!tmp_buf2) {
+ dbgp(2, "cannot allocate memory, size: %d\n", length);
+ rc = -ENOMEM;
+ goto error;
+ }
+ tmp_buf = tmp_buf2;
+
+ if (!(length % DMA_BLOCK_MODE_SIZE))
+ block_mode = 1;
+ else
+ block_mode = 0;
+
+ dma_buf = dma_map_single(dev, tmp_buf, length, DMA_FROM_DEVICE);
+
+ dsc[s].src_addr = (uintptr_t)kcop->cop.src[i].addr;
+ dsc[s].tgt_addr = dma_buf;
+ dsc[s].dsc_cfg.d32 = 0;
+ dsc[s].dsc_cfg.b.enc_sha_only = (kcop->cop.op
+ == CRYPTO_OP_ENCRYPT);
+ dsc[s].dsc_cfg.b.block = block_mode;
+ if (block_mode)
+ dsc[s].dsc_cfg.b.length =
+ length / DMA_BLOCK_MODE_SIZE;
+ else
+ dsc[s].dsc_cfg.b.length = length;
+ dsc[s].dsc_cfg.b.op_mode = ses_ptr->cdata.op_mode;
+ dsc[s].dsc_cfg.b.mode = ses_ptr->cdata.crypt_mode;
+ dsc[s].dsc_cfg.b.eoc = 1;
+ dsc[s].dsc_cfg.b.owner = 1;
+
+#if !USE_BUSY_POLLING
+ set_current_state(TASK_INTERRUPTIBLE);
+#endif
+
+ aml_dma_debug(dsc, s + 1, __func__,
+ crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread,
+ (uintptr_t)dsc_addr | 2);
+
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ dma_unmap_single(dev, dma_buf, length, DMA_FROM_DEVICE);
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+ count_dst = __copy_buffers_out(&dst, length,
+ &offset_dst, tmp_buf);
+ if (unlikely(count_dst != length)) {
+ dbgp(2, "incorrect number of data, c = %d, dst = %d\n",
+ length, count_dst);
+ goto error;
+ }
+ s = 0;
+ }
+
+ key_clean = dma_alloc_coherent(dev, DMA_KEY_IV_BUF_SIZE, &cleanup_addr,
+ GFP_KERNEL | GFP_DMA);
+ if (!key_clean) {
+ dbgp(2, "cannot allocate key_clean\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memset(key_clean, 0, DMA_KEY_IV_BUF_SIZE);
+ dsc[0].src_addr = cleanup_addr;
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = DMA_KEY_IV_BUF_SIZE;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 1;
+ dsc[0].dsc_cfg.b.owner = 1;
+
+ aml_dma_debug(dsc, 1, __func__, crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread, (uintptr_t)dsc_addr | 2);
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC) {
+ if (kcop->cop.op == CRYPTO_OP_ENCRYPT) {
+ memcpy(kcop->iv, tmp_buf + count_dst -
+ ses_ptr->cdata.blocksize,
+ ses_ptr->cdata.blocksize);
+ }
+ } else if (ses_ptr->cdata.op_mode == OP_MODE_CTR) {
+ u32 dma_nblock =
+ (src_bufsz + ses_ptr->cdata.blocksize - 1)
+ / ses_ptr->cdata.blocksize;
+ ctr_update_iv(kcop->iv, dma_nblock);
+ }
+
+error:
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 0;
+ mutex_unlock(&crypto_dd->lock);
+
+ if (iv)
+ dma_free_coherent(dev, kcop->ivlen, iv, dma_iv_addr);
+ if (dsc)
+ dma_free_coherent(dev, 3 * sizeof(struct dma_dsc),
+ dsc, dsc_addr);
+ if (key_clean)
+ dma_free_coherent(dev, DMA_KEY_IV_BUF_SIZE,
+ key_clean, cleanup_addr);
+ kfree(tmp_buf);
+
+ return rc;
+}
+
+int __crypto_run_virtual(struct crypto_session *ses_ptr,
+ struct kernel_crypt_op *kcop)
+{
+ int i = 0;
+ dma_addr_t dsc_addr = 0;
+ dma_addr_t dma_iv_addr = 0;
+ dma_addr_t dma_buf = 0;
+ dma_addr_t cleanup_addr = 0;
+ struct dma_dsc *dsc = NULL;
+ u8 *key_clean = NULL;
+ u8 *iv = NULL;
+ struct device *dev = NULL;
+ int s = 0;
+ int nsrc_bufs = 0;
+ int ndst_bufs = 0;
+ u32 total = 0;
+ u32 src_bufsz = 0;
+ u32 dst_bufsz = 0;
+ u8 *tmp_buf = NULL;
+ int rc = 0;
+ u32 offset = 0, offset_dst = 0;
+ struct crypt_mem *src = kcop->cop.src;
+ struct crypt_mem *dst = kcop->cop.dst;
+ int count = 0, count_dst = 0;
+ int err = 0;
+
+ if (unlikely(!ses_ptr || !kcop)) {
+ dbgp(2, "no ses_ptr or no kcop\n");
+ return -EINVAL;
+ }
+
+ dev = crypto_dd->dev;
+
+ nsrc_bufs = kcop->cop.num_src_bufs;
+ for (i = 0; i < nsrc_bufs; i++)
+ src_bufsz += kcop->cop.src[i].length;
+ total = src_bufsz;
+
+ ndst_bufs = kcop->cop.num_dst_bufs;
+ for (i = 0; i < ndst_bufs; i++)
+ dst_bufsz += kcop->cop.dst[i].length;
+
+ if (dst_bufsz < src_bufsz) {
+ dbgp(2, "buffer size mismatch, src: %d, dst: %d\n",
+ src_bufsz, dst_bufsz);
+ return -EINVAL;
+ }
+
+ tmp_buf = (void *)__get_free_pages(GFP_KERNEL, 0);
+ if (!tmp_buf) {
+ dbgp(2, "cannot allocate tmpbuf\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ dma_buf = dma_map_single(dev, tmp_buf, PAGE_SIZE, DMA_TO_DEVICE);
+
+ /* three descriptor for key, IV and data */
+ dsc = dma_alloc_coherent(dev, 3 * sizeof(struct dma_dsc),
+ &dsc_addr, GFP_KERNEL | GFP_DMA);
+ if (!dsc) {
+ dbgp(2, "cannot allocate dsc\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+
+ dsc[0].src_addr = (u32)(0xffffff00 | ses_ptr->cdata.kte);
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = ses_ptr->cdata.keylen;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 0;
+ dsc[0].dsc_cfg.b.owner = 1;
+ s++;
+
+ if (kcop->ivlen) {
+ iv = dma_alloc_coherent(dev, kcop->ivlen,
+ &dma_iv_addr, GFP_KERNEL | GFP_DMA);
+ if (!iv) {
+ dbgp(2, "cannot allocate iv\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memcpy(iv, kcop->iv, kcop->ivlen);
+ dsc[1].src_addr = (u32)dma_iv_addr;
+ dsc[1].tgt_addr = 32;
+ dsc[1].dsc_cfg.d32 = 0;
+ /* HW bug, iv length needs to stay at 16 */
+ dsc[1].dsc_cfg.b.length = 16;
+ dsc[1].dsc_cfg.b.mode = MODE_KEY;
+ dsc[1].dsc_cfg.b.eoc = 0;
+ dsc[1].dsc_cfg.b.owner = 1;
+ s++;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC &&
+ kcop->cop.op != CRYPTO_OP_ENCRYPT) {
+ uintptr_t s_end = (uintptr_t)kcop->cop.src[nsrc_bufs - 1].addr +
+ kcop->cop.src[nsrc_bufs - 1].length;
+ rc = copy_from_user(kcop->iv,
+ (void *)(s_end - ses_ptr->cdata.blocksize),
+ ses_ptr->cdata.blocksize);
+ if (unlikely(rc)) {
+ dbgp(2, "failed to get next IV\n");
+ rc = -EPERM;
+ goto error;
+ }
+ }
+
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 1;
+ crypto_dd->processing = current;
+ mutex_unlock(&crypto_dd->lock);
+
+ while (total) {
+ count = __copy_buffers_in(&src, total, &offset,
+ tmp_buf, PAGE_SIZE);
+ if (count < 0)
+ goto error;
+ dma_sync_single_for_device(dev, dma_buf,
+ PAGE_SIZE, DMA_TO_DEVICE);
+
+ dsc[s].src_addr = dma_buf;
+ dsc[s].tgt_addr = dma_buf;
+ dsc[s].dsc_cfg.d32 = 0;
+ dsc[s].dsc_cfg.b.enc_sha_only = (kcop->cop.op
+ == CRYPTO_OP_ENCRYPT);
+ dsc[s].dsc_cfg.b.length = count;
+ dsc[s].dsc_cfg.b.op_mode = ses_ptr->cdata.op_mode;
+ dsc[s].dsc_cfg.b.mode = ses_ptr->cdata.crypt_mode;
+ dsc[s].dsc_cfg.b.eoc = 1;
+ dsc[s].dsc_cfg.b.owner = 1;
+
+#if !USE_BUSY_POLLING
+ set_current_state(TASK_INTERRUPTIBLE);
+#endif
+
+ aml_dma_debug(dsc, s + 1, __func__,
+ crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread,
+ (uintptr_t)dsc_addr | 2);
+
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ dma_sync_single_for_cpu(dev, dma_buf,
+ PAGE_SIZE, DMA_FROM_DEVICE);
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+ count_dst = __copy_buffers_out(&dst, count,
+ &offset_dst, tmp_buf);
+ if (unlikely(count_dst != count)) {
+ dbgp(2, "incorrect number of data, c = %d, dst = %d\n",
+ count, count_dst);
+ goto error;
+ }
+ total -= count;
+ s = 0;
+ }
+
+ key_clean = dma_alloc_coherent(dev, DMA_KEY_IV_BUF_SIZE, &cleanup_addr,
+ GFP_KERNEL | GFP_DMA);
+ if (!key_clean) {
+ dbgp(2, "cannot allocate key_clean\n");
+ rc = -ENOMEM;
+ goto error;
+ }
+ memset(key_clean, 0, DMA_KEY_IV_BUF_SIZE);
+ dsc[0].src_addr = cleanup_addr;
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = DMA_KEY_IV_BUF_SIZE;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 1;
+ dsc[0].dsc_cfg.b.owner = 1;
+
+ aml_dma_debug(dsc, 1, __func__, crypto_dd->thread, crypto_dd->status);
+ aml_write_crypto_reg(crypto_dd->thread, (uintptr_t)dsc_addr | 2);
+#if USE_BUSY_POLLING
+ while ((err = aml_read_crypto_reg(crypto_dd->status)) == 0)
+ ;
+ aml_write_crypto_reg(crypto_dd->status, 0xf);
+#else
+ schedule();
+ err = crypto_dd->err;
+#endif
+ if (err & DMA_STATUS_KEY_ERROR) {
+ rc = -EACCES;
+ goto error;
+ }
+
+ if (ses_ptr->cdata.op_mode == OP_MODE_CBC) {
+ if (kcop->cop.op == CRYPTO_OP_ENCRYPT) {
+ memcpy(kcop->iv, tmp_buf + count_dst -
+ ses_ptr->cdata.blocksize,
+ ses_ptr->cdata.blocksize);
+ }
+ } else if (ses_ptr->cdata.op_mode == OP_MODE_CTR) {
+ u32 dma_nblock =
+ (src_bufsz + ses_ptr->cdata.blocksize - 1)
+ / ses_ptr->cdata.blocksize;
+ ctr_update_iv(kcop->iv, dma_nblock);
+ }
+
+error:
+ mutex_lock(&crypto_dd->lock);
+ crypto_dd->dma_busy = 0;
+ mutex_unlock(&crypto_dd->lock);
+
+ if (dma_buf)
+ dma_unmap_single(dev, dma_buf, PAGE_SIZE, DMA_TO_DEVICE);
+ if (iv)
+ dma_free_coherent(dev, kcop->ivlen, iv, dma_iv_addr);
+ if (dsc)
+ dma_free_coherent(dev, 3 * sizeof(struct dma_dsc),
+ dsc, dsc_addr);
+ if (key_clean)
+ dma_free_coherent(dev, DMA_KEY_IV_BUF_SIZE,
+ key_clean, cleanup_addr);
+ if (tmp_buf)
+ free_page((uintptr_t)tmp_buf);
+
+ return rc;
+}
+
+int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop)
+{
+ struct crypto_session *ses_ptr;
+ struct crypt_op *cop = &kcop->cop;
+ int ret = 0;
+
+ if (unlikely(cop->op != CRYPTO_OP_ENCRYPT &&
+ cop->op != CRYPTO_OP_DECRYPT)) {
+ dbgp(2, "invalid operation op=%u", cop->op);
+ return -EINVAL;
+ }
+
+ if (crypto_dd->dma_busy)
+ wait_event_interruptible(crypto_dd->waiter,
+ crypto_dd->dma_busy == 0);
+
+ /* this also enters ses_ptr->sem */
+ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses);
+ if (unlikely(!ses_ptr)) {
+ dbgp(2, "invalid session ID=0x%08X", cop->ses);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (ses_ptr->cdata.init != 0) {
+ if (ses_ptr->cdata.op_mode == OP_MODE_CTR) {
+ /* ctr only supports encrypt */
+ kcop->cop.op = CRYPTO_OP_ENCRYPT;
+ }
+ if (ses_ptr->cdata.op_mode != OP_MODE_ECB && !kcop->cop.ivlen) {
+ dbgp(2, "no iv for non-ecb\n");
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ if (kcop->cop.src_phys && kcop->cop.dst_phys)
+ ret = __crypto_run_physical(ses_ptr, kcop);
+ else if (!kcop->cop.src_phys && kcop->cop.dst_phys)
+ ret = __crypto_run_virt_to_phys(ses_ptr, kcop);
+ else if (kcop->cop.src_phys && !kcop->cop.dst_phys)
+ ret = __crypto_run_phys_to_virt(ses_ptr, kcop);
+ else
+ ret = __crypto_run_virtual(ses_ptr, kcop);
+ } else {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
+out_unlock:
+ crypto_put_session(ses_ptr);
+
+out:
+ wake_up_interruptible(&crypto_dd->waiter);
+ return ret;
+}
+
+static int aml_crypto_dev_open(struct inode *inode, struct file *filp)
+{
+ struct crypt_priv *pcr;
+
+ pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
+ if (!pcr)
+ return -ENOMEM;
+ filp->private_data = pcr;
+
+ mutex_init(&pcr->fcrypt.sem);
+
+ INIT_LIST_HEAD(&pcr->fcrypt.list);
+ return 0;
+}
+
+static int aml_crypto_dev_release(struct inode *inode, struct file *filp)
+{
+ struct crypt_priv *pcr = filp->private_data;
+
+ if (!pcr)
+ return 0;
+
+ mutex_destroy(&pcr->fcrypt.sem);
+ kfree(pcr);
+ filp->private_data = NULL;
+
+ return 0;
+}
+
+static long aml_crypto_dev_ioctl(struct file *filp,
+ unsigned int cmd, unsigned long arg_)
+{
+ void __user *arg = (void __user *)arg_;
+ struct session_op sop;
+ struct kernel_crypt_op kcop;
+ struct crypt_priv *pcr = filp->private_data;
+ struct fcrypt *fcr;
+ u32 ses;
+ int ret = 0;
+
+ if (unlikely(!pcr)) {
+ dbgp(2, "empty pcr\n");
+ return -EINVAL;
+ }
+
+ fcr = &pcr->fcrypt;
+
+ switch (cmd) {
+ case CREATE_SESSION:
+ if (unlikely(copy_from_user(&sop, arg, sizeof(sop))))
+ return -EFAULT;
+
+ ret = crypto_create_session(fcr, &sop);
+ if (unlikely(ret))
+ return ret;
+ ret = copy_to_user(arg, &sop, sizeof(sop));
+ if (unlikely(ret)) {
+ crypto_finish_session(fcr, sop.ses);
+ return -EFAULT;
+ }
+ return ret;
+ case CLOSE_SESSION:
+ ret = get_user(ses, (u32 __user *)arg);
+ if (unlikely(ret))
+ return ret;
+ ret = crypto_finish_session(fcr, ses);
+ return ret;
+
+ case DO_CRYPTO:
+ ret = kcop_from_user(&kcop, fcr, arg);
+ if (unlikely(ret)) {
+ dbgp(2, "Error copying from user");
+ return ret;
+ }
+
+ ret = crypto_run(fcr, &kcop);
+ if (unlikely(ret)) {
+ dbgp(2, "Error in crypto_run");
+ return ret;
+ }
+
+ return kcop_to_user(&kcop, fcr, arg);
+ default:
+ dbgp(3, "unknown cmd: %d\n", cmd);
+ return -EINVAL;
+ }
+}
+
+#ifdef CONFIG_COMPAT
+static inline void compat_to_crypt_op(struct compat_crypt_op *compat,
+ struct crypt_op *cop)
+{
+ int i = 0;
+#if TEST_PHYSICAL_PROCESS
+ struct device *dev = NULL;
+ int rc = 0;
+
+ dev = crypto_dd->dev;
+#endif
+
+ cop->ses = compat->ses;
+ cop->op = compat->op;
+ cop->src_phys = compat->src_phys;
+ cop->dst_phys = compat->dst_phys;
+ cop->ivlen = compat->ivlen;
+ cop->num_src_bufs = compat->num_src_bufs;
+ cop->num_dst_bufs = compat->num_src_bufs;
+ cop->reserved = compat->reserved;
+
+ for (i = 0; i < MAX_CRYPTO_BUFFERS; i++) {
+ if (cop->src_phys) {
+#if TEST_PHYSICAL_PROCESS
+ g_src[i] = dma_alloc_coherent(dev,
+ compat->src[i].length,
+ &g_src_dma[i],
+ GFP_KERNEL | GFP_DMA);
+ g_tmp_src_addr[i] = compat_ptr(compat->src[i].addr);
+ cop->src[i].addr = (u8 *)(uintptr_t)g_src_dma[i];
+ cop->src[i].length = compat->src[i].length;
+ rc = copy_from_user(g_src[i],
+ compat_ptr(compat->src[i].addr),
+ compat->src[i].length);
+ if (unlikely(rc))
+ dev_err(dev, "failed at %s %d\n",
+ __func__, __LINE__);
+#else
+ cop->src[i].addr = (u8 *)(uintptr_t)compat->src[i].addr;
+ cop->src[i].length = compat->src[i].length;
+#endif
+ } else {
+ cop->src[i].addr = compat_ptr(compat->src[i].addr);
+ cop->src[i].length = compat->src[i].length;
+ }
+ if (cop->dst_phys) {
+#if TEST_PHYSICAL_PROCESS
+ g_dst[i] = dma_alloc_coherent(dev,
+ compat->dst[i].length,
+ &g_dst_dma[i],
+ GFP_KERNEL | GFP_DMA);
+ g_tmp_dst_addr[i] = compat_ptr(compat->dst[i].addr);
+ cop->dst[i].addr = (u8 *)(uintptr_t)g_dst_dma[i];
+ cop->dst[i].length = compat->dst[i].length;
+ rc = copy_from_user(g_dst[i],
+ compat_ptr(compat->dst[i].addr),
+ compat->src[i].length);
+ if (unlikely(rc))
+ dev_err(dev, "failed at %s %d\n",
+ __func__, __LINE__);
+#else
+ cop->dst[i].addr = (u8 *)(uintptr_t)compat->dst[i].addr;
+ cop->dst[i].length = compat->dst[i].length;
+#endif
+ } else {
+ cop->dst[i].addr = compat_ptr(compat->dst[i].addr);
+ cop->dst[i].length = compat->dst[i].length;
+ }
+ }
+ cop->iv = compat_ptr(compat->iv);
+}
+
+static inline void crypt_op_to_compat(struct crypt_op *cop,
+ struct compat_crypt_op *compat)
+{
+ int i = 0;
+#if TEST_PHYSICAL_PROCESS
+ int rc = 0;
+ struct device *dev = NULL;
+
+ dev = crypto_dd->dev;
+#endif
+
+ compat->ses = cop->ses;
+ compat->op = cop->op;
+ compat->src_phys = cop->src_phys;
+ compat->dst_phys = cop->dst_phys;
+ compat->ivlen = compat->ivlen;
+ compat->num_src_bufs = cop->num_src_bufs;
+ compat->num_dst_bufs = cop->num_src_bufs;
+ compat->reserved = cop->reserved;
+
+ for (i = 0; i < MAX_CRYPTO_BUFFERS; i++) {
+ if (cop->src_phys) {
+#if TEST_PHYSICAL_PROCESS
+ rc = copy_to_user(g_tmp_src_addr[i],
+ g_src[i], cop->src[i].length);
+ if (unlikely(rc))
+ dev_err(dev, "failed at %s %d\n",
+ __func__, __LINE__);
+ compat->src[i].addr = ptr_to_compat(g_tmp_src_addr[i]);
+ compat->src[i].length = cop->src[i].length;
+ dma_free_coherent(dev, cop->src[i].length,
+ g_src[i], g_src_dma[i]);
+#else
+ compat->src[i].addr = (uintptr_t)cop->src[i].addr;
+ compat->src[i].length = cop->src[i].length;
+#endif
+ } else {
+ compat->src[i].addr = ptr_to_compat(cop->src[i].addr);
+ compat->src[i].length = cop->src[i].length;
+ }
+ if (cop->dst_phys) {
+#if TEST_PHYSICAL_PROCESS
+ rc = copy_to_user(g_tmp_dst_addr[i], g_dst[i],
+ cop->dst[i].length);
+ if (unlikely(rc))
+ dev_err(dev, "failed at %s %d\n",
+ __func__, __LINE__);
+ compat->dst[i].addr = ptr_to_compat(g_tmp_dst_addr[i]);
+ compat->dst[i].length = cop->dst[i].length;
+ dma_free_coherent(dev, cop->dst[i].length,
+ g_dst[i], g_dst_dma[i]);
+#else
+ compat->dst[i].addr = (uintptr_t)cop->dst[i].addr;
+ compat->dst[i].length = cop->dst[i].length;
+#endif
+ } else {
+ compat->dst[i].addr = ptr_to_compat(cop->dst[i].addr);
+ compat->dst[i].length = compat->dst[i].length;
+ }
+ }
+ compat->iv = ptr_to_compat(cop->iv);
+}
+
+static int compat_kcop_from_user(struct kernel_crypt_op *kcop,
+ struct fcrypt *fcr, void __user *arg)
+{
+ struct compat_crypt_op compat_cop;
+
+ if (unlikely(copy_from_user(&compat_cop, arg, sizeof(compat_cop))))
+ return -EFAULT;
+ compat_to_crypt_op(&compat_cop, &kcop->cop);
+
+ return fill_kcop_from_cop(kcop, fcr);
+}
+
+static int compat_kcop_to_user(struct kernel_crypt_op *kcop,
+ struct fcrypt *fcr, void __user *arg)
+{
+ int ret;
+ struct compat_crypt_op compat_cop;
+
+ ret = fill_cop_from_kcop(kcop, fcr);
+ if (unlikely(ret)) {
+ dbgp(2, "Error in fill_cop_from_kcop");
+ return ret;
+ }
+ crypt_op_to_compat(&kcop->cop, &compat_cop);
+
+ if (unlikely(copy_to_user(arg, &compat_cop, sizeof(compat_cop)))) {
+ dbgp(2, "Error copying to user");
+ return -EFAULT;
+ }
+ return 0;
+}
+
+static long aml_crypto_dev_compat_ioctl(struct file *filp,
+ unsigned int cmd, unsigned long arg_)
+{
+ void __user *arg = (void __user *)arg_;
+ struct crypt_priv *pcr = filp->private_data;
+ struct fcrypt *fcr;
+ struct kernel_crypt_op kcop;
+ int ret = 0;
+
+ if (unlikely(!pcr)) {
+ dbgp(2, "empty pcr\n");
+ return -EINVAL;
+ }
+
+ fcr = &pcr->fcrypt;
+
+ switch (cmd) {
+ case CREATE_SESSION:
+ /* fall through */
+ case CLOSE_SESSION:
+ return aml_crypto_dev_ioctl(filp, cmd, arg_);
+ case DO_CRYPTO_COMPAT:
+ ret = compat_kcop_from_user(&kcop, fcr, arg);
+ if (unlikely(ret))
+ return ret;
+
+ ret = crypto_run(fcr, &kcop);
+ if (unlikely(ret))
+ return ret;
+
+ return compat_kcop_to_user(&kcop, fcr, arg);
+ default:
+ dbgp(3, "unknown cmd: %d\n", cmd);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+static const struct file_operations aml_crypto_dev_fops = {
+ .owner = THIS_MODULE,
+ .open = aml_crypto_dev_open,
+ .release = aml_crypto_dev_release,
+ .unlocked_ioctl = aml_crypto_dev_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = aml_crypto_dev_compat_ioctl,
+#endif /* CONFIG_COMPAT */
+};
+
+static struct miscdevice aml_crypto_device = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "aml_crypto",
+ .fops = &aml_crypto_dev_fops,
+ .mode = 0666,
+};
+
+static int aml_crypto_dev_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match;
+ struct resource *res_irq = 0;
+ const struct meson_crypto_dev_data *priv_data = NULL;
+ int err = 0;
+ u8 thread = 0;
+
+ crypto_dd = devm_kzalloc(dev, sizeof(struct aml_crypto_dev),
+ GFP_KERNEL);
+ if (!crypto_dd) {
+ err = -ENOMEM;
+ goto error;
+ }
+
+ match = of_match_device(aml_crypto_dev_dt_match, &pdev->dev);
+ if (!match) {
+ dev_err(dev, "%s: cannot find match dt\n", __func__);
+ err = -EINVAL;
+ goto error;
+ }
+
+ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+ of_property_read_u8(pdev->dev.of_node, "thread", &thread);
+
+ priv_data = match->data;
+ crypto_dd->dev = dev;
+ crypto_dd->thread = thread;
+ crypto_dd->status = priv_data->status + thread;
+ crypto_dd->irq = res_irq->start;
+ crypto_dd->processing = NULL;
+ init_waitqueue_head(&crypto_dd->waiter);
+ mutex_init(&crypto_dd->lock);
+ platform_set_drvdata(pdev, crypto_dd);
+
+#if !USE_BUSY_POLLING
+ err = devm_request_irq(dev, crypto_dd->irq, aml_crypto_dev_irq,
+ IRQF_SHARED, "aml-aes", crypto_dd);
+ if (err) {
+ dev_err(dev, "unable to request aes irq.\n");
+ err = -EINVAL;
+ goto error;
+ }
+#endif
+ err = misc_register(&aml_crypto_device);
+ if (unlikely(err)) {
+ dev_err(dev, "registration of /dev/aml_crypto failed\n");
+ err = -EPERM;
+ goto error;
+ }
+
+ dev_info(dev, "Aml crypto device\n");
+
+ return err;
+
+error:
+ dev_err(dev, "initialization failed.\n");
+
+ return err;
+}
+
+static int aml_crypto_dev_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ static struct aml_crypto_dev *dd;
+ const struct of_device_id *match;
+
+ dd = platform_get_drvdata(pdev);
+ if (!dd)
+ return -ENODEV;
+ match = of_match_device(aml_crypto_dev_dt_match, &pdev->dev);
+ if (!match) {
+ dev_err(dev, "%s: cannot find match dt\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static struct platform_driver aml_crypto_dev_driver = {
+ .probe = aml_crypto_dev_probe,
+ .remove = aml_crypto_dev_remove,
+ .driver = {
+ .name = "aml_crypto_dev",
+ .owner = THIS_MODULE,
+ .of_match_table = aml_crypto_dev_dt_match,
+ },
+};
+
+module_platform_driver(aml_crypto_dev_driver);
+
+MODULE_DESCRIPTION("Aml crypto device for hw acceleration support.");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("matthew.shyu <matthew.shyu@amlogic.com>");
*
*/
-#ifndef _AML_CRYPTO_H_
-#define _AML_CRYPTO_H_
+#ifndef _AML_CRYPTO_DMA_H_
+#define _AML_CRYPTO_DMA_H_
#include <linux/io.h>
/* Reserved 4096 bytes and table is 12 bytes each */
#define MAX_NUM_TABLES 341
+#define DMA_BLOCK_MODE_SIZE (512)
+
enum GXL_DMA_REG_OFFSETS {
GXL_DMA_T0 = 0x00,
GXL_DMA_T1 = 0x01,
return 0;
}
+static void aml_sha_clean_key(struct ahash_request *req)
+{
+ struct aml_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
+ struct aml_sha_dev *dd = tctx->dd;
+ struct dma_dsc *dsc = 0;
+ dma_addr_t dma_key = 0;
+ dma_addr_t dma_descript_tab = 0;
+ u8 *key = 0;
+
+ dsc = dmam_alloc_coherent(dd->dev, sizeof(struct dma_dsc),
+ &dma_descript_tab, GFP_ATOMIC | GFP_DMA);
+ if (!dsc)
+ return;
+
+ key = dmam_alloc_coherent(dd->dev, tctx->keylen,
+ &dma_key, GFP_ATOMIC | GFP_DMA);
+ if (!key) {
+ dmam_free_coherent(dd->dev, sizeof(struct dma_dsc),
+ dsc, dma_descript_tab);
+ return;
+ }
+
+ memset(key, 0, tctx->keylen);
+
+ dsc[0].src_addr = (u32)dma_key;
+ dsc[0].tgt_addr = 0;
+ dsc[0].dsc_cfg.d32 = 0;
+ dsc[0].dsc_cfg.b.length = tctx->keylen;
+ dsc[0].dsc_cfg.b.mode = MODE_KEY;
+ dsc[0].dsc_cfg.b.eoc = 1;
+ dsc[0].dsc_cfg.b.owner = 1;
+
+ aml_dma_debug(dsc, 1, __func__, dd->thread, dd->status);
+
+ aml_write_crypto_reg(dd->thread,
+ (uintptr_t)dma_descript_tab | 2);
+ while (aml_read_crypto_reg(dd->status) == 0)
+ ;
+ aml_write_crypto_reg(dd->status, 0xf);
+
+ dmam_free_coherent(dd->dev, tctx->keylen, key, dma_key);
+ dmam_free_coherent(dd->dev, sizeof(struct dma_dsc),
+ dsc, dma_descript_tab);
+}
+
static int aml_sha_finish(struct ahash_request *req)
{
struct aml_sha_reqctx *ctx = ahash_request_ctx(req);
struct aml_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
int err = 0;
- if (tctx->is_hmac)
+ if (tctx->is_hmac) {
err = aml_sha_finish_hmac(req);
+ aml_sha_clean_key(req);
+ }
aml_sha_copy_ready_hash(req);
kfree(ctx->digest);
return -EINVAL;
}
- memcpy(key_iv, key, keylen);
+ if (key)
+ memcpy(key_iv, key, keylen);
if (iv) {
memcpy(piv, iv, 8);
return; /* DMA started. Not fininishing. */
}
+ if (dd->ctx->kte < 0)
+ err = set_tdes_key_iv(dd, NULL, 0, NULL);
+
aml_tdes_finish_req(dd, err);
aml_tdes_handle_queue(dd, NULL);
}
reboot.
Enable if doubt.
+config AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS
+ bool "Amlogic ddr scrambler keypreserve mode for pstore debug"
+ depends on AMLOGIC_DEBUG
+ depends on PSTORE
+ default n
+ help
+ Preserve ddr scrambler key to dump kernel console message and panic/oops
+ message.
obj-$(CONFIG_AMLOGIC_DEBUG_LOCKUP) += debug_lockup.o
obj-$(CONFIG_AMLOGIC_DEBUG_ATRACE) += meson_atrace.o
obj-$(CONFIG_AMLOGIC_DEBUG_FTRACE_PSTORE)+= debug_ftrace_ramoops.o
+obj-$(CONFIG_AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS)+= debug_scrambler_ramoops.o
if (!strcmp(reboot_mode, "cold_boot"))
return;
+ if (!strcmp(reboot_mode, "normal"))
+ return;
+
if (!ramoops_io_dump)
return;
--- /dev/null
+/*
+ * drivers/amlogic/debug/debug_scrambler_ramoops.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+int scrambler_ramoops_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ void __iomem *vaddr;
+ unsigned int val;
+
+ np = of_find_compatible_node(NULL, NULL,
+ "amlogic, ddr-scrambler-preserve");
+ if (!np)
+ return -ENODEV;
+
+ if (of_address_to_resource(np, 0, &res))
+ return -ENODEV;
+
+ vaddr = ioremap(res.start, resource_size(&res));
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ val = readl(vaddr);
+ val = val | 0x1;
+ writel(val, vaddr);
+
+ iounmap(vaddr);
+ pr_warn("%s preserve startup key\n", __func__);
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (C) 2014 Endless Mobile
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- * Written by:
- * Jasper St. Pierre <jstpierre@mecheye.net>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of_graph.h>
-#include <linux/component.h>
-
-#include <drm/drmP.h>
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_flip_work.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_plane_helper.h>
-#include <drm/drm_gem_cma_helper.h>
-#include <drm/drm_fb_cma_helper.h>
-#include <drm/drm_rect.h>
-#include <drm/drm_fb_helper.h>
-
-#include "am_meson_fbdev.h"
-#ifdef CONFIG_DRM_MESON_USE_ION
-#include "am_meson_gem.h"
-#include "am_meson_fb.h"
-#endif
-#include "am_meson_drv.h"
-
-
-#define DRIVER_NAME "meson"
-#define DRIVER_DESC "Amlogic Meson DRM driver"
-
-
-static void am_meson_fb_output_poll_changed(struct drm_device *dev)
-{
-#ifdef CONFIG_DRM_MESON_EMULATE_FBDEV
- struct meson_drm *priv = dev->dev_private;
-
- drm_fbdev_cma_hotplug_event(priv->fbdev);
-#endif
-}
-
-static const struct drm_mode_config_funcs meson_mode_config_funcs = {
- .output_poll_changed = am_meson_fb_output_poll_changed,
- .atomic_check = drm_atomic_helper_check,
- .atomic_commit = drm_atomic_helper_commit,
-#ifdef CONFIG_DRM_MESON_USE_ION
- .fb_create = am_meson_fb_create,
-#else
- .fb_create = drm_fb_cma_create,
-#endif
-};
-
-int am_meson_register_crtc_funcs(struct drm_crtc *crtc,
- const struct meson_crtc_funcs *crtc_funcs)
-{
- int pipe = drm_crtc_index(crtc);
- struct meson_drm *priv = crtc->dev->dev_private;
-
- if (pipe >= MESON_MAX_CRTC)
- return -EINVAL;
-
- priv->crtc_funcs[pipe] = crtc_funcs;
-
- return 0;
-}
-EXPORT_SYMBOL(am_meson_register_crtc_funcs);
-
-void am_meson_unregister_crtc_funcs(struct drm_crtc *crtc)
-{
- int pipe = drm_crtc_index(crtc);
- struct meson_drm *priv = crtc->dev->dev_private;
-
- if (pipe >= MESON_MAX_CRTC)
- return;
-
- priv->crtc_funcs[pipe] = NULL;
-}
-EXPORT_SYMBOL(am_meson_unregister_crtc_funcs);
-
-static int am_meson_enable_vblank(struct drm_device *dev, unsigned int crtc)
-{
- struct meson_drm *priv = dev->dev_private;
-
- if (crtc > MESON_MAX_CRTC)
- return -EBADFD;
-
- return priv->crtc_funcs[crtc]->enable_vblank(priv->crtc);
-}
-
-static void am_meson_disable_vblank(struct drm_device *dev, unsigned int crtc)
-{
- struct meson_drm *priv = dev->dev_private;
-
- if (crtc > MESON_MAX_CRTC)
- return;
-
- return priv->crtc_funcs[crtc]->disable_vblank(priv->crtc);
-}
-
-static void am_meson_load(struct drm_device *dev)
-{
-#if 0
- struct meson_drm *priv = dev->dev_private;
- struct drm_crtc *crtc = priv->crtc;
- int pipe = drm_crtc_index(crtc);
-
- if (priv->crtc_funcs[pipe] &&
- priv->crtc_funcs[pipe]->loader_protect)
- priv->crtc_funcs[pipe]->loader_protect(crtc, true);
-#endif
-}
-
-#ifdef CONFIG_DRM_MESON_USE_ION
-static const struct drm_ioctl_desc meson_ioctls[] = {
- DRM_IOCTL_DEF_DRV(MESON_GEM_CREATE, am_meson_gem_create_ioctl,
- DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
-};
-#endif
-
-static const struct file_operations fops = {
- .owner = THIS_MODULE,
- .open = drm_open,
- .release = drm_release,
- .unlocked_ioctl = drm_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = drm_compat_ioctl,
-#endif
- .poll = drm_poll,
- .read = drm_read,
- .llseek = no_llseek,
-#ifdef CONFIG_DRM_MESON_USE_ION
- .mmap = am_meson_gem_mmap,
-#else
- .mmap = drm_gem_cma_mmap,
-#endif
-};
-
-static struct drm_driver meson_driver = {
- /*driver_features setting move to probe functions*/
- .driver_features = 0,
- /* Vblank */
- .enable_vblank = am_meson_enable_vblank,
- .disable_vblank = am_meson_disable_vblank,
- .get_vblank_counter = drm_vblank_no_hw_counter,
-
-#ifdef CONFIG_DRM_MESON_USE_ION
- /* PRIME Ops */
- .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
- .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
-
- .gem_prime_export = drm_gem_prime_export,
- .gem_prime_get_sg_table = am_meson_gem_prime_get_sg_table,
-
- .gem_prime_import = drm_gem_prime_import,
- /*
- * If gem_prime_import_sg_table is NULL,only buffer created
- * by meson driver can be imported ok.
- */
- /*.gem_prime_import_sg_table = am_meson_gem_prime_import_sg_table,*/
-
- .gem_prime_vmap = am_meson_gem_prime_vmap,
- .gem_prime_vunmap = am_meson_gem_prime_vunmap,
- .gem_prime_mmap = am_meson_gem_prime_mmap,
-
- /* GEM Ops */
- .dumb_create = am_meson_gem_dumb_create,
- .dumb_destroy = am_meson_gem_dumb_destroy,
- .dumb_map_offset = am_meson_gem_dumb_map_offset,
- .gem_free_object_unlocked = am_meson_gem_object_free,
- .gem_vm_ops = &drm_gem_cma_vm_ops,
- .ioctls = meson_ioctls,
- .num_ioctls = ARRAY_SIZE(meson_ioctls),
-#else
- /* PRIME Ops */
- .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
- .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
- .gem_prime_import = drm_gem_prime_import,
- .gem_prime_export = drm_gem_prime_export,
- .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
- .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
- .gem_prime_vmap = drm_gem_cma_prime_vmap,
- .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
- .gem_prime_mmap = drm_gem_cma_prime_mmap,
-
- /* GEM Ops */
- .dumb_create = drm_gem_cma_dumb_create,
- .dumb_destroy = drm_gem_dumb_destroy,
- .dumb_map_offset = drm_gem_cma_dumb_map_offset,
- .gem_free_object_unlocked = drm_gem_cma_free_object,
- .gem_vm_ops = &drm_gem_cma_vm_ops,
-#endif
-
- /* Misc */
- .fops = &fops,
- .name = DRIVER_NAME,
- .desc = DRIVER_DESC,
- .date = "20180321",
- .major = 1,
- .minor = 0,
-};
-
-static int am_meson_drm_bind(struct device *dev)
-{
- struct meson_drm *priv;
- struct drm_device *drm;
- int ret = 0;
-
- meson_driver.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
- DRIVER_MODESET | DRIVER_PRIME |
- DRIVER_ATOMIC | DRIVER_IRQ_SHARED;
-
- drm = drm_dev_alloc(&meson_driver, dev);
- if (!drm)
- return -ENOMEM;
-
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- ret = -ENOMEM;
- goto err_free1;
- }
- drm->dev_private = priv;
- priv->drm = drm;
- priv->dev = dev;
- dev_set_drvdata(dev, priv);
-
-#ifdef CONFIG_DRM_MESON_USE_ION
- ret = am_meson_gem_create(priv);
- if (ret)
- goto err_free2;
-#endif
-
- drm_mode_config_init(drm);
-
- /* Try to bind all sub drivers. */
- ret = component_bind_all(dev, drm);
- if (ret)
- goto err_gem;
- DRM_INFO("mode_config crtc number:%d\n", drm->mode_config.num_crtc);
-
- ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
- if (ret)
- goto err_unbind_all;
-
- drm_mode_config_reset(drm);
- drm->mode_config.max_width = 8192;
- drm->mode_config.max_height = 8192;
- drm->mode_config.funcs = &meson_mode_config_funcs;
- /*
- * irq will init in each crtc, just mark the enable flag here.
- */
- drm->irq_enabled = true;
-
- drm_kms_helper_poll_init(drm);
-
- am_meson_load(drm);
-
-#ifdef CONFIG_DRM_MESON_EMULATE_FBDEV
- ret = am_meson_drm_fbdev_init(drm);
- if (ret)
- goto err_poll_fini;
- drm->mode_config.allow_fb_modifiers = true;
-#endif
-
- ret = drm_dev_register(drm, 0);
- if (ret)
- goto err_fbdev_fini;
-
- return 0;
-
-
-err_fbdev_fini:
-#ifdef CONFIG_DRM_MESON_EMULATE_FBDEV
- am_meson_drm_fbdev_fini(drm);
-err_poll_fini:
-#endif
- drm_kms_helper_poll_fini(drm);
- drm->irq_enabled = false;
- drm_vblank_cleanup(drm);
-err_unbind_all:
- component_unbind_all(dev, drm);
-err_gem:
- drm_mode_config_cleanup(drm);
-#ifdef CONFIG_DRM_MESON_USE_ION
- am_meson_gem_cleanup(drm->dev_private);
-err_free2:
-#endif
- drm->dev_private = NULL;
- dev_set_drvdata(dev, NULL);
-err_free1:
- drm_dev_unref(drm);
-
- return ret;
-}
-
-static void am_meson_drm_unbind(struct device *dev)
-{
- struct drm_device *drm = dev_get_drvdata(dev);
-
- drm_dev_unregister(drm);
-#ifdef CONFIG_DRM_MESON_EMULATE_FBDEV
- am_meson_drm_fbdev_fini(drm);
-#endif
- drm_kms_helper_poll_fini(drm);
- drm->irq_enabled = false;
- drm_vblank_cleanup(drm);
- component_unbind_all(dev, drm);
- drm_mode_config_cleanup(drm);
-#ifdef CONFIG_DRM_MESON_USE_ION
- am_meson_gem_cleanup(drm->dev_private);
-#endif
- drm->dev_private = NULL;
- dev_set_drvdata(dev, NULL);
- drm_dev_unref(drm);
-}
-
-static int compare_of(struct device *dev, void *data)
-{
- struct device_node *np = data;
-
- return dev->of_node == np;
-}
-
-static void am_meson_add_endpoints(struct device *dev,
- struct component_match **match,
- struct device_node *port)
-{
- struct device_node *ep, *remote;
-
- for_each_child_of_node(port, ep) {
- remote = of_graph_get_remote_port_parent(ep);
- if (!remote || !of_device_is_available(remote)) {
- of_node_put(remote);
- continue;
- } else if (!of_device_is_available(remote->parent)) {
- of_node_put(remote);
- continue;
- }
- component_match_add(dev, match, compare_of, remote);
- of_node_put(remote);
- }
-}
-
-static const struct component_master_ops am_meson_drm_ops = {
- .bind = am_meson_drm_bind,
- .unbind = am_meson_drm_unbind,
-};
-
-static bool am_meson_drv_use_osd(void)
-{
- struct device_node *node;
- const char *str;
- int ret;
-
- node = of_find_node_by_path("/meson-fb");
- if (node) {
- ret = of_property_read_string(node, "status", &str);
- if (ret) {
- DRM_INFO("get 'status' failed:%d\n", ret);
- return false;
- }
-
- if (strcmp(str, "okay") && strcmp(str, "ok")) {
- DRM_INFO("device %s status is %s\n",
- node->name, str);
- } else {
- DRM_INFO("device %s status is %s\n",
- node->name, str);
- return true;
- }
- }
- return false;
-}
-
-static int am_meson_drv_probe_prune(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct meson_drm *priv;
- struct drm_device *drm;
- int ret;
-
- /*driver_features reset to DRIVER_GEM | DRIVER_PRIME, for prune drm*/
- meson_driver.driver_features = DRIVER_GEM | DRIVER_PRIME;
-
- drm = drm_dev_alloc(&meson_driver, dev);
- if (!drm)
- return -ENOMEM;
-
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- ret = -ENOMEM;
- goto err_free1;
- }
- drm->dev_private = priv;
- priv->drm = drm;
- priv->dev = dev;
-
- platform_set_drvdata(pdev, priv);
-
-#ifdef CONFIG_DRM_MESON_USE_ION
- ret = am_meson_gem_create(priv);
- if (ret)
- goto err_free2;
-#endif
-
- ret = drm_dev_register(drm, 0);
- if (ret)
- goto err_gem;
-
- return 0;
-
-err_gem:
-#ifdef CONFIG_DRM_MESON_USE_ION
- am_meson_gem_cleanup(drm->dev_private);
-err_free2:
-#endif
- drm->dev_private = NULL;
- platform_set_drvdata(pdev, NULL);
-err_free1:
- drm_dev_unref(drm);
- return ret;
-}
-
-static int am_meson_drv_remove_prune(struct platform_device *pdev)
-{
- struct drm_device *drm = platform_get_drvdata(pdev);
-
- drm_dev_unregister(drm);
-#ifdef CONFIG_DRM_MESON_USE_ION
- am_meson_gem_cleanup(drm->dev_private);
-#endif
- drm->dev_private = NULL;
- platform_set_drvdata(pdev, NULL);
- drm_dev_unref(drm);
-
- return 0;
-}
-
-static int am_meson_drv_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *port;
- struct component_match *match = NULL;
- int i;
-
- if (am_meson_drv_use_osd())
- return am_meson_drv_probe_prune(pdev);
-
- if (!np)
- return -ENODEV;
-
- /*
- * Bind the crtc ports first, so that
- * drm_of_find_possible_crtcs called from encoder .bind callbacks
- * works as expected.
- */
- for (i = 0;; i++) {
- port = of_parse_phandle(np, "ports", i);
- if (!port)
- break;
-
- if (!of_device_is_available(port->parent)) {
- of_node_put(port);
- continue;
- }
-
- component_match_add(dev, &match, compare_of, port->parent);
- of_node_put(port);
- }
-
- if (i == 0) {
- dev_err(dev, "missing 'ports' property.\n");
- return -ENODEV;
- }
-
- if (!match) {
- dev_err(dev, "No available vout found for display-subsystem.\n");
- return -ENODEV;
- }
-
- /*
- * For each bound crtc, bind the encoders attached to its
- * remote endpoint.
- */
- for (i = 0;; i++) {
- port = of_parse_phandle(np, "ports", i);
- if (!port)
- break;
-
- if (!of_device_is_available(port->parent)) {
- of_node_put(port);
- continue;
- }
-
- am_meson_add_endpoints(dev, &match, port);
- of_node_put(port);
- }
-
- return component_master_add_with_match(dev, &am_meson_drm_ops, match);
-}
-
-static int am_meson_drv_remove(struct platform_device *pdev)
-{
- if (am_meson_drv_use_osd())
- return am_meson_drv_remove_prune(pdev);
-
- component_master_del(&pdev->dev, &am_meson_drm_ops);
- return 0;
-}
-
-static const struct of_device_id am_meson_drm_dt_match[] = {
- { .compatible = "amlogic,drm-subsystem" },
- {}
-};
-MODULE_DEVICE_TABLE(of, am_meson_drm_dt_match);
-
-static struct platform_driver am_meson_drm_platform_driver = {
- .probe = am_meson_drv_probe,
- .remove = am_meson_drv_remove,
- .driver = {
- .owner = THIS_MODULE,
- .name = DRIVER_NAME,
- .of_match_table = am_meson_drm_dt_match,
- },
-};
-
-module_platform_driver(am_meson_drm_platform_driver);
-
-MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
-MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
-MODULE_AUTHOR("MultiMedia Amlogic <multimedia-sh@amlogic.com>");
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __AM_MESON_DRV_H
-#define __AM_MESON_DRV_H
-
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <drm/drmP.h>
-#ifdef CONFIG_DRM_MESON_USE_ION
-#include <ion/ion_priv.h>
-#endif
-
-#define MESON_MAX_CRTC 2
-
-/*
- * Amlogic drm private crtc funcs.
- * @loader_protect: protect loader logo crtc's power
- * @enable_vblank: enable crtc vblank irq.
- * @disable_vblank: disable crtc vblank irq.
- */
-struct meson_crtc_funcs {
- int (*loader_protect)(struct drm_crtc *crtc, bool on);
- int (*enable_vblank)(struct drm_crtc *crtc);
- void (*disable_vblank)(struct drm_crtc *crtc);
-};
-
-struct meson_drm {
- struct device *dev;
-
- struct drm_device *drm;
- struct drm_crtc *crtc;
- const struct meson_crtc_funcs *crtc_funcs[MESON_MAX_CRTC];
- struct drm_fbdev_cma *fbdev;
- struct drm_fb_helper *fbdev_helper;
- struct drm_gem_object *fbdev_bo;
- struct drm_plane *primary_plane;
- struct drm_plane *cursor_plane;
-
-#ifdef CONFIG_DRM_MESON_USE_ION
- struct ion_client *gem_client;
-#endif
-};
-
-static inline int meson_vpu_is_compatible(struct meson_drm *priv,
- const char *compat)
-{
- return of_device_is_compatible(priv->dev->of_node, compat);
-}
-
-extern int am_meson_register_crtc_funcs(struct drm_crtc *crtc,
- const struct meson_crtc_funcs *crtc_funcs);
-extern void am_meson_unregister_crtc_funcs(struct drm_crtc *crtc);
-
-#endif /* __AM_MESON_DRV_H */
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_fb.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#include <drm/drm_atomic_helper.h>
-
-#include "am_meson_fb.h"
-
-#define to_am_meson_fb(x) container_of(x, struct am_meson_fb, base)
-
-void am_meson_fb_destroy(struct drm_framebuffer *fb)
-{
- struct am_meson_fb *meson_fb = to_am_meson_fb(fb);
-
- drm_gem_object_unreference_unlocked(&meson_fb->bufp->base);
- drm_framebuffer_cleanup(fb);
- kfree(meson_fb);
-}
-
-int am_meson_fb_create_handle(struct drm_framebuffer *fb,
- struct drm_file *file_priv,
- unsigned int *handle)
-{
- struct am_meson_fb *meson_fb = to_am_meson_fb(fb);
-
- return drm_gem_handle_create(file_priv,
- &meson_fb->bufp->base, handle);
-}
-
-struct drm_framebuffer_funcs am_meson_fb_funcs = {
- .create_handle = am_meson_fb_create_handle, //must for fbdev emulate
- .destroy = am_meson_fb_destroy,
-};
-
-struct drm_framebuffer *
-am_meson_fb_alloc(struct drm_device *dev,
- struct drm_mode_fb_cmd2 *mode_cmd,
- struct drm_gem_object *obj)
-{
- struct am_meson_fb *meson_fb;
- struct am_meson_gem_object *meson_gem;
- int ret = 0;
-
- meson_fb = kzalloc(sizeof(*meson_fb), GFP_KERNEL);
- if (!meson_fb)
- return ERR_PTR(-ENOMEM);
-
- meson_gem = container_of(obj, struct am_meson_gem_object, base);
- meson_fb->bufp = meson_gem;
-
- drm_helper_mode_fill_fb_struct(&meson_fb->base, mode_cmd);
-
- ret = drm_framebuffer_init(dev, &meson_fb->base,
- &am_meson_fb_funcs);
- if (ret) {
- dev_err(dev->dev, "Failed to initialize framebuffer: %d\n",
- ret);
- goto err_free_fb;
- }
-
- return &meson_fb->base;
-
-err_free_fb:
- kfree(meson_fb);
- return ERR_PTR(ret);
-}
-
-struct drm_framebuffer *am_meson_fb_create(struct drm_device *dev,
- struct drm_file *file_priv,
- const struct drm_mode_fb_cmd2 *mode_cmd)
-{
- struct am_meson_fb *meson_fb = 0;
- struct drm_gem_object *obj = 0;
- struct am_meson_gem_object *meson_gem;
- int ret;
-
- meson_fb = kzalloc(sizeof(*meson_fb), GFP_KERNEL);
- if (!meson_fb)
- return ERR_PTR(-ENOMEM);
-
- /* only support one handle now.*/
- obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
- if (!obj) {
- dev_err(dev->dev, "Failed to lookup GEM handle\n");
- kfree(meson_fb);
- return ERR_PTR(-ENOMEM);
- }
-
- meson_gem = container_of(obj, struct am_meson_gem_object, base);
- meson_fb->bufp = meson_gem;
-
- drm_helper_mode_fill_fb_struct(&meson_fb->base, mode_cmd);
-
- ret = drm_framebuffer_init(dev, &meson_fb->base, &am_meson_fb_funcs);
- if (ret) {
- dev_err(dev->dev,
- "Failed to initialize framebuffer: %d\n",
- ret);
- drm_gem_object_unreference(obj);
- kfree(meson_fb);
- return ERR_PTR(ret);
- }
-
- return &meson_fb->base;
-}
-
-struct drm_framebuffer *
-am_meson_drm_framebuffer_init(struct drm_device *dev,
- struct drm_mode_fb_cmd2 *mode_cmd,
- struct drm_gem_object *obj)
-{
- struct drm_framebuffer *fb;
-
- fb = am_meson_fb_alloc(dev, mode_cmd, obj);
- if (IS_ERR(fb))
- return NULL;
-
- return fb;
-}
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_fb.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __AM_MESON_FB_H
-#define __AM_MESON_FB_H
-#include <drm/drmP.h>
-#include <drm/drm_gem.h>
-#include <drm/drm_framebuffer.h>
-#include <drm/drm_modeset_helper.h>
-
-#include "am_meson_gem.h"
-
-struct am_meson_fb {
- struct drm_framebuffer base;
- struct am_meson_gem_object *bufp;
-};
-
-struct drm_framebuffer *am_meson_fb_create(struct drm_device *dev,
- struct drm_file *file_priv,
- const struct drm_mode_fb_cmd2 *mode_cmd);
-struct drm_framebuffer *am_meson_drm_framebuffer_init(
- struct drm_device *dev,
- struct drm_mode_fb_cmd2 *mode_cmd,
- struct drm_gem_object *obj);
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_fbdev.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <drm/drm.h>
-#include <drm/drmP.h>
-#include <drm/drm_fb_helper.h>
-#include <drm/drm_crtc_helper.h>
-
-#include "am_meson_drv.h"
-#include "am_meson_gem.h"
-#include "am_meson_fb.h"
-#include "am_meson_fbdev.h"
-
-#define PREFERRED_BPP 32
-#define MESON_DRM_MAX_CONNECTOR 2
-
-static int am_meson_fbdev_mmap(struct fb_info *info,
- struct vm_area_struct *vma)
-{
- struct drm_fb_helper *helper = info->par;
- struct meson_drm *private;
- struct am_meson_gem_object *meson_gem;
-
- private = helper->dev->dev_private;
- meson_gem = container_of(private->fbdev_bo,
- struct am_meson_gem_object, base);
-
- return am_meson_gem_object_mmap(meson_gem, vma);
-}
-
-static int am_meson_drm_fbdev_sync(struct fb_info *info)
-{
- return 0;
-}
-
-static int am_meson_drm_fbdev_ioctl(struct fb_info *info,
- unsigned int cmd, unsigned long arg)
-{
- return 0;
-}
-
-static struct fb_ops meson_drm_fbdev_ops = {
- .owner = THIS_MODULE,
- .fb_mmap = am_meson_fbdev_mmap,
- .fb_fillrect = drm_fb_helper_cfb_fillrect,
- .fb_copyarea = drm_fb_helper_cfb_copyarea,
- .fb_imageblit = drm_fb_helper_cfb_imageblit,
- .fb_check_var = drm_fb_helper_check_var,
- .fb_set_par = drm_fb_helper_set_par,
- .fb_blank = drm_fb_helper_blank,
- .fb_pan_display = drm_fb_helper_pan_display,
- .fb_setcmap = drm_fb_helper_setcmap,
- .fb_sync = am_meson_drm_fbdev_sync,
- .fb_ioctl = am_meson_drm_fbdev_ioctl,
-#ifdef CONFIG_COMPAT
- .fb_compat_ioctl = am_meson_drm_fbdev_ioctl,
-#endif
-};
-
-static int am_meson_drm_fbdev_create(struct drm_fb_helper *helper,
- struct drm_fb_helper_surface_size *sizes)
-{
- struct meson_drm *private = helper->dev->dev_private;
- struct drm_mode_fb_cmd2 mode_cmd = { 0 };
- struct drm_device *dev = helper->dev;
- struct am_meson_gem_object *meson_obj;
- struct drm_framebuffer *fb;
- struct ion_client *client;
- unsigned int bytes_per_pixel;
- unsigned long offset;
- struct fb_info *fbi;
- size_t size;
- int ret;
-
- bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
-
- mode_cmd.width = sizes->surface_width;
- mode_cmd.height = sizes->surface_height;
- mode_cmd.pitches[0] = ALIGN(sizes->surface_width * bytes_per_pixel, 64);
- mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
- sizes->surface_depth);
-
- size = mode_cmd.pitches[0] * mode_cmd.height;
-
- client = (struct ion_client *)private->gem_client;
- meson_obj = am_meson_gem_object_create(dev, 0, size, client);
- if (IS_ERR(meson_obj))
- return -ENOMEM;
-
- private->fbdev_bo = &meson_obj->base;
-
- fbi = drm_fb_helper_alloc_fbi(helper);
- if (IS_ERR(fbi)) {
- dev_err(dev->dev, "Failed to create framebuffer info.\n");
- ret = PTR_ERR(fbi);
- goto err_meson_gem_free_object;
- }
-
- helper->fb = am_meson_drm_framebuffer_init(dev, &mode_cmd,
- private->fbdev_bo);
- if (IS_ERR(helper->fb)) {
- dev_err(dev->dev, "Failed to allocate DRM framebuffer.\n");
- ret = PTR_ERR(helper->fb);
- goto err_release_fbi;
- }
-
- fbi->par = helper;
- fbi->flags = FBINFO_FLAG_DEFAULT;
- fbi->fbops = &meson_drm_fbdev_ops;
-
- fb = helper->fb;
- drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->depth);
- drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height);
-
- offset = fbi->var.xoffset * bytes_per_pixel;
- offset += fbi->var.yoffset * fb->pitches[0];
-
- dev->mode_config.fb_base = 0;
- fbi->screen_size = size;
- fbi->fix.smem_len = size;
-
- DRM_DEBUG_KMS("FB [%dx%d]-%d offset=%ld size=%zu\n",
- fb->width, fb->height, fb->depth, offset, size);
-
- fbi->skip_vt_switch = true;
-
- return 0;
-
-err_release_fbi:
- drm_fb_helper_release_fbi(helper);
-err_meson_gem_free_object:
- am_meson_gem_object_free(&meson_obj->base);
- return ret;
-}
-
-static const struct drm_fb_helper_funcs meson_drm_fb_helper_funcs = {
- .fb_probe = am_meson_drm_fbdev_create,
-};
-
-int am_meson_drm_fbdev_init(struct drm_device *dev)
-{
- struct meson_drm *private = dev->dev_private;
- struct drm_fb_helper *helper;
- unsigned int num_crtc;
- int ret;
-
- if (!dev->mode_config.num_crtc || !dev->mode_config.num_connector)
- return -EINVAL;
-
- num_crtc = dev->mode_config.num_crtc;
-
- helper = devm_kzalloc(dev->dev, sizeof(*helper), GFP_KERNEL);
- if (!helper)
- return -ENOMEM;
-
- drm_fb_helper_prepare(dev, helper, &meson_drm_fb_helper_funcs);
-
- ret = drm_fb_helper_init(dev, helper, num_crtc,
- MESON_DRM_MAX_CONNECTOR);
- if (ret < 0) {
- dev_err(dev->dev, "Failed to initialize drm fb helper - %d.\n",
- ret);
- goto err_free;
- }
-
- ret = drm_fb_helper_single_add_all_connectors(helper);
- if (ret < 0) {
- dev_err(dev->dev, "Failed to add connectors - %d.\n", ret);
- goto err_drm_fb_helper_fini;
- }
-
- ret = drm_fb_helper_initial_config(helper, PREFERRED_BPP);
- if (ret < 0) {
- dev_err(dev->dev, "Failed to set initial hw config - %d.\n",
- ret);
- goto err_drm_fb_helper_fini;
- }
-
- private->fbdev_helper = helper;
-
- return 0;
-
-err_drm_fb_helper_fini:
- drm_fb_helper_fini(helper);
-err_free:
- kfree(fbdev_cma);
- return ret;
-}
-
-void am_meson_drm_fbdev_fini(struct drm_device *dev)
-{
- struct meson_drm *private = dev->dev_private;
- struct drm_fb_helper *helper = private->fbdev_helper;
-
- if (!helper)
- return;
-
- drm_fb_helper_unregister_fbi(helper);
- drm_fb_helper_release_fbi(helper);
-
- if (helper->fb)
- drm_framebuffer_unreference(helper->fb);
-
- drm_fb_helper_fini(helper);
-}
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_fbdev.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __AM_MESON_FBDEV_H
-#define __AM_MESON_FBDEV_H
-
-#ifdef CONFIG_DRM_MESON_EMULATE_FBDEV
-int am_meson_drm_fbdev_init(struct drm_device *dev);
-void am_meson_drm_fbdev_fini(struct drm_device *dev);
-#endif
-
-#endif /* __AM_MESON_FBDEV_H */
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_gem.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#include <drm/drmP.h>
-#include <drm/drm_gem.h>
-#include <drm/drm_vma_manager.h>
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/dma-buf.h>
-#include <linux/meson_ion.h>
-#include <ion/ion.h>
-
-#include "am_meson_gem.h"
-
-#define to_am_meson_gem_obj(x) container_of(x, struct am_meson_gem_object, base)
-
-static int am_meson_gem_alloc_ion_buff(
- struct ion_client *client,
- struct am_meson_gem_object *meson_gem_obj,
- int flags)
-{
- struct ion_handle *handle;
- bool bscatter = false;
-
- if (!client)
- return -EINVAL;
-
- if (!meson_gem_obj)
- return -EINVAL;
-
- //check flags to set different ion heap type.
- //if flags is set to 0, need to use ion dma buffer.
- if (((flags & (BO_USE_SCANOUT | BO_USE_CURSOR)) != 0)
- || (flags == 0)) {
- handle = ion_alloc(client, meson_gem_obj->base.size,
- 0, (1 << ION_HEAP_TYPE_DMA), 0);
- }
- else {
- handle = ion_alloc(client, meson_gem_obj->base.size,
- 0, (1 << ION_HEAP_TYPE_SYSTEM), 0);
- bscatter = true;
- }
-
- if (IS_ERR(handle)) {
- DRM_ERROR("%s: FAILED, flags:0x%x.\n",
- __func__, flags);
- return -ENOMEM;
- }
-
- meson_gem_obj->handle = handle;
- meson_gem_obj->bscatter = bscatter;
- DRM_DEBUG("%s: allocate handle (%p).\n",
- __func__, meson_gem_obj->handle);
- return 0;
-}
-
-static void am_meson_gem_free_ion_buf(
- struct drm_device *dev,
- struct am_meson_gem_object *meson_gem_obj)
-{
- struct ion_client *client = NULL;
-
- if (meson_gem_obj->handle) {
- DRM_DEBUG("am_meson_gem_free_ion_buf free handle (%p).\n",
- meson_gem_obj->handle);
- client = meson_gem_obj->handle->client;
- ion_free(client, meson_gem_obj->handle);
- meson_gem_obj->handle = NULL;
- } else {
- DRM_ERROR("meson_gem_obj handle is null\n");
- }
-}
-
-struct am_meson_gem_object *am_meson_gem_object_create(
- struct drm_device *dev,
- unsigned int flags,
- unsigned long size,
- struct ion_client *client)
-{
- struct am_meson_gem_object *meson_gem_obj = NULL;
- int ret;
-
- if (!size) {
- DRM_ERROR("invalid size.\n");
- return ERR_PTR(-EINVAL);
- }
-
- size = roundup(size, PAGE_SIZE);
- if (size == 0)
- return ERR_PTR(-EINVAL);
- meson_gem_obj = kzalloc(sizeof(*meson_gem_obj), GFP_KERNEL);
- if (!meson_gem_obj)
- return ERR_PTR(-ENOMEM);
-
- ret = drm_gem_object_init(dev, &meson_gem_obj->base, size);
- if (ret < 0) {
- DRM_ERROR("failed to initialize gem object\n");
- goto error;
- }
-
- ret = am_meson_gem_alloc_ion_buff(client, meson_gem_obj, flags);
- if (ret < 0) {
- drm_gem_object_release(&meson_gem_obj->base);
- goto error;
- }
-
- return meson_gem_obj;
-
-error:
- kfree(meson_gem_obj);
- return ERR_PTR(ret);
-}
-
-void am_meson_gem_object_free(struct drm_gem_object *obj)
-{
- struct am_meson_gem_object *meson_gem_obj = to_am_meson_gem_obj(obj);
-
- DRM_DEBUG("am_meson_gem_object_free %p handle count = %d\n",
- meson_gem_obj, obj->handle_count);
-
- if (obj->import_attach == false)
- am_meson_gem_free_ion_buf(obj->dev, meson_gem_obj);
- else
- DRM_ERROR("Not support import buffer from other driver.\n");
-
- drm_gem_free_mmap_offset(obj);
-
- /* release file pointer to gem object. */
- drm_gem_object_release(obj);
-
- kfree(meson_gem_obj);
- meson_gem_obj = NULL;
-}
-
-int am_meson_gem_object_mmap(
- struct am_meson_gem_object *obj,
- struct vm_area_struct *vma)
-{
- int ret = 0;
- struct ion_buffer *buffer;
-
- /*
- * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
- * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
- * the whole buffer.
- */
- vma->vm_flags &= ~VM_PFNMAP;
- vma->vm_pgoff = 0;
-
- if (obj->base.import_attach) {
- DRM_ERROR("Not support import buffer from other driver.\n");
- } else {
- buffer = obj->handle->buffer;
-
- if (!buffer->heap->ops->map_user) {
- DRM_ERROR("%s:heap does not define map to userspace\n",
- __func__);
- ret = -EINVAL;
- } else {
-
- if (!(buffer->flags & ION_FLAG_CACHED))
- vma->vm_page_prot =
- pgprot_writecombine(vma->vm_page_prot);
-
- mutex_lock(&buffer->lock);
- /* now map it to userspace */
- ret = buffer->heap->ops->map_user(
- buffer->heap, buffer, vma);
- mutex_unlock(&buffer->lock);
- }
- }
-
- if (ret) {
- DRM_ERROR("%s: failure mapping buffer to userspace (%d)\n",
- __func__, ret);
- drm_gem_vm_close(vma);
- }
-
- return ret;
-}
-
-int am_meson_gem_mmap(
- struct file *filp,
- struct vm_area_struct *vma)
-{
- struct drm_gem_object *obj;
- struct am_meson_gem_object *meson_gem_obj;
- int ret;
-
- ret = drm_gem_mmap(filp, vma);
- if (ret)
- return ret;
-
- obj = vma->vm_private_data;
- meson_gem_obj = to_am_meson_gem_obj(obj);
- DRM_DEBUG("am_meson_gem_mmap %p.\n", meson_gem_obj);
-
- ret = am_meson_gem_object_mmap(meson_gem_obj, vma);
-
- return ret;
-}
-
-int am_meson_gem_object_get_phyaddr(
- struct meson_drm *drm,
- struct am_meson_gem_object *meson_gem)
-{
- int addr;
- size_t len;
-
- if (!meson_gem->handle) {
- DRM_INFO("%s handle null\n", __func__);
- return -1;
- }
-
- ion_phys(drm->gem_client, meson_gem->handle,
- (ion_phys_addr_t *)&addr, &len);
-
- return addr;
-}
-EXPORT_SYMBOL(am_meson_gem_object_get_phyaddr);
-
-int am_meson_gem_dumb_create(
- struct drm_file *file_priv,
- struct drm_device *dev,
- struct drm_mode_create_dumb *args)
-{
- int ret = 0;
- struct am_meson_gem_object *meson_gem_obj;
- struct meson_drm *drmdrv = dev->dev_private;
- struct ion_client *client = (struct ion_client *)drmdrv->gem_client;
- int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-
- args->pitch = ALIGN(min_pitch, 64);
- if (args->size < args->pitch * args->height)
- args->size = args->pitch * args->height;
-
- args->size = round_up(args->size, PAGE_SIZE);
-
- meson_gem_obj = am_meson_gem_object_create(
- dev, args->flags, args->size, client);
- if (IS_ERR(meson_gem_obj))
- return PTR_ERR(meson_gem_obj);
-
- /*
- * allocate a id of idr table where the obj is registered
- * and handle has the id what user can see.
- */
- ret = drm_gem_handle_create(file_priv,
- &meson_gem_obj->base, &args->handle);
- /* drop reference from allocate - handle holds it now. */
- drm_gem_object_unreference_unlocked(&meson_gem_obj->base);
- if (ret) {
- DRM_ERROR("%s: create dumb handle failed %d\n",
- __func__, ret);
- return ret;
- }
-
- DRM_DEBUG("%s: create dumb %p with gem handle (0x%x)\n",
- __func__, meson_gem_obj, args->handle);
- return 0;
-}
-
-int am_meson_gem_dumb_destroy(
- struct drm_file *file,
- struct drm_device *dev,
- uint32_t handle)
-{
- DRM_DEBUG("%s: destroy dumb with handle (0x%x)\n", __func__, handle);
- drm_gem_handle_delete(file, handle);
- return 0;
-}
-
-int am_meson_gem_dumb_map_offset(
- struct drm_file *file_priv,
- struct drm_device *dev,
- uint32_t handle,
- uint64_t *offset)
-{
- struct drm_gem_object *obj;
- int ret = 0;
-
- mutex_lock(&dev->struct_mutex);
-
- /*
- * get offset of memory allocated for drm framebuffer.
- * - this callback would be called by user application
- * with DRM_IOCTL_MODE_MAP_DUMB command.
- */
- obj = drm_gem_object_lookup(file_priv, handle);
- if (!obj) {
- DRM_ERROR("failed to lookup gem object.\n");
- ret = -EINVAL;
- goto unlock;
- }
-
- ret = drm_gem_create_mmap_offset(obj);
- if (ret)
- goto out;
-
- *offset = drm_vma_node_offset_addr(&obj->vma_node);
- DRM_DEBUG("offset = 0x%lx\n", (unsigned long)*offset);
-
-out:
- drm_gem_object_unreference(obj);
-unlock:
- mutex_unlock(&dev->struct_mutex);
- return ret;
-}
-
-int am_meson_gem_create_ioctl(
- struct drm_device *dev,
- void *data,
- struct drm_file *file_priv)
-{
- struct am_meson_gem_object *meson_gem_obj;
- struct meson_drm *drmdrv = dev->dev_private;
- struct ion_client *client = (struct ion_client *)drmdrv->gem_client;
- struct drm_meson_gem_create *args = data;
- int ret = 0;
-
- meson_gem_obj = am_meson_gem_object_create(
- dev, args->flags, args->size, client);
- if (IS_ERR(meson_gem_obj))
- return PTR_ERR(meson_gem_obj);
-
- /*
- * allocate a id of idr table where the obj is registered
- * and handle has the id what user can see.
- */
- ret = drm_gem_handle_create(file_priv,
- &meson_gem_obj->base, &args->handle);
- /* drop reference from allocate - handle holds it now. */
- drm_gem_object_unreference_unlocked(&meson_gem_obj->base);
- if (ret) {
- DRM_ERROR("%s: create dumb handle failed %d\n",
- __func__, ret);
- return ret;
- }
-
- DRM_DEBUG("%s: create dumb %p with gem handle (0x%x)\n",
- __func__, meson_gem_obj, args->handle);
- return 0;
-}
-
-
-int am_meson_gem_create(struct meson_drm *drmdrv)
-{
- drmdrv->gem_client = meson_ion_client_create(-1, "meson-gem");
- if (!drmdrv->gem_client) {
- DRM_ERROR("open ion client error\n");
- return -EFAULT;
- }
-
- DRM_DEBUG("open ion client: %p\n", drmdrv->gem_client);
- return 0;
-}
-
-void am_meson_gem_cleanup(struct meson_drm *drmdrv)
-{
- struct ion_client *gem_ion_client = drmdrv->gem_client;
-
- if (gem_ion_client) {
- DRM_DEBUG(" destroy ion client: %p\n", gem_ion_client);
- ion_client_destroy(gem_ion_client);
- }
-}
-
-struct sg_table *am_meson_gem_prime_get_sg_table(
- struct drm_gem_object *obj)
-{
- struct am_meson_gem_object *meson_gem_obj;
- struct sg_table *dst_table = NULL;
- struct scatterlist *dst_sg = NULL;
- struct sg_table *src_table = NULL;
- struct scatterlist *src_sg = NULL;
- int ret, i;
-
- meson_gem_obj = to_am_meson_gem_obj(obj);
- DRM_DEBUG("am_meson_gem_prime_get_sg_table %p.\n", meson_gem_obj);
-
- if (meson_gem_obj->base.import_attach == false) {
- src_table = meson_gem_obj->handle->buffer->sg_table;
- dst_table = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
- if (!dst_table) {
- ret = -ENOMEM;
- return ERR_PTR(ret);
- }
-
- ret = sg_alloc_table(dst_table, src_table->nents, GFP_KERNEL);
- if (ret) {
- kfree(dst_table);
- return ERR_PTR(ret);
- }
-
- dst_sg = dst_table->sgl;
- src_sg = src_table->sgl;
- for (i = 0; i < src_table->nents; i++) {
- sg_set_page(dst_sg, sg_page(src_sg), src_sg->length, 0);
- dst_sg = sg_next(dst_sg);
- src_sg = sg_next(src_sg);
- }
- return dst_table;
- }
- else {
- DRM_ERROR("Not support import buffer from other driver.\n");
- return NULL;
- }
-}
-
-struct drm_gem_object *am_meson_gem_prime_import_sg_table(
- struct drm_device *dev,
- struct dma_buf_attachment *attach,
- struct sg_table *sgt)
-{
- struct am_meson_gem_object *meson_gem_obj;
- int ret;
-
- meson_gem_obj = kzalloc(sizeof(*meson_gem_obj), GFP_KERNEL);
- if (!meson_gem_obj)
- return ERR_PTR(-ENOMEM);
-
- ret = drm_gem_object_init(dev,
- &meson_gem_obj->base,
- attach->dmabuf->size);
- if (ret < 0) {
- DRM_ERROR("failed to initialize gem object\n");
- kfree(meson_gem_obj);
- return ERR_PTR(-ENOMEM);
- }
-
- DRM_DEBUG("%s: %p, sg_table %p\n", __func__, meson_gem_obj, sgt);
- /*meson_gem_obj->sgt = sgt;*/
- return &meson_gem_obj->base;
-}
-
-void *am_meson_gem_prime_vmap(struct drm_gem_object *obj)
-{
- DRM_DEBUG("am_meson_gem_prime_vmap %p.\n", obj);
-
- return NULL;
-}
-
-void am_meson_gem_prime_vunmap(
- struct drm_gem_object *obj,
- void *vaddr)
-{
- DRM_DEBUG("am_meson_gem_prime_vunmap nothing to do.\n");
-}
-
-int am_meson_gem_prime_mmap(
- struct drm_gem_object *obj,
- struct vm_area_struct *vma)
-{
- struct am_meson_gem_object *meson_gem_obj;
- int ret;
-
- ret = drm_gem_mmap_obj(obj, obj->size, vma);
- if (ret < 0)
- return ret;
-
- meson_gem_obj = to_am_meson_gem_obj(obj);
- DRM_DEBUG("am_meson_gem_prime_mmap %p.\n", meson_gem_obj);
-
- return am_meson_gem_object_mmap(meson_gem_obj, vma);
-}
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_gem.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __AM_MESON_GEM_H
-#define __AM_MESON_GEM_H
-#include <drm/drm_gem.h>
-#include <linux/amlogic/meson_drm.h>
-#include <ion/ion_priv.h>
-
-#include "am_meson_drv.h"
-
-struct am_meson_gem_object {
- struct drm_gem_object base;
- unsigned int flags;
-
- /*for buffer create from ion heap */
- struct ion_handle *handle;
- bool bscatter;
-};
-
-/* GEM MANAGER CREATE*/
-int am_meson_gem_create(struct meson_drm *drmdrv);
-
-void am_meson_gem_cleanup(struct meson_drm *drmdrv);
-
-int am_meson_gem_mmap(
- struct file *filp,
- struct vm_area_struct *vma);
-
-/* GEM DUMB OPERATIONS */
-int am_meson_gem_dumb_create(
- struct drm_file *file_priv,
- struct drm_device *dev,
- struct drm_mode_create_dumb *args);
-
-int am_meson_gem_dumb_destroy(
- struct drm_file *file,
- struct drm_device *dev,
- uint32_t handle);
-
-int am_meson_gem_create_ioctl(
- struct drm_device *dev,
- void *data,
- struct drm_file *file_priv);
-
-int am_meson_gem_dumb_map_offset(
- struct drm_file *file_priv,
- struct drm_device *dev,
- uint32_t handle,
- uint64_t *offset);
-
-/* GEM OBJECT OPERATIONS */
-struct am_meson_gem_object *am_meson_gem_object_create(
- struct drm_device *dev, unsigned int flags,
- unsigned long size, struct ion_client *client);
-
-void am_meson_gem_object_free(struct drm_gem_object *gem_obj);
-
-int am_meson_gem_object_mmap(
- struct am_meson_gem_object *obj,
- struct vm_area_struct *vma);
-
-extern int am_meson_gem_object_get_phyaddr(
- struct meson_drm *drm,
- struct am_meson_gem_object *meson_gem);
-
-/* GEM PRIME OPERATIONS */
-struct sg_table *am_meson_gem_prime_get_sg_table(
- struct drm_gem_object *obj);
-
-struct drm_gem_object *am_meson_gem_prime_import_sg_table(
- struct drm_device *dev,
- struct dma_buf_attachment *attach,
- struct sg_table *sgt);
-
-void *am_meson_gem_prime_vmap(
- struct drm_gem_object *obj);
-
-void am_meson_gem_prime_vunmap(
- struct drm_gem_object *obj,
- void *vaddr);
-
-int am_meson_gem_prime_mmap(
- struct drm_gem_object *obj,
- struct vm_area_struct *vma);
-
-#endif /* __AM_MESON_GEM_H */
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_hdcp.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <drm/drm_modeset_helper.h>
-#include <drm/drmP.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
-
-#include <linux/component.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/jiffies.h>
-#include <linux/workqueue.h>
-#include <linux/amlogic/media/vout/vout_notify.h>
-#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
-#include <linux/arm-smccc.h>
-
-#include "am_meson_hdmi.h"
-#include "am_meson_hdcp.h"
-
-static int hdcp_topo_st = -1;
-static int hdmitx_hdcp_opr(unsigned int val)
-{
- struct arm_smccc_res res;
-
- if (val == 1) { /* HDCP14_ENABLE */
- arm_smccc_smc(0x82000010, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 2) { /* HDCP14_RESULT */
- arm_smccc_smc(0x82000011, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- if (val == 0) { /* HDCP14_INIT */
- arm_smccc_smc(0x82000012, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 3) { /* HDCP14_EN_ENCRYPT */
- arm_smccc_smc(0x82000013, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 4) { /* HDCP14_OFF */
- arm_smccc_smc(0x82000014, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 5) { /* HDCP_MUX_22 */
- arm_smccc_smc(0x82000015, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 6) { /* HDCP_MUX_14 */
- arm_smccc_smc(0x82000016, 0, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 7) { /* HDCP22_RESULT */
- arm_smccc_smc(0x82000017, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- if (val == 0xa) { /* HDCP14_KEY_LSTORE */
- arm_smccc_smc(0x8200001a, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- if (val == 0xb) { /* HDCP22_KEY_LSTORE */
- arm_smccc_smc(0x8200001b, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- if (val == 0xc) { /* HDCP22_KEY_SET_DUK */
- arm_smccc_smc(0x8200001c, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- if (val == 0xd) { /* HDCP22_SET_TOPO */
- arm_smccc_smc(0x82000083, hdcp_topo_st, 0, 0, 0, 0, 0, 0, &res);
- }
- if (val == 0xe) { /* HDCP22_GET_TOPO */
- arm_smccc_smc(0x82000084, 0, 0, 0, 0, 0, 0, 0, &res);
- return (unsigned int)((res.a0)&0xffffffff);
- }
- return -1;
-}
-
-static void get_hdcp_bstatus(void)
-{
- int ret1 = 0;
- int ret2 = 0;
-
- hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 1, 0, 1);
- hdmitx_poll_reg(HDMITX_DWC_A_KSVMEMCTRL, (1<<1), 2 * HZ);
- ret1 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_0);
- ret2 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_1);
- hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 0, 0, 1);
- DRM_INFO("BSTATUS0 = 0x%x BSTATUS1 = 0x%x\n", ret1, ret2);
-}
-
-static void hdcp14_events_handle(unsigned long arg)
-{
- struct am_hdmi_tx *am_hdmi = (struct am_hdmi_tx *)arg;
- unsigned int bcaps_6_rp;
- static unsigned int st_flag = -1;
-
- bcaps_6_rp = !!(hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3) & (1 << 6));
- if (st_flag != hdmitx_rd_reg(HDMITX_DWC_A_APIINTSTAT)) {
- st_flag = hdmitx_rd_reg(HDMITX_DWC_A_APIINTSTAT);
- DRM_INFO("hdcp14: instat: 0x%x\n", st_flag);
- }
- if (st_flag & (1 << 7)) {
- hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 1 << 7);
- hdmitx_hdcp_opr(3);
- get_hdcp_bstatus();
- }
-
- if (st_flag & (1 << 1)) {
- hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, (1 << 1));
- hdmitx_wr_reg(HDMITX_DWC_A_KSVMEMCTRL, 0x1);
- hdmitx_poll_reg(HDMITX_DWC_A_KSVMEMCTRL, (1<<1), 2 * HZ);
- if (hdmitx_rd_reg(HDMITX_DWC_A_KSVMEMCTRL) & (1 << 1))
- ;//hdcp_ksv_sha1_calc(hdev); todo
- else {
- DRM_INFO("hdcptx14: KSV List memory access denied\n");
- return;
- }
- hdmitx_wr_reg(HDMITX_DWC_A_KSVMEMCTRL, 0x4);
- }
-
- if (am_hdmi->hdcp_try_times)
- mod_timer(&am_hdmi->hdcp_timer, jiffies + HZ / 100);
- else
- return;
- am_hdmi->hdcp_try_times--;
-}
-
-static void hdcp14_start_timer(struct am_hdmi_tx *am_hdmi)
-{
- static int init_flag;
-
- if (!init_flag) {
- init_flag = 1;
- init_timer(&am_hdmi->hdcp_timer);
- am_hdmi->hdcp_timer.data = (ulong)am_hdmi;
- am_hdmi->hdcp_timer.function = hdcp14_events_handle;
- am_hdmi->hdcp_timer.expires = jiffies + HZ / 100;
- add_timer(&am_hdmi->hdcp_timer);
- am_hdmi->hdcp_try_times = 500;
- return;
- }
- am_hdmi->hdcp_try_times = 500;
- am_hdmi->hdcp_timer.expires = jiffies + HZ / 100;
- mod_timer(&am_hdmi->hdcp_timer, jiffies + HZ / 100);
-}
-
-static int am_hdcp14_enable(struct am_hdmi_tx *am_hdmi)
-{
- am_hdmi->hdcp_mode = HDCP_MODE14;
- hdmitx_ddc_hw_op(DDC_MUX_DDC);
- hdmitx_hdcp_opr(6);
- hdmitx_hdcp_opr(1);
- hdcp14_start_timer(am_hdmi);
- return 0;
-}
-
-static int am_hdcp14_disable(struct am_hdmi_tx *am_hdmi)
-{
- hdmitx_hdcp_opr(4);
- return 0;
-}
-
-static void set_pkf_duk_nonce(void)
-{
- static int nonce_mode = 1; /* 1: use HW nonce 0: use SW nonce */
-
- /* Configure duk/pkf */
- hdmitx_hdcp_opr(0xc);
- if (nonce_mode == 1)
- hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xf);
- else {
- hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xe);
-/* Configure nonce[127:0].
- * MSB must be written the last to assert nonce_vld signal.
- */
- hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x32107654);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xba98fedc);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0xcdef89ab);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x45670123);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x76543210);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xfedcba98);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0x89abcdef);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x01234567);
- }
- udelay(10);
-}
-
-static void am_sysfs_hdcp_event(struct drm_device *dev, unsigned int flag)
-{
- char *envp1[2] = { "HDCP22=1", NULL };
- char *envp0[2] = { "HDCP22=0", NULL };
-
- DRM_INFO("generating hdcp22: %d\n event\n", flag);
- if (flag)
- kobject_uevent_env(&dev->primary->kdev->kobj,
- KOBJ_CHANGE, envp1);
- else
- kobject_uevent_env(&dev->primary->kdev->kobj,
- KOBJ_CHANGE, envp0);
-}
-
-static int am_hdcp22_enable(struct am_hdmi_tx *am_hdmi)
-{
- am_hdmi->hdcp_mode = HDCP_MODE22;
- hdmitx_ddc_hw_op(DDC_MUX_DDC);
- hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
- udelay(5);
- hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 3, 1, 2);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
- udelay(10);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
- udelay(10);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MASK, 0);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MUTE, 0);
- set_pkf_duk_nonce();
-
- /*uevent to open hdcp_tx22*/
- am_sysfs_hdcp_event(am_hdmi->connector.dev, 1);
- return 0;
-}
-
-static int am_hdcp22_disable(struct am_hdmi_tx *am_hdmi)
-{
- hdmitx_hdcp_opr(6);
- /*uevent to close hdcp_tx22*/
- am_sysfs_hdcp_event(am_hdmi->connector.dev, 0);
- return 0;
-}
-
-void am_hdcp_disable(struct am_hdmi_tx *am_hdmi)
-{
- if (am_hdmi->hdcp_mode == HDCP_MODE22)
- am_hdcp22_disable(am_hdmi);
- else if (am_hdmi->hdcp_mode == HDCP_MODE14)
- am_hdcp14_disable(am_hdmi);
-}
-EXPORT_SYMBOL(am_hdcp_disable);
-
-static int is_hdcp_hdmirx_supported(struct am_hdmi_tx *am_hdmi)
-{
- unsigned int hdcp_rx_type = 0x1;
- int st;
-
- /*if tx has hdcp22, then check if rx support hdcp22*/
- if (am_hdmi->hdcp_tx_type & 0x2) {
- hdmitx_ddc_hw_op(DDC_MUX_DDC);
- //mutex_lock(&am_hdmi->hdcp_mutex);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, HDCP_SLAVE);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, HDCP2_VERSION);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 0);
- mdelay(2);
- if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
- st = 0;
- DRM_INFO("ddc rd8b error 0x%02x 0x%02x\n",
- HDCP_SLAVE, HDCP2_VERSION);
- } else
- st = 1;
- hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
- if (hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI) & (1 << 2))
- hdcp_rx_type = 0x3;
- //mutex_unlock(&am_hdmi->hdcp_mutex);
- } else {
- /*if tx has hdcp14 or no key, then rx support hdcp14 acquiescently*/
- hdcp_rx_type = 0x1;
- }
- am_hdmi->hdcp_rx_type = hdcp_rx_type;
-
- DRM_INFO("hdmirx support hdcp14: %d\n", hdcp_rx_type & 0x1);
- DRM_INFO("hdmirx support hdcp22: %d\n", (hdcp_rx_type & 0x2) >> 1);
- return hdcp_rx_type;
-}
-
-int am_hdcp14_auth(struct am_hdmi_tx *am_hdmi)
-{
- return hdmitx_hdcp_opr(0x2);
-}
-
-int am_hdcp22_auth(struct am_hdmi_tx *am_hdmi)
-{
- return hdmitx_hdcp_opr(0x7);
-}
-
-/*firstly,check the hdmirx key
- *if hdmirx has hdcp22 key, start hdcp22. check auth status,
- *if failure,then start hdcp14
- *if hdmirx has hdcp14 key, start hdcp 14
- */
-int am_hdcp_work(void *data)
-{
- struct am_hdmi_tx *am_hdmi = data;
- struct drm_connector_state *state = am_hdmi->connector.state;
- int hdcp_fsm = 0;
-
- is_hdcp_hdmirx_supported(am_hdmi);
- if ((am_hdmi->hdcp_tx_type & 0x2) &&
- (am_hdmi->hdcp_rx_type & 0x2))
- hdcp_fsm = HDCP22_ENABLE;
- else
- hdcp_fsm = HDCP14_ENABLE;
-
- while (hdcp_fsm) {
- if (am_hdmi->hdcp_stop_flag)
- hdcp_fsm = HDCP_QUIT;
-
- switch (hdcp_fsm) {
- case HDCP22_ENABLE:
- am_hdcp22_enable(am_hdmi);
- DRM_INFO("hdcp22 work after 10s\n");
- /*this time is used to debug*/
- msleep_interruptible(10000);
- hdcp_fsm = HDCP22_AUTH;
- break;
- case HDCP22_AUTH:
- if (am_hdcp22_auth(am_hdmi))
- hdcp_fsm = HDCP22_SUCCESS;
- else
- hdcp_fsm = HDCP22_FAIL;
- break;
- case HDCP22_SUCCESS:
- state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_ENABLED;
- DRM_DEBUG("hdcp22 is authenticated successfully\n");
- hdcp_fsm = HDCP22_AUTH;
- msleep_interruptible(200);
- break;
- case HDCP22_FAIL:
- am_hdcp22_disable(am_hdmi);
- state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
- DRM_INFO("hdcp22 failure and start hdcp14\n");
- hdcp_fsm = HDCP14_ENABLE;
- msleep_interruptible(2000);
- break;
- case HDCP14_ENABLE:
- if ((am_hdmi->hdcp_tx_type & 0x1) == 0) {
- hdcp_fsm = HDCP_QUIT;
- break;
- }
- am_hdcp14_enable(am_hdmi);
- msleep_interruptible(500);
- hdcp_fsm = HDCP14_AUTH;
- break;
- case HDCP14_AUTH:
- if (am_hdcp14_auth(am_hdmi))
- hdcp_fsm = HDCP14_SUCCESS;
- else
- hdcp_fsm = HDCP14_FAIL;
- break;
- case HDCP14_SUCCESS:
- state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_ENABLED;
- DRM_DEBUG("hdcp14 is authenticated successfully\n");
- hdcp_fsm = HDCP14_AUTH;
- msleep_interruptible(200);
- break;
- case HDCP14_FAIL:
- am_hdcp14_disable(am_hdmi);
- state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
- DRM_DEBUG("hdcp14 failure\n");
- hdcp_fsm = HDCP_QUIT;
- break;
- case HDCP_QUIT:
- default:
- break;
- }
- }
- return 0;
-}
-EXPORT_SYMBOL(am_hdcp_work);
-
-int am_hdcp_init(struct am_hdmi_tx *am_hdmi)
-{
- int ret;
-
- ret = drm_connector_attach_content_protection_property(
- &am_hdmi->connector);
- if (ret)
- return ret;
- return 0;
-}
-EXPORT_SYMBOL(am_hdcp_init);
-
-/*bit0:hdcp14 bit 1:hdcp22*/
-int is_hdcp_hdmitx_supported(struct am_hdmi_tx *am_hdmi)
-{
- unsigned int hdcp_tx_type = 0;
-
- hdcp_tx_type |= hdmitx_hdcp_opr(0xa);
- hdcp_tx_type |= ((hdmitx_hdcp_opr(0xb)) << 1);
- am_hdmi->hdcp_tx_type = hdcp_tx_type;
- DRM_INFO("hdmitx support hdcp14: %d\n", hdcp_tx_type & 0x1);
- DRM_INFO("hdmitx support hdcp22: %d\n", (hdcp_tx_type & 0x2) >> 1);
- return hdcp_tx_type;
-}
-EXPORT_SYMBOL(is_hdcp_hdmitx_supported);
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_hdcp.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __AM_MESON_HDCP_H
-#define __AM_MESON_HDCP_H
-
-#define HDCP_SLAVE 0x3a
-#define HDCP2_VERSION 0x50
-#define HDCP_MODE14 1
-#define HDCP_MODE22 2
-
-#define HDCP_QUIT 0
-#define HDCP14_ENABLE 1
-#define HDCP14_AUTH 2
-#define HDCP14_SUCCESS 3
-#define HDCP14_FAIL 4
-#define HDCP22_ENABLE 5
-#define HDCP22_AUTH 6
-#define HDCP22_SUCCESS 7
-#define HDCP22_FAIL 8
-
-int am_hdcp_init(struct am_hdmi_tx *am_hdmi);
-int is_hdcp_hdmitx_supported(struct am_hdmi_tx *am_hdmi);
-int am_hdcp_work(void *data);
-void am_hdcp_disable(struct am_hdmi_tx *am_hdmi);
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_hdmi.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#include <drm/drm_modeset_helper.h>
-#include <drm/drmP.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_connector.h>
-
-#include <linux/component.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/jiffies.h>
-#include <linux/kthread.h>
-#include <linux/device.h>
-
-#include <linux/workqueue.h>
-#include <linux/amlogic/media/vout/vout_notify.h>
-#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
-#include "am_meson_hdmi.h"
-#include "am_meson_hdcp.h"
-
-#define DEVICE_NAME "amhdmitx"
-struct am_hdmi_tx am_hdmi_info;
-
-struct am_vout_mode {
- char name[DRM_DISPLAY_MODE_LEN];
- enum vmode_e mode;
- int width, height, vrefresh;
- unsigned int flags;
-};
-
-static struct am_vout_mode am_vout_modes[] = {
- { "1080p60hz", VMODE_HDMI, 1920, 1080, 60, 0},
- { "1080p30hz", VMODE_HDMI, 1920, 1080, 30, 0},
- { "1080p50hz", VMODE_HDMI, 1920, 1080, 50, 0},
- { "1080p25hz", VMODE_HDMI, 1920, 1080, 25, 0},
- { "1080p24hz", VMODE_HDMI, 1920, 1080, 24, 0},
- { "2160p30hz", VMODE_HDMI, 3840, 2160, 30, 0},
- { "2160p60hz", VMODE_HDMI, 3840, 2160, 60, 0},
- { "2160p50hz", VMODE_HDMI, 3840, 2160, 50, 0},
- { "2160p25hz", VMODE_HDMI, 3840, 2160, 25, 0},
- { "2160p24hz", VMODE_HDMI, 3840, 2160, 24, 0},
- { "smpte30hz", VMODE_HDMI, 4096, 2160, 30, 0},
- { "smpte60hz", VMODE_HDMI, 4096, 2160, 60, 0},
- { "smpte50hz", VMODE_HDMI, 4096, 2160, 50, 0},
- { "smpte25hz", VMODE_HDMI, 4096, 2160, 25, 0},
- { "smpte24hz", VMODE_HDMI, 4096, 2160, 24, 0},
- { "1080i60hz", VMODE_HDMI, 1920, 1080, 60, DRM_MODE_FLAG_INTERLACE},
- { "1080i50hz", VMODE_HDMI, 1920, 1080, 50, DRM_MODE_FLAG_INTERLACE},
- { "720p60hz", VMODE_HDMI, 1280, 720, 60, 0},
- { "720p50hz", VMODE_HDMI, 1280, 720, 50, 0},
- { "480p60hz", VMODE_HDMI, 720, 480, 60, 0},
- { "480i60hz", VMODE_HDMI, 720, 480, 60, DRM_MODE_FLAG_INTERLACE},
- { "576p50hz", VMODE_HDMI, 720, 576, 50, 0},
- { "576i50hz", VMODE_HDMI, 720, 576, 50, DRM_MODE_FLAG_INTERLACE},
- { "480p60hz", VMODE_HDMI, 720, 480, 60, 0},
-};
-
-char *am_meson_hdmi_get_voutmode(struct drm_display_mode *mode)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(am_vout_modes); i++) {
- if ((am_vout_modes[i].width == mode->hdisplay)
- && (am_vout_modes[i].height == mode->vdisplay)
- && (am_vout_modes[i].vrefresh == mode->vrefresh)
- && (am_vout_modes[i].flags ==
- (mode->flags&DRM_MODE_FLAG_INTERLACE)))
- return am_vout_modes[i].name;
- }
- return NULL;
-}
-
-static unsigned char default_edid[] = {
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
- 0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x16, 0x01, 0x03, 0x6d, 0x32, 0x1c, 0x78,
- 0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
- 0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0xd1, 0xc0,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
- 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
- 0x45, 0x00, 0xf4, 0x19, 0x11, 0x00, 0x00, 0x1e,
- 0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
- 0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
- 0x3d, 0x42, 0x44, 0x0f, 0x00, 0x0a, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
- 0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x46,
- 0x48, 0x44, 0x0a, 0x20, 0x20, 0x20, 0x00, 0x05,
-};
-
-int am_hdmi_tx_get_modes(struct drm_connector *connector)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(connector);
- struct edid *edid;
- int count = 0;
-
- DRM_INFO("get_edid\n");
- edid = drm_get_edid(connector, am_hdmi->ddc);
-
- if (edid) {
- drm_mode_connector_update_edid_property(connector, edid);
- count = drm_add_edid_modes(connector, edid);
- kfree(edid);
- } else {
- DRM_INFO("edid error and load default edid\n");
- drm_mode_connector_update_edid_property(connector,
- (struct edid *)default_edid);
- count = drm_add_edid_modes(connector,
- (struct edid *)default_edid);
- }
- return count;
-}
-
-enum drm_mode_status am_hdmi_tx_check_mode(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- if (am_meson_hdmi_get_voutmode(mode))
- return MODE_OK;
- else
- return MODE_NOMODE;
-}
-
-static struct drm_encoder *am_hdmi_connector_best_encoder
- (struct drm_connector *connector)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(connector);
-
- return &am_hdmi->encoder;
-}
-
-static enum drm_connector_status am_hdmi_connector_detect
- (struct drm_connector *connector, bool force)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(connector);
-
- /* HPD rising */
- if (am_hdmi->hpd_flag == 1) {
- DRM_INFO("connector_status_connected\n");
- return connector_status_connected;
- }
- /* HPD falling */
- if (am_hdmi->hpd_flag == 2) {
- DRM_INFO("connector_status_disconnected\n");
- /*
- *clean the hdmi info and output : todo
- */
- return connector_status_disconnected;
- }
- /*if the status is unknown, read GPIO*/
- if (hdmitx_hpd_hw_op(HPD_READ_HPD_GPIO)) {
- DRM_INFO("connector_status_connected\n");
- return connector_status_connected;
- }
- if (!(hdmitx_hpd_hw_op(HPD_READ_HPD_GPIO))) {
- DRM_INFO("connector_status_disconnected\n");
- return connector_status_disconnected;
- }
-
- DRM_INFO("connector_status_unknown\n");
- return connector_status_unknown;
-}
-
-static int am_hdmi_connector_set_property(struct drm_connector *connector,
- struct drm_property *property, uint64_t val)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(connector);
- struct drm_connector_state *state = am_hdmi->connector.state;
-
- if (property == connector->content_protection_property) {
- DRM_INFO("property:%s val: %lld\n", property->name, val);
- if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
- DRM_DEBUG_KMS("only drivers can set CP Enabled\n");
- return -EINVAL;
- }
- state->content_protection = val;
- }
- /*other parperty todo*/
- return 0;
-}
-
-static int am_hdmi_connector_atomic_get_property
- (struct drm_connector *connector,
- const struct drm_connector_state *state,
- struct drm_property *property, uint64_t *val)
-{
- if (property == connector->content_protection_property) {
- DRM_INFO("get content_protection val: %d\n",
- state->content_protection);
- *val = state->content_protection;
- } else {
- DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name);
- return -EINVAL;
- }
- return 0;
-}
-
-static void am_hdmi_connector_destroy(struct drm_connector *connector)
-{
- drm_connector_unregister(connector);
- drm_connector_cleanup(connector);
-}
-
-static const
-struct drm_connector_helper_funcs am_hdmi_connector_helper_funcs = {
- .get_modes = am_hdmi_tx_get_modes,
- .mode_valid = am_hdmi_tx_check_mode,
- .best_encoder = am_hdmi_connector_best_encoder,
-};
-
-static const struct drm_connector_funcs am_hdmi_connector_funcs = {
- .dpms = drm_atomic_helper_connector_dpms,
- .detect = am_hdmi_connector_detect,
- .fill_modes = drm_helper_probe_single_connector_modes,
- .set_property = am_hdmi_connector_set_property,
- .atomic_get_property = am_hdmi_connector_atomic_get_property,
- .destroy = am_hdmi_connector_destroy,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-void am_hdmi_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- const char attr1[16] = "rgb,8bit";
- const char attr2[16] = "420,8bit";
- int vic;
- struct am_hdmi_tx *am_hdmi = &am_hdmi_info;
-
- DRM_INFO("mode : %s, adjusted_mode : %s\n",
- mode->name, adjusted_mode->name);
- am_hdmi->hdmi_info.vic = drm_match_cea_mode(adjusted_mode);
- vic = am_hdmi->hdmi_info.vic;
- DRM_INFO("the hdmi mode vic : %d\n", am_hdmi->hdmi_info.vic);
- /* Store the display mode for plugin/DPMS poweron events */
- memcpy(&am_hdmi->previous_mode, adjusted_mode,
- sizeof(am_hdmi->previous_mode));
- if ((vic == 96) || (vic == 97) || (vic == 101) || (vic == 102)
- || (vic == 106) || (vic == 107))
- setup_attr(attr2);
- else
- setup_attr(attr1);
-}
-
-void am_hdmi_encoder_enable(struct drm_encoder *encoder)
-{
- enum vmode_e vmode = get_current_vmode();
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(encoder);
- struct drm_connector_state *state = am_hdmi->connector.state;
-
- if (vmode == VMODE_HDMI)
- DRM_INFO("am_hdmi_encoder_enable\n");
- else
- DRM_INFO("am_hdmi_encoder_enable fail! vmode:%d\n", vmode);
-
- vout_notifier_call_chain(VOUT_EVENT_MODE_CHANGE_PRE, &vmode);
- set_vout_vmode(vmode);
- vout_notifier_call_chain(VOUT_EVENT_MODE_CHANGE, &vmode);
- mdelay(1000);
- if (state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED) {
- if (am_hdmi->hdcp_tx_type) {
- am_hdmi->hdcp_stop_flag = 0;
- am_hdmi->hdcp_work = kthread_run(am_hdcp_work,
- (void *)am_hdmi, "kthread_hdcp_task");
- } else
- DRM_INFO("hdmitx doesn't has hdcp key\n");
- }
-}
-
-void am_hdmi_encoder_disable(struct drm_encoder *encoder)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(encoder);
- struct drm_connector_state *state = am_hdmi->connector.state;
-
- /*need to add hdmitx disable function ..todo*/
- if (state->content_protection !=
- DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
- state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
- am_hdmi->hdcp_stop_flag = 1;
- kthread_stop(am_hdmi->hdcp_work);
- am_hdcp_disable(am_hdmi);
- }
-}
-
-static int am_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct am_hdmi_tx *am_hdmi = to_am_hdmi(encoder);
-
- DRM_INFO("content_protection:%d\n", conn_state->content_protection);
-
- if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_ENABLED) {
- kthread_stop(am_hdmi->hdcp_work);
- am_hdcp_disable(am_hdmi);
- conn_state->content_protection =
- DRM_MODE_CONTENT_PROTECTION_DESIRED;
- }
- return 0;
-}
-
-static const struct drm_encoder_helper_funcs
- am_hdmi_encoder_helper_funcs = {
- .mode_set = am_hdmi_encoder_mode_set,
- .enable = am_hdmi_encoder_enable,
- .disable = am_hdmi_encoder_disable,
- .atomic_check = am_hdmi_encoder_atomic_check,
-};
-
-static const struct drm_encoder_funcs am_hdmi_encoder_funcs = {
- .destroy = drm_encoder_cleanup,
-};
-
-static int am_hdmi_i2c_write(struct am_hdmi_tx *am_hdmi,
- unsigned char *buf, unsigned int length)
-{
- struct am_hdmi_i2c *i2c = am_hdmi->i2c;
- int stat;
-
- if (!i2c->is_regaddr) {
- /* Use the first write byte as register address */
- i2c->slave_reg = buf[0];
- length--;
- buf++;
- i2c->is_regaddr = true;
- }
-
- while (length--) {
- reinit_completion(&i2c->cmp);
-
- hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, *buf++);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, i2c->slave_reg++);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 4);
-
- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 100);
-
- stat = 1;
- /* Check for error condition on the bus */
- if (i2c->stat & 1)
- return -EIO;
- }
-
- return 0;
-}
-
-static int am_hdmi_i2c_read(struct am_hdmi_tx *am_hdmi,
- unsigned char *buf, unsigned int length)
-{
- struct am_hdmi_i2c *i2c = am_hdmi->i2c;
- int stat;
-
- if (!i2c->is_regaddr) {
- dev_dbg(am_hdmi->dev, "set read register address to 0\n");
- i2c->slave_reg = 0x00;
- i2c->is_regaddr = true;
- }
-
- while (length--) {
- reinit_completion(&i2c->cmp);
-
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, i2c->slave_reg++);
- if (i2c->is_segment)
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 1);
- else
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 0);
-
- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 100);
-
- stat = 1;
-
- /* Check for error condition on the bus */
- if (i2c->stat & 0x1)
- return -EIO;
-
- *buf++ = hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
- }
- i2c->is_segment = false;
-
- return 0;
-}
-
-static int am_hdmi_i2c_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
-{
- struct am_hdmi_tx *am_hdmi = i2c_get_adapdata(adap);
- struct am_hdmi_i2c *i2c = am_hdmi->i2c;
- u8 addr = msgs[0].addr;
- int i, ret = 0;
-
- dev_dbg(am_hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
-
- for (i = 0; i < num; i++) {
- if (msgs[i].len == 0) {
- dev_dbg(am_hdmi->dev,
- "unsupported transfer %d/%d, no data\n",
- i + 1, num);
- return -EOPNOTSUPP;
- }
- }
-
- mutex_lock(&i2c->lock);
-
- /* Clear the EDID interrupt flag and unmute the interrupt */
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SOFTRSTZ, 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CM_STAT0, 0);
- /* TODO */
- hdmitx_ddc_hw_op(DDC_MUX_DDC);
-
- /* Set slave device address taken from the first I2C message */
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, addr);
-
- /* Set slave device register address on transfer */
- i2c->is_regaddr = false;
-
- /* Set segment pointer for I2C extended read mode operation */
- i2c->is_segment = false;
-
- for (i = 0; i < num; i++) {
- dev_dbg(am_hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
- i + 1, num, msgs[i].len, msgs[i].flags);
- if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
- i2c->is_segment = true;
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR,
- DDC_SEGMENT_ADDR);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, *msgs[i].buf);
- } else {
- if (msgs[i].flags & I2C_M_RD)
- ret = am_hdmi_i2c_read(am_hdmi, msgs[i].buf,
- msgs[i].len);
- else
- ret = am_hdmi_i2c_write(am_hdmi, msgs[i].buf,
- msgs[i].len);
- }
- if (ret < 0)
- break;
- }
-
- if (!ret)
- ret = num;
-
- mutex_unlock(&i2c->lock);
-
- return ret;
-}
-
-static u32 am_hdmi_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm am_hdmi_algorithm = {
- .master_xfer = am_hdmi_i2c_xfer,
- .functionality = am_hdmi_i2c_func,
-};
-
-static struct i2c_adapter *am_hdmi_i2c_adapter(struct am_hdmi_tx *am_hdmi)
-{
- struct i2c_adapter *adap;
- struct am_hdmi_i2c *i2c;
- int ret;
-
- i2c = devm_kzalloc(am_hdmi->priv->dev, sizeof(*i2c), GFP_KERNEL);
- if (!i2c) {
- ret = -ENOMEM;
- DRM_INFO("error : %d\n", ret);
- }
-
- mutex_init(&i2c->lock);
- init_completion(&i2c->cmp);
-
- adap = &i2c->adap;
- adap->class = I2C_CLASS_DDC;
- adap->owner = THIS_MODULE;
- adap->dev.parent = am_hdmi->priv->dev;
- adap->dev.of_node = am_hdmi->priv->dev->of_node;
- adap->algo = &am_hdmi_algorithm;
- strlcpy(adap->name, "Am HDMI", sizeof(adap->name));
- i2c_set_adapdata(adap, am_hdmi);
-
- ret = i2c_add_adapter(adap);
- if (ret) {
- DRM_INFO("cannot add %s I2C adapter\n",
- adap->name);
- devm_kfree(am_hdmi->priv->dev, i2c);
- return ERR_PTR(ret);
- }
- am_hdmi->i2c = i2c;
- DRM_INFO("registered %s I2C bus driver\n", adap->name);
-
- return adap;
-
-}
-static irqreturn_t am_hdmi_hardirq(int irq, void *dev_id)
-{
- unsigned int data32 = 0;
- irqreturn_t ret = IRQ_NONE;
-
- data32 = hdmitx_rd_reg(HDMITX_TOP_INTR_STAT);
-
- /* check HPD status */
- if ((data32 & (1 << 1)) && (data32 & (1 << 2))) {
- if (hdmitx_hpd_hw_op(HPD_READ_HPD_GPIO))
- data32 &= ~(1 << 2);
- else
- data32 &= ~(1 << 1);
- }
-
- if ((data32 & (1 << 1)) || (data32 & (1 << 2))) {
- ret = IRQ_WAKE_THREAD;
- DRM_INFO("hotplug irq: %x\n", data32);
- am_hdmi_info.hpd_flag = 0;
- if (data32 & (1 << 1))
- am_hdmi_info.hpd_flag = 1;/* HPD rising */
- if (data32 & (1 << 2))
- am_hdmi_info.hpd_flag = 2;/* HPD falling */
- /* ack INTERNAL_INTR or else*/
- hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, data32 | 0x7);
- }
- return ret;
-}
-
-static irqreturn_t am_hdmi_irq(int irq, void *dev_id)
-{
- struct am_hdmi_tx *am_hdmi = dev_id;
-
- drm_helper_hpd_irq_event(am_hdmi->connector.dev);
- return IRQ_HANDLED;
-}
-
-static int amhdmitx_get_dt_info(struct am_hdmi_tx *am_hdmi)
-{
- struct device_node *hdcp_node;
- unsigned char *hdcp_status;
- int ret = 0;
-
- hdcp_node = of_find_node_by_path("/drm-amhdmitx");
- if (hdcp_node) {
- ret = of_property_read_string(hdcp_node, "hdcp",
- (const char **)&(hdcp_status));
- if (ret)
- DRM_INFO("not find hdcp_feature\n");
- else {
- if (memcmp(hdcp_status, "okay", 4) == 0)
- am_hdmi->hdcp_feature = 1;
- else
- am_hdmi->hdcp_feature = 0;
- DRM_INFO("hdcp_feature: %d\n",
- am_hdmi->hdcp_feature);
- }
- } else {
- DRM_INFO("not find drm_amhdmitx\n");
- }
- return 0;
-}
-
-
-static const struct of_device_id am_meson_hdmi_dt_ids[] = {
- { .compatible = "amlogic,drm-amhdmitx", },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, am_meson_hdmi_dt_ids);
-
-static int am_meson_hdmi_bind(struct device *dev,
- struct device *master, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct drm_device *drm = data;
- struct meson_drm *priv = drm->dev_private;
- struct am_hdmi_tx *am_hdmi;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
- int ret;
- int irq;
-
- am_hdmi = devm_kzalloc(priv->dev, sizeof(*am_hdmi),
- GFP_KERNEL);
- if (!am_hdmi)
- return -ENOMEM;
- memcpy(&am_hdmi_info, am_hdmi, sizeof(*am_hdmi));
- am_hdmi = &am_hdmi_info;
-
- DRM_INFO("drm hdmitx init and version:%s\n", DRM_HDMITX_VER);
- am_hdmi->priv = priv;
- encoder = &am_hdmi->encoder;
- connector = &am_hdmi->connector;
-
- /* Connector */
- am_hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
- drm_connector_helper_add(connector,
- &am_hdmi_connector_helper_funcs);
-
- ret = drm_connector_init(drm, connector, &am_hdmi_connector_funcs,
- DRM_MODE_CONNECTOR_HDMIA);
- if (ret) {
- dev_err(priv->dev, "Failed to init hdmi tx connector\n");
- return ret;
- }
-
- connector->interlace_allowed = 1;
-
- /* Encoder */
- drm_encoder_helper_add(encoder, &am_hdmi_encoder_helper_funcs);
-
- ret = drm_encoder_init(drm, encoder, &am_hdmi_encoder_funcs,
- DRM_MODE_ENCODER_TVDAC, "am_hdmi_encoder");
- if (ret) {
- dev_err(priv->dev, "Failed to init hdmi encoder\n");
- return ret;
- }
-
- encoder->possible_crtcs = BIT(0);
-
- drm_mode_connector_attach_encoder(connector, encoder);
-
- /*DDC init*/
- am_hdmi->ddc = am_hdmi_i2c_adapter(am_hdmi);
- DRM_INFO("hdmitx:DDC init complete\n");
- /*Hotplug irq*/
- irq = platform_get_irq(pdev, 0);
- DRM_INFO("hdmi connector irq:%d\n", irq);
- if (irq < 0)
- return irq;
- hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0x7);
- ret = devm_request_threaded_irq(am_hdmi->priv->dev, irq,
- am_hdmi_hardirq, am_hdmi_irq, IRQF_SHARED,
- dev_name(am_hdmi->priv->dev), am_hdmi);
- if (ret) {
- dev_err(am_hdmi->priv->dev,
- "failed to request hdmi irq: %d\n", ret);
- }
-
- /*HDCP INIT*/
- amhdmitx_get_dt_info(am_hdmi);
- if (am_hdmi->hdcp_feature) {
- if (is_hdcp_hdmitx_supported(am_hdmi)) {
- ret = am_hdcp_init(am_hdmi);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
- }
- return 0;
-}
-
-static void am_meson_hdmi_unbind(struct device *dev,
- struct device *master, void *data)
-{
- am_hdmi_info.connector.funcs->destroy(&am_hdmi_info.connector);
- am_hdmi_info.encoder.funcs->destroy(&am_hdmi_info.encoder);
-}
-
-static const struct component_ops am_meson_hdmi_ops = {
- .bind = am_meson_hdmi_bind,
- .unbind = am_meson_hdmi_unbind,
-};
-
-static int am_meson_hdmi_probe(struct platform_device *pdev)
-{
- return component_add(&pdev->dev, &am_meson_hdmi_ops);
-}
-
-static int am_meson_hdmi_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &am_meson_hdmi_ops);
- return 0;
-}
-
-static struct platform_driver am_meson_hdmi_pltfm_driver = {
- .probe = am_meson_hdmi_probe,
- .remove = am_meson_hdmi_remove,
- .driver = {
- .name = "meson-amhdmitx",
- .of_match_table = am_meson_hdmi_dt_ids,
- },
-};
-
-module_platform_driver(am_meson_hdmi_pltfm_driver);
-
-MODULE_AUTHOR("MultiMedia Amlogic <multimedia-sh@amlogic.com>");
-MODULE_DESCRIPTION("Amlogic Meson Drm HDMI driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_hdmi.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#ifndef __AM_MESON_HDMI_H
-#define __AM_MESON_HDMI_H
-
-#include "am_meson_drv.h"
-#define DDC_SEGMENT_ADDR 0x30
-#define VIC_MAX_NUM 512
-#define DRM_HDMITX_VER "20180705"
-
-struct am_hdmi_data {
- unsigned int vic;
- bool sink_is_hdmi;
- bool sink_has_audio;
- unsigned int colorimetry;
- unsigned int cd; /* cd8, cd10 or cd12 */
- unsigned int cs; /* rgb, y444, y422, y420 */
- unsigned int cr; /* limit, full */
- struct hdmi_pwr_ctl *pwr_ctl;
- unsigned int aud_output_ch;
- unsigned int tx_aud_cfg; /* 0, off; 1, on */
- unsigned int tmds_clk_div40;
- unsigned int VIC[VIC_MAX_NUM];
-};
-
-struct am_hdmi_i2c {
- struct i2c_adapter adap;
- struct mutex lock;
- struct completion cmp;
- u8 ddc_addr;
- u8 segment_addr;
- u8 slave_reg;
- u8 stat;
- bool is_regaddr;
- bool is_segment;
-};
-
-struct am_hdmi_tx {
- struct device *dev;
- struct drm_encoder encoder;
- struct drm_connector connector;
- struct meson_drm *priv;
- int irq;
- unsigned int input_color_format;
- unsigned int output_color_format;
- unsigned int color_depth;
- struct drm_display_mode previous_mode;
- struct am_hdmi_data hdmi_info;
- struct am_hdmi_i2c *i2c;
- struct i2c_adapter *ddc;
- struct workqueue_struct *hdmi_wq;
- const char *hpd_pin;
- const char *ddc_pin;
- unsigned int hpd_flag;/*0:none 1:up 2:down*/
- struct mutex hdcp_mutex;
- unsigned int hdcp_feature;
- unsigned int hdcp_tx_type;/*bit0:hdcp14 bit 1:hdcp22*/
- unsigned int hdcp_rx_type;/*bit0:hdcp14 bit 1:hdcp22*/
- struct timer_list hdcp_timer;
- unsigned int hdcp_mode;
- unsigned int hdcp_state;
- unsigned int hdcp_stop_flag;/*turn off hdcp state machine*/
- unsigned int hdcp_try_times;
- struct task_struct *hdcp_work;
-};
-
-#define to_am_hdmi(x) container_of(x, struct am_hdmi_tx, x)
-
-#define HDMITX_REG_IDX 6
-#define HDMITX_SEC_REG_IDX 7
-#define BASE_REG_OFFSET 24
-
-#define HDMITX_SEC_REG_ADDR(reg) \
- ((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
-#define HDMITX_REG_ADDR(reg) \
- ((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
-
-/* TOP-level wrapper registers addresses
- * bit24: 1 means secure access
- * bit28: 1 means DWC, 0 means TOP
- */
-#define SEC_OFFSET (0x1UL << 24)
-#define TOP_OFFSET_MASK (0x0UL << 24)
-#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET))
-#define DWC_OFFSET_MASK (0x10UL << 24)
-#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET))
-
-/* Bit 7 RW Reserved. Default 1.
- * Bit 6 RW Reserved. Default 1.
- * Bit 5 RW Reserved. Default 1.
- * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
- * Default 1.
- * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
- * 0=Release from reset. Default 1.
- * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
- * Default 1.
- * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
- * 0=Release from reset. Default 1.
- * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
- * 0=Release from reset. Default 1.
- */
-#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000)
-
-/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */
-/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */
-/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */
-/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */
-/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */
-/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */
-/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */
-/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */
-/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */
-/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */
-#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001)
-
-/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */
-/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */
-#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002)
-
-/* intr_maskn: MASK_N, one bit per interrupt source.
- * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
- * [ 4] hdcp22_rndnum_err
- * [ 3] nonce_rfrsh_rise
- * [ 2] hpd_fall_intr
- * [ 1] hpd_rise_intr
- * [ 0] core_intr
- */
-#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003)
-
-/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
- * bit, read back the interrupt status.
- * Bit 31 R IP interrupt status
- * Bit 2 RW hpd_fall
- * Bit 1 RW hpd_rise
- * Bit 0 RW IP interrupt
- */
-#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004)
-
-/* [4] hdcp22_rndnum_err */
-/* [3] nonce_rfrsh_rise */
-/* [2] hpd_fall */
-/* [1] hpd_rise */
-/* [0] core_intr_rise */
-#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005)
-
-/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
- * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
- * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
- * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
- * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable.
- * Default 0.
- * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
- * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
- * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
- * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
- */
-#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006)
-
-/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
-/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007)
-
-/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
-/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008)
-
-/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009)
-
-/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
-/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
-#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A)
-
-/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
-/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
-#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B)
-
-/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
- * used when TMDS CLK rate = TMDS character rate /4. Default 0.
- * Bit 0 R Reserved. Default 0.
- */
-/* [ 1] shift_tmds_clk_pttn */
-/* [ 0] load_tmds_clk_pttn */
-#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C)
-
-/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
- * failure, write 1 to clear the failure flag. Default 0.
- */
-#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D)
-
-/* Bit 0 R filtered HPD status. */
-#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E)
-#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010)
-#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011)
-#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012)
-#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013)
-#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014)
-#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015)
-#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016)
-#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017)
-#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018)
-#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019)
-#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A)
-#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B)
-#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C)
-/* [26:24] infilter_ddc_intern_clk_divide */
-/* [23:16] infilter_ddc_sample_clk_divide */
-/* [10: 8] infilter_cec_intern_clk_divide */
-/* [ 7: 0] infilter_cec_sample_clk_divide */
-#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D)
-#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E)
-#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F)
-
-#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE)
-#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF)
-
-/* DWC_HDMI_TX Controller registers addresses */
-
-/* Identification Registers */
-#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000)
-#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001)
-#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002)
-#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003)
-#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004)
-#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005)
-#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006)
-#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007)
-
-/* Interrupt Registers */
-#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100)
-#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101)
-#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102)
-#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103)
-#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104)
-#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105)
-#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106)
-#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107)
-#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108)
-#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170)
-/* [ 7] mute_AUDI */
-/* [ 6] mute_ACP */
-/* [ 5] mute_HBR */
-/* [ 4] mute_MAS */
-/* [ 3] mute_NVBI */
-/* [ 2] mute_AUDS */
-/* [ 1] mute_ACR */
-/* [ 0] mute_NULL */
-#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180)
-/* [ 7] mute_GMD */
-/* [ 6] mute_ISRC1 */
-/* [ 5] mute_ISRC2 */
-/* [ 4] mute_VSD */
-/* [ 3] mute_SPD */
-/* [ 2] mute_AMP */
-/* [ 1] mute_AVI */
-/* [ 0] mute_GCP */
-#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181)
-/* [ 1] mute_LowPriority_fifo_full */
-/* [ 0] mute_HighPriority_fifo_full */
-#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182)
-/* [ 4] mute_aud_fifo_underrun */
-/* [ 3] mute_aud_fifo_overrun */
-/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */
-/* [ 1] mute_aud_fifo_empty */
-/* [ 0] mute_aud_fifo_full */
-#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183)
-#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184)
-/* [ 2] mute_scdc_readreq */
-/* [ 1] mute_edid_i2c_master_done */
-/* [ 0] mute_edid_i2c_master_error */
-#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185)
-/* [ 6] cec_wakeup */
-/* [ 5] cec_error_follower */
-/* [ 4] cec_error_initiator */
-/* [ 3] cec_arb_lost */
-/* [ 2] cec_nack */
-/* [ 1] cec_eom */
-/* [ 0] cec_done */
-#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186)
-#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187)
-#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188)
-/* [ 1] mute_wakeup_interrupt */
-/* [ 0] mute_all_interrupt */
-#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF)
-
-/* Video Sampler Registers */
-/* [ 7] internal_de_generator */
-/* [4:0] video_mapping */
-#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200)
-/* [ 2] bcbdata_stuffing */
-/* [ 1] rcrdata_stuffing */
-/* [ 0] gydata_stuffing */
-#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201)
-#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202)
-#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203)
-#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204)
-#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205)
-#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206)
-#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207)
-
-/* Video Packetizer Registers */
-#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800)
-/* [3:0] desired_pr_factor */
-#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801)
-/* [ 5] default_phase */
-/* [ 2] ycc422_stuffing */
-/* [ 1] pp_stuffing */
-/* [ 0] pr_stuffing */
-#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802)
-#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803)
-#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804)
-/* [ 7] mask_int_full_prpt */
-/* [ 6] mask_int_empty_prpt */
-/* [ 5] mask_int_full_ppack */
-/* [ 4] mask_int_empty_ppack */
-/* [ 3] mask_int_full_remap */
-/* [ 2] mask_int_empty_remap */
-/* [ 1] mask_int_full_byp */
-/* [ 0] mask_int_empty_byp */
-#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807)
-
-/* Frmae Composer Registers */
-/* [ 7] HDCP_keepout */
-/* [ 6] vs_in_pol: 0=active low; 1=active high. */
-/* [ 5] hs_in_pol: 0=active low; 1=active high. */
-/* [ 4] de_in_pol: 0=active low; 1=active high. */
-/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */
-/* [ 1] r_v_blank_in_osc */
-/* [ 0] in_I_P: 0=progressive; 1=interlaced. */
-#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000)
-/* [7:0] H_in_active[7:0] */
-#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001)
-/* [5:0] H_in_active[13:8] */
-#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002)
-/* [7:0] H_in_blank[7:0] */
-#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003)
-/* [4:0] H_in_blank[12:8] */
-#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004)
-/* [7:0] V_in_active[7:0] */
-#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005)
-/* [4:0] V_in_active[12:8] */
-#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006)
-/* [7:0] V_in_blank */
-#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007)
-/* [7:0] H_in_delay[7:0] */
-#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008)
-/* [4:0] H_in_delay[12:8] */
-#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009)
-/* [7:0] H_in_width[7:0] */
-#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A)
-/* [1:0] H_in_width[9:8] */
-#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B)
-/* [7:0] V_in_delay */
-#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C)
-/* [5:0] V_in_width */
-#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D)
-#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E)
-#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F)
-#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010)
-#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011)
-#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012)
-#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013)
-#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014)
-#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015)
-#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016)
-/* [3:2] YQ */
-/* [1:0] CN */
-#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017)
-/* [ 2] default_phase */
-/* [ 1] set_avmute */
-/* [ 0] clear_avmute */
-#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018)
-/* [ 7] rgb_ycc_indication[2] */
-/* [ 6] active_format_present */
-/* [5:4] scan_information */
-/* [3:2] bar_information */
-/* [1:0] rgb_ycc_indication[1:0] */
-#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019)
-/* [7:6] colorimetry */
-/* [5:4] picture_aspect_ratio */
-/* [3:0] active_aspect_ratio */
-#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A)
-/* [ 7] IT_content */
-/* [6:4] extended_colorimetry */
-/* [3:2] quantization_range */
-/* [1:0] non_uniform_picture_scaling */
-#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B)
-#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C)
-#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D)
-#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E)
-#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F)
-#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020)
-#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021)
-#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022)
-#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023)
-#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024)
-/* [3:0] CT: coding type */
-#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025)
-/* [5:4] SS: sampling size */
-/* [2:0] SF: sampling frequency */
-#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026)
-/* CA: channel allocation */
-#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027)
-/* [6:5] LFEPBL: LFE playback info */
-/* [ 4] DM_INH: down mix enable */
-/* [3:0] LSv: Level shift value */
-#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028)
-#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029)
-#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A)
-#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030)
-#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031)
-#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032)
-#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033)
-#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034)
-#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035)
-#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036)
-#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037)
-#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038)
-#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039)
-#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A)
-#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B)
-#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C)
-#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D)
-#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E)
-#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F)
-#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040)
-#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041)
-#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042)
-#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043)
-#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044)
-#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045)
-#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046)
-#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047)
-#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048)
-#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049)
-#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A)
-#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B)
-#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C)
-#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D)
-#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E)
-#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F)
-#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050)
-#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060)
-#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061)
-#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062)
-/* [7:4] aud_packet_sampflat */
-/* [ 0] aud_packet_layout */
-#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063)
-#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064)
-/* [ 7] V3r */
-/* [ 6] V2r */
-/* [ 5] V1r */
-/* [ 4] V0r */
-/* [ 3] V3l */
-/* [ 2] V2l */
-/* [ 1] V1l */
-/* [ 0] V0l */
-#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065)
-#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066)
-/* bit5:4 CSB 41:40 */
-/* bit0 CSB 2 */
-#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067)
-/* bit7:0 CSB 15:8 */
-#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068)
-/* bit6:4 CSB 5:3 */
-/* bit3:0 CSB 17:16 */
-#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069)
-/* bit7:4 CSB 22:21 2nd right sub */
-/* bit3:0 CSB 22:21 1st right sub */
-#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A)
-/* bit?? CSB 22:21 4th right sub */
-/* bit?? CSB 22:21 3rd right sub */
-#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B)
-/* bit7:4 CSB 22:21 2nd left sub */
-/* bit3:0 CSB 22:21 1st left sub */
-#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C)
-/* bit?? CSB 22:21 4th left sub */
-/* bit?? CSB 22:21 3rd left sub */
-#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D)
-#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E)
-#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F)
-#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070)
-#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071)
-#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072)
-#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073)
-#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074)
-#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075)
-#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082)
-#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083)
-#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084)
-#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085)
-#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086)
-#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087)
-#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088)
-#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089)
-#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A)
-#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B)
-#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C)
-#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D)
-#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E)
-#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F)
-#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090)
-#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091)
-#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092)
-#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093)
-#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094)
-#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095)
-#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096)
-#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097)
-#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098)
-#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099)
-#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A)
-#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B)
-#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C)
-#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D)
-#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E)
-#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F)
-#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0)
-#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1)
-#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2)
-#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3)
-#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4)
-#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5)
-#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6)
-#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7)
-#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8)
-#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9)
-#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA)
-#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB)
-#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC)
-#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD)
-#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE)
-#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF)
-#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0)
-#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1)
-#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2)
-/* [ 4] spd_auto */
-/* [ 3] vsd_auto */
-/* [ 2] isrc2_auto */
-/* [ 1] isrc1_auto */
-/* [ 0] acp_auto */
-#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3)
-#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4)
-#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5)
-#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6)
-/* [ 6] drm_auto: instert on Vsync */
-/* [ 5] nvbi_auto: insert on Vsync */
-/* [ 4] amp_auto: insert on Vsync */
-/* [ 3] avi_auto: insert on Vsync */
-/* [ 2] gcp_auto: insert on Vsync */
-/* [ 1] audi_auto: insert on Vsync */
-/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid
- * initial packets with false CTS value
- */
-#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7)
-#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8)
-#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9)
-#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA)
-#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB)
-#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC)
-#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD)
-#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE)
-#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF)
-#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0)
-#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1)
-#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2)
-#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3)
-/* [ 7] AUDI_int_mask */
-/* [ 6] ACP_int_mask */
-/* [ 5] HBR_int_mask */
-/* [ 2] AUDS_int_mask */
-/* [ 1] ACR_int_mask */
-/* [ 0] NULL_int_mask */
-#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2)
-/* [ 7] GMD_int_mask */
-/* [ 6] ISRC1_int_mask */
-/* [ 5] ISRC2_int_mask */
-/* [ 4] VSD_int_mask */
-/* [ 3] SPD_int_mask */
-/* [ 1] AVI_int_mask */
-/* [ 0] GCP_int_mask */
-#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6)
-/* [ 2] Mask bit for FC_INT2.DRM interrupt bit */
-/* [ 1] LowPriority_fifo_full */
-/* [ 0] HighPriority_fifo_full */
-#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA)
-/* [7:4] incoming_pr_factor */
-/* [3:0] output_pr_factor */
-#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0)
-/* [ 4] scrambler_ucp_line */
-/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/
-#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1)
-#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2)
-/* [ 7] drm_tx_en */
-/* [ 6] nvbi_tx_en */
-/* [ 5] amp_tx_en */
-/* [ 4] aut_tx_en */
-/* [ 3] audi_tx_en */
-/* [ 2] avi_tx_en */
-/* [ 1] gcp_tx_en */
-/* [ 0] acr_tx_en */
-#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3)
-/* [ 1] actspc_hdlr_tgl */
-/* [ 0] actspc_hdlr_en */
-#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8)
-#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9)
-/* [3:0] fc_invact_2d_0[11:8] */
-/* [7:0] fc_invact_2d_0[7:0] */
-#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA)
-
-#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100)
-#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101)
-#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102)
-#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103)
-#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104)
-#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105)
-#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106)
-#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107)
-#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108)
-#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109)
-#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A)
-#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B)
-#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C)
-#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D)
-#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E)
-#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F)
-#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110)
-#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111)
-#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112)
-#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113)
-#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114)
-#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115)
-#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116)
-#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117)
-#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118)
-#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119)
-#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A)
-#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B)
-#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C)
-#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D)
-#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E)
-#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F)
-#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120)
-
-/* Audio Metadata Packet Registers */
-#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128)
-#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129)
-#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A)
-#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B)
-#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C)
-#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D)
-#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E)
-#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F)
-#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130)
-#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131)
-#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132)
-#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133)
-#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134)
-#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135)
-#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136)
-#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137)
-#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138)
-#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139)
-#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A)
-#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B)
-#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C)
-#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D)
-#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E)
-#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F)
-#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140)
-#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141)
-#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142)
-#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143)
-#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144)
-#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145)
-
-/* NTSC VBI Packet Registers */
-#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148)
-#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149)
-#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A)
-#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B)
-#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C)
-#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D)
-#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E)
-#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F)
-#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150)
-#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151)
-#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152)
-#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153)
-#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154)
-#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155)
-#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156)
-#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157)
-#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158)
-#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159)
-#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A)
-#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B)
-#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C)
-#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D)
-#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E)
-#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F)
-#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160)
-#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161)
-#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162)
-#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163)
-#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164)
-#define HDMITX_DWC_FC_DRM_HB01 (DWC_OFFSET_MASK + 0x1168)
-#define HDMITX_DWC_FC_DRM_HB02 (DWC_OFFSET_MASK + 0x1169)
-#define HDMITX_DWC_FC_DRM_PB00 (DWC_OFFSET_MASK + 0x116A)
-#define HDMITX_DWC_FC_DRM_PB01 (DWC_OFFSET_MASK + 0x116B)
-#define HDMITX_DWC_FC_DRM_PB02 (DWC_OFFSET_MASK + 0x116C)
-#define HDMITX_DWC_FC_DRM_PB03 (DWC_OFFSET_MASK + 0x116D)
-#define HDMITX_DWC_FC_DRM_PB04 (DWC_OFFSET_MASK + 0x116E)
-#define HDMITX_DWC_FC_DRM_PB05 (DWC_OFFSET_MASK + 0x116F)
-#define HDMITX_DWC_FC_DRM_PB06 (DWC_OFFSET_MASK + 0x1170)
-#define HDMITX_DWC_FC_DRM_PB07 (DWC_OFFSET_MASK + 0x1171)
-#define HDMITX_DWC_FC_DRM_PB08 (DWC_OFFSET_MASK + 0x1172)
-#define HDMITX_DWC_FC_DRM_PB09 (DWC_OFFSET_MASK + 0x1173)
-#define HDMITX_DWC_FC_DRM_PB10 (DWC_OFFSET_MASK + 0x1174)
-#define HDMITX_DWC_FC_DRM_PB11 (DWC_OFFSET_MASK + 0x1175)
-#define HDMITX_DWC_FC_DRM_PB12 (DWC_OFFSET_MASK + 0x1176)
-#define HDMITX_DWC_FC_DRM_PB13 (DWC_OFFSET_MASK + 0x1177)
-#define HDMITX_DWC_FC_DRM_PB14 (DWC_OFFSET_MASK + 0x1178)
-#define HDMITX_DWC_FC_DRM_PB15 (DWC_OFFSET_MASK + 0x1179)
-#define HDMITX_DWC_FC_DRM_PB16 (DWC_OFFSET_MASK + 0x117A)
-#define HDMITX_DWC_FC_DRM_PB17 (DWC_OFFSET_MASK + 0x117B)
-#define HDMITX_DWC_FC_DRM_PB18 (DWC_OFFSET_MASK + 0x117C)
-#define HDMITX_DWC_FC_DRM_PB19 (DWC_OFFSET_MASK + 0x117D)
-#define HDMITX_DWC_FC_DRM_PB20 (DWC_OFFSET_MASK + 0x117E)
-#define HDMITX_DWC_FC_DRM_PB21 (DWC_OFFSET_MASK + 0x117F)
-#define HDMITX_DWC_FC_DRM_PB22 (DWC_OFFSET_MASK + 0x1180)
-#define HDMITX_DWC_FC_DRM_PB23 (DWC_OFFSET_MASK + 0x1181)
-#define HDMITX_DWC_FC_DRM_PB24 (DWC_OFFSET_MASK + 0x1182)
-#define HDMITX_DWC_FC_DRM_PB25 (DWC_OFFSET_MASK + 0x1183)
-#define HDMITX_DWC_FC_DRM_PB26 (DWC_OFFSET_MASK + 0x1184)
-
-#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200)
-#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201)
-#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202)
-#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203)
-#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204)
-#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205)
-#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206)
-#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207)
-#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208)
-#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209)
-#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A)
-#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B)
-#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C)
-#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D)
-#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E)
-#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F)
-#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210)
-#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211)
-#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212)
-#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213)
-#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214)
-#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215)
-#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216)
-#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217)
-#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218)
-#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219)
-#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A)
-#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B)
-
-/* HDMI Source PHY Registers */
-#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000)
-#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001)
-#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002)
-#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003)
-#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004)
-#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005)
-#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006)
-#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007)
-
-/* I2C Master PHY Registers */
-#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020)
-#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021)
-#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022)
-#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023)
-#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024)
-#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025)
-#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026)
-#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027)
-#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028)
-#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029)
-#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032)
-#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033)
-
-/* Audio Sampler Registers */
-
- /* [ 7] sw_audio_fifo_rst */
- /* [ 5] 0=select SPDIF; 1=select I2S. */
- /* [3:0] i2s_in_en: enable it later in test.c */
-#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100)
-/* [4:0] i2s_width */
-/* [7:5] i2s_mode: 0=standard I2S mode */
-#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101)
-/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */
-/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102)
- /* [ 1] NLPCM */
-#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103)
-
-/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int.
- * Enable it later when audio starts.
- */
-#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104)
-
-#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200)
-#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201)
-#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202)
-#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203)
-#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204)
-#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205)
-#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206)
-/* [ 7] sw_audio_fifo_rst */
-#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300)
-/* [4:0] spdif_width */
-/* [ 7] setnlpcm */
-#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301)
-/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */
-/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302)
-/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303)
-
-/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */
-/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */
-
-/* Main Controller Registers */
-/* [ 6] hdcpclk_disable */
-/* [ 5] cecclk_disable */
-/* [ 4] cscclk_disable */
-/* [ 3] audclk_disable */
-/* [ 2] prepclk_disable */
-/* [ 1] tmdsclk_disable */
-/* [ 0] pixelclk_disable */
-#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001)
-/*
- * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset.
- */
-#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002)
-#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003)
-/* [ 0] CSC enable */
-#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004)
-#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005)
-#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006)
-
-/* Color Space Converter Registers */
-/* [ 7] csc_limit */
-#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100)
-#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101)
-#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102)
-#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103)
-#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104)
-#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105)
-#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106)
-#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107)
-#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108)
-#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109)
-#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A)
-#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B)
-#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C)
-#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D)
-#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E)
-#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F)
-#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110)
-#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111)
-#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112)
-#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113)
-#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114)
-#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115)
-#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116)
-#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117)
-#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118)
-#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119)
-#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A)
-#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B)
-#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C)
-#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D)
-
-/* HDCP Encryption Engine Registers */
-#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000)
-/* [ 4] hdcp_lock */
-/* [ 3] dissha1check */
-/* [ 2] ph2upshiftenc */
-/* [ 1] encryptiondisable */
-/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */
-#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001)
-#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002)
-#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003)
-#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004)
-#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005)
-#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006)
-#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007)
-/* [ 7] hdcp_engaged_int_mask */
-/* [ 6] hdcp_failed_int_mask */
-/* [ 4] i2c_nack_int_mask */
-/* [ 3] lost_arbitration_int_mask */
-/* [ 2] keepout_error_int_mask */
-/* [ 1] ksv_sha1_calc_int_mask */
-/* [ 0] ksv_access_int_mask */
-#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008)
-/* [6:5] unencryptconf */
-/* [ 4] dataenpol */
-/* [ 3] vsyncpol */
-/* [ 1] hsyncpol */
-#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009)
-#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A)
-#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014)
-#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015)
-/* [ 3] sha1_fail */
-/* [ 2] ksv_ctrl_update */
-/* [ 1] Rsvd for read-only ksv_mem_access */
-/* [ 0] ksv_mem_request */
-#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016)
-
-#define HDMITX_DWC_HDCP_BSTATUS_0 (DWC_OFFSET_MASK + 0x5020)
-#define HDMITX_DWC_HDCP_BSTATUS_1 (DWC_OFFSET_MASK + 0x5021)
-#define HDMITX_DWC_HDCP_M0_0 (DWC_OFFSET_MASK + 0x5022)
-#define HDMITX_DWC_HDCP_M0_1 (DWC_OFFSET_MASK + 0x5023)
-#define HDMITX_DWC_HDCP_M0_2 (DWC_OFFSET_MASK + 0x5024)
-#define HDMITX_DWC_HDCP_M0_3 (DWC_OFFSET_MASK + 0x5025)
-#define HDMITX_DWC_HDCP_M0_4 (DWC_OFFSET_MASK + 0x5026)
-#define HDMITX_DWC_HDCP_M0_5 (DWC_OFFSET_MASK + 0x5027)
-#define HDMITX_DWC_HDCP_M0_6 (DWC_OFFSET_MASK + 0x5028)
-#define HDMITX_DWC_HDCP_M0_7 (DWC_OFFSET_MASK + 0x5029)
-#define HDMITX_DWC_HDCP_KSV (DWC_OFFSET_MASK + 0x502A)
-#define HDMITX_DWC_HDCP_VH (DWC_OFFSET_MASK + 0x52A5)
-#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (DWC_OFFSET_MASK + 0x52B9)
-#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (DWC_OFFSET_MASK + 0x52BA)
-#define HDMITX_DWC_HDCP_REVOC_LIST (DWC_OFFSET_MASK + 0x52BB)
-#define HDMITX_DWC_HDCP_REVOC_LIST_END (DWC_OFFSET_MASK + 0x667E)
-
-/* HDCP BKSV Registers */
-#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800)
-#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801)
-#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802)
-#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803)
-#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804)
-
-/* HDCP AN Registers */
-#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805)
-#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806)
-#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807)
-#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808)
-#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809)
-#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A)
-#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B)
-#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C)
-#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D)
-#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E)
-
-/* Encrypted DPK Embedded Storage Registers */
-#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F)
-#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810)
-#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811)
-#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812)
-#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813)
-#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814)
-#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815)
-#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816)
-#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817)
-#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818)
-
-/* HDCP22 Registers */
-#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900)
-#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904)
-#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905)
-#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908)
-#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C)
-#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D)
-#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E)
-
-
-/* ********** CEC related ********** */
-
-/* CEC 2.0 Engine Registers */
-#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00)
-#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02)
-#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05)
-#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06)
-#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07)
-#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08)
-#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10)
-#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11)
-#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12)
-#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13)
-#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14)
-#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15)
-#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16)
-#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17)
-#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18)
-#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19)
-#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A)
-#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B)
-#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C)
-#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D)
-#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E)
-#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F)
-#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20)
-#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21)
-#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22)
-#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23)
-#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24)
-#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25)
-#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26)
-#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27)
-#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28)
-#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29)
-#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A)
-#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B)
-#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C)
-#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D)
-#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E)
-#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F)
-#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30)
-#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31)
-
-/* I2C Master Registers(E-DDC/SCDC) */
-#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00)
-#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01)
-#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02)
-#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03)
-#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04)
-/* [ 2] done_mask */
-/* [ 6] read_req_mask */
-#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05)
-/* [ 6] nack_mask */
-/* [ 2] arbitration_error_mask */
-#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06)
-/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */
-#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07)
-#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08)
-#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09)
-#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A)
-/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */
-/* Where Freq(sfrclkInMHz)=24; */
-#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B)
-#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C)
-#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D)
-#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E)
-#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F)
-#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10)
-#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11)
-#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12)
-#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13)
-/* [ 5] updt_rd_vsyncpoll_en */
-/* [ 4] read_request_en */
-/* [ 0] read_update */
-#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14)
-#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20)
-#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21)
-#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22)
-#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23)
-#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24)
-#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25)
-#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26)
-#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27)
-#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30)
-#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31)
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_lcd.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <drm/drm_modeset_helper.h>
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_mipi_dsi.h>
-#include <video/display_timing.h>
-#include <linux/component.h>
-#include <linux/amlogic/media/vout/lcd/lcd_vout.h>
-#include <linux/amlogic/media/vout/lcd/lcd_notify.h>
-
-#include "am_meson_lcd.h"
-
-struct am_drm_lcd_s {
- struct drm_panel panel;
- struct drm_connector connector;
- struct drm_encoder encoder;
- struct mipi_dsi_host dsi_host;
- struct drm_device *drm;
- struct aml_lcd_drv_s *lcd_drv;
- struct drm_display_mode *mode;
- struct display_timing *timing;
-};
-
-static struct am_drm_lcd_s *am_drm_lcd;
-
-static struct drm_display_mode am_lcd_mode = {
- .name = "panel",
- .status = 0,
- .clock = 74250,
- .hdisplay = 1280,
- .hsync_start = 1390,
- .hsync_end = 1430,
- .htotal = 1650,
- .hskew = 0,
- .vdisplay = 720,
- .vsync_start = 725,
- .vsync_end = 730,
- .vtotal = 750,
- .vscan = 0,
- .vrefresh = 60,
-};
-
-static struct display_timing am_lcd_timing = {
- .pixelclock = { 55000000, 65000000, 75000000 },
- .hactive = { 1024, 1024, 1024 },
- .hfront_porch = { 40, 40, 40 },
- .hback_porch = { 220, 220, 220 },
- .hsync_len = { 20, 60, 100 },
- .vactive = { 768, 768, 768 },
- .vfront_porch = { 7, 7, 7 },
- .vback_porch = { 21, 21, 21 },
- .vsync_len = { 10, 10, 10 },
- .flags = DISPLAY_FLAGS_DE_HIGH,
-};
-
-/* ***************************************************************** */
-/* drm driver function */
-/* ***************************************************************** */
-#if 0
-static inline struct am_drm_lcd_s *host_to_lcd(struct mipi_dsi_host *host)
-{
- return container_of(host, struct am_drm_lcd_s, dsi_host);
-}
-#endif
-
-static inline struct am_drm_lcd_s *con_to_lcd(struct drm_connector *con)
-{
- return container_of(con, struct am_drm_lcd_s, connector);
-}
-
-static inline struct am_drm_lcd_s *encoder_to_lcd(struct drm_encoder *encoder)
-{
- return container_of(encoder, struct am_drm_lcd_s, encoder);
-}
-
-static inline struct am_drm_lcd_s *panel_to_lcd(struct drm_panel *panel)
-{
- return container_of(panel, struct am_drm_lcd_s, panel);
-}
-
-static int am_lcd_connector_get_modes(struct drm_connector *connector)
-{
- struct drm_display_mode *mode;
- struct am_drm_lcd_s *lcd;
- int count = 0;
-
- lcd = con_to_lcd(connector);
-
- pr_info("***************************************************\n");
- pr_info("am_drm_lcd: %s: lcd mode [%s] display size: %d x %d\n",
- __func__, lcd->mode->name,
- lcd->mode->hdisplay, lcd->mode->vdisplay);
-
- mode = drm_mode_duplicate(connector->dev, lcd->mode);
- pr_info("am_drm_lcd: %s: drm mode [%s] display size: %d x %d\n",
- __func__, mode->name, mode->hdisplay, mode->vdisplay);
- pr_info("am_drm_lcd: %s: lcd config size: %d x %d\n",
- __func__, lcd->lcd_drv->lcd_config->lcd_basic.h_active,
- lcd->lcd_drv->lcd_config->lcd_basic.v_active);
-
- drm_mode_probed_add(connector, mode);
- count = 1;
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- pr_info("***************************************************\n");
-
- return count;
-}
-
-enum drm_mode_status am_lcd_connector_mode_valid(
- struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct am_drm_lcd_s *lcd;
-
- lcd = con_to_lcd(connector);
- if (!lcd)
- return MODE_ERROR;
- if (!lcd->lcd_drv)
- return MODE_ERROR;
-
- pr_info("am_drm_lcd: %s: mode [%s] display size: %d x %d\n",
- __func__, mode->name, mode->hdisplay, mode->vdisplay);
- pr_info("am_drm_lcd: %s: lcd config size: %d x %d\n",
- __func__, lcd->lcd_drv->lcd_config->lcd_basic.h_active,
- lcd->lcd_drv->lcd_config->lcd_basic.v_active);
-
- if (mode->hdisplay != lcd->lcd_drv->lcd_config->lcd_basic.h_active)
- return MODE_BAD_WIDTH;
- if (mode->vdisplay != lcd->lcd_drv->lcd_config->lcd_basic.v_active)
- return MODE_BAD_WIDTH;
-
- pr_info("am_drm_lcd: %s %d: check mode OK\n", __func__, __LINE__);
-
- return MODE_OK;
-}
-
-
-static const struct drm_connector_helper_funcs am_lcd_connector_helper_funcs = {
- .get_modes = am_lcd_connector_get_modes,
- .mode_valid = am_lcd_connector_mode_valid,
- //.best_encoder
- //.atomic_best_encoder
-};
-
-static enum drm_connector_status am_lcd_connector_detect(
- struct drm_connector *connector, bool force)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- return connector_status_connected;
-}
-
-#if 0
-static const struct drm_connector_funcs am_lcd_connector_funcs = {
- .dpms = drm_atomic_helper_connector_dpms,
- .detect = am_lcd_connector_detect,
- .fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = drm_connector_cleanup,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-#else
-
-static int am_lcd_connector_dpms(struct drm_connector *connector, int mode)
-{
- int ret = 0;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- ret = drm_atomic_helper_connector_dpms(connector, mode);
- return ret;
-}
-
-static int am_lcd_connector_fill_modes(struct drm_connector *connector,
- uint32_t maxX, uint32_t maxY)
-{
- int count = 0;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
- pr_info("am_drm_lcd: %s %d: count=%d\n", __func__, __LINE__, count);
- return count;
-}
-
-static void am_lcd_connector_destroy(struct drm_connector *connector)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- drm_connector_cleanup(connector);
-}
-
-static void am_lcd_connector_reset(struct drm_connector *connector)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- drm_atomic_helper_connector_reset(connector);
-}
-
-static struct drm_connector_state *am_lcd_connector_duplicate_state(
- struct drm_connector *connector)
-{
- struct drm_connector_state *state;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- state = drm_atomic_helper_connector_duplicate_state(connector);
- return state;
-}
-
-static void am_lcd_connector_destroy_state(struct drm_connector *connector,
- struct drm_connector_state *state)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- drm_atomic_helper_connector_destroy_state(connector, state);
-}
-
-static const struct drm_connector_funcs am_lcd_connector_funcs = {
- .dpms = am_lcd_connector_dpms,
- .detect = am_lcd_connector_detect,
- .fill_modes = am_lcd_connector_fill_modes,
- .destroy = am_lcd_connector_destroy,
- .reset = am_lcd_connector_reset,
- .atomic_duplicate_state = am_lcd_connector_duplicate_state,
- .atomic_destroy_state = am_lcd_connector_destroy_state,
-};
-#endif
-
-static void am_lcd_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-}
-
-static void am_lcd_encoder_enable(struct drm_encoder *encoder)
-{
- enum vmode_e vmode = get_current_vmode();
- struct am_drm_lcd_s *lcd = encoder_to_lcd(encoder);
-
- if (!lcd)
- return;
- if (!lcd->lcd_drv)
- return;
-
- if (vmode == VMODE_LCD)
- DRM_INFO("am_lcd_encoder_enable\n");
- else
- DRM_INFO("am_lcd_encoder_enable fail! vmode:%d\n", vmode);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- vout_notifier_call_chain(VOUT_EVENT_MODE_CHANGE_PRE, &vmode);
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_PREPARE, NULL);
- aml_lcd_notifier_call_chain(LCD_EVENT_ENABLE, NULL);
-
- lcd->lcd_drv->lcd_config->retry_enable_cnt = 0;
- while (lcd->lcd_drv->lcd_config->retry_enable_flag) {
- if (lcd->lcd_drv->lcd_config->retry_enable_cnt++ >=
- LCD_ENABLE_RETRY_MAX)
- break;
- pr_info("am_drm_lcd: retry enable...%d\n",
- lcd->lcd_drv->lcd_config->retry_enable_cnt);
- aml_lcd_notifier_call_chain(LCD_EVENT_IF_POWER_OFF, NULL);
- msleep(1000);
- aml_lcd_notifier_call_chain(LCD_EVENT_IF_POWER_ON, NULL);
- }
- lcd->lcd_drv->lcd_config->retry_enable_cnt = 0;
-
- mutex_unlock(&lcd->lcd_drv->power_mutex);
- vout_notifier_call_chain(VOUT_EVENT_MODE_CHANGE, &vmode);
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-}
-
-static void am_lcd_encoder_disable(struct drm_encoder *encoder)
-{
- struct am_drm_lcd_s *lcd = encoder_to_lcd(encoder);
-
- if (!lcd)
- return;
- if (!lcd->lcd_drv)
- return;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_DISABLE, NULL);
- aml_lcd_notifier_call_chain(LCD_EVENT_UNPREPARE, NULL);
- mutex_unlock(&lcd->lcd_drv->power_mutex);
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-}
-
-static void am_lcd_encoder_commit(struct drm_encoder *encoder)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-}
-
-static int am_lcd_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
- return 0;
-}
-
-static const struct drm_encoder_helper_funcs am_lcd_encoder_helper_funcs = {
- .commit = am_lcd_encoder_commit,
- .mode_set = am_lcd_encoder_mode_set,
- .enable = am_lcd_encoder_enable,
- .disable = am_lcd_encoder_disable,
- .atomic_check = am_lcd_encoder_atomic_check,
-};
-
-static const struct drm_encoder_funcs am_lcd_encoder_funcs = {
- .destroy = drm_encoder_cleanup,
-};
-
-static int am_lcd_disable(struct drm_panel *panel)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
-
- if (!lcd)
- return -ENODEV;
- if (!lcd->lcd_drv)
- return -ENODEV;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_DISABLE, NULL);
- mutex_unlock(&lcd->lcd_drv->power_mutex);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 0;
-}
-
-static int am_lcd_unprepare(struct drm_panel *panel)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
-
- if (!lcd)
- return -ENODEV;
- if (!lcd->lcd_drv)
- return -ENODEV;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_UNPREPARE, NULL);
- mutex_unlock(&lcd->lcd_drv->power_mutex);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 0;
-}
-
-static int am_lcd_prepare(struct drm_panel *panel)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
-
- if (!lcd)
- return -ENODEV;
- if (!lcd->lcd_drv)
- return -ENODEV;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_PREPARE, NULL);
- mutex_unlock(&lcd->lcd_drv->power_mutex);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 0;
-}
-
-static int am_lcd_enable(struct drm_panel *panel)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
-
- if (!lcd)
- return -ENODEV;
- if (!lcd->lcd_drv)
- return -ENODEV;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- mutex_lock(&lcd->lcd_drv->power_mutex);
- aml_lcd_notifier_call_chain(LCD_EVENT_ENABLE, NULL);
- mutex_unlock(&lcd->lcd_drv->power_mutex);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 0;
-}
-
-static int am_lcd_get_modes(struct drm_panel *panel)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
- struct drm_connector *connector = panel->connector;
- struct drm_device *drm = panel->drm;
- struct drm_display_mode *mode;
- struct lcd_config_s *pconf;
-
- if (!lcd->mode)
- return 0;
-
- mode = drm_mode_duplicate(drm, lcd->mode);
- if (!mode) {
- pr_err("error: am_drm_lcd: failed to add mode %ux%u@%u\n",
- mode->hdisplay, mode->vdisplay, mode->vrefresh);
- }
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- mode->type |= DRM_MODE_TYPE_DRIVER;
- mode->type |= DRM_MODE_TYPE_PREFERRED;
-
- drm_mode_set_name(mode);
-
- drm_mode_probed_add(connector, mode);
-
- pconf = lcd->lcd_drv->lcd_config;
- connector->display_info.bpc = pconf->lcd_basic.lcd_bits * 3;
- connector->display_info.width_mm = pconf->lcd_basic.screen_width;
- connector->display_info.height_mm = pconf->lcd_basic.screen_height;
-
- connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 1;
-}
-
-static int am_lcd_get_timings(struct drm_panel *panel,
- unsigned int num_timings,
- struct display_timing *timings)
-{
- struct am_drm_lcd_s *lcd = panel_to_lcd(panel);
-
- if (!lcd)
- return 0;
- if (!lcd->timing)
- return 0;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- num_timings = 1;
-
- if (timings)
- memcpy(&timings[0], lcd->timing, sizeof(struct display_timing));
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return 1;
-}
-
-static const struct drm_panel_funcs am_drm_lcd_funcs = {
- .disable = am_lcd_disable,
- .unprepare = am_lcd_unprepare,
- .prepare = am_lcd_prepare,
- .enable = am_lcd_enable,
- .get_modes = am_lcd_get_modes,
- .get_timings = am_lcd_get_timings,
-};
-
-static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
-{
- struct lcd_config_s *pconf;
- unsigned short tmp;
-
- if (!lcd->lcd_drv) {
- pr_info("invalid lcd driver\n");
- return;
- }
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- pconf = lcd->lcd_drv->lcd_config;
-
- lcd->mode = &am_lcd_mode;
- lcd->timing = &am_lcd_timing;
-
- lcd->mode->clock = pconf->lcd_timing.lcd_clk / 1000;
- lcd->mode->hdisplay = pconf->lcd_basic.h_active;
- tmp = pconf->lcd_basic.h_period - pconf->lcd_basic.h_active -
- pconf->lcd_timing.hsync_bp;
- lcd->mode->hsync_start = pconf->lcd_basic.h_active + tmp -
- pconf->lcd_timing.hsync_width;
- lcd->mode->hsync_end = pconf->lcd_basic.h_active + tmp;
- lcd->mode->htotal = pconf->lcd_basic.h_period;
- lcd->mode->vdisplay = pconf->lcd_basic.v_active;
- tmp = pconf->lcd_basic.v_period - pconf->lcd_basic.v_active -
- pconf->lcd_timing.vsync_bp;
- lcd->mode->vsync_start = pconf->lcd_basic.v_active + tmp -
- pconf->lcd_timing.vsync_width;
- lcd->mode->vsync_end = pconf->lcd_basic.v_active + tmp;
- lcd->mode->vtotal = pconf->lcd_basic.v_period;
- lcd->mode->width_mm = pconf->lcd_basic.screen_width;
- lcd->mode->height_mm = pconf->lcd_basic.screen_height;
- lcd->mode->vrefresh = pconf->lcd_timing.sync_duration_num /
- pconf->lcd_timing.sync_duration_den;
-
- lcd->timing->pixelclock.min = pconf->lcd_timing.lcd_clk;
- lcd->timing->pixelclock.typ = pconf->lcd_timing.lcd_clk;
- lcd->timing->pixelclock.max = pconf->lcd_timing.lcd_clk;
- lcd->timing->hactive.min = pconf->lcd_basic.h_active;
- lcd->timing->hactive.typ = pconf->lcd_basic.h_active;
- lcd->timing->hactive.max = pconf->lcd_basic.h_active;
- tmp = pconf->lcd_basic.h_period - pconf->lcd_basic.h_active -
- pconf->lcd_timing.hsync_bp - pconf->lcd_timing.hsync_width;
- lcd->timing->hfront_porch.min = tmp;
- lcd->timing->hfront_porch.typ = tmp;
- lcd->timing->hfront_porch.max = tmp;
- lcd->timing->hback_porch.min = pconf->lcd_timing.hsync_bp;
- lcd->timing->hback_porch.typ = pconf->lcd_timing.hsync_bp;
- lcd->timing->hback_porch.max = pconf->lcd_timing.hsync_bp;
- lcd->timing->hsync_len.min = pconf->lcd_timing.hsync_width;
- lcd->timing->hsync_len.typ = pconf->lcd_timing.hsync_width;
- lcd->timing->hsync_len.max = pconf->lcd_timing.hsync_width;
- lcd->timing->vactive.min = pconf->lcd_basic.v_active;
- lcd->timing->vactive.typ = pconf->lcd_basic.v_active;
- lcd->timing->vactive.max = pconf->lcd_basic.v_active;
- tmp = pconf->lcd_basic.v_period - pconf->lcd_basic.v_active -
- pconf->lcd_timing.vsync_bp - pconf->lcd_timing.vsync_width;
- lcd->timing->vfront_porch.min = tmp;
- lcd->timing->vfront_porch.typ = tmp;
- lcd->timing->vfront_porch.max = tmp;
- lcd->timing->vback_porch.min = pconf->lcd_timing.vsync_bp;
- lcd->timing->vback_porch.typ = pconf->lcd_timing.vsync_bp;
- lcd->timing->vback_porch.max = pconf->lcd_timing.vsync_bp;
- lcd->timing->vsync_len.min = pconf->lcd_timing.vsync_width;
- lcd->timing->vsync_len.typ = pconf->lcd_timing.vsync_width;
- lcd->timing->vsync_len.max = pconf->lcd_timing.vsync_width;
-
- pr_info("am_drm_lcd: %s: lcd config:\n"
- "lcd_clk %d\n"
- "h_active %d\n"
- "v_active %d\n"
- "screen_width %d\n"
- "screen_height %d\n"
- "sync_duration_den %d\n"
- "sync_duration_num %d\n",
- __func__,
- lcd->lcd_drv->lcd_config->lcd_timing.lcd_clk,
- lcd->lcd_drv->lcd_config->lcd_basic.h_active,
- lcd->lcd_drv->lcd_config->lcd_basic.v_active,
- lcd->lcd_drv->lcd_config->lcd_basic.screen_width,
- lcd->lcd_drv->lcd_config->lcd_basic.screen_height,
- lcd->lcd_drv->lcd_config->lcd_timing.sync_duration_den,
- lcd->lcd_drv->lcd_config->lcd_timing.sync_duration_num);
- pr_info("am_drm_lcd: %s: display mode:\n"
- "clock %d\n"
- "hdisplay %d\n"
- "vdisplay %d\n"
- "width_mm %d\n"
- "height_mm %d\n"
- "vrefresh %d\n",
- __func__,
- lcd->mode->clock,
- lcd->mode->hdisplay,
- lcd->mode->vdisplay,
- lcd->mode->width_mm,
- lcd->mode->height_mm,
- lcd->mode->vrefresh);
- pr_info("am_drm_lcd: %s: timing:\n"
- "pixelclock %d\n"
- "hactive %d\n"
- "vactive %d\n",
- __func__,
- lcd->timing->pixelclock.typ,
- lcd->timing->hactive.typ,
- lcd->timing->vactive.typ);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-}
-
-static const struct of_device_id am_meson_lcd_dt_ids[] = {
- { .compatible = "amlogic,drm-lcd", },
- {},
-};
-
-static int am_meson_lcd_bind(struct device *dev, struct device *master,
- void *data)
-{
- struct drm_device *drm = data;
- struct drm_connector *connector;
- struct drm_encoder *encoder;
- int encoder_type, connector_type;
- int ret = 0;
-
- am_drm_lcd = kzalloc(sizeof(*am_drm_lcd), GFP_KERNEL);
- if (!am_drm_lcd)
- return -ENOMEM;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- am_drm_lcd->lcd_drv = aml_lcd_get_driver();
- if (!am_drm_lcd->lcd_drv) {
- pr_err("invalid lcd driver, exit\n");
- return -ENODEV;
- }
-
- am_drm_lcd_display_mode_timing_init(am_drm_lcd);
-
- drm_panel_init(&am_drm_lcd->panel);
- am_drm_lcd->panel.dev = NULL;
- am_drm_lcd->panel.funcs = &am_drm_lcd_funcs;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- ret = drm_panel_add(&am_drm_lcd->panel);
- if (ret < 0)
- return ret;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- am_drm_lcd->drm = drm;
-
- encoder = &am_drm_lcd->encoder;
- connector = &am_drm_lcd->connector;
- encoder_type = DRM_MODE_ENCODER_LVDS;
- connector_type = DRM_MODE_CONNECTOR_LVDS;
-
- /* Encoder */
- drm_encoder_helper_add(encoder, &am_lcd_encoder_helper_funcs);
- ret = drm_encoder_init(drm, encoder, &am_lcd_encoder_funcs,
- encoder_type, "am_lcd_encoder");
- if (ret) {
- pr_err("error: am_drm_lcd: Failed to init lcd encoder\n");
- return ret;
- }
- pr_info("am_drm_lcd: %s %d: encoder possible_crtcs=%d\n",
- __func__, __LINE__, encoder->possible_crtcs);
-
- /* Connector */
- drm_connector_helper_add(connector, &am_lcd_connector_helper_funcs);
- ret = drm_connector_init(drm, connector, &am_lcd_connector_funcs,
- connector_type);
- if (ret) {
- pr_err("error: am_drm_lcd: Failed to init lcd connector\n");
- return ret;
- }
-
- /* force possible_crtcs */
- encoder->possible_crtcs = BIT(0);
-
- drm_mode_connector_attach_encoder(connector, encoder);
-
- pr_info("am_drm_lcd: register ok\n");
-
- return ret;
-}
-
-static void am_meson_lcd_unbind(struct device *dev, struct device *master,
- void *data)
-{
- if (!am_drm_lcd)
- return;
-
- if (!am_drm_lcd->lcd_drv)
- return;
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- drm_panel_detach(&am_drm_lcd->panel);
- drm_panel_remove(&am_drm_lcd->panel);
-
- pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
-
- return;
-}
-
-static const struct component_ops am_meson_lcd_ops = {
- .bind = am_meson_lcd_bind,
- .unbind = am_meson_lcd_unbind,
-};
-
-static int am_meson_lcd_probe(struct platform_device *pdev)
-{
- return component_add(&pdev->dev, &am_meson_lcd_ops);
-}
-
-static int am_meson_lcd_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &am_meson_lcd_ops);
- return 0;
-}
-
-static struct platform_driver am_meson_lcd_pltfm_driver = {
- .probe = am_meson_lcd_probe,
- .remove = am_meson_lcd_remove,
- .driver = {
- .name = "meson-lcd",
- .of_match_table = am_meson_lcd_dt_ids,
- },
-};
-
-module_platform_driver(am_meson_lcd_pltfm_driver);
-
-MODULE_AUTHOR("MultiMedia Amlogic <multimedia-sh@amlogic.com>");
-MODULE_DESCRIPTION("Amlogic Meson Drm LCD driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_lcd.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __AM_DRM_LCD_H
-#define __AM_DRM_LCD_H
-
-#include "am_meson_drv.h"
-
-#endif
-
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_vpu.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#include <drm/drmP.h>
-#include <drm/drm_plane.h>
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_fb_cma_helper.h>
-#include <drm/drm_gem_cma_helper.h>
-
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <linux/of.h>
-#include <linux/component.h>
-#include <linux/of_reserved_mem.h>
-#include <linux/dma-contiguous.h>
-#include <linux/cma.h>
-#ifdef CONFIG_DRM_MESON_USE_ION
-#include <ion/ion_priv.h>
-#endif
-
-/* Amlogic Headers */
-#include <linux/amlogic/media/vout/vout_notify.h>
-#include <linux/amlogic/media/amvecm/amvecm.h>
-
-#include "osd.h"
-#include "osd_drm.h"
-#ifdef CONFIG_DRM_MESON_USE_ION
-#include "am_meson_fb.h"
-#endif
-#include "am_meson_vpu.h"
-
-/*
- * Video Processing Unit
- *
- * VPU Handles the Global Video Processing, it includes management of the
- * clocks gates, blocks reset lines and power domains.
- *
- * What is missing :
- * - Full reset of entire video processing HW blocks
- * - Scaling and setup of the VPU clock
- * - Bus clock gates
- * - Powering up video processing HW blocks
- * - Powering Up HDMI controller and PHY
- */
-struct am_osd_plane {
- struct drm_plane base; //must be first element.
- struct meson_drm *drv; //point to struct parent.
- struct dentry *plane_debugfs_dir;
-
- u32 osd_idx;
-};
-#define to_am_osd_plane(x) container_of(x, struct am_osd_plane, base)
-
-struct am_meson_crtc {
- struct drm_crtc base;
- struct device *dev;
- struct drm_device *drm_dev;
-
- struct meson_drm *priv;
-
- struct drm_pending_vblank_event *event;
-
- unsigned int vblank_irq;
- spinlock_t vblank_irq_lock;
- bool vblank_enable;
-
- struct dentry *crtc_debugfs_dir;
-};
-
-#define to_am_meson_crtc(x) container_of(x, struct am_meson_crtc, base)
-
-struct am_vout_mode {
- char name[DRM_DISPLAY_MODE_LEN];
- enum vmode_e mode;
- int width, height, vrefresh;
- unsigned int flags;
-};
-
-static struct am_vout_mode am_vout_modes[] = {
- { "1080p60hz", VMODE_HDMI, 1920, 1080, 60, 0},
- { "1080p30hz", VMODE_HDMI, 1920, 1080, 30, 0},
- { "1080p50hz", VMODE_HDMI, 1920, 1080, 50, 0},
- { "1080p25hz", VMODE_HDMI, 1920, 1080, 25, 0},
- { "1080p24hz", VMODE_HDMI, 1920, 1080, 24, 0},
- { "2160p30hz", VMODE_HDMI, 3840, 2160, 30, 0},
- { "2160p60hz", VMODE_HDMI, 3840, 2160, 60, 0},
- { "2160p50hz", VMODE_HDMI, 3840, 2160, 50, 0},
- { "2160p25hz", VMODE_HDMI, 3840, 2160, 25, 0},
- { "2160p24hz", VMODE_HDMI, 3840, 2160, 24, 0},
- { "1080i60hz", VMODE_HDMI, 1920, 1080, 60, DRM_MODE_FLAG_INTERLACE},
- { "1080i50hz", VMODE_HDMI, 1920, 1080, 50, DRM_MODE_FLAG_INTERLACE},
- { "720p60hz", VMODE_HDMI, 1280, 720, 60, 0},
- { "720p50hz", VMODE_HDMI, 1280, 720, 50, 0},
- { "480p60hz", VMODE_HDMI, 720, 480, 60, 0},
- { "480i60hz", VMODE_HDMI, 720, 480, 60, DRM_MODE_FLAG_INTERLACE},
- { "576p50hz", VMODE_HDMI, 720, 576, 50, 0},
- { "576i50hz", VMODE_HDMI, 720, 576, 50, DRM_MODE_FLAG_INTERLACE},
- { "480p60hz", VMODE_HDMI, 720, 480, 60, 0},
-};
-
-
-static struct osd_device_data_s osd_gxbb = {
- .cpu_id = __MESON_CPU_MAJOR_ID_GXBB,
- .osd_ver = OSD_NORMAL,
- .afbc_type = NO_AFBC,
- .osd_count = 2,
- .has_deband = 0,
- .has_lut = 0,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 32,
- .vpp_fifo_len = 0x77f,
- .dummy_data = 0x00808000,
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_gxl = {
- .cpu_id = __MESON_CPU_MAJOR_ID_GXL,
- .osd_ver = OSD_NORMAL,
- .afbc_type = NO_AFBC,
- .osd_count = 2,
- .has_deband = 0,
- .has_lut = 0,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 32,
- .vpp_fifo_len = 0x77f,
- .dummy_data = 0x00808000,
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_gxm = {
- .cpu_id = __MESON_CPU_MAJOR_ID_GXM,
- .osd_ver = OSD_NORMAL,
- .afbc_type = MESON_AFBC,
- .osd_count = 2,
- .has_deband = 0,
- .has_lut = 0,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 32,
- .vpp_fifo_len = 0xfff,
- .dummy_data = 0x00202000,/* dummy data is different */
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_txl = {
- .cpu_id = __MESON_CPU_MAJOR_ID_TXL,
- .osd_ver = OSD_NORMAL,
- .afbc_type = NO_AFBC,
- .osd_count = 2,
- .has_deband = 0,
- .has_lut = 0,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 64,
- .vpp_fifo_len = 0x77f,
- .dummy_data = 0x00808000,
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_txlx = {
- .cpu_id = __MESON_CPU_MAJOR_ID_TXLX,
- .osd_ver = OSD_NORMAL,
- .afbc_type = NO_AFBC,
- .osd_count = 2,
- .has_deband = 1,
- .has_lut = 1,
- .has_rdma = 1,
- .has_dolby_vision = 1,
- .osd_fifo_len = 64, /* fifo len 64*8 = 512 */
- .vpp_fifo_len = 0x77f,
- .dummy_data = 0x00808000,
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_axg = {
- .cpu_id = __MESON_CPU_MAJOR_ID_AXG,
- .osd_ver = OSD_SIMPLE,
- .afbc_type = NO_AFBC,
- .osd_count = 1,
- .has_deband = 1,
- .has_lut = 1,
- .has_rdma = 0,
- .has_dolby_vision = 0,
- /* use iomap its self, no rdma, no canvas, no freescale */
- .osd_fifo_len = 64, /* fifo len 64*8 = 512 */
- .vpp_fifo_len = 0x400,
- .dummy_data = 0x00808000,
- .has_viu2 = 0,
-};
-
-static struct osd_device_data_s osd_g12a = {
- .cpu_id = __MESON_CPU_MAJOR_ID_G12A,
- .osd_ver = OSD_HIGH_ONE,
- .afbc_type = MALI_AFBC,
- .osd_count = 4,
- .has_deband = 1,
- .has_lut = 1,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 64, /* fifo len 64*8 = 512 */
- .vpp_fifo_len = 0xfff,/* 2048 */
- .dummy_data = 0x00808000,
- .has_viu2 = 1,
-};
-
-static struct osd_device_data_s osd_g12b = {
- .cpu_id = __MESON_CPU_MAJOR_ID_G12B,
- .osd_ver = OSD_HIGH_ONE,
- .afbc_type = MALI_AFBC,
- .osd_count = 4,
- .has_deband = 1,
- .has_lut = 1,
- .has_rdma = 1,
- .has_dolby_vision = 0,
- .osd_fifo_len = 64, /* fifo len 64*8 = 512 */
- .vpp_fifo_len = 0xfff,/* 2048 */
- .dummy_data = 0x00808000,
- .has_viu2 = 1,
-};
-
-static struct osd_device_data_s osd_meson_dev;
-static u32 logo_memsize;
-static struct page *logo_page;
-static struct delayed_work osd_dwork;
-static struct platform_device *gp_dev;
-
-
-int am_meson_crtc_dts_info_set(const void *dt_match_data)
-{
- struct osd_device_data_s *osd_meson;
-
- osd_meson = (struct osd_device_data_s *)dt_match_data;
- if (osd_meson) {
- memcpy(&osd_meson_dev, osd_meson,
- sizeof(struct osd_device_data_s));
- osd_meson_dev.viu1_osd_count = osd_meson_dev.osd_count;
- if (osd_meson_dev.has_viu2) {
- /* set viu1 osd count */
- osd_meson_dev.viu1_osd_count--;
- osd_meson_dev.viu2_index = osd_meson_dev.viu1_osd_count;
- }
- } else {
- DRM_ERROR("%s data NOT match\n", __func__);
- return -1;
- }
-
- return 0;
-}
-
-static const struct drm_plane_funcs am_osd_plane_funs = {
- .update_plane = drm_atomic_helper_update_plane,
- .disable_plane = drm_atomic_helper_disable_plane,
- .destroy = drm_plane_cleanup,
- .reset = drm_atomic_helper_plane_reset,
- .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
-};
-
-int am_osd_begin_display(
- struct drm_plane *plane,
- struct drm_plane_state *new_state)
-{
- struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
-
- DRM_DEBUG("%s osd %d.\n", __func__, osd_plane->osd_idx);
- return 0;
-}
-
-void am_osd_end_display(
- struct drm_plane *plane,
- struct drm_plane_state *old_state)
-{
- struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
-
- DRM_DEBUG("%s osd %d.\n", __func__, osd_plane->osd_idx);
-}
-
-void am_osd_do_display(
- struct drm_plane *plane,
- struct drm_plane_state *old_state)
-{
- struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
- struct drm_plane_state *state = plane->state;
- struct drm_framebuffer *fb = state->fb;
- struct meson_drm *drv = osd_plane->drv;
- struct osd_plane_map_s plane_map;
-#ifdef CONFIG_DRM_MESON_USE_ION
- struct am_meson_fb *meson_fb;
-#else
- struct drm_gem_cma_object *gem;
-#endif
- int format = DRM_FORMAT_ARGB8888;
- dma_addr_t phyaddr;
- unsigned long flags;
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(drv->crtc);
-
- //DRM_INFO("%s osd %d.\n", __func__, osd_plane->osd_idx);
-
- switch (fb->pixel_format) {
- case DRM_FORMAT_XRGB8888:
- /*
- *force convert to ARGB8888 format,
- *because overlay layer needs to display
- */
- format = COLOR_INDEX_32_XRGB;//COLOR_INDEX_32_ARGB;
- break;
- case DRM_FORMAT_XBGR8888:
- format = COLOR_INDEX_32_XBGR;
- break;
- case DRM_FORMAT_RGBX8888:
- format = COLOR_INDEX_32_RGBX;
- break;
- case DRM_FORMAT_BGRX8888:
- format = COLOR_INDEX_32_BGRX;
- break;
- case DRM_FORMAT_ARGB8888:
- format = COLOR_INDEX_32_ARGB;
- break;
- case DRM_FORMAT_ABGR8888:
- format = COLOR_INDEX_32_ABGR;
- break;
- case DRM_FORMAT_RGBA8888:
- format = COLOR_INDEX_32_RGBA;
- break;
- case DRM_FORMAT_BGRA8888:
- format = COLOR_INDEX_32_BGRA;
- break;
- case DRM_FORMAT_RGB888:
- format = COLOR_INDEX_24_RGB;
- break;
- case DRM_FORMAT_RGB565:
- format = COLOR_INDEX_16_565;
- break;
- case DRM_FORMAT_ARGB1555:
- format = COLOR_INDEX_16_1555_A;
- break;
- case DRM_FORMAT_ARGB4444:
- format = COLOR_INDEX_16_4444_A;
- break;
- default:
- DRM_INFO("unsupport fb->pixel_format=%x\n", fb->pixel_format);
- break;
- };
-
-
-#ifdef CONFIG_DRM_MESON_USE_ION
- meson_fb = container_of(fb, struct am_meson_fb, base);
- phyaddr = am_meson_gem_object_get_phyaddr(drv, meson_fb->bufp);
- if (meson_fb->bufp->bscatter)
- DRM_ERROR("ERROR:am_meson_plane meet a scatter framebuffer.\n");
-#else
- /* Update Canvas with buffer address */
- gem = drm_fb_cma_get_gem_obj(fb, 0);
- phyaddr = gem->paddr;
-#endif
-
- /* setup osd display parameters */
- plane_map.plane_index = osd_plane->osd_idx;
- plane_map.zorder = state->zpos;
- plane_map.phy_addr = phyaddr;
- plane_map.enable = 1;
- plane_map.format = format;
- plane_map.byte_stride = fb->pitches[0];
-
- plane_map.src_x = state->src_x;
- plane_map.src_y = state->src_y;
- plane_map.src_w = (state->src_w >> 16) & 0xffff;
- plane_map.src_h = (state->src_h >> 16) & 0xffff;
-
- plane_map.dst_x = state->crtc_x;
- plane_map.dst_y = state->crtc_y;
- plane_map.dst_w = state->crtc_w;
- plane_map.dst_h = state->crtc_h;
- #if 0
- DRM_INFO("flags:%d pixel_format:%d,zpos=%d\n",
- fb->flags, fb->pixel_format, state->zpos);
- DRM_INFO("plane index=%d, type=%d\n", plane->index, plane->type);
- #endif
-
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- osd_drm_plane_page_flip(&plane_map);
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
-}
-
-int am_osd_check(struct drm_plane *plane, struct drm_plane_state *state)
-{
- struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
-
- DRM_DEBUG("%s osd %d.\n", __func__, osd_plane->osd_idx);
- return 0;
-}
-
-void am_osd_blank(struct drm_plane *plane, struct drm_plane_state *old_state)
-{
- struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
-
- DRM_DEBUG("%s osd %d.\n", __func__, osd_plane->osd_idx);
-}
-
-static const struct drm_plane_helper_funcs am_osd_helper_funcs = {
- .prepare_fb = am_osd_begin_display,
- .cleanup_fb = am_osd_end_display,
- .atomic_update = am_osd_do_display,
- .atomic_check = am_osd_check,
- .atomic_disable = am_osd_blank,
-};
-
-static const uint32_t supported_drm_formats[] = {
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_RGB888,
- DRM_FORMAT_RGB565,
-};
-
-struct am_osd_plane *am_osd_plane_create(struct meson_drm *priv, u32 type)
-{
- struct am_osd_plane *osd_plane;
- struct drm_plane *plane;
- char *plane_name = NULL;
-
- osd_plane = devm_kzalloc(priv->drm->dev, sizeof(*osd_plane),
- GFP_KERNEL);
- if (!osd_plane)
- return 0;
-
- osd_plane->drv = priv;
- plane = &osd_plane->base;
-
- if (type == DRM_PLANE_TYPE_PRIMARY) {
- osd_plane->osd_idx = 0;
- plane_name = "osd-0";
- } else if (type == DRM_PLANE_TYPE_CURSOR) {
- osd_plane->osd_idx = 1;
- plane_name = "osd-1";
- }
-
- drm_universal_plane_init(priv->drm, plane, 0xFF,
- &am_osd_plane_funs,
- supported_drm_formats,
- ARRAY_SIZE(supported_drm_formats),
- NULL,
- type, plane_name);
-
- drm_plane_helper_add(plane, &am_osd_helper_funcs);
- osd_drm_debugfs_add(&(osd_plane->plane_debugfs_dir),
- plane_name, osd_plane->osd_idx);
- return osd_plane;
-}
-
-int am_meson_plane_create(struct meson_drm *priv)
-{
- struct am_osd_plane *plane;
-
- DRM_DEBUG("%s. enter\n", __func__);
- /*crate primary plane*/
- plane = am_osd_plane_create(priv, DRM_PLANE_TYPE_PRIMARY);
- if (plane == NULL)
- return -ENOMEM;
-
- priv->primary_plane = &(plane->base);
-
- /*crate cursor plane*/
- plane = am_osd_plane_create(priv, DRM_PLANE_TYPE_CURSOR);
- if (plane == NULL)
- return -ENOMEM;
-
- priv->cursor_plane = &(plane->base);
-
- return 0;
-}
-
-char *am_meson_crtc_get_voutmode(struct drm_display_mode *mode)
-{
- int i;
-
- if (!strcmp(mode->name, "panel"))
- return "panel";
-
- for (i = 0; i < ARRAY_SIZE(am_vout_modes); i++) {
- if ((am_vout_modes[i].width == mode->hdisplay)
- && (am_vout_modes[i].height == mode->vdisplay)
- && (am_vout_modes[i].vrefresh == mode->vrefresh)
- && (am_vout_modes[i].flags ==
- (mode->flags&DRM_MODE_FLAG_INTERLACE)))
- return am_vout_modes[i].name;
- }
- return NULL;
-}
-
-void am_meson_crtc_handle_vsync(struct am_meson_crtc *amcrtc)
-{
- unsigned long flags;
- struct drm_crtc *crtc;
-
- crtc = &amcrtc->base;
- drm_crtc_handle_vblank(crtc);
-
- spin_lock_irqsave(&crtc->dev->event_lock, flags);
- if (amcrtc->event) {
- drm_crtc_send_vblank_event(crtc, amcrtc->event);
- drm_crtc_vblank_put(crtc);
- amcrtc->event = NULL;
- }
- spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-}
-
-int am_meson_crtc_set_mode(struct drm_mode_set *set)
-{
- struct am_meson_crtc *amcrtc;
- int ret;
-
- DRM_DEBUG_DRIVER("%s\n", __func__);
- amcrtc = to_am_meson_crtc(set->crtc);
- ret = drm_atomic_helper_set_config(set);
-
- return ret;
-}
-
-static const struct drm_crtc_funcs am_meson_crtc_funcs = {
- .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
- .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
- .destroy = drm_crtc_cleanup,
- .page_flip = drm_atomic_helper_page_flip,
- .reset = drm_atomic_helper_crtc_reset,
- .set_config = am_meson_crtc_set_mode,
-};
-
-static int am_meson_crtc_loader_protect(struct drm_crtc *crtc, bool on)
-{
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(crtc);
-
- DRM_INFO("%s %d\n", __func__, on);
-
- if (on) {
- enable_irq(amcrtc->vblank_irq);
- drm_crtc_vblank_on(crtc);
- } else {
- disable_irq(amcrtc->vblank_irq);
- drm_crtc_vblank_off(crtc);
- }
-
- return 0;
-}
-
-static int am_meson_crtc_enable_vblank(struct drm_crtc *crtc)
-{
- unsigned long flags;
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(crtc);
-
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- amcrtc->vblank_enable = true;
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
-
- return 0;
-}
-
-static void am_meson_crtc_disable_vblank(struct drm_crtc *crtc)
-{
- unsigned long flags;
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(crtc);
-
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- amcrtc->vblank_enable = false;
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
-}
-
-static const struct meson_crtc_funcs meson_private_crtc_funcs = {
- .loader_protect = am_meson_crtc_loader_protect,
- .enable_vblank = am_meson_crtc_enable_vblank,
- .disable_vblank = am_meson_crtc_disable_vblank,
-};
-
-static bool am_meson_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- //DRM_INFO("%s !!\n", __func__);
-
- return true;
-}
-
-void am_meson_crtc_enable(struct drm_crtc *crtc)
-{
- unsigned long flags;
- char *name;
- enum vmode_e mode;
- struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(crtc);
-
- DRM_INFO("%s\n", __func__);
- if (!adjusted_mode) {
- DRM_ERROR("meson_crtc_enable fail, unsupport mode:%s\n",
- adjusted_mode->name);
- return;
- }
- DRM_INFO("%s: %s\n", __func__, adjusted_mode->name);
-
- name = am_meson_crtc_get_voutmode(adjusted_mode);
- mode = validate_vmode(name);
- if (mode == VMODE_MAX) {
- DRM_ERROR("no matched vout mode\n");
- return;
- }
-
- set_vout_init(mode);
- update_vout_viu();
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- amcrtc->vblank_enable = true;
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
- enable_irq(amcrtc->vblank_irq);
-}
-
-void am_meson_crtc_disable(struct drm_crtc *crtc)
-{
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(crtc);
- unsigned long flags;
-
- DRM_INFO("%s\n", __func__);
- if (crtc->state->event && !crtc->state->active) {
- spin_lock_irq(&crtc->dev->event_lock);
- drm_crtc_send_vblank_event(crtc, crtc->state->event);
- spin_unlock_irq(&crtc->dev->event_lock);
- crtc->state->event = NULL;
- }
-
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- amcrtc->vblank_enable = false;
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
-
- disable_irq(amcrtc->vblank_irq);
-}
-
-void am_meson_crtc_commit(struct drm_crtc *crtc)
-{
- //DRM_INFO("%s\n", __func__);
-}
-
-void am_meson_crtc_atomic_begin(struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state)
-{
- struct am_meson_crtc *amcrtc;
- unsigned long flags;
-
- amcrtc = to_am_meson_crtc(crtc);
-
- if (crtc->state->event) {
- WARN_ON(drm_crtc_vblank_get(crtc) != 0);
-
- spin_lock_irqsave(&crtc->dev->event_lock, flags);
- amcrtc->event = crtc->state->event;
- spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
- crtc->state->event = NULL;
- }
-}
-
-void am_meson_crtc_atomic_flush(struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state)
-{
- struct drm_color_ctm *ctm;
- struct drm_color_lut *lut;
- int gamma_lut_size = 0;
-
- if (crtc->state->color_mgmt_changed) {
- DRM_INFO("%s color_mgmt_changed!\n", __func__);
- if (crtc->state->ctm) {
- DRM_INFO("%s color_mgmt_changed 1!\n", __func__);
- ctm = (struct drm_color_ctm *)
- crtc->state->ctm->data;
- am_meson_ctm_set(0, ctm);
- }
- if (crtc->state->gamma_lut) {
- DRM_INFO("%s color_mgmt_changed 2!\n", __func__);
- lut = (struct drm_color_lut *)
- crtc->state->gamma_lut->data;
- gamma_lut_size = amvecm_drm_get_gamma_size(0);
- amvecm_drm_gamma_set(0, lut, gamma_lut_size);
- }
- }
-}
-
-static const struct drm_crtc_helper_funcs am_crtc_helper_funcs = {
- .enable = am_meson_crtc_enable,
- .disable = am_meson_crtc_disable,
- .commit = am_meson_crtc_commit,
- .mode_fixup = am_meson_crtc_mode_fixup,
- .atomic_begin = am_meson_crtc_atomic_begin,
- .atomic_flush = am_meson_crtc_atomic_flush,
-};
-
-int am_meson_crtc_create(struct am_meson_crtc *amcrtc)
-{
- struct meson_drm *priv = amcrtc->priv;
- struct drm_crtc *crtc = &amcrtc->base;
- int gamma_lut_size = 0;
- int ret;
-
- DRM_INFO("%s\n", __func__);
- ret = drm_crtc_init_with_planes(priv->drm, crtc,
- priv->primary_plane, priv->cursor_plane,
- &am_meson_crtc_funcs, "amlogic vpu");
- if (ret) {
- dev_err(amcrtc->dev, "Failed to init CRTC\n");
- return ret;
- }
-
- drm_crtc_helper_add(crtc, &am_crtc_helper_funcs);
- osd_drm_init(&osd_meson_dev);
-
- amvecm_drm_init(0);
- amvecm_drm_gamma_enable(0);
- gamma_lut_size = amvecm_drm_get_gamma_size(0);
- drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
- drm_crtc_enable_color_mgmt(crtc, 0, true, gamma_lut_size);
-
- priv->crtc = crtc;
- return 0;
-}
-
-void am_meson_crtc_irq(struct meson_drm *priv)
-{
- unsigned long flags;
- struct am_meson_crtc *amcrtc = to_am_meson_crtc(priv->crtc);
-
- spin_lock_irqsave(&amcrtc->vblank_irq_lock, flags);
- if (amcrtc->vblank_enable) {
- osd_drm_vsync_isr_handler();
- am_meson_crtc_handle_vsync(amcrtc);
- }
- spin_unlock_irqrestore(&amcrtc->vblank_irq_lock, flags);
-}
-
-static irqreturn_t am_meson_vpu_irq(int irq, void *arg)
-{
- struct drm_device *dev = arg;
- struct meson_drm *priv = dev->dev_private;
-
- am_meson_crtc_irq(priv);
-
- return IRQ_HANDLED;
-}
-
-static void mem_free_work(struct work_struct *work)
-{
- if (logo_memsize > 0) {
-#ifdef CONFIG_CMA
- pr_info("%s, free memory: addr:0x%x\n",
- __func__, logo_memsize);
-
- dma_release_from_contiguous(&(gp_dev->dev),
- logo_page,
- logo_memsize >> PAGE_SHIFT);
-#endif
- }
-}
-
-static int am_meson_vpu_bind(struct device *dev,
- struct device *master, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct drm_device *drm_dev = data;
- struct meson_drm *private = drm_dev->dev_private;
- struct am_meson_crtc *amcrtc;
-#ifdef CONFIG_CMA
- struct cma *cma;
-#endif
- int ret, irq;
-
- /* Allocate crtc struct */
- DRM_DEBUG("%s\n", __func__);
- amcrtc = devm_kzalloc(dev, sizeof(*amcrtc),
- GFP_KERNEL);
- if (!amcrtc)
- return -ENOMEM;
-
- amcrtc->priv = private;
- amcrtc->dev = dev;
- amcrtc->drm_dev = drm_dev;
-
- dev_set_drvdata(dev, amcrtc);
-
- /* init reserved memory */
- ret = of_reserved_mem_device_init(&pdev->dev);
- if (ret != 0)
- dev_err(dev, "failed to init reserved memory\n");
- else {
-#ifdef CONFIG_CMA
- gp_dev = pdev;
- cma = dev_get_cma_area(&pdev->dev);
- if (cma) {
- logo_memsize = cma_get_size(cma);
- pr_info("reserved memory base:0x%llx, size:0x%x\n",
- cma_get_base(cma), logo_memsize);
- if (logo_memsize > 0) {
- logo_page = dma_alloc_from_contiguous(
- &pdev->dev,
- logo_memsize >> PAGE_SHIFT,
- 0);
- if (!logo_page) {
- pr_err("allocate buffer failed:%d\n",
- logo_memsize);
- }
- }
- } else
- pr_info("------ NO CMA\n");
-#endif
- }
-
- ret = am_meson_plane_create(private);
- if (ret)
- return ret;
-
- ret = am_meson_crtc_create(amcrtc);
- if (ret)
- return ret;
-
- am_meson_register_crtc_funcs(private->crtc, &meson_private_crtc_funcs);
-
- /*vsync irq.*/
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_err(dev, "cannot find irq for vpu\n");
- return irq;
- }
- amcrtc->vblank_irq = (unsigned int)irq;
-
- spin_lock_init(&amcrtc->vblank_irq_lock);
- amcrtc->vblank_enable = false;
-
- ret = devm_request_irq(dev, amcrtc->vblank_irq, am_meson_vpu_irq,
- IRQF_SHARED, dev_name(dev), drm_dev);
- if (ret)
- return ret;
-
- disable_irq(amcrtc->vblank_irq);
-
- INIT_DELAYED_WORK(&osd_dwork, mem_free_work);
- schedule_delayed_work(&osd_dwork, msecs_to_jiffies(60 * 1000));
-
- return 0;
-}
-
-static void am_meson_vpu_unbind(struct device *dev,
- struct device *master, void *data)
-{
- struct drm_device *drm_dev = data;
- struct meson_drm *private = drm_dev->dev_private;
-
- am_meson_unregister_crtc_funcs(private->crtc);
- amvecm_drm_gamma_disable(0);
- am_meson_ctm_disable();
- osd_drm_debugfs_exit();
-}
-
-static const struct component_ops am_meson_vpu_component_ops = {
- .bind = am_meson_vpu_bind,
- .unbind = am_meson_vpu_unbind,
-};
-
-static const struct of_device_id am_meson_vpu_driver_dt_match[] = {
- { .compatible = "amlogic,meson-gxbb-vpu",
- .data = &osd_gxbb, },
- { .compatible = "amlogic,meson-gxl-vpu",
- .data = &osd_gxl, },
- { .compatible = "amlogic,meson-gxm-vpu",
- .data = &osd_gxm, },
- { .compatible = "amlogic,meson-txl-vpu",
- .data = &osd_txl, },
- { .compatible = "amlogic,meson-txlx-vpu",
- .data = &osd_txlx, },
- { .compatible = "amlogic,meson-axg-vpu",
- .data = &osd_axg, },
- { .compatible = "amlogic,meson-g12a-vpu",
- .data = &osd_g12a, },
- { .compatible = "amlogic,meson-g12b-vpu",
- .data = &osd_g12b, },
- {},
-};
-MODULE_DEVICE_TABLE(of, am_meson_vpu_driver_dt_match);
-
-static int am_meson_vpu_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- const void *vpu_data;
- int ret;
-
- if (!dev->of_node) {
- dev_err(dev, "can't find vpu devices\n");
- return -ENODEV;
- }
-
- vpu_data = of_device_get_match_data(dev);
- if (vpu_data) {
- ret = am_meson_crtc_dts_info_set(vpu_data);
- if (ret < 0)
- return -ENODEV;
- } else {
- dev_err(dev, "%s NOT match\n", __func__);
- return -ENODEV;
- }
-
- return component_add(dev, &am_meson_vpu_component_ops);
-}
-
-static int am_meson_vpu_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &am_meson_vpu_component_ops);
-
- return 0;
-}
-
-static struct platform_driver am_meson_vpu_platform_driver = {
- .probe = am_meson_vpu_probe,
- .remove = am_meson_vpu_remove,
- .driver = {
- .name = "meson-vpu",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(am_meson_vpu_driver_dt_match),
- },
-};
-
-module_platform_driver(am_meson_vpu_platform_driver);
-
-MODULE_AUTHOR("MultiMedia Amlogic <multimedia-sh@amlogic.com>");
-MODULE_DESCRIPTION("Amlogic Meson Drm VPU driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * drivers/amlogic/drm/am_meson_vpu.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-#ifndef __AM_MESON_VPU_H
-#define __AM_MESON_VPU_H
-
-struct am_meson_vpu_data {
- uint32_t version;
-};
-
-#endif /* __AM_MESON_VPU_H */
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
dv_policy = get_dolby_vision_policy();
#else
- dv_policy = DRM_MODE_DV_FOLLOW_SINK
+ dv_policy = DRM_MODE_DV_FOLLOW_SINK;
#endif
amcrtc = to_am_meson_crtc(crtc);
.write = meson_osd_blend_bypass_write,
};
+u32 overwrite_reg[256];
+u32 overwrite_val[256];
+int overwrite_enable;
+int reg_num;
+
+static int meson_reg_debug_show(struct seq_file *sf, void *data)
+{
+ int i;
+
+ seq_puts(sf, "echo rv reg > reg_debug to read the register\n");
+ seq_puts(sf, "echo wv reg val > reg_debug to overwrite the register\n");
+ seq_puts(sf, "echo ow 1 > reg_debug to enable overwrite register\n");
+ seq_printf(sf, "\noverwrited status: %s\n",
+ overwrite_enable ? "on" : "off");
+ if (overwrite_enable) {
+ for (i = 0; i < reg_num; i++)
+ seq_printf(sf, "reg[0x%04x]=0x%08x\n", overwrite_reg[i],
+ overwrite_val[i]);
+ }
+ //seq_printf(sf, "blank_enable: %d\n", amc->blank_enable);
+ return 0;
+}
+
+static int meson_reg_debug_open(struct inode *inode, struct file *file)
+{
+ struct drm_crtc *crtc = inode->i_private;
+
+ return single_open(file, meson_reg_debug_show, crtc);
+}
+
+static void parse_param(char *buf_orig, char **parm)
+{
+ char *ps, *token;
+ unsigned int n = 0;
+ char delim1[3] = " ";
+ char delim2[2] = "\n";
+
+ ps = buf_orig;
+ strcat(delim1, delim2);
+ while (1) {
+ token = strsep(&ps, delim1);
+ if (!token)
+ break;
+ if (*token == '\0')
+ continue;
+ parm[n++] = token;
+ }
+}
+
+static ssize_t meson_reg_debug_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ char buf[64];
+ long val;
+ int i;
+ unsigned int reg_addr, reg_val;
+ char *bufp, *parm[8] = {NULL};
+
+ if (len > sizeof(buf) - 1)
+ return -EINVAL;
+
+ if (copy_from_user(buf, ubuf, len))
+ return -EFAULT;
+
+ buf[len] = '\0';
+
+ bufp = buf;
+ parse_param(bufp, (char **)&parm);
+ if (!strcmp(parm[0], "rv")) {
+ if (kstrtoul(parm[1], 16, &val) < 0)
+ return -EINVAL;
+
+ reg_addr = val;
+ DRM_INFO("reg[0x%04x]=0x%08x\n", reg_addr,
+ meson_drm_read_reg(reg_addr));
+ } else if (!strcmp(parm[0], "wv")) {
+ if (kstrtoul(parm[1], 16, &val) < 0)
+ return -EINVAL;
+ reg_addr = val;
+
+ if (kstrtoul(parm[2], 16, &val) < 0)
+ return -EINVAL;
+
+ reg_val = val;
+ for (i = 0; i < reg_num; i++) {
+ if (overwrite_reg[i] == reg_addr) {
+ overwrite_val[i] = reg_val;
+ return len;
+ }
+ }
+
+ if (i == reg_num) {
+ overwrite_reg[i] = reg_addr;
+ overwrite_val[i] = reg_val;
+ reg_num++;
+ }
+ } else if (!strcmp(parm[0], "ow")) {
+ if (parm[1] && !strcmp(parm[1], "1"))
+ overwrite_enable = 1;
+ }
+
+ return len;
+}
+
+static const struct file_operations meson_reg_debug_fops = {
+ .owner = THIS_MODULE,
+ .open = meson_reg_debug_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = meson_reg_debug_write,
+};
+
int meson_crtc_debugfs_init(struct drm_crtc *crtc, struct dentry *root)
{
struct dentry *meson_vpu_root;
debugfs_remove_recursive(meson_vpu_root);
}
+ entry = debugfs_create_file("debug", 0644, meson_vpu_root, crtc,
+ &meson_reg_debug_fops);
+ if (!entry) {
+ DRM_ERROR("create reg_debug node error\n");
+ debugfs_remove_recursive(meson_vpu_root);
+ }
+
return 0;
}
struct drm_framebuffer *fb;
struct drm_display_mode *mode;
struct drm_connector **connector_set;
+ struct drm_connector *connector;
struct meson_drm *private = dev->dev_private;
if (!logo.alloc_flag) {
GFP_KERNEL);
if (!connector_set)
return;
-#ifdef CONFIG_DRM_MESON_HDMI
- connector_set[0] = am_meson_hdmi_connector();
-#endif
- if (!connector_set[0]) {
- DRM_INFO("%s:connector is NULL!\n", __func__);
- kfree(connector_set);
- return;
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
+ break;
+ else if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)
+ break;
}
+
+ connector_set[0] = connector;
mode = am_meson_drm_display_mode_init(connector_set[0]);
if (!mode) {
DRM_INFO("%s:display mode is NULL!\n", __func__);
struct am_meson_crtc *crtcs[MESON_MAX_CRTC];
u32 num_planes;
- struct am_osd_plane *planes[MESON_MAX_OSD];
+ struct am_osd_plane *osd_planes[MESON_MAX_OSD];
struct am_video_plane *video_planes[MESON_MAX_VIDEO];
struct meson_drm_fbdev_config ui_config;
};
struct am_meson_gem_object *meson_gem,
size_t *len)
{
- *len = meson_gem->base.size;
+ if (len)
+ *len = meson_gem->base.size;
return meson_gem->addr;
}
EXPORT_SYMBOL(am_meson_gem_object_get_phyaddr);
lcd->mode->hdisplay, lcd->mode->vdisplay);
mode = drm_mode_duplicate(connector->dev, lcd->mode);
+ if (!mode) {
+ pr_warn("am_drm_lcd: %s, null mode after duplication!\n",
+ __func__);
+ goto out;
+ }
pr_info("am_drm_lcd: %s: drm mode [%s] display size: %d x %d\n",
__func__, mode->name, mode->hdisplay, mode->vdisplay);
pr_info("am_drm_lcd: %s: lcd config size: %d x %d\n",
drm_mode_probed_add(connector, mode);
count = 1;
+
+out:
pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
pr_info("***************************************************\n");
#else
struct drm_gem_cma_object *gem;
#endif
- u32 fb_size = 0;
+ size_t fb_size = 0;
phys_addr_t phyaddr;
#ifdef CONFIG_DRM_MESON_USE_ION
} else if (meson_fb->bufp[0]) {
phyaddr = am_meson_gem_object_get_phyaddr(drv,
meson_fb->bufp[0],
- (size_t *)&fb_size);
+ &fb_size);
} else {
phyaddr = 0;
DRM_INFO("don't find phyaddr!\n");
phyaddr = gem->paddr;
#endif
plane_info->phy_addr = phyaddr;
- plane_info->fb_size = fb_size;
+ plane_info->fb_size = (u32)fb_size;
return 0;
}
#else
struct drm_gem_cma_object *gem;
#endif
- u32 fb_size[2] = {0};
+ size_t fb_size[2] = {0};
phys_addr_t phyaddr, phyaddr1 = 0;
#ifdef CONFIG_DRM_MESON_USE_ION
phyaddr =
am_meson_gem_object_get_phyaddr(drv,
meson_fb->bufp[0],
- (size_t *)&fb_size[0]);
+ &fb_size[0]);
} else {
phyaddr = 0;
DRM_INFO("don't find phyaddr!\n");
phyaddr1 =
am_meson_gem_object_get_phyaddr(drv,
meson_fb->bufp[1],
- (size_t *)&fb_size[1]);
+ &fb_size[1]);
/* start to get vframe from uvm */
if (meson_fb->bufp[0]->is_uvm) {
ubo = &meson_fb->bufp[0]->ubo;
phyaddr = gem->paddr;
#endif
plane_info->phy_addr[0] = phyaddr;
- plane_info->fb_size[0] = fb_size[0];
+ plane_info->fb_size[0] = (u32)fb_size[0];
plane_info->phy_addr[1] = phyaddr1;
- plane_info->fb_size[1] = fb_size[1];
+ plane_info->fb_size[1] = (u32)fb_size[1];
return 0;
}
if (WARN_ON(!plane->state))
return NULL;
+ DRM_DEBUG("meson_plane_duplicate_state (%s)\n", plane->name);
+
old_plane_state = to_am_meson_plane_state(plane->state);
meson_plane_state = kmemdup(old_plane_state,
sizeof(*meson_plane_state), GFP_KERNEL);
DRM_INFO("%s state/meson_drm is NULL!\n", __func__);
return -EINVAL;
}
+
+ DRM_DEBUG("meson_plane_atomic_check [%d]\n", osd_plane->plane_index);
+
mvps = meson_vpu_pipeline_get_state(drv->pipeline, state->state);
if (!mvps || osd_plane->plane_index >= MESON_MAX_OSDS) {
DRM_INFO("%s mvps/osd_plane is NULL!\n", __func__);
if (ret < 0 || plane_info->src_w > MESON_OSD_INPUT_W_LIMIT ||
plane_info->src_w == 0) {
plane_info->enable = 0;
+ DRM_DEBUG("fb is invalid, disable plane[%d].\n",
+ plane_info->src_w);
return ret;
}
plane_state = to_am_meson_plane_state(state);
plane_info->premult_en = plane_state->premult_en;
plane_info->enable = 1;
- DRM_DEBUG("index=%d, zorder=%d\n",
- plane_info->plane_index, plane_info->zorder);
+ DRM_DEBUG("OSD PLANE index=%d, zorder=%d, phy = %llx\n",
+ plane_info->plane_index, plane_info->zorder,
+ plane_info->phy_addr);
DRM_DEBUG("src_x/y/w/h=%d/%d/%d/%d\n",
plane_info->src_x, plane_info->src_y,
plane_info->src_w, plane_info->src_h);
DRM_INFO("%s state/meson_drm is NULL!\n", __func__);
return -EINVAL;
}
+
+ DRM_DEBUG("planeidx [%d]\n", video_plane->plane_index);
+
mvps = meson_vpu_pipeline_get_state(drv->pipeline, state->state);
if (!mvps || video_plane->plane_index >= MESON_MAX_VIDEO) {
DRM_INFO("%s mvps/video_plane is NULL!\n", __func__);
}
plane_info = &mvps->video_plane_info[video_plane->plane_index];
plane_info->plane_index = video_plane->plane_index;
- plane_info->zorder = state->zpos;
+ plane_info->zorder = state->zpos + plane_info->plane_index;
mvps->plane_index[video_plane->plane_index] = video_plane->plane_index;
meson_video_plane_position_calc(plane_info, state,
plane_state = to_am_meson_plane_state(state);
plane_info->enable = 1;
- DRM_DEBUG("index=%d, zorder=%d\n",
+ DRM_DEBUG("VIDOE PLANE index=%d, zorder=%d\n",
plane_info->plane_index, plane_info->zorder);
DRM_DEBUG("src_x/y/w/h=%d/%d/%d/%d\n",
plane_info->src_x, plane_info->src_y,
return 0;
}
-static struct am_osd_plane *am_plane_create(struct meson_drm *priv, int i)
+static struct am_osd_plane *am_osd_plane_create(struct meson_drm *priv, int i)
{
struct am_osd_plane *osd_plane;
struct drm_plane *plane;
- struct meson_vpu_pipeline *pipeline = priv->pipeline;
u32 type = 0, zpos, min_zpos, max_zpos;
char plane_name[8];
const u64 *format_modifiers = afbc_modifier;
else
type = DRM_PLANE_TYPE_OVERLAY;
+ min_zpos = OSD_PLANE_BEGIN_ZORDER;
+ max_zpos = OSD_PLANE_END_ZORDER;
+
osd_plane->drv = priv;
osd_plane->plane_index = i;
+ osd_plane->plane_type = OSD_PLANE;
if (logo.osd_reverse)
osd_plane->osd_reverse = DRM_REFLECT_MASK;
else
osd_plane->osd_reverse = DRM_ROTATE_0;
- zpos = osd_plane->plane_index + pipeline->num_video;
- min_zpos = MESON_PLANE_BEGIN_ZORDER;
- max_zpos = MESON_PLANE_END_ZORDER;
+ zpos = osd_plane->plane_index + min_zpos;
plane = &osd_plane->base;
sprintf(plane_name, "osd%d", i);
DRM_REFLECT_MASK);
drm_plane_create_zpos_property(plane, zpos, min_zpos, max_zpos);
drm_plane_helper_add(plane, &am_osd_helper_funcs);
+ DRM_INFO("osd plane %d create done\n", i);
return osd_plane;
}
DRM_INFO("no memory to alloc video plane\n");
return 0;
}
+ min_zpos = 0;
+ max_zpos = 255;
video_plane->drv = priv;
video_plane->plane_index = i;
- zpos = video_plane->plane_index;
- min_zpos = MESON_PLANE_BEGIN_ZORDER;
- max_zpos = MESON_PLANE_END_ZORDER;
+ video_plane->plane_type = VIDEO_PLANE;
+ zpos = video_plane->plane_index + min_zpos;
plane = &video_plane->base;
sprintf(plane_name, "video%d", i);
struct meson_vpu_pipeline *pipeline = priv->pipeline;
int i, osd_index, video_index;
- /*video plane*/
- for (i = pipeline->num_video - 1; i >= 0; i--) {
- video_index = pipeline->video[i]->base.index;
- video_plane = am_video_plane_create(priv, video_index);
-
- if (!video_plane)
- return -ENOMEM;
+ memset(priv->osd_planes, 0,
+ sizeof(struct am_osd_plane *) * MESON_MAX_OSD);
+ memset(priv->video_planes, 0,
+ sizeof(struct am_video_plane *) * MESON_MAX_VIDEO);
- priv->video_planes[i] = video_plane;
- priv->num_planes++;
- }
- DRM_DEBUG("create %d video plane done\n", pipeline->num_video);
/*osd plane*/
for (i = 0; i < pipeline->num_osds; i++) {
osd_index = pipeline->osds[i]->base.index;
- plane = am_plane_create(priv, osd_index);
+ plane = am_osd_plane_create(priv, osd_index);
if (!plane)
return -ENOMEM;
if (i == 0)
priv->primary_plane = &plane->base;
- priv->planes[priv->num_planes++] = plane;
+ priv->osd_planes[i] = plane;
+ priv->num_planes++;
+ }
+ DRM_INFO("create %d osd plane done\n", pipeline->num_osds);
+
+ /*video plane: init after osd to provide osd id at first.*/
+ for (i = 0; i < pipeline->num_video; i++) {
+ video_index = pipeline->video[i]->base.index;
+ video_plane = am_video_plane_create(priv, video_index);
+
+ if (!video_plane)
+ return -ENOMEM;
+
+ priv->video_planes[i] = video_plane;
+ priv->num_planes++;
}
- DRM_DEBUG("create %d osd plane done\n", pipeline->num_osds);
+ DRM_INFO("create %d video plane done\n", pipeline->num_video);
return 0;
}
#include <linux/amlogic/meson_uvm_core.h>
#include "meson_fb.h"
-#define MESON_PLANE_BEGIN_ZORDER 1
-#define MESON_PLANE_END_ZORDER 65
+/*legacy video driver issue caused zorder problem.*/
+#define OSD_PLANE_BEGIN_ZORDER 65
+#define OSD_PLANE_END_ZORDER 128
struct am_meson_plane_state {
struct drm_plane_state base;
u32 premult_en;
};
+enum meson_plane_type {
+ OSD_PLANE = 0,
+ VIDEO_PLANE,
+};
+
struct am_osd_plane {
+ /*base struct, same as am_video_plane*/
struct drm_plane base; //must be first element.
struct meson_drm *drv; //point to struct parent.
struct dentry *plane_debugfs_dir;
int plane_index;
+ int plane_type;
+
+ /*osd extend*/
u32 osd_reverse;
u32 osd_blend_bypass;
struct drm_property *prop_premult_en;
};
struct am_video_plane {
+ /*base struct, same as am_video_plane*/
struct drm_plane base; //must be first element.
struct meson_drm *drv; //point to struct parent.
struct dentry *plane_debugfs_dir;
int plane_index;
+ int plane_type;
+
+ /*video exted*/
};
#define to_am_osd_plane(x) container_of(x, \
ret = of_property_read_u8(dev->of_node,
"osd_ver", &pipeline->osd_version);
+ meson_drm_osd_canvas_alloc();
vpu_pipeline_init(pipeline);
/*vsync irq.*/
amvecm_drm_gamma_disable(0);
am_meson_ctm_disable();
#endif
+ meson_drm_osd_canvas_free();
}
static const struct component_ops am_meson_vpu_component_ops = {
link = of_find_node_by_phandle(be32_to_cpup(phandle));
of_property_read_u8(link, "id", &id);
para->inputs[j].id = id;
- in_mask |= 1 << id;
+ in_mask |= ((u64)1) << id;
}
para->inputs_mask = in_mask;
}
link = of_find_node_by_phandle(be32_to_cpup(phandle));
of_property_read_u8(link, "id", &id);
para->outputs[j].id = id;
- out_mask |= 1 << id;
+ out_mask |= ((u64)1) << id;
}
para->outputs_mask = out_mask;
}
mvps->plane_info[i].enable = 0;
continue;
}
+ DRM_DEBUG("osdplane [%d] enable:(%d-%llx, %d-%d)\n",
+ mvps->plane_info[i].plane_index,
+ mvps->plane_info[i].zorder,
+ mvps->plane_info[i].phy_addr,
+ mvps->plane_info[i].dst_w,
+ mvps->plane_info[i].dst_h);
mvps->num_plane++;
+ } else {
+ DRM_DEBUG("osdplane indx [%d] disable.\n", i);
}
}
for (i = 0; i < pipeline->num_video; i++) {
int vpu_pipeline_update(struct meson_vpu_pipeline *pipeline,
struct drm_atomic_state *old_state)
{
+#ifdef CONFIG_DEBUG_FS
+ int i;
+#endif
unsigned long id;
struct meson_vpu_block *mvb;
struct meson_vpu_block_state *mvbs;
}
}
+#ifdef CONFIG_DEBUG_FS
+ if (overwrite_enable) {
+ for (i = 0; i < reg_num; i++)
+ meson_vpu_write_reg(overwrite_reg[i], overwrite_val[i]);
+ }
+#endif
+
return 0;
}
extern struct meson_vpu_block_ops dolby_ops;
extern struct meson_vpu_block_ops postblend_ops;
+extern u32 overwrite_reg[256];
+extern u32 overwrite_val[256];
+extern int overwrite_enable;
+extern int reg_num;
+
#endif
int vpu_video_pipeline_check_block(struct meson_vpu_pipeline_state *mvps,
struct drm_atomic_state *state)
{
- int i, ret;
+ int i, ret = 0;
struct meson_vpu_block *block;
struct meson_vpu_block_state *mvbs;
}
};
-static unsigned int osd_canvas[3][2] = {
- {0x41, 0x42}, {0x43, 0x44}, {0x45, 0x46} };
+static unsigned int osd_canvas[3][2];
static u32 osd_canvas_index[3] = {0, 0, 0};
/*
vunmap(addr);
}
+void meson_drm_osd_canvas_alloc(void)
+{
+ if (canvas_pool_alloc_canvas_table("osd_drm",
+ &osd_canvas[0][0],
+ sizeof(osd_canvas) /
+ sizeof(osd_canvas[0][0]),
+ CANVAS_MAP_TYPE_1)) {
+ DRM_INFO("allocate drm osd canvas error.\n");
+ }
+}
+
+void meson_drm_osd_canvas_free(void)
+{
+ canvas_pool_free_canvas_table(&osd_canvas[0][0],
+ sizeof(osd_canvas) /
+ sizeof(osd_canvas[0][0]));
+}
+
static int osd_check_state(struct meson_vpu_block *vblk,
struct meson_vpu_block_state *state,
struct meson_vpu_pipeline_state *mvps)
DRM_INFO("mvos is NULL!\n");
return -1;
}
- DRM_DEBUG("%s check_state called.\n", osd->base.name);
+ DRM_DEBUG("%s - %d check_state called.\n", osd->base.name, vblk->index);
plane_info = &mvps->plane_info[vblk->index];
mvos->src_x = plane_info->src_x;
mvos->src_y = plane_info->src_y;
mvos->rotation = plane_info->rotation;
mvos->afbc_en = plane_info->afbc_en;
mvos->blend_bypass = plane_info->blend_bypass;
+ mvos->plane_index = plane_info->plane_index;
return 0;
}
char name_buf[64];
struct drm_crtc *crtc;
struct am_meson_crtc *amc;
- struct meson_vpu_osd *osd = to_osd_block(vblk);
- struct meson_vpu_osd_state *mvos = to_osd_state(state);
+ struct meson_vpu_osd *osd;
+ struct meson_vpu_osd_state *mvos;
u32 pixel_format, canvas_index, src_h, byte_stride;
struct osd_scope_s scope_src = {0, 1919, 0, 1079};
- struct osd_mif_reg_s *reg = osd->reg;
+ struct osd_mif_reg_s *reg;
bool alpha_div_en, reverse_x, reverse_y, afbc_en;
bool bflg = false;
void *buff = NULL;
u64 phy_addr;
u32 hold_line;
- crtc = vblk->pipeline->crtc;
- amc = to_am_meson_crtc(crtc);
-
- if (!vblk) {
+ if (!vblk || !state) {
DRM_DEBUG("set_state break for NULL.\n");
return;
}
+
+ osd = to_osd_block(vblk);
+ mvos = to_osd_state(state);
+
+ reg = osd->reg;
+ if (!reg) {
+ DRM_DEBUG("set_state break for NULL OSD mixer reg.\n");
+ return;
+ }
+
+ crtc = vblk->pipeline->crtc;
+ if (!crtc) {
+ DRM_DEBUG("set_state break for NULL crtc.\n");
+ return;
+ }
+
+ amc = to_am_meson_crtc(crtc);
+
+ DRM_DEBUG("%s - %d osd_set_state called.\n", osd->base.name, vblk->index);
+
alpha_div_en = (mvos->premult_en && !mvos->blend_bypass) ? 1 : 0;
afbc_en = mvos->afbc_en ? 1 : 0;
src_h = mvos->src_h;
{
struct meson_vpu_osd *osd = to_osd_block(vblk);
struct osd_mif_reg_s *reg = osd->reg;
- u8 version = vblk->pipeline->osd_version;
+ u8 version;
if (!vblk) {
DRM_DEBUG("disable break for NULL.\n");
return;
}
+
+ version = vblk->pipeline->osd_version;
+
/*G12B should always enable,avoid afbc decoder error*/
if ((version != OSD_V2) && (version != OSD_V3))
osd_block_enable(reg, 0);
const struct meson_drm_format_info *meson_drm_format_info(u32 format,
bool afbc_en);
+void meson_drm_osd_canvas_alloc(void);
+void meson_drm_osd_canvas_free(void);
#endif
list_for_each_entry(ops, &demod->list, list) {
if ((ops->attached && attach) ||
(!ops->attached && !attach)) {
- pr_err("Demod: demod [%d] had %s.\n", ops->cfg.id,
+ pr_err("Demod: demod%d [id %d] had %s.\n",
+ ops->index, ops->cfg.id,
attach ? "attached" : "detached");
continue;
ops->attached = true;
ops->fe = fe;
- dvb_tuner_attach(ops->fe);
+ if (!ops->external)
+ dvb_tuner_attach(ops->fe);
- pr_err("Demod: attach demod [%d] done.\n",
- ops->cfg.id);
+ pr_err("Demod: attach demod%d [id %d] done.\n",
+ ops->index, ops->cfg.id);
} else {
ops->attached = false;
- pr_err("Demod: attach demod [%d] fail.\n",
- ops->cfg.id);
+ pr_err("Demod: attach demod%d [id %d] fail.\n",
+ ops->index, ops->cfg.id);
}
} else {
if (demod->used == ops)
ops->type = AML_FE_UNDEFINED;
ops->fe = NULL;
- pr_err("Demod: detach demod [%d] done.\n",
- ops->cfg.id);
+ pr_err("Demod: detach demod%d [id %d] done.\n",
+ ops->index, ops->cfg.id);
}
}
if (!ops->attached || !ops->cfg.detect || ops->valid)
continue;
- if (ops->fe->ops.init)
+ if (ops->fe->ops.init) {
ret = ops->fe->ops.init(ops->fe);
+ } else {
+ pr_err("Demod: demod%d [id %d] init() is NULL.\n",
+ ops->index, ops->cfg.id);
+
+ continue;
+ }
if (!ret) {
ret = ops->module->detect(&ops->cfg);
else
ops->valid = false;
- pr_err("Demod: detect demod [%d] %s.\n", ops->cfg.id,
+ pr_err("Demod: detect demod%d [id %d] %s.\n",
+ ops->index, ops->cfg.id,
ops->valid ? "done" : "fail");
if (ops->fe->ops.release)
ops->fe->ops.release(ops->fe);
+ } else {
+ pr_err("Demod: demod%d [id %d] init() error, ret %d.\n",
+ ops->index, ops->cfg.id, ret);
}
}
list_for_each_entry(ops, &demod->list, list) {
if (!ops->attached) {
- pr_err("Demod: demod [%d] had not attached.\n",
- ops->cfg.id);
+ pr_err("Demod: demod%d [id %d] had not attached.\n",
+ ops->index, ops->cfg.id);
continue;
}
if (!ops->valid && ops->cfg.detect) {
- pr_err("Demod: demod [%d] had not detected.\n",
- ops->cfg.id);
+ pr_err("Demod: demod%d [id %d] had not detected.\n",
+ ops->index, ops->cfg.id);
continue;
}
if ((ops->registered && regist) ||
(!ops->registered && !regist)) {
- pr_err("Demod: demod [%d] had %sregistered.\n",
- ops->cfg.id, regist ? "" : "un");
+ pr_err("Demod: demod%d [id %d] had %sregistered.\n",
+ ops->index, ops->cfg.id,
+ regist ? "" : "un");
continue;
}
ret = ops->module->register_frontend(
demod->dvb_adapter, ops->fe);
if (ret)
- pr_err("Demod: demod [%d] register frontend fail, ret %d.\n",
- ops->cfg.id, ret);
+ pr_err("Demod: demod%d [id %d] register frontend fail, ret %d.\n",
+ ops->index, ops->cfg.id, ret);
else
ops->registered = true;
} else {
ret = ops->module->unregister_frontend(ops->fe);
if (ret)
- pr_err("Demod: demod [%d] unregister frontend fail, ret %d.\n",
- ops->cfg.id, ret);
+ pr_err("Demod: demod%d [Id %d] unregister frontend fail, ret %d.\n",
+ ops->index, ops->cfg.id, ret);
else
ops->registered = false;
}
return 0;
}
+static int demod_pre_init(struct dvb_demod *demod)
+{
+ struct demod_ops *ops = NULL;
+
+ if (IS_ERR_OR_NULL(demod))
+ return -EFAULT;
+
+ mutex_lock(&demod->mutex);
+
+ list_for_each_entry(ops, &demod->list, list) {
+ if (!ops->attached || ops->pre_inited)
+ continue;
+
+ /* In some cases, pre-init is required. */
+ ops->pre_inited = true;
+ }
+
+ mutex_unlock(&demod->mutex);
+
+ return 0;
+}
+
static DEFINE_MUTEX(dvb_demods_mutex);
static struct dvb_demod demods = {
.attach = demod_attach,
.match = demod_match,
.detect = demod_detect,
- .register_frontend = demod_register_frontend
+ .register_frontend = demod_register_frontend,
+ .pre_init = demod_pre_init
};
int dvb_extern_register_frontend(struct dvb_adapter *adapter)
demod->register_frontend(demod, true);
+ demod->pre_init(demod);
+
demod->refcount++;
mutex_unlock(&dvb_demods_mutex);
ops->attached = false;
ops->registered = false;
ops->index = -1;
+ ops->pre_inited = false;
ops->delivery_system = SYS_UNDEFINED;
ops->type = AML_FE_UNDEFINED;
ops->module = NULL;
if (p == ops) {
mutex_unlock(&dvb_demods_mutex);
- pr_err("Demod: demod ops [0x%p] exist.\n", ops);
+ pr_err("Demod: demod%d [id %d] ops [0x%p] exist.\n",
+ ops->index, ops->cfg.id, ops);
return -EEXIST;
}
return -ENODEV;
}
+ ops->cfg.name = ops->module->name;
+ ops->external = (ops->cfg.id != AM_DTV_DEMOD_AMLDTV);
+
list_add_tail(&ops->list, &demod->list);
mutex_unlock(&dvb_demods_mutex);
ops->attached = false;
ops->registered = false;
ops->valid = false;
+ ops->pre_inited = false;
+ ops->external = false;
ops->index = -1;
ops->delivery_system = SYS_UNDEFINED;
ops->type = AML_FE_UNDEFINED;
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
#include <linux/amlogic/aml_tuner.h>
#include <linux/amlogic/aml_dtvdemod.h>
#include <linux/amlogic/aml_dvb_extern.h>
#define AML_DVB_EXTERN_MODULE_NAME "aml_dvb_extern"
#define AML_DVB_EXTERN_CLASS_NAME "aml_dvb_extern"
-#define AML_DVB_EXTERN_VERSION "V1.03"
+#define AML_DVB_EXTERN_VERSION "V1.06"
static struct dvb_extern_device *dvb_extern_dev;
"SYS_ANALOG"
};
+static void aml_dvb_extern_set_power(struct gpio_config *pin_cfg, int on)
+{
+ if (!aml_gpio_is_valid(pin_cfg->pin)) {
+ pr_err("%s: dvb power gpio is invalid.", __func__);
+
+ return;
+ }
+
+ /* OD pin[No output capacity], set direction output as low output. */
+ if (pin_cfg->dir == GPIOF_DIR_OUT) {
+ if (on)
+ aml_gpio_set_value(pin_cfg->pin, pin_cfg->value);
+ else
+ aml_gpio_set_value(pin_cfg->pin, !(pin_cfg->value));
+ } else {
+ if (on) {
+ aml_gpio_direction_input(pin_cfg->pin);
+ aml_gpio_set_value(pin_cfg->pin, pin_cfg->value);
+ } else {
+ aml_gpio_direction_output(pin_cfg->pin, !(pin_cfg->value));
+ }
+ }
+}
+
static ssize_t tuner_debug_store(struct class *class,
struct class_attribute *attr, const char *buf, size_t count)
{
unsigned int ret = 0;
char *buf_orig = NULL, *ps = NULL, *token = NULL, *name = NULL;
char *parm[10] = { NULL };
- unsigned long val = 0, symbol_rate = 0, rolloff = 0;
+ unsigned long val = 0, bw = 0, symbol_rate = 0, rolloff = 0;
struct tuner_ops *ops = NULL;
struct dvb_tuner *tuner = get_dvb_tuners();
struct dvb_extern_device *dev =
container_of(class, struct dvb_extern_device, class);
- struct dvb_frontend *fe = &dev->fe;
+ struct dvb_frontend *fe = dev->tuner_fe;
struct analog_parameters *p = &dev->para;
+ u32 status = FE_TIMEDOUT, frequency = 0, bandwidth = 0;
+ u32 if_frequency[2] = { 0 };
+ s16 strength = 0;
buf_orig = kstrdup(buf, GFP_KERNEL);
ps = buf_orig;
if (!parm[0])
goto EXIT;
+ if (!fe && strncmp(parm[0], "attach", 6) && strncmp(parm[0], "status", 6)) {
+ pr_err("please attach first:\n");
+ pr_err("echo attach [tuner_id] > /sys/class/aml_dvb_extern/tuner_debug\n");
+ goto EXIT;
+ }
+
if (!strncmp(parm[0], "init", 4)) {
if (parm[1] && kstrtoul(parm[1], 0, &val) == 0)
fe->ops.info.type = val;
pr_err("init tuner mode [%d][%s].\n",
fe->ops.info.type,
fe_type_name[fe->ops.info.type]);
+
+ if (fe->ops.tuner_ops.init)
+ ret = fe->ops.tuner_ops.init(fe);
+
if (fe->ops.tuner_ops.set_config)
ret = fe->ops.tuner_ops.set_config(fe, NULL);
} else if (!strncmp(parm[0], "tune", 4)) {
pr_err("tune mode DVB-S, need to set Roll off factor.\n");
}
+ if (parm[2] && kstrtoul(parm[2], 0, &bw) == 0) {
+ c->bandwidth_hz = bw;
+ } else {
+ bw = 8000000;
+ c->bandwidth_hz = bw;
+ }
+
if (fe->ops.tuner_ops.set_params)
ret = fe->ops.tuner_ops.set_params(fe);
}
fe_type_name[fe->ops.info.type],
val, symbol_rate, rolloff);
} else {
- pr_err("tune mode [%d][%s] freq[%ld].\n",
+ pr_err("tune mode [%d][%s] freq[%ld], bw[%ld].\n",
fe->ops.info.type,
- fe_type_name[fe->ops.info.type], val);
+ fe_type_name[fe->ops.info.type], val, bw);
}
} else {
pr_err("please input frequency.\n");
else
pr_err("invaild audio std.\n");
} else if (!strncmp(parm[0], "status", 6)) {
- pr_err("tuner numbers %d.\n", dev->tuner_num);
+ pr_err("tuner numbers: %d.\n", dev->tuner_num);
pr_err("all tuners:\n");
list_for_each_entry(ops, &tuner->list, list) {
name = ops->fe.ops.tuner_ops.info.name;
- pr_err("tuner %d, id %d (%s) %s.\n",
+ pr_err("tuner%d, id %d (%s) addr 0x%x, adap 0x%p %s, %sdetected.\n",
ops->index, ops->cfg.id,
- name ? name : "", ops->attached ?
- "attached" : "detached");
+ name ? name : "",
+ ops->cfg.i2c_addr, ops->cfg.i2c_adap,
+ ops->attached ? "attached" : "detached",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ");
}
if (tuner->used) {
name = tuner->used->fe.ops.tuner_ops.info.name;
- pr_err("current use tuner %d, id %d (%s), fe type %d.\n",
+ pr_err("current use tuner%d, id %d (%s), fe type %d.\n",
tuner->used->index,
tuner->used->cfg.id,
name ? name : "",
tuner->used->type);
+
+ if (tuner->used->fe.ops.tuner_ops.get_status) {
+ tuner->used->fe.ops.tuner_ops.get_status(
+ &tuner->used->fe, &status);
+ pr_err("signal status: %s.\n",
+ status & FE_HAS_LOCK ? "Locked" : "Unlocked");
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_strength) {
+ tuner->used->fe.ops.tuner_ops.get_strength(
+ &tuner->used->fe, &strength);
+ pr_err("strength: %d dBm.\n", strength);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_frequency(
+ &tuner->used->fe, &frequency);
+ pr_err("frequency: %d Hz.\n", frequency);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_bandwidth) {
+ tuner->used->fe.ops.tuner_ops.get_bandwidth(
+ &tuner->used->fe, &bandwidth);
+ pr_err("bandwidth: %d Hz.\n", bandwidth);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_if_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_if_frequency(
+ &tuner->used->fe, if_frequency);
+ pr_err("if frequency: %d Hz (IF spectrum %s).\n",
+ if_frequency[1],
+ if_frequency[0] ? "inverted" : "normal");
+ }
}
} else if (!strncmp(parm[0], "uninit", 6)) {
if (fe->ops.tuner_ops.release)
val = 0;
if (val >= dev->tuner_num) {
- pr_err("tuner index %ld error, the max is %d, use default %d.\n",
+ pr_err("input tuner index %ld error, the max is %d, use default %d.\n",
val, dev->tuner_num - 1, dev->tuner_cur);
goto EXIT;
dev->tuner_cur = val;
ops = dvb_tuner_ops_get_byindex(dev->tuner_cur);
if (ops) {
- memcpy(&fe->ops.tuner_ops, &ops->fe.ops.tuner_ops,
- sizeof(struct dvb_tuner_ops));
- fe->tuner_priv = ops->fe.tuner_priv;
+ dev->tuner_fe = &ops->fe;
+ //memcpy(&fe->ops.tuner_ops, &ops->fe.ops.tuner_ops,
+ // sizeof(struct dvb_tuner_ops));
+ //fe->tuner_priv = ops->fe.tuner_priv;
pr_err("tuner %d attach done.\n", dev->tuner_cur);
}
} else if (!strncmp(parm[0], "detach", 6)) {
tuner->attach(tuner, false);
+ } else if (!strncmp(parm[0], "match", 5)) {
+ if (parm[1])
+ ret = kstrtoul(parm[1], 0, &val);
+ else
+ val = FE_ANALOG;
+
+ if (val > FE_ISDBT) {
+ pr_err("input tuner match fe type %ld error.\n", val);
+
+ goto EXIT;
+ }
+
+ if (tuner->match(tuner, val))
+ pr_err("tuner match fe type %ld (%s) done.\n",
+ val, fe_type_name[val]);
+ else
+ pr_err("tuner match fe type %ld (%s) fail.\n",
+ val, fe_type_name[val]);
+
+ } else if (!strncmp(parm[0], "detect", 6)) {
+ tuner->detect(tuner);
+
+ dev->tuner_fe = NULL;
} else {
pr_err("invalid command: %s.\n", parm[0]);
}
struct dvb_tuner *tuner = get_dvb_tuners();
struct dvb_extern_device *dev =
container_of(class, struct dvb_extern_device, class);
+ u32 status = FE_TIMEDOUT, frequency = 0, bandwidth = 0;
+ u32 if_frequency[2] = { 0 };
+ s16 strength = 0;
- n += sprintf(buff + n, "\nTuner Debug Usage:\n");
+ n += sprintf(buff + n, "\nTuner Debug Usage (%s):\n", AML_DVB_EXTERN_VERSION);
n += sprintf(buff + n, "[status]\necho status > %s\n", path);
- n += sprintf(buff + n, "[attach]\necho attach > %s\n", path);
+ n += sprintf(buff + n, "[attach]\necho attach [tuner_id] > %s\n", path);
n += sprintf(buff + n, "[detach]\necho detach > %s\n", path);
+ n += sprintf(buff + n, "[match]\necho match [fe_type] > %s\n", path);
+ n += sprintf(buff + n, "\tfe_type:\n");
+ n += sprintf(buff + n, "\tDVB-S/S2 [FE_QPSK] : 0\n");
+ n += sprintf(buff + n, "\tDVB-C [FE_QAM] : 1\n");
+ n += sprintf(buff + n, "\tDVB-T/T2 [FE_OFDM] : 2\n");
+ n += sprintf(buff + n, "\tATSC [FE_ATSC] : 3\n");
+ n += sprintf(buff + n, "\tANALOG [FE_ANALOG]: 4\n");
+ n += sprintf(buff + n, "\tDTMB [FE_DTMB] : 5\n");
+ n += sprintf(buff + n, "\tISDBT [FE_ISDBT] : 6\n");
+ n += sprintf(buff + n, "[detect]\necho detect > %s\n", path);
n += sprintf(buff + n, "[init]\n");
n += sprintf(buff + n, "echo init [fe_type] > %s\n", path);
n += sprintf(buff + n, "\tfe_type:\n");
- n += sprintf(buff + n, "\tDVB-S [FE_QPSK] : 0\n");
- n += sprintf(buff + n, "\tDVB-C [FE_QAM] : 1\n");
- n += sprintf(buff + n, "\tDVB-T [FE_OFDM] : 2\n");
- n += sprintf(buff + n, "\tATSC [FE_ATSC] : 3\n");
- n += sprintf(buff + n, "\tANALOG [FE_ANALOG]: 4\n");
- n += sprintf(buff + n, "\tDTMB [FE_DTMB] : 5\n");
- n += sprintf(buff + n, "\tISDBT [FE_ISDBT] : 6\n");
+ n += sprintf(buff + n, "\tDVB-S/S2 [FE_QPSK] : 0\n");
+ n += sprintf(buff + n, "\tDVB-C [FE_QAM] : 1\n");
+ n += sprintf(buff + n, "\tDVB-T/T2 [FE_OFDM] : 2\n");
+ n += sprintf(buff + n, "\tATSC [FE_ATSC] : 3\n");
+ n += sprintf(buff + n, "\tANALOG [FE_ANALOG]: 4\n");
+ n += sprintf(buff + n, "\tDTMB [FE_DTMB] : 5\n");
+ n += sprintf(buff + n, "\tISDBT [FE_ISDBT] : 6\n");
n += sprintf(buff + n, "[set atv std]\n");
n += sprintf(buff + n, "echo std [vstd] [astd] > %s\n", path);
n += sprintf(buff + n, "\tvstd: pal, ntsc, secam\n");
n += sprintf(buff + n, "\t3: roll-off = 0.40\n");
n += sprintf(buff + n, "[uninit]\necho uninit > %s\n", path);
- n += sprintf(buff + n, "\ntuner status:\n");
- n += sprintf(buff + n, "tuner numbers %d.\n", dev->tuner_num);
+ n += sprintf(buff + n, "\n------------------------------------------------------------\n");
+ n += sprintf(buff + n, "\nTuner Status:\n");
+ n += sprintf(buff + n, "tuner numbers: %d.\n", dev->tuner_num);
n += sprintf(buff + n, "all tuners:\n");
list_for_each_entry(ops, &tuner->list, list) {
name = ops->fe.ops.tuner_ops.info.name;
- n += sprintf(buff + n, "tuner %d, id %d (%s) %s.\n",
+ n += sprintf(buff + n, "tuner%d, id %d (%s) addr 0x%x, adap 0x%p %s, %sdetected.\n",
ops->index, ops->cfg.id,
- name ? name : "", ops->attached ?
- "attached" : "detached");
+ name ? name : "",
+ ops->cfg.i2c_addr, ops->cfg.i2c_adap,
+ ops->attached ? "attached" : "detached",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ");
}
if (tuner->used) {
name = tuner->used->fe.ops.tuner_ops.info.name;
- n += sprintf(buff + n, "current use tuner %d, id %d (%s), fe type %d.\n",
+ n += sprintf(buff + n, "current use tuner%d, id %d (%s), fe type %d.\n",
tuner->used->index,
tuner->used->cfg.id,
name ? name : "",
tuner->used->type);
+
+ if (tuner->used->fe.ops.tuner_ops.get_status) {
+ tuner->used->fe.ops.tuner_ops.get_status(
+ &tuner->used->fe, &status);
+ n += sprintf(buff + n, "signal status: %s.\n",
+ status & FE_HAS_LOCK ? "Locked" : "Unlocked");
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_strength) {
+ tuner->used->fe.ops.tuner_ops.get_strength(
+ &tuner->used->fe, &strength);
+ n += sprintf(buff + n, "strength: %d dBm.\n", strength);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_frequency(
+ &tuner->used->fe, &frequency);
+ n += sprintf(buff + n, "frequency: %d Hz.\n", frequency);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_bandwidth) {
+ tuner->used->fe.ops.tuner_ops.get_bandwidth(
+ &tuner->used->fe, &bandwidth);
+ n += sprintf(buff + n, "bandwidth: %d Hz.\n", bandwidth);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_if_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_if_frequency(
+ &tuner->used->fe, if_frequency);
+ n += sprintf(buff + n, "if frequency: %d Hz (IF spectrum %s).\n",
+ if_frequency[1],
+ if_frequency[0] ? "inverted" : "normal");
+ }
}
n += sprintf(buff + n, "\n");
struct class_attribute *attr, const char *buf, size_t count)
{
int n = 0;
- unsigned int ret = 0;
+ unsigned int ret = 0, delay = 0;
char *buf_orig = NULL, *ps = NULL, *token = NULL, *name = NULL;
char *parm[10] = { NULL };
unsigned long val = 0, freq = 0, symbol = 0, bw = 0, modul = 0;
struct dvb_demod *demod = get_dvb_demods();
struct dvb_extern_device *dev =
container_of(class, struct dvb_extern_device, class);
- struct dvb_frontend *fe = &dev->fe;
+ struct dvb_frontend *fe = dev->demod_fe;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dtv_property tvp;
+ enum fe_status s = 0;
buf_orig = kstrdup(buf, GFP_KERNEL);
ps = buf_orig;
if (!parm[0])
goto EXIT;
+ if (!fe && strncmp(parm[0], "attach", 6) && strncmp(parm[0], "status", 6)) {
+ pr_err("please attach first:\n");
+ pr_err("echo attach [demod_id] > /sys/class/aml_dvb_extern/demod_debug\n");
+ goto EXIT;
+ }
+
if (!strncmp(parm[0], "init", 4)) {
if (parm[1])
ret = kstrtoul(parm[1], 0, &val);
pr_err("init demod delsys [%d][%s].\n",
c->delivery_system,
fe_delsys_name[c->delivery_system]);
+
+ if (fe->ops.init)
+ ret = fe->ops.init(fe);
+
if (fe->ops.set_property)
ret = fe->ops.set_property(fe, &tvp);
} else if (!strncmp(parm[0], "tune", 4)) {
c->bandwidth_hz = bw;
c->modulation = modul;
- pr_err("[mxl258c] [tune] delivery_system %d, frequency %d, symbol_rate %d, bandwidth_hz %d, modulation %d, inversion %d.\n",
+ pr_err("tune delivery_system %d, frequency %d, symbol_rate %d, bandwidth_hz %d, modulation %d, inversion %d.\n",
c->delivery_system, c->frequency, c->symbol_rate,
c->bandwidth_hz, c->modulation, c->inversion);
- if (fe->ops.set_frontend)
- fe->ops.set_frontend(fe);
+ if (fe->ops.tune)
+ fe->ops.tune(fe, true, 0, &delay, &s);
+ pr_err("tune status: [0x%x] %s.\n", s, s != FE_TIMEDOUT ? "Locked" : "Unlocked");
+ //if (fe->ops.set_frontend)
+ // fe->ops.set_frontend(fe);
} else if (!strncmp(parm[0], "status", 6)) {
- pr_err("demod numbers %d.\n", dev->demod_num);
+ pr_err("demod numbers: %d.\n", dev->demod_num);
pr_err("all demods:\n");
list_for_each_entry(ops, &demod->list, list) {
- name = demod->used->fe ? ops->fe->ops.info.name : "";
- pr_err("demod %d, id %d (%s) %s, %sregistered.\n",
+ name = ops->fe ? ops->fe->ops.info.name : "";
+ pr_err("demod%d, id %d (%s) %s, %sregistered, %sdetected, use tuner0 %s, tuner1 %s.\n",
ops->index, ops->cfg.id,
name ? name : "", ops->attached ?
"attached" : "detached",
- ops->registered ? "" : "un");
+ ops->registered ? "" : "un",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ",
+ ops->cfg.tuner0.name ? ops->cfg.tuner0.name : "NONE",
+ ops->cfg.tuner1.name ? ops->cfg.tuner1.name : "NONE");
}
if (demod->used && demod->used->fe) {
name = ops->fe->ops.info.name;
- pr_err("current use demod %d, id %d (%s), fe type %d, delivery system %d.\n",
+ pr_err("current use demod%d, id %d (%s), fe type %d, delivery system %d.\n",
demod->used->index,
demod->used->cfg.id,
name ? name : "",
if (fe->ops.set_property)
ret = fe->ops.set_property(fe, &tvp);
+
+ if (fe->ops.sleep)
+ ret = fe->ops.sleep(fe);
} else if (!strncmp(parm[0], "attach", 6)) {
demod->attach(demod, true);
if (parm[1])
dev->demod_cur = val;
ops = dvb_demod_ops_get_byindex(dev->demod_cur);
- if (ops) {
- memcpy(&fe->ops, &ops->fe->ops,
- sizeof(struct dvb_frontend_ops));
- memcpy(&fe->dtv_property_cache,
- &ops->fe->dtv_property_cache,
- sizeof(struct dtv_frontend_properties));
+ if (ops && ops->fe) {
+ dev->demod_fe = ops->fe;
+ //memcpy(&fe->ops, &ops->fe->ops,
+ // sizeof(struct dvb_frontend_ops));
+ //memcpy(&fe->dtv_property_cache,
+ // &ops->fe->dtv_property_cache,
+ // sizeof(struct dtv_frontend_properties));
- fe->demodulator_priv = ops->fe->demodulator_priv;
- fe->frontend_priv = ops->fe->frontend_priv;
+ //fe->demodulator_priv = ops->fe->demodulator_priv;
+ //fe->frontend_priv = ops->fe->frontend_priv;
demod->used = ops;
}
} else if (!strncmp(parm[0], "detach", 6)) {
demod->attach(demod, false);
+
+ dev->demod_fe = NULL;
+ } else if (!strncmp(parm[0], "match", 5)) {
+ if (parm[1])
+ ret = kstrtoul(parm[1], 0, &val);
+ else
+ val = FE_ANALOG;
+
+ if (val > FE_ISDBT) {
+ pr_err("input demod match fe type %ld error.\n", val);
+
+ goto EXIT;
+ }
+
+ if (demod->match(demod, val))
+ pr_err("demod match fe type %ld (%s) done.\n",
+ val, fe_type_name[val]);
+ else
+ pr_err("demod match fe type %ld (%s) fail.\n",
+ val, fe_type_name[val]);
+
+ } else if (!strncmp(parm[0], "detect", 6)) {
+ demod->detect(demod);
} else if (!strncmp(parm[0], "register", 8)) {
demod->register_frontend(demod, true);
} else if (!strncmp(parm[0], "unregister", 10)) {
struct dvb_extern_device *dev =
container_of(class, struct dvb_extern_device, class);
- n += sprintf(buff + n, "\nDemod Debug Usage:\n");
+ n += sprintf(buff + n, "\nDemod Debug Usage (%s):\n", AML_DVB_EXTERN_VERSION);
n += sprintf(buff + n, "[status]\necho status > %s\n", path);
- n += sprintf(buff + n, "[attach]\necho attach > %s\n", path);
+ n += sprintf(buff + n, "[attach]\necho attach [demod_id] > %s\n", path);
n += sprintf(buff + n, "[detach]\necho detach > %s\n", path);
+ n += sprintf(buff + n, "[match]\necho match [fe_type] > %s\n", path);
+ n += sprintf(buff + n, "\tfe_type:\n");
+ n += sprintf(buff + n, "\tDVB-S/S2 [FE_QPSK] : 0\n");
+ n += sprintf(buff + n, "\tDVB-C [FE_QAM] : 1\n");
+ n += sprintf(buff + n, "\tDVB-T/T2 [FE_OFDM] : 2\n");
+ n += sprintf(buff + n, "\tATSC [FE_ATSC] : 3\n");
+ n += sprintf(buff + n, "\tANALOG [FE_ANALOG]: 4\n");
+ n += sprintf(buff + n, "\tDTMB [FE_DTMB] : 5\n");
+ n += sprintf(buff + n, "\tISDBT [FE_ISDBT] : 6\n");
+ n += sprintf(buff + n, "[detect]\necho detect > %s\n", path);
n += sprintf(buff + n, "[register]\necho register > %s\n", path);
n += sprintf(buff + n, "[unregister]\necho unregister > %s\n", path);
n += sprintf(buff + n, "[init]\n");
n += sprintf(buff + n, "\tQAM_4_NR : 13\n");
n += sprintf(buff + n, "[uninit]\necho uninit > %s\n", path);
- n += sprintf(buff + n, "\ndemod status:\n");
- n += sprintf(buff + n, "demod numbers %d.\n", dev->demod_num);
+ n += sprintf(buff + n, "\n------------------------------------------------------------\n");
+ n += sprintf(buff + n, "\nDemod Status:\n");
+ n += sprintf(buff + n, "demod numbers: %d.\n", dev->demod_num);
n += sprintf(buff + n, "all demods:\n");
list_for_each_entry(ops, &demod->list, list) {
name = ops->fe ? ops->fe->ops.info.name : "";
- n += sprintf(buff + n, "demod %d, id %d (%s) %s, %sregistered.\n",
+ n += sprintf(buff + n, "demod%d, id %d (%s) %s, %sregistered, %sdetected, use tuner0 %s, tuner1 %s.\n",
ops->index, ops->cfg.id,
name ? name : "", ops->attached ?
"attached" : "detached",
- ops->registered ? "" : "un");
+ ops->registered ? "" : "un",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ",
+ ops->cfg.tuner0.name ? ops->cfg.tuner0.name : "NONE",
+ ops->cfg.tuner1.name ? ops->cfg.tuner1.name : "NONE");
}
if (demod->used && demod->used->fe) {
name = demod->used->fe->ops.info.name;
n += sprintf(buff + n,
- "current use demod %d, id %d (%s), fe type %d, delivery system %d.\n",
+ "current use demod%d, id %d (%s), fe type %d, delivery system %d.\n",
demod->used->index,
demod->used->cfg.id,
name ? name : "",
return n;
}
+static ssize_t dvb_debug_store(struct class *class,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ int n = 0;
+ unsigned long val = 0;
+ char *buf_orig = NULL, *ps = NULL, *token = NULL;
+ char *parm[10] = { NULL };
+ struct dvb_extern_device *dev =
+ container_of(class, struct dvb_extern_device, class);
+
+ buf_orig = kstrdup(buf, GFP_KERNEL);
+ ps = buf_orig;
+
+ while (1) {
+ token = strsep(&ps, "\n ");
+ if (!token)
+ break;
+
+ if (*token == '\0')
+ continue;
+
+ if (n >= 10)
+ break;
+
+ parm[n++] = token;
+ }
+
+ if (!parm[0])
+ goto EXIT;
+
+ if (!strncmp(parm[0], "dvb_power", 9)) {
+ if (parm[1] && kstrtoul(parm[1], 0, &val) == 0) {
+ aml_dvb_extern_set_power(&dev->dvb_power, val);
+
+ pr_err("set dvb power: %s.\n", val ? "ON" : "OFF");
+ } else {
+ pr_err("please input power status of DVB to be set: 1[ON] or 0[OFF].\n");
+ }
+ } else {
+ pr_err("invalid command: %s.\n", parm[0]);
+ }
+
+EXIT:
+ kfree(buf_orig);
+
+ return count;
+}
+
+static ssize_t dvb_debug_show(struct class *class,
+ struct class_attribute *attr, char *buff)
+{
+ int n = 0;
+ const char *path = "/sys/class/aml_dvb_extern/dvb_debug";
+ struct dvb_extern_device *dev =
+ container_of(class, struct dvb_extern_device, class);
+
+ n += sprintf(buff + n, "\nDVB Extern Version: %s.\n",
+ AML_DVB_EXTERN_VERSION);
+ n += sprintf(buff + n, "\ndvb power gpio: %d, dir: %d, value: %d.\n",
+ dev->dvb_power.pin, dev->dvb_power.dir, dev->dvb_power.value);
+ n += sprintf(buff + n, "[set dvb power]\necho dvb_power [value] > %s\n",
+ path);
+ n += sprintf(buff + n, "\tvalue: 1 - [ON], 0 - [OFF].\n");
+
+ return n;
+}
+
+static int tuner_debug_seq_show(struct seq_file *m, void *v)
+{
+ char *name = NULL;
+ struct tuner_ops *ops = NULL;
+ struct dvb_tuner *tuner = get_dvb_tuners();
+ u32 status = FE_TIMEDOUT, frequency = 0, bandwidth = 0;
+ u32 if_frequency[2] = { 0 };
+ s16 strength = 0;
+ struct dvb_extern_device *dev = m->private;
+
+ seq_puts(m, "\n------------------------------------------------------------\n");
+ seq_puts(m, "Tuner Status:\n");
+ seq_printf(m, "tuner numbers: %d.\n", dev->tuner_num);
+ seq_puts(m, "all tuners:\n");
+ list_for_each_entry(ops, &tuner->list, list) {
+ name = ops->fe.ops.tuner_ops.info.name;
+ seq_printf(m, "tuner %d, id %d (%s) addr 0x%x, adap 0x%p %s, %sdetected.\n",
+ ops->index, ops->cfg.id,
+ name ? name : "",
+ ops->cfg.i2c_addr, ops->cfg.i2c_adap,
+ ops->attached ? "attached" : "detached",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ");
+ }
+
+ if (tuner->used) {
+ name = tuner->used->fe.ops.tuner_ops.info.name;
+ seq_printf(m, "current use tuner%d, id %d (%s), fe type %d.\n",
+ tuner->used->index,
+ tuner->used->cfg.id,
+ name ? name : "",
+ tuner->used->type);
+
+ if (tuner->used->fe.ops.tuner_ops.get_status) {
+ tuner->used->fe.ops.tuner_ops.get_status(
+ &tuner->used->fe, &status);
+ seq_printf(m, "signal status: %s.\n",
+ status & FE_HAS_LOCK ? "Locked" : "Unlocked");
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_strength) {
+ tuner->used->fe.ops.tuner_ops.get_strength(
+ &tuner->used->fe, &strength);
+ seq_printf(m, "strength: %d dBm.\n", strength);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_frequency(
+ &tuner->used->fe, &frequency);
+ seq_printf(m, "frequency: %d Hz.\n", frequency);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_bandwidth) {
+ tuner->used->fe.ops.tuner_ops.get_bandwidth(
+ &tuner->used->fe, &bandwidth);
+ seq_printf(m, "bandwidth: %d Hz.\n", bandwidth);
+ }
+
+ if (tuner->used->fe.ops.tuner_ops.get_if_frequency) {
+ tuner->used->fe.ops.tuner_ops.get_if_frequency(
+ &tuner->used->fe, if_frequency);
+ seq_printf(m, "if frequency: %d Hz (IF spectrum %s).\n",
+ if_frequency[1],
+ if_frequency[0] ? "inverted" : "normal");
+ }
+ }
+
+ seq_puts(m, "------------------------------------------------------------\n\n");
+
+ return 0;
+}
+
+static int tuner_debug_seq_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, tuner_debug_seq_show, PDE_DATA(inode));
+}
+
+static const struct file_operations tuner_debug_fops = {
+ .owner = THIS_MODULE,
+ .open = tuner_debug_seq_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release
+};
+
+static int demod_debug_seq_show(struct seq_file *m, void *v)
+{
+ char *name = NULL;
+ struct demod_ops *ops = NULL;
+ struct dvb_demod *demod = get_dvb_demods();
+ struct dvb_extern_device *dev = m->private;
+
+ seq_puts(m, "\nDemod Status:\n");
+ seq_printf(m, "demod numbers: %d.\n", dev->demod_num);
+ seq_puts(m, "all demods:\n");
+ list_for_each_entry(ops, &demod->list, list) {
+ name = ops->fe ? ops->fe->ops.info.name : "";
+ seq_printf(m, "demod%d, id %d (%s) %s, %sregistered, %sdetected, use tuner0 %s, tuner1 %s.\n",
+ ops->index, ops->cfg.id,
+ name ? name : "", ops->attached ?
+ "attached" : "detached",
+ ops->registered ? "" : "un",
+ ops->cfg.detect ? (ops->valid ? "" : "un") : "no ",
+ ops->cfg.tuner0.name ? ops->cfg.tuner0.name : "NONE",
+ ops->cfg.tuner1.name ? ops->cfg.tuner1.name : "NONE");
+ }
+
+ if (demod->used && demod->used->fe) {
+ name = demod->used->fe->ops.info.name;
+ seq_printf(m, "current use demod%d, id %d (%s), fe type %d, delivery system %d.\n",
+ demod->used->index,
+ demod->used->cfg.id,
+ name ? name : "",
+ demod->used->type,
+ demod->used->fe->dtv_property_cache.delivery_system);
+ }
+
+ seq_puts(m, "\n");
+
+ return 0;
+}
+
+static int demod_debug_seq_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, demod_debug_seq_show, PDE_DATA(inode));
+}
+
+static const struct file_operations demod_debug_fops = {
+ .owner = THIS_MODULE,
+ .open = demod_debug_seq_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release
+};
+
static struct class_attribute dvb_extern_class_attrs[] = {
__ATTR(tuner_debug, 0644, tuner_debug_show, tuner_debug_store),
__ATTR(demod_debug, 0644, demod_debug_show, demod_debug_store),
+ __ATTR(dvb_debug, 0644, dvb_debug_show, dvb_debug_store),
__ATTR_NULL
};
{
int ret = -1, i = 0;
unsigned int val = 0;
+ char buf[32] = { 0 };
+ const char *str = NULL;
struct tuner_ops *tops = NULL;
struct demod_ops *dops = NULL;
struct dvb_extern_device *dvbdev = NULL;
dvbdev->class.owner = THIS_MODULE;
dvbdev->class.class_attrs = dvb_extern_class_attrs;
+ dvbdev->debug_proc_dir = proc_mkdir(AML_DVB_EXTERN_DEVICE_NAME, NULL);
+ if (!dvbdev->debug_proc_dir)
+ goto fail_proc_dir;
+
+ if (!proc_create_data("tuner_debug", 0644, dvbdev->debug_proc_dir,
+ &tuner_debug_fops, dvbdev)) {
+ pr_err("proc create tuner_debug fail.\n");
+ goto fail_proc_create;
+ }
+
+ if (!proc_create_data("demod_debug", 0644, dvbdev->debug_proc_dir,
+ &demod_debug_fops, dvbdev)) {
+ pr_err("proc create tuner_debug fail.\n");
+ goto fail_proc_create;
+ }
+
if (class_register(&dvbdev->class)) {
pr_err("class register fail.\n");
goto fail_class_register;
}
+ /* DVB Power pin. */
+ str = NULL;
+ ret = of_property_read_string(pdev->dev.of_node,
+ "dvb_power_gpio", &str);
+ if (ret) {
+ dvbdev->dvb_power.pin = -1;
+ } else {
+ dvbdev->dvb_power.pin = of_get_named_gpio_flags(pdev->dev.of_node,
+ "dvb_power_gpio", 0, NULL);
+ pr_err("get dvb_power_gpio: %d.\n", dvbdev->dvb_power.pin);
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "dvb_power_dir", &val);
+ if (ret) {
+ dvbdev->dvb_power.dir = 0;
+ } else {
+ dvbdev->dvb_power.dir = val;
+ pr_err("get dvb_power_dir: %d (%s).\n",
+ dvbdev->dvb_power.pin, val ? "IN" : "OUT");
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "dvb_power_value", &val);
+ if (ret) {
+ dvbdev->dvb_power.value = 0;
+ } else {
+ dvbdev->dvb_power.value = val;
+ pr_err("get dvb_power_value: %d.\n", dvbdev->dvb_power.value);
+ }
+
/* PROPERTY_TUNER */
ret = of_property_read_u32(pdev->dev.of_node, "tuner_num", &val);
if (ret == 0) {
}
ret = of_property_read_u32(pdev->dev.of_node, "tuner_cur", &val);
- if (ret) {
- pr_err("can't find tuner_cur, use default 0.\n");
+ if (ret)
dvbdev->tuner_cur = 0;
- } else {
+ else
dvbdev->tuner_cur = val;
- }
for (i = 0; i < dvbdev->tuner_num; ++i) {
tops = dvb_tuner_ops_create();
if (ret) {
dvb_tuner_ops_destroy(tops);
- pr_err("can't find tuner %d.\n", i);
+ pr_err("can't find tuner%d.\n", i);
} else {
tops->index = i;
- pr_err("find tuner %d, id %d, i2c_addr 0x%x.\n",
+ pr_err("find tuner%d, id %d, i2c_addr 0x%x.\n",
i, tops->cfg.id, tops->cfg.i2c_addr);
ret = dvb_tuner_ops_add(tops);
}
ret = of_property_read_u32(pdev->dev.of_node, "fe_cur", &val);
- if (ret) {
- pr_err("can't find fe current use, use default 0.\n");
+ if (ret)
dvbdev->demod_cur = 0;
- } else {
+ else
dvbdev->demod_cur = val;
- }
for (i = 0; i < dvbdev->demod_num; ++i) {
dops = dvb_demod_ops_create();
if (ret) {
dvb_demod_ops_destroy(dops);
- pr_err("can't find demod %d.\n", i);
+ pr_err("can't find demod%d.\n", i);
continue;
}
dops->index = i;
- pr_err("find demod %d, id %d, i2c_addr 0x%x.\n",
+ pr_err("find demod%d, id %d, i2c_addr 0x%x.\n",
i, dops->cfg.id, dops->cfg.i2c_addr);
ret = dvb_demod_ops_add(dops);
* demod includes the tuner driver.
*/
/* T/C tuner */
- ret = of_property_read_u32(pdev->dev.of_node,
- "fe0_tuner0", &val);
+ memset(buf, 0, sizeof(buf));
+ snprintf(buf, sizeof(buf), "fe%d_tuner0", i);
+ ret = of_property_read_u32(pdev->dev.of_node, buf, &val);
if (!ret) {
tops = dvb_tuner_ops_get_byindex(val);
if (tops)
memcpy(&dops->cfg.tuner0, &tops->cfg,
sizeof(struct tuner_config));
- pr_err("get fe0_tuner0 %d.\n", val);
+ pr_err("get %s %d.\n", buf, val);
}
/* S/S2 tuner */
- ret = of_property_read_u32(pdev->dev.of_node,
- "fe0_tuner1", &val);
+ memset(buf, 0, sizeof(buf));
+ snprintf(buf, sizeof(buf), "fe%d_tuner1", i);
+ ret = of_property_read_u32(pdev->dev.of_node, buf, &val);
if (!ret) {
tops = dvb_tuner_ops_get_byindex(val);
if (tops)
memcpy(&dops->cfg.tuner1, &tops->cfg,
sizeof(struct tuner_config));
- pr_err("get fe0_tuner1 %d.\n", val);
+ pr_err("get %s %d.\n", buf, val);
}
}
+ aml_demod_gpio_config(&dvbdev->dvb_power, "dvb_power");
+ aml_dvb_extern_set_power(&dvbdev->dvb_power, 1);
+
PROPERTY_DONE:
dvb_extern_dev = dvbdev;
class_unregister(&dvbdev->class);
fail_class_register:
+fail_proc_create:
+ proc_remove(dvbdev->debug_proc_dir);
+
+fail_proc_dir:
kfree(dvbdev);
dvbdev = NULL;
dvb_demod_ops_destroy_all();
class_unregister(&dvbdev->class);
+ if (dvbdev->debug_proc_dir)
+ proc_remove(dvbdev->debug_proc_dir);
+
+ aml_dvb_extern_set_power(&dvbdev->dvb_power, 0);
kfree(dvbdev);
dvbdev = NULL;
static void aml_dvb_extern_shutdown(struct platform_device *pdev)
{
+ struct dvb_extern_device *dvbdev = platform_get_drvdata(pdev);
+
+ if (IS_ERR_OR_NULL(dvbdev))
+ return;
+
+ aml_dvb_extern_set_power(&dvbdev->dvb_power, 0);
}
static int aml_dvb_extern_suspend(struct platform_device *pdev,
pm_message_t state)
{
+ struct dvb_extern_device *dvbdev = platform_get_drvdata(pdev);
+
+ if (IS_ERR_OR_NULL(dvbdev))
+ return -EFAULT;
+
+ aml_dvb_extern_set_power(&dvbdev->dvb_power, 0);
+
return 0;
}
static int aml_dvb_extern_resume(struct platform_device *pdev)
{
+ struct dvb_extern_device *dvbdev = platform_get_drvdata(pdev);
+
+ if (IS_ERR_OR_NULL(dvbdev))
+ return -EFAULT;
+
+ aml_dvb_extern_set_power(&dvbdev->dvb_power, 1);
+
return 0;
}
struct class class;
struct device *dev;
+ struct proc_dir_entry *debug_proc_dir;
+
/* for debug. */
- struct dvb_frontend fe;
+ struct dvb_frontend *tuner_fe;
+ struct dvb_frontend *demod_fe;
struct analog_parameters para;
+ struct gpio_config dvb_power;
+
int tuner_num;
int tuner_cur;
int tuner_cur_attached;
{
int i = 0;
int ret = 0;
- unsigned char data_w[2] = { 0, 0 };
- unsigned char data_r[2] = { 0, 0 };
+ unsigned char data_w[4] = { 0, 0, 0, 0 };
+ unsigned char data_r[4] = { 0, 0, 0, 0 };
struct i2c_msg msg_w, msg_r;
if (IS_ERR_OR_NULL(cfg) || IS_ERR_OR_NULL(cfg->i2c_adap))
break;
case AM_TUNER_MXL661:
- msg_w.len = 1;
- data_w[0] = 0x18;
+ msg_w.len = 2;
+ data_w[0] = 0xFB;
+ data_w[1] = 0x18;
msg_r.len = 1;
data_r[0] = 0x00;
list_for_each_entry(ops, &tuner->list, list) {
if ((ops->attached && attach) ||
(!ops->attached && !attach)) {
- pr_err("Tuner: tuner [%d] had %s.\n", ops->cfg.id,
+ pr_err("Tuner: tuner%d [id %d] had %s.\n",
+ ops->index, ops->cfg.id,
attach ? "attached" : "detached");
continue;
else
ops->attached = false;
- pr_err("Tuner: attach tuner [%d] %s.\n", ops->cfg.id,
+ pr_err("Tuner: attach tuner%d [id %d] %s.\n",
+ ops->index, ops->cfg.id,
ops->attached ? "done" : "fail");
} else {
if (tuner->used == ops)
memset(&ops->fe, 0, sizeof(struct dvb_frontend));
- pr_err("Tuner: detach tuner [%d] done.\n",
- ops->cfg.id);
+ pr_err("Tuner: detach tuner%d [id %d] done.\n",
+ ops->index, ops->cfg.id);
}
}
mutex_lock(&tuner->mutex);
list_for_each_entry(ops, &tuner->list, list) {
+ ret = 0;
+
if (!ops->attached || !ops->cfg.detect || ops->valid)
continue;
- if (ops->fe.ops.tuner_ops.set_config)
+ if (ops->fe.ops.tuner_ops.set_config) {
ret = ops->fe.ops.tuner_ops.set_config(&ops->fe, NULL);
+ } else {
+ pr_err("Tuner: tuner%d [id %d] set_config() is NULL.\n",
+ ops->index, ops->cfg.id);
+
+ continue;
+ }
if (!ret) {
ret = ops->module->detect(&ops->cfg);
else
ops->valid = false;
- pr_err("Tuner: detect tuner [%d] %s.\n", ops->cfg.id,
+ pr_err("Tuner: detect tuner%d [id %d] %s.\n",
+ ops->index, ops->cfg.id,
ops->valid ? "done" : "fail");
if (ops->fe.ops.tuner_ops.release)
- ret = ops->fe.ops.tuner_ops.release(&ops->fe);
+ ops->fe.ops.tuner_ops.release(&ops->fe);
+ } else {
+ pr_err("Tuner: tuner%d [id %d] set_config() error, ret %d.\n",
+ ops->index, ops->cfg.id, ret);
+ }
+ }
+
+ mutex_unlock(&tuner->mutex);
+
+ return 0;
+}
+
+static int tuner_pre_init(struct dvb_tuner *tuner)
+{
+ int ret = 0;
+ struct tuner_ops *ops = NULL;
+
+ if (IS_ERR_OR_NULL(tuner))
+ return -EFAULT;
+
+ mutex_lock(&tuner->mutex);
+
+ list_for_each_entry(ops, &tuner->list, list) {
+ if (!ops->attached || ops->pre_inited)
+ continue;
+
+ /* In some cases, pre-init is required. */
+ /* 1. Loop thorugh is enabled. */
+ if (ops->cfg.lt_out) {
+ ret = ops->fe.ops.tuner_ops.set_config(&ops->fe, NULL);
+
+ ops->pre_inited = ret ? false : true;
+
+ pr_err("Tuner: pre_init tuner%d [id %d] %s.\n",
+ ops->index, ops->cfg.id,
+ ret ? "fail" : "done");
+ } else {
+ ops->pre_inited = true;
}
}
.refcount = 0,
.attach = tuner_attach,
.match = tuner_match,
- .detect = tuner_detect
+ .detect = tuner_detect,
+ .pre_init = tuner_pre_init
};
static DEFINE_MUTEX(tuner_fe_type_match_mutex);
+static bool tuner_is_same_cfg(struct tuner_config *cfg1,
+ struct tuner_config *cfg2)
+{
+ return (cfg1->id == cfg2->id &&
+ cfg1->i2c_addr == cfg2->i2c_addr &&
+ cfg1->i2c_adap == cfg2->i2c_adap);
+}
+
+static bool tuner_is_valid_cfg(struct tuner_config *cfg)
+{
+ return !cfg ? false : cfg->id != AM_TUNER_NONE;
+}
+
+static bool tuner_is_valid_ops(struct tuner_ops *ops)
+{
+ return !ops ? false :
+ !(!ops->attached || (ops->cfg.detect && !ops->valid));
+}
+
static struct tuner_ops *tuner_fe_type_match(struct dvb_frontend *fe)
{
char *name = NULL;
- struct tuner_ops *match = NULL;
+ struct tuner_ops *match = NULL, *tops = NULL;
+ struct demod_ops *dops = NULL, *find = NULL;
struct dvb_tuner *tuner = get_dvb_tuners();
+ struct dvb_demod *demod = get_dvb_demods();
mutex_lock(&tuner_fe_type_match_mutex);
- if (tuner->used && tuner->used->type == fe->ops.info.type) {
+ /* First, lookup in the previous match. */
+ if (tuner->used && tuner->used->user == fe &&
+ tuner->used->type == fe->ops.info.type) {
/* name = tuner->used->fe.ops.tuner_ops.info.name;
- * pr_err("Tuner: return current match fe type [%d] tuner (%s).\n",
- * fe->ops.info.type, name ? name : "");
+ * pr_err("Tuner: return current match fe type [%d] tuner%d (%s).\n",
+ * fe->ops.info.type, ops->index, name ? name : "");
*/
mutex_unlock(&tuner_fe_type_match_mutex);
return tuner->used;
}
- match = tuner->match(tuner, fe->ops.info.type);
+ /* Then, check if the specified tuner configuration is present. */
+ list_for_each_entry(dops, &demod->list, list) {
+ if (dops->fe == fe) {
+ /* External demod doesn't need to match tuner. */
+ if (dops->external) {
+ mutex_unlock(&tuner_fe_type_match_mutex);
+
+ return NULL;
+ }
+
+ find = dops;
+
+ break;
+ }
+ }
+
+ if (find) {
+ if (tuner_is_valid_cfg(&find->cfg.tuner0) ||
+ tuner_is_valid_cfg(&find->cfg.tuner1)) {
+ list_for_each_entry(tops, &tuner->list, list) {
+ if (tuner_is_same_cfg(&tops->cfg,
+ &find->cfg.tuner0) ||
+ tuner_is_same_cfg(&tops->cfg,
+ &find->cfg.tuner1)) {
+ if (!tuner_is_valid_ops(tops))
+ continue;
+
+ if (!tops->module->match(tops->module,
+ fe->ops.info.type)) {
+ match = tops;
+
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ /* Finally, lookup all the configurations, not include specified. */
+ if (!match)
+ match = tuner->match(tuner, fe->ops.info.type);
+
if (!match) {
pr_err("Tuner: can't get match fe type [%d] tuner.\n",
fe->ops.info.type);
sizeof(struct dvb_tuner_info));
fe->tuner_priv = match->fe.tuner_priv;
+ match->type = fe->ops.info.type;
match->delivery_system = fe->dtv_property_cache.delivery_system;
+ match->user = fe;
+ tuner->used = match;
+
name = match->fe.ops.tuner_ops.info.name;
- pr_err("Tuner: get match fe type [%d] tuner (%s).\n",
- fe->ops.info.type, name ? name : "");
+ pr_err("Tuner: get match fe type [%d] tuner%d (%s).\n",
+ fe->ops.info.type, match->index,
+ name ? name : "");
}
mutex_unlock(&tuner_fe_type_match_mutex);
/* try detect */
tuner->detect(tuner);
+ tuner->pre_init(tuner);
+
memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
/* try match */
if (ops) {
ops->attached = false;
ops->index = -1;
+ ops->pre_inited = false;
ops->delivery_system = SYS_UNDEFINED;
ops->type = AML_FE_UNDEFINED;
ops->module = NULL;
if (p == ops) {
mutex_unlock(&dvb_tuners_mutex);
- pr_err("Tuner: tuner ops [0x%p] exist.\n", ops);
+ pr_err("Tuner: tuner%d ops [0x%p] exist.\n",
+ ops->index, ops);
return -EEXIST;
}
return -ENODEV;
}
+ ops->cfg.name = ops->module->name;
+
list_add_tail(&ops->list, &tuner->list);
mutex_unlock(&dvb_tuners_mutex);
ops->attached = false;
ops->valid = false;
+ ops->pre_inited = false;
ops->index = -1;
ops->delivery_system = SYS_UNDEFINED;
ops->type = AML_FE_UNDEFINED;
request_firmware_into_buf(&my_fw, "aucpu_fw.bin", device, fw,
AUCPU_MAX_FW_SZ -
sizeof(struct dma_aucpu_dsc_t));
-
+ if (!my_fw) {
+ aucpu_pr(LOG_ERROR, "load aucpu_fw.bin fail\n");
+ kfree(buf);
+ result = AUCPU_ERROR_NOT_IMPLEMENTED;
+ return result;
+ }
length = my_fw->size;
release_firmware(my_fw);
}
/* load FW and start AUCPU */
load_firmware_status = load_start_aucpu_fw(&pdev->dev /*aucpu_dev */);
-
+ if (load_firmware_status) {
+ aucpu_pr(LOG_ERROR, "load start_aucpu_fw fail\n");
+ goto ERROR_PROVE_DEVICE;
+ }
mutex_init(&pctx->mutex);
/*setup the DEBUG buffer */
setup_debug_polling();
#define MAX_SEC_FEED_NUM 32
#define MAX_TS_FEED_NUM 32
-#define MAX_FILTER_PER_SEC_FEED 8
+#define MAX_FILTER_PER_SEC_FEED 32
#define DMX_STATE_FREE 0
#define DMX_STATE_ALLOCATED 1
int media_type = 0;
int cb_id = 0;
int pts_level = 0;
+ int ret = 0;
pr_dbg("%s pid:0x%0x\n", __func__, pid);
0, demux->id, &cb_id);
ts_output_add_cb(feed->ts_out_elem,
out_ts_elem_cb, feed, cb_id,
- format, 0);
+ format, 0, demux->id);
feed->cb_id = cb_id;
mutex_unlock(demux->pmutex);
return 0;
sec_level = DMX_MEM_SEC_LEVEL1;
}
if (sec_level != 0)
- ts_output_set_mem(feed->ts_out_elem,
+ ret = ts_output_set_mem(feed->ts_out_elem,
mem_size, sec_level,
TS_OUTPUT_CHAN_PTS_SEC_BUF_SIZE,
pts_level);
else
- ts_output_set_mem(feed->ts_out_elem,
+ ret = ts_output_set_mem(feed->ts_out_elem,
mem_size, sec_level,
TS_OUTPUT_CHAN_PTS_BUF_SIZE, pts_level);
+ if (ret != 0) {
+ ts_output_close(feed->ts_out_elem);
+ feed->ts_out_elem = NULL;
+ mutex_unlock(demux->pmutex);
+ return -1;
+ }
if (feed->pid == 0x2000)
ts_output_add_pid(feed->ts_out_elem, feed->pid, 0x1fff,
demux->id, &cb_id);
ts_output_add_pid(feed->ts_out_elem, feed->pid, 0,
demux->id, &cb_id);
ts_output_add_cb(feed->ts_out_elem, out_ts_elem_cb, feed,
- cb_id, format, 0);
+ cb_id, format, 0, demux->id);
feed->cb_id = cb_id;
} else {
dprint("%s error\n", __func__);
int sid = 0;
int mem_size = 0;
int cb_id = 0;
+ int ret = 0;
- pr_dbg("%s\n", __func__);
+ pr_dbg("%s dmx id:%d\n", __func__, demux->id);
if (mutex_lock_interruptible(demux->pmutex))
return -ERESTARTSYS;
(unsigned long)(sec_feed->sec_out_elem));
ts_output_add_cb(sec_feed->sec_out_elem,
_ts_out_sec_cb, sec_feed, demux->id,
- SECTION_FORMAT, 1);
+ SECTION_FORMAT, 1, demux->id);
mutex_unlock(demux->pmutex);
return 0;
}
sid, demux->id, SECTION_FORMAT, SEC_TYPE, MEDIA_TS_SYS, 0);
if (sec_feed->sec_out_elem) {
mem_size = sec_buf_size;
- ts_output_set_mem(
- sec_feed->sec_out_elem, mem_size, sec_level, 0, 0);
+ ret = ts_output_set_mem(sec_feed->sec_out_elem,
+ mem_size, sec_level, 0, 0);
+ if (ret != 0) {
+ ts_output_close(sec_feed->sec_out_elem);
+ sec_feed->sec_out_elem = NULL;
+ mutex_unlock(demux->pmutex);
+ return -1;
+ }
ts_output_add_pid(sec_feed->sec_out_elem, sec_feed->pid, 0,
demux->id, &cb_id);
ts_output_add_cb(sec_feed->sec_out_elem,
_ts_out_sec_cb, sec_feed, cb_id,
- SECTION_FORMAT, 1);
+ SECTION_FORMAT, 1, demux->id);
}
pr_dbg("sec_out_elem:0x%lx\n", (unsigned long)(sec_feed->sec_out_elem));
mutex_unlock(demux->pmutex);
int i = 0;
int start_flag = 0;
- pr_dbg("%s\n", __func__);
+ pr_dbg("%s dmx id:%d\n", __func__, demux->id);
if (mutex_lock_interruptible(demux->pmutex))
return -ERESTARTSYS;
struct aml_dmx *demux = (struct aml_dmx *)feed->parent->priv;
int i = 0;
- pr_dbg("%s\n", __func__);
+ pr_dbg("%s dmx id:%d\n", __func__, demux->id);
if (mutex_lock_interruptible(demux->pmutex))
return -ERESTARTSYS;
sec_feed->filter = vmalloc(sizeof(*sec_feed->filter) *
sec_feed->sec_filter_num);
if (!sec_feed->filter) {
+ sec_feed->state = DMX_STATE_FREE;
mutex_unlock(demux->pmutex);
return -EBUSY;
}
if (hw_source >= DMA_0 && hw_source <= DMA_7) {
demux->local_sid = hw_source - DMA_0;
+ ts_output_update_filter(demux->id, demux->local_sid);
dsc_set_sid(demux->id, INPUT_LOCAL, demux->local_sid);
} else if (hw_source >= FRONTEND_TS0 && hw_source <= FRONTEND_TS7) {
demux->ts_index = hw_source - FRONTEND_TS0;
if (advb->ts[demux->ts_index].ts_sid != -1) {
demux->demod_sid = advb->ts[demux->ts_index].ts_sid;
+ ts_output_update_filter(demux->id, demux->demod_sid);
dsc_set_sid(demux->id, INPUT_DEMOD, demux->demod_sid);
}
}
return size;
}
-static int out_ts_elem_cb_test(struct out_elem *pout, char *buf,
- int count, void *udata,
- int req_len, int *req_ret)
-{
- dprint("get data...\n");
- return count;
-}
-
-void test_sid(void)
-{
- int i = 0;
- struct out_elem *ts_out_elem;
-
- for (i = 0; i < 64; i++) {
- dprint("##########sid:%d\n", i);
- ts_out_elem = ts_output_open(i, 0, SECTION_FORMAT,
- OTHER_TYPE, 0, 0);
- if (ts_out_elem) {
- ts_output_add_cb(ts_out_elem,
- out_ts_elem_cb_test, NULL, 0,
- SECTION_FORMAT, 1);
- ts_output_set_mem(ts_out_elem, pes_buf_size, 0, 0, 0);
- ts_output_add_pid(ts_out_elem, 0, 0, 0, 0);
- } else {
- dprint("%s error\n", __func__);
- }
- msleep(2000);
- sc2_dump_register();
-
- ts_output_close(ts_out_elem);
- }
-}
-
-static ssize_t debug_sid_show(struct class *class,
- struct class_attribute *attr, char *buf)
-{
- ts_output_sid_debug();
- test_sid();
- return 0;
-}
-
static ssize_t dump_register_show(struct class *class,
struct class_attribute *attr, char *buf)
{
return size;
}
+static ssize_t cache_status_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ ssize_t size;
+ struct aml_dvb *advb = aml_get_dvb_device();
+
+ if (mutex_lock_interruptible(&advb->mutex))
+ return -ERESTARTSYS;
+
+ size = cache_status_info(buf);
+ mutex_unlock(&advb->mutex);
+ return size;
+}
+
+static ssize_t cache_status_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t size)
+{
+ int cache0_count = 0;
+ int cache1_count = 0;
+ int ret = 0;
+
+ struct aml_dvb *advb = aml_get_dvb_device();
+
+ if (mutex_lock_interruptible(&advb->mutex))
+ return -ERESTARTSYS;
+
+ dprint_i("%s\n", buf);
+ if (!strncmp(buf, "clear", 5)) {
+ cache_clear();
+ } else if (!strncmp(buf, "adjust", 6)) {
+ ret = sscanf(buf + 7, "%d %d", &cache0_count, &cache1_count);
+ if (ret == 2 && cache0_count > 0 && cache1_count > 0)
+ cache_adjust(cache0_count, cache1_count);
+ }
+ mutex_unlock(&advb->mutex);
+ return size;
+}
+
static ssize_t dump_av_level_show(struct class *class,
struct class_attribute *attr, char *buf)
{
dump_register_store),
__ATTR(dump_filter, 0644, dump_filter_show,
dump_filter_store),
- __ATTR(debug_sid, 0644, debug_sid_show,
- NULL),
__ATTR(dump_av_level, 0644, dump_av_level_show,
NULL),
+ __ATTR(cache_status, 0644, cache_status_show,
+ cache_status_store),
__ATTR_NULL
};
#include <linux/dvb/dmx.h>
#include <linux/amlogic/tee.h>
#include <linux/amlogic/aml_key.h>
+#include <linux/amlogic/tee_demux.h>
#include "aml_dvb.h"
#include "am_key.h"
static int sid_info[MAX_DMX_DEV_NUM];
#define DEFAULT_DMX_DEV_NUM 3
+int is_security_dmx;
+
ssize_t get_pcr_show(struct class *class,
struct class_attribute *attr, char *buf)
{
{
struct aml_dvb *advb = aml_get_dvb_device();
int tsn_in_reg = 0;
- int i = 0;
if (!strncmp(buf, "demod", 5))
tsn_in = INPUT_DEMOD;
// pr_dbg("tsn_in:%d, tsn_out:%d\n", tsn_in_reg, tsn_out);
advb->dsc_pipeline = tsn_in_reg;
//set demod/local
+#ifdef CONFIG_AMLOGIC_TEE
tee_demux_config_pipeline(tsn_in_reg, tsn_out);
- for (i = 0; i < dmx_dev_num; i++) {
- advb->dmx[i].source = tsn_in;
- advb->dsc[i].source = tsn_in;
- }
-
+#endif
mutex_unlock(&advb->mutex);
return count;
}
class_register(&aml_dvb_class);
dmx_regist_dmx_class();
- dprint("probe dvb done\n");
+#ifdef CONFIG_AMLOGIC_TEE
+ ret = tee_demux_get(TEE_DMX_GET_SECURITY_ENABLE,
+ NULL, 0, &is_security_dmx, sizeof(is_security_dmx));
+
+#endif
+ dprint("probe dvb done, ret:%d, is_security_dmx:%d\n",
+ ret, is_security_dmx);
return 0;
struct aml_dvb *aml_get_dvb_device(void);
struct device *aml_get_device(void);
+extern int is_security_dmx;
+
#endif
#define MKL_STS_OK (0)
#define MKL_USER_CRYPTO_T0 (0)
+#define MKL_USER_CRYPTO_T1 (1)
+#define MKL_USER_CRYPTO_T2 (2)
+#define MKL_USER_CRYPTO_T3 (3)
+#define MKL_USER_CRYPTO_T4 (4)
+#define MKL_USER_CRYPTO_T5 (5)
#define MKL_USER_LOC_DEC (8)
#define MKL_USER_NETWORK (9)
#define MKL_USER_LOC_ENC (10)
case CRYPTO_T0:
key_table[index].key_userid = MKL_USER_CRYPTO_T0;
break;
+ case CRYPTO_T1:
+ key_table[index].key_userid = MKL_USER_CRYPTO_T1;
+ break;
+ case CRYPTO_T2:
+ key_table[index].key_userid = MKL_USER_CRYPTO_T2;
+ break;
+ case CRYPTO_T3:
+ key_table[index].key_userid = MKL_USER_CRYPTO_T3;
+ break;
+ case CRYPTO_T4:
+ key_table[index].key_userid = MKL_USER_CRYPTO_T4;
+ break;
+ case CRYPTO_T5:
+ key_table[index].key_userid = MKL_USER_CRYPTO_T5;
+ break;
default:
dprint("%s, %d invalid user id\n",
__func__, __LINE__);
memcpy((void *)&key3, &key[12], 4);
user_id = key_table[index].key_userid;
- if (user_id == MKL_USER_CRYPTO_T0) {
+ if (user_id <= MKL_USER_CRYPTO_T5) {
if (key_len == 1) {
en_decrypt = 1;
} else if (key_len == 2) {
} else if (!strcmp(str, "parallel")) {
dprint("ts%d:%s\n", i, str);
- if (i != 1) {
- dprint("error %s:parallel should be ts1\n", buf);
- return;
- }
+ /*internal demod will use tsin_b/tsin_c parallel*/
+// if (i != 1) {
+// dprint("error %s:parallel should be ts1\n", buf);
+// return;
+// }
memset(buf, 0, 32);
snprintf(buf, sizeof(buf), "p_ts%d", i);
advb->ts[i].mode = AM_TS_PARALLEL;
memset(buf, 0, 32);
snprintf(buf, sizeof(buf), "ts%d_sid_offset", i);
ret = of_property_read_u32(pdev->dev.of_node, buf, &value);
- if (!ret) {
+ if (!ret && advb->ts[i].header_len) {
advb->ts[i].sid_offset = value;
advb->ts[i].ts_sid = advb->ts[i].header[value];
}
if (advb->ts[i].ts_sid != -1) {
sid = advb->ts[i].ts_sid;
demod_config_single(i, sid);
+ demod_config_fifo(i, 5 * 188);
}
- } else
+ } else {
demod_config_multi(i, advb->ts[i].header_len / 4,
advb->ts[i].header[0],
advb->ts[i].sid_offset);
+ demod_config_fifo(i, 5 * 188);
+ }
}
}
#define INPUT_DUMP_FILE "/data/input_dump.ts"
+struct mem_cache {
+ unsigned long start_virt;
+ unsigned long start_phys;
+ unsigned char elem_count;
+ unsigned int elem_size;
+ unsigned int used_count;
+ char flag_arry[64];
+};
+
+#define FIRST_CACHE_ELEM_COUNT 64
+
+#define SECOND_CACHE_ELEM_COUNT 48
+#define SECOND_CACHE_ELEM_SIZE (188 * 500)
+
+static int cache0_count_max = FIRST_CACHE_ELEM_COUNT;
+static int cache1_count_max = SECOND_CACHE_ELEM_COUNT;
+
+static struct mem_cache *first_cache;
+static struct mem_cache *second_cache;
+
+static int cache_init(int cache_level)
+{
+ int total_size = 0;
+ int flags = 0;
+ int buf_page_num = 0;
+
+ if (cache_level == 0 && !first_cache) {
+ first_cache = vmalloc(sizeof(*first_cache));
+ if (!first_cache)
+ return -1;
+
+ memset(first_cache, 0, sizeof(struct mem_cache));
+ first_cache->elem_size = sizeof(union mem_desc);
+ first_cache->elem_count = cache0_count_max;
+ total_size = sizeof(union mem_desc) * cache0_count_max;
+ first_cache->start_virt =
+ (unsigned long)kmalloc(total_size, GFP_KERNEL);
+ if (!first_cache->start_virt) {
+ vfree(first_cache);
+ first_cache = NULL;
+ dprint("%s first cache fail\n", __func__);
+ return -1;
+ }
+ first_cache->start_phys =
+ (unsigned long)virt_to_phys((void *)first_cache->start_virt);
+ } else if (cache_level == 1 && !second_cache) {
+ second_cache = vmalloc(sizeof(*second_cache));
+ if (!second_cache)
+ return -1;
+
+ memset(second_cache, 0, sizeof(struct mem_cache));
+ second_cache->elem_size = SECOND_CACHE_ELEM_SIZE;
+ second_cache->elem_count = cache1_count_max;
+ total_size = cache1_count_max * SECOND_CACHE_ELEM_SIZE;
+
+ flags = CODEC_MM_FLAGS_DMA_CPU;
+ buf_page_num = PAGE_ALIGN(total_size) / PAGE_SIZE;
+
+ second_cache->start_phys =
+ codec_mm_alloc_for_dma("dmx_cache", buf_page_num,
+ 4 + PAGE_SHIFT, flags);
+ if (!second_cache->start_phys) {
+ vfree(second_cache);
+ second_cache = NULL;
+ dprint("%s second cache fail\n", __func__);
+ return -1;
+ }
+ second_cache->start_virt =
+ (unsigned long)codec_mm_phys_to_virt(second_cache->start_phys);
+ }
+ return 0;
+}
+
+static void cache_destroy(int cache_level)
+{
+ if (cache_level == 0 && first_cache) {
+ kfree((void *)first_cache->start_virt);
+ vfree(first_cache);
+ first_cache = NULL;
+ dprint_i("clear first cache done\n");
+ } else if (cache_level == 1 && second_cache) {
+ codec_mm_free_for_dma("dmx_cache", second_cache->start_phys);
+ vfree(second_cache);
+ second_cache = NULL;
+ dprint_i("clear second cache done\n");
+ }
+}
+
+static int cache_get_block(struct mem_cache *cache,
+ unsigned long *p_virt, unsigned long *p_phys)
+{
+ int i = 0;
+
+ for (i = 0; i < cache->elem_count; i++) {
+ if (cache->flag_arry[i] == 0)
+ break;
+ }
+
+ if (i == cache->elem_count) {
+ dprint_i("dmx cache full\n");
+ return -1;
+ }
+ if (p_virt)
+ *p_virt = cache->start_virt + i * cache->elem_size;
+ if (p_phys)
+ *p_phys = cache->start_phys + i * cache->elem_size;
+
+ cache->flag_arry[i] = 1;
+ cache->used_count++;
+ return 0;
+}
+
+static int cache_free_block(struct mem_cache *cache, unsigned long phys_mem)
+{
+ int i = 0;
+
+ if (phys_mem >= cache->start_phys &&
+ phys_mem <= cache->start_phys +
+ (cache->elem_count - 1) * cache->elem_size) {
+ for (i = 0; i < cache->elem_count; i++) {
+ if (phys_mem ==
+ cache->start_phys +
+ i * cache->elem_size) {
+ cache->flag_arry[i] = 0;
+ cache->used_count--;
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
+static int cache_malloc(int len, unsigned long *p_virt, unsigned long *p_phys)
+{
+// dprint("%s, len:%d\n", __func__, len);
+ if (!first_cache) {
+ if (cache_init(0) != 0)
+ return -1;
+ }
+ if (!second_cache) {
+ if (cache_init(1) != 0)
+ return -1;
+ }
+
+ if (len <= first_cache->elem_size)
+ return cache_get_block(first_cache, p_virt, p_phys);
+ else if (len <= second_cache->elem_size)
+ return cache_get_block(second_cache, p_virt, p_phys);
+
+ return -1;
+}
+
+static int cache_free(int len, unsigned long phys_mem)
+{
+ int iret = -1;
+
+ if (first_cache && len <= first_cache->elem_size)
+ iret = cache_free_block(first_cache, phys_mem);
+ else if (second_cache && len <= second_cache->elem_size)
+ iret = cache_free_block(second_cache, phys_mem);
+
+ return iret;
+}
+
+int cache_clear(void)
+{
+ if (first_cache && first_cache->used_count == 0)
+ cache_destroy(0);
+ if (second_cache && second_cache->used_count == 0)
+ cache_destroy(1);
+ return 0;
+}
+
+int cache_adjust(int cache0_count, int cache1_count)
+{
+ if (cache0_count > 64 || cache1_count > 64) {
+ dprint_i("cache count can't bigger than 64\n");
+ return -1;
+ }
+ dprint_i("cache0 count:%d, cache1 count:%d\n",
+ cache0_count, cache1_count);
+ cache0_count_max = cache0_count;
+ cache1_count_max = cache1_count;
+
+ if (first_cache && first_cache->used_count == 0)
+ cache_destroy(0);
+ if (second_cache && second_cache->used_count == 0)
+ cache_destroy(1);
+
+ cache_init(0);
+ cache_init(1);
+ return 0;
+}
+
static void dump_file_open(char *path)
{
if (input_dump_fp)
}
}
+int cache_status_info(char *buf)
+{
+ int r, total = 0;
+
+ if (first_cache) {
+ r = sprintf(buf, "first cache:\n");
+ buf += r;
+ total += r;
+
+ r = sprintf(buf, "total size:%d, block count:%d, ",
+ first_cache->elem_count * first_cache->elem_size,
+ first_cache->elem_count);
+ buf += r;
+ total += r;
+
+ r = sprintf(buf, "block size:%d, used count:%d\n",
+ first_cache->elem_size,
+ first_cache->used_count);
+ buf += r;
+ total += r;
+ } else {
+ r = sprintf(buf, "first cache:no\n");
+ buf += r;
+ total += r;
+ }
+
+ if (second_cache) {
+ r = sprintf(buf, "second cache:\n");
+ buf += r;
+ total += r;
+
+ r = sprintf(buf, "total size:%d, block count:%d, ",
+ second_cache->elem_count * second_cache->elem_size,
+ second_cache->elem_count);
+ buf += r;
+ total += r;
+
+ r = sprintf(buf, "block size:%d, used count:%d\n",
+ second_cache->elem_size,
+ second_cache->used_count);
+ buf += r;
+ total += r;
+ } else {
+ r = sprintf(buf, "second cache:no\n");
+ buf += r;
+ total += r;
+ }
+ return total;
+}
+
int _alloc_buff(unsigned int len, int sec_level,
unsigned long *vir_mem, unsigned long *phy_mem,
unsigned int *handle)
{
int flags = 0;
int buf_page_num = 0;
- unsigned long buf_start;
- unsigned long buf_start_virt;
- u32 ret;
+ unsigned long buf_start = 0;
+ unsigned long buf_start_virt = 0;
+ u32 ret = -1;
+ int iret = 0;
+
+ iret = cache_malloc(len, &buf_start_virt, &buf_start);
+ if (iret == 0) {
+ if (sec_level) {
+#ifdef CONFIG_AMLOGIC_TEE
+ ret = tee_protect_mem_by_type(TEE_MEM_TYPE_DEMUX,
+ buf_start, len, handle);
+#endif
+ pr_dbg("%s, protect 0x%lx, len:%d, ret:0x%x\n",
+ __func__, buf_start, len, ret);
+ }
+ *vir_mem = buf_start_virt;
+ *phy_mem = buf_start;
+ return 0;
+ }
if (len < BEN_LEVEL_SIZE)
flags = CODEC_MM_FLAGS_DMA_CPU;
return -1;
}
if (sec_level) {
+#ifdef CONFIG_AMLOGIC_TEE
//ret = tee_protect_tvp_mem(buf_start, len, handle);
ret = tee_protect_mem_by_type(TEE_MEM_TYPE_DEMUX,
buf_start, len, handle);
+#endif
pr_dbg("%s, protect 0x%lx, len:%d, ret:0x%x\n",
__func__, buf_start, len, ret);
}
void _free_buff(unsigned long buf, unsigned int len, int sec_level,
unsigned int handle)
{
+ int iret = 0;
+
if (sec_level) {
+#ifdef CONFIG_AMLOGIC_TEE
tee_unprotect_mem(handle);
+#endif
pr_dbg("%s, unprotect handle:%d\n", __func__, handle);
}
+ iret = cache_free(len, buf);
+ if (iret == 0)
+ return;
+
codec_mm_free_for_dma("dmx", buf);
}
unsigned int mem_size, int sec_level)
{
pr_dbg("%s mem_size:%d,sec_level:%d\n", __func__, mem_size, sec_level);
- _bufferid_malloc_desc_mem(pchan, mem_size, sec_level);
- return 0;
+ return _bufferid_malloc_desc_mem(pchan, mem_size, sec_level);
}
/**
pchan->enable = enable;
tmp = pchan->memdescs_phy & 0xFFFFFFFF;
- wdma_config_enable(pchan->id, enable, tmp, pchan->mem_size);
+ pr_dbg("WCH_ADDR, buffer id:%d, desc_phy:0x%x, addr:0x%x, length:%d\n",
+ pchan->id, tmp,
+ pchan->memdescs->bits.address,
+ pchan->memdescs->bits.byte_length);
+ //wdma_config_enable(pchan->id, enable, tmp, pchan->mem_size);
+ wdma_config_enable(pchan, enable, tmp, pchan->mem_size);
pr_dbg("######wdma start###########\n");
pr_dbg("err:0x%0x, active:%d\n", wdma_get_err(pchan->id),
tmp = (unsigned long)(pchan->memdescs) & 0xFFFFFFFF;
len = pchan->memdescs->bits.byte_length;
- rdma_config_enable(pchan->id, 1, tmp, count, len);
+ //rdma_config_enable(pchan->id, 1, tmp, count, len);
+ rdma_config_enable(pchan, 1, tmp, count, len);
pr_dbg("%s isphybuf\n", __func__);
/*it will exit write loop*/
r = len;
pchan->enable = 1;
tmp = pchan->memdescs_phy & 0xFFFFFFFF;
- rdma_config_enable(pchan->id, 1, tmp,
+ //rdma_config_enable(pchan->id, 1, tmp,
+ rdma_config_enable(pchan, 1, tmp,
pchan->mem_size, len);
}
pr_dbg("#######rdma##########\n");
/*disable */
- rdma_config_enable(pchan->id, 0, 0, 0, 0);
+ //rdma_config_enable(pchan->id, 0, 0, 0, 0);
+ rdma_config_enable(pchan, 0, 0, 0, 0);
rdma_clean(pchan->id);
p += len;
void _free_buff(unsigned long buf, unsigned int len, int sec_level,
unsigned int handle);
+int cache_status_info(char *buf);
+int cache_clear(void);
+int cache_adjust(int cache0_count, int cache1_count);
#endif
#include "demod_reg.h"
#include "dsc_reg.h"
#include "../dmx_log.h"
+#include "ts_output.h"
+#include "../aml_dvb.h"
+
+#include <linux/amlogic/tee_demux.h>
enum es_on_off {
EST_OFF = 0,
return READ_CBUS_REG(PID_RDY);
}
+static void tee_tsout_config_sid_table(u32 sid, u32 begin, u32 length)
+{
+#ifdef CONFIG_AMLOGIC_TEE
+ struct tee_dmx_sid_table_param param = {0};
+ int ret = -1;
+
+ pr_dbg("%s TEE sid:%d, pid begin:%d,len:%d\n",
+ __func__, sid, begin, length);
+
+ param.sid = sid;
+ param.begin = begin;
+ param.length = length;
+ ret = tee_demux_set(TEE_DMX_SET_SID_TABLE,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+#else
+ return;
+#endif
+}
+
void tsout_config_sid_table(u32 sid, u32 begin, u32 length)
{
u32 sid_reg_idx = sid / 2;
u32 sid_addr;
sid_addr = TS_OUT_SID_TAB_BASE + sid_reg_idx * 4;
- pr_dbg("%s read addr:0x%0x,sid:%d, pid begin:%d,len:%d\n",
- __func__, sid_addr, sid, begin, length);
+ pr_dbg("%s, read addr:0x%0x,sid:%d, pid begin:%d,len:%d\n",
+ __func__, sid_addr, sid, begin, length);
+
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_tsout_config_sid_table(sid, begin, length);
data = READ_CBUS_REG(sid_addr);
if (sid_offset == 0) {
WRITE_CBUS_REG(sid_addr, data);
}
+static void tee_tsout_config_ts_table(int pid,
+ u32 pid_mask, u32 pid_entry, u32 buffer_id)
+{
+#ifdef CONFIG_AMLOGIC_TEE
+ struct tee_dmx_ts_table_param param = {0};
+ int ret = -1;
+
+ pr_dbg("%s, TEE pid:0x%0x, mask:0x%0x, pid_entry:0x%0x, buf_id:%d\n",
+ __func__, pid, pid_mask, pid_entry, buffer_id);
+
+ param.pid = pid;
+ param.pid_mask = pid_mask;
+ param.pid_entry = pid_entry;
+ param.buffer_id = buffer_id;
+
+ ret = tee_demux_set(TEE_DMX_SET_TS_TABLE,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+#else
+ return;
+#endif
+}
+
void tsout_config_ts_table(int pid, u32 pid_mask, u32 pid_entry, u32 buffer_id)
{
union PID_CFG_FIELD cfg;
pr_dbg("%s,pid:0x%0x, mask:0x%0x, pid_entry:0x%0x, buf_id:%d\n",
__func__, pid, pid_mask, pid_entry, buffer_id);
+
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_tsout_config_ts_table(pid,
+ pid_mask, pid_entry, buffer_id);
+
cfg.data = 0;
data.data = 0;
if (pid == -1) {
} while (cfg.b.ap_pending);
}
+static void tee_tsout_config_es_table(u32 es_entry, int pid,
+ u32 sid, u32 reset, u32 dup_ok, u8 fmt)
+{
+#ifdef CONFIG_AMLOGIC_TEE
+ struct tee_dmx_es_table_param param = {0};
+ int ret = -1;
+
+ pr_dbg("%s TEE es_entry:%d, pid:0x%0x, sid:0x%0x,",
+ __func__, es_entry, pid, sid);
+ pr_dbg("reset:%d, dup_ok:%d, fmt:%d\n", reset, dup_ok, fmt);
+
+ param.es_entry = es_entry;
+ param.pid = pid;
+ param.sid = sid;
+ param.reset = reset;
+ param.dup_ok = dup_ok;
+ param.fmt = fmt;
+ ret = tee_demux_set(TEE_DMX_SET_ES_TABLE,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+#else
+ return;
+#endif
+}
+
void tsout_config_es_table(u32 es_entry, int pid,
u32 sid, u32 reset, u32 dup_ok, u8 fmt)
{
pr_dbg("%s es_entry:%d, pid:0x%0x, sid:0x%0x,",
__func__, es_entry, pid, sid);
pr_dbg("reset:%d, dup_ok:%d, fmt:%d\n", reset, dup_ok, fmt);
+
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_tsout_config_es_table(es_entry, pid,
+ sid, reset, dup_ok, fmt);
+
if (pid == -1) {
data.b.on_off = EST_OFF;
} else {
WRITE_CBUS_REG(TS_OUTPUT_ES_TAB(es_entry), data.data);
}
+static void tee_tsout_config_pcr_table(u32 pcr_entry, u32 pcr_pid, u32 sid)
+{
+#ifdef CONFIG_AMLOGIC_TEE
+ struct tee_dmx_pcr_table_param param = {0};
+
+ param.pcr_entry = pcr_entry;
+ param.pcr_pid = pcr_pid;
+ param.sid = sid;
+ tee_demux_set(TEE_DMX_SET_PCR_TABLE, (void *)¶m, sizeof(param));
+#else
+ return;
+#endif
+}
+
void tsout_config_pcr_table(u32 pcr_entry, u32 pcr_pid, u32 sid)
{
union PCR_TAB_FIELD data;
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_tsout_config_pcr_table(pcr_entry, pcr_pid, sid);
data.data = 0;
if (pcr_pid != -1) {
pr_dbg("%s data.data:0x%0x\n", __func__, data.data);
}
+static int tee_tsout_config_get_pcr(u32 pcr_entry, u64 *pcr)
+{
+ return tee_demux_get(TEE_DMX_GET_PCR,
+ &pcr_entry, sizeof(pcr_entry), pcr, sizeof(*pcr));
+}
+
int tsout_config_get_pcr(u32 pcr_entry, u64 *pcr)
{
union PCR_REG_LSB_FIELD lsb;
union PCR_REG_MSB_FIELD msb;
u64 data = 0;
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_tsout_config_get_pcr(pcr_entry, pcr);
+
lsb.data = READ_CBUS_REG(TS_OUTPUT_PCR_REG_LSB(pcr_entry));
msb.data = READ_CBUS_REG(TS_OUTPUT_PCR_REG_MSB(pcr_entry));
WRITE_CBUS_REG(TSE_PID_READY, 1);
}
-//unsigned int dsc_get_pid_status(int dsc_type)
-//{
-//}
+static void tee_dsc_config_pid_table(struct dsc_pid_table *pid_entry,
+ int dsc_type)
+{
+#ifdef CONFIG_AMLOGIC_TEE
+ struct tee_dmx_pid_table_param param = {0};
+ int ret = -1;
+
+ pr_dbg("%s dsc_type:%d, pid_entry:%d, pid:%d\n",
+ __func__, dsc_type, pid_entry->id, pid_entry->pid);
+ param.type = dsc_type;
+ param.id = pid_entry->id;
+ param.table.bits.valid = pid_entry->valid;
+ //param.table.bits.resv0 = pid_entry->valid;
+ //param.table.bits.resv1 = pid_entry->valid;
+ param.table.bits.scb00 = pid_entry->scb00;
+ param.table.bits.scb_out = pid_entry->scb_out;
+ param.table.bits.scb_as_is = pid_entry->scb_as_is;
+ param.table.bits.odd_iv = pid_entry->odd_iv;
+ param.table.bits.even_00_iv = pid_entry->even_00_iv;
+ param.table.bits.sid = pid_entry->sid;
+ param.table.bits.pid = pid_entry->pid;
+ param.table.bits.algo = pid_entry->algo;
+ param.table.bits.kte_odd = pid_entry->kte_odd;
+ param.table.bits.kte_even_00 = pid_entry->kte_even_00;
+ //memcpy(¶m.table, pid_entry, sizeof(struct dsc_pid_table));
+ ret = tee_demux_set(TEE_DMX_SET_PID_TABLE,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+ dsc_get_ready(dsc_type);
+ dsc_config_ready(dsc_type);
+#else
+ return;
+#endif
+}
void dsc_config_pid_table(struct dsc_pid_table *pid_entry, int dsc_type)
{
pr_dbg("%s dsc_type:%d, pid_entry:%d, sid:%d\n",
__func__, dsc_type, pid_entry->id, pid_entry->sid);
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ return tee_dsc_config_pid_table(pid_entry, dsc_type);
dsc_get_ready(dsc_type);
+
if (dsc_type == CA_DSC_COMMON_TYPE) {
lo_addr = TSN_BASE_ADDR + pid_entry->id * 8;
hi_addr = TSN_BASE_ADDR + pid_entry->id * 8 + 4;
dsc_config_ready(dsc_type);
}
-void rdma_config_enable(u8 chan_id, int enable,
+//void rdma_config_enable(u8 chan_id, int enable,
+void rdma_config_enable(struct chan_id *pchan, int enable,
unsigned int desc, unsigned int total_size,
unsigned int len)
{
u32 data = 0;
if (enable) {
- WRITE_CBUS_REG(TS_DMA_RCH_ADDR(chan_id), desc);
- WRITE_CBUS_REG(TS_DMA_RCH_LEN(chan_id), len);
+ WRITE_CBUS_REG(TS_DMA_RCH_ADDR(pchan->id), desc);
+ WRITE_CBUS_REG(TS_DMA_RCH_LEN(pchan->id), len);
pr_dbg("%s desc:0x%0x\n", __func__, desc);
pr_dbg("%s total_size:0x%0x\n", __func__, len);
data = 188 << RCH_CFG_READ_LEN;
data |= 188 << RCH_CFG_PACKET_LEN;
data |= 1 << RCH_CFG_ENABLE;
- WRITE_CBUS_REG(TS_DMA_RCH_EACH_CFG(chan_id), data);
+ WRITE_CBUS_REG(TS_DMA_RCH_EACH_CFG(pchan->id), data);
pr_dbg("%s addr:0x%0x data:0x%0x\n", __func__,
- TS_DMA_RCH_EACH_CFG(chan_id), data);
+ TS_DMA_RCH_EACH_CFG(pchan->id), data);
+ pr_dbg("%s, output address:0x%x, len:%d\n", __func__,
+ pchan->memdescs->bits.address,
+ pchan->memdescs->bits.byte_length);
} else {
- data = READ_CBUS_REG(TS_DMA_RCH_EACH_CFG(chan_id));
+ data = READ_CBUS_REG(TS_DMA_RCH_EACH_CFG(pchan->id));
data &= ~(1 << RCH_CFG_ENABLE);
- WRITE_CBUS_REG(TS_DMA_RCH_EACH_CFG(chan_id), data);
+ WRITE_CBUS_REG(TS_DMA_RCH_EACH_CFG(pchan->id), data);
pr_dbg("%s data:0x%0x\n", __func__, data);
}
}
WRITE_CBUS_REG(TS_DMA_WCH_READY(chan_id), 1);
}
-void wdma_config_enable(u8 chan_id, int enable,
+//void wdma_config_enable(u8 chan_id, int enable,
+void wdma_config_enable(struct chan_id *pchan, int enable,
unsigned int desc, unsigned int total_size)
{
int times = 0;
unsigned int cnt = 0;
+ struct tee_dmx_dma_desc_param param = {0};
+#ifdef CONFIG_AMLOGIC_TEE
+ int ret = -1;
+#endif
if (enable) {
do {
- } while (!wdma_get_ready(chan_id) && times++ < 20);
-
- wdma_clean(chan_id);
-
- WRITE_CBUS_REG(TS_DMA_WCH_ADDR(chan_id), desc);
- WRITE_CBUS_REG(TS_DMA_WCH_LEN(chan_id), total_size);
-
+ } while (!wdma_get_ready(pchan->id) && times++ < 20);
+
+ wdma_clean(pchan->id);
+
+ param.address = pchan->memdescs->bits.address;
+ param.len = pchan->memdescs->bits.byte_length;
+ param.buffer_id = pchan->id;
+#ifdef CONFIG_AMLOGIC_TEE
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ ret = tee_demux_set(TEE_DMX_SET_DMA_DESC,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+
+#endif
+ WRITE_CBUS_REG(TS_DMA_WCH_ADDR(pchan->id), desc);
+ WRITE_CBUS_REG(TS_DMA_WCH_LEN(pchan->id), total_size);
+
+ pr_dbg("%s, output address:0x%x, len:%d\n", __func__,
+ pchan->memdescs->bits.address,
+ pchan->memdescs->bits.byte_length);
pr_dbg("%s desc:0x%0x\n", __func__, desc);
pr_dbg("%s total_size:0x%0x\n", __func__, total_size);
} else {
// unsigned int data;
-// data = READ_CBUS_REG(TS_DMA_WCH_CFG(chan_id));
+// data = READ_CBUS_REG(TS_DMA_WCH_CFG(pchan->id));
// data |= (1 << WCH_CFG_CLEAR);
-// WRITE_CBUS_REG(TS_DMA_WCH_CFG(chan_id), data);
- WRITE_CBUS_REG(TS_DMA_WCH_ADDR(chan_id), 0);
- WRITE_CBUS_REG(TS_DMA_WCH_LEN(chan_id), 0);
+// WRITE_CBUS_REG(TS_DMA_WCH_CFG(pchan->id), data);
+
+ param.address = 0;
+ param.len = 0;
+ param.buffer_id = pchan->id;
+#ifdef CONFIG_AMLOGIC_TEE
+ if (is_security_dmx == TEE_DMX_ENABLE)
+ ret = tee_demux_set(TEE_DMX_SET_DMA_DESC,
+ (void *)¶m, sizeof(param));
+ pr_dbg("[demux] %s ret:%d\n", __func__, ret);
+
+#endif
+ WRITE_CBUS_REG(TS_DMA_WCH_ADDR(pchan->id), 0);
+ WRITE_CBUS_REG(TS_DMA_WCH_LEN(pchan->id), 0);
/*if dmx have cmd completed, need delay,
* or clean will cause
* demod enter overflow status,
* it can't resolve except reboot
*/
- cnt = wdma_get_wcmdcnt(chan_id);
+ cnt = wdma_get_wcmdcnt(pchan->id);
if (cnt)
msleep(20);
- wdma_clean(chan_id);
+ wdma_clean(pchan->id);
//delay
// while (times ++ < 500);
pr_dbg("%s wptr:0x%0x\n", __func__,
- READ_CBUS_REG(TS_DMA_WCH_WR_LEN(chan_id)));
- wdam_config_ready(chan_id);
+ READ_CBUS_REG(TS_DMA_WCH_WR_LEN(pchan->id)));
+ wdam_config_ready(pchan->id);
}
}
pr_dbg("%s data:0x%0x\n", __func__, data);
}
+void demod_config_fifo(u8 port, u16 fifo_th)
+{
+ unsigned int data = 0;
+
+ data = READ_CBUS_REG(DEMOD_FIFO_CFG(port));
+ if (port % 2 == 0)
+ data = (data & 0xFFFF0000) | fifo_th;
+ else
+ data = (data & 0xFFFF) | (fifo_th << 16);
+
+ WRITE_CBUS_REG(DEMOD_FIFO_CFG(port), data);
+ pr_dbg("%s data:0x%0x\n", __func__, data);
+}
+
void demod_config_tsin_invert(u8 port, u8 invert)
{
unsigned int data = 0;
data |= (0x1 << FEC_S2P_3WIRE);
if (port == DEMOD_FEC_B)
data |= DEMOD_1_SERIAL << TS_S_OR_P_SEL1;
+ else if (port == DEMOD_FEC_A)
+ data |= DEMOD_1_SERIAL << TS_S_OR_P_SEL1;
+
} else if (wire_type == DEMOD_4WIRE) {
data |= 1 << FEC_S2P_SEL;
data |= (0 << FEC_S2P_3WIRE);
if (port == DEMOD_FEC_B)
data |= DEMOD_1_SERIAL << TS_S_OR_P_SEL1;
+ else if (port == DEMOD_FEC_A)
+ data |= DEMOD_1_SERIAL << TS_S_OR_P_SEL1;
} else {
- if (port == DEMOD_FEC_B)
+ if (port == DEMOD_FEC_B || port == DEMOD_FEC_C)
data |= DEMOD_1_PARALLEL << TS_S_OR_P_SEL1;
else
return;
#ifndef _SC2_CONTROL_H_
#define _SC2_CONTROL_H_
+#include "mem_desc.h"
struct dsc_pid_table {
int id;
/*****************************************************/
/*****************************************************/
/*****************************************************/
-void rdma_config_enable(u8 chan_id, int enable,
+//void rdma_config_enable(u8 chan_id, int enable,
+void rdma_config_enable(struct chan_id *pchan, int enable,
unsigned int desc, unsigned int total_size,
unsigned int len);
void rdma_config_ready(u8 chan_id);
/*****************************************************/
/*****************************************************/
void wdma_clean(u8 chan_id);
-void wdma_config_enable(u8 chan_id, int enable,
+//void wdma_config_enable(u8 chan_id, int enable,
+void wdma_config_enable(struct chan_id *pchan, int enable,
unsigned int desc, unsigned int total_size);
void wdam_config_ready(u8 chan_id);
unsigned int wdma_get_wptr(u8 chan_id);
/*bit0: set 1 to invert input clk signal*/
void demod_config_tsin_invert(u8 port, u8 invert);
void demod_config_in(u8 port, u8 wire_type);
-
+void demod_config_fifo(u8 port, u16 fifo_th);
/*****************************************************/
/*****************************************************/
/*****************************************************/
struct in_elem {
__u8 used;
__u8 mem_level;
+ __u8 id;
struct chan_id *pchan;
};
return NULL;
ts_input_table[id].mem_level = sec_level;
+ ts_input_table[id].id = id;
ts_input_table[id].used = 1;
elem = &ts_input_table[id];
if (SC2_bufferid_set_mem(elem->pchan,
- TS_INPUT_BUFF_SIZE, sec_level) != 0)
+ TS_INPUT_BUFF_SIZE, sec_level) != 0) {
+ SC2_bufferid_dealloc(ts_input_table[id].pchan);
+ ts_input_table[id].used = 0;
dprint("input id:%d, malloc fail\n", id);
-
+ return NULL;
+ }
pr_dbg("%s line:%d\n", __func__, __LINE__);
return elem;
}
{
if (elem && elem->pchan)
SC2_bufferid_dealloc(elem->pchan);
- elem->used = 0;
+ if (elem)
+ elem->used = 0;
return 0;
}
{
int ret = 0;
- pr_dbg("%s line:%d\n", __func__, __LINE__);
-
- if (elem && elem->mem_level && count > TS_INPUT_DESC_MAX_SIZE)
+ if (!elem)
return -1;
- pr_dbg("%s line:%d\n", __func__, __LINE__);
-
if (!elem->pchan || !buf) {
pr_dbg("%s invalid parameter line:%d\n", __func__, __LINE__);
return 0;
}
+ pr_dbg("%s id:%d count:%d\n", __func__, elem->id, count);
+
ret = SC2_bufferid_write(elem->pchan,
buf, count, elem->mem_level ? 1 : 0);
return ret;
struct es_params_t {
struct dmx_non_sec_es_header header;
+ char last_last_header[16];
char last_header[16];
u8 have_header;
u8 have_send_header;
unsigned long data_start;
unsigned int data_len;
int es_overflow;
+ int es_error_cn;
+ u32 header_wp;
};
struct ts_out {
u8 id;
u8 format;
u8 ref;
+ u8 demux_id;
ts_output_cb cb;
void *udata[MAX_FEED_NUM];
struct cb_entry *next;
continue;
}
if (ptmp->pout->format == ES_FORMAT) {
- pr_dbg("get %s data\n",
- ptmp->pout->type == AUDIO_TYPE ?
- "audio" : "video");
+// pr_dbg("get %s data\n",
+// ptmp->pout->type == AUDIO_TYPE ?
+// "audio" : "video");
do {
ret =
_handle_es(ptmp->pout,
ptmp->es_params);
} while (ret == 0);
- pr_dbg("get %s data done\n",
- ptmp->pout->type == AUDIO_TYPE ?
- "audio" : "video");
+// pr_dbg("get %s data done\n",
+// ptmp->pout->type == AUDIO_TYPE ?
+// "audio" : "video");
}
ptmp = ptmp->pnext;
}
unsigned int last_es_bytes = 0;
// pr_dbg("%s enter\n", __func__);
+// pr_dbg("%s pid:0x%0x\n", __func__, pout->es_pes->pid);
header_len = 16;
offset = 0;
pr_dbg("%s len:%d,cur_es_bytes:0x%0x, last_es_bytes:0x%0x\n",
__func__, pheader->len, cur_es_bytes, last_es_bytes);
- pr_dbg("%s exit\n", __func__);
+ pr_dbg("%s pid:0x%0x\n", __func__, pout->es_pes->pid);
+
return 0;
}
int ret;
int flag = 0;
+ pr_dbg("%s pid:0x%0x enter\n", __func__, pout->es_pes->pid);
if (es_params->header.len == 0)
return -1;
ret = SC2_bufferid_read(pout->pchan, &ptmp, len, flag);
if (ret == 0)
return -1;
+
if (es_params->data_start == 0)
es_params->data_start = (unsigned long)ptmp;
}
if (ret != len) {
- if (pout->pchan->r_offset != 0)
- return -1;
+// if (pout->pchan->r_offset != 0)
+// return -1;
+
/*if loop back , read one time */
len = es_params->header.len - es_params->data_len;
ret = SC2_bufferid_read(pout->pchan, &ptmp, len, flag);
- es_params->data_len += ret;
-
- if (pout->dump_file.file_fp) {
- if (flag) {
- enforce_flush_cache(ptmp, ret);
- dump_file_write(
- ptmp - pout->pchan->mem_phy +
- pout->pchan->mem, ret,
- &pout->dump_file);
- } else {
- dump_file_write(ptmp, ret,
- &pout->dump_file);
+ if (ret != 0) {
+ es_params->data_len += ret;
+
+ if (pout->dump_file.file_fp) {
+ if (flag) {
+ enforce_flush_cache(ptmp, ret);
+ dump_file_write(ptmp -
+ pout->pchan->mem_phy +
+ pout->pchan->mem, ret,
+ &pout->dump_file);
+ } else {
+ dump_file_write(ptmp, ret,
+ &pout->dump_file);
+ }
}
+ if (ret != len)
+ dprint("get es len err2, req:%d, actual:%d\n",
+ es_params->header.len,
+ es_params->data_len);
+ } else {
+ len = es_params->data_len;
+ dprint("get es len err1, req:%d, actual:%d\n",
+ es_params->header.len,
+ es_params->data_len);
}
-
- if (ret != len)
- return -1;
}
memset(&sec_es_data, 0, sizeof(struct dmx_sec_es_data));
sec_es_data.pts_dts_flag = es_params->header.pts_dts_flag;
sec_es_data.data_start, sec_es_data.data_end,
(sec_es_data.data_end - sec_es_data.data_start));
else
- pr_err("video data start:0x%x,data end:0x%x\n",
+ pr_dbg("video data start:0x%x,data end:0x%x\n",
sec_es_data.data_start, sec_es_data.data_end);
- if (sec_es_data.data_start > sec_es_data.buf_end)
- pr_err("video data start:0x%x, buf end:0x%x\n",
- sec_es_data.data_start, sec_es_data.buf_end);
-
- pr_dbg("video pdts_flag:%d, pts:0x%lx, dts:0x%lx, offset:0x%lx\n",
+ pr_dbg("video pid:0x%0x sid:0x%0x flag:%d, pts:0x%lx, dts:0x%lx, offset:0x%lx\n",
+ pout->es_pes->pid,
+ pout->sid,
sec_es_data.pts_dts_flag,
(unsigned long)sec_es_data.pts,
(unsigned long)sec_es_data.dts,
else
ret = clean_es_data(pout,
pout->pchan, dirty_len);
+ memcpy(&es_params->last_last_header,
+ &es_params->last_header, 16);
memcpy(&es_params->last_header, pcur_header,
sizeof(es_params->last_header));
+ dprint("error: clean dirty len:0x%0x\n", dirty_len);
return 0;
}
if (pheader->len == 0) {
+ memcpy(&es_params->last_last_header,
+ &es_params->last_header, 16);
+ memcpy(&es_params->last_header, pcur_header,
+ sizeof(es_params->last_header));
+ dprint("error: header.len is 0, jump\n");
+ return 0;
+ } else if (pheader->len >= pout->pchan->mem_size) {
+ memcpy(&es_params->last_last_header,
+ &es_params->last_header, 16);
memcpy(&es_params->last_header, pcur_header,
sizeof(es_params->last_header));
- pr_dbg("header.len is 0, jump\n");
+ es_params->header_wp =
+ SC2_bufferid_get_wp_offset(pout->pchan1);
+ dprint("error: es len: 0x%0x\n", pheader->len);
+ es_params->es_error_cn++;
return 0;
}
+ memcpy(&es_params->last_last_header,
+ &es_params->last_header, 16);
memcpy(&es_params->last_header, pcur_header,
sizeof(es_params->last_header));
es_params->have_header = 1;
}
+ if (debug_ts_output == 2 && es_params->es_error_cn) {
+ int cn = 0;
+ dprint("##############pid:0x%0x\n",
+ pout->es_pes->pid);
+ dprint("es_params header:%d\n", es_params->have_header);
+ dprint("es_params have_send_header:%d\n",
+ es_params->have_send_header);
+ dprint("es_params data_len:%d\n", es_params->data_len);
+ dprint("es_params header len:0x%0x\n", es_params->header.len);
+ dprint("es_params es_error_cn:%d\n", es_params->es_error_cn);
+ dprint("es_params header_wp:0x%0x\n", es_params->header_wp);
+
+ dprint("get last header:\n");
+ for (cn = 0; cn < 16; cn++)
+ dprint("0x%0x ", es_params->last_header[cn]);
+
+ dprint("get last last header:\n");
+ for (cn = 0; cn < 16; cn++)
+ dprint("0x%0x ", es_params->last_last_header[cn]);
+
+ dprint("\n#########################\n");
+ }
if (pout->output_mode || pout->pchan->sec_level) {
+ if (es_params->have_header == 0)
+ return -1;
+
if (pout->type == VIDEO_TYPE) {
ret = write_sec_video_es_data(pout, es_params);
} else {
struct pid_entry *pid_slot = NULL;
struct es_entry *es_pes = NULL;
+ if (!pout)
+ return -1;
+
if (cb_id)
*cb_id = 0;
tsout_config_es_table(es_pes->buff_id, es_pes->pid,
pout->sid, 1, !drop_dup, pout->format);
} else {
+ if (cb_id)
+ *cb_id = dmx_id;
pid_slot = pout->pid_list;
while (pid_slot) {
if (pid_slot->pid == pid) {
int ts_output_set_mem(struct out_elem *pout, int memsize,
int sec_level, int pts_memsize, int pts_level)
{
+ int ret = 0;
pr_dbg("%s mem size:0x%0x, pts_memsize:0x%0x, sec_level:%d\n",
__func__, memsize, pts_memsize, sec_level);
- if (pout && pout->pchan)
- SC2_bufferid_set_mem(pout->pchan, memsize, sec_level);
-
- if (pout && pout->pchan1)
- SC2_bufferid_set_mem(pout->pchan1, pts_memsize, pts_level);
-
+ if (pout && pout->pchan) {
+ ret = SC2_bufferid_set_mem(pout->pchan, memsize, sec_level);
+ if (ret != 0)
+ return -1;
+ }
+ if (pout && pout->pchan1) {
+ ret = SC2_bufferid_set_mem(pout->pchan1,
+ pts_memsize, pts_level);
+ if (ret != 0)
+ return -1;
+ }
return 0;
}
* \param cb_id:cb_id
* \param format:format
* \param is_sec: is section callback
+ * \param demux_id:dmx id
* \retval 0:success.
* \retval -1:fail.
*/
int ts_output_add_cb(struct out_elem *pout, ts_output_cb cb, void *udata,
- u8 cb_id, u8 format, bool is_sec)
+ u8 cb_id, u8 format, bool is_sec, u8 demux_id)
{
struct cb_entry *tmp_cb = NULL;
tmp_cb->format = format;
tmp_cb->ref = 0;
tmp_cb->id = cb_id;
+ tmp_cb->demux_id = demux_id;
if (is_sec) {
tmp_cb->next = pout->cb_sec_list;
/*remove the free feed*/
for (i = 0; i <= tmp_cb->ref && i < MAX_FEED_NUM; i++) {
if (tmp_cb->udata[i] == udata) {
- for (j = i; j < tmp_cb->ref && j < MAX_FEED_NUM; j++)
+ for (j = i; j < tmp_cb->ref && j < MAX_FEED_NUM - 1;
+ j++)
tmp_cb->udata[j] = tmp_cb->udata[j + 1];
}
}
unsigned int free_size = 0;
unsigned int wp_offset = 0;
struct pid_entry *pid_list;
+ struct cb_entry *tmp_cb = NULL;
if (pout->used && pout->format == DVR_FORMAT) {
+ tmp_cb = pout->cb_ts_list;
+
r = sprintf(buf, "%d sid:0x%0x ref:%d ",
count, pout->sid, pout->ref);
buf += r;
total += r;
+ r = sprintf(buf, "dmx_id ");
+ buf += r;
+ total += r;
+
+ while (tmp_cb) {
+ r = sprintf(buf, "%d ", tmp_cb->demux_id);
+ buf += r;
+ total += r;
+
+ tmp_cb = tmp_cb->next;
+ }
+
ts_output_get_mem_info(pout,
&total_size,
&buf_phy_start,
total += r;
r = sprintf(buf,
- "free size:0x%0x, wp:0x%0x\n",
- free_size, wp_offset);
+ "free size:0x%0x, rp:0x%0x, wp:0x%0x\n",
+ free_size, pout->pchan->r_offset,
+ wp_offset);
buf += r;
total += r;
total += r;
r = sprintf(buf,
- "free size:0x%0x, wp:0x%0x\n",
- free_size, wp_offset);
+ "free size:0x%0x, rp:0x%0x, wp:0x%0x\n",
+ free_size, es_slot->pout->pchan->r_offset,
+ wp_offset);
buf += r;
total += r;
total += r;
r = sprintf(buf,
- "free size:0x%0x, wp:0x%0x, ",
- free_size, wp_offset);
+ "free size:0x%0x, rp:0x%0x, wp:0x%0x, ",
+ free_size, es_slot->pout->pchan->r_offset,
+ wp_offset);
buf += r;
total += r;
unsigned int buf_phy_start = 0;
unsigned int free_size = 0;
unsigned int wp_offset = 0;
+ struct cb_entry *tmp_cb = NULL;
+ struct out_elem *pout = NULL;
if (es_slot->used && es_slot->status == SECTION_FORMAT) {
- r = sprintf(buf, "%d dmxid:%d sid:0x%0x ",
- count, es_slot->dmx_id, es_slot->pout->sid);
+ pout = es_slot->pout;
+ tmp_cb = pout->cb_sec_list;
+
+ r = sprintf(buf, "%d dmx_id:", count);
+ buf += r;
+ total += r;
+
+ while (tmp_cb) {
+ r = sprintf(buf, "%d ", tmp_cb->demux_id);
+ buf += r;
+ total += r;
+
+ tmp_cb = tmp_cb->next;
+ }
+
+ r = sprintf(buf, "sid:0x%0x ", es_slot->pout->sid);
buf += r;
total += r;
return total;
}
+
+static void update_dvr_sid(struct out_elem *pout, int sid, int dmx_no)
+{
+ struct pid_entry *head_pid_slot = NULL;
+ struct pid_entry *prev_pid_slot = NULL;
+ struct pid_entry *new_pid_slot = NULL;
+ struct pid_entry *pid_slot = NULL;
+
+ pout->sid = sid;
+ pid_slot = pout->pid_list;
+ while (pid_slot) {
+ dprint("change dmx id:%d, dvr dmx filter sid:0x%0x, pid:0x%0x\n",
+ dmx_no, pout->sid, pid_slot->pid);
+ /*free slot*/
+ tsout_config_ts_table(-1, pid_slot->pid_mask,
+ pid_slot->id, pout->pchan->id);
+
+ /*remalloc slot and */
+ new_pid_slot = _malloc_pid_entry_slot(pout->sid, pid_slot->pid);
+ if (!new_pid_slot) {
+ pr_dbg("malloc pid entry fail\n");
+ _free_pid_entry_slot(pid_slot);
+ pid_slot = pid_slot->pnext;
+ return;
+ }
+ new_pid_slot->pid = pid_slot->pid;
+ new_pid_slot->pid_mask = pid_slot->pid_mask;
+ new_pid_slot->used = 1;
+ new_pid_slot->dmx_id = pid_slot->dmx_id;
+ new_pid_slot->ref = pid_slot->ref;
+ new_pid_slot->pout = pout;
+
+ if (!head_pid_slot)
+ head_pid_slot = new_pid_slot;
+ else
+ prev_pid_slot->pnext = new_pid_slot;
+
+ prev_pid_slot = new_pid_slot;
+ tsout_config_ts_table(new_pid_slot->pid,
+ new_pid_slot->pid_mask,
+ new_pid_slot->id,
+ pout->pchan->id);
+
+ _free_pid_entry_slot(pid_slot);
+ pid_slot = pid_slot->pnext;
+ }
+ pout->pid_list = head_pid_slot;
+}
+
+int ts_output_update_filter(int dmx_no, int sid)
+{
+ int i = 0;
+
+ /*update dvr filter*/
+ for (i = 0; i < MAX_OUT_ELEM_NUM; i++) {
+ struct out_elem *pout = &out_elem_table[i];
+ u8 flag = 0;
+
+ if (pout->used && pout->format == DVR_FORMAT) {
+ struct cb_entry *tmp_cb = pout->cb_ts_list;
+
+ while (tmp_cb) {
+ if (tmp_cb->demux_id == dmx_no) {
+ flag = 1;
+ break;
+ }
+ tmp_cb = tmp_cb->next;
+ }
+ if (flag)
+ update_dvr_sid(pout, sid, dmx_no);
+ }
+ }
+ /*update es table filter*/
+ for (i = 0; i < MAX_ES_NUM; i++) {
+ struct es_entry *es_slot = &es_table[i];
+ struct out_elem *pout = NULL;
+ u8 flag = 0;
+
+ if (es_slot->used) {
+ struct cb_entry *tmp_cb = NULL;
+ pout = es_slot->pout;
+
+ if (es_slot->status == ES_FORMAT || es_slot->status == PES_FORMAT)
+ tmp_cb = pout->cb_ts_list;
+ else if (es_slot->status == SECTION_FORMAT)
+ tmp_cb = pout->cb_sec_list;
+
+ while (tmp_cb) {
+ if (tmp_cb->demux_id == dmx_no) {
+ flag = 1;
+ break;
+ }
+ tmp_cb = tmp_cb->next;
+ }
+
+ if (flag) {
+ pout->sid = sid;
+ dprint("change dmx id:%d, filter sid:0x%0x, pid:0x%0x\n",
+ dmx_no, pout->sid, es_slot->pid);
+ tsout_config_es_table(es_slot->buff_id, es_slot->pid,
+ pout->sid, 1, !drop_dup, pout->format);
+ }
+ }
+ }
+ return 0;
+}
+
* \param dmx_id:dmx_id
* \param format:format
* \param is_sec: is section callback
+ * \param demux_id:dmx id
* \retval 0:success.
* \retval -1:fail.
*/
int ts_output_add_cb(struct out_elem *pout, ts_output_cb cb, void *udata,
- u8 dmx_id, u8 format, bool is_sec);
+ u8 dmx_id, u8 format, bool is_sec, u8 demux_id);
/**
* remove callback for getting data
int ts_output_sid_debug(void);
int ts_output_dump_info(char *buf);
+int ts_output_update_filter(int dmx_no, int sid);
+
#endif
unsigned char buf[sizeof(struct esm_ioc_data) + 1];
} u;
- if (copy_from_user(&u.data, arg, sizeof(u.buf)) != 0)
+ if (copy_from_user(&u.data, arg, sizeof(u.data)) != 0)
return -EFAULT;
if (esm->data_size < u.data.len)
+++ /dev/null
-/*
- * drivers/amlogic/hifi4dsp/hifi4dsp_ipc.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/wait.h>
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/kthread.h>
-#include <linux/amlogic/major.h>
-
-#include "hifi4dsp_priv.h"
-#include "hifi4dsp_firmware.h"
-#include "hifi4dsp_dsp.h"
-#include "hifi4dsp_ipc.h"
-
-/* locks held by caller */
-static struct hifi4dsp_ipc_message *ipc_get_empty_msg(
- struct hifi4dsp_ipc *ipc)
-{
- struct hifi4dsp_ipc_message *msg = NULL;
-
- if (!list_empty(&ipc->empty_list)) {
- msg = list_first_entry(&ipc->empty_list,
- struct hifi4dsp_ipc_message, list);
- list_del(&msg->list);
- }
-
- return msg;
-}
-
-static int tx_wait_done(struct hifi4dsp_ipc *ipc,
- struct hifi4dsp_ipc_message *msg, void *rx_data)
-{
- unsigned long flags;
- int ret;
-
- /* wait for DSP completion (in all cases atm inc pending) */
- ret = wait_event_timeout(msg->waitq, msg->complete,
- msecs_to_jiffies(IPC_MSG_TIMEOUT_MSECS));
-
- spin_lock_irqsave(&ipc->dsp->spinlock, flags);
- if (ret == 0) {
- if (ipc->ops.debug_info != NULL)
- ipc->ops.debug_info(ipc, "message timeout");
-
- list_del(&msg->list);
- ret = -ETIMEDOUT;
- } else {
-
- /* copy the data returned from DSP */
- if (msg->rx_size)
- memcpy(rx_data, msg->rx_data, msg->rx_size);
- ret = msg->errno;
- }
-
- list_add_tail(&msg->list, &ipc->empty_list);
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
- return ret;
-}
-
-static int ipc_tx_message(struct hifi4dsp_ipc *ipc, u64 header,
- void *tx_data, size_t tx_bytes, void *rx_data,
- size_t rx_bytes, int wait)
-{
- struct hifi4dsp_ipc_message *msg;
- unsigned long flags;
-
- spin_lock_irqsave(&ipc->dsp->spinlock, flags);
-
- msg = ipc_get_empty_msg(ipc);
- if (msg == NULL) {
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
- return -EBUSY;
- }
-
- msg->header = header;
- msg->tx_size = tx_bytes;
- msg->rx_size = rx_bytes;
- msg->wait = wait;
- msg->errno = 0;
- msg->pending = false;
- msg->complete = false;
-
- if ((tx_bytes) && (ipc->ops.tx_data_copy != NULL))
- ipc->ops.tx_data_copy(msg, tx_data, tx_bytes);
-
- list_add_tail(&msg->list, &ipc->tx_list);
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
-
- kthread_queue_work(&ipc->kworker, &ipc->kwork);
-
- if (wait)
- return tx_wait_done(ipc, msg, rx_data);
- else
- return 0;
-}
-
-static int ipc_msg_empty_list_init(struct hifi4dsp_ipc *ipc)
-{
- int i;
-
- ipc->msg = kzalloc(sizeof(struct hifi4dsp_ipc_message) *
- IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
- if (ipc->msg == NULL)
- return -ENOMEM;
-
- for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
- ipc->msg[i].tx_data = kzalloc
- (ipc->tx_data_max_size, GFP_KERNEL);
- if (ipc->msg[i].tx_data == NULL)
- goto free_mem;
-
- ipc->msg[i].rx_data = kzalloc
- (ipc->rx_data_max_size, GFP_KERNEL);
- if (ipc->msg[i].rx_data == NULL) {
- kfree(ipc->msg[i].tx_data);
- goto free_mem;
- }
-
- init_waitqueue_head(&ipc->msg[i].waitq);
- list_add(&ipc->msg[i].list, &ipc->empty_list);
- }
-
- return 0;
-
-free_mem:
- while (i > 0) {
- kfree(ipc->msg[i-1].tx_data);
- kfree(ipc->msg[i-1].rx_data);
- --i;
- }
- kfree(ipc->msg);
-
- return -ENOMEM;
-}
-
-static void ipc_tx_msgs(struct kthread_work *work)
-{
- struct hifi4dsp_ipc *ipc =
- container_of(work, struct hifi4dsp_ipc, kwork);
- struct hifi4dsp_ipc_message *msg;
- unsigned long flags;
-
- spin_lock_irqsave(&ipc->dsp->spinlock, flags);
-
- if (list_empty(&ipc->tx_list) || ipc->pending) {
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
- return;
- }
-
- /* if the DSP is busy, we will TX messages after IRQ.
- * also postpone if we are in the middle of procesing completion irq
- */
- if (ipc->ops.is_dsp_busy && ipc->ops.is_dsp_busy(ipc->dsp)) {
- pr_err("ipc_tx_msgs dsp busy\n");
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
- return;
- }
-
- msg = list_first_entry(&ipc->tx_list,
- struct hifi4dsp_ipc_message, list);
- list_move(&msg->list, &ipc->rx_list);
-
- if (ipc->ops.tx_msg != NULL)
- ipc->ops.tx_msg(ipc, msg);
-
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
-}
-
-int hifi4dsp_ipc_tx_message_wait(struct hifi4dsp_ipc *ipc, u64 header,
- void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
-{
- return ipc_tx_message(ipc, header, tx_data, tx_bytes,
- rx_data, rx_bytes, 1);
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_tx_message_wait);
-
-int hifi4dsp_ipc_tx_message_nowait(struct hifi4dsp_ipc *ipc, u64 header,
- void *tx_data, size_t tx_bytes)
-{
- return ipc_tx_message(ipc, header, tx_data, tx_bytes,
- NULL, 0, 0);
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_tx_message_nowait);
-
-struct hifi4dsp_ipc_message *hifi4dsp_ipc_reply_find_msg(
- struct hifi4dsp_ipc *ipc, u64 header)
-{
- struct hifi4dsp_ipc_message *msg;
- u64 mask = 0;
-
- if (ipc->ops.reply_msg_match != NULL)
- header = ipc->ops.reply_msg_match(header, &mask);
-
- if (list_empty(&ipc->rx_list)) {
- pr_err("error: rx list empty but received 0x%llx\n",
- header);
- return NULL;
- }
-
- list_for_each_entry(msg, &ipc->rx_list, list) {
- if ((msg->header & mask) == header)
- return msg;
- }
-
- return NULL;
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_reply_find_msg);
-
-/* locks held by caller */
-void hifi4dsp_ipc_tx_msg_reply_complete(struct hifi4dsp_ipc *ipc,
- struct hifi4dsp_ipc_message *msg)
-{
- msg->complete = true;
-
- if (!msg->wait)
- list_add_tail(&msg->list, &ipc->empty_list);
- else
- wake_up(&msg->waitq);
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_tx_msg_reply_complete);
-
-void hifi4dsp_ipc_drop_all(struct hifi4dsp_ipc *ipc)
-{
- struct hifi4dsp_ipc_message *msg, *tmp;
- unsigned long flags;
- int tx_drop_cnt = 0, rx_drop_cnt = 0;
-
- /* drop all TX and Rx messages before we stall + reset DSP */
- spin_lock_irqsave(&ipc->dsp->spinlock, flags);
-
- list_for_each_entry_safe(msg, tmp, &ipc->tx_list, list) {
- list_move(&msg->list, &ipc->empty_list);
- tx_drop_cnt++;
- }
-
- list_for_each_entry_safe(msg, tmp, &ipc->rx_list, list) {
- list_move(&msg->list, &ipc->empty_list);
- rx_drop_cnt++;
- }
-
- spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
-
- if (tx_drop_cnt || rx_drop_cnt)
- pr_err("dropped IPC tx_msg cnt %d, rx_msg=%d\n",
- tx_drop_cnt, rx_drop_cnt);
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_drop_all);
-
-int hifi4dsp_ipc_init(struct hifi4dsp_ipc *ipc)
-{
- int ret;
-
- INIT_LIST_HEAD(&ipc->tx_list);
- INIT_LIST_HEAD(&ipc->rx_list);
- INIT_LIST_HEAD(&ipc->empty_list);
- init_waitqueue_head(&ipc->wait_txq);
-
- ret = ipc_msg_empty_list_init(ipc);
- if (ret < 0)
- return -ENOMEM;
-
- /* start the IPC message thread */
- kthread_init_worker(&ipc->kworker);
- ipc->tx_thread = kthread_run(kthread_worker_fn,
- &ipc->kworker, "%s",
- dev_name(ipc->dev));
- if (IS_ERR(ipc->tx_thread)) {
- pr_err("error: failed to create message TX task\n");
- ret = PTR_ERR(ipc->tx_thread);
- kfree(ipc->msg);
- return ret;
- }
-
- kthread_init_work(&ipc->kwork, ipc_tx_msgs);
- return 0;
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_init);
-
-void hifi4dsp_ipc_finish(struct hifi4dsp_ipc *ipc)
-{
- int i;
-
- if (ipc->tx_thread)
- kthread_stop(ipc->tx_thread);
-
- if (ipc->msg) {
- for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
- kfree(ipc->msg[i].tx_data);
- kfree(ipc->msg[i].rx_data);
- }
- kfree(ipc->msg);
- }
-}
-EXPORT_SYMBOL_GPL(hifi4dsp_ipc_finish);
-
+++ /dev/null
-/*
- * drivers/amlogic/hifi4dsp/hifi4dsp_ipc.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _HIFI4DSP_IPC_H
-#define _HIFI4DSP_IPC_H
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/wait.h>
-#include <linux/list.h>
-#include <linux/workqueue.h>
-#include <linux/sched.h>
-#include <linux/kthread.h>
-
-#include "hifi4dsp_dsp.h"
-
-struct hifi4dsp_ipc;
-
-#define IPC_MAILBOX_MAX_BYTES 256
-#define IPC_EMPTY_LIST_SIZE 8
-#define IPC_MSG_TIMEOUT_MSECS 300 /* IPC message timeout (msecs) */
-
-struct hifi4dsp_ipc_message {
- struct list_head list;
- u64 header;
-
- char *tx_data;
- size_t tx_size;
- char *rx_data;
- size_t rx_size;
-
- wait_queue_head_t waitq;
- bool pending;
- bool complete;
- bool wait;
- int errno;
-};
-
-struct hifi4dsp_ipc_plat_ops {
- void (*tx_msg)(struct hifi4dsp_ipc *, struct hifi4dsp_ipc_message *);
- void (*tx_data_copy)(struct hifi4dsp_ipc_message *, char *, size_t);
- bool (*is_dsp_busy)(struct hifi4dsp_dsp *dsp);
- void (*debug_info)(struct hifi4dsp_ipc *, const char *);
- u64 (*reply_msg_match)(u64 header, u64 *mask);
-};
-
-struct hifi4dsp_ipc {
- struct device *dev;
- struct hifi4dsp_dsp *dsp;
-
- /* IPC messaging */
- struct list_head tx_list;
- struct list_head rx_list;
- struct list_head empty_list;
- wait_queue_head_t wait_txq;
- struct task_struct *tx_thread;
- struct kthread_worker kworker;
- struct kthread_work kwork;
- bool pending;
- struct hifi4dsp_ipc_message *msg;
- int tx_data_max_size;
- int rx_data_max_size;
-
- struct hifi4dsp_ipc_plat_ops ops;
-};
-
-int hifi4dsp_ipc_tx_message_wait(struct hifi4dsp_ipc *ipc, u64 header,
- void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes);
-
-int hifi4dsp_ipc_tx_message_nowait(struct hifi4dsp_ipc *ipc, u64 header,
- void *tx_data, size_t tx_bytes);
-
-struct hifi4dsp_ipc_message *hifi4dsp_ipc_reply_find_msg(
- struct hifi4dsp_ipc *ipc, u64 header);
-
-void hifi4dsp_ipc_tx_msg_reply_complete(struct hifi4dsp_ipc *ipc,
- struct hifi4dsp_ipc_message *msg);
-
-void hifi4dsp_ipc_drop_all(struct hifi4dsp_ipc *ipc);
-int hifi4dsp_ipc_init(struct hifi4dsp_ipc *ipc);
-void hifi4dsp_ipc_fini(struct hifi4dsp_ipc *ipc);
-
-#endif /*_HIFI4DSP_IPC_H*/
+++ /dev/null
-/*
- * drivers/amlogic/hifi4dsp/tm2_dsp_top.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/firmware.h>
-#include <linux/amlogic/major.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/amlogic/scpi_protocol.h>
-
-#include "hifi4dsp_priv.h"
-#include "hifi4dsp_firmware.h"
-#include "hifi4dsp_dsp.h"
-
-/*AO_RTI*/
-#define AO_RTI_ADDR_BASE (0xff800000)
-#define REG_AO_RTI_GEN_PWR_SLEEP0 (0x03a << 2)
-#define REG_AO_RTI_GEN_PWR_ISO0 (0x03b << 2)
-
-/*HIU*/
-#define HUI_ADDR_BASE (0xff63c000)
-#define REG_HHI_DSP_CLK_CNTL (0x0fc << 2)
-#define REG_HHI_DSP_MEM_PD_REG0 (0x044 << 2)
-
-/*reset*/
-#define RESET_ADDR_BASE (0xffd01000)
-#define REG_RESET1_LEVEL (0x84)
-#define REG_RESET4_LEVEL (0x90)
-
-/*DSP TOP*/
-#define DSPA_REG_BASE (0xff680000)
-#define DSPB_REG_BASE (0xff690000)
-
-#define REG_DSP_CFG0 (0x0)
-#define REG_DSP_CFG1 (0x4)
-#define REG_DSP_CFG2 (0x8)
-#define REG_DSP_RESET_VEC (0x004 << 2)
-
-struct reg_iomem_t {
- void __iomem *dsp_addr;
- void __iomem *dspa_addr;
- void __iomem *dspb_addr;
- void __iomem *hiu_addr; /*HIU*/
- void __iomem *ao_rti_addr; /*AO_RTI*/
- void __iomem *reset_addr;
- void __iomem *sleep_addr;
-};
-
-static struct reg_iomem_t g_regbases;
-static bool regs_iomem_is_inited;
-
-static void __iomem *reg_iomem_init(phys_addr_t paddr, u32 size)
-{
- void __iomem *vaddr = NULL;
-
- vaddr = ioremap_nocache(paddr, size);
- pr_debug("%s phys: %llx, virt: %p, size:%x Bytes\n",
- __func__,
- (unsigned long long)paddr,
- vaddr,
- size);
- return vaddr;
-}
-
-static inline void tm2_dsp_top_reg_dump(char *name,
- void __iomem *reg_base, u32 reg_offset)
-{
- pr_info("%s (%p) = 0x%x\n", name,
- (reg_base + reg_offset),
- readl(reg_base + reg_offset));
-}
-
-void tm2_dsp_regs_iomem_init(void)
-{
- if (regs_iomem_is_inited == true) {
- pr_info("%s has been done\n", __func__);
- return;
- }
-
- g_regbases.dspa_addr = reg_iomem_init(DSPA_REG_BASE, 0x8B*4);
- g_regbases.dspb_addr = reg_iomem_init(DSPB_REG_BASE, 0x8B*4);
-
- g_regbases.hiu_addr = reg_iomem_init(HUI_ADDR_BASE, 0xFF*4);
- g_regbases.ao_rti_addr = reg_iomem_init(AO_RTI_ADDR_BASE, 0xFF*4);
- g_regbases.reset_addr = reg_iomem_init(RESET_ADDR_BASE, 0x40*4);
-
- regs_iomem_is_inited = true;
-
- pr_debug("%s done\n", __func__);
-}
-
-void tm2_dsp_regs_iounmem(void)
-{
- iounmap(g_regbases.dspa_addr);
- iounmap(g_regbases.dspb_addr);
-
- iounmap(g_regbases.hiu_addr);
- iounmap(g_regbases.ao_rti_addr);
- iounmap(g_regbases.reset_addr);
-
- regs_iomem_is_inited = false;
-
- pr_debug("%s done\n", __func__);
-}
-
-static inline void __iomem *get_hiu_addr(void)
-{
- return g_regbases.hiu_addr;
-}
-
-static inline void __iomem *get_ao_rti_addr(void)
-{
- return g_regbases.ao_rti_addr;
-}
-
-static inline void __iomem *get_reset_addr(void)
-{
- return g_regbases.reset_addr;
-}
-
-static inline void __iomem *get_dsp_addr(int dsp_id)
-{
- if (dsp_id == 1)
- return g_regbases.dspb_addr;
- else
- return g_regbases.dspa_addr;
-}
-
-/*
- * clk_util_set_dsp_clk
- * freq_sel: 0:286MHz fclk_7
- * 1:400MHz fclk_5
- * 2:500MHz fclk_2/2
- * 3:667MHz fclk_3
- * 4:1000MHz fclk_2
- * others:286MHz fclk/7
- */
-//crt_clk_div_mux4_ns #(8)
-// u_crt_dspa_clk_mux_div(
-// .clk0 (fclk_div2 ),
-// .clk1 (fclk_div3 ),
-// .clk2 (fclk_div5 ),
-// .clk3 (fclk_div7 ),
-// .reset_n (crt_reset_n ),
-// .force_oscin_clk (1'b0 ),
-// .cts_oscin_clk (1'b0 ),
-//
-// .clk_div (hi_dsp_clk_cntl[7:0] ),
-// .clk_en (hi_dsp_clk_cntl[15] ),
-// .clk_sel (hi_dsp_clk_cntl[9:8] ),
-// .clk_out (cts_dspa_clk ));
-
-static void clk_util_set_dsp_clk(uint32_t id, uint32_t freq_sel)
-{
- uint32_t clk_sel = 0;
- uint32_t clk_div = 0;
- uint32_t read;
- void __iomem *reg;
-
- reg = get_hiu_addr() + REG_HHI_DSP_CLK_CNTL;
- switch (freq_sel) {
- case 1:
- clk_sel = 2;
- clk_div = 0;
- pr_debug("CLK_UTIL:dsp:fclk/5:400MHz\n");
- break;
- case 2:
- clk_sel = 0;
- clk_div = 1;
- pr_debug("CLK_UTIL:dsp:fclk/4:500MHz\n");
- break;
- case 3:
- //clk_sel = 1;
- //clk_div = 0;
- //pr_debug("CLK_UTIL:dsp:fclk/3:667MHz\n");
- break;
- case 4:
- clk_sel = 1;
- clk_div = 1;
- pr_debug("CLK_UTIL:dsp:fclk/3/2:333MHz\n");
- break;
- case 5:
- clk_sel = 0;
- clk_div = 3;
- pr_debug("CLK_UTIL:dsp:fclk/2:250MHz\n");
- break;
- case 6:
- clk_sel = 2;
- clk_div = 1;
- pr_debug("CLK_UTIL:dsp:fclk/4/2:200MHz\n");
- break;
- case 7:
- clk_sel = 2;
- clk_div = 3;
- pr_debug("CLK_UTIL:dsp:fclk/4/4:100MHz\n");
- break;
- case 8:
- clk_sel = 4;
- clk_div = 0;
- pr_debug("CLK_UTIL:dsp:oscin:24MHz\n");
- break;
- case 10:
- //clk_sel = 0;
- //clk_div = 0;
- //pr_debug("CLK_UTIL:dsp:fclk/2:1000MHz\n");
- break;
- default:
- clk_sel = 3;
- clk_div = 0;
- pr_debug("CLK_UTIL:dsp:fclk/7:286MHz\n");
- break;
- }
-
- read = readl(reg);
- if (id == 0) {
- //read = (read & ~((0x3<<8) | (0xff<<0)));
- //read = read | ((1<<15) | (clk_sel<<8) | (clk_div<<0));
- if (read & (1 << 15)) { //if sync_mux ==1, sel mux 0
- read &= (~((1 << 15) | (0xf << 0) | (0x7 << 4)));
- read |= (1 << 7) | (clk_div << 0) | (clk_sel << 4);
- } else {
- read &= (~((1 << 15) | (0xf << 8) | (0x7 << 12)));
- read |= (1 << 7) | (clk_div << 8);
- read |= (clk_sel << 12) | (1 << 15);
- }
- } else {
- //read = (read & ~((0x3<<24) | (0xff<<16)));
- //read = read | ((1<<31) | (clk_sel<<24) | (clk_div<<16));
- if (read & (1 << 31)) { //if sync_mux ==1, sel mux 0
- read &= (~((1 << 31) | (0xf << 16) | (0x7 << 20)));
- read |= (1 << 23) | (clk_div << 16) | (clk_sel << 20);
- } else {
- read &= (~((1 << 31) | (0xf << 24) | (0x7 << 28)));
- read |= (1 << 23) | (clk_div << 24);
- read |= (clk_sel << 28) | (1 << 31);
- }
- }
- writel(read, reg);
-
- pr_debug("%s\n", __func__);
-
-}
-
-static void start_dsp(uint32_t dsp_id, uint32_t reset_addr)
-{
- uint32_t StatVectorSel;
- uint32_t strobe = 1;
- uint32_t tmp;
- uint32_t read;
- void __iomem *reg;
-
- reg = get_dsp_addr(dsp_id);
- StatVectorSel = (reset_addr != 0xfffa0000);
-
- // the bit 0 is no use, dsp in tm2 is non-secure
- tmp = 0x1 | StatVectorSel<<1 | strobe<<2;
- scpi_init_dsp_cfg0(dsp_id, reset_addr, tmp);
-
-
- read = readl(reg+REG_DSP_CFG0);
- pr_debug("REG_DSP_CFG0 read=0x%x\n", read);
- if (dsp_id == 0) {
- read = read & (~((1 << 31) | (1 << 30) | (0xffff << 0)));
- read = read | (1 << 29) | (0 << 0); // 29 irq_clk_en
- } else {
- read = read & (~((1 << 31) | (1 << 30) | (0xffff << 0)));
- read = read | (1 << 29) | (1 << 0);
- }
- writel(read, reg+REG_DSP_CFG0);
- tm2_dsp_top_reg_dump("REG_DSP_CFG0", reg, REG_DSP_CFG0);
-
- pr_debug("%s\n", __func__);
-
-}
-
-static void power_switch_to_dsp_a(int pwr_cntl)
-{
- uint32_t tmp;
- void __iomem *reg;
-
- pr_info("[PWR]: Power %s DSP A\n", pwr_cntl?"On":"Off");
- if (pwr_cntl == 1) {
- // Powerup dsp a
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_SLEEP0;
- tmp = readl(reg) & (~(0x1<<21));
- writel(tmp, reg);// power on
- udelay(5);
-
- // Power up memory
- reg = get_hiu_addr() + REG_HHI_DSP_MEM_PD_REG0;
- tmp = readl(reg) & (~(0xffff<<0));
- writel(tmp, reg);
- udelay(5);
-
- // reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) & (~(0x1<<0));
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) & (~(0x1<<20));
- writel(tmp, reg);
-
- // remove isolation
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_ISO0;
- tmp = readl(reg) & (~(0x1<<21));
- writel(tmp, reg);
-
- // pull up reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) | (0x1<<0);
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) | (0x1<<20);
- writel(tmp, reg);
- } else {
- // reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) & (~(0x1<<0));
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) & (~(0x1<<20));
- writel(tmp, reg);
-
- // add isolation
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_ISO0;
- tmp = readl(reg) | (0x1<<21);
- writel(tmp, reg);
- udelay(5);
-
- // power down memory
- reg = get_hiu_addr() + REG_HHI_DSP_MEM_PD_REG0;
- tmp = readl(reg) | (0xffff<<0);
- writel(tmp, reg);
- udelay(5);
-
- // power down dsp a
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_SLEEP0;
- tmp = readl(reg) | (0x1<<21);
- writel(tmp, reg);
- udelay(5);
- }
-
-}
-
-static void power_switch_to_dsp_b(int pwr_cntl)
-{
- uint32_t tmp;
- void __iomem *reg;
-
- if (pwr_cntl == 1) {
- pr_info("[PWR]: Power on DSP B\n");
- // Powerup dsp a
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_SLEEP0;
- tmp = readl(reg) & (~(0x1<<22));
- writel(tmp, reg);// power on
- udelay(5);
-
- // Power up memory
- reg = get_hiu_addr() + REG_HHI_DSP_MEM_PD_REG0;
- tmp = readl(reg) & (~(0xffff<<16));
- writel(tmp, reg);
- udelay(5);
-
- // reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) & (~(0x1<<1));
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) & (~(0x1<<21));
- writel(tmp, reg);
-
- // remove isolation
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_ISO0;
- tmp = readl(reg) & (~(0x1<<22));
- writel(tmp, reg);
-
- // pull up reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) | (0x1<<1);
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) | (0x1<<21);
- writel(tmp, reg);
- } else {
- pr_info("[PWR]: Power off DSP B\n");
- // reset
- reg = get_reset_addr() + REG_RESET4_LEVEL;
- tmp = readl(reg) & (~(0x1<<1));
- writel(tmp, reg);
-
- reg = get_reset_addr() + REG_RESET1_LEVEL;
- tmp = readl(reg) & (~(0x1<<21));
- writel(tmp, reg);
-
- // add isolation
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_ISO0;
- tmp = readl(reg) | (0x1<<22);
- writel(tmp, reg);
- udelay(5);
-
- // power down memory
- reg = get_hiu_addr() + REG_HHI_DSP_MEM_PD_REG0;
- tmp = readl(reg) | (0xffff<<16);
- writel(tmp, reg);
- udelay(5);
-
- // power down dsp a
- reg = get_ao_rti_addr() + REG_AO_RTI_GEN_PWR_SLEEP0;
- tmp = readl(reg) | (0x1<<22);
- writel(tmp, reg);
- udelay(5);
- }
-
-}
-
-static void tm2_dsp_power_switch(int dsp_id, int pwr_cntl)
-{
- if (dsp_id == 0)
- power_switch_to_dsp_a(pwr_cntl);
- else if (dsp_id == 1)
- power_switch_to_dsp_b(pwr_cntl);
- else
- pr_err("%s param: dsp_id=%d error\n", __func__, dsp_id);
-}
-
-void tm2_dsp_top_regs_dump(int dsp_id)
-{
- void __iomem *reg;
-
- pr_debug("%s\n", __func__);
-
- reg = get_dsp_addr(dsp_id);
- pr_debug("%s base=%p\n", __func__, reg);
-
- tm2_dsp_top_reg_dump("REG_DSP_CFG0", reg, REG_DSP_CFG0);
- tm2_dsp_top_reg_dump("REG_DSP_CFG1", reg, REG_DSP_CFG1);
- tm2_dsp_top_reg_dump("REG_DSP_CFG2", reg, REG_DSP_CFG2);
- tm2_dsp_top_reg_dump("REG_DSP_RESET_VEC", reg, REG_DSP_RESET_VEC);
-
- reg = get_hiu_addr();
- tm2_dsp_top_reg_dump("REG_HHI_DSP_CLK_CNTL", reg,
- REG_HHI_DSP_CLK_CNTL);
- tm2_dsp_top_reg_dump("REG_HHI_DSP_MEM_PD_REG0", reg,
- REG_HHI_DSP_MEM_PD_REG0);
-
- reg = get_ao_rti_addr();
- tm2_dsp_top_reg_dump("REG_AO_RTI_GEN_PWR_SLEEP0", reg,
- REG_AO_RTI_GEN_PWR_SLEEP0);
- tm2_dsp_top_reg_dump("REG_AO_RTI_GEN_PWR_ISO0", reg,
- REG_AO_RTI_GEN_PWR_ISO0);
-
- reg = get_reset_addr();
- tm2_dsp_top_reg_dump("REG_RESET1_LEVEL", reg, REG_RESET1_LEVEL);
- tm2_dsp_top_reg_dump("REG_RESET4_LEVEL", reg, REG_RESET4_LEVEL);
-
-}
-
-static void tm2_dsp_set_clk(int dsp_id, int freq_sel)
-{
- clk_util_set_dsp_clk(dsp_id, freq_sel);
-}
-
-void tm2_dsp_hw_init(int dsp_id, int freq_sel)
-{
- int pwr_cntl = 1;
-
- tm2_dsp_regs_iomem_init();
- tm2_dsp_set_clk(dsp_id, freq_sel);
- tm2_dsp_power_switch(dsp_id, pwr_cntl);
-
- pr_debug("%s done\n", __func__);
-}
-
-void tm2_dsp_start(int dsp_id, int freq_sel)
-{
- start_dsp(dsp_id, freq_sel);
-}
-
-void tm2_dsp_bootup(int dsp_id, uint32_t reset_addr, int freq_sel)
-{
- int pwr_cntl = 1;
-
- //reset_addr = 0x30000000;
- //dsp_id = 0;
- freq_sel = 1;
-
- pr_debug("%s dsp_id=%d, address=0x%x\n",
- __func__, dsp_id, reset_addr);
-
- tm2_dsp_set_clk(dsp_id, freq_sel);
- tm2_dsp_power_switch(dsp_id, pwr_cntl);
- tm2_dsp_start(dsp_id, reset_addr);
-
- msleep(5*1000);
- tm2_dsp_top_regs_dump(dsp_id);
-}
+++ /dev/null
-/*
- * drivers/amlogic/hifi4dsp/tm2_dsp_top.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _TM2_DSP_TOP_H
-#define _TM2_DSP_TOP_H
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/firmware.h>
-#include <linux/irqreturn.h>
-
-#include "hifi4dsp_priv.h"
-#include "hifi4dsp_firmware.h"
-#include "hifi4dsp_dsp.h"
-
-extern void tm2_dsp_bootup(int dsp_id, uint32_t reset_addr, int freq_sel);
-extern void tm2_dsp_regs_iomem_init(void);
-extern void tm2_dsp_hw_init(int dsp_id, int freq_sel);
-extern void tm2_dsp_top_regs_dump(int dsp_id);
-
-#endif /*_TM2_DSP_TOP_H*/
*enable: 1
*/
static bool remote_debug_enable;
+static bool remote_enable = 1;
void remote_repeat(struct remote_dev *dev)
{
return remote_debug_enable;
}
+void remote_set_enable(bool enable)
+{
+ remote_enable = enable;
+}
+
+bool remote_get_enable(void)
+{
+ return remote_enable;
+}
+
static void ir_do_keyup(struct remote_dev *dev)
{
input_report_key(dev->input_device, dev->last_keycode, 0);
/*debug printk */
void remote_debug_set_enable(bool enable);
bool remote_debug_get_enable(void);
+void remote_set_enable(bool enable);
+bool remote_get_enable(void);
int debug_log_printk(struct remote_dev *dev, const char *fmt);
#endif
{ REG_LDR_REPEAT, 0},
{ REG_BIT_0, (52 << 16) | (45<<0)},
{ REG_REG0, ((7 << 28) | (0x5DC << 12) | (0x13))},
- { REG_STATUS, (87 << 20) | (80 << 10)},
+ { REG_STATUS, (86 << 20) | (80 << 10)},
{ REG_REG1, 0x9f00},
{ REG_REG2, 0xa90e},
/*n=10,758+137*10=2128us,2128/20= 106*/
return count;
}
+static ssize_t enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int enable;
+
+ enable = remote_get_enable();
+
+ return sprintf(buf, "%d\n", enable);
+}
+
+static ssize_t enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct remote_chip *chip = dev_get_drvdata(dev);
+ unsigned int val;
+ int enable;
+ int ret;
+ int cnt;
+
+ ret = kstrtoint(buf, 0, &enable);
+ if ((ret != 0) || ((enable != 0) && (enable != 1)))
+ return -EINVAL;
+
+ for (cnt = 0; cnt < (ENABLE_LEGACY_IR(chip->protocol) ? 2 : 1); cnt++) {
+ if (enable) {
+ remote_reg_read(chip, cnt, REG_FRAME, &val);
+ remote_reg_update_bits(chip, cnt, REG_REG1,
+ BIT(15), BIT(15));
+ } else {
+ remote_reg_update_bits(chip, cnt, REG_REG1, BIT(15), 0);
+ }
+ }
+ remote_set_enable(enable);
+
+ return count;
+}
+
int debug_log_printk(struct remote_dev *dev, const char *fmt)
{
char *p;
DEVICE_ATTR_RW(protocol);
DEVICE_ATTR_RW(keymap);
DEVICE_ATTR_RW(debug_enable);
+DEVICE_ATTR_RW(enable);
DEVICE_ATTR_RW(debug_log);
DEVICE_ATTR_RO(map_tables);
&dev_attr_map_tables.attr,
&dev_attr_keymap.attr,
&dev_attr_debug_enable.attr,
+ &dev_attr_enable.attr,
&dev_attr_repeat_enable.attr,
&dev_attr_debug_log.attr,
&dev_attr_led_blink.attr,
.translate = meson_gpio_irq_domain_translate,
};
-static unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags)
-{
- return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long),
- flags);
-}
-
static int __init meson_gpio_irq_parse_dt(struct device_node *node,
struct meson_gpio_irq_controller *ctl)
{
struct mhu_mbox *mbox_dev = filp->private_data;
struct device *dev = mbox_dev->mhu_dev;
int channel = mbox_dev->channel_id;
- unsigned long wait;
spin_lock_irqsave(&mbox_dev->mhu_lock, flags);
if (list_empty(&mbox_list[channel])) {
msg = list_entry(list, struct mbox_message, list);
if (msg->task == current) {
spin_unlock_irqrestore(&mbox_dev->mhu_lock, flags);
- wait = msecs_to_jiffies(MBOX_TIME_OUT);
- ret =
- wait_for_completion_killable_timeout(&msg->complete,
- wait);
- if (ret <= 0) {
- dev_err(dev, "Read msg wait time out\n");
+ ret = wait_for_completion_killable(&msg->complete);
+ if (ret < 0) {
+ dev_err(dev, "Read msg wait killed %d\n",
+ ret);
return -ENXIO;
}
dev_dbg(dev, "Wait end %s\n", msg->data);
struct mhu_mbox *mbox_dev = filp->private_data;
struct device *dev = mbox_dev->mhu_dev;
int channel = mbox_dev->channel_id;
- unsigned long wait;
-
- pr_debug("%s, %d, chanenel %d\n", __func__, __LINE__, channel);
spin_lock_irqsave(&mhu_list_lock, flags);
if (list_empty(&mbox_list[channel])) {
spin_unlock_irqrestore(&mhu_list_lock, flags);
return -ENXIO;
}
- pr_debug("%s, %d, chanenel %d\n", __func__, __LINE__, channel);
list_for_each(list, &mbox_list[channel]) {
msg = list_entry(list, struct mbox_message, list);
if (msg->task == current) {
spin_unlock_irqrestore(&mhu_list_lock, flags);
- wait = msecs_to_jiffies(MBOX_TIME_OUT);
- ret =
- wait_for_completion_killable_timeout(&msg->complete,
- wait);
- if (ret == 0 || ret == -ERESTARTSYS) {
- dev_err(dev, "Read msg wait time out or killable %d\n",
- ret);
+ ret = wait_for_completion_killable(&msg->complete);
+ if (ret < 0) {
+ dev_err(dev, "Read msg wait killed %d\n", ret);
return -ENXIO;
}
dev_dbg(dev, "Wait end %s\n", msg->data);
* multi-times when your data is bigger
* than 0x1fe
*/
-int scpi_send_usr_data(u32 client_id, u32 *val, u32 size)
+int scpi_send_usr_data(u32 client_id, void *val, u32 size)
{
struct scpi_data_buf sdata;
struct mhu_data_buf mdata;
* multi-times when your data is bigger
* than 0x20
*/
-int scpi_send_cec_data(u32 cmd_id, u32 *val, u32 size)
+int scpi_send_cec_data(u32 cmd_id, void *val, u32 size)
{
struct scpi_data_buf sdata;
struct mhu_data_buf mdata;
source "drivers/amlogic/media/deinterlace/Kconfig"
source "drivers/amlogic/media/di_multi/Kconfig"
source "drivers/amlogic/media/di_local/Kconfig"
-source "drivers/amlogic/media/di_multi_v3/Kconfig"
source "drivers/amlogic/media/vin/Kconfig"
source "drivers/amlogic/media/video_processor/Kconfig"
source "drivers/amlogic/media/enhancement/Kconfig"
source "drivers/amlogic/media/gdc/Kconfig"
source "drivers/amlogic/media/algorithm/Kconfig"
source "drivers/amlogic/media/camera/Kconfig"
+source "drivers/amlogic/media/avsync/Kconfig"
endif
source "drivers/amlogic/media/dtv_demod/Kconfig"
endmenu
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += deinterlace/
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi/
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_local/
-obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di_multi_v3/
obj-$(CONFIG_AMLOGIC_MEDIA_VIN) += vin/
obj-$(CONFIG_AMLOGIC_MEDIA_VIDEO_PROCESSOR) += video_processor/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT) += enhancement/
obj-$(CONFIG_AMLOGIC_MEDIA_GDC) += gdc/
obj-$(CONFIG_AMLOGIC_MEDIA_ALGORITHM) += algorithm/
-obj-$(CONFIG_AMLOGIC_VIDEO_CAPTURE) += camera/
\ No newline at end of file
+obj-$(CONFIG_AMLOGIC_VIDEO_CAPTURE) += camera/
+obj-$(CONFIG_AMLOGIC_MEDIA_MSYNC) += avsync/
--- /dev/null
+#
+# Amlogic multi-instance AVsync
+#
+config AMLOGIC_MEDIA_MSYNC
+ bool "Multi-Instance AVSync"
+ default n
+ help
+ Amlogic multi instance AVSync support
--- /dev/null
+obj-y += amavsync.o
+amavsync-objs += msync.o
--- /dev/null
+/*
+ * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <linux/atomic.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/timer.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/vmalloc.h>
+#include <linux/pid.h>
+#include <linux/amlogic/media/vout/vout_notify.h>
+#include <linux/amlogic/major.h>
+#include <uapi/linux/amlogic/msync.h>
+
+#define UNIT90K (90000)
+#define DEFAULT_WALL_ADJ_THRES (UNIT90K / 10) //100ms
+#define MAX_SESSION_NUM 8
+#define CHECK_INTERVAL ((HZ / 10) * 3) //300ms
+#define WAIT_INTERVAL (2 * (HZ)) //2s
+#define TRANSIT_INTERVAL (HZ) //1s
+#define DISC_THRE_REC (UNIT90K / 5)
+#define DISC_THRE_MIN (UNIT90K / 3)
+#define DISC_THRE_MAX (UNIT90K * 20)
+
+#define TEN_MS_INTERVAL (HZ / 100)
+#define MIN_GAP (UNIT90K * 3) /* 3s */
+#define MAX_GAP (UNIT90K * 3) /* 4s */
+#define MAX_AV_DIFF (UNIT90K * 5)
+#define PCR_INVALID_THRES (10 * UNIT90K)
+#define PCR_DISC_THRES (UNIT90K * 3 / 2)
+#define VALID_PTS(pts) ((pts) != AVS_INVALID_PTS)
+
+enum av_sync_stat {
+ AVS_STAT_INIT,
+ AVS_STAT_STARTING,
+ AVS_STAT_STARTED,
+ AVS_STAT_PAUSED,
+ AVS_STAT_TRANSITION,
+};
+
+enum pcr_init_flag {
+ INITCHECK_PCR = 1,
+ INITCHECK_VPTS = 2,
+ INITCHECK_APTS = 4,
+ INITCHECK_DONE = 6, /* all set */
+};
+
+enum pcr_init_priority_e {
+ INIT_PRIORITY_PCR = 0,
+ INIT_PRIORITY_AUDIO = 1,
+ INIT_PRIORITY_VIDEO = 2,
+};
+
+enum pcr_disc_flag {
+ PCR_DISC = 1,
+ VIDEO_DISC = 2,
+ AUDIO_DISC = 4
+};
+
+#define A_DISC_SET(flag) (((flag) & AUDIO_DISC) == AUDIO_DISC)
+#define V_DISC_SET(flag) (((flag) & VIDEO_DISC) == VIDEO_DISC)
+#define PCR_DISC_SET(flag) (((flag) & PCR_DISC) == PCR_DISC)
+
+struct sync_session {
+ u32 id;
+ atomic_t refcnt;
+ struct list_head node;
+ /* mutext for event handling */
+ struct mutex session_mutex;
+ struct class session_class;
+ struct workqueue_struct *wq;
+ char name[16];
+
+ /* target mode */
+ enum av_sync_mode mode;
+ /* current working mode */
+ enum av_sync_mode cur_mode;
+ enum av_sync_stat stat;
+ u32 start_policy;
+
+ bool clock_start;
+ /* lock for ISR resource */
+ spinlock_t lock;
+ u32 wall_clock;
+ u32 wall_clock_inc_remainer;
+ u32 wall_adj_thres;
+ /* 1000 for 1.0f, 2000 for 2.0f, 100 for 0.1f */
+ u32 rate;
+
+ bool v_active;
+ bool a_active;
+
+ /* pts wrapping */
+ u32 freerun_period;
+ u32 disc_thres_min;
+ u32 disc_thres_max;
+ bool v_disc;
+ bool a_disc;
+
+ /* pcr master */
+ bool use_pcr;
+ struct pcr_pair pcr_clock;
+ u32 pcr_init_flag;
+ u32 pcr_init_mode;
+ struct timer_list pcr_timer;
+ bool pcr_timer_added;
+ u64 first_time_record;
+ u32 last_check_vpts;
+ u32 last_check_vpts_cnt;
+ u32 last_check_apts;
+ u32 last_check_apts_cnt;
+ u32 last_check_pcr_clock;
+ u32 pcr_disc_flag;
+ u32 pcr_disc_cnt;
+ u32 pcr_cont_cnt;
+ u32 pcr_disc_clock;
+ int clk_dev; /*pcr mono deviation. Positive if pcr is faster.*/
+
+ struct pts_tri first_vpts;
+ struct pts_tri last_vpts;
+ struct pts_tri first_apts;
+ struct pts_tri last_apts;
+
+ struct device *session_dev;
+ /* wait queue for poll */
+ wait_queue_head_t poll_wait;
+ bool event_pending;
+
+ /* start policy timer */
+ bool wait_work_on;
+ struct delayed_work wait_work;
+ bool pcr_work_on;
+ struct delayed_work pcr_start_work;
+ bool transit_work_on;
+ struct delayed_work transit_work;
+ bool audio_change_work_on;
+ struct delayed_work audio_change_work;
+ bool start_posted;
+ bool v_timeout;
+
+ /* debug */
+ bool debug_freerun;
+ bool audio_switching;
+};
+
+struct msync {
+ s32 multi_sync_major;
+ s32 session_major;
+ /* vsync isr context */
+ spinlock_t lock;
+ /* session management */
+ struct list_head head;
+ struct device *msync_dev;
+ u8 id_pool[MAX_SESSION_NUM];
+
+ /* callback for vout_register_client() */
+ struct notifier_block msync_notifier;
+ /* ready to receive vsync */
+ bool ready;
+
+ /* vout info */
+ u32 sync_duration_den;
+ u32 sync_duration_num;
+ u32 vsync_pts_inc;
+
+ /* start buffering time in 90K */
+ u32 start_buf_thres;
+};
+
+struct msync_priv {
+ int session_id;
+};
+
+enum {
+ LOG_ERR = 0,
+ LOG_WARN = 1,
+ LOG_INFO = 2,
+ LOG_DEBUG = 3,
+ LOG_TRACE = 4,
+};
+
+#define msync_dbg(level, x...) \
+ do { \
+ if ((level) <= log_level) \
+ pr_info(x); \
+ } while (0)
+
+static struct msync sync;
+static int log_level;
+static void pcr_set(struct sync_session *session);
+
+static u32 abs_diff(u32 a, u32 b)
+{
+ return (int)(a - b) > 0 ? a - b : b - a;
+}
+
+static u32 pts_early(u32 a, u32 b)
+{
+ return (int)(a - b) > 0 ? b : a;
+}
+
+static void session_set_wall_clock(struct sync_session *session, u32 clock)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&session->lock, flags);
+ session->wall_clock = clock;
+ session->wall_clock_inc_remainer = 0;
+ spin_unlock_irqrestore(&session->lock, flags);
+}
+
+static void session_vsync_update(struct sync_session *session)
+{
+ if (session->clock_start) {
+ unsigned long flags;
+ u32 temp = 0;
+ u32 r = 0;
+ u32 den = sync.sync_duration_den;
+
+ /* both den and num * 20 to handle
+ * speed with multiple of 0.05
+ */
+ den = den * 20 * session->rate / 1000;
+ spin_lock_irqsave(&session->lock, flags);
+ temp = div_u64_rem(90000ULL * den, sync.sync_duration_num * 20, &r);
+ r /= 20;
+ session->wall_clock += temp;
+ session->wall_clock_inc_remainer += r;
+ if (session->wall_clock_inc_remainer >= sync.sync_duration_num) {
+ session->wall_clock++;
+ session->wall_clock_inc_remainer -= sync.sync_duration_num;
+ }
+ spin_unlock_irqrestore(&session->lock, flags);
+ }
+}
+
+int msync_vsync_update(void)
+{
+ struct sync_session *session;
+ struct list_head *p;
+ unsigned long flags;
+
+ if (!sync.ready)
+ return 0;
+
+ spin_lock_irqsave(&sync.lock, flags);
+ list_for_each(p, &sync.head) {
+ session = list_entry(p, struct sync_session, node);
+ session_vsync_update(session);
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+ return 0;
+}
+EXPORT_SYMBOL(msync_vsync_update);
+
+static void msync_update_mode(void)
+{
+ u32 inc;
+ unsigned long flags;
+ const struct vinfo_s *info;
+
+ info = get_current_vinfo();
+ /* pre-calculate vsync_pts_inc in 90k unit */
+ inc = 90000 * info->sync_duration_den /
+ info->sync_duration_num;
+ sync.vsync_pts_inc = inc;
+ spin_lock_irqsave(&sync.lock, flags);
+ if (info->sync_duration_num == 2997 ||
+ info->sync_duration_num == 5994) {
+ /* this is an adjustment to give accurate num/dem pair */
+ sync.sync_duration_den = 1001;
+ sync.sync_duration_num = 3000 * 1000 / info->sync_duration_den;
+ sync.sync_duration_num *= (info->sync_duration_num / 2997);
+ } else {
+ sync.sync_duration_den = info->sync_duration_den;
+ sync.sync_duration_num = info->sync_duration_num;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+ msync_dbg(0, "vsync_pts_inc %d %d/%d\n", inc,
+ sync.sync_duration_den, sync.sync_duration_num);
+}
+
+static int msync_notify_callback(struct notifier_block *block,
+ unsigned long cmd, void *para)
+{
+ switch (cmd) {
+ case VOUT_EVENT_MODE_CHANGE:
+ msync_update_mode();
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static unsigned int session_poll(struct file *file, poll_table *wait_table)
+{
+ struct sync_session *session = file->private_data;
+
+ poll_wait(file, &session->poll_wait, wait_table);
+ if (session->event_pending)
+ return POLLPRI;
+ return 0;
+}
+
+static void wait_up_poll(struct sync_session *session)
+{
+ session->event_pending = true;
+ wake_up_interruptible(&session->poll_wait);
+}
+
+static void transit_work_func(struct work_struct *work)
+{
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct sync_session *session =
+ container_of(dwork, struct sync_session, transit_work);
+
+ mutex_lock(&session->session_mutex);
+ if (session->transit_work_on) {
+ session_set_wall_clock(session, session->last_apts.wall_clock);
+ session->stat = AVS_STAT_STARTED;
+ session->cur_mode = AVS_MODE_A_MASTER;
+ session->transit_work_on = false;
+ }
+ mutex_unlock(&session->session_mutex);
+}
+
+static void wait_work_func(struct work_struct *work)
+{
+ bool wake = false;
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct sync_session *session =
+ container_of(dwork, struct sync_session, wait_work);
+
+ mutex_lock(&session->session_mutex);
+ if (!session->wait_work_on) {
+ mutex_unlock(&session->session_mutex);
+ return;
+ }
+ if (!VALID_PTS(session->first_vpts.pts)) {
+ msync_dbg(LOG_WARN, "[%d]wait video timeout\n",
+ session->id);
+ session->clock_start = true;
+ session->v_timeout = true;
+ }
+
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ !session->start_posted) {
+ msync_dbg(LOG_DEBUG, "[%d]start posted\n", session->id);
+ session->start_posted = true;
+ wake = true;
+ }
+ session->wait_work_on = false;
+ mutex_unlock(&session->session_mutex);
+ if (wake)
+ wait_up_poll(session);
+}
+
+static void audio_change_work_func(struct work_struct *work)
+{
+ bool wake = false;
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct sync_session *session =
+ container_of(dwork, struct sync_session, audio_change_work);
+
+ mutex_lock(&session->session_mutex);
+ msync_dbg(LOG_WARN, "[%d] audio start now clock %u apts %u\n",
+ session->id, session->wall_clock, session->first_apts.pts);
+ if (!session->audio_change_work_on) {
+ mutex_unlock(&session->session_mutex);
+ return;
+ }
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ !session->start_posted) {
+ session->start_posted = true;
+ session->stat = AVS_STAT_STARTED;
+ msync_dbg(LOG_WARN, "[%d] audio allow start\n",
+ session->id);
+ wake = true;
+ }
+ session->audio_change_work_on = false;
+ mutex_unlock(&session->session_mutex);
+ if (wake)
+ wait_up_poll(session);
+}
+
+static void pcr_start_work_func(struct work_struct *work)
+{
+ struct delayed_work *dwork = to_delayed_work(work);
+ struct sync_session *session =
+ container_of(dwork, struct sync_session, pcr_start_work);
+
+ mutex_lock(&session->session_mutex);
+ if (!session->pcr_work_on) {
+ mutex_unlock(&session->session_mutex);
+ return;
+ }
+ if (!VALID_PTS(session->first_apts.pts)) {
+ msync_dbg(LOG_WARN, "[%d]wait audio timeout\n",
+ session->id);
+ }
+ pcr_set(session);
+ session->stat = AVS_STAT_STARTED;
+ session->pcr_work_on = false;
+
+ msync_dbg(LOG_INFO,
+ "[%d]%d video start %u w %u\n",
+ session->id, __LINE__,
+ session->last_vpts.pts, session->wall_clock);
+ mutex_unlock(&session->session_mutex);
+}
+
+static void use_pcr_clock(struct sync_session *session, bool enable, u32 pts)
+{
+ if (enable) {
+ /* use pcr as reference */
+ session->use_pcr = true;
+ session_set_wall_clock(session, session->pcr_clock.pts);
+ } else {
+ /* use wall clock as reference */
+ session->use_pcr = false;
+ session_set_wall_clock(session, pts);
+ }
+ session->clock_start = true;
+}
+
+#if 0
+static u32 get_ref_pcr(struct sync_session *session,
+ u32 cur_vpts, u32 cur_apts, u32 min_pts)
+{
+ //u32 v_cache_pts = AVS_INVALID_PTS;
+ u32 a_pts_span = AVS_INVALID_PTS;
+ u32 first_vpts = AVS_INVALID_PTS;
+ u32 first_apts = AVS_INVALID_PTS;
+ u32 ref_pcr = AVS_INVALID_PTS;
+
+ //if (VALID_PTS(cur_vpts) && VALID_PTS(session->first_vpts.pts))
+ // v_cache_pts = cur_vpts - session->first_vpts.pts;
+ if (VALID_PTS(cur_apts) && VALID_PTS(session->first_apts.pts))
+ a_pts_span = cur_apts - session->first_apts.pts;
+ if (VALID_PTS(session->first_vpts.pts))
+ first_vpts = session->first_vpts.pts;
+ if (VALID_PTS(session->first_apts.pts))
+ first_apts = session->first_apts.pts;
+
+ if ((VALID_PTS(first_apts) && VALID_PTS(first_vpts) &&
+ VALID_PTS(a_pts_span) &&
+ first_apts < first_vpts &&
+ (first_vpts - first_apts <= MAX_AV_DIFF) &&
+ (a_pts_span < first_vpts - first_apts)) ||
+ (!VALID_PTS(first_vpts) && !VALID_PTS(cur_vpts))) {
+ //use audio
+ if (VALID_PTS(cur_apts))
+ ref_pcr = cur_apts;
+ else
+ ref_pcr = first_apts;
+ } else if ((VALID_PTS(first_vpts) && VALID_PTS(first_apts) &&
+ first_apts >= first_vpts) ||
+ (!VALID_PTS(first_apts) && !VALID_PTS(cur_apts))) {
+ //use video
+ if (VALID_PTS(cur_vpts))
+ ref_pcr = cur_vpts;
+ else
+ ref_pcr = first_vpts;
+ } else if (!VALID_PTS(first_vpts) && !VALID_PTS(first_apts)) {
+ //use smaller one
+ ref_pcr = min_pts;
+ } else if (!VALID_PTS(first_apts) && VALID_PTS(cur_apts) &&
+ VALID_PTS(first_vpts) &&
+ VALID_PTS(a_pts_span) &&
+ (first_vpts > cur_apts) &&
+ (first_vpts - cur_apts <= MAX_AV_DIFF) &&
+ (a_pts_span < first_vpts - cur_apts)) {
+ //use audio
+ ref_pcr = cur_apts;
+ } else {
+ //use video by default
+ if (VALID_PTS(cur_vpts))
+ ref_pcr = cur_vpts;
+ else
+ ref_pcr = first_vpts;
+ }
+
+ return ref_pcr;
+}
+#endif
+
+/* only handle first arrived A/V/PCR */
+static void pcr_set(struct sync_session *session)
+{
+ u32 cur_pcr = AVS_INVALID_PTS;
+ u32 cur_vpts = AVS_INVALID_PTS;
+ u32 cur_apts = AVS_INVALID_PTS;
+ //u32 ref_pcr = AVS_INVALID_PTS;
+ u32 min_pts = AVS_INVALID_PTS;
+
+ if (session->pcr_init_flag & INITCHECK_DONE)
+ return;
+
+ if (VALID_PTS(session->first_vpts.pts))
+ cur_vpts = session->first_vpts.pts;
+ if (VALID_PTS(session->first_apts.pts))
+ cur_apts = session->first_apts.pts;
+ if (VALID_PTS(session->pcr_clock.pts))
+ cur_pcr = session->pcr_clock.pts;
+
+ if (VALID_PTS(session->last_vpts.pts))
+ cur_vpts = session->last_vpts.pts;
+ if (VALID_PTS(session->last_apts.pts))
+ cur_apts = session->last_apts.pts;
+
+ if (VALID_PTS(cur_vpts) && VALID_PTS(cur_apts))
+ min_pts = pts_early(cur_vpts, cur_apts);
+ else if (VALID_PTS(cur_vpts))
+ min_pts = cur_vpts;
+ else if (VALID_PTS(cur_apts))
+ min_pts = cur_apts;
+
+ /* buffering */
+ if (VALID_PTS(min_pts))
+ min_pts -= sync.start_buf_thres;
+
+ /* pcr comes first */
+ if (VALID_PTS(cur_pcr)) {
+ session->pcr_init_flag |= INITCHECK_PCR;
+ session->pcr_init_mode = INIT_PRIORITY_PCR;
+ if (!VALID_PTS(cur_vpts) && !VALID_PTS(cur_apts)) {
+ use_pcr_clock(session, true, 0);
+ msync_dbg(LOG_TRACE, "[%d]%d enable pcr %u\n",
+ session->id, __LINE__, cur_pcr);
+ }
+ }
+#if 0
+ if (VALID_PTS(cur_pcr) && VALID_PTS(cur_vpts) && VALID_PTS(cur_apts)) {
+ u32 gap_pa, gap_pv, gap_av;
+
+ gap_pa = abs_diff(cur_pcr, cur_apts);
+ gap_av = abs_diff(cur_apts, cur_vpts);
+ gap_pv = abs_diff(cur_pcr, cur_vpts);
+ if (gap_pa > MAX_GAP && gap_pv > MAX_GAP) {
+ if (gap_av > MAX_GAP)
+ ref_pcr = cur_vpts;
+ else
+ ref_pcr = min_pts;
+
+ session->pcr_init_flag |= INITCHECK_VPTS;
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, ref_pcr);
+ msync_dbg(LOG_TRACE, "[%d]%d pcr %u v %u a %u\n",
+ session->id, __LINE__,
+ cur_pcr, cur_vpts, cur_apts);
+ msync_dbg(LOG_TRACE, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, ref_pcr);
+ return;
+ }
+ if (cur_vpts < cur_pcr && cur_vpts < cur_apts) {
+ session->pcr_init_flag |= INITCHECK_VPTS;
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, cur_vpts);
+ msync_dbg(LOG_TRACE, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, cur_vpts);
+ return;
+ }
+ }
+
+ if (VALID_PTS(cur_pcr) && VALID_PTS(min_pts)) {
+ session->pcr_init_flag |= INITCHECK_PCR;
+ if (VALID_PTS(cur_vpts) &&
+ abs_diff(cur_pcr, cur_vpts) > PCR_INVALID_THRES) {
+ if (VALID_PTS(session->first_vpts.pts))
+ ref_pcr = session->first_vpts.pts;
+ else
+ ref_pcr = cur_vpts;
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, ref_pcr);
+ msync_dbg(LOG_TRACE, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, ref_pcr);
+ } else if (((cur_pcr > min_pts) &&
+ (cur_pcr - min_pts) > (UNIT90K / 2)) ||
+ session->use_pcr) {
+ if (VALID_PTS(cur_apts) &&
+ VALID_PTS(cur_vpts) &&
+ abs_diff(cur_apts, cur_vpts) > MAX_GAP) {
+ if (VALID_PTS(session->first_vpts.pts))
+ ref_pcr = session->first_vpts.pts;
+ else
+ ref_pcr = cur_vpts;
+ } else {
+ ref_pcr = min_pts;
+ }
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, ref_pcr);
+ msync_dbg(LOG_TRACE, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, ref_pcr);
+ } else {
+ session->pcr_init_mode = INIT_PRIORITY_PCR;
+ use_pcr_clock(session, true, 0);
+ msync_dbg(LOG_TRACE, "[%d]%d enable pcr %u\n",
+ session->id, __LINE__, ref_pcr);
+ }
+ return;
+ }
+#endif
+
+ if (VALID_PTS(session->first_apts.pts)) {
+ session->pcr_init_flag |= INITCHECK_APTS;
+ //ref_pcr = get_ref_pcr(session, cur_vpts, cur_apts, min_pts);
+ if (VALID_PTS(cur_pcr))
+ session->pcr_init_mode = INIT_PRIORITY_PCR;
+ else
+ session->pcr_init_mode = INIT_PRIORITY_AUDIO;
+ use_pcr_clock(session, false, min_pts);
+ msync_dbg(LOG_DEBUG, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, min_pts);
+ }
+
+ if (VALID_PTS(session->first_vpts.pts) && !session->pcr_work_on) {
+ session->pcr_init_flag |= INITCHECK_VPTS;
+ //ref_pcr = get_ref_pcr(session, cur_vpts, cur_apts, min_pts);
+ if (VALID_PTS(cur_pcr))
+ session->pcr_init_mode = INIT_PRIORITY_PCR;
+ else
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, min_pts);
+ msync_dbg(LOG_DEBUG, "[%d]%d disable pcr %u\n",
+ session->id, __LINE__, min_pts);
+ }
+}
+
+static u32 pcr_get(struct sync_session *session)
+{
+ if (session->use_pcr)
+ return session->pcr_clock.pts;
+ else
+ return session->wall_clock;
+}
+
+static void update_f_vpts(struct sync_session *session, u32 pts)
+{
+ session->first_vpts.wall_clock = pts;
+ session->first_vpts.pts = pts;
+}
+
+static void update_f_apts(struct sync_session *session, u32 pts)
+{
+ session->first_apts.wall_clock = pts;
+ session->first_apts.pts = pts;
+}
+
+static void session_video_start(struct sync_session *session, u32 pts)
+{
+ bool wakeup = false;
+
+ session->v_active = true;
+ mutex_lock(&session->session_mutex);
+ if (session->mode == AVS_MODE_V_MASTER) {
+ session_set_wall_clock(session, pts);
+ session->clock_start = true;
+ session->stat = AVS_STAT_STARTED;
+ update_f_vpts(session, pts);
+ msync_dbg(LOG_INFO, "[%d]%d video start %u\n",
+ session->id, __LINE__, pts);
+ } else if (session->mode == AVS_MODE_A_MASTER) {
+ update_f_vpts(session, pts);
+
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ VALID_PTS(session->first_apts.pts)) {
+ if (session->clock_start)
+ goto exit;
+ session->stat = AVS_STAT_STARTED;
+ if ((int)(session->first_apts.pts - pts) > 900) {
+ u32 delay = (session->first_apts.pts - pts) / 900;
+
+ msync_dbg(LOG_INFO,
+ "[%d]%d video start %u ad %u\n",
+ session->id, __LINE__, pts, delay * 10);
+ /* use video pts as starting point */
+ session_set_wall_clock(session, pts);
+ session->clock_start = true;
+ mod_delayed_work(session->wq,
+ &session->wait_work,
+ TEN_MS_INTERVAL * delay);
+ } else {
+ session->clock_start = true;
+ cancel_delayed_work_sync(&session->wait_work);
+ session->wait_work_on = false;
+ session->start_posted = true;
+ wakeup = true;
+ msync_dbg(LOG_INFO, "[%d]%d video start %u\n",
+ session->id, __LINE__, pts);
+ }
+ }
+ } else if (session->mode == AVS_MODE_IPTV) {
+ update_f_vpts(session, pts);
+
+ if (session->start_policy == AMSYNC_START_ASAP &&
+ !VALID_PTS(session->first_apts.pts)) {
+ session_set_wall_clock(session, pts);
+ session->clock_start = true;
+ session->stat = AVS_STAT_STARTED;
+ session->cur_mode = AVS_MODE_V_MASTER;
+ wakeup = true;
+ msync_dbg(LOG_INFO, "[%d]%d video start %u\n",
+ session->id, __LINE__, pts);
+ } else if (session->start_policy == AMSYNC_START_ASAP) {
+ msync_dbg(LOG_INFO, "[%d]%d video start %u keep AMASTER\n",
+ session->id, __LINE__, pts);
+ }
+ } else if (session->mode == AVS_MODE_PCR_MASTER) {
+ update_f_vpts(session, pts);
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ !VALID_PTS(session->first_apts.pts)) {
+ msync_dbg(LOG_INFO,
+ "[%d]%d video start %u deferred\n",
+ session->id, __LINE__, pts);
+ if (session->pcr_work_on)
+ cancel_delayed_work(&session->pcr_start_work);
+ queue_delayed_work(session->wq,
+ &session->pcr_start_work,
+ CHECK_INTERVAL);
+ session->stat = AVS_STAT_STARTING;
+ session->pcr_work_on = true;
+ } else {
+ pcr_set(session);
+ msync_dbg(LOG_INFO,
+ "[%d]%d video start %u w %u\n",
+ session->id, __LINE__,
+ pts, session->wall_clock);
+ }
+ }
+exit:
+ mutex_unlock(&session->session_mutex);
+ if (wakeup)
+ wait_up_poll(session);
+}
+
+static u32 session_audio_start(struct sync_session *session,
+ const struct audio_start *start)
+{
+ bool wakeup = false;
+ u32 ret = AVS_START_SYNC;
+ u32 pts = start->pts;
+ u32 start_pts = start->pts - start->delay;
+
+ session->a_active = true;
+ mutex_lock(&session->session_mutex);
+ if (session->audio_switching) {
+ update_f_apts(session, pts);
+ if (session->wall_clock > pts ||
+ session->start_policy != AMSYNC_START_ALIGN) {
+ /* audio start immediately pts to small */
+ /* (need drop) or no wait */
+ session->stat = AVS_STAT_STARTED;
+ msync_dbg(LOG_INFO,
+ "[%d]%d audio immediate start %u clock %u\n",
+ session->id, __LINE__, pts,
+ session->wall_clock);
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ !session->start_posted) {
+ session->start_posted = true;
+ wakeup = true;
+ }
+ } else if (session->start_policy == AMSYNC_START_ALIGN) {
+ // normal case, wait audio start point
+ u32 diff_ms = (pts - session->wall_clock) / 90;
+ u32 delay_jiffies = (diff_ms / 10) * HZ / 100;
+
+ msync_dbg(LOG_INFO,
+ "[%d]%d audio start %u def %u ms clock %u\n",
+ session->id, __LINE__,
+ pts, diff_ms, session->wall_clock);
+
+ if (session->audio_change_work_on)
+ cancel_delayed_work(
+ &session->audio_change_work);
+
+ queue_delayed_work(session->wq,
+ &session->audio_change_work,
+ delay_jiffies);
+ session->audio_change_work_on = true;
+ session->stat = AVS_STAT_TRANSITION;
+ ret = AVS_START_ASYNC;
+ }
+ } else if (session->mode == AVS_MODE_A_MASTER) {
+ session_set_wall_clock(session, start_pts);
+ update_f_apts(session, pts);
+
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ !VALID_PTS(session->first_vpts.pts)) {
+ msync_dbg(LOG_INFO, "[%d]%d audio start %u deferred\n",
+ session->id, __LINE__, pts);
+ if (session->wait_work_on)
+ cancel_delayed_work(&session->wait_work);
+ queue_delayed_work(session->wq,
+ &session->wait_work,
+ WAIT_INTERVAL);
+ session->wait_work_on = true;
+ session->stat = AVS_STAT_STARTING;
+ ret = AVS_START_ASYNC;
+ } else {
+ if (session->start_policy == AMSYNC_START_ALIGN) {
+ u32 vpts = session->first_vpts.pts;
+ u32 delay;
+
+ if ((int)(pts - vpts) <= 900) {
+ /* use audio as start */
+ msync_dbg(LOG_INFO,
+ "[%d]%d audio start %u\n",
+ session->id, __LINE__, pts);
+ session->clock_start = true;
+ session->start_posted = true;
+ session->stat = AVS_STAT_STARTED;
+ wakeup = true;
+ goto exit;
+ }
+ /* use video as start, delay audio start */
+ delay = (pts - vpts) / 900;
+ msync_dbg(LOG_INFO,
+ "[%d]%d audio start %u deferred %ums\n",
+ session->id, __LINE__, pts, delay * 10);
+ session_set_wall_clock(session, vpts);
+ session->clock_start = true;
+ if (session->wait_work_on)
+ cancel_delayed_work(&session->wait_work);
+ queue_delayed_work(session->wq,
+ &session->wait_work,
+ delay * TEN_MS_INTERVAL);
+ session->wait_work_on = true;
+ session->stat = AVS_STAT_STARTING;
+ } else
+ session->clock_start = true;
+ }
+ } else if (session->mode == AVS_MODE_IPTV) {
+ update_f_apts(session, pts);
+
+ if (session->start_policy == AMSYNC_START_ASAP &&
+ !VALID_PTS(session->first_vpts.pts)) {
+ session_set_wall_clock(session, start_pts);
+ session->clock_start = true;
+ session->stat = AVS_STAT_STARTED;
+ session->cur_mode = AVS_MODE_A_MASTER;
+ wakeup = true;
+ msync_dbg(LOG_INFO, "[%d]%d audio start %u\n",
+ session->id, __LINE__, pts);
+ } else if (session->start_policy == AMSYNC_START_ASAP) {
+ /* transition start from V to A master */
+ session->stat = AVS_STAT_TRANSITION;
+ /* enter grace period */
+ if (session->transit_work_on)
+ cancel_delayed_work(&session->transit_work);
+ queue_delayed_work(session->wq,
+ &session->transit_work,
+ TRANSIT_INTERVAL);
+ session->transit_work_on = true;
+ wakeup = true;
+ msync_dbg(LOG_INFO, "[%d]%d audio start %u\n",
+ session->id, __LINE__, pts);
+ }
+ } else if (session->mode == AVS_MODE_PCR_MASTER) {
+ msync_dbg(LOG_INFO, "[%d]%d audio start %u\n",
+ session->id, __LINE__, pts);
+ update_f_apts(session, pts);
+ if (session->start_policy == AMSYNC_START_ALIGN &&
+ session->pcr_work_on) {
+ cancel_delayed_work(&session->pcr_start_work);
+ session->pcr_work_on = false;
+ }
+ pcr_set(session);
+ session->stat = AVS_STAT_STARTED;
+ if (session->clock_start &&
+ (int)(pts - session->wall_clock) >
+ sync.start_buf_thres) {
+ ret = AVS_START_AGAIN;
+ msync_dbg(LOG_DEBUG, "[%d]%d audio drop %u\n",
+ session->id, __LINE__, pts);
+ }
+ }
+exit:
+ mutex_unlock(&session->session_mutex);
+ if (wakeup)
+ wait_up_poll(session);
+ return ret;
+}
+
+static void session_pause(struct sync_session *session, bool pause)
+{
+ mutex_lock(&session->session_mutex);
+ if (session->stat == AVS_STAT_STARTING) {
+ msync_dbg(LOG_INFO, "[%d]%s ignore pause %d during starting\n",
+ session->id, __func__, pause);
+ } else {
+ session->clock_start = !pause;
+ msync_dbg(LOG_INFO, "[%d]%s pause %d\n",
+ session->id, __func__, pause);
+ if (pause)
+ session->stat = AVS_STAT_PAUSED;
+ else
+ session->stat = AVS_STAT_STARTED;
+ }
+ mutex_unlock(&session->session_mutex);
+}
+
+static void session_video_stop(struct sync_session *session)
+{
+ session->v_active = false;
+ update_f_vpts(session, AVS_INVALID_PTS);
+
+ mutex_lock(&session->session_mutex);
+ if (!session->a_active) {
+ session->clock_start = false;
+ session->start_posted = false;
+ session->v_timeout = false;
+ msync_dbg(LOG_INFO, "[%d]%s clock stop\n",
+ session->id, __func__);
+ } else if (session->mode == AVS_MODE_IPTV) {
+ session->cur_mode = AVS_MODE_A_MASTER;
+ session_set_wall_clock(session, session->last_apts.wall_clock);
+ msync_dbg(LOG_INFO, "[%d]%s to Amaster\n",
+ session->id, __func__);
+ } else if (session->mode == AVS_MODE_PCR_MASTER) {
+ if (!session->a_active)
+ use_pcr_clock(session, true, 0);
+ session->first_vpts.pts = AVS_INVALID_PTS;
+ session->last_vpts.pts = AVS_INVALID_PTS;
+ session->pcr_disc_clock = AVS_INVALID_PTS;
+ session->last_check_vpts_cnt = 0;
+ session->pcr_disc_flag = 0;
+ session->first_time_record =
+ div64_u64((u64)jiffies * UNIT90K, HZ);
+ }
+ mutex_unlock(&session->session_mutex);
+ wait_up_poll(session);
+}
+
+static void session_audio_stop(struct sync_session *session)
+{
+ session->a_active = false;
+ update_f_apts(session, AVS_INVALID_PTS);
+
+ mutex_lock(&session->session_mutex);
+ if (!session->v_active) {
+ session->clock_start = false;
+ session->start_posted = false;
+ session->v_timeout = false;
+ msync_dbg(LOG_INFO, "[%d]%d clock stop\n",
+ session->id, __LINE__);
+ } else if (session->audio_switching) {
+ session->start_posted = false;
+ if (session->audio_change_work_on) {
+ cancel_delayed_work(&session->audio_change_work);
+ session->audio_change_work_on = false;
+ }
+ msync_dbg(LOG_INFO, "[%d]%s audio switching stop audio\n",
+ session->id, __func__);
+ } else if (session->mode == AVS_MODE_IPTV) {
+ session->cur_mode = AVS_MODE_V_MASTER;
+ session_set_wall_clock(session, session->last_vpts.wall_clock);
+
+ msync_dbg(LOG_INFO, "[%d]%s to Vmaster\n",
+ session->id, __func__);
+ } else if (session->mode == AVS_MODE_PCR_MASTER) {
+ if (!session->v_active)
+ use_pcr_clock(session, true, 0);
+ session->first_apts.pts = AVS_INVALID_PTS;
+ session->last_apts.pts = AVS_INVALID_PTS;
+ session->last_check_apts_cnt = 0;
+ }
+ mutex_unlock(&session->session_mutex);
+ wait_up_poll(session);
+}
+
+/*
+ *Video and audio PTS discontinuity happen typically with a loopback
+ *playback, with same bit stream play in loop and PTS wrap back from
+ *starting point.
+ *When video discontinuity happens first, wall clock is set
+ *immediately to keep video running in VMATSER mode. This
+ *mode is restored to AMASTER when audio discontinuity follows,
+ *or apts is close to wall clock in a later time.
+ *When audio discontinuity happens first, VMASTER mode is
+ *set to keep video running w/o setting wall clock. This mode
+ *is restored to AMASTER when video discontinuity follows.
+ *And wall clock is restored along with video time stamp.
+ */
+static void session_video_disc_iptv(struct sync_session *session, u32 pts)
+{
+ u32 last_pts = session->last_vpts.pts;
+ u32 wall = session->wall_clock;
+
+ if (session->mode != AVS_MODE_PCR_MASTER &&
+ session->mode != AVS_MODE_IPTV)
+ return;
+
+ mutex_lock(&session->session_mutex);
+ if (VALID_PTS(session->pcr_clock.pts))
+ wall = session->pcr_clock.pts;
+ if (VALID_PTS(session->pcr_clock.pts) &&
+ abs_diff(pts, last_pts) > session->disc_thres_min) {
+ session->v_disc = true;
+ if (session->a_disc) {
+ session->v_disc = false;
+ session->a_disc = false;
+ session_set_wall_clock(session, pts);
+ msync_dbg(LOG_INFO, "[%d]%s reset wall %u\n",
+ session->id, __func__, pts);
+ } else {
+ session_set_wall_clock(session, last_pts);
+ msync_dbg(LOG_INFO, "[%d]%s reset wall %u\n",
+ session->id, __func__, pts);
+ }
+ goto exit;
+ }
+ if (abs_diff(pts, last_pts) > session->disc_thres_min)
+ session->v_disc = true;
+exit:
+ mutex_unlock(&session->session_mutex);
+}
+
+static bool pcr_v_disc(struct sync_session *session, u32 pts)
+{
+ u32 pcr = pcr_get(session);
+
+ if (!VALID_PTS(pcr))
+ return false;
+ if (abs_diff(pts, pcr) > session->disc_thres_min)
+ return true;
+ return false;
+}
+
+static void session_video_disc_pcr(struct sync_session *session, u32 pts)
+{
+ mutex_lock(&session->session_mutex);
+ if (session->pcr_init_mode != INIT_PRIORITY_PCR) {
+ /* set wall clock */
+ session_set_wall_clock(session, pts);
+ } else if (pcr_v_disc(session, pts)) {
+ /* TODO: dead code */
+ u32 pcr = pcr_get(session);
+
+ if (session->use_pcr) {
+ if ((int)(pts - (pcr + 10 * UNIT90K)) > 0) {
+ use_pcr_clock(session, false, pts);
+ msync_dbg(LOG_DEBUG,
+ "[%d]%d disable pcr %u\n",
+ __LINE__, session->id, pts);
+ } else {
+ session_set_wall_clock(session, pts);
+ msync_dbg(LOG_DEBUG,
+ "[%d]%d vdisc set wall %u\n",
+ __LINE__, session->id, pts);
+ }
+ }
+ }
+ session->pcr_disc_flag |= VIDEO_DISC;
+ session->last_vpts.pts = pts;
+ session->last_vpts.wall_clock = session->wall_clock;
+ mutex_unlock(&session->session_mutex);
+}
+
+static void session_video_disc_v(struct sync_session *session, u32 pts)
+{
+ mutex_lock(&session->session_mutex);
+
+ msync_dbg(LOG_WARN, "[%d]vdisc reset wall %u --> %u\n",
+ session->id, session->wall_clock, pts);
+ session_set_wall_clock(session, pts);
+ session->last_vpts.pts = pts;
+ session->last_vpts.wall_clock = session->wall_clock;
+
+ mutex_unlock(&session->session_mutex);
+}
+
+static void session_audio_disc(struct sync_session *session, u32 pts)
+{
+ //u32 last_pts = session->last_apts.pts;
+
+ if (session->mode != AVS_MODE_PCR_MASTER &&
+ session->mode != AVS_MODE_IPTV)
+ return;
+ if (session->mode == AVS_MODE_PCR_MASTER) {
+ session->pcr_disc_flag |= AUDIO_DISC;
+ session->last_apts.pts = pts;
+ session->last_apts.wall_clock = session->wall_clock;
+ }
+}
+
+static void session_audio_switch(struct sync_session *session, u32 start)
+{
+ //u32 last_pts = session->last_apts.pts;
+ msync_dbg(LOG_WARN, "[%d] set audio switch to %u @ pos %u\n",
+ session->id, start, session->wall_clock);
+ session->audio_switching = start ? true : false;
+}
+
+static void session_update_vpts(struct sync_session *session)
+{
+#if 0
+ if (session->mode == AVS_MODE_V_MASTER) {
+ struct pts_tri *p = &session->last_vpts;
+ u32 pts = p->pts;
+
+ if (pts > p->delay)
+ pts -= p->delay;
+ if (abs_diff(pts, session->wall_clock) >=
+ session->wall_adj_thres) {
+ unsigned long flags;
+
+ msync_dbg(LOG_WARN, "[%d]v reset wall %u --> %u\n",
+ session->id, session->wall_clock, pts);
+ /* correct wall with vpts */
+ spin_lock_irqsave(&sync.lock, flags);
+ session->wall_clock = pts;
+ spin_unlock_irqrestore(&sync.lock, flags);
+ }
+ }
+#endif
+}
+
+static void session_update_apts(struct sync_session *session)
+{
+ if (session->mode == AVS_MODE_A_MASTER) {
+ struct pts_tri *p = &session->last_apts;
+ u32 pts = p->pts;
+
+ if (session->debug_freerun)
+ return;
+ if (pts > p->delay)
+ pts -= p->delay;
+ if (abs_diff(pts, session->wall_clock) >=
+ session->wall_adj_thres) {
+ unsigned long flags;
+
+ /* correct wall with apts */
+ msync_dbg(LOG_WARN, "[%d]a reset wall %u --> %u\n",
+ session->id, session->wall_clock, pts);
+ spin_lock_irqsave(&sync.lock, flags);
+ session->wall_clock = pts;
+ spin_unlock_irqrestore(&sync.lock, flags);
+ }
+ }
+}
+
+static void pcr_check(struct sync_session *session)
+{
+ u32 checkin_vpts = AVS_INVALID_PTS;
+ u32 checkin_apts = AVS_INVALID_PTS;
+ u32 min_pts = AVS_INVALID_PTS;
+ int max_gap = 40;
+ u32 flag, last_pts, gap_cnt = 0;
+
+ if (session->a_active) {
+ checkin_apts = session->last_apts.pts;
+ if (VALID_PTS(checkin_apts) &&
+ VALID_PTS(session->last_check_apts)) {
+ flag = session->pcr_disc_flag;
+ last_pts = session->last_check_apts;
+ gap_cnt = 0;
+
+ /* apts timeout */
+ if (abs_diff(last_pts, checkin_apts)
+ > session->disc_thres_max) {
+ session->pcr_disc_flag |= AUDIO_DISC;
+ msync_dbg(LOG_DEBUG, "[%d] %d adisc %x\n",
+ session->id, __LINE__,
+ session->pcr_disc_flag);
+ }
+ if (last_pts == checkin_apts) {
+ session->last_check_apts_cnt++;
+ if (session->last_check_apts_cnt > max_gap) {
+ session->pcr_disc_flag |= AUDIO_DISC;
+ gap_cnt = session->last_check_apts_cnt;
+ session->last_check_apts_cnt = 0;
+ }
+ } else {
+ session->last_check_apts = checkin_apts;
+ session->last_check_apts_cnt = 0;
+ }
+ if (flag != session->pcr_disc_flag)
+ msync_dbg(LOG_WARN,
+ "[%d] %d adisc f:%x %u --> %u x %u w %u\n",
+ session->id, __LINE__,
+ session->pcr_disc_flag,
+ last_pts,
+ checkin_apts,
+ gap_cnt,
+ session->wall_clock);
+ } else {
+ session->last_check_apts = checkin_apts;
+ }
+ }
+
+ if (session->v_active) {
+ checkin_vpts = session->last_vpts.pts;
+ if (VALID_PTS(checkin_vpts) &&
+ VALID_PTS(session->last_check_vpts)) {
+ flag = session->pcr_disc_flag;
+ last_pts = session->last_check_vpts;
+ gap_cnt = 0;
+
+ /* vpts timeout */
+ if (abs_diff(last_pts, checkin_vpts) > 2 * UNIT90K) {
+ session->pcr_disc_flag |= VIDEO_DISC;
+ } else if (last_pts == checkin_vpts) {
+ session->last_check_vpts_cnt++;
+ if (session->last_check_vpts_cnt > max_gap) {
+ session->pcr_disc_flag |= VIDEO_DISC;
+ gap_cnt = session->last_check_vpts_cnt;
+ session->last_check_vpts_cnt = 0;
+ }
+ } else {
+ session->last_check_vpts = checkin_vpts;
+ session->last_check_vpts_cnt = 0;
+ if (abs_diff(session->wall_clock,
+ checkin_vpts) < DISC_THRE_REC)
+ session->pcr_disc_flag &= ~(VIDEO_DISC);
+ }
+ if (flag != session->pcr_disc_flag)
+ msync_dbg(LOG_WARN,
+ "[%d] %d vdisc f:%x %u --> %u x %u w %u\n",
+ session->id, __LINE__,
+ session->pcr_disc_flag,
+ last_pts,
+ checkin_vpts,
+ gap_cnt,
+ session->wall_clock);
+ } else {
+ session->last_check_vpts = checkin_vpts;
+ }
+ }
+
+ if (session->use_pcr) {
+ if (VALID_PTS(session->pcr_clock.pts) &&
+ VALID_PTS(session->last_check_pcr_clock) &&
+ abs_diff(session->pcr_clock.pts,
+ session->last_check_pcr_clock) > PCR_DISC_THRES &&
+ session->pcr_init_flag) {
+ session->pcr_disc_flag |= PCR_DISC;
+ session->pcr_disc_clock = session->pcr_clock.pts;
+ msync_dbg(LOG_WARN, "[%d] %d pdisc f:%x %u --> %u\n",
+ session->id, __LINE__,
+ session->pcr_disc_flag,
+ session->last_check_vpts,
+ checkin_vpts);
+ } else if (PCR_DISC_SET(session->pcr_disc_flag) &&
+ VALID_PTS(session->pcr_disc_clock)) {
+ if (abs_diff(session->pcr_clock.pts,
+ session->pcr_disc_clock) > (4 * UNIT90K)) {
+ /* to pause the pcr check */
+ session->pcr_disc_flag = 0;
+ session->pcr_disc_clock =
+ AVS_INVALID_PTS;
+ msync_dbg(LOG_WARN, "[%d] %d pdisc reset\n",
+ session->id, __LINE__);
+ }
+ }
+ }
+
+ /* pcr discontinuity detection */
+ if (VALID_PTS(session->pcr_clock.pts) &&
+ VALID_PTS(session->last_check_pcr_clock) &&
+ abs_diff(session->pcr_clock.pts,
+ session->last_check_pcr_clock) > PCR_DISC_THRES) {
+ session->last_check_pcr_clock = session->pcr_clock.pts;
+ session->pcr_disc_cnt++;
+ session->pcr_cont_cnt = 0;
+ } else if (VALID_PTS(session->pcr_clock.pts)) {
+ session->last_check_pcr_clock = session->pcr_clock.pts;
+ session->pcr_cont_cnt++;
+ session->pcr_disc_cnt = 0;
+ }
+
+ //TODO nowhere to clear pcr_init_flag to 0
+ if (!session->pcr_init_flag) {
+ u64 cur_time = div64_u64((u64)jiffies * UNIT90K, HZ);
+
+ if (!VALID_PTS(checkin_apts) && !VALID_PTS(checkin_vpts)) {
+ session->first_time_record = cur_time;
+ } else if ((cur_time - session->first_time_record <
+ 3 * UNIT90K) && session->v_active) {
+ //do nothing
+ }
+ return;
+ }
+
+ if (session->pcr_init_mode != INIT_PRIORITY_PCR) {
+ if (V_DISC_SET(session->pcr_disc_flag) &&
+ VALID_PTS(checkin_apts) &&
+ VALID_PTS(checkin_vpts)) {
+ msync_dbg(LOG_INFO, "[%d] %d pcr_disc reset %u\n",
+ session->id, __LINE__, checkin_vpts);
+ use_pcr_clock(session, false, checkin_vpts);
+ session->pcr_disc_flag = 0;
+ }
+ return;
+ }
+
+ min_pts = pts_early(checkin_apts, checkin_vpts);
+ if (session->pcr_disc_cnt > 100 && VALID_PTS(min_pts)) {
+ min_pts -= sync.start_buf_thres;
+ msync_dbg(LOG_INFO, "[%d] %d pcr_disc reset %u\n",
+ session->id, __LINE__, min_pts);
+ session->pcr_init_mode = INIT_PRIORITY_VIDEO;
+ use_pcr_clock(session, false, min_pts);
+ }
+
+ /* TODO: dead code? */
+ if (!V_DISC_SET(session->pcr_disc_flag) &&
+ PCR_DISC_SET(session->pcr_disc_flag) &&
+ session->use_pcr) {
+ session->use_pcr = false;
+ msync_dbg(LOG_INFO, "[%d] %d pdisc ignored\n",
+ session->id, __LINE__);
+ }
+
+ if (A_DISC_SET(session->pcr_disc_flag) &&
+ V_DISC_SET(session->pcr_disc_flag) &&
+ VALID_PTS(checkin_apts) &&
+ VALID_PTS(checkin_vpts)) {
+
+ if (abs_diff(checkin_apts, checkin_vpts) <
+ session->disc_thres_min) {
+ min_pts -= sync.start_buf_thres;
+ use_pcr_clock(session, false, min_pts);
+ session->pcr_disc_flag = 0;
+ msync_dbg(LOG_INFO,
+ "[%d] %d disable pcr %u vs %u\n",
+ session->id, __LINE__, min_pts,
+ session->pcr_clock.pts);
+ }
+ }
+}
+
+static void pcr_timer_func(unsigned long arg)
+{
+ struct sync_session *session = (struct sync_session *)arg;
+
+ pcr_check(session);
+
+ session->pcr_timer.expires =
+ (unsigned long)(jiffies + TEN_MS_INTERVAL);
+
+ add_timer(&session->pcr_timer);
+}
+
+static const char *event_dbg[AVS_EVENT_MAX] = {
+ "video_start",
+ "pause",
+ "resume",
+ "video_stop",
+ "audio_stop",
+ "video_disc",
+ "audio_disc",
+ "audio_switch",
+};
+
+static void session_handle_event(struct sync_session *session,
+ const struct session_event *event)
+{
+ msync_dbg(LOG_DEBUG, "[%d]event %s/%u\n",
+ session->id,
+ event_dbg[event->event], event->value);
+ switch (event->event) {
+ case AVS_VIDEO_START:
+ session_video_start(session, event->value);
+ break;
+ case AVS_PAUSE:
+ session_pause(session, true);
+ break;
+ case AVS_RESUME:
+ session_pause(session, false);
+ break;
+ case AVS_VIDEO_STOP:
+ session_video_stop(session);
+ break;
+ case AVS_AUDIO_STOP:
+ session_audio_stop(session);
+ break;
+ case AVS_VIDEO_TSTAMP_DISCONTINUITY:
+ if (session->mode == AVS_MODE_IPTV)
+ session_video_disc_iptv(session, event->value);
+ else if (session->mode == AVS_MODE_PCR_MASTER)
+ session_video_disc_pcr(session, event->value);
+ else if (session->mode == AVS_MODE_V_MASTER)
+ session_video_disc_v(session, event->value);
+ break;
+ case AVS_AUDIO_TSTAMP_DISCONTINUITY:
+ session_audio_disc(session, event->value);
+ break;
+ case AVS_AUDIO_SWITCH:
+ session_audio_switch(session, event->value);
+ break;
+ default:
+ break;
+ }
+}
+
+static long session_ioctl(struct file *file, unsigned int cmd, ulong arg)
+{
+ struct sync_session *session = file->private_data;
+ void __user *argp = (void __user *)arg;
+
+ switch (cmd) {
+ case AMSYNCS_IOC_SET_MODE:
+ {
+ enum av_sync_mode mode;
+ bool wakeup = false;
+
+ get_user(mode, (u32 __user *)argp);
+ msync_dbg(LOG_INFO,
+ "session[%d] mode %d --> %d\n",
+ session->id, session->mode, mode);
+ mutex_lock(&session->session_mutex);
+ if (session->mode != AVS_MODE_PCR_MASTER &&
+ mode == AVS_MODE_PCR_MASTER &&
+ !session->pcr_timer_added) {
+ session->use_pcr = true;
+ session->pcr_init_mode = INIT_PRIORITY_PCR;
+
+ session->pcr_timer.data = (ulong)session;
+ session->pcr_timer.function = pcr_timer_func;
+ session->pcr_timer.expires = jiffies;
+
+ session->first_time_record =
+ div64_u64((u64)jiffies * UNIT90K, HZ);
+ add_timer(&session->pcr_timer);
+ session->pcr_timer_added = true;
+ session->mode = mode;
+ session->cur_mode = mode;
+ } else if (session->mode == AVS_MODE_PCR_MASTER &&
+ mode == AVS_MODE_FREE_RUN) {
+ session->cur_mode = AVS_MODE_FREE_RUN;
+ wakeup = true;
+ } else {
+ session->mode = mode;
+ }
+ mutex_unlock(&session->session_mutex);
+ if (wakeup)
+ wait_up_poll(session);
+ break;
+ }
+ case AMSYNCS_IOC_GET_MODE:
+ put_user(session->mode, (u32 __user *)argp);
+ break;
+ case AMSYNCS_IOC_SET_START_POLICY:
+ get_user(session->start_policy, (u32 __user *)argp);
+ msync_dbg(LOG_INFO, "session[%d] start policy %d\n",
+ session->id, session->start_policy);
+ break;
+ case AMSYNCS_IOC_GET_START_POLICY:
+ put_user(session->start_policy, (u32 __user *)argp);
+ break;
+ case AMSYNCS_IOC_SET_V_TS:
+ {
+ struct pts_tri ts;
+
+ if (!copy_from_user(&ts, argp, sizeof(ts))) {
+ if (!VALID_PTS(session->last_vpts.pts))
+ msync_dbg(LOG_DEBUG,
+ "session[%d] first vpts %u w %u\n",
+ session->id, ts.pts,
+ session->wall_clock);
+ session->last_vpts = ts;
+ session_update_vpts(session);
+ }
+ break;
+ }
+ case AMSYNCS_IOC_GET_V_TS:
+ {
+ if (copy_to_user(argp, &session->last_vpts, sizeof(struct pts_tri)))
+ return -EFAULT;
+ break;
+ }
+ case AMSYNCS_IOC_SET_A_TS:
+ {
+ struct pts_tri ts;
+
+ if (!copy_from_user(&ts, argp, sizeof(ts))) {
+ if (!VALID_PTS(session->last_apts.pts))
+ msync_dbg(LOG_DEBUG,
+ "session[%d] first apts %u w %u\n",
+ session->id, ts.pts,
+ session->wall_clock);
+ session->last_apts = ts;
+ session_update_apts(session);
+ }
+ break;
+ }
+ case AMSYNCS_IOC_GET_A_TS:
+ {
+ if (copy_to_user(argp, &session->last_apts, sizeof(struct pts_tri)))
+ return -EFAULT;
+ break;
+ }
+ case AMSYNCS_IOC_SEND_EVENT:
+ {
+ struct session_event event;
+
+ if (!copy_from_user(&event, argp, sizeof(event))) {
+ if (event.event >= AVS_EVENT_MAX)
+ return -EINVAL;
+ session_handle_event(session, &event);
+ }
+ break;
+ }
+ case AMSYNCS_IOC_GET_SYNC_STAT:
+ {
+ struct session_sync_stat stat;
+
+ if (session->mode != AVS_MODE_PCR_MASTER &&
+ session->mode != AVS_MODE_A_MASTER &&
+ session->mode != AVS_MODE_IPTV)
+ return -EINVAL;
+ stat.v_active = session->v_active;
+ stat.v_timeout = session->v_timeout;
+ stat.a_active = session->a_active;
+ stat.mode = session->cur_mode;
+ stat.audio_switch = session->audio_switching;
+ if (copy_to_user(argp, &stat, sizeof(stat)))
+ return -EFAULT;
+ session->event_pending = false;
+ break;
+ }
+ case AMSYNCS_IOC_SET_PCR:
+ {
+ struct pcr_pair pcr;
+
+ if (copy_from_user(&pcr, argp, sizeof(pcr)))
+ return -EFAULT;
+ if (!VALID_PTS(session->pcr_clock.pts))
+ msync_dbg(LOG_INFO, "[%d]pcr set %u\n",
+ __LINE__, pcr.pts);
+ mutex_lock(&session->session_mutex);
+ session->pcr_clock = pcr;
+ pcr_set(session);
+ mutex_unlock(&session->session_mutex);
+ break;
+ }
+ case AMSYNCS_IOC_GET_PCR:
+ if (copy_to_user(argp, &session->pcr_clock, sizeof(struct pcr_pair)))
+ return -EFAULT;
+ break;
+ case AMSYNCS_IOC_GET_WALL:
+ {
+ struct pts_wall wall;
+
+ wall.interval = sync.vsync_pts_inc;
+ if (session->mode != AVS_MODE_PCR_MASTER) {
+ if (session->clock_start)
+ wall.wall_clock = session->wall_clock;
+ else
+ wall.wall_clock = AVS_INVALID_PTS;
+ } else {
+ wall.wall_clock = session->wall_clock;
+ }
+ if (copy_to_user(argp, &wall, sizeof(struct pts_wall)))
+ return -EFAULT;
+ break;
+ }
+ case AMSYNCS_IOC_SET_RATE:
+ {
+ u32 rate;
+
+ get_user(rate, (u32 __user *)argp);
+ if (rate == 0 || rate > 10 * 1000) {
+ msync_dbg(LOG_ERR, "[%d]wrong rate %u\n",
+ session->id, rate);
+ return -EINVAL;
+ }
+ if (session->rate == rate)
+ return 0;
+ msync_dbg(LOG_WARN, "[%d]rate %u --> %u\n",
+ session->id, session->rate, rate);
+ session->rate = rate;
+ if (session->mode == AVS_MODE_A_MASTER)
+ wait_up_poll(session);
+ break;
+ }
+ case AMSYNCS_IOC_GET_RATE:
+ put_user(session->rate, (u32 __user *)argp);
+ break;
+ case AMSYNCS_IOC_SET_NAME:
+ if (strncpy_from_user(session->name,
+ (const char __user *)argp,
+ sizeof(session->name)))
+ return -EFAULT;
+ break;
+ case AMSYNCS_IOC_SET_WALL_ADJ_THRES:
+ get_user(session->wall_adj_thres, (u32 __user *)argp);
+ msync_dbg(LOG_WARN, "[%d]wall_adj_thres %d\n",
+ session->id, session->wall_adj_thres);
+ break;
+ case AMSYNCS_IOC_GET_WALL_ADJ_THRES:
+ put_user(session->wall_adj_thres, (u32 __user *)argp);
+ break;
+ case AMSYNCS_IOC_GET_CLOCK_START:
+ put_user(session->clock_start, (u32 __user *)argp);
+ break;
+ case AMSYNCS_IOC_AUDIO_START:
+ {
+ struct audio_start start;
+
+ if (!copy_from_user(&start, argp, sizeof(struct audio_start))) {
+ start.mode = session_audio_start(session, &start);
+ msync_dbg(LOG_DEBUG, "[%d]audio start mode %u\n",
+ session->id, start.mode);
+ }
+ if (copy_to_user(argp, &start, sizeof(struct audio_start)))
+ return -EFAULT;
+ break;
+ }
+ case AMSYNCS_IOC_GET_DEBUG_MODE:
+ {
+ struct session_debug debug;
+
+ debug.debug_freerun = session->debug_freerun;
+ debug.pcr_init_mode = session->pcr_init_mode;
+ debug.pcr_init_flag = session->pcr_init_flag;
+ if (copy_to_user(argp, &debug, sizeof(debug)))
+ return -EFAULT;
+ break;
+ }
+ case AMSYNCS_IOC_SET_CLK_DEV:
+ {
+ int dev;
+
+ get_user(dev, (int __user *)argp);
+ if (dev > 1000 || dev < -1000)
+ return -EINVAL;
+ session->clk_dev = dev;
+ //TODO change video PLL
+ msync_dbg(LOG_WARN, "[%d]clk dev %d\n",
+ session->id, dev);
+ break;
+ }
+ case AMSYNCS_IOC_GET_CLK_DEV:
+ {
+ put_user(session->clk_dev, (int __user *)argp);
+ break;
+ }
+ default:
+ break;
+ }
+ return 0;
+}
+
+#ifdef CONFIG_COMPAT
+static long session_compat_ioctl(struct file *filp, u32 cmd, ulong arg)
+{
+ long ret;
+
+ arg = (ulong)compat_ptr(arg);
+ ret = session_ioctl(filp, cmd, arg);
+ return ret;
+}
+#endif
+
+static int session_open(struct inode *inode, struct file *file)
+{
+ struct sync_session *session = NULL;
+ struct list_head *p;
+ int id = iminor(inode);
+ unsigned long flags;
+
+ spin_lock_irqsave(&sync.lock, flags);
+ list_for_each(p, &sync.head) {
+ session = list_entry(p, struct sync_session, node);
+ if (session->id == id)
+ break;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+
+ if (!session) {
+ msync_dbg(LOG_ERR, "can not find %d\n", id);
+ return -EBADF;
+ }
+
+ atomic_inc(&session->refcnt);
+ msync_dbg(LOG_DEBUG, "session[%d] open pid[%d]\n",
+ id, task_tgid_nr(current));
+ file->private_data = session;
+ return 0;
+}
+
+static void free_session(struct sync_session *session)
+{
+ unsigned long flags;
+
+ msync_dbg(LOG_INFO, "free session[%d]\n", session->id);
+ mutex_lock(&session->session_mutex);
+ if (session->wait_work_on)
+ cancel_delayed_work(&session->wait_work);
+ if (session->transit_work_on)
+ cancel_delayed_work(&session->transit_work);
+ if (session->pcr_work_on)
+ cancel_delayed_work(&session->pcr_start_work);
+ if (session->audio_change_work_on)
+ cancel_delayed_work(&session->audio_change_work);
+
+ if (session->pcr_timer_added)
+ del_timer_sync(&session->pcr_timer);
+ mutex_unlock(&session->session_mutex);
+
+ if (session->wq) {
+ flush_workqueue(session->wq);
+ destroy_workqueue(session->wq);
+ }
+
+ device_destroy(&session->session_class,
+ MKDEV(AMSYNC_SESSION_MAJOR, session->id));
+ class_unregister(&session->session_class);
+ vfree(session->session_class.name);
+
+ spin_lock_irqsave(&sync.lock, flags);
+ sync.id_pool[session->id] = 0;
+ spin_unlock_irqrestore(&sync.lock, flags);
+
+ vfree(session);
+}
+
+static int session_release(struct inode *inode, struct file *file)
+{
+ struct sync_session *session = file->private_data;
+
+ msync_dbg(LOG_DEBUG, "session[%d] close pid[%d]\n",
+ session->id, task_tgid_nr(current));
+ file->private_data = NULL;
+ if (atomic_dec_and_test(&session->refcnt))
+ free_session(session);
+ return 0;
+}
+
+static const struct file_operations session_fops = {
+ .owner = THIS_MODULE,
+ .open = session_open,
+ .release = session_release,
+ .unlocked_ioctl = session_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = session_compat_ioctl,
+#endif
+ .poll = session_poll,
+};
+
+static ssize_t session_stat_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session;
+
+ session = container_of(cla, struct sync_session, session_class);
+ return sprintf(buf,
+ "active v/%d a/%d\n"
+ "first v/%x a/%x\n"
+ "last v/%x a/%x\n"
+ "diff-ms a-w %d v-w %d a-v %d\n"
+ "start %d r %d\n"
+ "w %x pcr(%c) %x\n"
+ "audio switch %c\n",
+ session->v_active, session->a_active,
+ session->first_vpts.pts,
+ session->first_apts.pts,
+ session->last_vpts.pts,
+ session->last_apts.pts,
+ (int)(session->last_apts.pts - session->wall_clock) / 90,
+ (int)(session->last_vpts.pts - session->wall_clock) / 90,
+ (int)(session->last_apts.pts - session->last_vpts.pts) / 90,
+ session->clock_start, session->rate,
+ session->wall_clock,
+ session->use_pcr ? 'y' : 'n',
+ session->pcr_clock.pts,
+ session->audio_switching ? 'y' : 'n');
+}
+
+static ssize_t pcr_stat_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session;
+
+ session = container_of(cla, struct sync_session, session_class);
+ if (session->mode != AVS_MODE_PCR_MASTER)
+ return sprintf(buf, "not pcr master mode\n");
+
+ return sprintf(buf,
+ "init_flag %x\n"
+ "init_mode %x\n"
+ "pcr_disc_flag %x\n"
+ "pcr_cont (d)%u/(c)%u\n"
+ "pcr_disc_clock %x\n",
+ session->pcr_init_flag,
+ session->pcr_init_mode,
+ session->pcr_disc_flag,
+ session->pcr_disc_cnt,
+ session->pcr_cont_cnt,
+ session->pcr_disc_clock);
+}
+
+static ssize_t disc_thres_min_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session;
+
+ session = container_of(cla, struct sync_session, session_class);
+ return sprintf(buf, "%d", session->disc_thres_min);
+}
+
+static ssize_t disc_thres_min_store(struct class *cla,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ struct sync_session *session;
+ size_t r;
+
+ session = container_of(cla, struct sync_session, session_class);
+ r = kstrtoint(buf, 0, &session->disc_thres_min);
+ if (r != 0)
+ return -EINVAL;
+ return count;
+}
+
+static ssize_t disc_thres_max_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session;
+
+ session = container_of(cla, struct sync_session, session_class);
+ return sprintf(buf, "%d", session->disc_thres_max);
+}
+
+static ssize_t disc_thres_max_store(struct class *cla,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ struct sync_session *session;
+ size_t r;
+
+ session = container_of(cla, struct sync_session, session_class);
+ r = kstrtoint(buf, 0, &session->disc_thres_max);
+ if (r != 0)
+ return -EINVAL;
+ return count;
+}
+
+static ssize_t free_run_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session;
+
+ session = container_of(cla, struct sync_session, session_class);
+ return sprintf(buf, "%u", session->debug_freerun);
+}
+
+static ssize_t free_run_store(struct class *cla,
+ struct class_attribute *attr, const char *buf, size_t count)
+{
+ struct sync_session *session;
+ size_t r;
+
+ session = container_of(cla, struct sync_session, session_class);
+ r = kstrtobool(buf, &session->debug_freerun);
+ if (r != 0)
+ return -EINVAL;
+ wait_up_poll(session);
+ return count;
+}
+static struct class_attribute session_class_attrs[] = {
+ __ATTR_RO(session_stat),
+ __ATTR_RW(disc_thres_min),
+ __ATTR_RW(disc_thres_max),
+ __ATTR_RW(free_run),
+ __ATTR_RO(pcr_stat),
+ __ATTR_NULL
+};
+
+#define AVS_DEV_NAME_MAX 20
+static int create_session(u32 id)
+{
+ int r;
+ unsigned long flags;
+ char device_name[AVS_DEV_NAME_MAX];
+ char *class_name = NULL;
+ struct sync_session *session;
+
+ class_name = vmalloc(AVS_DEV_NAME_MAX);
+ if (!class_name) {
+ r = -ENOMEM;
+ goto err;
+ }
+
+ snprintf(device_name, AVS_DEV_NAME_MAX, "avsync_s%d", id);
+ snprintf(class_name, AVS_DEV_NAME_MAX, "avsync_session%d", id);
+
+ session = vzalloc(sizeof(*session));
+ if (!session) {
+ r = -ENOMEM;
+ goto err;
+ }
+ session->session_class.name = class_name;
+ session->session_class.class_attrs = session_class_attrs;
+
+ r = class_register(&session->session_class);
+ if (r) {
+ msync_dbg(LOG_ERR, "session %d class fail\n", id);
+ goto err2;
+ }
+
+ session->session_dev = device_create(&session->session_class, NULL,
+ MKDEV(AMSYNC_SESSION_MAJOR, id), NULL, device_name);
+ if (IS_ERR(session->session_dev)) {
+ msync_dbg(LOG_ERR, "Can't create avsync_session device %d\n", id);
+ r = -ENXIO;
+ goto err3;
+ }
+
+ session->wq = alloc_ordered_workqueue("avs_wq",
+ WQ_MEM_RECLAIM | WQ_FREEZABLE);
+ if (!session->wq) {
+ msync_dbg(LOG_ERR, "session %d create wq fail\n", id);
+ r = -EFAULT;
+ goto err4;
+ }
+
+ session->id = id;
+ atomic_set(&session->refcnt, 1);
+ init_waitqueue_head(&session->poll_wait);
+ session->rate = 1000;
+ session->stat = AVS_STAT_INIT;
+ strncpy(session->name, current->comm, sizeof(session->name));
+ session->first_vpts.pts = AVS_INVALID_PTS;
+ session->last_vpts.pts = AVS_INVALID_PTS;
+ session->first_apts.pts = AVS_INVALID_PTS;
+ session->last_apts.pts = AVS_INVALID_PTS;
+ session->wall_adj_thres = DEFAULT_WALL_ADJ_THRES;
+ session->lock = __SPIN_LOCK_UNLOCKED(session->lock);
+ session->disc_thres_min = DISC_THRE_MIN;
+ session->disc_thres_max = DISC_THRE_MAX;
+ session->pcr_clock.pts = AVS_INVALID_PTS;
+ session->last_check_apts = AVS_INVALID_PTS;
+ session->last_check_vpts = AVS_INVALID_PTS;
+ session->last_check_pcr_clock = AVS_INVALID_PTS;
+ session->pcr_disc_clock = AVS_INVALID_PTS;
+ INIT_DELAYED_WORK(&session->wait_work, wait_work_func);
+ INIT_DELAYED_WORK(&session->transit_work, transit_work_func);
+ INIT_DELAYED_WORK(&session->pcr_start_work, pcr_start_work_func);
+ INIT_DELAYED_WORK(&session->audio_change_work, audio_change_work_func);
+
+ mutex_init(&session->session_mutex);
+ spin_lock_irqsave(&sync.lock, flags);
+ list_add(&session->node, &sync.head);
+ spin_unlock_irqrestore(&sync.lock, flags);
+ msync_dbg(LOG_INFO, "av session %d created\n", id);
+ return 0;
+
+err4:
+ device_destroy(&session->session_class,
+ MKDEV(AMSYNC_SESSION_MAJOR, id));
+err3:
+ class_unregister(&session->session_class);
+err2:
+ vfree(session);
+err:
+ vfree(class_name);
+ return r;
+}
+
+static void destroy_session(u32 id)
+{
+ struct sync_session *session = NULL;
+ struct list_head *p;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sync.lock, flags);
+ list_for_each(p, &sync.head) {
+ session = list_entry(p, struct sync_session, node);
+ if (session->id == id)
+ break;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+ if (!session)
+ return;
+
+ spin_lock_irqsave(&sync.lock, flags);
+ list_del(&session->node);
+ spin_unlock_irqrestore(&sync.lock, flags);
+
+ if (atomic_dec_and_test(&session->refcnt))
+ free_session(session);
+ msync_dbg(LOG_INFO, "av session %d deref\n", id);
+}
+
+static long msync_ioctl(struct file *file, unsigned int cmd, ulong arg)
+{
+ u32 i;
+ int rc;
+ unsigned long flags;
+ void __user *argp = (void __user *)arg;
+
+ switch (cmd) {
+ case AMSYNC_IOC_ALLOC_SESSION:
+ {
+ struct msync_priv *priv = NULL;
+ spin_lock_irqsave(&sync.lock, flags);
+ for (i = 0 ; i < MAX_SESSION_NUM ; i++) {
+ if (!sync.id_pool[i]) {
+ sync.id_pool[i] = 1;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+ if (i >= MAX_SESSION_NUM) {
+ msync_dbg(LOG_ERR, "out of sync session\n");
+ return -EMFILE;
+ }
+
+ priv = vmalloc(sizeof(*priv));
+ if (!priv)
+ return -ENOMEM;
+
+ rc = create_session(i);
+ if (rc) {
+ spin_lock_irqsave(&sync.lock, flags);
+ sync.id_pool[i] = 0;
+ spin_unlock_irqrestore(&sync.lock, flags);
+ msync_dbg(LOG_ERR, "fail to create session %d\n", i);
+ vfree(priv);
+ return rc;
+ }
+ put_user(i, (u32 __user *)argp);
+ priv->session_id = i;
+ file->private_data = priv;
+ break;
+ }
+ case AMSYNC_IOC_REMOVE_SESSION:
+ {
+ u32 id;
+
+ get_user(id, (u32 __user *)argp);
+ if (id >= MAX_SESSION_NUM) {
+ msync_dbg(LOG_ERR, "destroy invalid id %d\n", id);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&sync.lock, flags);
+ if (!sync.id_pool[id]) {
+ spin_unlock_irqrestore(&sync.lock, flags);
+ return -EBADF;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+
+ destroy_session(id);
+ vfree(file->private_data);
+ file->private_data = NULL;
+ break;
+ }
+ default:
+ break;
+ }
+ return 0;
+}
+
+#ifdef CONFIG_COMPAT
+static long msync_compat_ioctl(struct file *filp, u32 cmd, ulong arg)
+{
+ long ret;
+
+ arg = (ulong)compat_ptr(arg);
+ ret = msync_ioctl(filp, cmd, arg);
+ return ret;
+}
+#endif
+
+static int msync_open(struct inode *inode, struct file *file)
+{
+ file->private_data = NULL;
+ return 0;
+}
+
+static int msync_release(struct inode *inode, struct file *file)
+{
+ struct msync_priv *priv = file->private_data;
+ int id = MAX_SESSION_NUM;
+ unsigned long flags;
+
+ if (!priv)
+ return 0;
+ id = priv->session_id;
+ if (id >= MAX_SESSION_NUM) {
+ msync_dbg(LOG_ERR, "destroy invalid id %d\n", id);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&sync.lock, flags);
+ if (!sync.id_pool[id]) {
+ spin_unlock_irqrestore(&sync.lock, flags);
+ return -EBADF;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+
+ destroy_session(id);
+ vfree(priv);
+ file->private_data = NULL;
+ return 0;
+}
+
+static const struct file_operations msync_fops = {
+ .owner = THIS_MODULE,
+ .open = msync_open,
+ .release = msync_release,
+ .unlocked_ioctl = msync_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = msync_compat_ioctl,
+#endif
+};
+
+static ssize_t log_level_show(struct class *cla,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d\n", log_level);
+}
+
+static ssize_t log_level_store(struct class *cla,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ int r;
+
+ r = kstrtoint(buf, 0, &log_level);
+ if (r < 0)
+ return -EINVAL;
+
+ return count;
+}
+
+static ssize_t vout_mode_show(struct class *cla,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "den %d num %d inc %d\n",
+ sync.sync_duration_den,
+ sync.sync_duration_num,
+ sync.vsync_pts_inc);
+}
+
+static ssize_t list_session_show(struct class *cla,
+ struct class_attribute *attr, char *buf)
+{
+ struct sync_session *session = NULL;
+ struct list_head *p;
+ unsigned long flags;
+ char tmp[256];
+ int i = 0;
+
+ spin_lock_irqsave(&sync.lock, flags);
+ list_for_each(p, &sync.head) {
+ session = list_entry(p, struct sync_session, node);
+ i += snprintf(tmp + i, sizeof(tmp) - i,
+ "%d: %s\n", session->id, session->name);
+ if (i >= sizeof(tmp))
+ break;
+ }
+ spin_unlock_irqrestore(&sync.lock, flags);
+ if (i == 0)
+ return sprintf(buf, "empty\n");
+
+ return snprintf(buf, sizeof(tmp), "%s", tmp);
+}
+
+static ssize_t start_buf_thres_show(struct class *cla,
+ struct class_attribute *attr, char *buf) {
+ return sprintf(buf, "%d in 90K unit\n",
+ sync.start_buf_thres);
+}
+
+static ssize_t start_buf_thres_store(struct class *cla,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ int r, thres;
+
+ r = kstrtouint(buf, 0, &thres);
+ if (r != 0)
+ return -EINVAL;
+ if (thres >= UNIT90K) {
+ msync_dbg(LOG_ERR, "must less than 90K");
+ return -EINVAL;
+ }
+ sync.start_buf_thres = thres;
+ return count;
+}
+
+static struct class_attribute msync_class_attrs[] = {
+ __ATTR_RW(log_level),
+ __ATTR_RO(list_session),
+ __ATTR_RO(vout_mode),
+ __ATTR_RW(start_buf_thres),
+ __ATTR_NULL
+};
+
+static struct class msync_class = {
+ .name = "aml_msync",
+ .class_attrs = msync_class_attrs,
+};
+
+static int __init msync_init(void)
+{
+ int r = 0;
+
+ r = register_chrdev(AMSYNC_MAJOR, "aml_msync", &msync_fops);
+ if (r < 0) {
+ msync_dbg(LOG_ERR,
+ "Can't register major for aml_msync device\n");
+ return r;
+ }
+ sync.multi_sync_major = r;
+
+ r = register_chrdev(AMSYNC_SESSION_MAJOR, "aml_msync_session", &session_fops);
+ if (r < 0) {
+ msync_dbg(LOG_ERR,
+ "Can't register major for aml_msync_session device\n");
+ goto err;
+ }
+ sync.session_major = r;
+
+ r = class_register(&msync_class);
+ if (r) {
+ msync_dbg(LOG_ERR, "msync class fail.\n");
+ goto err2;
+ }
+
+ sync.msync_dev = device_create(&msync_class, NULL,
+ MKDEV(AMSYNC_MAJOR, 0), NULL, "aml_msync");
+
+ if (IS_ERR(sync.msync_dev)) {
+ msync_dbg(LOG_ERR, "Can't create aml_msync device\n");
+ r = -ENXIO;
+ goto err3;
+ }
+ sync.lock = __SPIN_LOCK_UNLOCKED(sync.lock);
+ INIT_LIST_HEAD(&sync.head);
+ msync_update_mode();
+ sync.msync_notifier.notifier_call = msync_notify_callback;
+ vout_register_client(&sync.msync_notifier);
+ sync.ready = true;
+ sync.start_buf_thres = UNIT90K / 10;
+ return 0;
+err3:
+ class_unregister(&msync_class);
+err2:
+ unregister_chrdev(AMSYNC_SESSION_MAJOR, "aml_msync_session");
+err:
+ unregister_chrdev(AMSYNC_MAJOR, "aml_msync");
+ return r;
+}
+
+static void __exit msync_exit(void)
+{
+ if (sync.msync_dev) {
+ class_unregister(&msync_class);
+ device_destroy(&msync_class, MKDEV(AMSYNC_MAJOR, 0));
+ }
+ unregister_chrdev(AMSYNC_MAJOR, "aml_msync");
+}
+
+#ifndef MODULE
+module_init(msync_init);
+module_exit(msync_exit);
+#endif
+
+MODULE_LICENSE("GPL");
}
EXPORT_SYMBOL(canvas_get_height);
/*********************************************************/
-#define to_canvas(kobj) container_of(kobj, struct canvas_s, kobj)
-static ssize_t addr_show(struct canvas_s *canvas, char *buf)
-{
- return sprintf(buf, "0x%lx\n", canvas->addr);
-}
-
-static ssize_t width_show(struct canvas_s *canvas, char *buf)
-{
- return sprintf(buf, "%d\n", canvas->width);
-}
-
-static ssize_t height_show(struct canvas_s *canvas, char *buf)
-{
- return sprintf(buf, "%d\n", canvas->height);
-}
-
-static ssize_t show_canvas(struct canvas_s *canvas, char *buf)
-{
- int l = 0;
-
- l = sprintf(buf + l, "index:0x%x\n", (unsigned int)canvas->index);
- l += sprintf(buf + l, "addr:0x%x\n", (unsigned int)canvas->addr);
- l += sprintf(buf + l, "height:%d\n", canvas->height);
- l += sprintf(buf + l, "width:%d\n", canvas->width);
- l += sprintf(buf + l, "wrap:%d\n", canvas->wrap);
- l += sprintf(buf + l, "blkmode:%d\n", canvas->blkmode);
- l += sprintf(buf + l, "endian:%d\n", canvas->endian);
- l += sprintf(buf + l, "datal:%x\n", canvas->dataL);
- l += sprintf(buf + l, "datah:%x\n", canvas->dataH);
- return l;
-}
-
-static ssize_t config_show(struct canvas_s *canvas, char *buf)
-{
- return show_canvas(canvas, buf);
-}
-
-static ssize_t confighw_show(struct canvas_s *canvas, char *buf)
-{
- struct canvas_s hwcanvas;
-
- memset(&hwcanvas, 0, sizeof(hwcanvas));
- hwcanvas.index = canvas->index;
- canvas_read_hw(canvas->index, &hwcanvas);
- return show_canvas(&hwcanvas, buf);
-}
-
-static ssize_t confighw_store(struct canvas_s *canvas,
- const char *buf, size_t size)
-{
- /*TODO FOR DEBUG
- *
- *ulong addr;
- *u32 width;
- *u32 height;
- *u32 wrap;
- *u32 blkmode;
- *u32 endian;
- *int ret;
- *
- *ret = sscanf(buf, "0x%x %d %d %d %d %d\n",
- *(unsigned int *)&addr, &width,
- *&height, &wrap, &blkmode, &endian);
- *if (ret != 6) {
- *pr_err("get parameters %d\n", ret);
- *pr_err("usage: echo 0xaddr width height wrap blk end >\n");
- *return -EIO;
- *}
- *canvas->addr = addr;
- *canvas->width = width;
- *canvas->height = height;
- *canvas->wrap = wrap;
- *canvas->blkmode = blkmode;
- *canvas->endian = endian;
- *
- *canvas_config_locked(canvas->index, canvas);
- */
- return 0;
-}
-
-struct canvas_sysfs_entry {
- struct attribute attr;
-
- ssize_t (*show)(struct canvas_s *, char *);
- ssize_t (*store)(struct canvas_s *, const char *, size_t);
-};
-
-static struct canvas_sysfs_entry addr_attribute = __ATTR_RO(addr);
-static struct canvas_sysfs_entry width_attribute = __ATTR_RO(width);
-static struct canvas_sysfs_entry height_attribute = __ATTR_RO(height);
-static struct canvas_sysfs_entry config_attribute = __ATTR_RO(config);
-static struct canvas_sysfs_entry confighw_attribute = __ATTR_RW(confighw);
-
-static void canvas_release(struct kobject *kobj)
-{
-}
-
-static ssize_t canvas_type_show(struct kobject *kobj, struct attribute *attr,
- char *buf)
-{
- struct canvas_s *canvas = to_canvas(kobj);
- struct canvas_sysfs_entry *entry;
-
- entry = container_of(attr, struct canvas_sysfs_entry, attr);
-
- if (!entry->show)
- return -EIO;
-
- return entry->show(canvas, buf);
-}
-
-static ssize_t canvas_type_store(struct kobject *kobj, struct attribute *attr,
- const char *buf, size_t size)
-{
- struct canvas_s *canvas = to_canvas(kobj);
- struct canvas_sysfs_entry *entry;
-
- entry = container_of(attr, struct canvas_sysfs_entry, attr);
-
- if (!entry->store)
- return -EIO;
-
- return entry->store(canvas, buf, size);
-}
-
-static const struct sysfs_ops canvas_sysfs_ops = {
- .show = canvas_type_show,
- .store = canvas_type_store,
-};
-
-static struct attribute *canvas_attrs[] = {
- &addr_attribute.attr,
- &width_attribute.attr,
- &height_attribute.attr,
- &config_attribute.attr,
- &confighw_attribute.attr,
- NULL,
-};
-
-static struct kobj_type canvas_attr_type = {
- .release = canvas_release,
- .sysfs_ops = &canvas_sysfs_ops,
- .default_attrs = canvas_attrs,
-};
-
/* static int __devinit canvas_probe(struct platform_device *pdev) */
static int canvas_probe(struct platform_device *pdev)
{
- int i, r;
+ int r;
struct canvas_device_info *info = &canvas_info;
struct resource *res;
int size;
memset(info->canvasPool, 0, CANVAS_MAX_NUM * sizeof(struct canvas_s));
info->max_canvas_num = canvas_pool_canvas_num();
spin_lock_init(&info->lock);
- for (i = 0; i < info->max_canvas_num; i++) {
- info->canvasPool[i].index = i;
- r = kobject_init_and_add(&info->canvasPool[i].kobj,
- &canvas_attr_type,
- &pdev->dev.kobj, "%d", i);
- if (r) {
- pr_error("Unable to create canvas objects %d\n", i);
- goto err2;
- }
- }
info->canvas_dev = pdev;
return 0;
-
-err2:
- for (i--; i >= 0; i--)
- kobject_put(&info->canvasPool[i].kobj);
- amcanvas_manager_exit();
- devm_iounmap(&pdev->dev, info->reg_base);
err1:
devm_release_mem_region(&pdev->dev, res->start, size);
pr_error("Canvas driver probe failed\n");
#define RES_IS_MAPED
#define DEFAULT_TVP_SIZE_FOR_4K (236 * SZ_1M)
#define DEFAULT_TVP_SIZE_FOR_NO4K (160 * SZ_1M)
+#define DEFAULT_TVP_SEGMENT_MIN_SIZE (16 * SZ_1M)
#define ALLOC_MAX_RETRY 1
static int default_tvp_size;
static int default_tvp_4k_size;
static int default_cma_res_size;
-
+static int default_tvp_pool_segment_size[4];
+static int default_tvp_4k_pool_segment_size[4];
+static int default_tvp_pool_size_0;
+static int default_tvp_pool_size_1;
+static int default_tvp_pool_size_2;
+static int default_tvp_4k_pool_size_0;
+static int default_tvp_4k_pool_size_1;
+static int default_tvp_4k_pool_size_2;
+static u32 tvp_dynamic_increase_disable;
+
+#define TVP_POOL_SEGMENT_MAX_USED 4
+#define TVP_POOL_SEGMENT_USED_NORMAL 3
#define TVP_MAX_SLOT 8
/*
*tvp_mode == 0 means protect secure memory in secmem ta
#define VAL_OFF_VAL(mem, off) (*(unsigned long *)((unsigned long)(mem) + off))
static int codec_mm_extpool_pool_release(struct extpool_mgt_s *tvp_pool);
+static int codec_mm_tvp_pool_alloc_by_slot(struct extpool_mgt_s *tvp_pool,
+ int memflags, int flags);
+static int codec_mm_tvp_pool_unprotect_and_release(
+ struct extpool_mgt_s *tvp_pool);
static struct codec_mm_mgt_s *get_mem_mgt(void)
{
return have_found;
}
+static int codec_mm_alloc_tvp_pre_check_in(
+ struct codec_mm_mgt_s *mgt, int need_size, int flags)
+{
+ struct extpool_mgt_s *tvp_pool = &mgt->tvp_pool;
+ int i = 0;
+
+ for (i = 0; i < tvp_pool->slot_num; i++) {
+ if (gen_pool_avail(tvp_pool->gen_pool[i]) >= need_size)
+ return 1;
+ }
+ return 0;
+}
/*
*have_space:
if (aligned_size / PAGE_SIZE <= mgt->alloc_from_sys_pages_max)
have_space |= 4;
- if (aligned_size <= mgt->tvp_pool.total_size -
- mgt->tvp_pool.alloced_size)
- have_space |= 8;
-
- if (flags & 1)
- have_space = have_space & 8;
+ if (tvp_dynamic_increase_disable) {
+ if (aligned_size <= mgt->tvp_pool.total_size -
+ mgt->tvp_pool.alloced_size)
+ have_space |= 8;
+ } else {
+ if (flags & CODEC_MM_FLAGS_TVP) {
+ if (codec_mm_alloc_tvp_pre_check_in(mgt, aligned_size,
+ flags)) {
+ have_space |= 8;
+ } else {
+ do {
+ if (codec_mm_tvp_pool_alloc_by_slot(
+ &mgt->tvp_pool, 0,
+ mgt->tvp_enable) == 0) {
+ pr_err("no more memory can be alloc %d",
+ mgt->tvp_enable);
+ break;
+ }
+ if (codec_mm_alloc_tvp_pre_check_in(mgt,
+ aligned_size,
+ flags)) {
+ have_space |= 8;
+ break;
+ }
+ } while (mgt->tvp_pool.slot_num
+ <= TVP_POOL_SEGMENT_MAX_USED);
+ }
+ }
+ }
if (debug_mode & 0xf) {
have_space = have_space & (~(debug_mode & 1));
can_from_cma = 0;
}
- have_space = codec_mm_alloc_pre_check_in(mgt, mem->buffer_size, 0);
+ have_space = codec_mm_alloc_pre_check_in(mgt, mem->buffer_size,
+ mem->flags);
if (!have_space)
return -10001;
int aligned_buffer_size = ALIGN(mem->buffer_size,
(1 << RESERVE_MM_ALIGNED_2N));
alloc_trace_mask |= 1 << 5;
- mem->mem_handle = (void *)codec_mm_extpool_alloc(
+ if (tvp_dynamic_increase_disable) {
+ mem->mem_handle =
+ (void *)codec_mm_extpool_alloc(
&mgt->tvp_pool,
&mem->from_ext,
aligned_buffer_size);
- mem->from_flags =
- AMPORTS_MEM_FLAGS_FROM_GET_FROM_TVP;
- if (mem->mem_handle) {
- /*no vaddr for TVP MEMORY */
- mem->vbuffer = NULL;
- mem->phy_addr = (unsigned long)mem->mem_handle;
- mem->buffer_size = aligned_buffer_size;
- break;
+ mem->from_flags =
+ AMPORTS_MEM_FLAGS_FROM_GET_FROM_TVP;
+ if (mem->mem_handle) {
+ /*no vaddr for TVP MEMORY */
+ mem->vbuffer = NULL;
+ mem->phy_addr =
+ (unsigned long)mem->mem_handle;
+ mem->buffer_size = aligned_buffer_size;
+ break;
+ }
+ } else {
+ do {
+ mem->mem_handle =
+ (void *)codec_mm_extpool_alloc(
+ &mgt->tvp_pool,
+ &mem->from_ext,
+ aligned_buffer_size);
+ if (mem->mem_handle) {
+ /*no vaddr for TVP MEMORY */
+ mem->from_flags =
+ AMPORTS_MEM_FLAGS_FROM_GET_FROM_TVP;
+ mem->vbuffer = NULL;
+ mem->phy_addr = (unsigned long)
+ mem->mem_handle;
+ mem->buffer_size =
+ aligned_buffer_size;
+ break;
+ }
+ if (codec_mm_tvp_pool_alloc_by_slot(
+ &mgt->tvp_pool, 0,
+ mgt->tvp_enable) == 0) {
+ pr_err("no more memory can be alloc %d",
+ mgt->tvp_enable);
+ break;
+ }
+ } while (mgt->tvp_pool.slot_num <=
+ TVP_POOL_SEGMENT_MAX_USED);
}
}
}
}
-static int codec_mm_tvp_pool_unprotect(struct extpool_mgt_s *tvp_pool)
-{
- struct codec_mm_mgt_s *mgt = get_mem_mgt();
- int ret = -1;
- int i = 0;
-
- if (mgt->tvp_pool.alloced_size <= 0) {
- for (i = 0; i < tvp_pool->slot_num; i++) {
- pr_info("unprotect tvp %d handle is %d\n",
- i, tvp_pool->mm[i]->tvp_handle);
- if (tvp_pool->mm[i]->tvp_handle > 0) {
- tee_unprotect_tvp_mem(
- tvp_pool->mm[i]->tvp_handle);
- tvp_pool->mm[i]->tvp_handle = -1;
- }
- }
- ret = 0;
- }
- return ret;
-}
-
static void codec_mm_free_in(struct codec_mm_mgt_s *mgt,
struct codec_mm_s *mem)
{
spin_unlock_irqrestore(&mgt->lock, flags);
if ((mem->from_flags == AMPORTS_MEM_FLAGS_FROM_GET_FROM_TVP) &&
- (tvp_mode >= 1)) {
+ (tvp_mode >= 1)) {
mutex_lock(&mgt->tvp_protect_lock);
if (atomic_read(&mgt->tvp_user_count) == 0) {
- if (codec_mm_tvp_pool_unprotect(&mgt->tvp_pool) == 0) {
- codec_mm_extpool_pool_release(&mgt->tvp_pool);
+ if (codec_mm_tvp_pool_unprotect_and_release(
+ &mgt->tvp_pool) == 0) {
mgt->tvp_enable = 0;
pr_info("disalbe tvp\n");
}
return slot_num_start;
}
+static int codec_mm_tvp_pool_alloc_by_type(
+ struct extpool_mgt_s *tvp_pool,
+ int size, int memflags, int type)
+{
+ struct codec_mm_s *mem;
+ int ret;
+
+ if (type == CODEC_MM_FLAGS_CMA) {
+ mem = codec_mm_alloc(TVP_POOL_NAME,
+ size,
+ RESERVE_MM_ALIGNED_2N,
+ CODEC_MM_FLAGS_FOR_LOCAL_MGR |
+ CODEC_MM_FLAGS_CMA);
+ if (mem) {
+ struct page *mm = mem->mem_handle;
+
+ if (mem->from_flags ==
+ AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA_RES)
+ mm = phys_to_page((unsigned long)mm);
+ cma_mmu_op(mm, mem->page_count, 0);
+ ret = codec_mm_init_tvp_pool(tvp_pool, mem);
+ if (ret < 0) {
+ cma_mmu_op(mm, mem->page_count, 1);
+ codec_mm_release(mem, TVP_POOL_NAME);
+ } else {
+ tvp_pool->total_size += size;
+ tvp_pool->slot_num++;
+ if (tvp_mode >= 1) {
+ if (codec_mm_tvp_pool_protect
+ (tvp_pool)) {
+ codec_mm_extpool_pool_release_inner(
+ tvp_pool->slot_num - 1,
+ tvp_pool);
+ return 1;
+ }
+ }
+ return 0;
+ }
+ }
+ } else if (type == CODEC_MM_FLAGS_RESERVED) {
+ mem = codec_mm_alloc(TVP_POOL_NAME,
+ size,
+ RESERVE_MM_ALIGNED_2N,
+ CODEC_MM_FLAGS_FOR_LOCAL_MGR |
+ CODEC_MM_FLAGS_RESERVED);
+
+ if (mem) {
+ ret = codec_mm_init_tvp_pool(
+ tvp_pool, mem);
+ if (ret < 0) {
+ codec_mm_release(mem, TVP_POOL_NAME);
+ } else {
+ tvp_pool->total_size += size;
+ tvp_pool->slot_num++;
+ if (tvp_mode >= 1) {
+ if (codec_mm_tvp_pool_protect
+ (tvp_pool)) {
+ codec_mm_extpool_pool_release_inner(
+ tvp_pool->slot_num - 1,
+ tvp_pool);
+ return 1;
+ }
+ }
+ return 0;
+ }
+ }
+ }
+ return 1;
+}
+
+static int codec_mm_tvp_pool_alloc_by_slot(
+ struct extpool_mgt_s *tvp_pool, int memflags, int flags)
+{
+ struct codec_mm_mgt_s *mgt = get_mem_mgt();
+ int size = 0;
+ int try_alloced_size = 0;
+ int max_reserved_free_size = 0;
+ int max_cma_free_size = 0;
+ int use_cma_pool_first = 0;
+ int retry_cnt = 0;
+ int need_add_size = 0;
+ int needed_total_size = 0;
+ int i = 0;
+
+ mutex_lock(&tvp_pool->pool_lock);
+ max_reserved_free_size = mgt->total_reserved_size
+ - mgt->alloced_res_size;
+ max_cma_free_size = mgt->total_cma_size - mgt->alloced_cma_size;
+ use_cma_pool_first = max_cma_free_size > max_reserved_free_size ? 1 : 0;
+
+ if (flags == 1) {
+ if (tvp_pool->slot_num >= TVP_POOL_SEGMENT_USED_NORMAL) {
+ try_alloced_size = 0;
+ pr_info("slot_num exceed the limit %d\n",
+ tvp_pool->slot_num);
+ goto alloced_finished;
+ }
+ size = default_tvp_pool_segment_size[tvp_pool->slot_num];
+ for (i = 0; i < tvp_pool->slot_num; i++)
+ needed_total_size += default_tvp_pool_segment_size[i];
+ } else {
+ if (tvp_pool->slot_num >= TVP_POOL_SEGMENT_MAX_USED) {
+ try_alloced_size = 0;
+ pr_info("slot_num for 4k exceed the limit %d\n",
+ tvp_pool->slot_num);
+ goto alloced_finished;
+ }
+ size = default_tvp_4k_pool_segment_size[tvp_pool->slot_num];
+ for (i = 0; i < tvp_pool->slot_num; i++)
+ needed_total_size +=
+ default_tvp_4k_pool_segment_size[i];
+ }
+
+ if (needed_total_size > 0) {
+ if (needed_total_size >= tvp_pool->total_size) {
+ need_add_size = needed_total_size
+ - tvp_pool->total_size;
+ } else {
+ pr_info("have alloc engouth buffer %d %d",
+ needed_total_size, tvp_pool->total_size);
+ try_alloced_size = size;
+ goto alloced_finished;
+ }
+ }
+ size += need_add_size;
+ if (size <= 0) {
+ try_alloced_size = 0;
+ goto alloced_finished;
+ }
+
+ if (use_cma_pool_first) {
+ try_alloced_size = size > max_cma_free_size
+ ? max_cma_free_size : size;
+ try_alloced_size = MM_ALIGN_DOWN_2N(try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ retry_cnt = try_alloced_size / (4 * SZ_1M);
+ if (try_alloced_size > 0) {
+ int retry = 0;
+
+ do {
+ if (codec_mm_tvp_pool_alloc_by_type(tvp_pool,
+ try_alloced_size, memflags,
+ CODEC_MM_FLAGS_CMA)) {
+ try_alloced_size = try_alloced_size
+ - 4 * SZ_1M;
+ if (try_alloced_size < 16 * SZ_1M)
+ break;
+ try_alloced_size = MM_ALIGN_UP2N(
+ try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ } else {
+ goto alloced_finished;
+ }
+ } while (retry++ < retry_cnt);
+ }
+ } else {
+ try_alloced_size = size > max_reserved_free_size
+ ? max_reserved_free_size : size;
+ try_alloced_size = MM_ALIGN_DOWN_2N(try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ retry_cnt = try_alloced_size / (4 * SZ_1M);
+ if (try_alloced_size > 0) {
+ int retry = 0;
+
+ do {
+ if (codec_mm_tvp_pool_alloc_by_type(tvp_pool,
+ try_alloced_size, memflags,
+ CODEC_MM_FLAGS_RESERVED)) {
+ try_alloced_size = try_alloced_size
+ - 4 * SZ_1M;
+ if (try_alloced_size < 16 * SZ_1M)
+ break;
+ try_alloced_size = MM_ALIGN_UP2N(
+ try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ } else {
+ goto alloced_finished;
+ }
+ } while (retry++ < retry_cnt);
+ }
+ }
+
+ if (use_cma_pool_first) {
+ try_alloced_size = size > max_reserved_free_size
+ ? max_reserved_free_size : size;
+ try_alloced_size = MM_ALIGN_DOWN_2N(try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ retry_cnt = try_alloced_size / (4 * SZ_1M);
+ if (try_alloced_size > 0) {
+ int retry = 0;
+
+ do {
+ if (codec_mm_tvp_pool_alloc_by_type(tvp_pool,
+ try_alloced_size, memflags,
+ CODEC_MM_FLAGS_RESERVED)) {
+ try_alloced_size = try_alloced_size
+ - 4 * SZ_1M;
+ if (try_alloced_size < 16 * SZ_1M)
+ break;
+ try_alloced_size = MM_ALIGN_UP2N(
+ try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ } else {
+ goto alloced_finished;
+ }
+ } while (retry++ < retry_cnt);
+ }
+ } else {
+ try_alloced_size = size > max_cma_free_size
+ ? max_cma_free_size : size;
+ try_alloced_size = MM_ALIGN_DOWN_2N(try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ retry_cnt = try_alloced_size / (4 * SZ_1M);
+ if (try_alloced_size > 0) {
+ int retry = 0;
+
+ do {
+ if (codec_mm_tvp_pool_alloc_by_type(tvp_pool,
+ try_alloced_size, memflags,
+ CODEC_MM_FLAGS_CMA)) {
+ try_alloced_size = try_alloced_size
+ - 4 * SZ_1M;
+ if (try_alloced_size < 16 * SZ_1M)
+ break;
+ try_alloced_size = MM_ALIGN_UP2N(
+ try_alloced_size,
+ RESERVE_MM_ALIGNED_2N);
+ } else {
+ goto alloced_finished;
+ }
+ } while (retry++ < retry_cnt);
+ }
+ }
+ try_alloced_size = 0;
+alloced_finished:
+ mutex_unlock(&tvp_pool->pool_lock);
+ return try_alloced_size;
+}
+
int codec_mm_extpool_pool_alloc(
struct extpool_mgt_s *tvp_pool,
int size, int memflags, int for_tvp)
if (try_alloced_size < 16 * SZ_1M)
break;
}
- if (tvp_pool->slot_num < 3 &&
+ if (tvp_pool->slot_num < TVP_POOL_SEGMENT_USED_NORMAL &&
alloced_size < size) {
try_alloced_size = MM_ALIGN_UP2N(
try_alloced_size,
}
} while (retry++ < retry_cnt);
}
- if (alloced_size >= size || tvp_pool->slot_num >= 3) {
+ if (alloced_size >= size || tvp_pool->slot_num >=
+ TVP_POOL_SEGMENT_USED_NORMAL) {
/*alloc finished. */
goto alloced_finished;
}
if (try_alloced_size < 16 * SZ_1M)
break;
}
- if (tvp_pool->slot_num < 3 &&
+ if (tvp_pool->slot_num < TVP_POOL_SEGMENT_USED_NORMAL &&
alloced_size < size) {
try_alloced_size = MM_ALIGN_UP2N(
try_alloced_size,
tvp_pool->gen_pool[i];
tvp_pool->mm[before_free_slot] =
tvp_pool->mm[i];
- tvp_pool->gen_pool[i] = NULL;
- tvp_pool->mm[i] = NULL;
before_free_slot++;
}
if (!tvp_pool->gen_pool[i] && before_free_slot > i) {
return ignored;
}
+static int codec_mm_tvp_pool_unprotect_and_release(
+ struct extpool_mgt_s *tvp_pool)
+{
+ int i;
+ int ignored = 0;
+
+ mutex_lock(&tvp_pool->pool_lock);
+ for (i = 0; i < tvp_pool->slot_num; i++) {
+ struct gen_pool *gpool = tvp_pool->gen_pool[i];
+ int slot_mem_size = 0;
+
+ if (gpool) {
+ if (gen_pool_avail(gpool) != gen_pool_size(gpool)) {
+ pr_err("ERROR: TVP pool is not free.\n");
+ ignored++;
+ continue; /*ignore this free now, */
+ }
+ slot_mem_size = gen_pool_size(gpool);
+ gen_pool_destroy(tvp_pool->gen_pool[i]);
+ if (tvp_pool->mm[i]) {
+ struct page *mm = tvp_pool->mm[i]->mem_handle;
+
+ pr_info("unprotect tvp %d handle is %d\n",
+ i, tvp_pool->mm[i]->tvp_handle);
+ if (tvp_pool->mm[i]->tvp_handle > 0) {
+ tee_unprotect_tvp_mem(
+ tvp_pool->mm[i]->tvp_handle);
+ tvp_pool->mm[i]->tvp_handle = -1;
+ }
+ if (tvp_pool->mm[i]->from_flags ==
+ AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA_RES)
+ mm = phys_to_page(
+ (unsigned long)mm);
+ cma_mmu_op(mm,
+ tvp_pool->mm[i]->page_count,
+ 1);
+ codec_mm_release(tvp_pool->mm[i],
+ TVP_POOL_NAME);
+ }
+ }
+ tvp_pool->total_size -= slot_mem_size;
+ tvp_pool->gen_pool[i] = NULL;
+ tvp_pool->mm[i] = NULL;
+ }
+ if (ignored > 0) {
+ int before_free_slot = tvp_pool->slot_num + 1;
+
+ for (i = 0; i < tvp_pool->slot_num; i++) {
+ if (tvp_pool->gen_pool[i] && before_free_slot < i) {
+ tvp_pool->gen_pool[before_free_slot] =
+ tvp_pool->gen_pool[i];
+ tvp_pool->mm[before_free_slot] =
+ tvp_pool->mm[i];
+ tvp_pool->mm[before_free_slot]->tvp_handle =
+ tvp_pool->mm[i]->tvp_handle;
+ before_free_slot++;
+ }
+ if (!tvp_pool->gen_pool[i] && before_free_slot > i) {
+ before_free_slot = i;
+ /**/
+ }
+ }
+ }
+ tvp_pool->slot_num = ignored;
+ mutex_unlock(&tvp_pool->pool_lock);
+ return ignored;
+}
+
/*
*victor_size
*=sizeof(res)/sizeof(ulong)
if (buf) {
pbuf += s;
if (tsize > size - 256) {
- s += snprintf(pbuf + s, size - tsize,
+ s = snprintf(pbuf, size - tsize,
"\n\t\t**NOT END**\n");
tsize += s;
break;/*no memory for dump now.*/
return 0;
}
+static void codec_mm_tvp_segment_init(void)
+{
+ int size = 0;
+ int segment_size = 0;
+ int rest_size = 0;
+
+ size = default_tvp_pool_size_0 +
+ default_tvp_pool_size_1 + default_tvp_pool_size_2;
+ if (size > default_tvp_size) {
+ default_tvp_pool_size_0 = 0;
+ default_tvp_pool_size_1 = 0;
+ default_tvp_pool_size_2 = 0;
+ }
+
+ if (default_tvp_4k_pool_size_0 < default_tvp_pool_size_0)
+ default_tvp_4k_pool_size_0 = default_tvp_pool_size_0;
+ if (default_tvp_4k_pool_size_1 < default_tvp_pool_size_1)
+ default_tvp_4k_pool_size_1 = default_tvp_pool_size_1;
+ if (default_tvp_4k_pool_size_2 < default_tvp_pool_size_2)
+ default_tvp_4k_pool_size_2 = default_tvp_pool_size_2;
+
+ size = default_tvp_4k_pool_size_0 +
+ default_tvp_4k_pool_size_1 + default_tvp_4k_pool_size_2;
+ if (size > default_tvp_4k_size) {
+ default_tvp_4k_pool_size_0 = 0;
+ default_tvp_4k_pool_size_1 = 0;
+ default_tvp_4k_pool_size_2 = 0;
+ }
+
+ if (default_tvp_4k_size > default_tvp_size) {
+ if (default_tvp_4k_pool_size_0 >=
+ DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[0] =
+ default_tvp_4k_pool_size_0;
+ } else {
+ default_tvp_4k_pool_segment_size[0] =
+ default_tvp_4k_size * 4 / 12;
+ }
+ size = default_tvp_4k_pool_segment_size[0];
+ if (default_tvp_4k_pool_size_1 >=
+ DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[1] =
+ default_tvp_4k_pool_size_1;
+ } else {
+ segment_size = default_tvp_4k_size * 3 / 12;
+ rest_size = default_tvp_4k_size - size;
+ default_tvp_4k_pool_segment_size[1] =
+ (rest_size > segment_size) ?
+ segment_size : rest_size;
+ }
+ size += default_tvp_4k_pool_segment_size[1];
+ if (default_tvp_4k_pool_size_2 >=
+ DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[2] =
+ default_tvp_4k_pool_size_2;
+ } else {
+ segment_size = default_tvp_4k_size * 3 / 12;
+ rest_size = default_tvp_4k_size - size;
+ default_tvp_4k_pool_segment_size[2] =
+ (rest_size > segment_size) ?
+ segment_size : rest_size;
+ }
+ size += default_tvp_4k_pool_segment_size[2];
+ default_tvp_4k_pool_segment_size[3] =
+ default_tvp_4k_size - size;
+
+ if (default_tvp_pool_size_0 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_pool_segment_size[0] =
+ default_tvp_pool_size_0;
+ } else {
+ default_tvp_pool_segment_size[0] =
+ default_tvp_size * 4 / 12;
+ }
+ size = default_tvp_pool_segment_size[0];
+ if (default_tvp_pool_size_1 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_pool_segment_size[1] =
+ default_tvp_pool_size_1;
+ } else {
+ segment_size = default_tvp_size * 3 / 12;
+ rest_size = default_tvp_size - size;
+ default_tvp_pool_segment_size[1] =
+ (rest_size > segment_size) ?
+ segment_size : rest_size;
+ }
+ size += default_tvp_pool_segment_size[1];
+ if (default_tvp_pool_size_2 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_pool_segment_size[2] =
+ default_tvp_pool_size_2;
+ default_tvp_size =
+ size + default_tvp_pool_size_2;
+ } else {
+ default_tvp_pool_segment_size[2] =
+ default_tvp_size - size;
+ }
+ default_tvp_pool_segment_size[3] = 0;
+ } else {
+ if (default_tvp_pool_size_0 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[0] =
+ default_tvp_pool_size_0;
+ default_tvp_pool_segment_size[0] =
+ default_tvp_pool_size_0;
+ } else {
+ default_tvp_4k_pool_segment_size[0] =
+ default_tvp_4k_size * 4 / 12;
+ default_tvp_pool_segment_size[0] =
+ default_tvp_4k_size * 4 / 12;
+ }
+ size = default_tvp_pool_segment_size[0];
+ if (default_tvp_pool_size_1 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[1] =
+ default_tvp_pool_size_1;
+ default_tvp_pool_segment_size[1] =
+ default_tvp_pool_size_1;
+ } else {
+ segment_size = default_tvp_4k_size * 3 / 12;
+ rest_size = default_tvp_4k_size - size;
+ default_tvp_4k_pool_segment_size[1] =
+ (rest_size > segment_size) ?
+ segment_size : rest_size;
+ default_tvp_pool_segment_size[1] =
+ (rest_size > segment_size) ?
+ segment_size : rest_size;
+ }
+ size += default_tvp_pool_segment_size[1];
+ if (default_tvp_pool_size_2 >= DEFAULT_TVP_SEGMENT_MIN_SIZE) {
+ default_tvp_4k_pool_segment_size[2] =
+ default_tvp_pool_size_2;
+ default_tvp_pool_segment_size[2] =
+ default_tvp_pool_size_2;
+ } else {
+ default_tvp_4k_pool_segment_size[2] =
+ default_tvp_4k_size - size;
+ default_tvp_pool_segment_size[2] =
+ default_tvp_4k_size - size;
+ }
+ default_tvp_pool_segment_size[3] = 0;
+ default_tvp_4k_size = size + default_tvp_pool_segment_size[2];
+ default_tvp_size = default_tvp_4k_size;
+ }
+}
+
int codec_mm_enable_tvp(int size, int flags)
{
int ret;
else
size = default_tvp_4k_size;
}
- ret = codec_mm_extpool_pool_alloc(
- &mgt->tvp_pool,
- size, 0, 1);
- if (ret) {
- ret = 0;
- mgt->tvp_enable = flags;
- if (tvp_mode > 0)
- atomic_add_return(1, &mgt->tvp_user_count);
- pr_info("enable tvp for %d\n", flags);
+ if (tvp_dynamic_increase_disable) {
+ ret = codec_mm_extpool_pool_alloc(
+ &mgt->tvp_pool,
+ size, 0, 1);
+ if (ret) {
+ ret = 0;
+ mgt->tvp_enable = flags;
+ if (tvp_mode > 0)
+ atomic_add_return(1, &mgt->tvp_user_count);
+ pr_info("enable tvp for %d\n", flags);
+ } else {
+ pr_info("tvp enable failed size %d\n", size);
+ mutex_unlock(&mgt->tvp_protect_lock);
+ return -1;
+ }
} else {
- pr_info("tvp enable failed size %d\n",
- size);
- mutex_unlock(&mgt->tvp_protect_lock);
- return -1;
+ if (mgt->tvp_pool.slot_num <= 0) {
+ codec_mm_tvp_segment_init();
+ ret = codec_mm_tvp_pool_alloc_by_slot(
+ &mgt->tvp_pool, 0, flags);
+ if (ret) {
+ ret = 0;
+ if (mgt->tvp_enable != 2)
+ mgt->tvp_enable = flags;
+ if (tvp_mode > 0)
+ atomic_add_return(1,
+ &mgt->tvp_user_count);
+ pr_info("enable tvp for %d\n", flags);
+ } else {
+ pr_info("tvp enable failed size %d\n", size);
+ mutex_unlock(&mgt->tvp_protect_lock);
+ return -1;
+ }
+ } else {
+ ret = 0;
+ if (mgt->tvp_enable != 2)
+ mgt->tvp_enable = flags;
+ if (tvp_mode > 0)
+ atomic_add_return(1, &mgt->tvp_user_count);
+ pr_info("enable tvp for %d\n", flags);
+ }
}
if (tvp_mode > 0)
pr_info("tvp_user_count is %d\n",
return ret;
}
if (atomic_dec_and_test(&mgt->tvp_user_count)) {
- if (codec_mm_tvp_pool_unprotect(&mgt->tvp_pool) == 0) {
- ret = codec_mm_extpool_pool_release(&mgt->tvp_pool);
+ if (codec_mm_tvp_pool_unprotect_and_release(&mgt->tvp_pool)
+ == 0) {
mgt->tvp_enable = 0;
pr_info("disalbe tvp\n");
mutex_unlock(&mgt->tvp_protect_lock);
int codec_mm_mgt_init(struct device *dev)
{
-
struct codec_mm_mgt_s *mgt = get_mem_mgt();
INIT_LIST_HEAD(&mgt->mem_list);
DEFAULT_TVP_SIZE_FOR_NO4K ?
DEFAULT_TVP_SIZE_FOR_NO4K :
default_tvp_4k_size;
+ codec_mm_tvp_segment_init();
default_cma_res_size = mgt->total_cma_size;
mgt->global_memid = 0;
MC_PI32("default_tvp_size", &default_tvp_size),
MC_PI32("default_tvp_4k_size", &default_tvp_4k_size),
MC_PI32("default_cma_res_size", &default_cma_res_size),
+ MC_PI32("default_tvp_pool_size_0", &default_tvp_pool_size_0),
+ MC_PI32("default_tvp_pool_size_1", &default_tvp_pool_size_1),
+ MC_PI32("default_tvp_pool_size_2", &default_tvp_pool_size_2),
+ MC_PI32("default_tvp_4k_pool_size_0", &default_tvp_4k_pool_size_0),
+ MC_PI32("default_tvp_4k_pool_size_1", &default_tvp_4k_pool_size_1),
+ MC_PI32("default_tvp_4k_pool_size_2", &default_tvp_4k_pool_size_2),
};
static struct mconfig_node codec_mm_trigger_node;
int codec_mm_trigger_fun(const char *trigger, int id, const char *buf, int size)
MODULE_PARM_DESC(debug_keep_mode, "\n debug keep module\n");
module_param(tvp_mode, uint, 0664);
MODULE_PARM_DESC(tvp_mode, "\n tvp module\n");
+module_param(tvp_dynamic_increase_disable, uint, 0664);
+MODULE_PARM_DESC(tvp_dynamic_increase_disable, "\n disable tvp_dynamic_increase\n");
/* get rdma_table_num resource */
rdma_table_size = RDMA_TABLE_SIZE;
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- rdma_table_size = RDMA_TABLE_SIZE * 2;
+ rdma_table_size = 16 * PAGE_SIZE;
prop = of_get_property(pdev->dev.of_node,
"rdma_table_page_count", NULL);
if (prop)
{RESMAN_ID_SEC_TVP, "tvp"},
{RESMAN_ID_TSPARSER, "tsparser"},
{RESMAN_ID_CODEC_MM, "codec_mm"},
+ {RESMAN_ID_ADC_PLL, "adc_pll"},
{0, NULL}
};
"videopip,type:1,avail:1;"
"tvp,type:3;"
"tsparser,type:1,avail:1;"
- "codec_mm,type:4,total:0;";
+ "codec_mm,type:4,total:0;"
+ "adc_pll,type:1,avail:1;";
INIT_LIST_HEAD(&sessions_head);
INIT_LIST_HEAD(&resources_head);
RESMAN_ID_SEC_TVP,
RESMAN_ID_TSPARSER,
RESMAN_ID_CODEC_MM,
+ RESMAN_ID_ADC_PLL,
RESMAN_ID_MAX,
};
enum RESMAN_APP {
RESMAN_APP_NONE = -1,
RESMAN_APP_OMX = 0,
- RESMAN_APP_DVB,
+ RESMAN_APP_XDVB,
RESMAN_APP_HDMI_IN,
RESMAN_APP_SEC_TVP,
+ RESMAN_APP_DVBKIT,
+ RESMAN_APP_TSPLAYER,
RESMAN_APP_OTHER = 10,
};
}
TABLE_UNLOCK();
if (i < MAX_PROVIDER_NUM) {
+ TABLE_LOCK();
vf_update_active_map();
receiver = vf_get_receiver(prov->name);
+ TABLE_UNLOCK();
if (receiver && receiver->ops && receiver->ops->event_cb) {
receiver->ops->event_cb(VFRAME_EVENT_PROVIDER_REG,
(void *)prov->name,
vf_provider_close(prov);
if (vfm_debug_flag & 1)
pr_err("%s:%s\n", __func__, prov->name);
+ TABLE_LOCK();
receiver = vf_get_receiver(prov->name);
+ TABLE_UNLOCK();
if (receiver && receiver->ops
&& receiver->ops->event_cb) {
receiver->ops->event_cb(
pr_err("%s Error to notify receiver\n",
__func__);
}
+ TABLE_LOCK();
vf_update_active_map();
+ TABLE_UNLOCK();
break;
}
TABLE_UNLOCK();
else
ccflags-y := -DDEBUG
endif
-CFLAGS_deinterlace.o := -I$(src)
+CFLAGS_deinterlace_dbg.o := -I$(src)
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di.o
di-objs += deinterlace.o
di-objs += deinterlace_hw.o
di-objs += detect3d.o
di-objs += nr_downscale.o
di-objs += di_pps.o
+di-objs += di_afbc.o
di-objs += film_mode_fmw/vof_soft_top.o
di-objs += film_mode_fmw/flm_mod_xx.o
di-objs += film_mode_fmw/film_fw1.o
#include <linux/dma-contiguous.h>
#include <linux/ctype.h>
#include <linux/string.h>
+#include <linux/of_device.h>
#include <linux/amlogic/iomap.h>
#include <linux/amlogic/media/codec_mm/codec_mm.h>
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/media/rdma/rdma_mgr.h>
#endif
#include <linux/amlogic/media/video_sink/video.h>
+
+#include "../common/vfm/vfm.h"
+
#include "register.h"
#include "register_nr4.h"
#include "deinterlace.h"
#include "di_pps.h"
#include "di_pqa.h"
-#define CREATE_TRACE_POINTS
-#include "deinterlace_trace.h"
-
-/*2018-07-18 add debugfs*/
#include <linux/seq_file.h>
#include <linux/debugfs.h>
-/*2018-07-18 -----------*/
-
-#undef TRACE_INCLUDE_PATH
-#undef TRACE_INCLUDE_FILE
-#define TRACE_INCLUDE_PATH .
-#define TRACE_INCLUDE_FILE deinterlace_trace
-#include <trace/define_trace.h>
#ifdef DET3D
#include "detect3d.h"
static unsigned int di_pre_rdma_enable;
static struct mutex di_event_mutex;
static atomic_t di_flag_unreg; //ary 2019-05-27
+static atomic_t di_clear_unreg;
static atomic_t di_trig_free_mem;
static unsigned int di_force_bit_mode = 10;
static unsigned int recovery_log_queue_idx;
static struct di_buf_s *recovery_log_di_buf;
-
static long same_field_top_count;
static long same_field_bot_count;
/* bit 0:
static unsigned int isbypass_flag = true;
static unsigned int needbypass_flag = true;
+unsigned int di_dbg_cfg = DI_NONE;
+module_param(di_dbg_cfg, uint, 0664);
+
static const
struct vframe_receiver_op_s di_vf_receiver = {
.event_cb = di_receiver_event_fun
};
+int di_get_disp_cnt_demo(void)
+{
+ return disp_frame_count;
+}
+
static struct vframe_receiver_s di_vf_recv;
static vframe_t *di_vf_peek(void *arg);
* width/height does not change)
*/
static vframe_t *vframe_in[MAX_IN_BUF_NUM];
-//static vframe_t vframe_in_dup[MAX_IN_BUF_NUM];
-//static vframe_t vframe_local[MAX_LOCAL_BUF_NUM * 2];
static vframe_t vframe_post[MAX_POST_BUF_NUM];
static struct di_buf_s *cur_post_ready_di_buf;
static struct di_buf_s di_buf_in[MAX_IN_BUF_NUM];
static struct di_buf_s di_buf_post[MAX_POST_BUF_NUM];
+#define signal_color_primaries ((vframe->signal_type >> 16) & 0xff)
+#define signal_transfer_characteristic ((vframe->signal_type >> 8) & 0xff)
/************For Write register**********************/
static unsigned int di_stop_reg_flag;
return de_devp;
}
+static inline struct div1_data_l_s *getv1_datal(void)
+{
+ return (struct div1_data_l_s *)get_di_de_devp()->data_l;
+}
+
+const struct afdv1_ops_s *di_afds(void)
+{
+ if (!de_devp)
+ return NULL;
+
+ return de_devp->afds;
+}
+
+struct afbcdv1_ctr_s *div1_get_afd_ctr(void)
+{
+ if (!de_devp)
+ return NULL;
+
+ return &de_devp->di_afd.ctr;
+}
+
const char *get_di_version_s(void)
{
return version_s;
up(&di_sema);
di_pr_info("%s\n", __func__);
}
-
- if (atomic_read(&di_flag_unreg)) {
- diwr_set_power_control_pst(0);
- di_pr_info("disable pst pd\n");
- }
}
EXPORT_SYMBOL(di_trig_free_mirror_mem);
struct device_attribute *attr,
const char *buf, size_t count)
{
- u32 val;
+ u32 val = 0;
char *buf_orig, *parm[8] = {NULL};
buf_orig = kstrdup(buf, GFP_KERNEL);
} else if (strncmp(buf, "dumpreg", 7) == 0) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
dump_di_reg_g12();
- dump_afbcd_reg();
+ /*dump_afbcd_reg();*/
+ if (di_afds())
+ di_afds()->dump_reg();
} else
pr_info("add new debugfs: cat /sys/kernel/debug/di/dumpreg\n");
} else if (strncmp(buf, "dumpafbc", 8) == 0) {
- dump_afbcd_reg();
+ /*dump_afbcd_reg();*/
+ if (di_afds())
+ di_afds()->dump_reg();
} else if (strncmp(buf, "dumpmif", 7) == 0) {
dump_mif_size_state(&di_pre_stru, &di_post_stru);
} else if (strncmp(buf, "dumppostmif", 11) == 0) {
} else if (strncmp(buf, "mem_map", 7) == 0) {
dump_buf_addr(di_buf_local, MAX_LOCAL_BUF_NUM * 2);
} else if (strncmp(buf, "afbc_on", 7) == 0) {
- if (kstrtoint(parm[1], 10, &val) < 0) {
- kfree(buf_orig);
- return count;
- }
- if (!val)
- afbc_sw(false);
- afbc_disable_flag = val > 0 ? 0:1;
- pr_info("afbc_disable_flag:%d\n", afbc_disable_flag);
} else if (strncmp(buf, "reqafbc", 7) == 0) {
- val = di_requeset_afbc(true);
- di_pre_stru.wait_afbc = false;
+ if (di_afds())
+ val = di_afds()->rqst_share(true);
+
pr_info("request_afbc(%d)\n", val);
} else if (strncmp(buf, "rlsafbc", 7) == 0) {
- val = di_requeset_afbc(false);
- di_pre_stru.wait_afbc = false;
+ if (di_afds())
+ val = di_afds()->rqst_share(true);
+
pr_info("rlease_afbc(%d)\n", val);
} else {
pr_info("DI no support cmd %s\n", buf);
return 1;
if (vf_in && vf_in->type & VIDTYPE_COMPRESS) {
- if (!afbc_is_supported())
- return 1;
+ if (di_afds() && !di_afds()->is_supported())
+ return 1;
}
if (/*di_pre_stru.cur_prog_flag && */
(di_pre_stru.cur_inp_type & VIDTYPE_RGB_444)))
return 1;
- if (di_pre_stru.cur_prog_flag)
- return 1;
-
if ((di_pre_stru.cur_width < 128) || (di_pre_stru.cur_height < 16))
return 1;
if (vf_in->type & VIDTYPE_COMPRESS) {
vf_tmp.width = vf_in->compWidth;
vf_tmp.height = vf_in->compHeight;
- if (vf_tmp.width > default_width ||
- vf_tmp.height > (default_height + 8))
+ if (vf_tmp.width > 1920 || vf_tmp.height > 1088)
return 1;
}
int flags = 0;
bool istvp = false;
- if (codec_mm_video_tvp_enabled()) {
+ if ((di_pre_stru.is_tvp == -1) &&
+ codec_mm_video_tvp_enabled()) {
+ istvp = true;
+ flags |= CODEC_MM_FLAGS_TVP;
+ } else if (di_pre_stru.is_tvp == 1) {
istvp = true;
flags |= CODEC_MM_FLAGS_TVP;
} else {
#endif
}
+static s8 check_tvp_state(void)
+{
+ struct provider_state_req_s req;
+ s8 ret = -1;
+ char *provider_name = vf_get_provider_name(VFM_NAME);
+
+ while (provider_name) {
+ if (!vf_get_provider_name(provider_name))
+ break;
+ provider_name =
+ vf_get_provider_name(provider_name);
+ }
+ if (provider_name) {
+ req.vf = NULL;
+ req.req_type = REQ_STATE_SECURE;
+ req.req_result[0] = 0xffffffff;
+ vf_notify_provider_by_name(
+ provider_name,
+ VFRAME_EVENT_RECEIVER_REQ_STATE,
+ (void *)&req);
+ if (req.req_result[0] == 0)
+ ret = 0;
+ else if (req.req_result[0] != 0xffffffff)
+ ret = 1;
+ }
+ return ret;
+}
+
static bool cma_print;
static unsigned int di_cma_alloc(struct di_dev_s *devp)
{
bool aret;
struct di_mm_s omm;
+ di_pre_stru.is_tvp = check_tvp_state();
+
start_time = jiffies_to_msecs(jiffies);
queue_for_each_entry(buf_p, ptmp, QUEUE_LOCAL_FREE, list) {
#if 0
end_time = jiffies_to_msecs(jiffies);
delta_time = end_time - start_time;
- pr_info("%s:alloc %u buffer use %u ms(%u~%u)\n",
- __func__, alloc_cnt, delta_time, start_time, end_time);
+ pr_info("%s:alloc %u buffer use %u ms(%u~%u), tvp:%d\n",
+ __func__, alloc_cnt, delta_time, start_time, end_time,
+ di_pre_stru.is_tvp);
return 1;
}
unsigned int mv_canvas_width = width, canvas_align_width = 32;
unsigned long di_post_mem = 0, nrds_mem = 0;
struct di_buf_s *keep_buf = di_post_stru.keep_buf;
- u8 *tmp;
+ u8 *tmp, *tmp_meta;
unsigned int buf_limit; /* for s805 */
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
same_field_bot_count = 0;
queue_init(de_devp->buf_num_avail);
+ tmp_meta = de_devp->local_meta_addr;
for (i = 0; i < de_devp->buf_num_avail; i++) {
struct di_buf_s *di_buf = &(di_buf_local[i]);
int ii = USED_LOCAL_BUF_MAX;
di_buf->vframe->canvas1Addr = di_buf->nr_canvas_idx;
di_buf->queue_index = -1;
di_buf->invert_top_bot_flag = 0;
+ if (de_devp->local_meta_addr) {
+ di_buf->local_meta = tmp_meta;
+ di_buf->local_meta_total_size =
+ LOCAL_META_BUFF_SIZE;
+ } else {
+ di_buf->local_meta = NULL;
+ di_buf->local_meta_total_size = 0;
+ }
+ di_buf->local_meta_used_size = 0;
queue_in(di_buf, QUEUE_LOCAL_FREE);
+ } else {
+ if (!di_buf->local_meta) {
+ if (de_devp->local_meta_addr) {
+ di_buf->local_meta = tmp_meta;
+ di_buf->local_meta_total_size =
+ LOCAL_META_BUFF_SIZE;
+ } else {
+ di_buf->local_meta = NULL;
+ di_buf->local_meta_total_size = 0;
+ }
+ di_buf->local_meta_used_size = 0;
+ }
+ if (di_buf->local_meta != tmp_meta)
+ pr_info("DI: local buf init, keep buffer meta %p, new:%p.\n",
+ di_buf->local_meta, tmp_meta);
}
+ if (tmp_meta)
+ tmp_meta += LOCAL_META_BUFF_SIZE;
}
#ifdef CONFIG_CMA
if (de_devp->flag_cma == 1 || (de_devp->flag_cma == 4) ||
di_post_buf_size = 0;
}
de_devp->post_buffer_size = di_post_buf_size;
+ tmp_meta = de_devp->local_meta_addr +
+ (MAX_LOCAL_BUF_NUM * LOCAL_META_BUFF_SIZE * 2);
for (i = 0; i < MAX_IN_BUF_NUM; i++) {
struct di_buf_s *di_buf = &(di_buf_in[i]);
di_buf->index = i;
di_buf->queue_index = -1;
di_buf->invert_top_bot_flag = 0;
+ if (de_devp->local_meta_addr) {
+ di_buf->local_meta = tmp_meta;
+ di_buf->local_meta_total_size =
+ LOCAL_META_BUFF_SIZE;
+ } else {
+ di_buf->local_meta = NULL;
+ di_buf->local_meta_total_size = 0;
+ }
+ di_buf->local_meta_used_size = 0;
queue_in(di_buf, QUEUE_IN_FREE);
}
+ if (tmp_meta)
+ tmp_meta += LOCAL_META_BUFF_SIZE;
}
+ tmp_meta = de_devp->local_meta_addr +
+ ((MAX_IN_BUF_NUM +
+ (MAX_LOCAL_BUF_NUM * 2)) * LOCAL_META_BUFF_SIZE);
for (i = 0; i < di_post_stru.di_post_num; i++) {
struct di_buf_s *di_buf = &(di_buf_post[i]);
di_buf->vframe->private_data = di_buf;
di_buf->queue_index = -1;
di_buf->invert_top_bot_flag = 0;
+ if (de_devp->local_meta_addr) {
+ di_buf->local_meta = tmp_meta;
+ di_buf->local_meta_total_size =
+ LOCAL_META_BUFF_SIZE;
+ } else {
+ di_buf->local_meta = NULL;
+ di_buf->local_meta_total_size = 0;
+ }
+ di_buf->local_meta_used_size = 0;
if (post_wr_en && post_wr_support) {
di_buf->canvas_width[NR_CANVAS] =
(nr_width << 1);
di_post_buf_size*i;
}
queue_in(di_buf, QUEUE_POST_FREE);
+ } else {
+ if (!di_buf->local_meta) {
+ if (de_devp->local_meta_addr) {
+ di_buf->local_meta = tmp_meta;
+ di_buf->local_meta_total_size =
+ LOCAL_META_BUFF_SIZE;
+ } else {
+ di_buf->local_meta = NULL;
+ di_buf->local_meta_total_size =
+ 0;
+ }
+ di_buf->local_meta_used_size = 0;
+ }
+ if (di_buf->local_meta != tmp_meta)
+ pr_info("DI:post keep buffer meta %p\n",
+ keep_buf->local_meta);
+ pr_info("DI:post keep buffer new:%p.\n",
+ tmp_meta);
}
}
+ if (tmp_meta)
+ tmp_meta += LOCAL_META_BUFF_SIZE;
}
if (de_devp->flag_cma == 0 && de_devp->nrds_enable) {
nrds_mem = di_post_mem +
isbypass_flag, needbypass_flag);
pr_info("di_pre_stru.bypass_flag=%d\n",
di_pre_stru.bypass_flag);
- pr_info("afbcd support %d\n", afbc_is_supported());
+ pr_info("afbcd support %d\n", (di_afds() && di_afds()->is_supported()) ?
+ true : false);
pr_info("recovery_flag = %d, recovery_log_reason=%d, di_blocking=%d",
recovery_flag, recovery_log_reason, di_blocking);
pr_info("recovery_log_queue_idx=%d, recovery_log_di_buf=0x%p\n",
if (di_buf->vframe != &de_devp->vfm_in_dup[di_buf->index])
error = 1;
} else if (di_buf->type == VFRAME_TYPE_LOCAL) {
- //if (di_buf->vframe != &vframe_local[di_buf->index])
if (di_buf->vframe != &de_devp->vfm_local[di_buf->index])
error = 1;
} else if (di_buf->type == VFRAME_TYPE_POST) {
if (di_buf) {
pre_size_w = di_buf->vframe->width;
- pre_size_h = (di_buf->vframe->height + 1) / 2;
+ pre_size_h = di_buf->vframe->height / 2;
di_mcinfo_mif->size_x = pre_size_h / 2 - 1;
di_mcinfo_mif->size_y = 1;
di_mcinfo_mif->canvas_num = di_buf->mcinfo_canvas_idx;
static void pre_inp_mif_w(struct DI_MIF_s *di_mif, struct vframe_s *vf);
-bool secam_cfr_en = true;
-unsigned int cfr_phase1 = 1;/*0x179c[6]*/
-unsigned int cfr_phase2 = 1;/*0x179c[7]*/
-unsigned int gb_flg = 1;/*1:top, 0:bot*/
-
-static ssize_t
-secam_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- int len = 0;
-
- len += sprintf(buf+len,
- "secam_cfr_en %u, gb_flg %u, cfr_phase2 %u.\n",
- secam_cfr_en, gb_flg, cfr_phase2);
- return len;
-}
-
-static ssize_t
-secam_store(struct device *dev, struct device_attribute *attr, const char *buf,
- size_t count)
-{
- char *parm[3] = { NULL }, *buf_orig;
- long val;
- ssize_t ret_ext = count;
-
- if (!buf)
- return count;
- buf_orig = kstrdup(buf, GFP_KERNEL);
- parse_cmd_params(buf_orig, (char **)(&parm));
-
- if (!parm[2]) {
- ret_ext = -EINVAL;
- pr_info("miss param!!\n");
- } else {
- if (kstrtol(parm[0], 10, &val) == 0)
- secam_cfr_en = val;
- if (kstrtol(parm[1], 10, &val) == 0)
- gb_flg = val;
- if (kstrtol(parm[2], 10, &val) == 0)
- cfr_phase2 = val;
- }
-
- kfree(buf_orig);
-
- pr_info("secam_cfr_en %u, gb_flg %u, cfr_phase2 %u.\n",
- secam_cfr_en, gb_flg, cfr_phase2);
- return ret_ext;
-}
-static DEVICE_ATTR(secam, 0664, secam_show, secam_store);
-
-static void secam_cfr_fun(int top)
-{
- DI_Wr_reg_bits(NR2_SW_EN, 1, 7, 1);/*set cfr_en:1*/
- DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, 1, 2, 2);
- DI_Wr_reg_bits(NR2_CFR_PARA_CFG1, 0x80, 8, 8);
- if (((gb_flg == 0) && top) || ((gb_flg == 1) && (!top))) {
- cfr_phase1 = ~cfr_phase1;
- DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, cfr_phase1, 6, 1);
- }
- DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, cfr_phase2, 7, 1);
-}
-
static void pre_de_process(void)
{
ulong irq_flag2 = 0;
di_pre_stru.input_size_change_flag = false;
}
+ #ifdef DI_FILM_GRAIN
+ if (di_pre_stru.source_change_flag && (di_dbg_cfg & DBG_M_FG))
+ di_fgrain_config(&di_pre_stru.di_inp_mif,
+ &di_pre_stru.fgrain_diset,
+ di_pre_stru.di_inp_buf->vframe);
+ #endif
di_patch_mov_setting();
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
if (de_devp->nrds_enable) {
}
/*patch for SECAM signal format from vlsi-feijun for all IC*/
- if (di_pre_stru.di_inp_buf->vframe->sig_fmt ==
- TVIN_SIG_FMT_CVBS_SECAM && secam_cfr_en) {
- secam_cfr_fun((di_pre_stru.di_inp_buf->vframe->type &
- VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP);
- } else {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
- DI_Wr_reg_bits(NR4_TOP_CTRL, 0, 12, 1);/*set cfr_en:0*/
- else
- DI_Wr_reg_bits(NR2_SW_EN, 0, 7, 1);/*set cfr_en:0*/
- DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, 2, 2, 2);
- }
+ secam_cfr_adjust(di_pre_stru.di_inp_buf->vframe->sig_fmt,
+ di_pre_stru.di_inp_buf->vframe->type);
/* set interrupt mask for pre module.
* we need to only leave one mask open
chan2_field_num,
di_pre_stru.vdin2nr);
- enable_afbc_input(di_pre_stru.di_inp_buf->vframe);
+ /*enable_afbc_input(di_pre_stru.di_inp_buf->vframe);*/
+ if (di_afds())
+ di_afds()->en_pre_set(di_pre_stru.di_inp_buf->vframe,
+ di_pre_stru.di_mem_buf_dup_p->vframe,
+ di_pre_stru.di_wr_buf->vframe);
+ #ifdef DI_FILM_GRAIN
+ if (di_dbg_cfg & DBG_M_FG) {
+ if (di_pre_stru.source_change_flag)
+ di_fgrain_setting(&di_pre_stru.fgrain_diset,
+ di_pre_stru.di_inp_buf->vframe);
+ di_fgrain_update_table(di_pre_stru.di_inp_buf->vframe);
+ }
+ #endif
if (mcpre_en) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
enable_mc_di_pre_g12(
di_pre_stru.field_count_for_cont++;
if (di_pre_stru.field_count_for_cont >= 5)
DI_Wr_reg_bits(DI_MTN_CTRL, 0, 30, 1);
-
+ if (di_afds()->is_cfg(EAFBCV1_CFG_PAUSE) &&
+ di_pre_stru.field_count_for_cont == 2) {
+ pre_run_flag = DI_RUN_FLAG_PAUSE;
+ }
di_txl_patch_prog(di_pre_stru.cur_prog_flag,
di_pre_stru.field_count_for_cont, mcpre_en);
di_pre_stru.irq_time[0] = cur_to_msecs();
di_pre_stru.irq_time[1] = cur_to_msecs();
ddbg_mod_save(eDI_DBG_MOD_PRE_SETE, 0, di_pre_stru.in_seq);/*dbg*/
+ di_tr_ops.pre_set(di_pre_stru.di_wr_buf->vframe->omx_index);
#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
if (di_pre_rdma_enable & 0x2)
rdma_config(de_devp->rdma_handle, RDMA_TRIGGER_MANUAL);
ddbg_mod_save(eDI_DBG_MOD_PRE_DONEB, 0, di_pre_stru.in_seq);/*dbg*/
if (di_pre_stru.di_wr_buf) {
+ di_tr_ops.pre_cnt0(di_pre_stru.di_wr_buf->vframe->omx_index);
+ di_tr_ops.pre_cnt1(di_pre_stru.di_wr_buf->vframe->omx_index);
+ di_tr_ops.pre_ready(di_pre_stru.di_wr_buf->vframe->omx_index);
+
if (di_pre_stru.pre_throw_flag > 0) {
di_pre_stru.di_wr_buf->throw_flag = 1;
di_pre_stru.pre_throw_flag--;
if (post_wr_buf) {
post_wr_buf->vframe->di_pulldown = 0;
post_wr_buf->vframe->di_gmv = 0;
+ post_wr_buf->vframe->di_cm_cnt = 0;
}
if (post_wr_buf && !di_pre_stru.cur_prog_flag) {
read_pulldown_info(&glb_frame_mot_num,
&glb_field_mot_num);
- if (pulldown_enable && di_pre_stru.di_inp_buf) {
+ if (pulldown_enable) {
pull_down_info = pulldown_detection(
&post_wr_buf->pd_config,
di_pre_stru.mtn_status, overturn,
}
post_wr_buf->vframe->di_pulldown |= 0x08;
+
post_wr_buf->vframe->di_gmv = glb_frame_mot_num;
+ post_wr_buf->vframe->di_cm_cnt = di_rd_mcdi_fldcnt();
if (di_pre_stru.combing_fix_en)
cur_lev = adaptive_combing_fixing(
di_pre_stru.mtn_status,
static int pre_hsc_down_width = 480;
module_param_named(pre_hsc_down_width, pre_hsc_down_width, int, 0644);
-
-u32 di_requeset_afbc(u32 onoff)
-{
- u32 afbc_busy;
-
- if (onoff)
- afbc_busy = di_request_afbc_hw(afbc_get_decnub(), true);
- else
- afbc_busy = di_request_afbc_hw(afbc_get_decnub(), false);
-
- return afbc_busy;
-}
-
static unsigned char pre_de_buf_config(void)
{
struct di_buf_s *di_buf = NULL;
unsigned char change_type = 0;
bool bit10_pack_patch = false;
unsigned int width_roundup = 2;
- u32 rls_timeout;
- u32 afbc_busy;
- u32 is_afbc_mode = 0;
bool flg_1080i = false;
bool flg_480i = false;
+ u32 cur_dw_width = 0xffff;
+ u32 cur_dw_height = 0xffff;
#ifdef DI_KEEP_DEC_VF
bool flg_2nd = false;
#endif
if (vframe == NULL)
return 0;
-
+ di_tr_ops.pre_get(vframe->omx_index);
/*for support compress from dec*/
- if (IS_COMP_MODE(vframe->type) &&
- !is_bypass(vframe) &&
- afbc_is_supported()) {
- is_afbc_mode = true;
+ if (IS_COMP_MODE(vframe->type)) {
+ /*backup the orignal vf->width/height for bypass case */
+ cur_dw_width = vframe->width;
+ cur_dw_height = vframe->height;
if (IS_VDIN_SRC(vframe->source_type)
&& IS_I_SRC(vframe->type)) {
vframe->width = vframe->compWidth;
return 0;
}
-
- /*
- * for afbc used by vpp and di, when di use it,
- * vpp need release afbc, waitting vpp release
- */
- if (di_pre_stru.wait_afbc) {
- /*check time out and afbc release status*/
- rls_timeout =
- jiffies_to_msecs(jiffies_64 -
- di_pre_stru.afbc_rls_time);
- afbc_busy = di_requeset_afbc(true);
- if (afbc_busy && (rls_timeout < 80)) {
- vf_put(vframe, VFM_NAME);
- vf_notify_provider(
- VFM_NAME, VFRAME_EVENT_RECEIVER_PUT, NULL);
- pr_info("di: drop vframe (%d) t:%d\n",
- afbc_busy, rls_timeout);
- return 0;
- } else if (!afbc_busy) {
- /*afbc_busy = di_requeset_afbc(false);*/
- di_pre_stru.wait_afbc = false;
- pr_info("di: afbc hw free\n");
- } else {
- di_pre_stru.wait_afbc = false;
- pr_info("di: afbc wait timeout\n");
- }
- }
-
bit10_pack_patch = (is_meson_gxtvbb_cpu() ||
is_meson_gxl_cpu() ||
is_meson_gxm_cpu());
#endif
memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
di_buf->width_bk = vframe->width;
+ di_buf->dw_width_bk = cur_dw_width;
di_buf->vframe->private_data = di_buf;
vframe_in[di_buf->index] = vframe;
di_buf->seq = di_pre_stru.in_seq;
di_pre_stru.in_seq++;
+ di_buf->local_meta_used_size = 0;
queue_out(di_buf);
+ if ((signal_transfer_characteristic == 0x30) &&
+ ((signal_color_primaries == 9) ||
+ (signal_color_primaries == 2))) {
+ struct provider_aux_req_s req;
+ char *provider_name = NULL, *tmp_name = NULL;
+
+ provider_name = vf_get_provider_name(VFM_NAME);
+ while (provider_name) {
+ tmp_name =
+ vf_get_provider_name(provider_name);
+ if (!tmp_name)
+ break;
+ provider_name = tmp_name;
+ }
+ if (provider_name) {
+ req.vf = vframe;
+ req.bot_flag = 0;
+ req.aux_buf = NULL;
+ req.aux_size = 0;
+ req.dv_enhance_exist = 0;
+ vf_notify_provider_by_name(
+ provider_name,
+ VFRAME_EVENT_RECEIVER_GET_AUX_DATA,
+ (void *)&req);
+ }
+ if (req.aux_buf && req.aux_size &&
+ di_buf->local_meta &&
+ (di_buf->local_meta_total_size >= req.aux_size)) {
+ memcpy(di_buf->local_meta,
+ req.aux_buf, req.aux_size);
+ di_buf->local_meta_used_size = req.aux_size;
+ } else if (di_buf->local_meta && provider_name) {
+ pr_info("DI:get meta data error aux_buf:%p\n",
+ req.aux_buf);
+ pr_info("DI:get meta data errorsize:%d (%d)\n",
+ req.aux_size,
+ di_buf->local_meta_total_size);
+ }
+ }
change_type = is_source_change(vframe);
/* source change, when i mix p,force p as i*/
if (change_type == 1 || (change_type == 2 &&
di_buf->vframe->height,
di_buf->vframe->source_type);
- if (IS_COMP_MODE(di_buf->vframe->type) &&
- !is_bypass(vframe)) {
+ if (IS_COMP_MODE(di_buf->vframe->type)) {
if (IS_VDIN_SRC(di_buf->vframe->source_type) &&
IS_I_SRC(di_buf->vframe->type)) {
di_pre_stru.cur_width =
}
#endif
- /*
- * for afbc used by vpp and di, when di use it,
- * vpp need release afbc, waitting vpp release
- */
- if (is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
- is_meson_tm2_cpu()) {
- /*compress mode and format changed*/
- if (!is_bypass(di_buf->vframe) &&
- di_pre_stru.source_change_flag &&
- IS_COMP_MODE(di_pre_stru.cur_inp_type)
- && !afbc_is_free()
- && !di_pre_stru.wait_afbc) {
- afbc_busy = di_requeset_afbc(true);
- vf_put(vframe, VFM_NAME);
- vf_notify_provider(VFM_NAME,
- VFRAME_EVENT_RECEIVER_PUT, NULL);
- recycle_vframe_type_pre(di_buf);
- di_pre_stru.afbc_rls_time = jiffies_64;
- di_pre_stru.wait_afbc = true;
- pr_info("di req afbc:%d\n", afbc_busy);
- return 0;
- }
- }
/*di_pre_stru.field_count_for_cont = 0;*/
} else if (di_pre_stru.cur_prog_flag == 0) {
/* check if top/bot interleaved */
}
if (is_bypass(di_buf->vframe)) {
+ if (IS_COMP_MODE(di_buf->vframe->type) &&
+ (cur_dw_width != 0xffff) &&
+ (cur_dw_height != 0xffff)) {
+ di_buf->vframe->width = cur_dw_width;
+ di_buf->vframe->height = cur_dw_height;
+ }
/* bypass progressive */
di_buf->seq = di_pre_stru.pre_ready_seq++;
di_buf->post_ref_count = 0;
di_buf->vframe->bitdepth &= ~(BITDEPTH_YMASK);
di_buf->vframe->bitdepth &= ~(FULL_PACK_422_MODE);
di_buf->width_bk = di_buf->vframe->width;
+ if (di_buf->local_meta &&
+ di_pre_stru.di_inp_buf->local_meta &&
+ di_pre_stru.di_inp_buf->local_meta_used_size) {
+ memcpy(di_buf->local_meta,
+ di_pre_stru.di_inp_buf->local_meta,
+ di_pre_stru.di_inp_buf->local_meta_used_size *
+ sizeof(u8));
+ di_buf->local_meta_used_size =
+ di_pre_stru.di_inp_buf->local_meta_used_size;
+ } else {
+ di_buf->local_meta_used_size = 0;
+ }
if (de_devp->pps_enable && pps_position) {
if (pps_dstw != di_buf->vframe->width) {
di_buf->vframe->width = pps_dstw;
di_buf->vframe->type |= VIDTYPE_PRE_INTERLACE;
}
- if (is_afbc_mode) {
- di_buf->vframe->type |= VIDTYPE_PRE_DI_AFBC;
- /*pr_info("vf type:0x%x\n", di_buf->vframe->type);*/
- }
-
if (is_bypass_post()) {
if (bypass_post_state == 0)
di_pre_stru.source_change_flag = 1;
if (flag) {
di_pre_stru.irq_time[0] =
(cur_to_msecs() - di_pre_stru.irq_time[0]);
- trace_di_pre("PRE-IRQ-0",
- di_pre_stru.field_count_for_cont,
- di_pre_stru.irq_time[0]);
+ di_tr_ops.pre(di_pre_stru.field_count_for_cont,
+ di_pre_stru.irq_time[0]);
/*add from valsi wang.feng*/
di_arb_sw(false);
di_arb_sw(true);
di_post_stru.post_de_busy = 0;
di_post_stru.irq_time =
(cur_to_msecs() - di_post_stru.irq_time);
- trace_di_post("POST-IRQ-1",
- di_post_stru.post_wr_cnt,
+ di_tr_ops.post(di_post_stru.post_wr_cnt,
di_post_stru.irq_time);
DI_Wr(DI_INTR_CTRL, (data32&0xffff0004)|(intr_mode<<30));
/* disable wr back avoid pps sreay in g12a */
return 0;
}
+ if (di_buf->vframe)
+ di_tr_ops.post_set(di_buf->vframe->omx_index);
+ else
+ return 0;
if (di_post_stru.toggle_flag && di_buf->di_buf_dup_p[1])
top_bot_config(di_buf->di_buf_dup_p[1]);
if (post_wr_en && post_wr_support)
queue_in(di_buf, QUEUE_POST_DOING);
- else
+ else {
queue_in(di_buf, QUEUE_POST_READY);
+ di_tr_ops.post_ready(di_buf->vframe->omx_index);
+ }
di_print("DI:%dth %s[%d] => post ready %u ms.\n",
frame_count, vframe_type_name[di_buf->type], di_buf->index,
jiffies_to_msecs(jiffies_64 - di_buf->vframe->ready_jiffies64));
int itmp;
int ready_count = list_count(QUEUE_PRE_READY);
bool check_drop = false;
- bool di_afbc = false;
#ifdef DI_KEEP_DEC_VF
struct di_buf_s *di_tmp;
struct vframe_s *vf;
return 0;
}
- if (ready_di_buf->vframe->type & VIDTYPE_PRE_DI_AFBC) {
- di_afbc = true;
- /*pr_info("di afbc mode 0x%x\n", ready_di_buf->vframe->type);*/
- }
-
if ((ready_di_buf->post_proc_flag) &&
(ready_count >= buffer_keep_count)) {
i = 0;
memcpy(di_buf->vframe,
di_buf->di_buf_dup_p[1]->vframe,
sizeof(vframe_t));
+ if (di_buf->local_meta &&
+ di_buf->di_buf_dup_p[1]->local_meta &&
+ di_buf->di_buf_dup_p[1]->local_meta_used_size) {
+ memset(di_buf->local_meta, 0,
+ di_buf->local_meta_total_size);
+ memcpy(di_buf->local_meta,
+ di_buf->di_buf_dup_p[1]->local_meta,
+ di_buf->di_buf_dup_p[1]->local_meta_used_size * sizeof(u8));
+ di_buf->local_meta_used_size =
+ di_buf->di_buf_dup_p[1]->local_meta_used_size;
+ } else {
+ di_buf->local_meta_used_size = 0;
+ }
di_buf->vframe->private_data = di_buf;
if (di_buf->di_buf_dup_p[1]->post_proc_flag == 3) {
/* dummy, not for display */
VIDTYPE_VIU_SINGLE_PLANE |
VIDTYPE_VIU_FIELD |
VIDTYPE_PRE_INTERLACE;
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
+
di_buf->vframe->width =
di_buf->di_buf_dup_p[1]->width_bk;
if (
VIDTYPE_VIU_SINGLE_PLANE |
VIDTYPE_VIU_FIELD |
VIDTYPE_PRE_INTERLACE;
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
di_buf->vframe->height >>= 1;
di_buf->vframe->canvas0Addr =
memcpy(di_buf->vframe,
di_buf_i->vframe,
sizeof(vframe_t));
- di_buf->vframe->width = di_buf_i->width_bk;
+ if (di_buf->local_meta &&
+ di_buf_i->local_meta &&
+ di_buf_i->local_meta_used_size) {
+ memset(di_buf->local_meta, 0,
+ di_buf->local_meta_total_size);
+ memcpy(di_buf->local_meta,
+ di_buf_i->local_meta,
+ di_buf_i->local_meta_used_size *
+ sizeof(u8));
+ di_buf->local_meta_used_size =
+ di_buf_i->local_meta_used_size;
+ } else {
+ di_buf->local_meta_used_size = 0;
+ }
+ if (IS_COMP_MODE(di_buf_i->vframe->type) &&
+ (di_buf_i->dw_width_bk != 0xffff))
+ di_buf->vframe->width =
+ di_buf_i->dw_width_bk;
+ else
+ di_buf->vframe->width =
+ di_buf_i->width_bk;
di_buf->vframe->private_data = di_buf;
if (ready_di_buf->new_format_flag &&
|= VIDTYPE_VIU_FIELD;
di_buf->vframe->type
&= ~(VIDTYPE_TYPEMASK);
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
di_buf->vframe->process_fun
= (post_wr_en && post_wr_support)?NULL:de_post_process;
memcpy(di_buf->vframe,
di_buf->di_buf_dup_p[0]->vframe,
sizeof(vframe_t));
+ if (di_buf->local_meta &&
+ di_buf->di_buf_dup_p[0]->local_meta &&
+ di_buf->di_buf_dup_p[0]->local_meta_used_size) {
+ memset(di_buf->local_meta, 0,
+ di_buf->local_meta_total_size);
+ memcpy(di_buf->local_meta,
+ di_buf->di_buf_dup_p[0]->local_meta,
+ di_buf->di_buf_dup_p[0]->local_meta_used_size * sizeof(u8));
+ di_buf->local_meta_used_size =
+ di_buf->di_buf_dup_p[0]->local_meta_used_size;
+ } else {
+ di_buf->local_meta_used_size = 0;
+ }
di_buf->vframe->private_data = di_buf;
/*separate one progressive frame
VIDTYPE_VIU_SINGLE_PLANE |
VIDTYPE_VIU_FIELD |
VIDTYPE_PRE_INTERLACE;
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
if (
di_buf->di_buf_dup_p[0]->
VIDTYPE_PROGRESSIVE |
VIDTYPE_VIU_422 |
VIDTYPE_VIU_SINGLE_PLANE;
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
if (
(di_buf->di_buf_dup_p[0]->
VIDTYPE_VIU_SINGLE_PLANE |
VIDTYPE_VIU_FIELD |
VIDTYPE_PRE_INTERLACE;
- if (di_afbc)
- di_buf->vframe->type |=
- VIDTYPE_PRE_DI_AFBC;
di_buf->vframe->height >>= 1;
di_buf->vframe->width =
adpative_combing_exit();
enable_di_pre_mif(false, mcpre_en);
/*disable afbc module when afbc working in DI*/
- afbc_reg_unreg_flag = 0;
+ /*afbc_reg_unreg_flag = 0;*/
#if 0
if (IS_COMP_MODE(di_pre_stru.cur_inp_type) &&
(!needbypass_flag && !isbypass_flag)) {
afbc_input_sw(false);
}
#endif
+ if (di_afds())
+ di_afds()->reg_sw(false);
di_hw_uninit();
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()
(de_devp->flag_cma == 4)) {
pr_dbg("%s:cma release req time: %d ms\n",
__func__, jiffies_to_msecs(jiffies));
- di_pre_stru.cma_release_req = 1;
+ //di_pre_stru.cma_release_req = 1;
+ atomic_set(&di_pre_stru.cma_release_req, 1);
up(&di_sema);
+ di_pr_info("rel\n");
}
#endif
/*dbg*/
if (vf->type & VIDTYPE_PIC)
return true;
-
- if ((vf->type & VIDTYPE_INTERLACE_BOTTOM) == 0)
- return true;
#if 0
if (vf->type & VIDTYPE_COMPRESS)
return true;
#else
/*support G12A and TXLX platform*/
if (vf->type & VIDTYPE_COMPRESS) {
- if (!afbc_is_supported())
+ if (di_afds() && !di_afds()->is_supported())
return true;
if ((vf->compHeight > (default_height + 8))
|| (vf->compWidth > default_width))
vframe = vf_peek(VFM_NAME);
if (vframe) {
+ if (di_afds())
+ di_afds()->reg_val();
+
if (need_bypass(vframe) || ((di_debug_flag>>20) & 0x1)) {
if (!di_pre_stru.bypass_flag) {
- pr_info("DI bypass all %ux%u-0x%x.",
- vframe->width, vframe->height, vframe->type);
+ pr_info("DI bypass all %ux%u-0x%x.\n",
+ vframe->width,
+ vframe->height,
+ vframe->type);
}
di_pre_stru.bypass_flag = true;
di_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
} else {
di_pre_stru.bypass_flag = false;
}
+ di_tr_ops.pre_get(vframe->omx_index);
/* patch for vdin progressive input */
if ((is_from_vdin(vframe) &&
is_progressive(vframe))
/*di pre h scaling down: sm1 tm2*/
de_devp->h_sc_down_en = pre_hsc_down_en;
switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON);
- diwr_set_power_control_pst(1);
if (post_wr_en && post_wr_support)
diwr_set_power_control(1);
/* up for vpu clkb rate change */
DI_Wr(DI_CLKG_CTRL, 0xfef60001);
/* nr/blend0/ei0/mtn0 clock gate */
}
+
+ if (di_afds())
+ di_afds()->reg_sw(true);
di_hdr2_hist_init();
if (di_printk_flag & 2)
di_printk_flag = 1;
}
#ifdef CONFIG_CMA
/* mutex_lock(&de_devp->cma_mutex);*/
- if (di_pre_stru.cma_release_req) {
+ if (atomic_read(&di_pre_stru.cma_release_req) &&
+ (!atomic_read(&di_clear_unreg))) {
atomic_set(&devp->mem_flag, 0);
di_cma_release(devp);
- di_pre_stru.cma_release_req = 0;
+ //di_pre_stru.cma_release_req = 0;
+ atomic_set(&di_pre_stru.cma_release_req, 0);
di_pre_stru.cma_alloc_done = 0;
}
if (di_pre_stru.cma_alloc_req) {
+ di_pr_info("all=%d\n",
+ atomic_read(&di_pre_stru.cma_release_req));
if (di_cma_alloc(devp))
atomic_set(&devp->mem_flag, 1);
else
di_pre_stru.cma_alloc_done = 1;
}
if (di_free_mem_pre()) {
+ usleep_range(40000, 40001);
di_cma_release(devp);
di_pr_info("release mirror\n");
atomic_set(&di_trig_free_mem, 0);
} else {
pr_info("di:no w\n");
}
- di_pre_stru.wait_afbc = false;
+
while (di_pre_stru.unreg_req_flag ||
di_pre_stru.reg_irq_busy) {
usleep_range(1000, 1001);
pr_info("%s: vframe provider reg %s\n", __func__,
provider_name);
ddbg_mod_save(eDI_DBG_MOD_REGB, 0, 0);
- di_pre_stru.wait_afbc = false;
+
atomic_set(&di_flag_unreg, 0); //ary
bypass_state = 0;
di_pre_stru.reg_req_flag = 1;
}
ddbg_mod_save(eDI_DBG_MOD_REGE, 0, 0);
mutex_unlock(&di_event_mutex);
+ pr_info("vpu_clkb = %ld.\n", clk_get_rate(de_devp->vpu_clkb));
pr_info("DI: reg f\n");
}
#ifdef DET3D
struct di_buf_s *di_buf = NULL;
video_peek_cnt++;
- if (di_pre_stru.bypass_flag)
+ if (di_pre_stru.bypass_flag) {
+ di_tr_ops.post_peek(0);
return vf_peek(VFM_NAME);
+ }
if ((init_flag == 0) || recovery_flag ||
- di_blocking || di_pre_stru.unreg_req_flag || dump_state_flag)
+ di_blocking || di_pre_stru.unreg_req_flag || dump_state_flag) {
+ di_tr_ops.post_peek(1);
return NULL;
+ }
if ((run_flag == DI_RUN_FLAG_PAUSE) ||
- (run_flag == DI_RUN_FLAG_STEP_DONE))
+ (run_flag == DI_RUN_FLAG_STEP_DONE)) {
+ di_tr_ops.post_peek(2);
return NULL;
-
+ }
+ /**************************/
+ if (list_count(QUEUE_DISPLAY) > 4) {
+ di_tr_ops.post_peek(3);
+ return NULL;
+ }
+ /**************************/
log_buffer_state("pek");
/*fast_process();*/
vframe_type_name[di_buf->type],
di_buf->index, vframe_ret);
#endif
+ if (vframe_ret)
+ di_tr_ops.post_peek(9);
+ else
+ di_tr_ops.post_peek(4);
return vframe_ret;
}
return vf_get(VFM_NAME);
if ((init_flag == 0) || recovery_flag ||
- di_blocking || di_pre_stru.unreg_req_flag || dump_state_flag)
+ di_blocking || di_pre_stru.unreg_req_flag || dump_state_flag) {
+ di_tr_ops.post_get2(1);
return NULL;
+ }
if ((run_flag == DI_RUN_FLAG_PAUSE) ||
- (run_flag == DI_RUN_FLAG_STEP_DONE))
+ (run_flag == DI_RUN_FLAG_STEP_DONE)) {
+ di_tr_ops.post_get2(2);
return NULL;
+ }
#ifdef SUPPORT_START_FRAME_HOLD
if ((disp_frame_count == 0) && (is_bypass(NULL) == 0)) {
if (di_buf) {
vframe_ret = di_buf->vframe;
nr_buf = di_buf->di_buf_dup_p[1];
+
+ clear_vframe_src_fmt(vframe_ret);
+ if (di_buf->local_meta &&
+ di_buf->local_meta_used_size)
+ update_vframe_src_fmt(
+ vframe_ret, di_buf->local_meta,
+ di_buf->local_meta_used_size,
+ false, NULL, NULL);
+
if ((post_wr_en && post_wr_support) &&
(di_buf->process_fun_index != PROCESS_FUN_NULL)) {
#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
di_buf->index, vframe_ret,
jiffies_to_msecs
(jiffies_64 - vframe_ret->ready_jiffies64));
+ di_tr_ops.post_get(vframe_ret->omx_index);
+ di_tr_ops.pos_cnt0(vframe_ret->omx_index);
+ di_tr_ops.pos_cnt1(vframe_ret->omx_index);
+ } else {
+ di_tr_ops.post_get2(3);
}
if (!post_wr_en && di_post_stru.run_early_proc_fun_flag && vframe_ret) {
static void set_di_flag(void)
{
+ struct di_dev_s *de_devp = get_di_de_devp();
+
if (is_meson_txl_cpu() ||
is_meson_txlx_cpu() ||
is_meson_gxlx_cpu() ||
di_limit_local = 6;
mtn_int_combing_glbmot();
+ if (!de_devp)
+ return;
+
+ if (is_meson_tm2b())
+ de_devp->ic_id = DI_IC_ID_TM2B;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TM2))
+ de_devp->ic_id = DI_IC_ID_TM2;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+ de_devp->ic_id = DI_IC_ID_TL1;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_SM1))
+ de_devp->ic_id = DI_IC_ID_SM1;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B))
+ de_devp->ic_id = DI_IC_ID_G12B;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+ de_devp->ic_id = DI_IC_ID_G12A;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
+ de_devp->ic_id = DI_IC_ID_TXHD;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
+ de_devp->ic_id = DI_IC_ID_GXLX;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
+ de_devp->ic_id = DI_IC_ID_TXLX;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
+ de_devp->ic_id = DI_IC_ID_TXL;
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXL))
+ de_devp->ic_id = DI_IC_ID_GXL;
+ else
+ de_devp->ic_id = DI_IC_ID_GXL;
+ di_pr_info("ic_id:0x%x [b]%d\n", de_devp->ic_id, is_meson_rev_b());
}
#if 0 /*move to di_local.c*/
#endif
}
+static struct div1_meson_data deinterlace = {
+ //.cpu_type = MESON_CPU_MAJOR_ID_DEINTERLACE,
+ .name = "di_deinterlace",
+ .ic_id = DI_IC_ID_DEINTERLACE,
+};
+
+static struct div1_meson_data deinterlace_tm2_revb = {
+ //.cpu_type = MESON_CPU_MAJOR_ID_TM2_REVB,
+ .name = "di_tm2_vb",
+ .ic_id = DI_IC_ID_TM2B,
+};
+
+static const struct of_device_id amlogic_deinterlace_dt_match[] = {
+ {
+ .compatible = "amlogic, deinterlace",
+ .data = &deinterlace,
+ },
+ {
+ .compatible = "amlogic, deinterlace_di_tm2b",
+ .data = &deinterlace_tm2_revb,
+ },
+ {}
+};
+
+bool is_meson_tm2b(void)
+{
+ if (getv1_datal()->mdata->ic_id == DI_IC_ID_TM2B)
+ return true;
+ else
+ return false;
+}
+
static int di_probe(struct platform_device *pdev)
{
int ret = 0;
struct di_dev_s *di_devp = NULL;
+ const struct of_device_id *match;
+ struct div1_data_l_s *pdata;
+ //struct di_device_data_s *di_meson;
+
di_pr_info("%s:\n", __func__);
#if 1 /*move from init*/
}
de_devp = di_devp;
memset(di_devp, 0, sizeof(struct di_dev_s));
+
+ di_devp->data_l = NULL;
+ di_devp->data_l = kzalloc(sizeof(struct div1_data_l_s), GFP_KERNEL);
+ if (!di_devp->data_l) {
+ pr_error("%s fail to allocate data l.\n", __func__);
+ goto fail_kmalloc_datal;
+ }
+
di_devp->flags |= DI_SUSPEND_FLAG;
cdev_init(&(di_devp->cdev), &di_fops);
di_devp->cdev.owner = THIS_MODULE;
}
dev_set_drvdata(di_devp->dev, di_devp);
platform_set_drvdata(pdev, di_devp);
+
+ match = of_match_device(amlogic_deinterlace_dt_match,
+ &pdev->dev);
+ if (!match) {
+ pr_error("%s,no matched table\n", __func__);
+ goto fail_cdev_add;
+ } else {
+ pdata = (struct div1_data_l_s *)di_devp->data_l;
+ pdata->mdata = match->data;
+ pr_info("match name: %s:id[%d]\n", pdata->mdata->name,
+ pdata->mdata->ic_id);
+ }
ret = of_reserved_mem_device_init(&pdev->dev);
if (ret != 0)
pr_info("DI no reserved mem.\n");
return ret;
}
#endif
-
+ de_devp->local_meta_size =
+ LOCAL_META_BUFF_SIZE *
+ (MAX_IN_BUF_NUM + MAX_POST_BUF_NUM +
+ (MAX_LOCAL_BUF_NUM * 2)) * sizeof(u8);
+ de_devp->local_meta_addr = vmalloc(de_devp->local_meta_size);
+ if (!de_devp->local_meta_addr) {
+ pr_info("DI: allocate local meta buffer fail, disable this function!\n");
+ de_devp->local_meta_size = 0;
+ }
device_create_file(di_devp->dev, &dev_attr_config);
device_create_file(di_devp->dev, &dev_attr_debug);
device_create_file(di_devp->dev, &dev_attr_dump_pic);
device_create_file(di_devp->dev, &dev_attr_provider_vframe_status);
device_create_file(di_devp->dev, &dev_attr_frame_format);
device_create_file(di_devp->dev, &dev_attr_tvp_region);
- device_create_file(di_devp->dev, &dev_attr_secam);
pd_device_files_add(di_devp->dev);
nr_drv_init(di_devp->dev);
mutex_init(&di_event_mutex);
di_hw_init(pulldown_enable, mcpre_en);
set_di_flag();
atomic_set(&di_flag_unreg, 0);
+ atomic_set(&di_clear_unreg, 0);
/* Disable MCDI when code does not surpport MCDI */
if (!mcpre_en)
DI_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 1);
dil_attach_ext_api(&di_ext);
di_patch_mov_ini();
+ di_attach_ops_afd(&di_devp->afds);
+ if (di_afds())
+ di_afds()->prob(di_devp->ic_id);
+ dil_set_cpuver_flag(getv1_datal()->mdata->ic_id);
dil_set_diffver_flag(0);
fail_cdev_add:
pr_info("%s:fail_cdev_add\n", __func__);
kfree(di_devp);
-
+fail_kmalloc_datal:
+ pr_info("%s:fail_kmalloc datal\n", __func__);
fail_kmalloc_dev:
#if 1 /*move from init*/
class_destroy(di_clsp);
di_debugfs_exit();
unregister_chrdev_region(di_devno, DI_COUNT);
#endif
+ vfree(di_devp->local_meta_addr);
kfree(di_devp);
/* free drvdata */
dev_set_drvdata(&pdev->dev, NULL);
pr_info("%s\n", __func__);
atomic_set(&di_flag_unreg, 1);
+ atomic_set(&di_clear_unreg, 1);
di_unreg_process();/*have flag*/
if (di_pre_stru.unreg_req_flag_irq)
di_unreg_process_irq();
#ifdef CONFIG_CMA
- if (di_pre_stru.cma_release_req) {
+ if (atomic_read(&di_pre_stru.cma_release_req)) {
pr_info("\tcma_release\n");
atomic_set(&di_devp->mem_flag, 0);
di_cma_release(di_devp);
- di_pre_stru.cma_release_req = 0;
+ //di_pre_stru.cma_release_req = 0;
+ atomic_set(&di_pre_stru.cma_release_req, 0);
di_pre_stru.cma_alloc_done = 0;
}
#endif
+ atomic_set(&di_clear_unreg, 0);
#ifdef DI_KEEP_HIS
hrtimer_cancel(&di_pre_hrtimer);
tasklet_kill(&di_pre_tasklet); //ary.sui
#endif
/* #ifdef CONFIG_USE_OF */
+#ifdef MARK_HIS
static const struct of_device_id amlogic_deinterlace_dt_match[] = {
{ .compatible = "amlogic, deinterlace", },
{},
};
+#endif
/* #else */
/* #define amlogic_deinterlace_dt_match NULL */
/* #endif */
/* for android q s805 */
#define DI_UNREG_RELEAS_ALL_BUF (1)
+#ifdef CONFIG_AMLOGIC_MEDIA_LUT_DMA
+#define DI_FILM_GRAIN
+#endif
+
+/**************************************
+ *
+ * debug config infor
+ *
+ *************************************/
+#define DI_NONE 0x00000000
+#define DI_BIT0 0x00000001
+#define DI_BIT1 0x00000002
+#define DI_BIT2 0x00000004
+#define DI_BIT3 0x00000008
+#define DI_BIT4 0x00000010
+#define DI_BIT5 0x00000020
+#define DI_BIT6 0x00000040
+#define DI_BIT7 0x00000080
+#define DI_BIT8 0x00000100
+#define DI_BIT9 0x00000200
+#define DI_BIT10 0x00000400
+#define DI_BIT11 0x00000800
+#define DI_BIT12 0x00001000
+#define DI_BIT13 0x00002000
+#define DI_BIT14 0x00004000
+#define DI_BIT15 0x00008000
+#define DI_BIT16 0x00010000
+#define DI_BIT17 0x00020000
+#define DI_BIT18 0x00040000
+#define DI_BIT19 0x00080000
+#define DI_BIT20 0x00100000
+#define DI_BIT21 0x00200000
+#define DI_BIT22 0x00400000
+#define DI_BIT23 0x00800000
+#define DI_BIT24 0x01000000
+#define DI_BIT25 0x02000000
+#define DI_BIT26 0x04000000
+#define DI_BIT27 0x08000000
+#define DI_BIT28 0x10000000
+#define DI_BIT29 0x20000000
+#define DI_BIT30 0x40000000
+#define DI_BIT31 0x80000000
+
+#define DBG_M_FG DI_BIT0 /*do film grain work*/
+
/*trigger_pre_di_process param*/
#define TRIGGER_PRE_BY_PUT 'p'
#define TRIGGER_PRE_BY_DE_IRQ 'i'
/* buffer management related */
#define MAX_IN_BUF_NUM 20
-#define MAX_LOCAL_BUF_NUM 16 //10
+#define MAX_LOCAL_BUF_NUM 10
#define MAX_POST_BUF_NUM 16
#define VFRAME_TYPE_IN 1
#define VFRAME_TYPE_POST 3
#define VFRAME_TYPE_NUM 3
+#define LOCAL_META_BUFF_SIZE 0x800 /* 2K size */
+
/*vframe define*/
#define vframe_t struct vframe_s
#define IS_COMP_MODE(vftype) (vftype & VIDTYPE_COMPRESS)
+#define IS_420P_SRC(vftype) (((vftype) & VIDTYPE_INTERLACE_BOTTOM) == 0 && \
+ ((vftype) & VIDTYPE_VIU_422) == 0 && \
+ ((vftype) & VIDTYPE_VIU_444) == 0)
+
enum process_fun_index_e {
PROCESS_FUN_NULL = 0,
PROCESS_FUN_DI,
bool bflg_vmap;
unsigned long mcvec_adr;
int mcvec_canvas_idx;
+ unsigned long afbc_adr;
+ unsigned long afbct_adr;
struct mcinfo_pre_s {
unsigned int highvertfrqflg;
unsigned int motionparadoxflg;
atomic_t di_cnt;
struct page *pages;
u32 width_bk;
+ u32 dw_width_bk;
+ /* local meta buffer */
+ u8 *local_meta;
+ u32 local_meta_used_size;
+ u32 local_meta_total_size;
};
#define RDMA_DET3D_IRQ 0x20
/* vdin0 rdma irq */
#define MAX_CANVAS_WIDTH 1920
#define MAX_CANVAS_HEIGHT 1088
-
-/* #define DI_BUFFER_DEBUG */
-
#define DI_LOG_MTNINFO 0x02
#define DI_LOG_PULLDOWN 0x10
#define DI_LOG_BUFFER_STATE 0x20
#define TABLE_LEN_MAX 10000
#define TABLE_FLG_END (0xfffffffe)
+extern unsigned int di_dbg_cfg; /* add for debug config */
+
/******************************************
* patch for TV-10258 multiwave group issue
*****************************************/
struct dentry *dbg_root; /*dbg_fs*/
struct vframe_s vfm_in_dup[MAX_IN_BUF_NUM];
struct vframe_s vfm_local[MAX_LOCAL_BUF_NUM * 2];
+ u8 *local_meta_addr;
+ u32 local_meta_size;
struct di_patch_mov_s mov;
u32 instance_id; /* di_instance_id; */
+ unsigned int ic_id;
+ struct afdv1_s di_afd;
+ const struct afdv1_ops_s *afds;
+ void *data_l;
+};
+
+#ifdef DI_FILM_GRAIN
+struct fgrain_diset_s {
+ u32 start_x;
+ u32 end_x;
+ u32 start_y;
+ u32 end_y;
+ u32 fmt_mode; /* only support 420 */
+ u32 bitdepth; /* 8 bit or 10 bit */
+ u32 reverse;
+ u32 afbc; /* afbc or not */
+ u32 last_in_mode; /* related with afbc */
+ u32 used;
+ /* lut dma */
+ u32 fgs_table_adr;
+ u32 table_size;
};
+void di_fgrain_config(struct DI_MIF_s *mif_setting,
+ struct fgrain_diset_s *setting,
+ struct vframe_s *vf);
+void di_fgrain_setting(struct fgrain_diset_s *setting,
+ struct vframe_s *vf);
+void di_fgrain_update_table(struct vframe_s *vf);
+#endif
+
struct di_pre_stru_s {
/* pre input */
struct DI_MIF_s di_inp_mif;
int mcinfo_size;
int mv_size;
int mtn_size;
+ int di_size; /* no afbc info size */
+ int afbci_size; /* afbc info size */
+ int afbct_size;
int cma_alloc_req;
int cma_alloc_done;
- int cma_release_req;
+ //int cma_release_req;
+ atomic_t cma_release_req;
/* for performance debug */
unsigned long irq_time[2];
/* combing adaptive */
struct combing_status_s *mtn_status;
- u64 afbc_rls_time;
- bool wait_afbc;
/*****************/
bool retry_en;
unsigned int retry_index;
/*****************/
bool combing_fix_en;
unsigned int comb_mode;
+ #ifdef DI_FILM_GRAIN
+ struct fgrain_diset_s fgrain_diset;
+ #endif
/*struct di_patch_mov_s mov;*/
+ s8 is_tvp; /* -1: unknown, 0: non tvp, 1: tvp */
};
struct di_post_stru_s {
unsigned long addr;
};
+enum cpu_type_e {
+ MESON_CPU_MAJOR_ID_DEINTERLACE = 0x1,
+ MESON_CPU_MAJOR_ID_TM2_REVB,
+ MESON_CPU_MAJOR_ID_UNKNOWN,
+};
+
+struct div1_meson_data {
+ const char *name;
+ unsigned int ic_id;
+ /*struct ic_ver icver;*/
+ /*struct ddemod_reg_off regoff;*/
+};
+
+struct div1_data_l_s {
+ const struct div1_meson_data *mdata;
+};
+
bool di_mm_alloc(int cma_mode, size_t count, struct di_mm_s *o);
bool di_mm_release(int cma_mode,
struct page *pages,
unsigned char is_bypass(vframe_t *vf_in);
+bool is_meson_tm2b(void);
/*---get di state parameter---*/
struct di_dev_s *get_di_de_devp(void);
void di_unreg_notify(void); //from video.c
s32 di_request_afbc_hw(u8 id, bool on);
-u32 di_requeset_afbc(u32 onoff);
/***********************/
bool di_wr_cue_int(void);
int get_mirror_status(void);
int reg_cue_int_show(struct seq_file *seq, void *v);
-
+int di_get_disp_cnt_demo(void);
bool dil_attach_ext_api(const struct di_ext_ops *di_api);
+const struct afdv1_ops_s *di_afds(void);
+struct afbcdv1_ctr_s *div1_get_afd_ctr(void);
+
/*--Different DI versions flag---*/
void dil_set_diffver_flag(unsigned int para);
#define pr_dbg(fmt, args ...) pr_debug("DI: " fmt, ## args)
-#define pr_error(fmt, args ...) pr_err("DI: " fmt, ## args)
+#define pr_error(fmt, args ...) pr_err("DI:err:" fmt, ## args)
/******************************************/
/*#define DI_KEEP_HIS 0*/
#include "di_pps.h"
#include "nr_downscale.h"
#include <linux/amlogic/media/vfm/vframe_provider.h>
-
+/********************************
+ *trace:
+ *******************************/
+#define CREATE_TRACE_POINTS
+#include "deinterlace_trace.h"
+
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE deinterlace_trace
+#include <trace/define_trace.h>
+/**********************/
/*2018-07-18 add debugfs*/
#include <linux/seq_file.h>
vf->pixel_ratio, &vf->list);
pr_info("di_pulldown 0x%x\n", vf->di_pulldown);
pr_info("di_gmv 0x%x\n", vf->di_gmv);
+ pr_info("di_mc_cnt 0x%x\n", vf->di_cm_cnt);
}
void print_di_buf(struct di_buf_s *di_buf, int format)
}
}
-void dump_afbcd_reg(void)
-{
- u32 i;
- u32 afbc_reg;
-
- pr_info("---- dump afbc eAFBC_DEC0 reg -----\n");
- for (i = 0; i < AFBC_REG_INDEX_NUB; i++) {
- afbc_reg = reg_AFBC[eAFBC_DEC0][i];
- pr_info("reg 0x%x val:0x%x\n", afbc_reg, RDMA_RD(afbc_reg));
- }
- pr_info("---- dump afbc eAFBC_DEC1 reg -----\n");
- for (i = 0; i < AFBC_REG_INDEX_NUB; i++) {
- afbc_reg = reg_AFBC[eAFBC_DEC1][i];
- pr_info("reg 0x%x val:0x%x\n", afbc_reg, RDMA_RD(afbc_reg));
- }
- pr_info("reg 0x%x val:0x%x\n",
- VD1_AFBCD0_MISC_CTRL, RDMA_RD(VD1_AFBCD0_MISC_CTRL));
- pr_info("reg 0x%x val:0x%x\n",
- VD2_AFBCD1_MISC_CTRL, RDMA_RD(VD2_AFBCD1_MISC_CTRL));
-}
-
static int dbg_patch_mov_data_show(struct seq_file *seq, void *v)
{
struct di_dev_s *de_devp = get_di_de_devp();
return 0;
}
+static int dbg_afd0_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afd_reg(s, EAFBC_DEC0);
+ return 0;
+}
+
+static int dbg_afd1_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afd_reg(s, EAFBC_DEC1);
+ return 0;
+}
+
+static int dbg_afd2_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afd_reg(s, EAFBC_DEC2_DI);
+ return 0;
+}
+
+static int dbg_afd3_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afd_reg(s, EAFBC_DEC3_MEM);
+ return 0;
+}
/*2018-08-17 add debugfs*/
#define DEFINE_SHOW_DI(__name) \
static int __name ## _open(struct inode *inode, struct file *file) \
DEFINE_SHOW_DI(reg_cue_int);
DEFINE_SHOW_DI(dbg_patch_mov_data);
+DEFINE_SHOW_DI(dbg_afbc_cfg);
+DEFINE_SHOW_DI(dbg_afd0_reg);
+DEFINE_SHOW_DI(dbg_afd1_reg);
+DEFINE_SHOW_DI(dbg_afd2_reg);
+DEFINE_SHOW_DI(dbg_afd3_reg);
struct di_debugfs_files_t {
const char *name;
const umode_t mode;
{"dumpafbc", S_IFREG | 0644, &seq_file_afbc_fops},
{"reg_cue", S_IFREG | 0644, ®_cue_int_fops},
{"dumpmov", S_IFREG | 0644, &dbg_patch_mov_data_fops},
+ {"afbc_cfg", S_IFREG | 0644, &dbg_afbc_cfg_fops},
+ {"reg_afd0", S_IFREG | 0644, &dbg_afd0_reg_fops},
+ {"reg_afd1", S_IFREG | 0644, &dbg_afd1_reg_fops},
+ {"reg_afd2", S_IFREG | 0644, &dbg_afd2_reg_fops},
+ {"reg_afd3", S_IFREG | 0644, &dbg_afd3_reg_fops},
};
void di_debugfs_init(void)
}
/*-----------------------*/
+/********************************
+ *trace:
+ *******************************/
+
+u64 dicur_to_usecs(void)/*2019*/
+{
+ u64 cur = sched_clock();
+
+ do_div(cur, NSEC_PER_USEC);
+ return cur;
+}
+
+#define DI_TRACE_LIMIT_DEMO 10000
+
+static void trace_pre_cnt0(unsigned int index)
+{
+ u64 data = 0;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ if (is_meson_tm2_cpu() && is_meson_tm2b())
+ data = RDMA_RD(DI_RO_PRE_FIELD_CNT0);
+
+ trace_di_pre_cnt0("PRE-GET-CNT0", index, data);
+}
+
+static void trace_pre_cnt1(unsigned int index)
+{
+ u64 data = 0;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ if (is_meson_tm2_cpu() && is_meson_tm2b())
+ data = RDMA_RD(DI_RO_PRE_FIELD_CNT1);
+ trace_di_pre_cnt1("PRE-GET-CNT1", index, data);
+}
+
+static void trace_pos_cnt0(unsigned int index)
+{
+ u64 data = 0;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ if (is_meson_tm2_cpu() && is_meson_tm2b())
+ data = RDMA_RD(DI_RO_POS_FRAME_CNT0);
+ trace_di_pos_cnt0("POS-GET-CNT0", index, data);
+}
+
+static void trace_pos_cnt1(unsigned int index)
+{
+ u64 data = 0;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ if (is_meson_tm2_cpu() && is_meson_tm2b())
+ data = RDMA_RD(DI_RO_POS_FRAME_CNT1);
+ trace_di_pos_cnt1("POS-GET-CNT1", index, data);
+}
+
+static void di_trace_pre(unsigned int index, unsigned long ctime)
+{
+ trace_di_pre("PRE-IRQ-0", index, ctime);
+}
+
+static void di_trace_post(unsigned int index, unsigned long ctime)
+{
+ trace_di_post("POST-IRQ-1", index, ctime);
+}
+
+static void di_pre_get(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pre_getxx("PRE-GET-01", index, ustime);
+}
+
+static void di_pre_set(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pre_setxx("PRE-SET-01", index, ustime);
+}
+
+static void di_pre_ready(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pre_ready("PRE-READY2", index, ustime);
+}
+
+static void di_post_ready(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_ready("PST-READY3", index, ustime);
+}
+
+static void di_post_get(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_getxx("PST-GET-04", index, ustime);
+}
+
+static void di_post_get2(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_get2x("PST-GET-0a", index, ustime);
+}
+
+static void di_post_set(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_setxx("PST-SET-05", index, ustime);
+}
+
+static void di_post_irq(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_irxxx("PST-IRQ-06", index, ustime);
+}
+
+static void di_post_doing(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_doing("PST-DOI-07", index, ustime);
+}
+
+static void di_post_peek(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt_demo() > DI_TRACE_LIMIT_DEMO)
+ return;
+
+ ustime = dicur_to_usecs();
+ trace_di_pst_peekx("PST-PEEK-8", index, ustime);
+}
+
+const struct di_tr_ops_s di_tr_ops = {
+ .pre = di_trace_pre,
+ .post = di_trace_post,
+
+ .pre_cnt0 = trace_pre_cnt0,
+ .pre_cnt1 = trace_pre_cnt1,
+ .pos_cnt0 = trace_pos_cnt0,
+ .pos_cnt1 = trace_pos_cnt1,
+
+ .pre_get = di_pre_get,
+ .pre_set = di_pre_set,
+ .pre_ready = di_pre_ready,
+ .post_ready = di_post_ready,
+ .post_get = di_post_get,
+ .post_get2 = di_post_get2,
+
+ .post_set = di_post_set,
+ .post_ir = di_post_irq,
+ .post_do = di_post_doing,
+ .post_peek = di_post_peek,
+};
+
#define _DI_DBG_H
#include "deinterlace.h"
-extern const unsigned int reg_AFBC[AFBC_DEC_NUB][AFBC_REG_INDEX_NUB];
-
void parse_cmd_params(char *buf_orig, char **parm);
void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p);
void dump_di_post_stru(struct di_post_stru_s *di_post_stru_p);
void print_di_buf(struct di_buf_s *di_buf, int format);
void dump_pre_mif_state(void);
void dump_post_mif_reg(void);
-void dump_afbcd_reg(void);
void dump_buf_addr(struct di_buf_s *di_buf, unsigned int num);
void dump_mif_size_state(struct di_pre_stru_s *pre,
struct di_post_stru_s *post);
void debug_device_files_del(struct device *dev);
extern void di_debugfs_init(void);
extern void di_debugfs_exit(void);
+
+/********************************
+ *trace:
+ *******************************/
+struct di_tr_ops_s {
+ void (*pre)(unsigned int index, unsigned long ctime);
+ void (*post)(unsigned int index, unsigned long ctime);
+
+ void (*pre_cnt0)(unsigned int index);
+ void (*pre_cnt1)(unsigned int index);
+ void (*pos_cnt0)(unsigned int index);
+ void (*pos_cnt1)(unsigned int index);
+
+ void (*pre_get)(unsigned int index);
+ void (*pre_set)(unsigned int index);
+ void (*pre_ready)(unsigned int index);
+ void (*post_ready)(unsigned int index);
+ void (*post_get)(unsigned int index);
+ void (*post_get2)(unsigned int index);
+ void (*post_set)(unsigned int index);
+ void (*post_ir)(unsigned int index);
+ void (*post_do)(unsigned int index);
+ void (*post_peek)(unsigned int index);
+};
+
+extern const struct di_tr_ops_s di_tr_ops;
#endif
#include "register_nr4.h"
#include "nr_drv.h"
+#ifdef CONFIG_AMLOGIC_MEDIA_LUT_DMA
+#include <linux/amlogic/media/lut_dma/lut_dma.h>
+#endif
+
#ifdef DET3D
#include "detect3d.h"
#endif
static void post_frame_reset_g12a(void);
+/* add for film grain */
+
+#ifdef DI_FILM_GRAIN
+#define FGRAIN_TBL_SIZE (498 * 16)
+static bool difgrain_support;
+static bool difgrain_start;
+module_param_named(difgrain_support, difgrain_support, bool, 0644);
+static void di_fgrain_set_config(struct fgrain_diset_s *setting)
+{
+ u32 reg_fgrain_glb_en = 1 << 0;
+ u32 reg_fgrain_loc_en = 1 << 1;
+ u32 reg_block_mode = 1 << 2;
+ u32 reg_rev_mode = 0 << 4;
+ u32 reg_comp_bits = 0 << 6;
+ /* unsigned , RW, default = 0:8bits; 1:10bits, else 12 bits */
+ u32 reg_fmt_mode = 2 << 8;
+ /* unsigned , RW, default = 0:444; 1:422; 2:420; 3:reserved */
+ u32 reg_last_in_mode = 0 << 14;
+ u32 reg_fgrain_ext_imode = 1;
+ /* unsigned , RW, default = 0 to indicate the
+ *input data is *4 in 8bit mode
+ */
+ if (!is_meson_tm2b())
+ return;
+ if (!setting)
+ return;
+
+ reg_block_mode = setting->afbc << 2;
+ reg_rev_mode = setting->reverse << 4;
+ reg_comp_bits = setting->bitdepth << 6;
+ reg_fmt_mode = setting->fmt_mode << 8;
+ reg_last_in_mode = setting->last_in_mode << 14;
+ DI_Wr_reg_bits(DI_FGRAIN_CTRL,
+ reg_fgrain_glb_en |
+ reg_fgrain_loc_en |
+ reg_block_mode |
+ reg_rev_mode |
+ reg_comp_bits |
+ reg_fmt_mode,
+ 0, 10);
+ DI_Wr_reg_bits(DI_FGRAIN_CTRL,
+ reg_fgrain_ext_imode, 16, 1);
+}
+
+static void di_fgrain_start(void)
+{
+ u32 reg_fgrain_glb_en = 1 << 0;
+ u32 reg_fgrain_loc_en = 1 << 1;
+
+ if (!is_meson_tm2b())
+ return;
+ if (difgrain_start)
+ return;
+
+ DI_Wr_reg_bits(DI_FGRAIN_CTRL,
+ reg_fgrain_glb_en |
+ reg_fgrain_loc_en,
+ 0, 2);
+ difgrain_start = true;
+}
+
+static void di_fgrain_stop(void)
+{
+ u32 reg_fgrain_glb_en = 1 << 0;
+ u32 reg_fgrain_loc_en = 0 << 1;
+
+ if (!is_meson_tm2b())
+ return;
+ if (!difgrain_start)
+ return;
+
+ DI_Wr_reg_bits(DI_FGRAIN_CTRL,
+ reg_fgrain_glb_en |
+ reg_fgrain_loc_en,
+ 0, 2);
+ difgrain_start = false;
+}
+
+static int di_fgrain_init(u32 table_size)
+{
+ int ret;
+ u32 channel = FILM_GRAIN_DI_CHAN;
+ struct lut_dma_set_t lut_dma_set;
+
+ if (!is_meson_tm2b())
+ return -1;
+
+ difgrain_support = false;
+ lut_dma_set.channel = channel;
+ lut_dma_set.dma_dir = LUT_DMA_WR;
+ lut_dma_set.irq_source = DI_VSYNC;
+ lut_dma_set.mode = LUT_DMA_MANUAL;
+ lut_dma_set.table_size = table_size;
+ ret = lut_dma_register(&lut_dma_set);
+ return ret;
+}
+
+static void di_fgrain_uninit(void)
+{
+ if (!is_meson_tm2b())
+ return;
+ lut_dma_unregister(LUT_DMA_WR, FILM_GRAIN_DI_CHAN);
+}
+
+static void di_fgrain_set_window(struct fgrain_diset_s *setting)
+{
+ DI_Wr(DI_FGRAIN_WIN_H,
+ (setting->start_x / 32 * 32 << 0) |
+ ((setting->end_x / 32 * 32) << 16));
+ DI_Wr(DI_FGRAIN_WIN_V,
+ (setting->start_y / 4 * 4 << 0) |
+ ((setting->end_y / 4 * 4) << 16));
+}
+
+static int di_fgrain_write(u32 fgs_table_addr)
+{
+ int table_size = FGRAIN_TBL_SIZE;
+
+ lut_dma_write_phy_addr(FILM_GRAIN_DI_CHAN,
+ fgs_table_addr,
+ table_size);
+ return 0;
+}
+
+static void di_fgrain_update_irq_source(void)
+{
+ lut_dma_update_irq_source(FILM_GRAIN_DI_CHAN, DI_VSYNC);
+}
+
+void di_fgrain_config(struct DI_MIF_s *mif_setting,
+ struct fgrain_diset_s *setting,
+ struct vframe_s *vf)
+{
+ u32 type;
+
+ if (!vf || !mif_setting || !setting)
+ return;
+ if (!is_meson_tm2b())
+ return;
+
+ type = vf->type;
+
+ if (type & VIDTYPE_COMPRESS) {
+ /* 1:afbc mode or 0: non-afbc mode */
+ setting->afbc = 1;
+ /* bit[2]=0, non-afbc mode */
+ setting->last_in_mode = 0;
+ /* afbc copress is always 420 */
+ setting->fmt_mode = 2;
+ setting->used = 1;
+ } else {
+ setting->afbc = 0;
+ setting->last_in_mode = 1;
+ #if 1
+ if (type & VIDTYPE_VIU_NV21) {
+ setting->fmt_mode = 2;
+ setting->used = 1;
+ } else {
+ /* only support 420 */
+ setting->used = 0;
+ }
+ #else
+ setting->used = 0;
+ #endif
+ }
+
+ if (vf->bitdepth == BITDEPTH_Y8)
+ setting->bitdepth = 0;
+ else if (vf->bitdepth & BITDEPTH_Y10)
+ setting->bitdepth = 1;
+
+ setting->start_x = mif_setting->luma_x_start0;
+ setting->end_x = mif_setting->luma_x_end0;
+ setting->start_y = mif_setting->luma_y_start0;
+ setting->end_y = mif_setting->luma_y_end0;
+}
+
+void di_fgrain_setting(struct fgrain_diset_s *setting,
+ struct vframe_s *vf)
+{
+ if (!vf || !setting)
+ return;
+ if (!is_meson_tm2b())
+ return;
+ if (!setting->used || !vf->fgs_valid)
+ di_fgrain_stop();
+
+ if (difgrain_support) {
+ if (setting->used && vf->fgs_valid &&
+ vf->fgs_table_adr) {
+ di_fgrain_set_config(setting);
+ di_fgrain_set_window(setting);
+ }
+ }
+}
+
+void di_fgrain_update_table(struct vframe_s *vf)
+{
+ if (!vf)
+ return;
+ if (!is_meson_tm2b())
+ return;
+ if (!vf->fgs_valid)
+ di_fgrain_stop();
+
+ if (difgrain_support) {
+ if (vf->fgs_valid && vf->fgs_table_adr) {
+ di_fgrain_start();
+ di_fgrain_update_irq_source();
+ di_fgrain_write(vf->fgs_table_adr);
+ vf->fgs_valid = 0;
+ }
+ }
+}
+#endif
+
static void ma_di_init(void)
{
/* 420->422 chrome difference is large motion is large,flick */
DI_Wr(DIPD_COMB_CTRL4, 0x20070002);
if (height > 288)
DI_Wr(DIPD_COMB_CTRL5, 0x04041020);
- else
- DI_Wr(DIPD_COMB_CTRL5, 0x04040804);
+ else {
+ /*adjust flm_smp_mtn_thd from vlsi-yanling*/
+ DI_Wr(DIPD_COMB_CTRL5, 0x04040805);
+ }
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
DI_Wr(DIPD_COMB_CTRL6, 0x00107064);
DI_Wr_reg_bits(DI_MC_32LVL0, 16, 0, 8);
ma_di_init();
ei_hw_init();
nr_hw_init();
+ #ifdef DI_FILM_GRAIN
+ if (di_dbg_cfg & DBG_M_FG)
+ di_fgrain_init(FGRAIN_TBL_SIZE);
+ #endif
if (pd_enable)
init_field_mode(288);
{
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
nr_gate_control(false);
+ #ifdef DI_FILM_GRAIN
+ if (di_dbg_cfg & DBG_M_FG)
+ di_fgrain_uninit();
+ #endif
+
}
/*
RDMA_WR_BITS(CONTRD_SCOPE_X, contprd_mif->end_x, 16, 13);
RDMA_WR_BITS(CONTRD_SCOPE_Y, contprd_mif->start_y, 0, 13);
RDMA_WR_BITS(CONTRD_SCOPE_Y, contprd_mif->end_y, 16, 13);
- RDMA_WR_BITS(CONTRD_CTRL1, contprd_mif->canvas_num, 16, 8);
+ RDMA_WR_BITS(CONTRD_CTRL1, contp2rd_mif->canvas_num, 16, 8);
RDMA_WR_BITS(CONTRD_CTRL1, 2, 8, 2);
RDMA_WR_BITS(CONTRD_CTRL1, 0, 0, 3);
RDMA_WR_BITS(CONT2RD_SCOPE_X, contp2rd_mif->end_x, 16, 13);
RDMA_WR_BITS(CONT2RD_SCOPE_Y, contp2rd_mif->start_y, 0, 13);
RDMA_WR_BITS(CONT2RD_SCOPE_Y, contp2rd_mif->end_y, 16, 13);
- RDMA_WR_BITS(CONT2RD_CTRL1, contp2rd_mif->canvas_num, 16, 8);
+ RDMA_WR_BITS(CONT2RD_CTRL1, contprd_mif->canvas_num, 16, 8);
RDMA_WR_BITS(CONT2RD_CTRL1, 2, 8, 2);
RDMA_WR_BITS(CONT2RD_CTRL1, 0, 0, 3);
}
}
-const unsigned int reg_AFBC[AFBC_DEC_NUB][AFBC_REG_INDEX_NUB] = {
- {
- AFBC_ENABLE,
- AFBC_MODE,
- AFBC_SIZE_IN,
- AFBC_DEC_DEF_COLOR,
- AFBC_CONV_CTRL,
- AFBC_LBUF_DEPTH,
- AFBC_HEAD_BADDR,
- AFBC_BODY_BADDR,
- AFBC_SIZE_OUT,
- AFBC_OUT_YSCOPE,
- AFBC_STAT,
- AFBC_VD_CFMT_CTRL,
- AFBC_VD_CFMT_W,
- AFBC_MIF_HOR_SCOPE,
- AFBC_MIF_VER_SCOPE,
- AFBC_PIXEL_HOR_SCOPE,
- AFBC_PIXEL_VER_SCOPE,
- AFBC_VD_CFMT_H,
- },
- {
- VD2_AFBC_ENABLE,
- VD2_AFBC_MODE,
- VD2_AFBC_SIZE_IN,
- VD2_AFBC_DEC_DEF_COLOR,
- VD2_AFBC_CONV_CTRL,
- VD2_AFBC_LBUF_DEPTH,
- VD2_AFBC_HEAD_BADDR,
- VD2_AFBC_BODY_BADDR,
- VD2_AFBC_OUT_XSCOPE,
- VD2_AFBC_OUT_YSCOPE,
- VD2_AFBC_STAT,
- VD2_AFBC_VD_CFMT_CTRL,
- VD2_AFBC_VD_CFMT_W,
- VD2_AFBC_MIF_HOR_SCOPE,
- VD2_AFBC_MIF_VER_SCOPE,
- VD2_AFBC_PIXEL_HOR_SCOPE,
- VD2_AFBC_PIXEL_VER_SCOPE,
- VD2_AFBC_VD_CFMT_H,
-
- },
-
-};
-
-enum eAFBC_DEC afbc_get_decnub(void)
-{
- enum eAFBC_DEC sel_dec = eAFBC_DEC0;
- /* info from vlsi feijun
- * gxl:have 1, AFBC_dec0
- * txlx:have 2, di only can use 1
- * g12a:have 2, di can use 2
- * tl1: have 1, AFBC_dec0
- */
- if (is_meson_gxl_cpu())
- sel_dec = eAFBC_DEC0;
- else if (is_meson_txlx_cpu())
- sel_dec = eAFBC_DEC1;
- else if (is_meson_g12a_cpu())
- sel_dec = eAFBC_DEC1;
- else if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- sel_dec = eAFBC_DEC0;
- return sel_dec;
-}
-
-static const unsigned int *afbc_get_regbase(void)
-{
- return ®_AFBC[afbc_get_decnub()][0];
-}
-
-bool afbc_is_supported(void)
-{
- bool ret = false;
-
- if (afbc_disable_flag)
- return false;
-
- /*currently support txlx and g12a*/
- if (is_meson_txlx_cpu())
- ret = false;
- else if (is_meson_g12a_cpu())
- ret = false;
- else if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- ret = false;
-
- return ret;
-
-}
-
-/*
- * after g12a, framereset will not reset simple
- * wr mif of pre such as mtn&cont&mv&mcinfo wr
- */
-
-#if 0
-void enable_afbc_input(struct vframe_s *vf)
-{
- unsigned int r, u, v;
-
- if (vf->type & VIDTYPE_COMPRESS) {
- r = (3 << 24) |
- (10 << 16) |
- (1 << 14) | /*burst1 1*/
- vf->bitdepth;
-
- if ((vf->type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP)
- r |= 0x44;
- else if ((vf->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_BOTTOM)
- r |= 0x88;
-
- RDMA_WR(AFBC_MODE, r);
- RDMA_WR(AFBC_CONV_CTRL, 0x100);
- u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
- v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
- RDMA_WR(AFBC_DEC_DEF_COLOR,
- 0x3FF00000 | /*Y,bit20+*/
- 0x80 << (u + 10) |
- 0x80 << v);
- /* chroma formatter */
- RDMA_WR(AFBC_VD_CFMT_CTRL,
- (1<<21)|/* HFORMATTER_YC_RATIO_2_1 */
- (1<<20)|/* HFORMATTER_EN */
- (1<<16)|/* VFORMATTER_RPTLINE0_EN */
- (0x8 << 1)|/* VFORMATTER_PHASE_BIT */
- 1);/* VFORMATTER_EN */
-
- RDMA_WR(AFBC_VD_CFMT_W,
- (vf->width << 16) | (vf->width/2));
-
- RDMA_WR(AFBC_MIF_HOR_SCOPE,
- (0 << 16) | ((vf->width - 1)>>5));
-
- RDMA_WR(AFBC_PIXEL_HOR_SCOPE,
- (0 << 16) | (vf->width - 1));
- RDMA_WR(AFBC_VD_CFMT_H, vf->height);
-
- RDMA_WR(AFBC_MIF_VER_SCOPE,
- (0 << 16) | ((vf->height-1)>>2));
-
- RDMA_WR(AFBC_PIXEL_VER_SCOPE,
- 0 << 16 | (vf->height-1));
- RDMA_WR(AFBC_SIZE_IN, vf->height | vf->width << 16);
- RDMA_WR(AFBC_HEAD_BADDR, vf->canvas0Addr>>4);
- RDMA_WR(AFBC_BODY_BADDR, vf->canvas1Addr>>4);
- /* disable inp memory */
- RDMA_WR_BITS(DI_INP_GEN_REG, 0, 0, 1);
- /* afbc to di enable */
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- /* DI inp(current data) switch to AFBC */
- if (RDMA_RD_BITS(VIU_MISC_CTRL0, 29, 1) != 1)
- RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 29, 1);
- if (RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 1)
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
- if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 1)
- RDMA_WR_BITS(VIU_MISC_CTRL1, 1, 0, 1);
- if (RDMA_RD(VD2_AFBC_ENABLE) != 0x1600)
- RDMA_WR(VD2_AFBC_ENABLE, 0x1600);
- }
- } else {
- RDMA_WR(AFBC_ENABLE, 0);
- /* afbc to vpp(replace vd1) enable */
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 0 ||
- RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 0) {
- RDMA_WR_BITS(VIU_MISC_CTRL1, 0, 0, 1);
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- }
- }
- }
-}
-#endif
-
-#define AFBC_DEC_SEL (eAFBC_DEC1)
-
-u32 enable_afbc_input(struct vframe_s *vf)
-{
- unsigned int r, u, v, w_aligned, h_aligned;
- const unsigned int *reg = afbc_get_regbase();
- unsigned int vfmt_rpt_first = 1, vt_ini_phase = 0;
- unsigned int out_height = 0;
-
- if (!afbc_is_supported())
- return false;
-
- if (vf->type & VIDTYPE_COMPRESS) {
- /*only reg for the first time*/
- afbc_reg_sw(true);
- afbc_sw(true);
- } else {
- afbc_sw(false);
- return false;
- }
-
- w_aligned = round_up((vf->width), 32);
- /*if (di_pre_stru.cur_inp_type & VIDTYPE_INTERLACE)*/
- if ((vf->type & VIDTYPE_INTERLACE) &&
- (vf->type & VIDTYPE_VIU_422))
- h_aligned = round_up((vf->height/2), 4);/*from vdin and is i */
- else
- h_aligned = round_up((vf->height), 4);
-
- /*AFBCD working mode config*/
- r = (3 << 24) |
- (10 << 16) |
- (1 << 14) | /*burst1 1*/
- (vf->bitdepth & BITDEPTH_MASK);
-
- if (vf->bitdepth & BITDEPTH_SAVING_MODE)
- r |= (1<<28); /* mem_saving_mode */
- if (vf->type & VIDTYPE_SCATTER)
- r |= (1<<29);
-
- out_height = h_aligned;
- if (!(vf->type & VIDTYPE_VIU_422)) {
- /*from dec, process P as i*/
- if ((vf->type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP) {
- r |= 0x40;
- vt_ini_phase = 0xc;
- vfmt_rpt_first = 1;
- out_height = h_aligned>>1;
- } else if ((vf->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_BOTTOM) {
- r |= 0x80;
- vt_ini_phase = 0x4;
- vfmt_rpt_first = 0;
- out_height = h_aligned>>1;
- }
- }
- RDMA_WR(reg[eAFBC_MODE], r);
-
- r = 0x1600;
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
- /* un compress mode data from vdin bit block order is
- * different with from dos
- */
- if (!(vf->type & VIDTYPE_VIU_422))
- r |= (1 << 19); /* dos_uncomp */
-
- if (vf->type & VIDTYPE_COMB_MODE)
- r |= (1 << 20);
- }
- RDMA_WR(reg[eAFBC_ENABLE], r);
-
- /*pr_info("AFBC_ENABLE:0x%x\n", RDMA_RD(reg[eAFBC_ENABLE]));*/
-
- r = 0x100;
- /* TL1 add bit[13:12]: fmt_mode; 0:yuv444; 1:yuv422; 2:yuv420
- * di does not support yuv444, so for fmt yuv444 di will bypass+
- */
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
- if (vf->type & VIDTYPE_VIU_444)
- r |= (0 << 12);
- else if (vf->type & VIDTYPE_VIU_422)
- r |= (1 << 12);
- else
- r |= (2 << 12);
- }
- RDMA_WR(reg[eAFBC_CONV_CTRL], r);
-
- u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
- v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
- RDMA_WR(reg[eAFBC_DEC_DEF_COLOR],
- 0x3FF00000 | /*Y,bit20+*/
- 0x80 << (u + 10) |
- 0x80 << v);
-
- u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
- v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
- RDMA_WR(reg[eAFBC_DEC_DEF_COLOR],
- 0x3FF00000 | /*Y,bit20+*/
- 0x80 << (u + 10) |
- 0x80 << v);
-
- /* chroma formatter */
- RDMA_WR(reg[eAFBC_VD_CFMT_CTRL],
- (1 << 21) |/* HFORMATTER_YC_RATIO_2_1 */
- (1 << 20) |/* HFORMATTER_EN */
- (vfmt_rpt_first << 16) |/* VFORMATTER_RPTLINE0_EN */
- (vt_ini_phase << 8) |
- (16 << 1)|/* VFORMATTER_PHASE_BIT */
- 0);/* different with inp */
- #if 0
- if (((vf->width-1) != RDMA_RD(reg[eAFBC_PIXEL_HOR_SCOPE])) ||
- ((vf->height-1) != RDMA_RD(reg[eAFBC_PIXEL_VER_SCOPE]))) {
- pr_info("[afbc] in vf type=0x%x\n", vf->type);
- /*pr_info("cur_inp_type=0x%x\n", di_pre_stru.cur_inp_type);*/
- pr_info("[afbc] w_aligned=%d, h_aligned=%d\n",
- w_aligned, h_aligned);
- pr_info("[afbc] vfwidth=%d, vfheight=%d\n",
- vf->width, vf->height);
- pr_info("[afbc] out_height=%d\n", out_height);
- }
- #endif
- if (vf->type & VIDTYPE_VIU_444)
- RDMA_WR(reg[eAFBC_VD_CFMT_W],
- (w_aligned << 16) | (w_aligned/2));
- else
- RDMA_WR(reg[eAFBC_VD_CFMT_W],
- (w_aligned << 16) | (w_aligned));
-
- RDMA_WR(reg[eAFBC_MIF_HOR_SCOPE],
- (0 << 16) | ((w_aligned>>5)-1));
- RDMA_WR(reg[eAFBC_MIF_VER_SCOPE],
- (0 << 16) | ((h_aligned>>2)-1));
-
- RDMA_WR(reg[eAFBC_PIXEL_HOR_SCOPE],
- (0 << 16) | (vf->width-1));
- RDMA_WR(reg[eAFBC_PIXEL_VER_SCOPE],
- 0 << 16 | (vf->height-1));
-
- RDMA_WR(reg[eAFBC_VD_CFMT_H], out_height);
-
- RDMA_WR(reg[eAFBC_SIZE_IN], (vf->height) | w_aligned << 16);
- RDMA_WR(reg[eAFBC_SIZE_OUT], out_height | w_aligned << 16);
-
- RDMA_WR(reg[eAFBC_HEAD_BADDR], vf->compHeadAddr>>4);
- RDMA_WR(reg[eAFBC_BODY_BADDR], vf->compBodyAddr>>4);
-
- return true;
-}
-#if 0
-static void afbcx_power_sw(enum eAFBC_DEC decsel, bool on) /*g12a*/
-{
- unsigned int reg_ctrl;
-
- if (decsel == eAFBC_DEC0)
- reg_ctrl = VD1_AFBCD0_MISC_CTRL;
- else
- reg_ctrl = VD2_AFBCD1_MISC_CTRL;
- if (on)
- RDMA_WR_BITS(reg_ctrl, 0, 0, 8);
- else
- RDMA_WR_BITS(reg_ctrl, 0x55, 0, 8);
-
-}
-#endif
-static void afbcx_sw(bool on) /*g12a*/
-{
- unsigned int tmp;
- unsigned int mask;
- unsigned int reg_ctrl, reg_en;
- enum eAFBC_DEC dec_sel;
- const unsigned int *reg = afbc_get_regbase();
-
- dec_sel = afbc_get_decnub();
-
- if (dec_sel == eAFBC_DEC0) {
- reg_ctrl = VD1_AFBCD0_MISC_CTRL;
- } else {
- reg_ctrl = VD2_AFBCD1_MISC_CTRL;
- }
- reg_en = reg[eAFBC_ENABLE];
-
- mask = (3<<20) | (1<<12) | (1<<9);
- /*clear*/
- tmp = RDMA_RD(reg_ctrl)&(~mask);
-
- if (on) {
- tmp = tmp
- /*0:go_file 1:go_filed_pre*/
- | (2<<20)
- /*0:afbc0 mif to axi 1:vd1 mif to axi*/
- | (1<<12)
- /*0:afbc0 to vpp 1:afbc0 to di*/
- | (1<<9);
- RDMA_WR(reg_ctrl, tmp);
- /*0:vd1 to di 1:vd2 to di */
- RDMA_WR_BITS(VD2_AFBCD1_MISC_CTRL,
- (reg_ctrl == VD1_AFBCD0_MISC_CTRL)?0:1, 8, 1);
- /*RDMA_WR(reg_en, 0x1600);*/
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
- /*TL1 add mem control bit */
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 1, 22, 1);
- } else {
- RDMA_WR(reg_ctrl, tmp);
- RDMA_WR(reg_en, 0x1600);
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 0, 22, 1);
- }
-}
-static void afbc_sw_old(bool on)/*txlx*/
-{
- enum eAFBC_DEC dec_sel;
- unsigned int reg_en;
- const unsigned int *reg = afbc_get_regbase();
-
- dec_sel = afbc_get_decnub();
- reg_en = reg[eAFBC_ENABLE];
-
- if (on) {
- /* DI inp(current data) switch to AFBC */
- if (RDMA_RD_BITS(VIU_MISC_CTRL0, 29, 1) != 1)
- RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 29, 1);
- if (RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 1)
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
- if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 1)
- RDMA_WR_BITS(VIU_MISC_CTRL1, 1, 0, 1);
- if (dec_sel == eAFBC_DEC0) {
- /*gxl only?*/
- if (RDMA_RD_BITS(VIU_MISC_CTRL0, 19, 1) != 1)
- RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 19, 1);
- }
- if (RDMA_RD(reg_en) != 0x1600)
- RDMA_WR(reg_en, 0x1600);
-
- } else {
- RDMA_WR(reg_en, 0);
- /* afbc to vpp(replace vd1) enable */
- if (RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 0 ||
- RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 0) {
- RDMA_WR_BITS(VIU_MISC_CTRL1, 0, 0, 1);
- RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- }
- }
-}
-static bool afbc_is_used(void)
-{
- bool ret = false;
-
- if (RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) == 1)
- ret = true;
-
- return ret;
-}
-static void afbc_power_sw(bool on)
-{
- /*afbc*/
- enum eAFBC_DEC dec_sel;
- unsigned int vpu_sel;
- unsigned int reg_ctrl;
-
- dec_sel = afbc_get_decnub();
- if (dec_sel == eAFBC_DEC0)
- vpu_sel = VPU_AFBC_DEC;
- else
- vpu_sel = VPU_AFBC_DEC1;
-
- switch_vpu_mem_pd_vmod(vpu_sel,
- on?VPU_MEM_POWER_ON:VPU_MEM_POWER_DOWN);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (dec_sel == eAFBC_DEC0)
- reg_ctrl = VD1_AFBCD0_MISC_CTRL;
- else
- reg_ctrl = VD2_AFBCD1_MISC_CTRL;
- if (on)
- RDMA_WR_BITS(reg_ctrl, 0, 0, 8);
- else
- RDMA_WR_BITS(reg_ctrl, 0x55, 0, 8);
- }
- /*afbcx_power_sw(dec_sel, on);*/
-}
-
-int afbc_reg_unreg_flag;
-void afbc_sw(bool on)
-{
- if (is_meson_gxl_cpu() || is_meson_txlx_cpu())
- afbc_sw_old(on);
- else
- afbcx_sw(on);
-}
-
-void afbc_reg_sw(bool on)
-{
- if (!afbc_is_supported())
- return;
-
- if (on && (!afbc_reg_unreg_flag)) {
- afbc_power_sw(true);
- afbc_reg_unreg_flag = 1;
- }
- if ((!on) && afbc_reg_unreg_flag) {
- afbc_sw(false);
- afbc_power_sw(false);
- afbc_reg_unreg_flag = 0;
- }
-}
-
-bool afbc_is_free(void)
-{
- bool sts = 0;
- u32 afbc_num = afbc_get_decnub();
-
- if (afbc_num == eAFBC_DEC0)
- sts = RDMA_RD_BITS(VD1_AFBCD0_MISC_CTRL, 8, 2);
- else
- sts = RDMA_RD_BITS(VD2_AFBCD1_MISC_CTRL, 8, 2);
-
- if (sts)
- return true;
- else
- return false;
-
- return sts;
-}
-
-#if 0
-void afbc_sw_trig(bool on)
-{
- afbc_sw(on);
-}
-#endif
-void afbc_input_sw(bool on)
-{
- const unsigned int *reg = afbc_get_regbase();
- unsigned int reg_AFBC_ENABLE;
-
- if (!afbc_is_supported())
- return;
-
- reg_AFBC_ENABLE = reg[eAFBC_ENABLE];
-
- //di_print("%s:0x%x\n", __func__,reg_AFBC_ENABLE);
- if (on)
- RDMA_WR_BITS(reg_AFBC_ENABLE, 1, 8, 1);
- else
- RDMA_WR_BITS(reg_AFBC_ENABLE, 0, 8, 1);
-
-}
-
void enable_mc_di_pre_g12(struct DI_MC_MIF_s *mcinford_mif,
struct DI_MC_MIF_s *mcinfowr_mif,
struct DI_MC_MIF_s *mcvecwr_mif,
void di_patch_post_update_mc_sw(unsigned int cmd, bool on)
{
- unsigned int l_flg = di_mc_update;
+// unsigned int l_flg = di_mc_update;
switch (cmd) {
case DI_MC_SW_IC:
break;
}
- if (l_flg != di_mc_update)
- pr_debug("%s:0x%x->0x%x\n", __func__, l_flg, di_mc_update);
+ //if (l_flg != di_mc_update)
+ // pr_debug("%s:0x%x->0x%x\n", __func__, l_flg, di_mc_update);
}
void initial_di_post_2(int hsize_post, int vsize_post,
enable?VPU_MEM_POWER_ON:VPU_MEM_POWER_DOWN);
}
-void diwr_set_power_control_pst(unsigned char enable)
-{
- switch_vpu_mem_pd_vmod(VPU_DI_POST,
- enable ? VPU_MEM_POWER_ON : VPU_MEM_POWER_DOWN);
-}
-
void di_hdr2_hist_init(void)
{
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TM2)) {
RDMA_WR_BITS(VD2_AFBC_ENABLE, 0, 8, 1);
}
#else
- if (afbc_is_used()) {
+ if (di_afds() && di_afds()->is_used()) {
DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
- afbc_input_sw(true);
+ //afbc_input_sw(true);
+ if (di_afds())
+ di_afds()->inp_sw(true);
} else {
DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) | 0x1);
/*afbc_input_sw(false);*/
+ if (di_afds())
+ di_afds()->inp_sw(false);
}
#endif
/* nrwr no clk gate en=0 */
char *info;
};
-#ifdef MARK_SC2
-struct reg_acc {
- void (*wr)(unsigned int adr, unsigned int val);
- unsigned int (*rd)(unsigned int adr);
- unsigned int (*bwr)(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len);
- unsigned int (*brd)(unsigned int adr, unsigned int start,
- unsigned int len);
-
-};
-#endif
-
-static unsigned int get_reg_bits(unsigned int val, unsigned int bstart,
- unsigned int bw)
+unsigned int get_reg_bits(unsigned int val, unsigned int bstart,
+ unsigned int bw)
{
//unsigned int valori;
#define SKIP_CTRE_NUM 13
-enum eAFBC_REG {
- eAFBC_ENABLE, /*0x1ae0*/
- eAFBC_MODE, /*0x1ae1*/
- eAFBC_SIZE_IN, /*0x1ae2*/
- eAFBC_DEC_DEF_COLOR, /*0x1ae3*/
- eAFBC_CONV_CTRL, /*0x1ae4*/
- eAFBC_LBUF_DEPTH, /*0x1ae5*/
- eAFBC_HEAD_BADDR, /*0x1ae6*/
- eAFBC_BODY_BADDR, /*0x1ae7*/
- eAFBC_SIZE_OUT, /*0x1ae8*/
- eAFBC_OUT_YSCOPE, /*0x1ae9*/
- eAFBC_STAT, /*0x1aea*/
- eAFBC_VD_CFMT_CTRL, /*0x1aeb*/
- eAFBC_VD_CFMT_W, /*0x1aec*/
- eAFBC_MIF_HOR_SCOPE, /*0x1aed*/
- eAFBC_MIF_VER_SCOPE, /*0x1aee*/
- eAFBC_PIXEL_HOR_SCOPE, /*0x1aef*/
- eAFBC_PIXEL_VER_SCOPE, /*0x1af0*/
- eAFBC_VD_CFMT_H, /*0x1af1*/
-};
-
-enum eAFBC_DEC {
- eAFBC_DEC0,
- eAFBC_DEC1,
-};
-#define AFBC_REG_INDEX_NUB (18)
-#define AFBC_DEC_NUB (2)
-
struct DI_MIF_s {
unsigned short luma_x_start0;
unsigned short luma_x_end0;
struct DI_SIM_MIF_s *di_contwr_mif,
unsigned char madi_en, unsigned char pre_field_num,
unsigned char pre_vdin_link);
-u32 enable_afbc_input(struct vframe_s *vf);
void mc_pre_mv_irq(void);
void enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
void di_pre_gate_control(bool enable, bool mc_enable);
void di_post_gate_control(bool gate);
void diwr_set_power_control(unsigned char enable);
-void diwr_set_power_control_pst(unsigned char enable);
void di_hw_disable(bool mc_enable);
void enable_di_pre_mif(bool enable, bool mc_enable);
void enable_di_post_mif(enum gate_mode_e mode);
unsigned char det3d_en, unsigned char nrds_en,
unsigned char post_wr, unsigned char mc_en);
void di_txl_patch_prog(int prog_flg, unsigned int cnt, bool mc_en);
-bool afbc_is_supported(void);
//extern void afbc_power_sw(bool on);
-extern void afbc_reg_sw(bool on);
/*extern void afbc_sw_trig(bool on);*/
-extern void afbc_sw(bool on);
-extern void afbc_input_sw(bool on);
extern void dump_vd2_afbc(void);
-extern int afbc_reg_unreg_flag;
extern u8 *di_vmap(ulong addr, u32 size, bool *bflg);
extern void di_unmap_phyaddr(u8 *vaddr);
extern void di_patch_post_update_mc(void);
extern void di_patch_post_update_mc_sw(unsigned int cmd, bool on);
+#ifdef MARK_SC2
+struct reg_acc {
+ void (*wr)(unsigned int adr, unsigned int val);
+ unsigned int (*rd)(unsigned int adr);
+ unsigned int (*bwr)(unsigned int adr, unsigned int val,
+ unsigned int start, unsigned int len);
+ unsigned int (*brd)(unsigned int adr, unsigned int start,
+ unsigned int len);
+
+};
+#endif
extern void di_rst_protect(bool on);
extern void di_pre_nr_wr_done_sel(bool on);
extern void di_arb_sw(bool on);
-extern bool afbc_is_free(void);
extern enum eAFBC_DEC afbc_get_decnub(void);
/*also see: dbg_mode_name*/
};
+unsigned int get_reg_bits(unsigned int val, unsigned int bstart,
+ unsigned int bw);
+
extern void ddbg_mod_save(unsigned int mod, unsigned int ch, unsigned int cnt);
#endif
#include <linux/amlogic/iomap.h>
#include "register.h"
#include "deinterlace_mtn.h"
+#include "deinterlace.h"
#include "di_pqa.h"
#define MAX_NUM_DI_REG 32
}
void mtn_int_combing_glbmot(void)
{
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {/*from VLSI yanling.liu*/
+ if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {/*from VLSI yanling.liu*/
combing_glbmot_radprat[0] = 30;
}
di_mtn_p_mode = 0;
if (
is_meson_txhd_cpu() ||
is_meson_tl1_cpu() ||
- is_meson_tm2_cpu()) {
+ is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
if (
glb_mot[0] < combing_diff_min &&
glb_mot[1] > combing_diff_max &&
DEFINE_DI_EVENT(di_pre);
DEFINE_DI_EVENT(di_post);
+DEFINE_DI_EVENT(di_pre_cnt0);
+DEFINE_DI_EVENT(di_pre_cnt1);
+DEFINE_DI_EVENT(di_pos_cnt0);
+DEFINE_DI_EVENT(di_pos_cnt1);
+DEFINE_DI_EVENT(di_pre_getxx);
+DEFINE_DI_EVENT(di_pre_setxx);
+DEFINE_DI_EVENT(di_pre_ready);
+DEFINE_DI_EVENT(di_pst_ready);
+DEFINE_DI_EVENT(di_pst_getxx);
+DEFINE_DI_EVENT(di_pst_setxx);
+DEFINE_DI_EVENT(di_pst_irxxx);
+DEFINE_DI_EVENT(di_pst_doing);
+DEFINE_DI_EVENT(di_pst_peekx);
+DEFINE_DI_EVENT(di_pst_get2x);
#endif /* _VDEC_TRACE_H */
#if 0
--- /dev/null
+/*
+ * drivers/amlogic/media/deinterlace/di_afbc.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/semaphore.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/major.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+#include <linux/proc_fs.h>
+#include <linux/list.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/of_irq.h>
+#include <linux/uaccess.h>
+#include <linux/of_fdt.h>
+#include <linux/cma.h>
+#include <linux/dma-contiguous.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/of_device.h>
+
+#include <linux/amlogic/media/vfm/vframe.h>
+
+/*dma_get_cma_size_int_byte*/
+#include <linux/amlogic/media/codec_mm/codec_mm.h>
+
+#include "deinterlace_dbg.h"
+#include "deinterlace.h"
+
+#include "register.h"
+#include "nr_downscale.h"
+#include "deinterlace_hw.h"
+#include "register_nr4.h"
+#include "di_afbc.h"
+
+#include <linux/amlogic/media/vpu/vpu.h>
+#if 1
+#define DI_BIT0 0x00000001
+#define DI_BIT1 0x00000002
+#define DI_BIT2 0x00000004
+#define DI_BIT3 0x00000008
+#define DI_BIT4 0x00000010
+#define DI_BIT5 0x00000020
+#define DI_BIT6 0x00000040
+#define DI_BIT7 0x00000080
+
+static unsigned int reg_rd(unsigned int addr)
+{
+ return aml_read_vcbus(addr);
+}
+
+static unsigned int reg_rdb(unsigned int adr, unsigned int start,
+ unsigned int len)
+{
+ return Rd_reg_bits(adr, start, len);
+}
+
+static void reg_wr(unsigned int addr, unsigned int val)
+{
+ Wr(addr, val);
+}
+
+static unsigned int reg_wrb(unsigned int adr, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ Wr_reg_bits(adr, val, start, len);
+ return 1;
+}
+
+const struct reg_acc di_normal_regset = {
+ .wr = reg_wr,
+ .rd = reg_rd,
+ .bwr = reg_wrb,
+ .brd = reg_rdb,
+};
+
+/*tmp*/
+/*static struct afd_s di_afd;*/
+/************************************
+ * bit[0]: on/off
+ * bit[1]: p -> need proce p use 2 i buf
+ * bit[2]: mode
+ ************************************/
+static u32 afbc_cfg;
+
+module_param_named(afbc_cfg, afbc_cfg, uint, 0664);
+
+#ifdef DBG_AFBC
+static u32 afbc_cfg_vf;
+module_param_named(afbc_cfg_vf, afbc_cfg_vf, uint, 0664);
+static u32 afbc_cfg_bt;
+module_param_named(afbc_cfg_bt, afbc_cfg_bt, uint, 0664);
+#endif
+/************************************************
+ * [0]: enable afbc
+ * [1]: p use 2 ibuf mode
+ * [2]: 2afbcd + 1afbce mode ([1] must 1)
+ * [3]: 2afbcd + 1afbce test mode (mem use inp vf)
+ * [4]: 4k test mode; i need bypass;
+ * [5]: pre_link mode
+ * [6]: stop when first frame display
+ * [7]: change level always 3
+ ***********************************************/
+
+static bool is_cfg(enum EAFBCV1_CFG cfg_cmd)
+{
+ bool ret;
+
+ ret = false;
+ switch (cfg_cmd) {
+ case EAFBCV1_CFG_EN:
+ if (afbc_cfg & DI_BIT0)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_PMODE:
+ if (afbc_cfg & DI_BIT1)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_EMODE:
+ if ((afbc_cfg & DI_BIT2) &&
+ (afbc_cfg & DI_BIT1))
+ ret = true;
+ break;
+ case EAFBCV1_CFG_ETEST:
+ if (afbc_cfg & DI_BIT3)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_4K:
+ if (afbc_cfg & DI_BIT4)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_PRE_LINK:
+ if (afbc_cfg & DI_BIT5)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_PAUSE:
+ if (afbc_cfg & DI_BIT6)
+ ret = true;
+ break;
+ case EAFBCV1_CFG_LEVE3:
+ if (afbc_cfg & DI_BIT7)
+ ret = true;
+ break;
+ }
+ return ret;
+}
+
+bool prelink_status;
+
+bool dbg_di_prelink(void)
+{
+ if (is_cfg(EAFBCV1_CFG_PRE_LINK))
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL(dbg_di_prelink);
+
+void dbg_di_prelink_reg_check(void)
+{
+ unsigned int val;
+
+ if (!prelink_status && is_cfg(EAFBCV1_CFG_PRE_LINK)) {
+ /* set on*/
+ reg_wrb(DI_AFBCE_CTRL, 1, 3, 1);
+ reg_wr(VD1_AFBCD0_MISC_CTRL, 0x100100);
+ prelink_status = true;
+ } else if (prelink_status && !is_cfg(EAFBCV1_CFG_PRE_LINK)) {
+ /* set off */
+ reg_wrb(DI_AFBCE_CTRL, 0, 3, 1);
+ prelink_status = false;
+ }
+
+ if (!is_cfg(EAFBCV1_CFG_PRE_LINK))
+ return;
+
+ val = reg_rd(VD1_AFBCD0_MISC_CTRL);
+ if (val != 0x100100) {
+ di_pr_info("%s:change 0x%x\n", __func__, val);
+ reg_wr(VD1_AFBCD0_MISC_CTRL, 0x100100);
+ }
+}
+
+#ifdef HIS_CODE
+static struct afbcdv1_ctr_s *div1_get_afd_ctr(void)
+{
+ return &di_afd.ctr;
+}
+#endif
+
+static const unsigned int reg_AFBC[AFBC_DEC_NUB][AFBC_REG_INDEX_NUB] = {
+ {
+ AFBC_ENABLE,
+ AFBC_MODE,
+ AFBC_SIZE_IN,
+ AFBC_DEC_DEF_COLOR,
+ AFBC_CONV_CTRL,
+ AFBC_LBUF_DEPTH,
+ AFBC_HEAD_BADDR,
+ AFBC_BODY_BADDR,
+ AFBC_SIZE_OUT,
+ AFBC_OUT_YSCOPE,
+ AFBC_STAT,
+ AFBC_VD_CFMT_CTRL,
+ AFBC_VD_CFMT_W,
+ AFBC_MIF_HOR_SCOPE,
+ AFBC_MIF_VER_SCOPE,
+ AFBC_PIXEL_HOR_SCOPE,
+ AFBC_PIXEL_VER_SCOPE,
+ AFBC_VD_CFMT_H,
+ },
+ {
+ VD2_AFBC_ENABLE,
+ VD2_AFBC_MODE,
+ VD2_AFBC_SIZE_IN,
+ VD2_AFBC_DEC_DEF_COLOR,
+ VD2_AFBC_CONV_CTRL,
+ VD2_AFBC_LBUF_DEPTH,
+ VD2_AFBC_HEAD_BADDR,
+ VD2_AFBC_BODY_BADDR,
+ VD2_AFBC_OUT_XSCOPE,
+ VD2_AFBC_OUT_YSCOPE,
+ VD2_AFBC_STAT,
+ VD2_AFBC_VD_CFMT_CTRL,
+ VD2_AFBC_VD_CFMT_W,
+ VD2_AFBC_MIF_HOR_SCOPE,
+ VD2_AFBC_MIF_VER_SCOPE,
+ VD2_AFBC_PIXEL_HOR_SCOPE,
+ VD2_AFBC_PIXEL_VER_SCOPE,
+ VD2_AFBC_VD_CFMT_H,
+
+ },
+ {
+ DI_INP_AFBC_ENABLE,
+ DI_INP_AFBC_MODE,
+ DI_INP_AFBC_SIZE_IN,
+ DI_INP_AFBC_DEC_DEF_COLOR,
+ DI_INP_AFBC_CONV_CTRL,
+ DI_INP_AFBC_LBUF_DEPTH,
+ DI_INP_AFBC_HEAD_BADDR,
+ DI_INP_AFBC_BODY_BADDR,
+ DI_INP_AFBC_SIZE_OUT,
+ DI_INP_AFBC_OUT_YSCOPE,
+ DI_INP_AFBC_STAT,
+ DI_INP_AFBC_VD_CFMT_CTRL,
+ DI_INP_AFBC_VD_CFMT_W,
+ DI_INP_AFBC_MIF_HOR_SCOPE,
+ DI_INP_AFBC_MIF_VER_SCOPE,
+ DI_INP_AFBC_PIXEL_HOR_SCOPE,
+ DI_INP_AFBC_PIXEL_VER_SCOPE,
+ DI_INP_AFBC_VD_CFMT_H,
+
+ },
+ {
+ DI_MEM_AFBC_ENABLE,
+ DI_MEM_AFBC_MODE,
+ DI_MEM_AFBC_SIZE_IN,
+ DI_MEM_AFBC_DEC_DEF_COLOR,
+ DI_MEM_AFBC_CONV_CTRL,
+ DI_MEM_AFBC_LBUF_DEPTH,
+ DI_MEM_AFBC_HEAD_BADDR,
+ DI_MEM_AFBC_BODY_BADDR,
+ DI_MEM_AFBC_SIZE_OUT,
+ DI_MEM_AFBC_OUT_YSCOPE,
+ DI_MEM_AFBC_STAT,
+ DI_MEM_AFBC_VD_CFMT_CTRL,
+ DI_MEM_AFBC_VD_CFMT_W,
+ DI_MEM_AFBC_MIF_HOR_SCOPE,
+ DI_MEM_AFBC_MIF_VER_SCOPE,
+ DI_MEM_AFBC_PIXEL_HOR_SCOPE,
+ DI_MEM_AFBC_PIXEL_VER_SCOPE,
+ DI_MEM_AFBC_VD_CFMT_H,
+ },
+
+};
+
+/*keep order with struct afbce_bits_s*/
+static const unsigned int reg_afbc_e[AFBC_ENC_NUB][DIM_AFBCE_NUB] = {
+ {
+ DI_AFBCE_ENABLE, /* 0 */
+ DI_AFBCE_MODE, /* 1 */
+ DI_AFBCE_SIZE_IN, /* 2 */
+ DI_AFBCE_BLK_SIZE_IN, /* 3 */
+ DI_AFBCE_HEAD_BADDR, /* 4 */
+
+ DI_AFBCE_MIF_SIZE, /* 5 */
+ DI_AFBCE_PIXEL_IN_HOR_SCOPE, /* 6 */
+ DI_AFBCE_PIXEL_IN_VER_SCOPE, /* 7 */
+ DI_AFBCE_CONV_CTRL, /* 8 */
+ DI_AFBCE_MIF_HOR_SCOPE, /* 9 */
+ DI_AFBCE_MIF_VER_SCOPE, /* 10 */
+ /**/
+ DI_AFBCE_FORMAT, /* 11 */
+ /**/
+ DI_AFBCE_DEFCOLOR_1, /* 12 */
+ DI_AFBCE_DEFCOLOR_2, /* 13 */
+ DI_AFBCE_QUANT_ENABLE, /* 14 */
+ //unsigned int mmu_num,
+ DI_AFBCE_MMU_RMIF_CTRL1, /* 15 */
+ DI_AFBCE_MMU_RMIF_CTRL2, /* 16 */
+ DI_AFBCE_MMU_RMIF_CTRL3, /* 17 */
+ DI_AFBCE_MMU_RMIF_CTRL4, /* 18 */
+ DI_AFBCE_MMU_RMIF_SCOPE_X, /* 19 */
+ DI_AFBCE_MMU_RMIF_SCOPE_Y, /* 20 */
+
+ /**********************/
+ DI_AFBCE_MODE_EN,
+ DI_AFBCE_DWSCALAR,
+ DI_AFBCE_IQUANT_LUT_1,
+ DI_AFBCE_IQUANT_LUT_2,
+ DI_AFBCE_IQUANT_LUT_3,
+ DI_AFBCE_IQUANT_LUT_4,
+ DI_AFBCE_RQUANT_LUT_1,
+ DI_AFBCE_RQUANT_LUT_2,
+ DI_AFBCE_RQUANT_LUT_3,
+ DI_AFBCE_RQUANT_LUT_4,
+ DI_AFBCE_YUV_FORMAT_CONV_MODE,
+ DI_AFBCE_DUMMY_DATA,
+ DI_AFBCE_CLR_FLAG,
+ DI_AFBCE_STA_FLAGT,
+ DI_AFBCE_MMU_NUM,
+ DI_AFBCE_STAT1, /*read only*/
+ DI_AFBCE_STAT2,
+ DI_AFBCE_MMU_RMIF_RO_STAT,
+ },
+};
+
+static const unsigned int *afbc_get_addrp(enum EAFBC_DEC eidx)
+{
+ return ®_AFBC[eidx][0];
+}
+
+static const unsigned int *afbce_get_addrp(enum EAFBC_ENC eidx)
+{
+ return ®_afbc_e[eidx][0];
+}
+
+static void dump_afbcd_reg(void)
+{
+ u32 i;
+ u32 afbc_reg;
+
+ pr_info("---- dump afbc EAFBC_DEC0 reg -----\n");
+ for (i = 0; i < AFBC_REG_INDEX_NUB; i++) {
+ afbc_reg = reg_AFBC[EAFBC_DEC0][i];
+ pr_info("reg 0x%x val:0x%x\n", afbc_reg, reg_rd(afbc_reg));
+ }
+ pr_info("---- dump afbc EAFBC_DEC1 reg -----\n");
+ for (i = 0; i < AFBC_REG_INDEX_NUB; i++) {
+ afbc_reg = reg_AFBC[EAFBC_DEC1][i];
+ pr_info("reg 0x%x val:0x%x\n", afbc_reg, reg_rd(afbc_reg));
+ }
+ pr_info("reg 0x%x val:0x%x\n",
+ VD1_AFBCD0_MISC_CTRL, reg_rd(VD1_AFBCD0_MISC_CTRL));
+ pr_info("reg 0x%x val:0x%x\n",
+ VD2_AFBCD1_MISC_CTRL, reg_rd(VD2_AFBCD1_MISC_CTRL));
+}
+
+int dbg_afbc_cfg_show(struct seq_file *s, void *v)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr)
+ return 0;
+
+ seq_printf(s, "%10s:%d\n", "version", pafd_ctr->fb.ver);
+ seq_printf(s, "%10s:inp[%d],mem[%d]\n", "support",
+ pafd_ctr->fb.sp_inp,
+ pafd_ctr->fb.sp_mem);
+ seq_printf(s, "%10s:%d\n", "mode", pafd_ctr->fb.mode);
+ seq_printf(s, "%10s:inp[%d],mem[%d]\n", "dec",
+ pafd_ctr->fb.pre_dec,
+ pafd_ctr->fb.mem_dec);
+
+ seq_printf(s, "%10s:%d\n", "int_flg", pafd_ctr->b.int_flg);
+ seq_printf(s, "%10s:%d\n", "en", pafd_ctr->b.en);
+ seq_printf(s, "%10s:%d\n", "level", pafd_ctr->b.chg_level);
+ return 0;
+}
+EXPORT_SYMBOL(dbg_afbc_cfg_show);
+
+static u32 di_requeset_afbc(bool onoff)
+{
+ u32 afbc_busy;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr || pafd_ctr->fb.ver >= AFBCD_V4) {
+ afbc_busy = 0;
+ return afbc_busy;
+ }
+
+ if (onoff)
+ afbc_busy = di_request_afbc_hw(pafd_ctr->fb.pre_dec, true);
+ else
+ afbc_busy = di_request_afbc_hw(pafd_ctr->fb.pre_dec, false);
+
+ di_pr_info("%s:busy:%d\n", __func__, afbc_busy);
+ return afbc_busy;
+}
+
+static u32 dbg_requeset_afbc(bool onoff)
+{
+ u32 afbc_busy;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr)
+ return 0;
+ if (onoff)
+ afbc_busy = di_request_afbc_hw(pafd_ctr->fb.pre_dec, true);
+ else
+ afbc_busy = di_request_afbc_hw(pafd_ctr->fb.pre_dec, false);
+
+ return afbc_busy;
+}
+
+static const unsigned int *afbc_get_inp_base(void)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr)
+ return NULL;
+ return ®_AFBC[pafd_ctr->fb.pre_dec][0];
+}
+
+static bool afbc_is_supported(void)
+{
+ bool ret = false;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr || !is_cfg(EAFBCV1_CFG_EN))
+ return false;
+
+ if (pafd_ctr->fb.ver != AFBCD_NONE)
+ ret = true;
+
+ return ret;
+}
+
+static void afbc_prob(unsigned int cid)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ afbc_cfg = 0;
+ if (!pafd_ctr) {
+ pr_error("%s:no data\n", __func__);
+ return;
+ }
+
+ if (IS_IC_EF(cid, TM2B)) {
+ pafd_ctr->fb.ver = AFBCD_V4;
+ pafd_ctr->fb.sp_inp = 1;
+ pafd_ctr->fb.sp_mem = 1;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC2_DI;
+ pafd_ctr->fb.mem_dec = EAFBC_DEC3_MEM;
+ pafd_ctr->fb.mode = 1;
+ afbc_cfg = 0x1;
+ } else if (IS_IC_EF(cid, TL1)) {
+ pafd_ctr->fb.ver = AFBCD_V3;
+ pafd_ctr->fb.sp_inp = 1;
+ pafd_ctr->fb.sp_mem = 0;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC0;
+ pafd_ctr->fb.mode = 0;
+ } else if (IS_IC_EF(cid, G12A)) {
+ pafd_ctr->fb.ver = AFBCD_V2;
+ pafd_ctr->fb.sp_inp = 1;
+ pafd_ctr->fb.sp_mem = 0;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC1;
+ pafd_ctr->fb.mode = 0;
+ } else if (IS_IC_EF(cid, GXL)) {
+ pafd_ctr->fb.ver = AFBCD_V1;
+ pafd_ctr->fb.sp_inp = 1;
+ pafd_ctr->fb.sp_mem = 0;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC0;
+ pafd_ctr->fb.mode = 0;
+ } else {
+ pafd_ctr->fb.ver = AFBCD_NONE;
+ pafd_ctr->fb.sp_inp = 0;
+ pafd_ctr->fb.sp_mem = 0;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC0;
+ pafd_ctr->fb.mode = 0;
+ }
+}
+
+/*
+ * after g12a, framereset will not reset simple
+ * wr mif of pre such as mtn&cont&mv&mcinfo wr
+ */
+
+static void afbc_reg_sw(bool on);
+
+//unsigned int test_afbc_en;
+static void afbc_sw(bool on);
+#define AFBCP (1)
+static void afbc_check_chg_level(struct vframe_s *vf,
+ struct vframe_s *mem_vf,
+ struct afbcdv1_ctr_s *pctr)
+{
+#ifdef AFBCP
+ struct di_buf_s *di_buf = NULL;
+#endif
+ /*check support*/
+ if (pctr->fb.ver == AFBCD_NONE)
+ return;
+
+ if (!(vf->type & VIDTYPE_COMPRESS)) {
+ if (pctr->b.en) {
+ /*from en to disable*/
+ pctr->b.en = 0;
+ }
+
+ return;
+ }
+ /* pach for not mask nv21 */
+ if ((vf->type & AFBC_VTYPE_MASK_CHG) !=
+ (pctr->l_vtype & AFBC_VTYPE_MASK_CHG) ||
+ vf->height != pctr->l_h ||
+ vf->width != pctr->l_w ||
+ vf->bitdepth != pctr->l_bitdepth) {
+ pctr->b.chg_level = 3;
+ pctr->l_vtype = (vf->type & AFBC_VTYPE_MASK_SAV);
+ pctr->l_h = vf->height;
+ pctr->l_w = vf->width;
+ pctr->l_bitdepth = vf->bitdepth;
+ } else {
+ if (vf->type & VIDTYPE_INTERLACE) {
+ pctr->b.chg_level = 2;
+ pctr->l_vtype = (vf->type & AFBC_VTYPE_MASK_SAV);
+ } else {
+ pctr->b.chg_level = 1;
+ }
+ }
+ if (is_cfg(EAFBCV1_CFG_LEVE3))
+ pctr->b.chg_level = 3;
+#ifdef AFBCP
+ /* mem */
+ if (pctr->fb.mode == 1) {
+ if ((mem_vf->type & AFBC_VTYPE_MASK_CHG) !=
+ (pctr->l_vt_mem & AFBC_VTYPE_MASK_CHG)) {
+ pctr->b.chg_mem = 3;
+ pctr->l_vt_mem = mem_vf->type;
+ } else {
+ pctr->b.chg_mem = 1;
+ }
+ di_buf = (struct di_buf_s *)mem_vf->private_data;
+ if (di_buf && (di_buf->type == VFRAME_TYPE_LOCAL)) {
+ #ifdef AFBC_MODE1
+ di_print("buf t[%d]:nr_adr[0x%lx], afbc_adr[0x%lx]\n",
+ di_buf->index,
+ di_buf->nr_adr,
+ di_buf->afbc_adr);
+ #endif
+ //mem_vf->compBodyAddr = di_buf->nr_adr;
+ //mem_vf->compHeadAddr = di_buf->afbc_adr;
+ }
+ }
+#endif
+ pctr->addr_h = vf->compHeadAddr;
+ pctr->addr_b = vf->compBodyAddr;
+ di_print("%s:vtype[0x%x],[0x%x],[0x%x]\n", __func__, pctr->l_vtype,
+ vf->type,
+ AFBC_VTYPE_MASK_SAV);
+#ifdef AFBCP
+ di_print("\t:mem_vtype[0x%x],[0x%x]\n", pctr->l_vt_mem,
+ mem_vf->type);
+ di_print("\t:inp:addr body[0x%x] inf[0x%x]\n",
+ vf->compBodyAddr, vf->compHeadAddr);
+
+ di_print("\t:mem:addr body[0x%x] inf[0x%x]\n",
+ mem_vf->compBodyAddr, mem_vf->compHeadAddr);
+#endif
+ di_print("\th[%d],w[%d],b[0x%x]\n", pctr->l_h,
+ pctr->l_w, pctr->l_bitdepth);
+ di_print("\tchg_level[%d] chg_mem[%d]\n",
+ pctr->b.chg_level, pctr->l_vt_mem);
+}
+
+static void afbc_update_level1(struct vframe_s *vf, enum EAFBC_DEC dec)
+{
+ const unsigned int *reg = afbc_get_addrp(dec);
+
+ reg_wr(reg[EAFBC_HEAD_BADDR], vf->compHeadAddr >> 4);
+ reg_wr(reg[EAFBC_BODY_BADDR], vf->compBodyAddr >> 4);
+}
+
+static u32 enable_afbc_input_local(struct vframe_s *vf, enum EAFBC_DEC dec)
+{
+ unsigned int r, u, v, w_aligned, h_aligned;
+ const unsigned int *reg = afbc_get_addrp(dec);
+ unsigned int vfmt_rpt_first = 1, vt_ini_phase = 0;
+ unsigned int out_height = 0;
+ /*ary add*/
+ unsigned int cvfmt_en = 0;
+ unsigned int cvfm_h, rpt_pix, phase_step = 16, hold_line = 8;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ di_print("afbc_in:vf typ[0x%x]\n", vf->type);
+
+ w_aligned = round_up((vf->width), 32);
+ /*if (di_pre_stru.cur_inp_type & VIDTYPE_INTERLACE)*/
+ if ((vf->type & VIDTYPE_INTERLACE) &&
+ (vf->type & VIDTYPE_VIU_422)) /*from vdin and is i */
+ h_aligned = round_up((vf->height / 2), 4);
+ else
+ h_aligned = round_up((vf->height), 4);
+
+ /*AFBCD working mode config*/
+ r = (3 << 24) |
+ (hold_line << 16) | /* hold_line_num : 2020 from 10 to 8*/
+ (2 << 14) | /*burst1 1:2020:ary change from 1 to 2*/
+ (vf->bitdepth & BITDEPTH_MASK);
+
+ if (vf->bitdepth & BITDEPTH_SAVING_MODE)
+ r |= (1 << 28); /* mem_saving_mode */
+ if (vf->type & VIDTYPE_SCATTER)
+ r |= (1 << 29);
+
+ out_height = h_aligned;
+ if (!(vf->type & VIDTYPE_VIU_422)) {
+ /*from dec, process P as i*/
+ if ((vf->type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP) {
+ r |= 0x40;
+ vt_ini_phase = 0xc;
+ vfmt_rpt_first = 1;
+ out_height = h_aligned >> 1;
+ } else if ((vf->type & VIDTYPE_TYPEMASK) ==
+ VIDTYPE_INTERLACE_BOTTOM) {
+ r |= 0x80;
+ vt_ini_phase = 0x4;
+ vfmt_rpt_first = 0;
+ out_height = h_aligned >> 1;
+ }
+ }
+
+ if (IS_420P_SRC(vf->type)) {
+ cvfmt_en = 1;
+ vt_ini_phase = 0xc;
+ cvfm_h = out_height >> 1;
+ rpt_pix = 1;
+ phase_step = 8;
+ } else {
+ cvfm_h = out_height;
+ rpt_pix = 0;
+ }
+ reg_wr(reg[EAFBC_MODE], r);
+
+ r = 0x1600;
+ //if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+ if (pafd_ctr->fb.ver >= AFBCD_V3) {
+ /* un compress mode data from vdin bit block order is
+ * different with from dos
+ */
+ if (!(vf->type & VIDTYPE_VIU_422))
+ r |= (1 << 19); /* dos_uncomp */
+
+ if (vf->type & VIDTYPE_COMB_MODE)
+ r |= (1 << 20);
+ }
+ reg_wr(reg[EAFBC_ENABLE], r);
+
+ /*pr_info("AFBC_ENABLE:0x%x\n", reg_rd(reg[eAFBC_ENABLE]));*/
+
+ r = 0x100;
+ /* TL1 add bit[13:12]: fmt_mode; 0:yuv444; 1:yuv422; 2:yuv420
+ * di does not support yuv444, so for fmt yuv444 di will bypass+
+ */
+ //if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
+ if (pafd_ctr->fb.ver >= AFBCD_V3) {
+ if (vf->type & VIDTYPE_VIU_444)
+ r |= (0 << 12);
+ else if (vf->type & VIDTYPE_VIU_422)
+ r |= (1 << 12);
+ else
+ r |= (2 << 12);
+ }
+ reg_wr(reg[EAFBC_CONV_CTRL], r);
+
+ u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
+ v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
+ reg_wr(reg[EAFBC_DEC_DEF_COLOR],
+ 0x3FF00000 | /*Y,bit20+*/
+ 0x80 << (u + 10) |
+ 0x80 << v);
+
+ u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
+ v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
+ reg_wr(reg[EAFBC_DEC_DEF_COLOR],
+ 0x3FF00000 | /*Y,bit20+*/
+ 0x80 << (u + 10) |
+ 0x80 << v);
+
+ /* chroma formatter */
+ reg_wr(reg[EAFBC_VD_CFMT_CTRL],
+ (rpt_pix << 28) |
+ (1 << 21) | /* HFORMATTER_YC_RATIO_2_1 */
+ (1 << 20) | /* HFORMATTER_EN */
+ (vfmt_rpt_first << 16) | /* VFORMATTER_RPTLINE0_EN */
+ (vt_ini_phase << 8) |
+ (phase_step << 1) | /* VFORMATTER_PHASE_BIT */
+ cvfmt_en);/* different with inp */
+
+ /*if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) { *//*ary add for g12a*/
+ if (pafd_ctr->fb.ver >= AFBCD_V3) {
+ if (vf->type & VIDTYPE_VIU_444)
+ reg_wr(reg[EAFBC_VD_CFMT_W],
+ (w_aligned << 16) | (w_aligned / 2));
+ else
+ reg_wr(reg[EAFBC_VD_CFMT_W],
+ (w_aligned << 16) | (w_aligned));
+ } else { /*ary add for g12a*/
+ reg_wr(reg[EAFBC_VD_CFMT_W],
+ (w_aligned << 16) | (w_aligned / 2));
+ }
+ reg_wr(reg[EAFBC_MIF_HOR_SCOPE],
+ (0 << 16) | ((w_aligned >> 5) - 1));
+ reg_wr(reg[EAFBC_MIF_VER_SCOPE],
+ (0 << 16) | ((h_aligned >> 2) - 1));
+
+ reg_wr(reg[EAFBC_PIXEL_HOR_SCOPE],
+ (0 << 16) | (vf->width - 1));
+ reg_wr(reg[EAFBC_PIXEL_VER_SCOPE],
+ 0 << 16 | (vf->height - 1));
+
+ reg_wr(reg[EAFBC_VD_CFMT_H], /*out_height*/cvfm_h);
+
+ reg_wr(reg[EAFBC_SIZE_IN], (vf->height) | w_aligned << 16);
+ reg_wr(reg[EAFBC_SIZE_OUT], out_height | w_aligned << 16);
+
+ reg_wr(reg[EAFBC_HEAD_BADDR], vf->compHeadAddr >> 4);
+ reg_wr(reg[EAFBC_BODY_BADDR], vf->compBodyAddr >> 4);
+
+ return true;
+}
+
+void afbc_update_level2_inp(struct afbcdv1_ctr_s *pctr)
+{
+ const unsigned int *reg = afbc_get_addrp(pctr->fb.pre_dec);
+ unsigned int vfmt_rpt_first = 1, vt_ini_phase = 12;
+ unsigned int old_mode, old_cfmt_ctrl;
+
+ di_print("%s\n", __func__);
+ old_mode = reg_rd(reg[EAFBC_MODE]);
+ old_cfmt_ctrl = reg_rd(reg[EAFBC_VD_CFMT_CTRL]);
+ old_mode &= (~(0x03 << 6));
+ if (!(pctr->l_vtype & VIDTYPE_VIU_422)) {
+ /*from dec, process P as i*/
+ if ((pctr->l_vtype & VIDTYPE_TYPEMASK) ==
+ VIDTYPE_INTERLACE_TOP) {
+ old_mode |= 0x40;
+
+ vt_ini_phase = 0xc;
+ vfmt_rpt_first = 1;
+ //out_height = h_aligned>>1;
+ } else if ((pctr->l_vtype & VIDTYPE_TYPEMASK) ==
+ VIDTYPE_INTERLACE_BOTTOM) {
+ old_mode |= 0x80;
+ vt_ini_phase = 0x4;
+ vfmt_rpt_first = 0;
+ //out_height = h_aligned>>1;
+ } else { //for p as p?
+ //out_height = h_aligned>>1;
+ }
+ }
+ reg_wr(reg[EAFBC_MODE], old_mode);
+ /* chroma formatter */
+ reg_wr(reg[EAFBC_VD_CFMT_CTRL],
+ old_cfmt_ctrl |
+ (vfmt_rpt_first << 16) | /* VFORMATTER_RPTLINE0_EN */
+ (vt_ini_phase << 8)); /* different with inp */
+
+ reg_wr(reg[EAFBC_HEAD_BADDR], pctr->addr_h >> 4);
+ reg_wr(reg[EAFBC_BODY_BADDR], pctr->addr_b >> 4);
+}
+
+static void afbce_set(struct vframe_s *vf);
+static void afbce_update_level1(struct vframe_s *vf,
+ const struct reg_acc *op,
+ enum EAFBC_ENC enc);
+
+static u32 enable_afbc_input(struct vframe_s *inp_vf,
+ struct vframe_s *mem_vf,
+ struct vframe_s *nr_vf)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+ //enum eAFBC_DEC dec = afbc_get_decnub();
+ struct vframe_s *mem_vf2;
+
+ if (!afbc_is_supported())
+ return false;
+
+ if (inp_vf->type & VIDTYPE_COMPRESS) {
+ afbc_sw(true);
+ } else {
+ afbc_sw(false);
+ return false;
+ }
+
+ if (is_cfg(EAFBCV1_CFG_ETEST))
+ mem_vf2 = inp_vf;
+ else
+ mem_vf2 = mem_vf;
+
+ afbc_check_chg_level(inp_vf, mem_vf, pafd_ctr);
+ if (pafd_ctr->b.chg_level == 3 || pafd_ctr->b.chg_mem == 3) {
+ /*inp*/
+ enable_afbc_input_local(inp_vf, pafd_ctr->fb.pre_dec);
+ if (pafd_ctr->fb.mode == 1 && pafd_ctr->b.chg_mem == 3) {
+ /*mem*/
+ enable_afbc_input_local(mem_vf2, pafd_ctr->fb.mem_dec);
+ /*nr*/
+ afbce_set(nr_vf);
+ }
+ } else if (pafd_ctr->b.chg_level == 2) {
+ afbc_update_level2_inp(pafd_ctr);
+
+ if (pafd_ctr->fb.mode == 1) { /*same as level 1*/
+ /*mem*/
+ afbc_update_level1(mem_vf2, pafd_ctr->fb.mem_dec);
+ /*nr*/
+ afbce_update_level1(nr_vf,
+ &di_normal_regset, EAFBC_ENC0);
+ }
+ } else if (pafd_ctr->b.chg_level == 1) {
+ /*inp*/
+ afbc_update_level1(inp_vf, pafd_ctr->fb.pre_dec);
+ if (pafd_ctr->fb.mode == 1) {
+ /*mem*/
+ afbc_update_level1(mem_vf2, pafd_ctr->fb.mem_dec);
+ /*nr*/
+ afbce_update_level1(nr_vf,
+ &di_normal_regset, EAFBC_ENC0);
+ }
+ }
+ return 0;
+}
+
+static void afbc_tm2_sw_inp(bool on)
+{
+ if (on)
+ reg_wrb(DI_AFBCE_CTRL, 0x03, 10, 2);
+ else
+ reg_wrb(DI_AFBCE_CTRL, 0x00, 10, 2);
+}
+
+static void afbc_tm2_sw_mem(bool on)
+{
+ if (on)
+ reg_wrb(DI_AFBCE_CTRL, 0x03, 12, 2);
+ else
+ reg_wrb(DI_AFBCE_CTRL, 0x00, 12, 2);
+}
+
+static void afbce_tm2_sw(bool on)
+{
+ if (on) {
+ /*1: nr channel 0 to afbce*/
+ reg_wrb(DI_AFBCE_CTRL, 0x01, 0, 1);
+ /* nr_en: important! 1:enable nr write to DDR; */
+ reg_wrb(DI_AFBCE_CTRL, 0x01, 4, 1);
+ } else {
+ reg_wrb(DI_AFBCE_CTRL, 0x00, 0, 1);
+ reg_wrb(DI_AFBCE_CTRL, 0x01, 4, 1);
+ }
+}
+
+static void afbcx_sw(bool on) /*g12a*/
+{
+ unsigned int tmp;
+ unsigned int mask;
+ unsigned int reg_ctrl, reg_en;
+ enum EAFBC_DEC dec_sel;
+ const unsigned int *reg = afbc_get_inp_base();
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ dec_sel = pafd_ctr->fb.pre_dec;
+
+ if (dec_sel == EAFBC_DEC0)
+ reg_ctrl = VD1_AFBCD0_MISC_CTRL;
+ else
+ reg_ctrl = VD2_AFBCD1_MISC_CTRL;
+
+ reg_en = reg[EAFBC_ENABLE];
+
+ mask = (3 << 20) | (1 << 12) | (1 << 9);
+ /*clear*/
+ tmp = reg_rd(reg_ctrl) & (~mask);
+
+ if (on) {
+ tmp = tmp
+ /*0:go_file 1:go_filed_pre*/
+ | (2 << 20)
+ /*0:afbc0 mif to axi 1:vd1 mif to axi*/
+ | (1 << 12)
+ /*0:afbc0 to vpp 1:afbc0 to di*/
+ | (1 << 9);
+ reg_wr(reg_ctrl, tmp);
+ /*0:vd1 to di 1:vd2 to di */
+ reg_wrb(VD2_AFBCD1_MISC_CTRL,
+ (reg_ctrl == VD1_AFBCD0_MISC_CTRL) ? 0 : 1, 8, 1);
+ /*reg_wr(reg_en, 0x1600);*/
+ reg_wrb(VIUB_MISC_CTRL0, 1, 16, 1);
+ /*TL1 add mem control bit */
+ //if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
+ if (pafd_ctr->fb.ver == AFBCD_V3)
+ reg_wrb(VD1_AFBCD0_MISC_CTRL, 1, 22, 1);
+ } else {
+ reg_wr(reg_ctrl, tmp);
+ reg_wr(reg_en, 0x1600);
+ reg_wrb(VIUB_MISC_CTRL0, 0, 16, 1);
+ //if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
+ if (pafd_ctr->fb.ver == AFBCD_V3)
+ reg_wrb(VD1_AFBCD0_MISC_CTRL, 0, 22, 1);
+ }
+}
+
+static void afbc_sw_old(bool on)/*txlx*/
+{
+ enum EAFBC_DEC dec_sel;
+ unsigned int reg_en;
+ const unsigned int *reg = afbc_get_inp_base();
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ dec_sel = pafd_ctr->fb.pre_dec;
+ reg_en = reg[EAFBC_ENABLE];
+
+ if (on) {
+ /* DI inp(current data) switch to AFBC */
+ if (reg_rdb(VIU_MISC_CTRL0, 29, 1) != 1)
+ reg_wrb(VIU_MISC_CTRL0, 1, 29, 1);
+ if (reg_rdb(VIUB_MISC_CTRL0, 16, 1) != 1)
+ reg_wrb(VIUB_MISC_CTRL0, 1, 16, 1);
+ if (reg_rdb(VIU_MISC_CTRL1, 0, 1) != 1)
+ reg_wrb(VIU_MISC_CTRL1, 1, 0, 1);
+ if (dec_sel == EAFBC_DEC0) {
+ /*gxl only?*/
+ if (reg_rdb(VIU_MISC_CTRL0, 19, 1) != 1)
+ reg_wrb(VIU_MISC_CTRL0, 1, 19, 1);
+ }
+ if (reg_rd(reg_en) != 0x1600)
+ reg_wr(reg_en, 0x1600);
+
+ } else {
+ reg_wr(reg_en, 0);
+ /* afbc to vpp(replace vd1) enable */
+ if (reg_rdb(VIU_MISC_CTRL1, 0, 1) != 0 ||
+ reg_rdb(VIUB_MISC_CTRL0, 16, 1) != 0) {
+ reg_wrb(VIU_MISC_CTRL1, 0, 0, 1);
+ reg_wrb(VIUB_MISC_CTRL0, 0, 16, 1);
+ }
+ }
+}
+
+static bool afbc_is_used(void)
+{
+ bool ret = false;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (pafd_ctr->b.en)
+ ret = true;
+
+ return ret;
+}
+
+static bool afbc_is_free(void)
+{
+ bool sts = 0;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+ u32 afbc_num = pafd_ctr->fb.pre_dec;
+
+ if (afbc_num == EAFBC_DEC0)
+ sts = reg_rdb(VD1_AFBCD0_MISC_CTRL, 8, 2);
+ else if (afbc_num == EAFBC_DEC1)
+ sts = reg_rdb(VD2_AFBCD1_MISC_CTRL, 8, 2);
+
+ if (sts)
+ return true;
+ else
+ return false;
+
+ return sts;
+}
+
+static void afbc_power_sw(bool on)
+{
+ /*afbc*/
+ enum EAFBC_DEC dec_sel;
+ unsigned int vpu_sel;
+ unsigned int reg_ctrl;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ dec_sel = pafd_ctr->fb.pre_dec;
+ if (dec_sel == EAFBC_DEC0)
+ vpu_sel = VPU_AFBC_DEC;
+ else
+ vpu_sel = VPU_AFBC_DEC1;
+
+ switch_vpu_mem_pd_vmod(vpu_sel,
+ on ? VPU_MEM_POWER_ON : VPU_MEM_POWER_DOWN);
+
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
+ if (dec_sel == EAFBC_DEC0)
+ reg_ctrl = VD1_AFBCD0_MISC_CTRL;
+ else
+ reg_ctrl = VD2_AFBCD1_MISC_CTRL;
+ if (on)
+ reg_wrb(reg_ctrl, 0, 0, 8);
+ else
+ reg_wrb(reg_ctrl, 0x55, 0, 8);
+ }
+ /*afbcx_power_sw(dec_sel, on);*/
+}
+
+//int afbc_reg_unreg_flag;
+
+static void afbc_sw_tl2(bool en)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!pafd_ctr->fb.mode) {
+ afbc_tm2_sw_inp(en);
+ } else if (pafd_ctr->fb.mode == 1) {
+ afbc_tm2_sw_inp(en);
+ afbc_tm2_sw_mem(en);
+ afbce_tm2_sw(en);
+ }
+}
+
+static void afbc_sw(bool on)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+ bool act = false;
+
+ /**/
+ if (pafd_ctr->b.en && !on)
+ act = true;
+ else if (!pafd_ctr->b.en && on)
+ act = true;
+
+ if (act) {
+ if (pafd_ctr->fb.ver == AFBCD_V1)
+ afbc_sw_old(on);
+ else if (pafd_ctr->fb.ver <= AFBCD_V3)
+ afbcx_sw(on);
+ else if (pafd_ctr->fb.ver == AFBCD_V4)
+ afbc_sw_tl2(on);
+
+ pafd_ctr->b.en = on;
+ pr_info("di:%s:%d\n", __func__, on);
+ }
+}
+
+void dbg_afbc_sw(bool on)
+{
+ afbc_sw(on);
+}
+
+static void afbc_input_sw(bool on);
+
+static void afbc_reg_variable(void)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (pafd_ctr->fb.ver == AFBCD_V4) {
+ if (is_cfg(EAFBCV1_CFG_EMODE))
+ pafd_ctr->fb.mode = 1;
+ else
+ pafd_ctr->fb.mode = 0;
+ }
+}
+
+static void afbc_reg_sw(bool on)
+{
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!afbc_is_supported())
+ return;
+ di_pr_info("%s:sw[%d]\n", __func__, on);
+ if (on) {
+ if (pafd_ctr->fb.ver <= AFBCD_V3) {
+ afbc_power_sw(true);
+ } else if (pafd_ctr->fb.ver == AFBCD_V4) {
+ if (is_cfg(EAFBCV1_CFG_EMODE))
+ pafd_ctr->fb.mode = 1;
+ else
+ pafd_ctr->fb.mode = 0;
+ reg_wrb(DI_AFBCE_CTRL, 0x01, 4, 1);
+ }
+ }
+ if (!on) {
+ pafd_ctr->l_vtype = 0;
+ pafd_ctr->l_vt_mem = 0;
+ pafd_ctr->l_h = 0;
+ pafd_ctr->l_w = 0;
+ pafd_ctr->l_bitdepth = 0;
+ if (pafd_ctr->fb.ver <= AFBCD_V3) {
+ /*input*/
+ afbc_input_sw(false);
+
+ afbc_sw(false);
+
+ afbc_power_sw(false);
+ } else {
+ /*AFBCD_V4*/
+ afbc_sw(false);
+ }
+ }
+}
+
+void dbg_afbc_on_g12a(bool on)
+{
+ if (on) {
+ afbc_power_sw(true);
+ afbc_sw(true);
+ } else {
+ afbc_power_sw(false);
+ afbc_sw(false);
+ }
+}
+
+static unsigned int afbc_count_info_size(unsigned int w, unsigned int h)
+{
+ unsigned int length = 0;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (afbc_is_supported() && pafd_ctr->fb.mode == 1)
+ length = PAGE_ALIGN((roundup(w, 32) * roundup(h, 4)) / 32);
+
+ pafd_ctr->size_info = length;
+ return length;
+}
+
+static unsigned int afbc_count_tab_size(unsigned int buf_size)
+{
+ unsigned int length = 0;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (afbc_is_supported() && pafd_ctr->fb.mode == 1)
+ length = PAGE_ALIGN(((buf_size * 2 + 0xfff) >> 12) *
+ sizeof(unsigned int));
+
+ pafd_ctr->size_tab = length;
+ return length;
+}
+
+static void afbc_int_tab(struct device *dev,
+ struct afbce_map_s *pcfg)
+{
+ bool flg;
+ unsigned int *p;
+ int i, cnt, last;
+ unsigned int body;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+ //struct di_mm_s *mm = dim_mm_get(ch);
+ //struct di_dev_s *de_devp = get_dim_de_devp();
+
+ if (!afbc_is_supported() ||
+ pafd_ctr->fb.mode != 1 ||
+ !pcfg ||
+ !dev)
+ return;
+
+ p = (unsigned int *)di_vmap(pcfg->tabadd, pcfg->size_buf, &flg);
+ if (!p) {
+ pafd_ctr->b.enc_err = 1;
+ pr_error("%s:vmap:0x%lx\n", __func__, pcfg->tabadd);
+ return;
+ }
+
+ cnt = (pcfg->size_buf * 2 + 0xfff) >> 12;
+ body = (unsigned int)(pcfg->bodyadd >> 12);
+ for (i = 0; i < cnt; i++) {
+ *(p + i) = body;
+ body++;
+ }
+ last = pcfg->size_tab - (cnt * sizeof(unsigned int));
+
+ memset((p + cnt), 0, last);
+
+ /*debug*/
+ di_pr_info("%s:tab:[0x%lx]: body[0x%lx];cnt[%d];last[%d]\n",
+ __func__,
+ pcfg->tabadd, pcfg->bodyadd, cnt, last);
+
+ dma_sync_single_for_device(dev,
+ pcfg->tabadd,
+ pcfg->size_tab,
+ DMA_TO_DEVICE);
+ if (flg)
+ di_unmap_phyaddr((u8 *)p);
+}
+
+static void afbc_input_sw(bool on)
+{
+ const unsigned int *reg;// = afbc_get_regbase();
+ unsigned int reg_AFBC_ENABLE;
+ struct afbcdv1_ctr_s *pafd_ctr = div1_get_afd_ctr();
+
+ if (!afbc_is_supported())
+ return;
+
+ reg = afbc_get_addrp(pafd_ctr->fb.pre_dec);
+ reg_AFBC_ENABLE = reg[EAFBC_ENABLE];
+
+ di_print("%s:reg[0x%x] sw[%d]\n", __func__, reg_AFBC_ENABLE, on);
+ if (on)
+ reg_wrb(reg_AFBC_ENABLE, 1, 8, 1);
+ else
+ reg_wrb(reg_AFBC_ENABLE, 0, 8, 1);
+
+ if (pafd_ctr->fb.mode == 1) {
+ /*mem*/
+ reg = afbc_get_addrp(pafd_ctr->fb.mem_dec);
+ reg_AFBC_ENABLE = reg[EAFBC_ENABLE];
+ if (on)
+ reg_wrb(reg_AFBC_ENABLE, 1, 8, 1);
+ else
+ reg_wrb(reg_AFBC_ENABLE, 0, 8, 1);
+ }
+}
+
+void dbg_afd_reg(struct seq_file *s, enum EAFBC_DEC eidx)
+{
+ int i;
+ unsigned int addr;
+
+ seq_printf(s, "dump reg:afd[%d]\n", eidx);
+
+ for (i = 0; i < AFBC_REG_INDEX_NUB; i++) {
+ addr = reg_AFBC[eidx][i];
+ seq_printf(s, "reg[0x%x]=0x%x.\n", addr, reg_rd(addr));
+ }
+}
+EXPORT_SYMBOL(dbg_afd_reg);
+
+void dbg_afe_reg(struct seq_file *s, enum EAFBC_ENC eidx)
+{
+ int i;
+ unsigned int addr;
+
+ seq_printf(s, "dump reg:afe[%d]\n", eidx);
+
+ for (i = 0; i < DIM_AFBCE_NUB; i++) {
+ addr = reg_afbc_e[eidx][i];
+ seq_printf(s, "reg[0x%x]=0x%x.\n", addr, reg_rd(addr));
+ }
+}
+EXPORT_SYMBOL(dbg_afe_reg);
+
+struct afdv1_ops_s di_afd_ops = {
+ .prob = afbc_prob,
+ .is_supported = afbc_is_supported,
+ .en_pre_set = enable_afbc_input,
+ .inp_sw = afbc_input_sw,
+ .reg_sw = afbc_reg_sw,
+ .reg_val = afbc_reg_variable,
+ .is_used = afbc_is_used,
+ .is_free = afbc_is_free,
+ .count_info_size = afbc_count_info_size,
+ .count_tab_size = afbc_count_tab_size,
+ .dump_reg = dump_afbcd_reg,
+ .rqst_share = di_requeset_afbc,
+ .get_d_addrp = afbc_get_addrp,
+ .get_e_addrp = afbce_get_addrp,
+ .dbg_rqst_share = dbg_requeset_afbc,
+ .int_tab = afbc_int_tab,
+ .is_cfg = is_cfg,
+};
+
+bool di_attach_ops_afd(const struct afdv1_ops_s **ops)
+{
+ *ops = &di_afd_ops;
+ return true;
+}
+EXPORT_SYMBOL(di_attach_ops_afd);
+
+/*afbc e**********************************************************************/
+/*****************************************************************************/
+
+/*don't change order*/
+
+static const unsigned int afbce_default_val[DIM_AFBCE_UP_NUB] = {
+ /*need add*/
+ 0x00000000,
+ 0x03044000,
+ 0x07800438,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+void vf_set_for_com(struct di_buf_s *di_buf)
+{
+ struct vframe_s *vf;
+
+ vf = di_buf->vframe;
+
+ vf->canvas0_config[0].phy_addr = di_buf->nr_adr;
+ vf->type |= (VIDTYPE_COMPRESS | VIDTYPE_SCATTER);
+ vf->canvas0_config[0].width = di_buf->canvas_width[NR_CANVAS],
+ vf->canvas0_config[0].height = di_buf->canvas_height;
+ vf->canvas0_config[0].block_mode = 0;
+ vf->plane_num = 1;
+ vf->canvas0Addr = -1;
+ vf->canvas1Addr = -1;
+ vf->compHeadAddr = di_buf->afbc_adr;
+ vf->compBodyAddr = di_buf->nr_adr;
+ vf->compHeight = vf->height;
+ vf->compWidth = vf->width;
+ vf->bitdepth |= (BITDEPTH_U10 | BITDEPTH_V10);
+#ifdef DBG_AFBC
+
+ if (afbc_cfg_vf)
+ vf->type |= afbc_cfg_vf;
+ if (afbc_cfg_bt)
+ vf->bitdepth |= afbc_cfg_bt;
+#endif
+}
+
+#if 1
+struct enc_cfg_s {
+ int enable;
+ int loosy_mode;
+ /* loosy_mode:
+ * 0:close 1:luma loosy 2:chrma loosy 3: luma & chrma loosy
+ */
+
+ int head_baddr;/*head addr*/
+ int mmu_info_baddr;/*mmu info linear addr*/
+ int reg_format_mode;/*0:444 1:422 2:420*/
+ int reg_compbits_y;/*bits num after compression*/
+ int reg_compbits_c;/*bits num after compression*/
+
+ int hsize_in;/*input hsize*/
+ int vsize_in;/*input hsize*/
+ int enc_win_bgn_h;/*input scope*/
+ int enc_win_end_h;/*input scope*/
+ int enc_win_bgn_v;/*input scope*/
+ int enc_win_end_v;/*input scope*/
+};
+
+/*enc: set_di_afbce_cfg ******************/
+static void ori_afbce_cfg(struct enc_cfg_s *cfg,
+ const struct reg_acc *op,
+ enum EAFBC_ENC enc)
+{
+ const unsigned int *reg;
+ int hold_line_num = 4;
+ int lbuf_depth = 256;
+ int rev_mode = 0;
+ int def_color_0 = 0x3ff;
+ int def_color_1 = 0x80;
+ int def_color_2 = 0x80;
+ int def_color_3 = 0;
+ int hblksize_out = (cfg->hsize_in + 31) >> 5;
+ int vblksize_out = (cfg->vsize_in + 3) >> 2;
+ /* output blk scope */
+ int blk_out_end_h = cfg->enc_win_bgn_h >> 5;
+ /* output blk scope */
+ int blk_out_bgn_h = (cfg->enc_win_end_h + 31) >> 5;
+ /*output blk scope */
+ int blk_out_end_v = cfg->enc_win_bgn_v >> 2;
+ /* output blk scope */
+ int blk_out_bgn_v = (cfg->enc_win_end_v + 3) >> 2;
+
+ int lossy_luma_en;
+ int lossy_chrm_en;
+ int cur_mmu_used = 0;/*mmu info linear addr*/
+
+ int reg_fmt444_comb;
+ int uncmp_size ;/*caculate*/
+ int uncmp_bits ;/*caculate*/
+ int sblk_num ;/*caculate*/
+
+ reg = ®_afbc_e[enc][0];
+
+ /*yuv444 can only support 8bit,and must use comb_mode*/
+ if (cfg->reg_format_mode == 0 && cfg->hsize_in > 2048)
+ reg_fmt444_comb = 1;
+ else
+ reg_fmt444_comb = 0;
+
+ /* 4*4 subblock number in every 32*4 mblk */
+ if (cfg->reg_format_mode == 2)
+ sblk_num = 12;
+ else if (cfg->reg_format_mode == 1)
+ sblk_num = 16;
+ else
+ sblk_num = 24;
+
+ if (cfg->reg_compbits_y > cfg->reg_compbits_c)
+ uncmp_bits = cfg->reg_compbits_y;
+ else
+ uncmp_bits = cfg->reg_compbits_c;
+
+ /*bit size of uncompression mode*/
+ uncmp_size = (((((16 * uncmp_bits * sblk_num) + 7) >> 3) +
+ 31) / 32) << 1;
+
+ /*chose loosy mode of luma and chroma */
+ if (cfg->loosy_mode == 0) {
+ lossy_luma_en = 0;
+ lossy_chrm_en = 0;
+ } else if (cfg->loosy_mode == 1) {
+ lossy_luma_en = 1;
+ lossy_chrm_en = 0;
+ } else if (cfg->loosy_mode == 2) {
+ lossy_luma_en = 0;
+ lossy_chrm_en = 1;
+ } else {
+ lossy_luma_en = 1;
+ lossy_chrm_en = 1;
+ }
+
+ op->wr(reg[EAFBCE_MODE],
+ (0 & 0x7) << 29 |
+ (rev_mode & 0x3) << 26 |
+ (3 & 0x3) << 24 |
+ (hold_line_num & 0x7f) << 16 |
+ (2 & 0x3) << 14 |
+ (reg_fmt444_comb & 0x1));
+ /* loosy */
+ op->bwr(reg[EAFBCE_QUANT_ENABLE], (lossy_luma_en & 0x1), 0, 1);
+ op->bwr(reg[EAFBCE_QUANT_ENABLE], (lossy_chrm_en & 0x1), 4, 1);
+
+ /* hsize_in of afbc input*/
+ /* vsize_in of afbc input*/
+ op->wr(reg[EAFBCE_SIZE_IN],
+ ((cfg->hsize_in & 0x1fff) << 16) |
+ ((cfg->vsize_in & 0x1fff) << 0)
+ );
+
+ /* out blk hsize*/
+ /* out blk vsize*/
+ op->wr(reg[EAFBCE_BLK_SIZE_IN],
+ ((hblksize_out & 0x1fff) << 16) |
+ ((vblksize_out & 0x1fff) << 0)
+ );
+
+ /*head addr of compressed data*/
+ op->wr(reg[EAFBCE_HEAD_BADDR], cfg->head_baddr);
+
+ /*uncmp_size*/
+ op->bwr(reg[EAFBCE_MIF_SIZE], (uncmp_size & 0x1fff), 16, 5);
+
+ /* scope of hsize_in ,should be a integer multipe of 32*/
+ /* scope of vsize_in ,should be a integer multipe of 4*/
+ op->wr(reg[EAFBCE_PIXEL_IN_HOR_SCOPE],
+ ((cfg->enc_win_end_h & 0x1fff) << 16) |
+ ((cfg->enc_win_bgn_h & 0x1fff) << 0));
+
+ /* scope of hsize_in ,should be a integer multipe of 32*/
+ /* scope of vsize_in ,should be a integer multipe of 4*/
+ op->wr(reg[EAFBCE_PIXEL_IN_VER_SCOPE],
+ ((cfg->enc_win_end_v & 0x1fff) << 16) |
+ ((cfg->enc_win_bgn_v & 0x1fff) << 0)
+ );
+
+ /*fix 256*/
+ op->wr(reg[EAFBCE_CONV_CTRL], lbuf_depth);
+
+ /* scope of out blk hsize*/
+ /* scope of out blk vsize*/
+ op->wr(reg[EAFBCE_MIF_HOR_SCOPE],
+ ((blk_out_bgn_h & 0x3ff) << 16) |
+ ((blk_out_end_h & 0xfff) << 0)
+ );
+
+ /* scope of out blk hsize*/
+ /* scope of out blk vsize*/
+ op->wr(reg[EAFBCE_MIF_VER_SCOPE],
+ ((blk_out_bgn_v & 0x3ff) << 16) |
+ ((blk_out_end_v & 0xfff) << 0)
+ );
+
+ op->wr(reg[EAFBCE_FORMAT],
+ (cfg->reg_format_mode & 0x3) << 8 |
+ (cfg->reg_compbits_c & 0xf) << 4 |
+ (cfg->reg_compbits_y & 0xf));
+
+ /* def_color_a*/
+ /* def_color_y*/
+ op->wr(reg[EAFBCE_DEFCOLOR_1],
+ ((def_color_3 & 0xfff) << 12) |
+ ((def_color_0 & 0xfff) << 0));
+
+ /* def_color_v*/
+ /* def_color_u*/
+ op->wr(reg[EAFBCE_DEFCOLOR_2],
+ ((def_color_2 & 0xfff) << 12) |
+ ((def_color_1 & 0xfff) << 0));
+
+ /*4k addr have used in every frame;*/
+ /*cur_mmu_used += Rd(DI_AFBCE_MMU_NUM);*/
+
+ op->bwr(reg[EAFBCE_MMU_RMIF_CTRL4], cfg->mmu_info_baddr, 0, 32);
+ op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], cur_mmu_used, 0, 12);
+ op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], 0x1ffe, 16, 13);
+ op->bwr(reg[EAFBCE_MMU_RMIF_CTRL3], 0x1fff, 0, 13);
+
+ if (is_meson_tm2b())//dis afbce mode from vlsi xianjun.fan
+ op->bwr(reg[EAFBCE_MODE_EN], 0x1, 18, 1);
+ op->bwr(reg[EAFBCE_ENABLE], cfg->enable, 8, 1);//enable afbce
+ op->bwr(DI_AFBCE_CTRL, cfg->enable, 0, 1);//di pre to afbce
+ op->bwr(DI_AFBCE_CTRL, cfg->enable, 4, 1);//di pre to afbce
+}
+
+/* set_di_afbce_cfg */
+static void afbce_set(struct vframe_s *vf)
+{
+ struct enc_cfg_s cfg_data;
+ struct enc_cfg_s *cfg = &cfg_data;
+ struct di_buf_s *di_buf;
+
+ if (!vf) {
+ pr_error("%s:0:no vf\n", __func__);
+ return;
+ }
+ di_buf = (struct di_buf_s *)vf->private_data;
+
+ if (!di_buf) {
+ pr_error("%s:1:no di buf\n", __func__);
+ return;
+ }
+
+ cfg->enable = 1;
+ /* 0:close 1:luma lossy 2:chrma lossy 3: luma & chrma lossy*/
+ cfg->loosy_mode = 0;
+ cfg->head_baddr = di_buf->afbc_adr;//head_baddr_enc;/*head addr*/
+ cfg->mmu_info_baddr = di_buf->afbct_adr;
+ //vf->compHeadAddr = cfg->head_baddr;
+ //vf->compBodyAddr = di_buf->nr_adr;
+ vf_set_for_com(di_buf);
+#ifdef AFBCP
+ di_print("%s:buf[%d],hadd[0x%x],info[0x%x]\n",
+ __func__,
+ di_buf->index,
+ cfg->head_baddr,
+ cfg->mmu_info_baddr);
+#endif
+ cfg->reg_format_mode = 1;/*0:444 1:422 2:420*/
+ cfg->reg_compbits_y = 10;//8;/*bits num after compression*/
+ cfg->reg_compbits_c = 10;//8;/*bits num after compression*/
+
+ /*input size*/
+ cfg->hsize_in = vf->width;//src_w;
+ cfg->vsize_in = vf->height;//src_h;
+ /*input scope*/
+ cfg->enc_win_bgn_h = 0;
+ cfg->enc_win_end_h = vf->width - 1;
+ cfg->enc_win_bgn_v = 0;
+ cfg->enc_win_end_v = vf->height - 1;
+
+ ori_afbce_cfg(cfg, &di_normal_regset, EAFBC_ENC0);
+}
+
+static void afbce_update_level1(struct vframe_s *vf,
+ const struct reg_acc *op,
+ enum EAFBC_ENC enc)
+{
+ const unsigned int *reg;
+ struct di_buf_s *di_buf;
+ unsigned int cur_mmu_used = 0;
+
+ di_buf = (struct di_buf_s *)vf->private_data;
+
+ if (!di_buf) {
+ pr_error("%s:1:no di buf\n", __func__);
+ return;
+ }
+
+ reg = ®_afbc_e[enc][0];
+ di_print("di_buf:t[%d][%d],adr[0x%lx],inf[0x%lx]\n",
+ di_buf->type, di_buf->index,
+ di_buf->nr_adr, di_buf->afbc_adr);
+ //vf->compHeadAddr = di_buf->afbc_adr;
+ //vf->compBodyAddr = di_buf->nr_adr;
+ vf_set_for_com(di_buf);
+
+ //head addr of compressed data
+ op->wr(reg[EAFBCE_HEAD_BADDR], di_buf->afbc_adr);
+ op->bwr(reg[EAFBCE_MMU_RMIF_CTRL4], di_buf->afbct_adr, 0, 32);
+ op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], cur_mmu_used, 0, 12);
+ op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], 0x1ffe, 16, 13);
+ op->bwr(reg[EAFBCE_MMU_RMIF_CTRL3], 0x1fff, 0, 13);
+}
+#endif
+#endif
+
--- /dev/null
+/*
+ * drivers/amlogic/media/deinterlace/di_afbc.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __DI_AFBC_H__
+#define __DI_AFBC_H__
+
+#define AFBC_REG_INDEX_NUB (18)
+/*also see enum eAFBC_DEC*/
+#define AFBC_DEC_NUB (4)
+#define AFBC_ENC_NUB (1)
+
+enum EAFBC_REG {
+ EAFBC_ENABLE,
+ EAFBC_MODE,
+ EAFBC_SIZE_IN,
+ EAFBC_DEC_DEF_COLOR,
+ EAFBC_CONV_CTRL,
+ EAFBC_LBUF_DEPTH,
+ EAFBC_HEAD_BADDR,
+ EAFBC_BODY_BADDR,
+ EAFBC_SIZE_OUT,
+ EAFBC_OUT_YSCOPE,
+ EAFBC_STAT,
+ EAFBC_VD_CFMT_CTRL,
+ EAFBC_VD_CFMT_W,
+ EAFBC_MIF_HOR_SCOPE,
+ EAFBC_MIF_VER_SCOPE,
+ EAFBC_PIXEL_HOR_SCOPE,
+ EAFBC_PIXEL_VER_SCOPE,
+ EAFBC_VD_CFMT_H,
+};
+
+#define DIM_AFBCE_NUB (39)
+#define DIM_AFBCE_UP_NUB (21)
+
+/* afbce bytes index */
+enum EAFBCE_INDEX {
+ EAFBCE_ENABLE, /* 0 */
+ EAFBCE_MODE, /* 1 */
+ EAFBCE_SIZE_IN, /* 2 */
+ EAFBCE_BLK_SIZE_IN, /* 3 */
+ EAFBCE_HEAD_BADDR, /* 4 */
+ EAFBCE_MIF_SIZE, /* 5 */
+ EAFBCE_PIXEL_IN_HOR_SCOPE, /* 6 */
+ EAFBCE_PIXEL_IN_VER_SCOPE, /* 7 */
+ EAFBCE_CONV_CTRL, /* 8 */
+ EAFBCE_MIF_HOR_SCOPE, /* 9 */
+ EAFBCE_MIF_VER_SCOPE, /* 10 */
+
+ EAFBCE_FORMAT, /* 11 */
+ EAFBCE_DEFCOLOR_1, /* 12 */
+ EAFBCE_DEFCOLOR_2, /* 13 */
+ EAFBCE_QUANT_ENABLE, /* 14 */
+
+ EAFBCE_MMU_RMIF_CTRL1, /* 15 */
+ EAFBCE_MMU_RMIF_CTRL2, /* 16 */
+ EAFBCE_MMU_RMIF_CTRL3, /* 17 */
+ EAFBCE_MMU_RMIF_CTRL4, /* 18 */
+ EAFBCE_MMU_RMIF_SCOPE_X, /* 29 */
+ EAFBCE_MMU_RMIF_SCOPE_Y, /* 20 */
+
+ /**********************/
+ EAFBCE_MODE_EN,
+ EAFBCE_DWSCALAR,
+ EAFBCE_IQUANT_LUT_1,
+ EAFBCE_IQUANT_LUT_2,
+ EAFBCE_IQUANT_LUT_3,
+ EAFBCE_IQUANT_LUT_4,
+ EAFBCE_RQUANT_LUT_1,
+ EAFBCE_RQUANT_LUT_2,
+ EAFBCE_RQUANT_LUT_3,
+ EAFBCE_RQUANT_LUT_4,
+ EAFBCE_YUV_FORMAT_CONV_MODE,
+ EAFBCE_DUMMY_DATA,
+ EAFBCE_CLR_FLAG,
+ EAFBCE_STA_FLAGT,
+ EAFBCE_MMU_NUM,
+ EAFBCE_STAT1, /*read only*/
+ EAFBCE_STAT2,
+ EAFBCE_MMU_RMIF_RO_STAT,
+};
+
+#define AFBC_VTYPE_MASK_CHG (VIDTYPE_INTERLACE | \
+ VIDTYPE_VIU_422 | \
+ VIDTYPE_VIU_444 | \
+ VIDTYPE_VIU_NV21 | \
+ VIDTYPE_COMPRESS | \
+ VIDTYPE_SCATTER | \
+ VIDTYPE_COMB_MODE)
+
+#define AFBC_VTYPE_MASK_OTHER (VIDTYPE_COMPRESS | \
+ VIDTYPE_SCATTER | \
+ VIDTYPE_COMB_MODE)
+
+#define AFBC_VTYPE_MASK_SAV (VIDTYPE_TYPEMASK | \
+ VIDTYPE_VIU_422 | \
+ VIDTYPE_VIU_444 | \
+ VIDTYPE_VIU_NV21 | \
+ VIDTYPE_COMPRESS | \
+ VIDTYPE_SCATTER | \
+ VIDTYPE_COMB_MODE)
+
+#define AFBCD_NONE (0)
+#define AFBCD_V1 (1) /*gxl and txlx*/
+#define AFBCD_V2 (2) /*g12a*/
+#define AFBCD_V3 (3) /*tl1*/
+#define AFBCD_V4 (4) /*tm2 vb*/
+
+//void afbc_prob(void);
+
+//unsigned int afbc_count_info_size(unsigned int w, unsigned int h);
+
+//extern struct afd_ops_s di_afd_ops;
+
+//const unsigned int *afbc_get_addrp(enum eAFBC_DEC eidx);
+//const unsigned int *afbce_get_addrp(enum EAFBC_ENC eidx);
+/*define in vpp*/
+s32 di_request_afbc_hw(u8 id, bool on);
+//bool cfg_pmode(void);
+//bool cfg_test4k(void);
+//bool dbg_di_prelink(void);
+//void dbg_afd_reg(struct seq_file *s, enum EAFBC_DEC eidx);
+#endif /*__DI_AFBC_H__*/
void (*cue_int)(struct vframe_s *vf);
void (*adaptive_cue_adjust)(unsigned int frame_diff,
unsigned int field_diff);
+ void (*secam_cfr_adjust)(unsigned int sig_fmt,
+ unsigned int frame_type);
int (*module_para)(struct seq_file *seq);
};
#define DI_IC_ID_TL1 (0x16)
#define DI_IC_ID_TM2 (0x17)
#define DI_IC_ID_TM2B (0x18)
-#define DI_IC_ID_T5 (0x19)// same with tm2b
+#define DI_IC_ID_T5 (0x19)// same with tm2b
+#define DI_IC_ID_T5D (0x1A)// same with tm2b
#define DI_IC_ID_SC2 (0x1B)
+#define DI_IC_ID_T7 (0x1C)
+#define DI_IC_ID_S4 (0x1D)
+
#define DI_IC_ID_DEINTERLACE (0xFF)
/* is_meson_g12a_cpu */
EAFBC_ENC1,
};
+enum EAFBCV1_CFG {
+ EAFBCV1_CFG_EN,
+ EAFBCV1_CFG_PMODE,
+ EAFBCV1_CFG_EMODE,
+ EAFBCV1_CFG_ETEST,
+ EAFBCV1_CFG_4K,
+ EAFBCV1_CFG_PRE_LINK,
+ EAFBCV1_CFG_PAUSE,
+ EAFBCV1_CFG_LEVE3,
+};
+
enum EAFBC_CFG {
EAFBC_CFG_DISABLE,
EAFBC_CFG_INP_AFBC, /* < AFBCD_V4 */
enum EAFBC_STS {
EAFBC_MEM_NEED,
EAFBC_MEMI_NEED,
+ EAFBC_EN_6CH, //en afbcd x 6
+ EAFBC_EN_ENC, //en afbce x 2
+};
+enum EAFBC_SNG_SET {
+ EAFBC_SNG_CLR_NR,
+ EAFBC_SNG_CLR_WR,
+ EAFBC_SNG_SET_NR,
+ EAFBC_SNG_SET_WR,
};
struct afbce_map_s {
//rev4 : 8;
};
+struct afbcdv1_ctr_s {
+ union {
+ unsigned int f32;
+ struct {
+ unsigned int ver : 8,
+
+ sp_inp : 1,
+ sp_mem : 1,
+ /*0:inp only, 1: inp + mem*/
+ mode : 2,
+ rev1 : 4,
+
+ pre_dec : 4,
+ mem_dec : 4,
+
+ rev4 : 8;
+ } fb;
+ };
+ union {
+ unsigned int d32;
+ struct {
+ unsigned int int_flg : 1, /*addr ini*/
+ en : 1,
+ enc_err : 1,
+ rev1 : 5,
+
+ chg_level : 2,
+ chg_mem : 2, /*add*/
+ rev2 : 4,
+
+ rev3 : 8,
+ rev4 : 8;
+ } b;
+ };
+ unsigned int size_tab;
+ unsigned int size_info;
+ unsigned int l_vtype;
+ unsigned int l_vt_mem;
+ unsigned int l_h;
+ unsigned int l_w;
+ unsigned int l_bitdepth;
+ unsigned int addr_h;
+ unsigned int addr_b;
+ unsigned int mem_addr_h;
+ unsigned int mem_addr_b;
+};
+
+struct afdv1_s {
+ struct afbcdv1_ctr_s ctr;
+};
+
struct afbcd_ctr_s {
struct afbc_fb_s fb;
union {
AFBC_SGN_I_H265,
};
+struct afdv1_ops_s {
+ void (*prob)(unsigned int cid);
+ bool (*is_supported)(void);
+ u32 (*en_pre_set)(struct vframe_s *inp_vf,
+ struct vframe_s *mem_vf,
+ struct vframe_s *nr_vf);
+ void (*inp_sw)(bool on);
+ bool (*is_used)(void);
+ bool (*is_free)(void);/*?*/
+ bool (*is_cfg)(enum EAFBCV1_CFG cfg_cmd);
+ unsigned int (*count_info_size)(unsigned int w, unsigned int h);
+ unsigned int (*count_tab_size)(unsigned int buf_size);
+ void (*int_tab)(struct device *dev,
+ struct afbce_map_s *pcfg);
+ void (*dump_reg)(void);
+ void (*reg_sw)(bool on);
+ void (*reg_val)(void);
+ u32 (*rqst_share)(bool onoff);
+ const unsigned int *(*get_d_addrp)(enum EAFBC_DEC eidx);
+ const unsigned int *(*get_e_addrp)(enum EAFBC_ENC eidx);
+ u32 (*dbg_rqst_share)(bool onoff);
+};
+
struct afd_ops_s {
void (*prob)(unsigned int cid, struct afd_s *p);
bool (*is_supported)(void);
//void (*pre_check2)(struct di_buf_s *di_buf);
void (*pst_check)(struct vframe_s *vf, void *pch);
bool (*is_sts)(enum EAFBC_STS status);
- void (*sgn_mode_set)(unsigned int sgn_mode);
+ void (*sgn_mode_set)(unsigned char *sgn_mode, enum EAFBC_SNG_SET cmd);
unsigned char (*cnt_sgn_mode)(unsigned int sgn);
void (*cfg_mode_set)(unsigned int mode, union afbc_blk_s *en_cfg);
};
int dbg_afbc_cfg_v3_show(struct seq_file *s, void *v);/*debug*/
void dbg_afd_reg_v3(struct seq_file *s, enum EAFBC_DEC eidx);
-bool di_attach_ops_afd(const struct afd_ops_s **ops);
+bool di_attach_ops_afd(const struct afdv1_ops_s **ops);
bool di_attach_ops_afd_v3(const struct afd_ops_s **ops);
/************************************************
*rCmb32Spcl = 1;
} else if (pRDat.pMod22[HISDETNUM - 1] == 2) {
nMod = pRDat.pMod22[HISDETNUM - 1];
+ pRDat.mNum32[HISDETNUM - 1] = 0;
/* nT0 = pRDat.pFlg22[HISDETNUM - 1] % 2; */
if (pRDat.mNum22[HISDETNUM - 1] < 255) /* maximum */
nFlgChk4 = nDif02[HISDIFNUM - 1] - nDif02[HISDIFNUM - 6];
if (nFlgChk4 < 0)
nFlgChk4 = -nFlgChk4;
- nFlgChk4 = nFlgChk4;
+ //nFlgChk4 = nFlgChk4;
nMean = (nDif02[HISDIFNUM - 1] + nDif01[HISDIFNUM - 6]) / 2;
nFlgChk4 = nflagch4_ratio * nFlgChk4 / nMean;
} else {
((nMx + nMn / 2) / (nMn + 1)) < flm32_dif02_gap &&
pFlg32[HISDETNUM - 1] > 1)
nSTP = 0;
+ /*bias static similar to pulldown, max02 must bigger than min02*/
+ /*suggest from vlsi yanling*/
+ if (nMx < (1 << 14) && nMx < (nMn << 7) && pFlg32[HISDETNUM - 1] > 1)
+ nSTP = 0;
/*---------------*/
for (nT0 = 1; nT0 < HISDETNUM; nT0++) {
pFlm02[nT0 - 1] = pFlm02[nT0];
int iHeight = pRDat->iHeight;
int nFlm22Lvl = 0;
int nSIZE = iWidth * iHeight + 1;
+ int max_diff;
+ int ratio;
prt_flg = ((pr_pd >> 3) & 0x1);
if (prt_flg)
}
/* ---------------------- */
/*DI:PQ patch fix 480i error into pulldown22(by yanling)*/
+ max_diff = max(abs(nDif01[HISDIFNUM - 1] - nDif01[HISDIFNUM - 3]),
+ abs(nDif01[HISDIFNUM - 2] - nDif01[HISDIFNUM - 4]));
+ if (max_diff > (1 << 15))
+ ratio = 2;
+ else
+ ratio = 3;
flm22_min = nDif01[HISDIFNUM-1] > nDif01[HISDIFNUM-2]
? nDif01[HISDIFNUM-2] : nDif01[HISDIFNUM-1];
- flm22_th = min(flm22_min / 2, 1 << 16);
+ flm22_th = max(flm22_min / ratio, 1 << 17);
dif_flag = abs(nDif01[HISDIFNUM-1]-nDif01[HISDIFNUM-2])
> flm22_th ? 1:0;
- dif_flag =
+ /*the small diff01 bigger*/
+ dif_flag = (flm22_min > max((3 << 17), nDif02[HISDIFNUM - 1])) ? 0 :
max(nDif01[HISDIFNUM-1], nDif01[HISDIFNUM-2]) > (1<<16) ?
dif_flag : 0;
- if (flm22_flag && dif_flag) {
+ if (pr_pd)
+ pr_info("max_diff = %d, dif_flag = %d, flm22_th = %d, flm22_min = %d\n",
+ max_diff, dif_flag, flm22_th, flm22_min);
+ if (flm22_flag && dif_flag && (max_diff < (5 << 14))) {
/* ---------------------- */
if (pFlg[HISDETNUM-1] == 3
|| pFlg[HISDETNUM-1] == 1) {
sModFlg01[tT0] = tModFlg01[tT0];
sModFlg02[tT0] = tModFlg02[tT0];
+
+ /*bias static similar to pulldown 32322*/
+ /*max02 must bigger than min02*/
+ /*suggest from vlsi yanling*/
+ if (nMax02 < (1 << 11))
+ nModLvl[tT0] = 0;
} /* 2-3-4-5*/
}
#include "register_nr4.h"
#include "nr_drv.h"
#include "deinterlace.h"
+#include "deinterlace_dbg.h"
#include "di_pqa.h"
+
static DNR_PRM_t dnr_param;
static struct NR_PARM_s nr_param;
static bool dnr_pr;
module_param(dnr_pr, bool, 0644);
MODULE_PARM_DESC(dnr_pr, "/n print dnr debug information /n");
-/*************************
- * dnr_dm_en
- * [0]: reg_dnr_dm_en
- * [1]: reg_dnr_dm_chrmen
- * [9]: force_dm_chrmen
- */
-static unsigned int dnr_dm_en;
-module_param(dnr_dm_en, uint, 0644);
+static bool dnr_dm_en;
+module_param(dnr_dm_en, bool, 0644);
MODULE_PARM_DESC(dnr_dm_en, "/n dnr dm enable debug /n");
-enum DM_MP {
- DM_EN,
- DM_CHRMEN,
-};
-
-static unsigned int dm_mp(enum DM_MP emp)
-{
- unsigned int val = 0;
-
- switch (emp) {
- case DM_EN:
- val = (dnr_dm_en & 0x01);
- break;
- case DM_CHRMEN:
- if (dnr_dm_en & 0x200) {
- val = (dnr_dm_en & 0x02) >> 1;
- } else {
- if (is_meson_gxlx_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_sm1_cpu()) {
- //cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)
- val = 0;
- } else {
- val = (dnr_dm_en & 0x02) >> 1;
- }
- }
- break;
- }
-
- return val;
-}
-
-/*dnr_en
- * bit[0]: dnr_en: bit16
- * bit[1]: dnr_db_chrmen: bit9
- * bit[3:2]: dnr_db_mod bit [11:10]
- */
-static unsigned int dnr_en = 0x0f;
-module_param_named(dnr_en, dnr_en, uint, 0644);
-
-enum DNR_MP {
- DNR_M_DNR,
- DNR_M_DB_CHR,
- DNR_M_DB_MOD,
-};
-
-static unsigned int dnr_mp(enum DNR_MP emp)
-{
- unsigned int val = 0;
-
- switch (emp) {
- case DNR_M_DNR:
- val = dnr_en & 0x01;
- break;
- case DNR_M_DB_CHR:
- val = (dnr_en & 0x02) >> 1;
- break;
- case DNR_M_DB_MOD:
- val = (dnr_en & 0x0c) >> 2;
- break;
- }
-
- return val;
-}
-
-static unsigned int dnr_cfg(unsigned int val)
-{
- val &= (~((1 << 16) |
- (1 << 9) |
- (3 << 10)));
-
- val |= (((dnr_en & 0x01) << 16) |
- (((dnr_en & 0x02) >> 1) << 9) |
- (((dnr_en & 0x0c) >> 2) << 10));
- return val;
-}
+static bool dnr_en = true;
+module_param_named(dnr_en, dnr_en, bool, 0644);
static unsigned int nr2_en = 0x1;
module_param_named(nr2_en, nr2_en, uint, 0644);
+static bool dynamic_dm_chk = true;
+module_param_named(dynamic_dm_chk, dynamic_dm_chk, bool, 0644);
+
static bool nr_ctrl_reg;
bool nr_demo_flag;
return 0;
}
#endif
+static u32 check_dnr_dm_ctrl(
+ u32 org_val, unsigned short width, unsigned short height)
+{
+ if (!dynamic_dm_chk)
+ return org_val;
+
+ if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
+ /* disable dm chroma when > 720p */
+ if (width > 1280)
+ org_val &= ~(1 << 8);
+ /* disable dm when > 1080p */
+ if (width > 1920 || !dnr_dm_en)
+ org_val &= ~(1 << 9);
+ } else if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() ||
+ is_meson_g12b_cpu() || is_meson_sm1_cpu()) {
+ /* disable chroma dm according to baozheng */
+ org_val &= ~(1 << 8);
+ /* disable dm when > 1080p */
+ if (width > 1920 || !dnr_dm_en)
+ org_val &= ~(1 << 9);
+ } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX) ||
+ is_meson_gxl_cpu()) {
+ /* disable dm when >720p */
+ if (width > 1280 || !dnr_dm_en) {
+ org_val &= ~(1 << 8);
+ /* disable dm for 1080 which will cause pre timeout*/
+ org_val &= ~(1 << 9);
+ }
+ } else {
+ /* disable dm when >= 1080p for other chips */
+ if (width >= 1920 || !dnr_dm_en)
+ org_val &= ~(1 << 9);
+ }
+ return org_val;
+}
+
static void dnr_config(struct DNR_PARM_s *dnr_parm_p,
unsigned short width, unsigned short height)
{
DI_Wr(DNR_STAT_Y_START_END, (((border_offset<<3)&0x3fff) << 16)
|((height-((border_offset<<3)+1))&0x3fff));
DI_Wr(DNR_DM_CTRL, Rd(DNR_DM_CTRL)|(1 << 11));
- /*DI_Wr_reg_bits(DNR_CTRL, dnr_en?1:0, 16, 1);*/
+ DI_Wr_reg_bits(DNR_CTRL, dnr_en ? 1 : 0, 16, 1);
/* dm for sd, hd will slower */
if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D) ||
(cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)))//from vlsi feijun
- DI_Wr(DNR_CTRL, dnr_cfg(0x1df00 | (0x03 << 18))); //5 line
+ DI_Wr(DNR_CTRL, 0x1df00 | (0x03 << 18)); //5 line
else
- DI_Wr(DNR_CTRL, dnr_cfg(0x1df00));
- if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() ||
+ DI_Wr(DNR_CTRL, 0x1df00);
+
+ if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
+ if (width > 1280)
+ DI_Wr_reg_bits(DNR_DM_CTRL, 0, 8, 1);
+ else
+ DI_Wr_reg_bits(DNR_DM_CTRL, 1, 8, 1);
+ if (width > 1920 || !dnr_dm_en)
+ DI_Wr_reg_bits(DNR_DM_CTRL, 0, 9, 1);
+ else
+ DI_Wr_reg_bits(DNR_DM_CTRL, 1, 9, 1);
+ } else if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu() || is_meson_sm1_cpu()) {
/* disable chroma dm according to baozheng */
- DI_Wr_reg_bits(DNR_DM_CTRL, dm_mp(DM_CHRMEN), 8, 1);
- /* dm en */
- DI_Wr_reg_bits(DNR_DM_CTRL, dm_mp(DM_EN), 9, 1);
-
- DI_Wr(DNR_CTRL, dnr_cfg(0x1dd00));
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
+ DI_Wr_reg_bits(DNR_DM_CTRL, 0, 8, 1);
+ DI_Wr(DNR_CTRL, 0x1dd00);
+ } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX) ||
+ is_meson_gxl_cpu()) {
/*disable */
if (width > 1280) {
DI_Wr_reg_bits(DNR_DM_CTRL, 0, 8, 1);
/* disable dm for 1080 which will cause pre timeout*/
DI_Wr_reg_bits(DNR_DM_CTRL, 0, 9, 1);
} else {
- DI_Wr_reg_bits(DNR_DM_CTRL, dm_mp(DM_CHRMEN), 8, 1);
- DI_Wr_reg_bits(DNR_DM_CTRL, dm_mp(DM_EN), 9, 1);
+ DI_Wr_reg_bits(DNR_DM_CTRL, 1, 8, 1);
+ DI_Wr_reg_bits(DNR_DM_CTRL, dnr_dm_en, 9, 1);
}
} else {
if (width >= 1920)
DI_Wr_reg_bits(DNR_DM_CTRL, 0, 9, 1);
else
- DI_Wr_reg_bits(DNR_DM_CTRL, dm_mp(DM_EN), 9, 1);
+ DI_Wr_reg_bits(DNR_DM_CTRL, dnr_dm_en, 9, 1);
}
}
static void nr4_config(struct NR4_PARM_s *nr4_parm_p,
if (is_meson_txlx_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D) ||
cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) {
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 2, 1);
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 15, 1);
pcue_parm->frame_count = 8;
pcue_parm->field_count1 = 8;
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) {
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5D)) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5))) {
if (field_type != VIDTYPE_PROGRESSIVE) {
DI_Wr_reg_bits(NR2_CUE_PRG_DIF, 0, 20, 1);
DI_Wr_reg_bits(NR4_TOP_CTRL, 0, 1, 1);
if (is_meson_txlx_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D) ||
cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) {
linebuffer_config(width);
nr4_config(nr_param.pnr4_parm, width, height);
linebuffer_config(width);
}
+bool secam_cfr_en = true;
+unsigned int cfr_phase1 = 1;/*0x179c[6]*/
+unsigned int cfr_phase2 = 1;/*0x179c[7]*/
+unsigned int gb_flg = 1;/*1:top, 0:bot*/
+
+static ssize_t
+secam_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf + len,
+ "secam_cfr_en %u, gb_flg %u, cfr_phase2 %u.\n",
+ secam_cfr_en, gb_flg, cfr_phase2);
+ return len;
+}
+
+static ssize_t
+secam_store(struct device *dev, struct device_attribute *attr, const char *buf,
+ size_t count)
+{
+ char *parm[3] = { NULL }, *buf_orig;
+ long val;
+ ssize_t ret_ext = count;
+
+ if (!buf)
+ return count;
+ buf_orig = kstrdup(buf, GFP_KERNEL);
+ parse_cmd_params(buf_orig, (char **)(&parm));
+
+ if (!parm[2]) {
+ ret_ext = -EINVAL;
+ pr_info("miss param!!\n");
+ } else {
+ if (kstrtol(parm[0], 10, &val) == 0)
+ secam_cfr_en = val;
+ if (kstrtol(parm[1], 10, &val) == 0)
+ gb_flg = val;
+ if (kstrtol(parm[2], 10, &val) == 0)
+ cfr_phase2 = val;
+ }
+
+ kfree(buf_orig);
+
+ return ret_ext;
+}
+static DEVICE_ATTR(secam, 0664, secam_show, secam_store);
+
+static void secam_cfr_fun(int top)
+{
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
+ DI_Wr_reg_bits(NR4_TOP_CTRL, 1, 12, 1);/*set cfr_en:1*/
+ else
+ DI_Wr_reg_bits(NR2_SW_EN, 1, 7, 1);/*set cfr_en:1*/
+ DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, 1, 2, 2);
+ DI_Wr_reg_bits(NR2_CFR_PARA_CFG1, 0x208020, 0, 24);
+ if (((gb_flg == 0) && top) || ((gb_flg == 1) && (!top))) {
+ cfr_phase1 = ~cfr_phase1;
+ DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, cfr_phase1, 6, 1);
+ }
+ DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, cfr_phase2, 7, 1);
+}
+
+void secam_cfr_adjust(unsigned int sig_fmt, unsigned int frame_type)
+{
+ if (sig_fmt == TVIN_SIG_FMT_CVBS_SECAM && secam_cfr_en) {
+ secam_cfr_fun((frame_type & VIDTYPE_TYPEMASK) ==
+ VIDTYPE_INTERLACE_TOP);
+ } else {
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
+ DI_Wr_reg_bits(NR4_TOP_CTRL, 0, 12, 1);/*set cfr_en:0*/
+ else
+ DI_Wr_reg_bits(NR2_SW_EN, 0, 7, 1);/*set cfr_en:0*/
+ DI_Wr_reg_bits(NR2_CFR_PARA_CFG0, 2, 2, 2);
+ }
+}
+
static int find_lut16(unsigned int val, int *pLut)
{
int idx_L, shft, dist;
#endif
int ll, lr;
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
+ if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
ll = Rd(DNR_RO_GBS_STAT_LR);
lr = Rd(DNR_RO_GBS_STAT_LL);
} else {
}
if (!nr_param.prog_flag) {
if (nr_param.frame_count > 1 && cue_glb_mot_check_en) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2))
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5D)) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5)))
DI_Wr_reg_bits(NR4_TOP_CTRL,
cue_en ? 1 : 0, 1, 1);
else
DI_Wr_reg_bits(DI_NR_CTRL0,
cue_en ? 1 : 0, 26, 1);
/*confirm with vlsi,fix jira SWPL-31571*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2))
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5D)) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5)))
DI_Wr_reg_bits(MCDI_CTRL_MODE,
(!cue_en) ? 1 : 0, 16, 1);
}
}
/*close cue when cue disable*/
if (!cue_en) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2))
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5D)) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5)))
DI_Wr_reg_bits(NR4_TOP_CTRL, 0, 1, 1);
else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
DI_Wr_reg_bits(DI_NR_CTRL0, 0, 26, 1);
return;
//if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) {
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_SC2) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5D)) &&
+ (!IS_IC(dil_get_cpuver_flag(), T5))) {
/*value from VLSI(yanling.liu)*/
/*after SC2 need new setting 2020-08-04: */
mask1 = 0x50362;
for (i = 0; i < pnr_regs->reg_num; i++) {
if (atomic_read(&pnr_regs->regs[i].load_flag)) {
+ if (pnr_regs->regs[i].addr == DNR_DM_CTRL)
+ pnr_regs->regs[i].value = check_dnr_dm_ctrl
+ (pnr_regs->regs[i].value,
+ nr_param.width,
+ nr_param.height);
DI_Wr(pnr_regs->regs[i].addr,
pnr_regs->regs[i].value);
atomic_set(&pnr_regs->regs[i].load_flag, 0);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX) &&
cue_glb_mot_check_en)
cue_process_irq();
- if (dnr_mp(DNR_M_DNR))
+ if (dnr_en)
dnr_process(&dnr_param);
if (is_meson_txlx_cpu() || is_meson_g12a_cpu()
|| is_meson_g12a_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D) ||
cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)) {
noise_meter_process(nr_param.pnr4_parm, nr_param.frame_count);
luma_enhancement_process(nr_param.pnr4_parm,
nr_param.frame_count);
}
}
-static void parse_cmd_params(char *buf_orig, char **parm)
-{
- char *ps, *token;
- char delim1[3] = " ";
- char delim2[2] = "\n";
- unsigned int n = 0;
-
- ps = buf_orig;
- strcat(delim1, delim2);
- while (1) {
- token = strsep(&ps, delim1);
- if (token == NULL)
- break;
- if (*token == '\0')
- continue;
- parm[n++] = token;
- }
-}
static dnr_param_t dnr_params[] = {
{"prm_sw_gbs_ctrl", &(dnr_param.prm_sw_gbs_ctrl)},
return len;
}
-
static DEVICE_ATTR(nr_debug, 0664, nr_dbg_show, nr_dbg_store);
void nr_hw_init(void)
{
nr_gate_control(true);
-
- if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() || is_meson_sm1_cpu())
- dnr_en = 0xd;
- else
- dnr_en = 0x0f;
-
if (is_meson_tl1_cpu() || is_meson_tm2_cpu() ||
+ IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D) ||
(cpu_after_eq(MESON_CPU_MAJOR_ID_SC2)))
- DI_Wr(DNR_CTRL, dnr_cfg(0x1df00|(0x03<<18)));//5 line
+ DI_Wr(DNR_CTRL, 0x1df00 | (0x03 << 18));//5 line
else
- DI_Wr(DNR_CTRL, dnr_cfg(0x1df00));
-
- /* dm */
- if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() || is_meson_sm1_cpu()) {
- /* disable chroma dm according to baozheng */
- dnr_dm_en = 0x1;
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
- dnr_dm_en = 0x3;
-
- } else {
- dnr_dm_en = 0x1;
- }
-
+ DI_Wr(DNR_CTRL, 0x1df00);
DI_Wr(NR3_MODE, 0x3);
DI_Wr(NR3_COOP_PARA, 0x28ff00);
DI_Wr(NR3_CNOOP_GAIN, 0x881900);
}
void nr_gate_control(bool gate)
{
- if (!is_meson_txlx_cpu() && !is_meson_g12a_cpu()
- && !is_meson_g12b_cpu() && !is_meson_sm1_cpu()
- && !is_meson_tl1_cpu() && !is_meson_tm2_cpu())
+ if (!is_meson_txlx_cpu() && !is_meson_g12a_cpu() &&
+ !is_meson_g12b_cpu() && !is_meson_sm1_cpu() &&
+ !is_meson_tl1_cpu() && !is_meson_tm2_cpu() &&
+ !IS_IC(dil_get_cpuver_flag(), T5) &&
+ !IS_IC(dil_get_cpuver_flag(), T5D))
return;
if (gate) {
/* enable nr auto gate */
device_remove_file(dev, &dev_attr_nr4_param);
device_remove_file(dev, &dev_attr_dnr_param);
device_remove_file(dev, &dev_attr_nr_debug);
+ device_remove_file(dev, &dev_attr_secam);
}
void nr_drv_init(struct device *dev)
{
nr_param.pdnr_parm = &dnr_param;
device_create_file(dev, &dev_attr_dnr_param);
device_create_file(dev, &dev_attr_nr_debug);
+ device_create_file(dev, &dev_attr_secam);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXBB))
dnr_dm_en = true;
else
.set_nr_ctrl_reg_table = set_nr_ctrl_reg_table,
.cue_int = cue_int,
.adaptive_cue_adjust = adaptive_cue_adjust,
+ .secam_cfr_adjust = secam_cfr_adjust,
/*.module_para = dim_seq_file_module_para_nr,*/
};
void nr_all_config(unsigned short nCol, unsigned short nRow,
unsigned short type);
bool set_nr_ctrl_reg_table(unsigned int addr, unsigned int value);
+void secam_cfr_adjust(unsigned int sig_fmt, unsigned int frame_type);
extern void cue_int(struct vframe_s *vf);
{ "flm32_en",
&(pd_param.flm32_en) },
{ "flm22_force",
- &(pd_param.flm22_force) },
+ &pd_param.flm22_force },
{ "flm22_flag",
&(pd_param.flm22_flag) },
{ "flm22_avg_flag",
void pd_device_files_del(struct device *dev)
{
- device_remove_file(dev, &dev_attr_pd_param);
+ device_create_file(dev, &dev_attr_pd_param);
}
#ifdef DEBUG_SUPPORT
module_param_named(flm22_sure_num, flm22_sure_num, uint, 0644);
* Bit 27:24, reg_NM_calc_length Length mode of the Noise
* measurement sample number for statistics.
* 0: 256 samples; 1: 512 samples; 2: 1024 samples;
- * ¡X: 2^(8+x) samples
+ * 2^(8+x) samples
* Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
* Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
* Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion
#define NR3_SUREMOT_YGAIN 0x2ff5
#define NR3_SUREMOT_CGAIN 0x2ff6
+/* for tm2-b */
+
+#define DI_RO_PRE_FIELD_CNT0 ((0x17A3))
+#define DI_RO_PRE_FIELD_CNT1 ((0x17A4))
+#define DI_RO_POS_FRAME_CNT0 ((0x17A5))
+#define DI_RO_POS_FRAME_CNT1 ((0x17A6))
+#define DI_INP_AFBC_ENABLE (0x1800)
+#define DI_INP_AFBC_MODE (0x1801)
+#define DI_INP_AFBC_SIZE_IN (0x1802)
+#define DI_INP_AFBC_DEC_DEF_COLOR (0x1803)
+#define DI_INP_AFBC_CONV_CTRL (0x1804)
+#define DI_INP_AFBC_LBUF_DEPTH (0x1805)
+#define DI_INP_AFBC_HEAD_BADDR (0x1806)
+#define DI_INP_AFBC_BODY_BADDR (0x1807)
+#define DI_INP_AFBC_SIZE_OUT (0x1808)
+#define DI_INP_AFBC_OUT_YSCOPE (0x1809)
+#define DI_INP_AFBC_STAT (0x180a)
+#define DI_INP_AFBC_VD_CFMT_CTRL (0x180b)
+#define DI_INP_AFBC_VD_CFMT_W (0x180c)
+#define DI_INP_AFBC_MIF_HOR_SCOPE (0x180d)
+#define DI_INP_AFBC_MIF_VER_SCOPE (0x180e)
+#define DI_INP_AFBC_PIXEL_HOR_SCOPE (0x180f)
+#define DI_INP_AFBC_PIXEL_VER_SCOPE (0x1810)
+#define DI_INP_AFBC_VD_CFMT_H (0x1811)
+
+#define DI_MEM_AFBC_ENABLE (0x1820)
+#define DI_MEM_AFBC_MODE (0x1821)
+#define DI_MEM_AFBC_SIZE_IN (0x1822)
+#define DI_MEM_AFBC_DEC_DEF_COLOR (0x1823)
+#define DI_MEM_AFBC_CONV_CTRL (0x1824)
+#define DI_MEM_AFBC_LBUF_DEPTH (0x1825)
+#define DI_MEM_AFBC_HEAD_BADDR (0x1826)
+#define DI_MEM_AFBC_BODY_BADDR (0x1827)
+#define DI_MEM_AFBC_SIZE_OUT (0x1828)
+#define DI_MEM_AFBC_OUT_YSCOPE (0x1829)
+#define DI_MEM_AFBC_STAT (0x182a)
+#define DI_MEM_AFBC_VD_CFMT_CTRL (0x182b)
+#define DI_MEM_AFBC_VD_CFMT_W (0x182c)
+#define DI_MEM_AFBC_MIF_HOR_SCOPE (0x182d)
+#define DI_MEM_AFBC_MIF_VER_SCOPE (0x182e)
+#define DI_MEM_AFBC_PIXEL_HOR_SCOPE (0x182f)
+#define DI_MEM_AFBC_PIXEL_VER_SCOPE (0x1830)
+#define DI_MEM_AFBC_VD_CFMT_H (0x1831)
+
+#define DI_AFBCE_CTRL (0x2003)
+/*
+ * bit[0]: nrwr_sel: 1: nr channel 0 to afbce; 0:nr channel 0 to normal mif
+ * bit[4]: nr_en: important! 1:enable nr write to DDR;
+ * bit[10]:inp_afbc0_sel:0:normal mif; 1:afbc dec0;
+ * bit[11]:inp_data_sel:0:normal sel; 1:afbc dec0;
+ * bit[12]:mem_afbc1_sel:0:normal mif; 1:afbc dec1;
+ * bit[13]:mem_data_sel:0:normal mif; 1:afbc dec1
+ */
+#define DI_AFBCE_ENABLE (0x2060)
+#define DI_AFBCE_MODE (0x2061)
+#define DI_AFBCE_SIZE_IN (0x2062)
+#define DI_AFBCE_BLK_SIZE_IN (0x2063)
+#define DI_AFBCE_HEAD_BADDR (0x2064)
+#define DI_AFBCE_MIF_SIZE (0x2065)
+#define DI_AFBCE_PIXEL_IN_HOR_SCOPE (0x2066)
+#define DI_AFBCE_PIXEL_IN_VER_SCOPE (0x2067)
+#define DI_AFBCE_CONV_CTRL (0x2068)
+#define DI_AFBCE_MIF_HOR_SCOPE (0x2069)
+#define DI_AFBCE_MIF_VER_SCOPE (0x206a)
+#define DI_AFBCE_STAT1 (0x206b)
+#define DI_AFBCE_STAT2 (0x206c)
+#define DI_AFBCE_FORMAT (0x206d)
+#define DI_AFBCE_MODE_EN (0x206e)
+#define DI_AFBCE_DWSCALAR (0x206f)
+#define DI_AFBCE_DEFCOLOR_1 (0x2070)
+#define DI_AFBCE_DEFCOLOR_2 (0x2071)
+#define DI_AFBCE_QUANT_ENABLE (0x2072)
+#define DI_AFBCE_IQUANT_LUT_1 (0x2073)
+#define DI_AFBCE_IQUANT_LUT_2 (0x2074)
+#define DI_AFBCE_IQUANT_LUT_3 (0x2075)
+#define DI_AFBCE_IQUANT_LUT_4 (0x2076)
+#define DI_AFBCE_RQUANT_LUT_1 (0x2077)
+#define DI_AFBCE_RQUANT_LUT_2 (0x2078)
+#define DI_AFBCE_RQUANT_LUT_3 (0x2079)
+#define DI_AFBCE_RQUANT_LUT_4 (0x207a)
+#define DI_AFBCE_YUV_FORMAT_CONV_MODE (0x207b)
+#define DI_AFBCE_DUMMY_DATA (0x207c)
+#define DI_AFBCE_CLR_FLAG (0x207d)
+#define DI_AFBCE_STA_FLAGT (0x207e)
+#define DI_AFBCE_MMU_NUM (0x207f) /*read only*/
+#define DI_AFBCE_MMU_RMIF_CTRL1 (0x2080)
+#define DI_AFBCE_MMU_RMIF_CTRL2 (0x2081)
+#define DI_AFBCE_MMU_RMIF_CTRL3 (0x2082)
+#define DI_AFBCE_MMU_RMIF_CTRL4 (0x2083)
+#define DI_AFBCE_MMU_RMIF_SCOPE_X (0x2084)
+#define DI_AFBCE_MMU_RMIF_SCOPE_Y (0x2085)
+#define DI_AFBCE_MMU_RMIF_RO_STAT (0x2086)
+
+/* for TM2-B DI FILM_GRAIN */
+
+#define DI_FGRAIN_CTRL 0x1840
+#define DI_FGRAIN_WIN_H 0x1841
+#define DI_FGRAIN_WIN_V 0x1842
+
#endif
dim-objs += di_api.o
dim-objs += di_que_buf.o
dim-objs += di_decont.o
+dim-objs += di_mmu_box.o
+dim-objs += di_mem_scatter.o
dim-objs += dolby_sys.o
+dim-objs += di_interface.o
#dim-objs += di_hw_v2.o
dim-objs += sc2/di_hw_v3.o
dim-objs += sc2/di_afbc_v3.o
#include "di_data_l.h"
#include "deinterlace_hw.h"
#include "sc2/di_hw_v3.h"
+#include "sc2/di_afbc_v3.h"
#include "di_dbg.h"
#include "di_pps.h"
#ifdef DET3D
#include "detect3d.h"
#endif
-#define ENABLE_SPIN_LOCK_ALWAYS
+//#define ENABLE_SPIN_LOCK_ALWAYS
static DEFINE_SPINLOCK(di_lock2);
#define di_unlock_irqfiq_restore(irq_flag) \
spin_unlock_irqrestore(&di_lock2, irq_flag)
+void di_lock_irq(void)
+{
+ spin_lock(&di_lock2);
+}
+
+void di_unlock_irq(void)
+{
+ spin_unlock(&di_lock2);
+}
#ifdef SUPPORT_MPEG_TO_VDIN
static int mpeg2vdin_flag;
static int kpi_frame_num;// default print first coming n frames
+int di_get_kpi_frame_num(void)
+{
+ return kpi_frame_num;
+}
/**************************************
*
*
*************************************/
+ //move to di_prc.c
+#ifdef MARK_HIS
unsigned int di_dbg = DBG_M_EVENT;
module_param(di_dbg, uint, 0664);
MODULE_PARM_DESC(di_dbg, "debug print");
+#endif
/* destroy unnecessary frames before display */
static unsigned int hold_video;
*/
static struct queue_s *get_queue_by_idx(unsigned int channel, int idx);
-static void dump_state(unsigned int channel);
+//static void dump_state(unsigned int channel);
//static void recycle_keep_buffer(unsigned int channel);
#define DI_PRE_INTERVAL (HZ / 100)
int pre_run_flag = DI_RUN_FLAG_RUN;
static int dump_state_flag;
+int dump_state_flag_get(void)
+{
+ return dump_state_flag;
+}
const struct afd_ops_s *dim_afds(void)
{
return get_datal()->afds;
return count;
dim_dump_pool(get_queue_by_idx(channel, idx));
} else if (strncmp(buf, "state", 4) == 0) {
- dump_state(channel);
+ //dump_state(channel);
pr_info("add new debugfs: cat /sys/kernel/debug/di/state\n");
} else if (strncmp(buf, "prog_proc_config", 16) == 0) {
if (buf[16] == '1')
static unsigned int di_log_rd_pos;
static unsigned int di_log_buf_size;
-static unsigned int buf_state_log_start;
+//static unsigned int buf_state_log_start;
/* set to 1 by condition of "post_ready count < buf_state_log_threshold",
* reset to 0 by set buf_state_log_threshold as 0
*/
ssize_t
store_kpi_frame_num(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len)
+ const char *buf, size_t len)
{
unsigned long num;
int ret = kstrtoul(buf, 0, (unsigned long *)&num);
void di_set_default(unsigned int ch)
{
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
// enum EDI_SGN sgn;
// struct di_pre_stru_s *ppre = get_pre_stru(ch);
void dbg_h_w(unsigned int ch, unsigned int nub)
{
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
mm = dim_mm_get(ch);
dbg_reg("%s:ch[%d][%d]:h[%d],w[%d]\n", __func__,
bool bflg_vmap = false;
unsigned int channel = get_current_channel();/* debug only*/
struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = get_dim_de_devp();
+// struct di_dev_s *de_devp = get_dim_de_devp();
/*ary add 2019-07-2 being*/
unsigned int indx;
struct di_buf_s *pbuf_post;
struct di_buf_s *pbuf_local;
struct di_post_stru_s *ppost;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
+ struct di_ch_s *pch;
+ unsigned int sh, sv;
/*************************/
+ pch = get_chdata(channel);
buf_orig = kstrdup(buf, GFP_KERNEL);
ps = buf_orig;
pbuf_local = get_buf_local(channel);
di_buf = &pbuf_local[indx];
} else if (strcmp(parm[0], "capture_pready") == 0) { /*ary add*/
-
+ #ifdef MARK_HIS
if (!di_que_is_empty(channel, QUE_POST_READY)) {
di_buf = di_que_peek(channel, QUE_POST_READY);
pr_info("get post ready di_buf:%d:0x%p\n",
} else {
pr_info("war:no post ready buf\n");
}
+ #else
+ di_buf = ndrd_qpeekbuf(pch);
+ if (di_buf)
+ pr_info("get post ready di_buf:%d:0x%p\n",
+ di_buf->index, di_buf);
+ else
+ pr_info("war:no post ready buf\n");
+
+ #endif
} else if (strcmp(parm[0], "capture_post") == 0) {
if (di_vf_l_peek(channel)) {
post_vf = di_vf_l_get(channel);
}
canvas_w = di_buf->canvas_width[NR_CANVAS];
canvas_h = di_buf->canvas_height;
- nr_size = canvas_w * canvas_h * 2;
+ //nr_size = canvas_w * canvas_h * 2;
dump_adr = di_buf->nr_adr;
+ sh = di_buf->vframe->canvas0_config[0].width;
+ sv = di_buf->vframe->canvas0_config[0].height;
+ nr_size = sh * sv;
+
+ if (di_buf->vframe->plane_num == 2)
+ nr_size = nr_size * 2;
pr_info("w=%d,h=%d,size=%ld,addr=%lx\n",
canvas_w, canvas_h, nr_size, dump_adr);
return len;
}
dump_state_flag = 1;
- if (de_devp->flags & DI_MAP_FLAG) {
+ if (/*de_devp->flags & DI_MAP_FLAG*/ 1) {
/*buff = (void *)phys_to_virt(dump_adr);*/
buff = dim_vmap(dump_adr, nr_size, &bflg_vmap);
if (!buff) {
return len;
}
}
+ pr_info("wr buffer 0x%lx to %s.\n", dump_adr, parm[1]);
+ pr_info("size:0x%lx, bflg_vmap[%d]\n", nr_size, bflg_vmap);
} else {
buff = ioremap(dump_adr, nr_size);
}
pr_info("write buffer 0x%lx to %s.\n", dump_adr, parm[1]);
if (bflg_vmap)
dim_unmap_phyaddr(buff);
-
+#ifdef MARK_HIS
if (!(de_devp->flags & DI_MAP_FLAG))
iounmap(buff);
+#endif
dump_state_flag = 0;
filp_close(filp, NULL);
set_fs(old_fs);
static void dis2_di(void)
{
- ulong flags = 0, irq_flag2 = 0;
+//ary 2020-12-09 ulong flags = 0, irq_flag2 = 0;
unsigned int channel = get_current_channel();/* debug only*/
struct vframe_s **pvframe_in = get_vframe_in(channel);
struct di_pre_stru_s *ppre = get_pre_stru(channel);
set_init_flag(channel, false);/*init_flag = 0;*/
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
/* vf_unreg_provider(&di_vf_prov); */
pw_vf_light_unreg_provider(channel);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
set_reg_flag(channel, false);
- spin_lock_irqsave(&plist_lock, flags);
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
if (ppre->di_inp_buf) {
if (pvframe_in[ppre->di_inp_buf->index]) {
pw_vf_put(pvframe_in[ppre->di_inp_buf->index],
if (dimp_get(edi_mp_post_wr_en) && dimp_get(edi_mp_post_wr_support))
dim_set_power_control(0);
- di_unlock_irqfiq_restore(irq_flag2);
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
}
ssize_t
static unsigned char is_source_change(vframe_t *vframe, unsigned int channel)
{
struct di_pre_stru_s *ppre = get_pre_stru(channel);
+ unsigned int x, y;
+ dim_vf_x_y(vframe, &x, &y);
#define VFRAME_FORMAT_MASK \
(VIDTYPE_VIU_422 | VIDTYPE_VIU_SINGLE_PLANE | VIDTYPE_VIU_444 | \
VIDTYPE_MVC)
- if (ppre->cur_width != vframe->width ||
- ppre->cur_height != vframe->height ||
+ if (ppre->cur_width != x ||
+ ppre->cur_height != y ||
(((ppre->cur_inp_type & VFRAME_FORMAT_MASK) !=
(vframe->type & VFRAME_FORMAT_MASK)) &&
(!is_handle_prog_frame_as_interlace(vframe))) ||
// unsigned int vtype = 0;
struct di_pre_stru_s *ppre = get_pre_stru(ch);
unsigned int reason = 0;
+ struct di_ch_s *pch;
/*need bypass*/
reason = dim_bypass_check(vf_in);
if (reason)
return reason;
+ pch = get_chdata(ch);
if (dimp_get(edi_mp_bypass_trick_mode)) {
int trick_mode_fffb = 0;
int trick_mode_i = 0;
reason = 0x88;
}
+ if (!reason && pch->rsc_bypass.d32)
+ reason = 0x89;
+
+ if (!reason &&
+ vf_in &&
+ pch->ponly &&
+ IS_I_SRC(vf_in->type)) {
+ reason = 0x8a;
+ //PR_INF("%s:bypass for p only\n", __func__);
+ }
return reason;
}
height = 1088;
if (dim_afds() && dim_afds()->cnt_info_size &&
- (cfgg(DAT) & DI_BIT1)) {
+ (cfggch(pch, DAT) & DI_BIT1)) {
afbc_info_size = dim_afds()->cnt_info_size(width,
height / 2,
&blk_total);
unsigned int nr_canvas_width = width, mtn_canvas_width = width;
unsigned int mv_canvas_width = width, canvas_align_width = 32;
unsigned int afbc_buffer_size = 0, blk_total = 0;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
unsigned int afbc_info_size = 0, afbc_tab_size = 0, old_size;
//unsigned int insert_line = 544;
}
if (dim_afds() && dim_afds()->cnt_tab_size &&
- (dim_afds()->is_sts(EAFBC_MEM_NEED) || cfgg(FIX_BUF)))
+ (dim_afds()->is_sts(EAFBC_MEMI_NEED) || cfgg(FIX_BUF)))
afbc_tab_size = dim_afds()->cnt_tab_size(nr_size);
mtn_size = (mtn_width * canvas_height) * 4 / 16;
insert_size = insert_line * nr_canvas_width;
di_buf_size = nr_size;
- if (mc_mem_alloc) {
+ if (mc_mem_alloc) {
di_buf_size += mtn_size +
count_size +
mv_size +
//one_idat_size = 0;
}
mm->cfg.afbct_local_max_size = di_cnt_pre_afbct(pch);
+ mm->cfg.ibuf_hsize = width;
one_idat_size += mm->cfg.afbct_local_max_size;
old_size = nr_size;
mm->cfg.canvas_width[MTN_CANVAS] = mtn_canvas_width;
mm->cfg.canvas_width[MV_CANVAS] = mv_canvas_width;
mm->cfg.canvas_height = (canvas_height >> 1);
- mm->cfg.canvas_height_mc = roundup(mm->cfg.canvas_height,
- canvas_align_width);
+ mm->cfg.canvas_height_mc = roundup(mm->cfg.canvas_height,
+ canvas_align_width);
dbg_mem2("\t%-15s:0x%x\n", "canvas_height_mc",
mm->cfg.canvas_height_mc);
unsigned int afbc_buffer_size = 0, afbc_tab_size = 0;
unsigned int afbc_info_size = 0, blk_total = 0, tsize;
bool flg_afbc = false;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
if (!pch)
return;
//if (cfgg(4K))
is_4k = true;
- pcfg = di_get_mm_tab(is_4k);
+ pcfg = di_get_mm_tab(is_4k, pch);
width = pcfg->di_w;
height = pcfg->di_h;
afbc_info_size = dim_afds()->cnt_info_size(width,
- height,
- &blk_total);
+ height,
+ &blk_total);
afbc_buffer_size =
dim_afds()->cnt_buf_size(0x21, blk_total);
afbc_buffer_size = roundup(afbc_buffer_size, PAGE_SIZE);
mm->cfg.dat_pafbct_flg.b.page = mm->cfg.size_pafbct_all >> PAGE_SHIFT;
mm->cfg.dat_pafbci_flg.b.tvp = 0;
dbg_mem2("%s:size_pafbct_all:0x%x, 0x%x, nub[%d]\n",
- __func__,
- mm->cfg.size_pafbct_all,
- mm->cfg.size_pafbct_one,
- mm->cfg.nub_pafbct);
+ __func__,
+ mm->cfg.size_pafbct_all,
+ mm->cfg.size_pafbct_one,
+ mm->cfg.nub_pafbct);
#endif
}
static int di_cnt_post_buf(struct di_ch_s *pch /*,enum EDPST_OUT_MODE mode*/)
{
unsigned int ch;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int nr_width, nr_canvas_width, canvas_align_width = 32;
unsigned int height, width;
unsigned int tmpa, tmpb;
unsigned int afbc_buffer_size = 0, blk_total = 0;
enum EDPST_MODE mode;
bool is_4k = false;
+ bool is_yuv420_10 = false;
ch = pch->ch_id;
mm = dim_mm_get(ch);
width = mm->cfg.di_w;
if (mm->cfg.di_w > 1920)
is_4k = true;
+ mm->cfg.pbuf_hsize = width;
nr_width = width;
- dbg_mem2("di_cnt_post_buf w[%d]h[%d]\n", width, height);
+ dbg_mem2("%s w[%d]h[%d]\n", __func__, width, height);
nr_canvas_width = width;
/**********************************************/
/* count buf info */
#else
mode = pch->mode;
if (is_4k &&
- ((cfgg(POUT_FMT) == 1) ||
- (cfgg(POUT_FMT) == 2) ||
- (cfgg(POUT_FMT) == 5)))
+ ((cfggch(pch, POUT_FMT) == 1) ||
+ (cfggch(pch, POUT_FMT) == 2) ||
+ (cfggch(pch, POUT_FMT) == 5)))
mode = EDPST_MODE_NV21_8BIT;
- dbg_mem2("di_cnt_post_buf:mode:%d\n", mode);
+ dbg_mem2("%s:mode:%d\n", __func__, mode);
#endif
/***********************/
if (mode == EDPST_MODE_422_10BIT_PACK)
nr_width = width;
/* p */
- nr_width = roundup(nr_width, canvas_align_width);
+ //tmp nr_width = roundup(nr_width, canvas_align_width);
mm->cfg.pst_mode = mode;
if (mode == EDPST_MODE_NV21_8BIT) {
+ nr_width = roundup(nr_width, canvas_align_width);
tmpa = (nr_width * canvas_height) >> 1;/*uv*/
tmpb = tmpa;
tmpa = nr_width * canvas_height;
dim_afds()->cnt_info_size(width,
height,
&blk_total);
- afbc_buffer_size =
- dim_afds()->cnt_buf_size(0x21, blk_total);
+ if (is_4k && dip_is_support_nv2110(ch))
+ is_yuv420_10 = true;
+
+ if (is_yuv420_10)
+ afbc_buffer_size =
+ dim_afds()->cnt_buf_size(0x20, blk_total);
+ else
+ afbc_buffer_size =
+ dim_afds()->cnt_buf_size(0x21,
+ blk_total);
afbc_buffer_size = roundup(afbc_buffer_size, PAGE_SIZE);
if (afbc_buffer_size > mm->cfg.pst_buf_size) {
PR_INF("%s:0x%x, 0x%x\n", "buf large:",
afbc_buffer_size);
mm->cfg.pst_buf_size = afbc_buffer_size;
}
+
+ if (is_yuv420_10)
+ mm->cfg.pst_buf_size = afbc_buffer_size;
+
afbc_tab_size =
dim_afds()->cnt_tab_size(mm->cfg.pst_buf_size);
}
mm->cfg.pst_afbct_size = afbc_tab_size;
#ifdef CFG_BUF_ALLOC_SP
- mm->cfg.size_post = mm->cfg.pst_buf_size +
+ if (is_4k && dip_is_4k_sct_mem(pch)) {
+ mm->cfg.size_post = mm->cfg.pst_afbci_size;
+ } else if (pch->ponly && dip_is_ponly_sct_mem(pch)) {
+ mm->cfg.size_post = mm->cfg.pst_afbci_size;
+ } else if (dip_itf_is_ins_exbuf(pch)) {
+ mm->cfg.size_post = mm->cfg.pst_afbci_size;
+ } else {
+ mm->cfg.size_post = mm->cfg.pst_buf_size +
mm->cfg.pst_afbci_size;
+ }
#else
mm->cfg.size_post = mm->cfg.pst_buf_size +
mm->cfg.pst_afbci_size + mm->cfg.pst_afbct_size;
#endif
mm->cfg.pst_cvs_w = nr_width << 1;
+ mm->cfg.pst_cvs_w = roundup(mm->cfg.pst_cvs_w,
+ canvas_align_width);
mm->cfg.pst_cvs_h = canvas_height;
}
mm->cfg.size_post = roundup(mm->cfg.size_post, PAGE_SIZE);
else
mm->cfg.pbuf_flg.b.dw = 0;
- mm->cfg.pbuf_flg.b.typ = EDIM_BLK_TYP_OLDP;
+ if (is_4k && dip_is_4k_sct_mem(pch))
+ mm->cfg.pbuf_flg.b.typ = EDIM_BLK_TYP_PSCT;
+ else if (pch->ponly && dip_is_ponly_sct_mem(pch))
+ mm->cfg.pbuf_flg.b.typ = EDIM_BLK_TYP_PSCT;
+ else
+ mm->cfg.pbuf_flg.b.typ = EDIM_BLK_TYP_OLDP;
+
+ if (dip_itf_is_ins_exbuf(pch))
+ mm->cfg.pbuf_flg.b.typ |= EDIM_BLK_TYP_POUT;
+
+ dbg_mem2("%s:3 pst_cvs_w[%d]\n", __func__, mm->cfg.pst_cvs_w);
#ifdef PRINT_BASIC
dbg_mem2("%s:size:\n", __func__);
dbg_mem2("\t%-15s:0x%x\n", "total_size", mm->cfg.size_post);
struct di_buf_s *pbuf_post;
struct di_buf_s *di_buf;
- struct di_mm_s *mm; /*mm-0705*/
+ struct div2_mm_s *mm; /*mm-0705*/
unsigned int cnt;
unsigned int ch;
di_buf = &pbuf_post[i];
if (di_buf) {
+#ifdef MARK_HIS
if (dimp_get(edi_mp_post_wr_en) &&
dimp_get(edi_mp_post_wr_support)) {
if (di_que_is_in_que(ch, QUE_POST_KEEP,
continue;
}
}
-
+#endif
memset(di_buf, 0, sizeof(struct di_buf_s));
di_buf->type = VFRAME_TYPE_POST;
static void check_tvp_state(struct di_ch_s *pch)
{
+#ifdef TMP_TEST /* for ko only */
+ set_flag_tvp(pch->ch_id, 1);
+#else
unsigned int ch;
-
struct provider_state_req_s req;
- char *provider_name = vf_get_provider_name(pch->vfm.name);
+ char *provider_name;// = vf_get_provider_name(pch->vfm.name);
ch = pch->ch_id;
+ if (!dip_itf_is_vfm(pch)) {
+ set_flag_secure_pre(ch, 0);
+ set_flag_secure_pst(ch, 0);
+ if (pch->itf.u.dinst.parm.output_format & DI_OUTPUT_TVP)
+ set_flag_tvp(pch->ch_id, 2);
+ else
+ set_flag_tvp(pch->ch_id, 1);
+ return;
+ }
+
set_flag_tvp(ch, 0);
set_flag_secure_pre(ch, 0);
set_flag_secure_pst(ch, 0);
+ provider_name = vf_get_provider_name(pch->itf.dvfm.name);
while (provider_name) {
if (!vf_get_provider_name(provider_name))
req.vf = NULL;
req.req_type = REQ_STATE_SECURE;
req.req_result[0] = 0xffffffff;
- vf_notify_provider_by_name(
- provider_name,
- VFRAME_EVENT_RECEIVER_REQ_STATE,
- (void *)&req);
+ vf_notify_provider_by_name
+ (provider_name,
+ VFRAME_EVENT_RECEIVER_REQ_STATE,
+ (void *)&req);
if (req.req_result[0] == 0)
set_flag_tvp(ch, 1);
else if (req.req_result[0] != 0xffffffff)
set_flag_tvp(ch, 1);
}
dbg_mem2("%s:tvp2:%d\n", __func__, get_flag_tvp(ch));
+#endif
}
static int di_init_buf_new(struct di_ch_s *pch)
{
struct mtsk_cmd_s blk_cmd;
//struct di_dev_s *de_devp = get_dim_de_devp();
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
unsigned int length_keep;
// struct di_dat_s *pdat;
di_cnt_post_buf(pch);
di_init_buf_simple(pch);
- length_keep = di_que_list_count(ch, QUE_POST_KEEP);
+ length_keep = ndis_cnt(pch, QBF_NDIS_Q_KEEP);
+ //di_que_list_count(ch, QUE_POST_KEEP);
if (cfgeq(MEM_FLAG, EDI_MEM_M_CMA) ||
cfgeq(MEM_FLAG, EDI_MEM_M_CODEC_A) ||
cfgeq(MEM_FLAG, EDI_MEM_M_CODEC_B)) { /*trig cma alloc*/
blk_cmd.cmd = ECMD_BLK_ALLOC;
-
#ifdef MARK_HIS
/*pre idat*/
if (!pch->rse_ori.dat_i.blk_buf) {
dbg_mem2("%s:send alloc afbct cmd\n", __func__);
} else {
dbg_mem2("%s:not afbct %d,%d\n", __func__,
- (!pdat->flg_alloc),
- mm->cfg.dat_pafbct_flg.d32);
+ (!pdat->flg_alloc),
+ mm->cfg.dat_pafbct_flg.d32);
}
#endif
#endif
blk_cmd.nub = mm->cfg.num_post - length_keep;
blk_cmd.flg.d32 = mm->cfg.pbuf_flg.d32;
- mtask_send_cmd(ch, &blk_cmd);
+ if (mm->cfg.pbuf_flg.b.page) {//@ary_note: ??
+ mtask_send_cmd(ch, &blk_cmd);
+ } else if ((mm->cfg.pbuf_flg.b.typ & 0x8) ==
+ EDIM_BLK_TYP_POUT) {
+ //move all to wait:
+ di_buf_no2wait(pch);
+ }
}
return 0;
}
struct di_buf_s *keep_buf = ppost->keep_buf;
struct di_dev_s *de_devp = get_dim_de_devp();
/* struct di_buf_s *keep_buf_post = ppost->keep_buf_post;*/
- struct di_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
+ struct div2_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
unsigned int mem_st_local;
unsigned int afbc_info_size = 0, afbc_tab_size = 0, old_size;
di_buf->canvas_height_mc = canvas_height;
if (cfgeq(MEM_FLAG, EDI_MEM_M_REV) ||
cfgeq(MEM_FLAG, EDI_MEM_M_CMA_ALL)) {
- di_buf->nr_adr = mem_st_local +
- di_buf_size * i;
+ di_buf->nr_adr = mem_st_local +
+ di_buf_size * i;
}
di_buf->canvas_config_flag = 1;
} else {
}
#endif
+#ifdef MARK_HIS/* @ary_note: no used */
void dim_post_keep_mirror_buffer(unsigned int channel)
{
struct di_buf_s *p = NULL;
ppost->keep_buf_post->invert_top_bot_flag = 0;
}
}
+#endif
+#ifdef MARK_HIS
void dim_post_keep_mirror_buffer2(unsigned int ch)
{
struct di_buf_s *p = NULL;
dbg_keep("%s %d\n", __func__, p->index);
}
}
+#endif
+#ifdef MARK_HIS
bool dim_post_keep_is_in(unsigned int ch, struct di_buf_s *di_buf)
{
{
struct di_buf_s *pbuf_post;
struct di_buf_s *di_buf;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
struct di_ch_s *pch = get_chdata(ch);
bool release_flg = false;
di_buf->blk_buf->flg.d32,
mm->cfg.pbuf_flg.d32);
di_buf->blk_buf = NULL;
- if (di_buf->pat_buf) {
- qpat_in_ready(pch,
- (struct dim_pat_s *)di_buf->pat_buf);
- di_buf->pat_buf = NULL;
- }
+
di_que_in(ch, QUE_PST_NO_BUF, di_buf);
release_flg = true;
mm->sts.flg_realloc++;
dbg_keep("%s:buf[%d]\n", __func__, di_buf_index);
return true;
}
-
+#endif
+/* @ary_note: only for ready */
+/* @ary_note: when ready, process non-keep buffer and keep buffer */
+#ifdef MARK_HIS
bool dim_post_keep_release_one_check(unsigned int ch, unsigned int di_buf_index)
{
struct di_buf_s *pbuf_post;
struct di_buf_s *di_buf;
- struct di_mm_s *mm = dim_mm_get(ch);
+ struct div2_mm_s *mm = dim_mm_get(ch);
bool flg_alloc = false;
struct di_ch_s *pch;
}
if (di_buf->blk_buf) {
- if (di_buf->blk_buf->flg.d32 != mm->cfg.pbuf_flg.d32) {
+ if ((di_buf->blk_buf->flg.d32 != mm->cfg.pbuf_flg.d32) ||
+ (di_buf->blk_buf->sct_keep != 0xff)) {
flg_alloc = true;
dbg_mem2("keep_buf:2:flg trig realloc,0x%x->0x%x\n",
di_buf->blk_buf->flg.d32,
/* IN_USED -> OUT */
pch = get_chdata(ch);
di_que_out_not_fifo(ch, QUE_POST_KEEP, di_buf);
- if (di_buf->pat_buf) {
- qpat_in_ready(pch, (struct dim_pat_s *)di_buf->pat_buf);
- di_buf->pat_buf = NULL;
- }
mem_release_one_inused(pch, di_buf->blk_buf);
di_que_in(ch, QUE_PST_NO_BUF, di_buf);
#endif
return true;
}
+#else
+bool dim_post_keep_release_one_check(unsigned int ch, unsigned int di_buf_index)
+{
+// struct di_buf_s *pbuf_post;
+ struct di_buf_s *di_buf;
+ struct div2_mm_s *mm = dim_mm_get(ch);
+// bool flg_alloc = false;
+ struct di_ch_s *pch;
+ struct dim_ndis_s *ndis;
+
+ pch = get_chdata(ch);
+
+ ndis = ndis_get_fromid(pch, di_buf_index);
+ if (!ndis) {
+ PR_ERR("%s:no ndis\n", __func__);
+ return false;
+ }
+
+ if (!ndis_is_in_keep(pch, ndis)) {
+ /* @ary_note: from put */
+ if (ndis_is_in_display(pch, ndis)) {
+ di_buf = ndis->c.di_buf;
+ if (!di_buf) {
+ PR_ERR("%s:no di_buf\n", __func__);
+ return false;
+ }
+ di_buf->queue_index = -1;
+ di_que_in(ch, QUE_POST_BACK, di_buf);
+ ndis_move_display2idle(pch, ndis);
+ if (dimp_get(edi_mp_bypass_post_state))
+ PR_INF("%s:buf[%d,%d]\n", __func__,
+ di_buf->type, di_buf->index);
+ dbg_keep("%s:to back[%d]\n", __func__, di_buf_index);
+ } else {
+ PR_ERR("%s:ndis[%d] is not in keep or display\n",
+ __func__, ndis->header.index);
+ }
+ return true;
+ }
+
+ mm->sts.flg_realloc++;
+ dbg_mem2("%s:stsflg_realloc[%d]\n", __func__, mm->sts.flg_realloc);
+ mem_release_one_inused(pch, ndis->c.blk);
+ ndis_move_keep2idle(pch, ndis);
+ return true;
+}
+#endif
/* after dim_post_keep_release_one_check */
void dim_post_re_alloc(unsigned int ch)
{
- struct di_mm_s *mm = dim_mm_get(ch);
+ struct div2_mm_s *mm = dim_mm_get(ch);
// struct di_mng_s *pbm = get_bufmng();
struct di_ch_s *pch;
unsigned int length;
}
}
+#ifdef MARK_HIS
bool dim_post_keep_release_all_2free(unsigned int ch)
{
struct di_buf_s *di_buf;
return true;
}
+#endif
+#ifdef MARK_HIS
+/* @ary_note debug release cmd */
void dim_post_keep_cmd_release(unsigned int ch, struct vframe_s *vframe)
{
struct di_buf_s *di_buf;
di_buf->channel,
di_buf->index));
}
+#endif
//EXPORT_SYMBOL(dim_post_keep_cmd_release2);
-
+#ifdef MARK_HIS
void dim_dbg_release_keep_all(unsigned int ch)
{
unsigned int tmpa[MAX_FIFO_SIZE];
}
pw_queue_clear(ch, QUE_POST_KEEP_BACK);
}
-
+#endif
+#ifdef MARK_HIS
void dim_post_keep_cmd_proc(unsigned int ch, unsigned int index)
{
struct di_dev_s *di_dev;
struct di_buf_s *pbuf_post;
struct di_buf_s *di_buf;
ulong flags = 0;
- struct di_mm_s *mm = dim_mm_get(ch);
+ struct div2_mm_s *mm = dim_mm_get(ch);
struct di_ch_s *pch;
/*must post or err*/
len_keep = di_que_list_count(ch, QUE_POST_KEEP);
len_back = di_que_list_count(ch, QUE_POST_KEEP_BACK);
mm->sts.flg_release++;
+ #ifdef HIS_CODE
if (len_back >= len_keep) {
/*release all*/
pw_queue_clear(ch, QUE_POST_KEEP);
mem_release_all_inused(pch);
//mtsk_release(ch, ECMD_BLK_RELEASE);
}
+ #endif
break;
case EDI_TOP_STATE_REG_STEP1:
case EDI_TOP_STATE_REG_STEP1_P1:
}
spin_unlock_irqrestore(&plist_lock, flags);
}
+#else
+void dim_post_keep_cmd_proc(unsigned int ch, unsigned int index)
+{
+ struct di_dev_s *di_dev;
+ enum EDI_TOP_STATE chst;
+// unsigned int len_keep, len_back;
+// struct di_buf_s *pbuf_post;
+// struct di_buf_s *di_buf;
+ //ulong flags = 0;
+ struct div2_mm_s *mm = dim_mm_get(ch);
+ struct di_ch_s *pch;
+
+ /*must post or err*/
+ di_dev = get_dim_de_devp();
+
+ if (!di_dev || !di_dev->data_l) {
+ PR_WARN("%s: no di_dev\n", __func__);
+ return;
+ }
+ pch = get_chdata(ch);
+
+ //ary 2020-12-07 spin_lock_irqsave(&plist_lock, flags);
+
+ chst = dip_chst_get(ch);
+ dbg_wq("k:p[%d]%d\n", chst, index);
+ switch (chst) {
+ case EDI_TOP_STATE_READY: /* need check tvp*/
+ case EDI_TOP_STATE_UNREG_STEP1:
+ case EDI_TOP_STATE_UNREG_STEP2:
+ /*dim_post_keep_release_one(ch, index);*/
+ dim_post_keep_release_one_check(ch, index);
+ break;
+ case EDI_TOP_STATE_IDLE:
+ case EDI_TOP_STATE_BYPASS:
+ ndkb_qin_byidx(pch, index);
+ mm->sts.flg_release++;
+ break;
+ case EDI_TOP_STATE_REG_STEP1:
+ case EDI_TOP_STATE_REG_STEP1_P1:
+ case EDI_TOP_STATE_REG_STEP2:
+ ndkb_qin_byidx(pch, index);
+ break;
+ default:
+ PR_ERR("%s:do nothing? %s:%d\n",
+ __func__,
+ dip_chst_get_name(chst),
+ index);
+ break;
+ }
+ //ary 2020-12-07 spin_unlock_irqrestore(&plist_lock, flags);
+}
+#endif
+#ifdef MARK_HIS
void dim_uninit_buf(unsigned int disable_mirror, unsigned int channel)
{
/*int i = 0;*/
&de_devp->pdev->dev);
}
}
+#else
+void dim_uninit_buf(unsigned int disable_mirror, unsigned int channel)
+{
+ /*int i = 0;*/
+ #ifdef VFM_ORI
+ struct vframe_s **pvframe_in = get_vframe_in(channel);
+ #endif
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+ struct di_post_stru_s *ppost = get_post_stru(channel);
+ struct di_dev_s *de_devp = get_dim_de_devp();
+ struct di_ch_s *pch;
+ struct dim_mm_blk_s *blks[POST_BUF_NUM];
+ unsigned int blk_nub = 0;
+ int i;
+
+ pch = get_chdata(channel);
+
+ for (i = 0; i < POST_BUF_NUM; i++)
+ blks[i] = NULL;
+
+ //if (!disable_mirror)
+ blk_nub = ndis_2keep(pch, &blks[0], POST_BUF_NUM, disable_mirror);
+ //dim_post_keep_mirror_buffer2(channel);
+
+ mem_release(pch, &blks[0], blk_nub);
+ mem_2_blk(pch);
+ queue_init(channel, 0);
+ di_que_init(channel); /*new que*/
+ //bufq_iat_rest(pch);
+ qiat_all_back2_ready(pch);
+ bufq_ndis_unreg(pch);
+
+ /* decoder'buffer had been releae no need put */
+ #ifdef VFM_ORI
+ memset(pvframe_in, 0, sizeof(*pvframe_in) * MAX_IN_BUF_NUM);
+ #else
+ /* clear all ?*/
+ #endif
+ ppre->pre_de_process_flag = 0;
+ if (dimp_get(edi_mp_post_wr_en) && dimp_get(edi_mp_post_wr_support)) {
+ ppost->cur_post_buf = NULL;
+ ppost->post_de_busy = 0;
+ ppost->de_post_process_done = 0;
+ ppost->post_wr_cnt = 0;
+ }
+ if (cfgeq(MEM_FLAG, EDI_MEM_M_REV) && de_devp->nrds_enable) {
+ dim_nr_ds_buf_uninit(cfgg(MEM_FLAG),
+ &de_devp->pdev->dev);
+ }
+}
+#endif
+#ifdef MARK_HIS
void dim_log_buffer_state(unsigned char *tag, unsigned int channel)
{
struct di_pre_stru_s *ppre;
di_unlock_irqfiq_restore(irq_flag2);
}
}
+#endif
+#ifdef MARK_HIS
static void dump_state(unsigned int channel)
{
struct di_buf_s *p = NULL/*, *keep_buf*/;
/*struct di_dev_s *de_devp = get_dim_de_devp();*/
unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
unsigned int psize; /*new que*/
- struct di_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
+ struct div2_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
dump_state_flag = 1;
pr_info("version %s, init_flag %d, is_bypass %d\n",
pr_info("reg_unreg_timerout = %lu\n", reg_unreg_timeout_cnt);
dump_state_flag = 0;
}
+#endif
unsigned char dim_check_di_buf(struct di_buf_s *di_buf, int reason,
unsigned int channel)
di_mcinford_mif->size_x = (di_buf->vframe->height + 2) / 4 - 1;
di_mcinford_mif->size_y = 1;
di_mcinford_mif->canvas_num = di_buf->mcinfo_canvas_idx;
+ di_mcinford_mif->addr = di_buf->mcinfo_adr;
}
}
di_mcinfo_mif->size_x = pre_size_h / 2 - 1;
di_mcinfo_mif->size_y = 1;
di_mcinfo_mif->canvas_num = di_buf->mcinfo_canvas_idx;
+ di_mcinfo_mif->addr = di_buf->mcinfo_adr;
di_mcvec_mif->size_x = (pre_size_w + 4) / 5 - 1;
di_mcvec_mif->size_y = pre_size_h - 1;
di_mcvec_mif->canvas_num = di_buf->mcvec_canvas_idx;
+ di_mcvec_mif->addr = di_buf->mcvec_adr;
}
}
di_cnt_mif->start_y = 0;
di_cnt_mif->end_y = di_buf->vframe->height / 2 - 1;
di_cnt_mif->canvas_num = di_buf->cnt_canvas_idx;
+ di_cnt_mif->addr = di_buf->cnt_adr;
}
}
-#if 1
static void
config_di_wr_mif(struct DI_SIM_MIF_s *di_nrwr_mif,
struct DI_SIM_MIF_s *di_mtnwr_mif,
di_mtnwr_mif->canvas_num = di_buf->mtn_canvas_idx;
}
}
-#endif
#ifdef MARK_SC2 /* move di_hw_v2.c */
static void config_di_nrwr_mif(struct DI_SIM_MIF_s *di_nrwr_mif,
}
#endif
-#if 1 /* move di_hw_v2.c */
+/* move di_hw_v2.c */
static void config_di_mtnwr_mif(struct DI_SIM_MIF_s *di_mtnwr_mif,
struct di_buf_s *di_buf)
{
di_mtnwr_mif->start_y = 0;
di_mtnwr_mif->end_y = vf->height / 2 - 1;
di_mtnwr_mif->canvas_num = di_buf->mtn_canvas_idx;
+ di_mtnwr_mif->addr = di_buf->mtn_adr;
}
}
-#endif
-#if 1 /*ary move to di_hw_v2.c */
+/*ary move to di_hw_v2.c */
static void config_di_mif(struct DI_MIF_S *di_mif, struct di_buf_s *di_buf,
unsigned int channel)
{
di_mif->canvas0_addr2 =
(di_buf->vframe->canvas0Addr >> 16) & 0xff;
}
+ di_mif->reg_swap = 1;
+ di_mif->l_endian = 0;
+ di_mif->cbcr_swap = 0;
} else {
if (di_buf->vframe->type & VIDTYPE_VIU_444)
di_mif->video_mode = 1;
else
di_mif->video_mode = 0;
- if (di_buf->vframe->type & VIDTYPE_VIU_NV21)
+ if ((di_buf->vframe->type & VIDTYPE_VIU_NV21) ||
+ (di_buf->vframe->type & VIDTYPE_VIU_NV12))
di_mif->set_separate_en = 2;
else
di_mif->set_separate_en = 1;
}
}
}
-#endif
+
static void di_pre_size_change(unsigned short width,
unsigned short height,
unsigned short vf_type,
static void pre_inp_canvas_config(struct vframe_s *vf);
#endif
-static void pre_inp_mif_w(struct DI_MIF_S *di_mif, struct vframe_s *vf);
+//static void pre_inp_mif_w(struct DI_MIF_S *di_mif, struct vframe_s *vf);
static void dim_canvas_set2(struct vframe_s *vf, u32 *index);
void dim_pre_de_process(unsigned int channel)
ppre->di_wr_buf->vframe->canvas0Addr;
ppre->di_wr_buf->nr_canvas_idx =
ppre->di_wr_buf->vframe->canvas0Addr;
+ if (ppre->di_wr_buf->flg_nv21 == 1)
+ ppre->di_nrwr_mif.cbcr_swap = 0;
+ else
+ ppre->di_nrwr_mif.cbcr_swap = 1;
+ if (dip_itf_is_o_linear(pch)) {
+ ppre->di_nrwr_mif.reg_swap = 0;
+ ppre->di_nrwr_mif.l_endian = 1;
+
+ } else {
+ ppre->di_nrwr_mif.reg_swap = 1;
+ ppre->di_nrwr_mif.l_endian = 0;
+ }
+ if (cfgg(LINEAR)) {
+ ppre->di_nrwr_mif.linear = 1;
+ ppre->di_nrwr_mif.addr =
+ ppre->di_wr_buf->vframe->canvas0_config[0].phy_addr;
+ ppre->di_nrwr_mif.addr1 =
+ ppre->di_wr_buf->vframe->canvas0_config[1].phy_addr;
+ }
+
//dim_print("wr:%px\n", ppre->di_wr_buf);
} else {
+ ppre->di_nrwr_mif.reg_swap = 1;
+ ppre->di_nrwr_mif.cbcr_swap = 0;
+ ppre->di_nrwr_mif.l_endian = 0;
+ if (cfgg(LINEAR)) {
+ ppre->di_nrwr_mif.linear = 1;
+ ppre->di_nrwr_mif.addr = ppre->di_wr_buf->nr_adr;
+ }
config_canvas_idx(ppre->di_wr_buf,
cvss->pre_idx[canvases_idex][4],
cvss->pre_idx[canvases_idex][5]);
else
config_di_mif(&ppre->di_mem_mif,
ppre->di_mem_buf_dup_p, channel);
+ /* patch */
+ if (ppre->di_wr_buf->flg_nv21 &&
+ ppre->di_mem_buf_dup_p &&
+ ppre->di_mem_buf_dup_p != ppre->di_inp_buf) {
+ ppre->di_mem_mif.l_endian = ppre->di_nrwr_mif.l_endian;
+ ppre->di_mem_mif.cbcr_swap = ppre->di_nrwr_mif.cbcr_swap;
+ ppre->di_mem_mif.reg_swap = ppre->di_nrwr_mif.reg_swap;
+ }
if (!ppre->di_chan2_buf_dup_p) {
if (DIM_IS_IC_EF(SC2))
opl1()->pre_cfg_mif(&ppre->di_chan2_mif,
dim_nr_ds_hw_ctrl(false);
}
}
-
+ #ifndef TMP_MASK_FOR_T7
+ /*patch for SECAM signal format from vlsi-feijun for all IC*/
+ get_ops_nr()->secam_cfr_adjust(ppre->di_inp_buf->vframe->sig_fmt,
+ ppre->di_inp_buf->vframe->type);
+ #endif
/* set interrupt mask for pre module.
* we need to only leave one mask open
* to prevent multiple entry for dim_irq
ppre->madi_enable,
chan2_field_num,
ppre->vdin2nr |
- (ppre->is_bypass_mem << 4));
+ (ppre->is_bypass_mem << 4),
+ ppre);
//dimh_enable_afbc_input(ppre->di_inp_buf->vframe);
if (IS_ERR_OR_NULL(ppre->di_wr_buf))
}
if (dimp_get(edi_mp_mcpre_en)) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+ if (DIM_IS_IC_EF(T7) && opl1()->pre_enable_mc)
+ opl1()->pre_enable_mc(&ppre->di_mcinford_mif,
+ &ppre->di_mcinfowr_mif,
+ &ppre->di_mcvecwr_mif,
+ ppre->mcdi_enable);
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
dimh_enable_mc_di_pre_g12(&ppre->di_mcinford_mif,
&ppre->di_mcinfowr_mif,
&ppre->di_mcvecwr_mif,
ppre->field_count_for_cont,
dimp_get(edi_mp_mcpre_en));
-
/* must make sure follow part issue without interrupts,
* otherwise may cause watch dog reboot
*/
di_unlock_irqfiq_restore(irq_flag2);
/*reinit pre busy flag*/
ppre->pre_de_busy = 1;
-
+ pch->sum_pre++;
dim_dbg_pre_cnt(channel, "s3");
ppre->irq_time[0] = cur_to_msecs();
ppre->irq_time[1] = cur_to_msecs();
void dim_pre_de_done_buf_config(unsigned int channel, bool flg_timeout)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
int tmp_cur_lev;
struct di_buf_s *post_wr_buf = NULL;
unsigned int frame_motnum = 0;
unsigned int field_motnum = 0;
unsigned int pd_info = 0;
struct di_pre_stru_s *ppre = get_pre_stru(channel);
- //struct di_ch_s *pch;
+ struct di_ch_s *pch;
//struct di_buf_s *bufn;
//bool crc_right;
+ unsigned int afbce_used;
dim_dbg_pre_cnt(channel, "d1");
dim_ddbg_mod_save(EDI_DBG_MOD_PRE_DONEB, channel, ppre->in_seq);/*dbg*/
if (ppre->di_wr_buf) {
if (flg_timeout) {
- hpre_timout_read();
+ hpre_timeout_read();
if (DIM_IS_IC_EF(SC2))
opl1()->pre_gl_sw(false);
else
hpre_gl_sw(false);
}
+
+ dim_pqrpt_init(&ppre->di_wr_buf->pq_rpt);
+ if (!flg_timeout)
+ dcntr_pq_tune(&ppre->di_wr_buf->pq_rpt);
dim_tr_ops.pre_ready(ppre->di_wr_buf->vframe->index_disp);
ppre->di_wr_buf->flg_nr = 1;
if (ppre->pre_throw_flag > 0) {
}
if (ppre->di_wr_buf->flg_afbce_set) {
ppre->di_wr_buf->flg_afbce_set = 0;
+ //tmp
+ //if (ppre->di_wr_buf->blk_buf->flg.b.typ ==
+ //EDIM_BLK_TYP_PSCT) {
+ if (ppre->di_wr_buf->blk_buf &&
+ dim_blk_tvp_is_sct(ppre->di_wr_buf->blk_buf)) {
+ afbce_used = afbce_read_used(EAFBC_ENC0);
+ pch = get_chdata(channel);
+ sct_free_tail_l(pch,
+ afbce_used,
+ (struct dim_sct_s *)ppre->di_wr_buf->blk_buf->sct);
+// tst_resize(pch, afbce_used);
+ }
+ /*************************/
//afbce_sw(EAFBC_ENC0, 0);
}
#ifdef DET3D
ppre->mtn_status,
overturn,
ppre->di_inp_buf->vframe);
- post_wr_buf->vframe->di_pulldown
- = pd_info;
+ post_wr_buf->vframe->di_pulldown = pd_info;
}
post_wr_buf->vframe->di_pulldown |= 0x08;
vframe_type_name[ppre->di_post_inp_buf->type],
ppre->di_post_inp_buf->index);
#endif
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
queue_in(channel, ppre->di_post_inp_buf, QUEUE_RECYCLE);
ppre->di_post_inp_buf = NULL;
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
}
if (ppre->di_inp_buf) {
if (!di_pre_rdma_enable) {
vframe_type_name[ppre->di_inp_buf->type],
ppre->di_inp_buf->index);
#endif
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
if (!(ppre->di_inp_buf->dec_vf_state & DI_BIT0)) {
/*dec vf keep*/
queue_in(channel, ppre->di_inp_buf,
QUEUE_RECYCLE);
ppre->di_inp_buf = NULL;
}
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
} else {
ppre->di_post_inp_buf = ppre->di_inp_buf;
ppre->di_inp_buf = NULL;
static void recycle_vframe_type_pre(struct di_buf_s *di_buf,
unsigned int channel)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
queue_in(channel, di_buf, QUEUE_RECYCLE);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
}
/*
}
}
-static void add_eos_pre(unsigned int ch)
+#ifdef HIS_CODE
+static void add_eos_pre(unsigned int ch, struct dim_nins_s *nin)
{
struct di_buf_s *di_buf;
//PR_INF("%s:ch[%d]\n", __func__, ch);
di_buf = di_que_out_to_di_buf(ch, QUE_PRE_NO_BUF);
di_buf->is_eos = 1;
+ if (nin)
+ di_buf->c.in = nin;
+ di_que_in(ch, QUE_PRE_READY, di_buf);
+}
+#endif
+/* 2021-01-26 for eos out*/
+static void add_eos_in(unsigned int ch, struct dim_nins_s *nin)
+{
+ struct di_buf_s *di_buf;
+
+ if (di_que_is_empty(ch, QUE_IN_FREE)) {
+ PR_ERR("%s:no in buf\n", __func__);
+ return;
+ }
+ //PR_INF("%s:ch[%d]\n", __func__, ch);
+ di_buf = di_que_out_to_di_buf(ch, QUE_IN_FREE);
+ di_buf->is_eos = 1;
+ if (nin) {
+ di_buf->c.in = nin;
+ di_buf->is_nbypass = 1;
+ } else {
+ di_buf->c.in = NULL;
+ }
+
di_que_in(ch, QUE_PRE_READY, di_buf);
+ dbg_bypass("%s:\n", __func__);
}
/*
#endif
}
-static void pre_inp_mif_w(struct DI_MIF_S *di_mif, struct vframe_s *vf)
+//static
+void pre_inp_mif_w(struct DI_MIF_S *di_mif, struct vframe_s *vf)
{
+ unsigned int dbga = dim_get_dbg_dec21();
+ int i;
+ unsigned long addr[3];
+
if (vf->canvas0Addr != (u32)-1)
- di_mif->canvas_w = canvas_get_width(
- vf->canvas0Addr & 0xff);
+ di_mif->canvas_w =
+ canvas_get_width(vf->canvas0Addr & 0xff);
else
di_mif->canvas_w = vf->canvas0_config[0].width;
-}
-#ifdef MARK_HIS
-bool di_get_pre_hsc_down_en(void)
-{
- return pre_hsc_down_en;
-}
+ if (cfgg(LINEAR)) {
+ for (i = 0; i < vf->plane_num; i++) {
+ addr[i] = vf->canvas0_config[i].phy_addr;
+ dbg_ic("%s:[%d]addr[0x%lx]\n", __func__, i, addr[i]);
+ }
+ di_mif->addr0 = addr[0];
+ di_mif->cvs0_w = vf->canvas0_config[0].width;
+ di_mif->cvs1_w = 0;
+ di_mif->cvs2_w = 0;
+ if (vf->plane_num >= 2) {
+ di_mif->addr1 = addr[1];
+ di_mif->cvs1_w = vf->canvas0_config[1].width;
+ }
+ if (vf->plane_num >= 3) {
+ di_mif->addr2 = addr[2];
+ di_mif->cvs2_w = vf->canvas0_config[2].width;
+ }
+ di_mif->linear = 1;
+ if (vf->plane_num == 2) {
+ di_mif->buf_crop_en = 1;
+ di_mif->buf_hsize = vf->canvas0_config[0].width;
+ dbg_ic("\t:buf_h[%d]\n", di_mif->buf_hsize);
+ } else {
+ di_mif->buf_crop_en = 0;
+ dbg_ic("\t:not nv21?\n");
+ }
+
+ if (vf->canvas0_config[0].block_mode)
+ di_mif->block_mode = 1;
+ else
+ di_mif->block_mode = 0;
+ }
+
+ if (vf->type & VIDTYPE_VIU_NV12)
+ di_mif->cbcr_swap = 1;
+ else
+ di_mif->cbcr_swap = 0;
+ if ((vf->flag & VFRAME_FLAG_VIDEO_LINEAR) ||
+ dim_in_linear()) {
+ di_mif->reg_swap = 0;
+ di_mif->l_endian = 1;
+
+ } else {
+ di_mif->reg_swap = 1;
+ di_mif->l_endian = 0;
+ //di_mif->cbcr_swap = 0;
+ }
+ if (dbga & 0xf) {
+ di_mif->reg_swap = bget(&dbga, 0);
+ di_mif->l_endian = bget(&dbga, 1);
+ di_mif->cbcr_swap = bget(&dbga, 2);
+ }
+}
+
+#ifdef MARK_HIS
+bool di_get_pre_hsc_down_en(void)
+{
+ return pre_hsc_down_en;
+}
#endif
bool dbg_first_frame; /*debug */
unsigned int dbg_first_cnt_pre;
return 1;
}
+#ifdef MARK_HIS
/*for first frame no need to ready buf*/
bool dim_bypass_first_frame(unsigned int ch)
{
PR_INF("%s:ok\n", __func__);
return true;
}
-
+#endif
static bool pp_check_buf_cfg(struct di_ch_s *pch)
{
unsigned int ch;
buft->dw_adr = buff->dw_adr;
buft->afbc_crc = buff->afbc_crc;
buft->adr_start = buff->adr_start;
- buft->pat_buf = buff->pat_buf;
+// buft->pat_buf = buff->pat_buf;
buft->nr_size = buff->nr_size;
buft->tab_size = buff->tab_size;
buft->canvas_height = buff->canvas_height;
buft->buf_is_i = buff->buf_is_i;
buft->flg_null = buff->flg_null;
buft->in_buf = buff->in_buf;
+ buft->afbce_out_yuv420_10 = buff->afbce_out_yuv420_10;
+ buft->c.buffer = buff->c.buffer;
+ buft->c.src_is_i = buff->c.src_is_i;
+ buft->buf_hsize = buff->buf_hsize;
/* clear */
buff->blk_buf = NULL;
buff->flg_null = 1;
buff->buf_is_i = 0;
buff->afbc_crc = 0;
- buff->pat_buf = 0;
+// buff->pat_buf = 0;
buff->adr_start = 0;
buff->nr_adr = 0;
buff->afbc_adr = 0;
buff->nr_size = 0;
buff->tab_size = 0;
buff->in_buf = NULL;
+ buff->afbce_out_yuv420_10 = 0;
+ buff->c.buffer = NULL;
+ buff->c.src_is_i = false;
+ buff->buf_hsize = 0;
}
static struct di_buf_s *pp_pst_2_local(struct di_ch_s *pch)
struct di_buf_s *di_buf = NULL;
struct di_buf_s *buf_pst = NULL;
unsigned int ch;
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
if (!pp_check_buf_cfg(pch))
return di_buf;
ch = pch->ch_id;
di_buf = di_que_out_to_di_buf(ch, QUE_PRE_NO_BUF);
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
buf_pst = di_que_out_to_di_buf(ch, QUE_POST_FREE);
pp_buf_cp(di_buf, buf_pst);
//dbg_buf_log_save(pch, di_buf, 1);
//dbg_buf_log_save(pch, buf_pst, 2);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
return di_buf;
}
//di_lock_irqfiq_save(irq_flag2);
buf_pst = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF);
//di_unlock_irqfiq_restore(irq_flag2);
-
+ if (!buf_pst)
+ return NULL;
pp_buf_cp(buf_pst, di_buf);
//di_que_in(ch, QUE_PRE_NO_BUF, di_buf);
static void pp_drop_frame(struct di_buf_s *di_buf,
unsigned int channel)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
if (dimp_get(edi_mp_post_wr_en) &&
dimp_get(edi_mp_post_wr_support)) {
//queue_in(channel, di_buf, QUEUE_POST_DOING);
di_que_in(channel, QUE_POST_DOING, di_buf);
} else {
- di_que_in(channel, QUE_POST_READY, di_buf);
+ //no use di_que_in(channel, QUE_POST_READY, di_buf);
}
dim_tr_ops.post_do(di_buf->vframe->index_disp);
dim_print("di:ch[%d]:%dth %s[%d] => post ready %u ms.\n",
jiffies_to_msecs(jiffies_64 -
di_buf->vframe->ready_jiffies64));
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
}
static void dimpst_fill_outvf(struct vframe_s *vfm,
struct di_buf_s *di_buf,
enum EDPST_OUT_MODE mode);
+//static void dimpst_fill_outvf_ext(struct vframe_s *vfm,
+// struct di_buf_s *di_buf,
+// enum EDPST_OUT_MODE mode);
static void re_build_buf(struct di_ch_s *pch, enum EDI_SGN sgn)
{
bool is_4k = false;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
const struct di_mm_cfg_s *ptab;
struct mtsk_cmd_s blk_cmd;
unsigned int ch;
mtsk_release(ch, ECMD_BLK_RELEASE);
/* mm change*/
- ptab = di_get_mm_tab(is_4k);
+ ptab = di_get_mm_tab(is_4k, pch);
mm = dim_mm_get(ch);
mm->cfg.di_h = ptab->di_h;
if ((post_nub) && (post_nub < POST_BUF_NUM))
mm->cfg.num_post = post_nub;
- if ((!is_4k) && (cfgg(POUT_FMT) == 4))
+ if (pch->ponly && dip_is_ponly_sct_mem(pch))
+ mm->cfg.dis_afbce = 0;
+ else if ((!is_4k &&
+ ((cfggch(pch, POUT_FMT) == 4) || (cfggch(pch, POUT_FMT) == 6))))
mm->cfg.dis_afbce = 1;
else
mm->cfg.dis_afbce = 0;
}
/* post */
+ if (mm->cfg.pbuf_flg.b.typ == EDIM_BLK_TYP_PSCT)
+ sct_sw_on(pch,
+ mm->cfg.num_post,
+ mm->cfg.pbuf_flg.b.tvp,
+ mm->cfg.pst_buf_size);
+ else
+ sct_sw_off_rebuild(pch);
+ release_post += mem_release_sct_wait(pch);
+
blk_cmd.nub = release_post;//mm->cfg.num_post;
blk_cmd.flg.d32 = mm->cfg.pbuf_flg.d32;
}
}
+/* @ary_note: change return val for check block reason */
+/* 0: ok
+ * other: reason
+ **/
unsigned char dim_pre_de_buf_config(unsigned int channel)
{
struct di_buf_s *di_buf = NULL;
struct vframe_s *vframe;
- int i, di_linked_buf_idx = -1;
+ int /*i,*/ di_linked_buf_idx = -1;
unsigned char change_type = 0;
unsigned char change_type2 = 0;
bool bit10_pack_patch = false;
unsigned int width_roundup = 2;
+ #ifdef VFM_ORI
struct vframe_s **pvframe_in = get_vframe_in(channel);
+ #endif
struct di_pre_stru_s *ppre = get_pre_stru(channel);
// struct di_post_stru_s *ppost = get_post_stru(channel);
struct di_dev_s *de_devp = get_dim_de_devp();
struct di_ch_s *pch;
unsigned int nv21_flg = 0;
enum EDI_SGN sgn;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
u32 cur_dw_width = 0xffff;
u32 cur_dw_height = 0xffff;
+ struct dim_nins_s *nins = NULL;
+ enum EDPST_OUT_MODE tmpmode;
pch = get_chdata(channel);
if (di_blocking /*|| !dip_cma_st_is_ready(channel)*/)
- return 0;
+ return 1;
if (di_que_list_count(channel, QUE_IN_FREE) < 1)
- return 0;
+ return 2;
if ((di_que_list_count(channel, QUE_IN_FREE) < 2 &&
!ppre->di_inp_buf_next) ||
- ((ppre->sgn_lv != EDI_SGN_4K) &&
+ (((ppre->sgn_lv != EDI_SGN_4K) && (!pch->ponly)) &&
(queue_empty(channel, QUEUE_LOCAL_FREE))))
- return 0;
+ return 3;
if (di_que_list_count(channel, QUE_PRE_READY) >= DI_PRE_READY_LIMIT)
- return 0;
+ return 4;
if (di_que_is_empty(channel, QUE_POST_FREE))
- return 0;
+ return 5;
di_buf = di_que_peek(channel, QUE_POST_FREE);
mm = dim_mm_get(channel);
- if (!di_buf->blk_buf ||
- di_buf->blk_buf->flg.d32 != mm->cfg.pbuf_flg.d32) {
+ if (!dip_itf_is_ins_exbuf(pch) &&
+ (!di_buf->blk_buf ||
+ di_buf->blk_buf->flg.d32 != mm->cfg.pbuf_flg.d32)) {
if (!di_buf->blk_buf)
PR_ERR("%s:pst no blk:idx[%d]\n",
__func__,
mm->cfg.pbuf_flg.d32,
di_buf->blk_buf->flg.d32);
- return 0;
+ return 6;
}
if (di_que_is_empty(channel, QUE_PRE_NO_BUF))
- return 0;
+ return 7;
if (dim_is_bypass(NULL, channel)) {
/* some provider has problem if receiver
int in_buf_num = 0;
/*cur_lev = 0;*/
dimp_set(edi_mp_cur_lev, 0);
+ #ifdef VFM_ORI
for (i = 0; i < MAX_IN_BUF_NUM; i++)
if (pvframe_in[i])
in_buf_num++;
+ #else
+ in_buf_num = nins_cnt_used_all(pch);
+ #endif
if (in_buf_num > BYPASS_GET_MAX_BUF_NUM) {
#ifdef DET3D
if (ppre->vframe_interleave_flag == 0)
#endif
- return 0;
+ return 30;
}
dimh_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
} else if (ppre->prog_proc_type == 2) {
di_linked_buf_idx = peek_free_linked_buf(channel);
if (di_linked_buf_idx == -1)
- return 0;
+ return 8;
} else if (ppre->prog_proc_type == 0x10) { //ary add for pp
if (!pp_check_buf_cfg(pch))
- return 0;
+ return 9;
}
if (ppre->di_inp_buf_next) {
ppre->di_inp_buf = ppre->di_inp_buf_next;
#endif
}
} else {
- /* check if source change */
- vframe = pw_vf_peek(channel);
- if (vframe && is_from_vdin(vframe)) {
-#ifdef RUN_DI_PROCESS_IN_IRQ
- ppre->vdin2nr = is_input2pre(channel);
-#endif
- }
- if (!vframe)
- return 0;
+ nins = nins_peek(pch);
+ if (!nins)
+ return 10;
+ vframe = &nins->c.vfm_cp;
+
/*eos check*/
- if (vframe->type & VIDTYPE_V4L_EOS) {
- // ||dbg_is_trig_eos()
- vframe = pw_vf_get(channel);
+ if ((vframe->type & VIDTYPE_V4L_EOS) ||
+ dbg_is_trig_eos(channel)) {
+ nins = nins_get(pch);
+ if (!nins)
+ return 11;
+ //vframe = &nins->c.vfm_cp;
- if (!vframe)
- return 0;
PR_INF("eos\n");
if ((ppre->cur_prog_flag == 0) &&
(ppre->field_count_for_cont > 0)) {
- add_eos_pre(channel);
+ if (dip_itf_is_ins(pch) && (vframe->type &
+ VIDTYPE_V4L_EOS))
+ add_eos_in(channel, nins);
+ else
+ add_eos_in(channel, NULL);
} else if (ppre->prog_proc_type == 0x10 &&
ppre->di_mem_buf_dup_p &&
ppre->di_mem_buf_dup_p->flg_nr) {
di_que_in(channel, QUE_PRE_READY,
ppre->di_mem_buf_dup_p);
ppre->di_mem_buf_dup_p = NULL;
+ if (dip_itf_is_ins(pch) &&
+ (vframe->type & VIDTYPE_V4L_EOS))
+ add_eos_in(channel, nins);
+ else
+ add_eos_in(channel, NULL);
+ } else {
+ if (dip_itf_is_ins(pch) &&
+ (vframe->type & VIDTYPE_V4L_EOS))
+ add_eos_in(channel, nins);
+ else
+ add_eos_in(channel, NULL);
}
ppre->cur_width = 0;
ppre->di_mem_buf_dup_p = NULL;
ppre->di_chan2_buf_dup_p = NULL;
ppre->field_count_for_cont = 0;
-
+ #ifdef VFM_ORI
pw_vf_put(vframe, channel);
pw_vf_notify_provider(channel,
VFRAME_EVENT_RECEIVER_PUT, NULL);
+ #else
+ if (dip_itf_is_vfm(pch))
+ nins_used_some_to_recycle(pch, nins);
+ #endif
/*debug only*/
//pre_run_flag = DI_RUN_FLAG_PAUSE;
- return 0;
+ return 12;
}
/**************************************************/
/*mem check*/
memcpy(&ppre->vfm_cpy, vframe, sizeof(ppre->vfm_cpy));
+ #ifdef HIS_CODE
if (vframe->type & VIDTYPE_COMPRESS) {
/* backup the orignal vf->width/height for bypass case */
cur_dw_width = vframe->width;
vframe->width = vframe->compWidth;
vframe->height = vframe->compHeight;
}
- bypassr = dim_is_bypass(di_buf->vframe, channel);
+ #endif
+ bypassr = dim_is_bypass(vframe, channel);
+ /*2020-12-02: here use di_buf->vframe is err*/
change_type = is_source_change(vframe, channel);
if ((!bypassr) && change_type) {
sgn = di_vframe_2_sgn(vframe);
- if ((sgn != ppre->sgn_lv) &&
+ if (pch->ponly && dip_is_ponly_sct_mem(pch)) {
+ if (sgn != ppre->sgn_lv)
+ PR_INF("%s:p:%d->%d\n", __func__,
+ ppre->sgn_lv, sgn);
+ ppre->sgn_lv = sgn;
+ } else if ((sgn != ppre->sgn_lv) &&
dim_afds() &&
dip_is_support_4k(channel) &&
(((sgn == EDI_SGN_4K) &&
PR_INF("%s:rebuild:%d,sgn[%d]\n",
__func__,
mm->cfg.fix_buf, ppre->sgn_lv);
- return 0;
+ return 13;
}
} else if (sgn != ppre->sgn_lv) {
PR_INF("%s:%d->%d\n", __func__,
}
/**************************************************/
- vframe = pw_vf_get(channel);
+ nins = nins_get(pch);
+ if (!nins)
+ return 14;
+ vframe = &nins->c.vfm_cp;
- if (!vframe)
- return 0;
+ if (vframe->type & VIDTYPE_COMPRESS) {
+ /*backup the orignal vf->width/height for bypass case */
+ cur_dw_width = vframe->width;
+ cur_dw_height = vframe->height;
+ vframe->width = vframe->compWidth;
+ vframe->height = vframe->compHeight;
+ }
/*dbg_vfm(vframe, 1);*/
if (ppre->in_seq < kpi_frame_num) {
pr_dbg("[di_kpi] DI:ch[%d] get %dth vf[0x%p] from frontend %u ms.\n",
- channel,
- ppre->in_seq, vframe,
- jiffies_to_msecs(jiffies_64 -
- vframe->ready_jiffies64));
+ channel,
+ ppre->in_seq, vframe,
+ jiffies_to_msecs(jiffies_64 -
+ vframe->ready_jiffies64));
}
dim_tr_ops.pre_get(vframe->index_disp);
- didbg_vframe_in_copy(channel, vframe);
+ if (dip_itf_is_vfm(pch))
+ didbg_vframe_in_copy(channel, nins->c.ori);
+ else
+ didbg_vframe_in_copy(channel, vframe);
#ifdef MARK_SC2
if (vframe->type & VIDTYPE_COMPRESS) {
vframe->width = vframe->compWidth;
vframe->ready_jiffies64));
vframe->prog_proc_config = (cfg_prog_proc & 0x20) >> 5;
+ #ifdef VFM_ORI /* 2020-12-02: di no need throw bad_frame */
if (vframe->width > 10000 || vframe->height > 10000 ||
hold_video || ppre->bad_frame_throw_count > 0) {
if (vframe->width > 10000 || vframe->height > 10000)
pw_vf_put(vframe, channel);
pw_vf_notify_provider(channel,
VFRAME_EVENT_RECEIVER_PUT, NULL);
- return 0;
+ return 15;
}
+ #endif //end of VFM_ORI
bit10_pack_patch = (is_meson_gxtvbb_cpu() ||
is_meson_gxl_cpu() ||
is_meson_gxm_cpu());
/* backup frame motion info */
vframe->combing_cur_lev = dimp_get(edi_mp_cur_lev);/*cur_lev;*/
- dim_print("%s: vf_get => 0x%p\n", __func__, vframe);
+ dim_print("%s: vf_get => 0x%p\n", __func__, nins->c.ori);
di_buf = di_que_out_to_di_buf(channel, QUE_IN_FREE);
di_buf->dec_vf_state = 0; /*dec vf keep*/
if (dim_check_di_buf(di_buf, 10, channel))
- return 0;
+ return 16;
if (dimp_get(edi_mp_di_log_flag) & DI_LOG_VFRAME)
dim_dump_vframe(vframe);
di_buf->dw_height_bk = cur_dw_height;
di_buf->vframe->private_data = di_buf;
//10-09 di_buf->vframe->vf_ext = NULL; /*09-25*/
+ #ifdef VFM_ORI
pvframe_in[di_buf->index] = vframe;
+ #else
+ di_buf->c.in = nins;
+ //dbg_nins_log_buf(di_buf, 1);
+ #endif
di_buf->seq = ppre->in_seq;
ppre->in_seq++;
(ppre->cur_prog_flag == 0) &&
/*(ppre->in_seq > 1)*/(ppre->field_count_for_cont > 0)) {
/* last is i */
- add_eos_pre(channel);
+ add_eos_in(channel, NULL);
}
/* source change, when i mix p,force p as i*/
//if (change_type == 1 || (change_type == 2 &&
if (di_bypass_state_get(channel) == 0) {
//cnt_rebuild = 0; /*from no bypass to bypass*/
ppre->is_bypass_all = true;
+ bset(&pch->self_trig_mask, 29);
/*********************************/
if ((ppre->cur_prog_flag == 0) &&
(ppre->in_seq > 1)) {
/* last is i */
- add_eos_pre(channel);
+ add_eos_in(channel, NULL);
PR_INF("i to bypass, inset eos\n");
}
vframe_type_name[di_buf->type],
di_buf->index);
#endif
- return 0;
+ di_buf->is_nbypass = 1; /* 2020-12-07*/
+ if (pch->rsc_bypass.b.ponly_fst_cnt) {
+ pch->rsc_bypass.b.ponly_fst_cnt--;
+ //PR_INF("%s:%d\n", __func__,
+ //pch->rsc_bypass.b.ponly_fst_cnt);
+ }
+ return 17;
} else if (is_progressive(di_buf->vframe)) {
if (ppre->is_bypass_all) {
ppre->input_size_change_flag = true;
ppre->source_change_flag = 1;
+ bclr(&pch->self_trig_mask, 29);
//ppre->field_count_for_cont = 0;
}
ppre->is_bypass_all = false;
is_handle_prog_frame_as_interlace(vframe) &&
is_progressive(vframe)) {
struct di_buf_s *di_buf_tmp = NULL;
-
+ #ifdef VFM_ORI
pvframe_in[di_buf->index] = NULL;
+ #else
+ di_buf->c.in = NULL;
+ #endif
di_buf->vframe->type &=
(~VIDTYPE_TYPEMASK);
di_buf->vframe->type |=
if (dim_check_di_buf(di_buf_tmp, 10, channel)) {
recycle_vframe_type_pre(di_buf, channel);
PR_ERR("DI:no free in_buffer for progressive skip.\n");
- return 0;
+ return 18;
}
di_buf_tmp->vframe->private_data = di_buf_tmp;
di_buf_tmp->seq = ppre->in_seq;
ppre->in_seq++;
+ #ifdef VFM_ORI
pvframe_in[di_buf_tmp->index] = vframe;
+ #else
+ di_buf_tmp->c.in = nins;
+ #endif
memcpy(di_buf_tmp->vframe, vframe,
sizeof(vframe_t));
ppre->di_inp_buf_next = di_buf_tmp;
VIDTYPE_INTERLACE_BOTTOM;
di_buf_tmp->post_proc_flag = 0;
/*keep dec vf*/
- if (cfgg(KEEP_DEC_VF) == 1)
+ if (pch->ponly && dip_is_ponly_sct_mem(pch))
+ di_buf_tmp->dec_vf_state = DI_BIT0;
+ else if (cfggch(pch, KEEP_DEC_VF) == 1)
di_buf_tmp->dec_vf_state = DI_BIT0;
- else if ((cfgg(KEEP_DEC_VF) == 2) &&
+ else if ((cfggch(pch, KEEP_DEC_VF) == 2) &&
(ppre->sgn_lv == EDI_SGN_4K))
di_buf_tmp->dec_vf_state = DI_BIT0;
ppre->di_inp_buf = di_buf;
* pr_dbg("%s:recycle keep buffer\n", __func__);
*/
recycle_vframe_type_pre(ppre->di_inp_buf, channel);
- return 0;
+ return 19;
}
queue_out(channel, di_buf);/*QUEUE_LOCAL_FREE*/
if (ppre->prog_proc_type & 0x10)
di_buf->canvas_config_flag = 2;
di_buf->di_wr_linked_buf = NULL;
- di_buf->di_buf_post =
- di_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (!di_buf->di_buf_post) {
- PR_ERR("%s:no post buf\n", __func__);
- return 0;
+ if (dimp_get(edi_mp_bypass_post_state)) {
+ PR_INF("%s:no post buffer\n", __func__);
+ } else {
+ di_buf->di_buf_post =
+ di_que_out_to_di_buf(channel, QUE_POST_FREE);
+ if (!di_buf->di_buf_post) {
+ PR_ERR("%s:no post buf\n", __func__);
+ return 20;
+ }
+ if (ppre->input_size_change_flag)
+ di_buf->di_buf_post->trig_post_update = 1;
+ else
+ di_buf->di_buf_post->trig_post_update = 0;
+ di_buf->di_buf_post->c.src_is_i = true;
+ mem_resize_buf(pch, di_buf->di_buf_post);
+ dim_pqrpt_init(&di_buf->di_buf_post->pq_rpt);
+ if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
+ dim_dbg_buffer2(di_buf->di_buf_post->c.buffer,
+ 3);
+ //dim_pqrpt_init(&di_buf->di_buf_post->pq_rpt);
}
- if (ppre->input_size_change_flag)
- di_buf->di_buf_post->trig_post_update = 1;
- else
- di_buf->di_buf_post->trig_post_update = 0;
} else if (ppre->prog_proc_type == 2) {
/* p use 2 i buf */
di_linked_buf_idx = peek_free_linked_buf(channel);
*/
//recycle_keep_buffer(channel);
ppre->di_inp_buf_next = ppre->di_inp_buf;
- return 0;
+ return 21;
}
di_buf->post_proc_flag = 0;
di_buf->di_wr_linked_buf->pre_ref_count = 0;
di_buf->di_wr_linked_buf->post_ref_count = 0;
di_buf->canvas_config_flag = 1;
+ di_buf->c.src_is_i = false;
#ifdef TEST_4K_NR
} else if (ppre->prog_proc_type == 0x10) {
/********************************************************/
di_buf = pp_pst_2_local(pch);
if (dim_check_di_buf(di_buf, 17, channel)) {
//di_unlock_irqfiq_restore(irq_flag2);
- return 0;
+ return 22;
}
+ mem_resize_buf(pch, di_buf);
di_buf->post_proc_flag = 0;
di_buf->canvas_config_flag = 1;
di_buf->di_wr_linked_buf = NULL;
+ di_buf->c.src_is_i = false;
//if (dim_cfg_pre_nv21(0)) {
- if ((cfgg(POUT_FMT) == 1) || (cfgg(POUT_FMT) == 2)) {
+ if (pch->ponly && dip_is_ponly_sct_mem(pch)) {
+ nv21_flg = 0;
+ di_buf->flg_nv21 = 0;
+ } else if ((cfggch(pch, POUT_FMT) == 1) ||
+ (cfggch(pch, POUT_FMT) == 2)) {
nv21_flg = 1; /*nv21*/
- di_buf->flg_nv21 = 1;
- } else if ((cfgg(POUT_FMT) == 5) &&
+ di_buf->flg_nv21 = cfggch(pch, POUT_FMT);
+ } else if ((cfggch(pch, POUT_FMT) == 5) &&
(ppre->sgn_lv == EDI_SGN_4K)) {
nv21_flg = 1; /*nv21*/
di_buf->flg_nv21 = 1;
}
/*keep dec vf*/
//di_buf->dec_vf_state = DI_BIT0;
- if (cfgg(KEEP_DEC_VF) == 1)
+ if (pch->ponly && dip_is_ponly_sct_mem(pch))
ppre->di_inp_buf->dec_vf_state = DI_BIT0;
- else if ((cfgg(KEEP_DEC_VF) == 2) &&
+ else if (cfggch(pch, KEEP_DEC_VF) == 1)
+ ppre->di_inp_buf->dec_vf_state = DI_BIT0;
+ else if ((cfggch(pch, KEEP_DEC_VF) == 2) &&
(ppre->sgn_lv == EDI_SGN_4K))
ppre->di_inp_buf->dec_vf_state = DI_BIT0;
+ if ((dip_is_support_nv2110(channel)) &&
+ (ppre->sgn_lv == EDI_SGN_4K))
+ di_buf->afbce_out_yuv420_10 = 1;
+ else
+ di_buf->afbce_out_yuv420_10 = 0;
+
if (ppre->input_size_change_flag)
di_buf->trig_post_update = 1;
else
* pr_dbg("%s:recycle keep buffer\n", __func__);
*/
recycle_vframe_type_pre(ppre->di_inp_buf, channel);
- return 0;
+ return 23;
}
queue_out(channel, di_buf);/*QUEUE_LOCAL_FREE*/
if (ppre->prog_proc_type & 0x10)
ppre->di_wr_buf = di_buf;
ppre->di_wr_buf->pre_ref_count = 1;
#ifdef DBG_TEST_CRC_P
- dbg_checkcrc(ppre->di_wr_buf, 2); //debug
+ //if (ppre->di_wr_buf->blk_buf->flg.b.typ != EDIM_BLK_TYP_PSCT)
+ if (ppre->di_wr_buf->blk_buf &&
+ ((ppre->di_wr_buf->blk_buf->flg.b.typ == EDIM_BLK_TYP_OLDI) ||
+ (ppre->di_wr_buf->blk_buf->flg.b.typ == EDIM_BLK_TYP_OLDP)))
+ dbg_checkcrc(ppre->di_wr_buf, 2); //debug
#endif
#ifdef DI_BUFFER_DEBUG
dim_print("%s: %s[%d] => di_wr_buf\n", __func__,
//if (di_buf->vframe->width == 3840 && di_buf->vframe->height == 2160)
if (ppre->sgn_lv == EDI_SGN_4K) {
di_buf->is_4k = 1;
- if (cfgg(BYPASS_MEM) == 2)
+ if (cfgg(BYPASS_MEM) == 2) {
ppre->is_bypass_mem = 1;
- else
+ } else if (cfgg(BYPASS_MEM) == 3) {
+ if (IS_VDIN_SRC(pch->src_type))
+ ppre->is_bypass_mem = 0;
+ else
+ ppre->is_bypass_mem = 1;
+ } else {
ppre->is_bypass_mem = 0;
+ }
} else {
di_buf->is_4k = 0;
}
/* set vframe bit info */
di_buf->vframe->bitdepth &= ~(BITDEPTH_YMASK);
di_buf->vframe->bitdepth &= ~(FULL_PACK_422_MODE);
+ /* pps auto */
+ if (de_devp->pps_enable & DI_BIT1) {
+ if (VFMT_IS_I(ppre->cur_inp_type))
+ dimp_set(edi_mp_pps_position, 0);
+ else
+ dimp_set(edi_mp_pps_position, 1);
+ }
if (de_devp->pps_enable && dimp_get(edi_mp_pps_position)) {
if (dimp_get(edi_mp_pps_dstw) != di_buf->vframe->width) {
di_buf->vframe->width = dimp_get(edi_mp_pps_dstw);
if (ppre->cur_inp_type & VIDTYPE_PRE_INTERLACE)
di_buf->vframe->type |= VIDTYPE_PRE_INTERLACE;
- if (ppre->prog_proc_type == 0x10 &&
- (nv21_flg || (cfgg(POUT_FMT) == 0) ||
- (((cfgg(POUT_FMT) == 4) || (cfgg(POUT_FMT) == 5)) &&
+ if (pch->ponly && dip_is_ponly_sct_mem(pch)) {
+ if (dim_afds() && dim_afds()->cnt_sgn_mode) {
+ if (IS_COMP_MODE
+ (ppre->di_inp_buf->vframe->type)) {
+ di_buf->afbc_sgn_cfg =
+ dim_afds()->cnt_sgn_mode
+ (AFBC_SGN_P_H265);
+ } else {
+ di_buf->afbc_sgn_cfg =
+ dim_afds()->cnt_sgn_mode(AFBC_SGN_P);
+ }
+ }
+ } else if (ppre->prog_proc_type == 0x10 &&
+ (nv21_flg ||
+ (cfggch(pch, POUT_FMT) == 0) ||
+ (((cfggch(pch, POUT_FMT) == 4) ||
+ (cfggch(pch, POUT_FMT) == 5) ||
+ (cfggch(pch, POUT_FMT) == 6)) &&
(ppre->sgn_lv <= EDI_SGN_HD)))) {
if (dim_afds() && dim_afds()->cnt_sgn_mode) {
if (IS_COMP_MODE
(AFBC_SGN_BYPSS);
}
}
-
} else {
if (dim_afds() && dim_afds()->cnt_sgn_mode) {
if (IS_COMP_MODE
}
if (nv21_flg && ppre->prog_proc_type == 0x10) {
dim_print("cfg wr buf as nv21\n");
- dimpst_fill_outvf(di_buf->vframe,
- di_buf, EDPST_OUT_MODE_NV21);
+ //if (dip_itf_is_ins_exbuf(pch)) {
+ if (cfggch(pch, POUT_FMT) == 1)
+ tmpmode = EDPST_OUT_MODE_NV21;
+ else
+ tmpmode = EDPST_OUT_MODE_NV12;
+ dimpst_fill_outvf(di_buf->vframe,
+ di_buf, tmpmode);
+ //} else {
+ // dimpst_fill_outvf(di_buf->vframe,
+ // di_buf, EDPST_OUT_MODE_NV21);
+ //}
}
} else {
if (((ppre->di_inp_buf->vframe->type &
if (VFMT_IS_I(ppre->cur_inp_type))
di_buf->afbc_info |= DI_BIT1;/*flg is real i */
-
+ #ifdef HIS_CODE
if (DIM_IS_IC_EF(SC2) && dim_afds() &&
dim_afds()->cnt_sgn_mode) {
if (IS_COMP_MODE(ppre->di_inp_buf->vframe->type)) {
di_buf->afbc_sgn_cfg =
dim_afds()->cnt_sgn_mode(AFBC_SGN_BYPSS);
}
+ #else
+ if (dim_afds()) {
+ if (dim_afds()->is_sts(EAFBC_EN_6CH)) {
+ if (IS_COMP_MODE(ppre->di_inp_buf->vframe->type)) {
+ di_buf->afbc_sgn_cfg =
+ dim_afds()->cnt_sgn_mode(AFBC_SGN_I_H265);
+ } else {
+ di_buf->afbc_sgn_cfg =
+ dim_afds()->cnt_sgn_mode(AFBC_SGN_I);
+ }
+ if (cfggch(pch, IOUT_FMT) != 3) //afbce
+ dim_afds()->sgn_mode_set(&di_buf->afbc_sgn_cfg,
+ EAFBC_SNG_CLR_WR);
+ } else {
+ di_buf->afbc_sgn_cfg =
+ dim_afds()->cnt_sgn_mode(AFBC_SGN_BYPSS);
+ if (cfggch(pch, IOUT_FMT) == 3)
+ dim_afds()->sgn_mode_set(&di_buf->afbc_sgn_cfg,
+ EAFBC_SNG_SET_WR);
+ }
+ }
+ #endif
}
if (is_bypass_post(channel)) {
recovery_log_reason = 12;
recovery_flag++;
- return 0;
+
+ return 24;
}
if (is_meson_tl1_cpu() &&
ppre->comb_mode &&
else
get_ops_mtn()->com_patch_pre_sw_set(0);
}
- return 1;
+ return 0; /*ok*/
}
int dim_check_recycle_buf(unsigned int channel)
struct di_buf_s *tmp;
int itmp;
int ret = 0;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
struct di_ch_s *pch = get_chdata(channel);
#ifdef DI_BUFFER_DEBUG
int type;
int index;
#endif
+ #ifdef VFM_ORI
struct vframe_s **pvframe_in = get_vframe_in(channel);
+ #else
+ struct dim_nins_s *ins = NULL;
+ #endif
struct di_pre_stru_s *ppre = get_pre_stru(channel);
mm = dim_mm_get(channel);
di_buf->post_ref_count <= 0) { /*ary maybe <=*/
if (di_buf->type == VFRAME_TYPE_IN) {
queue_out(channel, di_buf);
+ #ifdef VFM_ORI
if (pvframe_in[di_buf->index]) {
pw_vf_put(pvframe_in[di_buf->index],
channel);
- pw_vf_notify_provider(channel,
- VFRAME_EVENT_RECEIVER_PUT,
- NULL);
+ pw_vf_notify_provider
+ (channel,
+ VFRAME_EVENT_RECEIVER_PUT,
+ NULL);
dim_print("%s:ch[%d]:idx[%d]\n",
__func__, channel,
di_buf->index);
ready_jiffies64));
pvframe_in[di_buf->index] = NULL;
}
+ #else
+ if (di_buf->c.in) {
+ ins = (struct dim_nins_s *)di_buf->c.in;
+ nins_used_some_to_recycle(pch, ins);
+ di_buf->c.in = NULL;
+ }
+ #endif
di_buf->invert_top_bot_flag = 0;
di_buf->dec_vf_state = 0;
di_que_in(channel, QUE_IN_FREE, di_buf);
di_buf->afbc_sgn_cfg = 0;
di_buf->flg_nr = 0;
di_buf->flg_nv21 = 0;
+ di_buf->afbce_out_yuv420_10 = 0;
di_buf->post_ref_count = 0;/*ary maybe*/
if (mm->cfg.num_local == 0) {
if (di_buf->iat_buf) {
mem_release_one_inused(pch,
di_buf->blk_buf);
di_buf->blk_buf = NULL;
- if (di_buf->pat_buf) {
- qpat_in_ready(pch,
- (struct dim_pat_s *)di_buf->pat_buf);
- di_buf->pat_buf = NULL;
- }
di_que_in(channel,
QUE_PRE_NO_BUF, di_buf);
} else {
sc2_dbg_pre_info(data32);
return IRQ_HANDLED;
}
-
+ di_lock_irq(); //2020-12-10
channel = pre->curr_ch;
ppre = pre->pres;
}
#else
+ di_lock_irq(); //2020-12-10
channel = pre->curr_ch;
ppre = pre->pres;
#endif
-#ifdef DET3D
- if (dimp_get(edi_mp_det3d_en)) {
- if ((data32 & 0x100) && !(mask32 & 0x100) && flag) {
- DIM_DI_WR(DI_INTR_CTRL, data32);
- det3d_irq(channel);
- } else {
- goto end;
- }
- } else {
- DIM_DI_WR(DI_INTR_CTRL, data32);
- }
-#else
if (flag) {
if (DIM_IS_IC_EF(SC2))
opl1()->pre_gl_sw(false);
DIM_DI_WR(DI_INTR_CTRL,
(data32 & 0xfffffffb) | (intr_mode << 30));
}
-#endif
/*if (ppre->pre_de_busy == 0) {*/
/*if (!di_pre_wait_irq_get()) {*/
- if (!atomic_dec_and_test(&get_hw_pre()->flg_wait_int)) {
+ if (flag && (!atomic_dec_and_test(&get_hw_pre()->flg_wait_int))) {
PR_ERR("%s:ch[%d]:enter:reg[0x%x]= 0x%x,dtab[%d]\n", __func__,
channel,
DI_INTR_CTRL,
RD(DI_INTR_CTRL),
pre->sdt_mode.op_crr);
+ di_unlock_irq(); //2020-12-10
return IRQ_HANDLED;
}
dim_tr_ops.pre(ppre->field_count_for_cont, ppre->irq_time[0]);
/*add from valsi wang.feng*/
- dim_arb_sw(false);
- dim_arb_sw(true);
+ if (!dim_dbg_cfg_disable_arb()) {
+ dim_arb_sw(false);
+ dim_arb_sw(true);
+ dbg_ic("arb reset\n");
+ } else {
+ dbg_ic("arb not reset\n");
+ }
if (dimp_get(edi_mp_mcpre_en)) {
get_mcinfo_from_reg_in_irq(channel);
if ((is_meson_gxlx_cpu() &&
pre->flg_int_done = 1;
}
-
+ di_unlock_irq(); //2020-12-10
return IRQ_HANDLED;
}
vf->canvas0Addr = 0;
for (i = 0; i < planes; i++, canvas_index++, cfg++) {
canvas_config_config(*canvas_index, cfg);
- dim_print("\tw[%d],h[%d],cid[%d]\n",
- cfg->width, cfg->height, *canvas_index);
+ dim_print("\tw[%d],h[%d],cid[%d],0x%x\n",
+ cfg->width, cfg->height,
+ *canvas_index, cfg->phy_addr);
shift = 8 * i;
vf->canvas0Addr |= (*canvas_index << shift);
//vf->plane_num = planes;
unsigned int *v,
unsigned int ch)
{
- struct di_mm_s *mm = dim_mm_get(ch); /*mm-0705*/
+ struct div2_mm_s *mm = dim_mm_get(ch); /*mm-0705*/
int width = mm->cfg.di_w;
int height = mm->cfg.di_h;
int canvas_height = height + 8;
*v = canvas_height;
}
+/* @ary_note: use di_buf to fill vfm */
static void dimpst_fill_outvf(struct vframe_s *vfm,
struct di_buf_s *di_buf,
enum EDPST_OUT_MODE mode)
{
- struct canvas_config_s *cvsp;
+ struct canvas_config_s *cvsp, *cvsf;
unsigned int cvsh, cvsv, csize;
struct di_dev_s *de_devp = get_dim_de_devp();
+ struct di_buffer *buffer; //for ext buff
+ unsigned int ch;
+ struct di_ch_s *pch;
+ bool ext_buf = false;
- memcpy(vfm, di_buf->vframe, sizeof(*vfm));
+ //check ext buffer:
+ ch = di_buf->channel;
+ pch = get_chdata(ch);
+
+ if (dip_itf_is_ins_exbuf(pch)) {
+ ext_buf = true;
+ if (!di_buf->c.buffer) {
+ PR_ERR("%s:ext_buf,no buffer\n", __func__);
+ return;
+ }
+ buffer = (struct di_buffer *)di_buf->c.buffer;
+ if (!buffer->vf) {
+ PR_ERR("%s:ext_buf,no vf\n", __func__);
+ return;
+ }
+ dim_print("%s:buffer %px\n", __func__, buffer);
+ cvsf = &buffer->vf->canvas0_config[0];
+ }
+// unsigned int tmp;
+ if (vfm != di_buf->vframe) //@ary_note
+ memcpy(vfm, di_buf->vframe, sizeof(*vfm));
/* canvas */
vfm->canvas0Addr = (u32)-1;
di_cnt_cvs_nv21(0, &cvsh, &cvsv, di_buf->channel);
/* 0 */
cvsp = &vfm->canvas0_config[0];
- cvsp->phy_addr = di_buf->nr_adr;
+ if (ext_buf) {
+ cvsp->phy_addr = cvsf->phy_addr;
+ cvsp->width = cvsf->width;
+ cvsp->height = cvsf->height;
+ } else {
+ cvsp->phy_addr = di_buf->nr_adr;
+ cvsp->width = cvsh;
+ cvsp->height = cvsv;
+ }
+ cvsp->block_mode = 0;
+ cvsp->endian = 0;
+
+ csize = roundup((cvsh * cvsv), PAGE_SIZE);
+ /* 1 */
+ cvsp = &vfm->canvas0_config[1];
+
+ if (ext_buf) {
+ cvsf = &buffer->vf->canvas0_config[1];
+ cvsp->phy_addr = cvsf->phy_addr;
+ cvsp->width = cvsf->width;
+ cvsp->height = cvsf->height;
+ } else {
+ cvsp->phy_addr = di_buf->nr_adr + csize;
+ cvsp->width = cvsh;
+ cvsp->height = cvsv;
+ }
+ cvsp->block_mode = 0;
+ cvsp->endian = 0;
+ }
+ #ifdef CVS_UINT
+ dim_print("%s:%d:addr0[0x%x], 1[0x%x],w[%d,%d]\n",
+ __func__,
+ ext_buf, vfm->canvas0_config[0].phy_addr,
+ vfm->canvas0_config[1].phy_addr,
+ vfm->canvas0_config[0].width,
+ vfm->canvas0_config[0].height);
+ #else
+ dim_print("%s:%d:addr0[0x%lx], 1[0x%lx],w[%d,%d]\n",
+ __func__,
+ ext_buf,
+ vfm->canvas0_config[0].phy_addr,
+ vfm->canvas0_config[1].phy_addr,
+ vfm->canvas0_config[0].width,
+ vfm->canvas0_config[0].height);
+ #endif
+ /* type */
+ if (mode == EDPST_OUT_MODE_NV21 ||
+ mode == EDPST_OUT_MODE_NV12) {
+ /*clear*/
+ vfm->type &= ~(VIDTYPE_VIU_NV12 |
+ VIDTYPE_VIU_444 |
+ VIDTYPE_VIU_NV21 |
+ VIDTYPE_VIU_422 |
+ VIDTYPE_VIU_SINGLE_PLANE |
+ VIDTYPE_COMPRESS |
+ VIDTYPE_PRE_INTERLACE);
+ vfm->type |= VIDTYPE_VIU_FIELD;
+ vfm->type |= VIDTYPE_DI_PW;
+ if (mode == EDPST_OUT_MODE_NV21)
+ vfm->type |= VIDTYPE_VIU_NV21;
+ else
+ vfm->type |= VIDTYPE_VIU_NV12;
+
+ /* bit */
+ vfm->bitdepth &= ~(BITDEPTH_MASK);
+ vfm->bitdepth &= ~(FULL_PACK_422_MODE);
+ vfm->bitdepth |= (BITDEPTH_Y8 |
+ BITDEPTH_U8 |
+ BITDEPTH_V8);
+ }
+
+ if (de_devp->pps_enable &&
+ dimp_get(edi_mp_pps_position) == 0) {
+ if (dimp_get(edi_mp_pps_dstw))
+ vfm->width = dimp_get(edi_mp_pps_dstw);
+
+ if (dimp_get(edi_mp_pps_dsth))
+ vfm->height = dimp_get(edi_mp_pps_dsth);
+ }
+
+ if (di_buf->afbc_info & DI_BIT0)
+ vfm->height = vfm->height / 2;
+
+ //dim_print("%s:h[%d]\n", __func__, vfm->height);
+#ifdef NV21_DBG
+ if (cfg_vf)
+ vfm->type = cfg_vf;
+#endif
+}
+
+#ifdef MARK_HIS
+/* for exit buffer */
+/* only change addr */
+static void dimpst_fill_outvf_ext(struct vframe_s *vfm,
+ struct di_buf_s *di_buf,
+ enum EDPST_OUT_MODE mode)
+{
+ struct canvas_config_s *cvsp, *cvsf;
+ unsigned int cvsh, cvsv, csize;
+ struct di_dev_s *de_devp = get_dim_de_devp();
+// unsigned int tmp;
+ struct di_buffer *buffer; //for ext buff
+
+ if (!di_buf->c.buffer) {
+ PR_ERR("%s:no buffer\n", __func__);
+ return;
+ }
+ buffer = (struct di_buffer *)di_buf->c.buffer;
+ if (!buffer->vf) {
+ PR_ERR("%s:no buffer vf\n", __func__);
+ return;
+ }
+ if (vfm != di_buf->vframe) //@ary_note
+ memcpy(vfm, di_buf->vframe, sizeof(*vfm));
+
+ /* canvas */
+ vfm->canvas0Addr = (u32)-1;
+
+ if (mode == EDPST_OUT_MODE_DEF) {
+ vfm->plane_num = 1;
+ cvsp = &vfm->canvas0_config[0];
+ cvsf = &buffer->vf->canvas0_config[0];
+ cvsp->phy_addr = cvsf->phy_addr;
+ cvsp->block_mode = 0;
+ cvsp->endian = 0;
+ cvsp->width = di_buf->canvas_width[NR_CANVAS];
+ cvsp->height = di_buf->canvas_height;
+ } else {
+ vfm->plane_num = 2;
+ /* count canvs size */
+ di_cnt_cvs_nv21(0, &cvsh, &cvsv, di_buf->channel);
+ /* 0 */
+ cvsp = &vfm->canvas0_config[0];
+ cvsf = &buffer->vf->canvas0_config[0];
+ cvsp->phy_addr = cvsf->phy_addr;
cvsp->block_mode = 0;
cvsp->endian = 0;
cvsp->width = cvsh;
csize = roundup((cvsh * cvsv), PAGE_SIZE);
/* 1 */
cvsp = &vfm->canvas0_config[1];
+ cvsf = &buffer->vf->canvas0_config[1];
cvsp->width = cvsh;
cvsp->height = cvsv;
- cvsp->phy_addr = di_buf->nr_adr + csize;
+ cvsp->phy_addr = cvsf->phy_addr;
cvsp->block_mode = 0;
cvsp->endian = 0;
}
if (di_buf->afbc_info & DI_BIT0)
vfm->height = vfm->height / 2;
- //dim_print("%s:h[%d]\n", __func__, vfm->height);
+ dim_print("%s:h[%d]\n", __func__, vfm->height);
#ifdef NV21_DBG
if (cfg_vf)
vfm->type = cfg_vf;
#endif
}
+#endif
#if 1/* move to di_hw_v2.c */
static void dim_cfg_s_mif(struct DI_SIM_MIF_s *smif,
for (i = 0; i < vf->plane_num; i++) {
PR_INF("%d:\n", i);
cvsp = &vf->canvas0_config[i];
+ #ifdef CVS_UINT
PR_INF("\tph=0x%x\n", cvsp->phy_addr);
+ #else
+ PR_INF("\tph=0x%lx\n", cvsp->phy_addr);
+ #endif
PR_INF("\tw=%d\n", cvsp->width);
PR_INF("\th=%d\n", cvsp->height);
PR_INF("\tb=%d\n", cvsp->block_mode);
union hw_sc2_ctr_pst_s *sc2_post_cfg;
union hw_sc2_ctr_pst_s *sc2_post_cfg_set;
unsigned int tmp;
+ unsigned int dbg_r;
struct di_ch_s *pch;
/*dbg*/
if (ppost->frame_cnt == 1 && kpi_frame_num > 0) {
pr_dbg("[di_kpi] di:ch[%d]:queue 1st frame to post ready.\n",
- channel);
+ channel);
}
dim_secure_sw_post(channel);
else
di_height++;
}
+ if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
+ dim_dbg_buffer2(di_buf->c.buffer, 7);
#ifdef DIM_OUT_NV21
/* nv 21*/
if (is_mask(SC2_DW_EN))
dw_fill_outvf(&pst->vf_post, di_buf);
- else if (cfg_nv21 & DI_BIT0)
+ //else if (cfg_nv21 & DI_BIT0)
+ else if (cfggch(pch, IOUT_FMT) == 1)
dimpst_fill_outvf(&pst->vf_post, di_buf, EDPST_OUT_MODE_NV21);
+ else if (cfggch(pch, IOUT_FMT) == 2)
+ dimpst_fill_outvf(&pst->vf_post, di_buf, EDPST_OUT_MODE_NV12);
else
dimpst_fill_outvf(&pst->vf_post, di_buf, EDPST_OUT_MODE_DEF);
/*************************************************/
if (di_buf->trig_post_update) {
pst->last_pst_size = 0;
//PR_INF("post trig\n");
+ ppost->seq = 0;
}
-
+ di_buf->seq = ppost->seq;
if (/*RD(DI_POST_SIZE)*/pst->last_pst_size != ((di_width - 1) |
((di_height - 1) << 16)) ||
ppost->buf_type != di_buf->di_buf_dup_p[0]->type ||
else
sc2_post_cfg->b.post_frm_sel = 0;
//dim_sc2_contr_pst(sc2_post_cfg);
+ if (cfgg(LINEAR)) {
+ ppost->di_diwr_mif.linear = 1;
+ ppost->di_diwr_mif.buf_crop_en = 1;
+ ppost->di_diwr_mif.buf_hsize =
+ di_buf->buf_hsize;//1920; tmp;
+ ppost->di_buf0_mif.linear = 1;
+ ppost->di_buf0_mif.buf_crop_en = 1;
+ ppost->di_buf0_mif.buf_hsize =
+ di_buf->buf_hsize; /*tmp*/;
+ ppost->di_buf1_mif.linear = 1;
+ ppost->di_buf1_mif.buf_crop_en = 1;
+ ppost->di_buf1_mif.buf_hsize =
+ di_buf->buf_hsize; /*tmp*/;
+ ppost->di_buf2_mif.linear = 1;
+ ppost->di_buf2_mif.buf_crop_en = 1;
+ ppost->di_buf2_mif.buf_hsize =
+ di_buf->buf_hsize; /*tmp*/;
+
+ ppost->di_mtnprd_mif.linear = 1;
+ ppost->di_mcvecrd_mif.linear = 1;
+ }
}
pst->last_pst_size = ((di_width - 1) | ((di_height - 1) << 16));
#ifdef DIM_OUT_NV21
/* nv 21*/
+ if ((di_buf->flg_nv21 == 2) || cfggch(pch, IOUT_FMT) == 2)
+ ppost->di_diwr_mif.cbcr_swap = 1;
+ else
+ ppost->di_diwr_mif.cbcr_swap = 0;
+
+ if (dip_itf_is_o_linear(pch) &&
+ (cfggch(pch, IOUT_FMT) == 2 ||
+ cfggch(pch, IOUT_FMT) == 1)) {
+ ppost->di_diwr_mif.reg_swap = 0;
+ ppost->di_diwr_mif.l_endian = 1;
+ } else {
+ ppost->di_diwr_mif.reg_swap = 1;
+ ppost->di_diwr_mif.l_endian = 0;
+ }
+ dbg_r = dim_get_dbg_dec21();
+ if (dbg_r & 0xf0) {
+ ppost->di_diwr_mif.reg_swap = bget(&dbg_r, 4);
+ ppost->di_diwr_mif.l_endian = bget(&dbg_r, 5);
+ ppost->di_diwr_mif.cbcr_swap = bget(&dbg_r, 6);
+ }
+ dim_print("%s1:reg_swap[%d],%d,%d\n", __func__,
+ ppost->di_diwr_mif.reg_swap,
+ dip_itf_is_o_linear(pch),
+ di_buf->flg_nv21);
if (DIM_IS_IC_EF(SC2))
opl1()->wr_cfg_mif(&ppost->di_diwr_mif,
EDI_MIFSM_WR,
}
} else if (di_buf->vframe->type & VIDTYPE_VIU_422) {
if (DIM_IS_IC_EF(SC2)) {
- if (opl1()->info.main_version == 3) {
+ if (opl1()->info.main_version >= 3) {
ppost->di_buf0_mif.video_mode = 1;
ppost->di_buf1_mif.video_mode = 1;
ppost->di_buf2_mif.video_mode = 1;
if (ppost->buf_type == VFRAME_TYPE_IN &&
!(di_buf->di_buf_dup_p[0]->vframe->type &
VIDTYPE_VIU_FIELD)) {
- if (di_buf->vframe->type & VIDTYPE_VIU_NV21) {
+ if ((di_buf->vframe->type & VIDTYPE_VIU_NV21) ||
+ (di_buf->vframe->type & VIDTYPE_VIU_NV12)) {
ppost->di_buf0_mif.set_separate_en = 1;
ppost->di_buf1_mif.set_separate_en = 1;
ppost->di_buf2_mif.set_separate_en = 1;
ppost->di_buf2_mif.luma_x_start0 = di_start_x;
ppost->di_buf2_mif.luma_x_end0 = di_end_x;
+ ppost->di_buf0_mif.reg_swap = 1;
+ ppost->di_buf0_mif.l_endian = 0;
+ ppost->di_buf0_mif.cbcr_swap = 0;
+
+ ppost->di_buf1_mif.reg_swap = 1;
+ ppost->di_buf1_mif.l_endian = 0;
+ ppost->di_buf1_mif.cbcr_swap = 0;
+ ppost->di_buf2_mif.reg_swap = 1;
+ ppost->di_buf2_mif.l_endian = 0;
+ ppost->di_buf2_mif.cbcr_swap = 0;
if (dimp_get(edi_mp_post_wr_en) &&
dimp_get(edi_mp_post_wr_support)) {
if (de_devp->pps_enable &&
ppost->di_mtnprd_mif.end_x = di_end_x;
ppost->di_mtnprd_mif.start_y = di_start_y >> 1;
ppost->di_mtnprd_mif.end_y = di_end_y >> 1;
+ ppost->di_mtnprd_mif.per_bits = 4;
if (dimp_get(edi_mp_mcpre_en)) {
ppost->di_mcvecrd_mif.start_x = di_start_x / 5;
mv_offset = (di_start_x % 5) ? (5 - di_start_x % 5) : 0;
(di_end_x + 1 + 4) / 5 - 1 - di_start_x / 5;
ppost->di_mcvecrd_mif.end_y =
(di_end_y >> 1);
+ ppost->di_mcvecrd_mif.per_bits = 16;
}
ppost->update_post_reg_flag = 1;
/* if height decrease, mtn will not enough */
di_buf->di_buf_dup_p[0]->nr_canvas_idx;
ppost->di_buf2_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[2]->nr_canvas_idx;
+ //t7
+ ppost->di_buf0_mif.addr0 = di_buf->di_buf_dup_p[1]->nr_adr;
+ ppost->di_buf1_mif.addr0 =
+ di_buf->di_buf_dup_p[0]->nr_adr;
+ ppost->di_buf2_mif.addr0 =
+ di_buf->di_buf_dup_p[2]->nr_adr;
+
/* afbc dec */
acfg->buf_mif[0] = di_buf->di_buf_dup_p[1];
acfg->buf_mif[1] = di_buf->di_buf_dup_p[0];
/************/
ppost->di_mtnprd_mif.canvas_num =
di_buf->di_buf_dup_p[2]->mtn_canvas_idx;
+ ppost->di_mtnprd_mif.addr = di_buf->di_buf_dup_p[2]->mtn_adr;
/*mc_pre_flag = is_meson_txl_cpu()?2:(overturn?0:1);*/
if (is_meson_txl_cpu() && overturn) {
/* swap if1&if2 mean negation of mv for normal di*/
if (dimp_get(edi_mp_mcpre_en)) {
ppost->di_mcvecrd_mif.canvas_num =
di_buf->di_buf_dup_p[2]->mcvec_canvas_idx;
+ ppost->di_mcvecrd_mif.addr =
+ di_buf->di_buf_dup_p[2]->mcvec_adr;
}
blend_mtn_en = 1;
ei_en = 1;
ppost->di_buf2_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[0]->nr_canvas_idx;
+ ppost->di_buf0_mif.addr0 =
+ di_buf->di_buf_dup_p[1]->nr_adr;
+ ppost->di_buf1_mif.addr0 =
+ di_buf->di_buf_dup_p[2]->nr_adr;
+ ppost->di_buf2_mif.addr0 =
+ di_buf->di_buf_dup_p[0]->nr_adr;
+
/* afbc dec */
acfg->buf_mif[0] = di_buf->di_buf_dup_p[1];
acfg->buf_mif[1] = di_buf->di_buf_dup_p[2];
/************/
ppost->di_mtnprd_mif.canvas_num =
di_buf->di_buf_dup_p[2]->mtn_canvas_idx;
+ ppost->di_mtnprd_mif.addr =
+ di_buf->di_buf_dup_p[2]->mtn_adr;
if (is_meson_txl_cpu() && overturn) {
ppost->di_buf1_mif.canvas0_addr0 =
ppost->di_buf2_mif.canvas0_addr0;
if (dimp_get(edi_mp_mcpre_en)) {
ppost->di_mcvecrd_mif.canvas_num =
di_buf->di_buf_dup_p[2]->mcvec_canvas_idx;
+ ppost->di_mcvecrd_mif.addr =
+ di_buf->di_buf_dup_p[2]->mcvec_adr;
mc_pre_flag = is_meson_txl_cpu() ? 0 :
(overturn ? 1 : 0);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
di_buf->di_buf_dup_p[1]->nr_canvas_idx;
ppost->di_buf1_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[0]->nr_canvas_idx;
+ //t7
+ ppost->di_buf0_mif.addr0 =
+ di_buf->di_buf_dup_p[1]->nr_adr;
+ ppost->di_buf1_mif.addr0 =
+ di_buf->di_buf_dup_p[0]->nr_adr;
/* afbc dec */
acfg->buf_mif[0] = di_buf->di_buf_dup_p[1];
acfg->buf_mif[1] = di_buf->di_buf_dup_p[0];
/************/
ppost->di_mtnprd_mif.canvas_num =
di_buf->di_buf_dup_p[2]->mtn_canvas_idx;
+ ppost->di_mtnprd_mif.addr =
+ di_buf->di_buf_dup_p[2]->mtn_adr;
post_blend_mode = 0;
blend_mtn_en = 1;
ei_en = 1;
== VIDTYPE_INTERLACE_TOP ? 0 : 1;
ppost->di_buf0_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[1]->nr_canvas_idx;
+ //t7:
+ ppost->di_buf0_mif.addr0 =
+ di_buf->di_buf_dup_p[1]->nr_adr;
ppost->di_mtnprd_mif.canvas_num =
di_buf->di_buf_dup_p[1]->mtn_canvas_idx;
+ ppost->di_mtnprd_mif.addr =
+ di_buf->di_buf_dup_p[1]->mtn_adr;
ppost->di_buf1_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[0]->nr_canvas_idx;
-
+ ppost->di_buf1_mif.addr0 =
+ di_buf->di_buf_dup_p[0]->nr_adr;
/* afbc dec */
acfg->buf_mif[0] = di_buf->di_buf_dup_p[1];
acfg->buf_mif[1] = di_buf->di_buf_dup_p[0];
if (di_buf->di_buf_dup_p[1]) {
ppost->di_buf0_mif.canvas0_addr0 =
di_buf->di_buf_dup_p[1]->nr_canvas_idx;
+ ppost->di_buf0_mif.addr0 =
+ di_buf->di_buf_dup_p[1]->nr_adr;
/* afbc dec */
acfg->buf_mif[0] = di_buf->di_buf_dup_p[1];
acfg->buf_mif[1] = NULL;
cvs_nv21[1] = cvss->post_idx[1][0];
dim_canvas_set2(&pst->vf_post, &cvs_nv21[0]);
ppost->di_diwr_mif.canvas_num = pst->vf_post.canvas0Addr;
+ ppost->di_diwr_mif.addr =
+ pst->vf_post.canvas0_config[0].phy_addr;
+ ppost->di_diwr_mif.addr1 =
+ pst->vf_post.canvas0_config[1].phy_addr;
+
ppost->di_diwr_mif.ddr_en = 1;
#endif
is_meson_tm2_cpu() ||
is_meson_sm1_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
DIM_IS_IC_EF(SC2)) {
if (di_cfg_top_get(EDI_CFG_REF_2) &&
mc_pre_flag &&
dim_ddbg_mod_save(EDI_DBG_MOD_POST_SETE, channel, ppost->frame_cnt);
dbg_post_cnt(channel, "ps2");
ppost->frame_cnt++;
+ ppost->seq++;
+ pch->sum_pst++;
return 0;
}
{
struct vframe_s *vframe_ret = NULL;
struct di_buf_s *nr_buf = NULL;
+ #ifdef VFM_ORI
struct vframe_s **pvframe_in = get_vframe_in(ch);
+ #else
+ struct dim_nins_s *ins;
+ #endif
struct vframe_s *vf;
-#ifdef DIM_OUT_NV21
+
struct di_hpst_s *pst = get_hw_pst();
-#endif
+ struct di_ch_s *pch;
+ struct di_buffer *buffer;
+ struct di_buf_s *buf_in;
+
+ pch = get_chdata(ch);
vframe_ret = di_buf->vframe;
nr_buf = di_buf->di_buf_dup_p[1];
/* 2019-04-22 Suggestions from brian.zhu*/
vframe_ret->mem_handle = NULL;
vframe_ret->type |= VIDTYPE_DI_PW;
+ #ifdef VFRAME_FLAG_DI_PW_VFM
+ vframe_ret->flag &=
+ ~(VFRAME_FLAG_DI_PW_VFM |
+ VFRAME_FLAG_DI_PW_N_LOCAL |
+ VFRAME_FLAG_DI_PW_N_EXT);
+ if (dip_itf_is_vfm(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_VFM;
+ else if (dip_itf_is_ins_lbuf(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_LOCAL;
+ else
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_EXT;
+ #endif
+ if (!dip_itf_is_o_linear(pch))
+ vframe_ret->flag &= (~VFRAME_FLAG_VIDEO_LINEAR);
+
/* 2019-04-22 */
/* dec vf keep */
if (di_buf->in_buf) {
vframe_ret->flag |= VFRAME_FLAG_DOUBLE_FRAM;
- vframe_ret->vf_ext = pvframe_in[di_buf->in_buf->index];
+ //vframe_ret->vf_ext =
+ //pvframe_in[di_buf->in_buf->index];
+ if (dip_itf_is_vfm(pch)) {
+ ins = (struct dim_nins_s *)di_buf->in_buf->c.in;
+ vframe_ret->vf_ext = ins->c.ori;
+ } else {
+ ins = (struct dim_nins_s *)di_buf->in_buf->c.in;
+ buffer = (struct di_buffer *)ins->c.ori;
+ vframe_ret->vf_ext = buffer->vf;
+ }
+
if (vframe_ret->vf_ext) {
- vf = pvframe_in[di_buf->in_buf->index];
+ //vf = pvframe_in[di_buf->in_buf->index];
+ vf = &ins->c.vfm_cp; //@ary_note: need change
if (vf->type & VIDTYPE_COMPRESS) {
vf->width = di_buf->dw_width_bk;
vf->height = di_buf->dw_height_bk;
di_buf->index, di_buf->in_buf->index);
}
}
+ if (dimp_get(edi_mp_force_width)) {
+ if (IS_COMP_MODE(di_buf->vframe->type)) {
+ vframe_ret->compWidth =
+ dimp_get(edi_mp_force_width);
+ } else {
+ vframe_ret->width =
+ dimp_get(edi_mp_force_width);
+ }
+ }
/* dbg_vfm(vframe_ret, 2);*/
} else if (di_buf->flg_nr) {
vframe_ret->mem_handle = NULL;
vframe_ret->type |= VIDTYPE_DI_PW;
+ #ifdef VFRAME_FLAG_DI_PW_VFM
+ vframe_ret->flag &=
+ ~(VFRAME_FLAG_DI_PW_VFM |
+ VFRAME_FLAG_DI_PW_N_LOCAL |
+ VFRAME_FLAG_DI_PW_N_EXT);
+ if (dip_itf_is_vfm(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_VFM;
+ else if (dip_itf_is_ins_lbuf(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_LOCAL;
+ else
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_EXT;
+ #endif
+ if (!dip_itf_is_o_linear(pch))
+ vframe_ret->flag &= (~VFRAME_FLAG_VIDEO_LINEAR);
if (di_buf->flg_nv21) {
//vframe_ret->plane_num = di_buf->vframe->plane_num;
vframe_ret->canvas0Addr = -1;
/* dec vf keep */
if (di_buf->in_buf) {
vframe_ret->flag |= VFRAME_FLAG_DOUBLE_FRAM;
- vframe_ret->vf_ext = pvframe_in[di_buf->in_buf->index];
+ if (dip_itf_is_vfm(pch)) {
+ ins = (struct dim_nins_s *)di_buf->in_buf->c.in;
+ vframe_ret->vf_ext = ins->c.ori;
+ } else {
+ ins = (struct dim_nins_s *)di_buf->in_buf->c.in;
+ buffer = (struct di_buffer *)ins->c.ori;
+ vframe_ret->vf_ext = buffer->vf;
+ }
+
if (vframe_ret->vf_ext) {
- vf = pvframe_in[di_buf->in_buf->index];
+ //vf = pvframe_in[di_buf->in_buf->index];
+ vf = &ins->c.vfm_cp; //@ary_note:need change
if (vf->type & VIDTYPE_COMPRESS) {
vf->width = di_buf->dw_width_bk;
vf->height = di_buf->dw_height_bk;
di_buf->index, di_buf->in_buf->index);
}
}
+ } else if (di_buf->is_bypass_pst) {
+ if (di_buf->di_buf_dup_p[0] &&
+ di_buf->di_buf_dup_p[0]->type == 2) {
+ buf_in = di_buf->di_buf_dup_p[0];
+ PR_INF("post bypass:\n");
+ vframe_ret->mem_handle = NULL;
+ #ifdef VFRAME_FLAG_DI_PW_VFM
+ if (dip_itf_is_vfm(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_VFM;
+ else if (dip_itf_is_ins_lbuf(pch))
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_LOCAL;
+ else
+ vframe_ret->flag |= VFRAME_FLAG_DI_PW_N_EXT;
+ #endif
+ if (!dip_itf_is_o_linear(pch))
+ vframe_ret->flag &= (~VFRAME_FLAG_VIDEO_LINEAR);
+ vframe_ret->type |= VIDTYPE_DI_PW;
+ vframe_ret->type &= (~0xf);
+ vframe_ret->plane_num = 1;
+ di_buf->buf_hsize = buf_in->buf_hsize;
+ if (IS_COMP_MODE(di_buf->vframe->type)) {
+ vframe_ret->compHeight =
+ buf_in->vframe->compHeight / 2;
+ } else {
+ vframe_ret->height = buf_in->vframe->height / 2;
+ vframe_ret->canvas0_config[0].phy_addr =
+ buf_in->nr_adr;
+ vframe_ret->canvas0_config[0].width =
+ buf_in->canvas_width[0];
+ vframe_ret->canvas0_config[0].block_mode = 0;
+ }
+ if (dimp_get(edi_mp_force_width)) {
+ if (IS_COMP_MODE(di_buf->vframe->type))
+ vframe_ret->compWidth =
+ dimp_get(edi_mp_force_width);
+ else
+ vframe_ret->width =
+ dimp_get(edi_mp_force_width);
+ }
+ PR_INF("\t:buf[%d,%d],vfm[%d,%d,0x%x]\n",
+ di_buf->type, di_buf->index,
+ di_buf->vframe->width, di_buf->vframe->height,
+ di_buf->vframe->type);
+ #ifdef CVS_UINT
+ PR_INF("\t:0x%x,0x%x\n",
+ di_buf->vframe->canvas0_config[0].phy_addr,
+ di_buf->vframe->canvas0_config[1].phy_addr);
+ #else
+ PR_INF("\t:0x%lx,0x%lx\n",
+ di_buf->vframe->canvas0_config[0].phy_addr,
+ di_buf->vframe->canvas0_config[1].phy_addr);
+ #endif
+ PR_INF("\t:cmp[%d,%d]\n", di_buf->vframe->compWidth,
+ di_buf->vframe->compHeight);
+ PR_INF("\t:0x%x,0x%x\n",
+ di_buf->vframe->compBodyAddr,
+ di_buf->vframe->compHeadAddr);
+ }
+
+ } else {
+ dim_print("%s:c\n", __func__);
+ }
+ if (dip_itf_is_ins_exbuf(pch)) {
+ vframe_ret->type &= (~VIDTYPE_DI_PW);
+ } else {
+ #ifdef MARK_HIS
+ if ((vframe_ret->type & VIDTYPE_DI_PW) &&
+ cfgg(LINEAR) &&
+ !IS_COMP_MODE(vframe_ret->type)) {
+ vframe_ret->canvas0_config[0].width = di_buf->buf_hsize;
+ vframe_ret->canvas0_config[1].width = di_buf->buf_hsize;
+ dbg_ic("set w buf_size[%d]:\n", di_buf->buf_hsize);
+ }
+ #endif
}
}
#endif
void dim_post_de_done_buf_config(unsigned int channel)
{
- ulong irq_flag2 = 0;
+ //2020-12-07 ulong irq_flag2 = 0;
struct di_buf_s *di_buf = NULL;
struct di_post_stru_s *ppost = get_post_stru(channel);
struct di_dev_s *de_devp = get_dim_de_devp();
+ struct di_ch_s *pch;
+ unsigned int datacrc = 0xffffffff;
if (!ppost->cur_post_buf) {
PR_ERR("%s:no cur\n", __func__);
return;
}
+ pch = get_chdata(channel);
dbg_post_cnt(channel, "pd1");
/*dbg*/
dim_ddbg_mod_save(EDI_DBG_MOD_POST_DB, channel, ppost->frame_cnt);
di_buf = ppost->cur_post_buf;
- di_lock_irqfiq_save(irq_flag2);
+ //2020-12-07 di_lock_irqfiq_save(irq_flag2);
queue_out(channel, ppost->cur_post_buf);/*? which que?post free*/
if (de_devp->pps_enable && dimp_get(edi_mp_pps_position) == 0) {
di_buf->is_lastp = 0;
}
- di_que_in(channel, QUE_POST_READY, ppost->cur_post_buf);
+ //ary 2020-12-07di_que_in(channel, QUE_POST_READY, ppost->cur_post_buf);
#ifdef DI_DEBUG_POST_BUF_FLOW
#else
/*add by ary:*/
- recycle_post_ready_local(ppost->cur_post_buf, channel);
+ if (!di_buf->is_bypass_pst)
+ recycle_post_ready_local(ppost->cur_post_buf, channel);
#endif
- di_unlock_irqfiq_restore(irq_flag2);
+ //2020-12-07 di_unlock_irqfiq_restore(irq_flag2);
dim_tr_ops.post_ready(di_buf->vframe->index_disp);
+ if (dimp_get(edi_mp_pstcrc_ctrl) == 1) {
+ if (DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D)) {
+ datacrc = RD(DI_T5_RO_CRC_DEINT);
+ DIM_DI_WR_REG_BITS(DI_T5_CRC_CHK0,
+ 0x1, 30, 1);
+ } else if (DIM_IS_IC_EF(SC2)) {
+ datacrc = RD(DI_RO_CRC_DEINT);
+ DIM_DI_WR_REG_BITS(DI_CRC_CHK0,
+ 0x1, 30, 1);
+ }
+ dbg_post_ref("DEINT ==ch[=0x%x]\n", datacrc);
+ //dbg_post_ref("irq p= 0x%p\n",ppost->cur_post_buf);
+ ppost->cur_post_buf->datacrc = datacrc;
+ }
+ pch->itf.op_fill_ready(pch, ppost->cur_post_buf);
+ mtask_wake_m();
+ #ifdef MARK_HIS//2020-12-07 move to ndis_fill_ready
pw_vf_notify_receiver(channel,
VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ #endif
ppost->cur_post_buf = NULL;
/*dbg*/
dim_ddbg_mod_save(EDI_DBG_MOD_POST_DE, channel, ppost->frame_cnt);
unsigned int channel)
{
int i;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
struct di_ch_s *pch = get_chdata(channel);
bool release_flg = false;
+ bool sct_buf = false;//for sct
if (!di_buf) {
PR_ERR("%s:\n", __func__);
dim_print("%s: ch[%d]:di_buf[%d],type=%d\n", __func__,
channel, di_buf->di_buf[i]->index,
di_buf->di_buf[i]->type);
+ if (dimp_get(edi_mp_bypass_post_state)) {
+ PR_INF("%s: ch[%d]:di_buf[%d],type=%d\n",
+ __func__,
+ channel, di_buf->di_buf[i]->index,
+ di_buf->di_buf[i]->type);
+ }
}
}
queue_out(channel, di_buf); /* remove it from display_list_head */
mm = dim_mm_get(channel);
if (di_buf->blk_buf) {
if (di_buf->blk_buf->flg.d32 != mm->cfg.pbuf_flg.d32) {
- if (di_buf->pat_buf) {
- qpat_in_ready(pch,
- (struct dim_pat_s *)di_buf->pat_buf);
- di_buf->pat_buf = NULL;
- }
mem_release_one_inused(pch, di_buf->blk_buf);
dbg_mem2("keep_buf:3:flg trig realloc,0x%x->0x%x\n",
di_buf->blk_buf->flg.d32,
di_que_in(channel, QUE_PST_NO_BUF, di_buf);
release_flg = true;
mm->sts.flg_realloc++;
+ dbg_mem2("%s:stsflg_realloc[%d]\n", __func__,
+ mm->sts.flg_realloc);
+ } else if (di_buf->blk_buf->flg.b.typ == EDIM_BLK_TYP_PSCT) {
+ if (di_buf->blk_buf->sct) {
+ qsct_used_some_to_recycle(pch,
+ (struct dim_sct_s *)di_buf->blk_buf->sct);
+ di_buf->blk_buf->sct = NULL;
+ di_buf->blk_buf->pat_buf = NULL;
+ di_que_in(channel, QUE_PST_NO_BUF_WAIT, di_buf);
+ sct_buf = true;
+ }
}
} else {
release_flg = true;
di_que_in(channel, QUE_PST_NO_BUF, di_buf);
}
- if (!release_flg)
+ if ((!release_flg) && (!sct_buf))
di_que_in(channel, QUE_POST_FREE, di_buf);
}
static void drop_frame(int check_drop, int throw_flag, struct di_buf_s *di_buf,
unsigned int channel)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
int i = 0, drop_flag = 0;
struct di_post_stru_s *ppost = get_post_stru(channel);
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
if (frame_count == 0 && check_drop) {
ppost->start_pts = di_buf->vframe->pts;
ppost->start_pts64 = di_buf->vframe->pts_us64;
//queue_in(channel, di_buf, QUEUE_POST_DOING);
di_que_in(channel, QUE_POST_DOING, di_buf);
} else {
- di_que_in(channel, QUE_POST_READY, di_buf);
+ //no use di_que_in(channel, QUE_POST_READY, di_buf);
}
dim_tr_ops.post_do(di_buf->vframe->index_disp);
dim_print("di:ch[%d]:%dth %s[%d] => post ready %u ms.\n",
jiffies_to_msecs(jiffies_64 -
di_buf->vframe->ready_jiffies64));
}
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
+}
+
+static bool dim_pst_vfm_bypass(struct di_ch_s *pch, struct di_buf_s *ready_buf)
+{
+ unsigned int ch;
+ struct di_buf_s *di_buf, *p;
+
+ ch = pch->ch_id;
+ if (ready_buf && ready_buf->is_eos && !ready_buf->c.in) {
+ /* int eos */
+ dbg_bypass("%s:only int eos\n", __func__);
+ p = di_que_out_to_di_buf(ch, QUE_PRE_READY);
+ p->is_eos = 0;
+ queue_in(ch, p, QUEUE_RECYCLE);
+ return true;
+ }
+
+ //dbg_bypass("%s:1\n", __func__);
+ di_buf = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF);
+ if (dim_check_di_buf(di_buf, 19, ch)) {
+ PR_ERR("%s:no pst_no_buf", __func__);
+ return false;
+ }
+ //dbg_bypass("%s:2\n", __func__);
+ p = di_que_out_to_di_buf(ch, QUE_PRE_READY);
+ //dbg_bypass("%s:3\n", __func__);
+ di_buf->di_buf_dup_p[0] = p;
+ di_buf->di_buf_dup_p[1] = NULL;
+ di_buf->di_buf_dup_p[2] = NULL;
+ di_buf->process_fun_index = PROCESS_FUN_NULL;
+ di_buf->is_nbypass = p->is_nbypass;
+ //dbg_bypass("%s:4\n", __func__);
+ di_que_in(ch, QUE_POST_DOING, di_buf);
+ //dbg_bypass("%s:5\n", __func__);
+ //dbg_bypass("%s:0x%px:%d,%d\n", __func__, p, p->type, p->index);
+ //dbg_bypass("%s:\n", __func__);
+ return true;
}
int dim_process_post_vframe(unsigned int channel)
* 2) get buf from pre_ready_list, attach it to buf from post_free_list
* (it will be send to recycle_list in di_vf_put() )
*/
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
int i = 0;
int tmp = 0;
int tmp0 = 0;
struct di_ch_s *pch = get_chdata(channel);
struct di_buf_s *tmp_buf[3];
bool flg_eos = false;
+ //struct dim_nins_s *nins; //add for eos
+
#ifdef MARK_SC2 /* */
if (di_que_is_empty(channel, QUE_POST_FREE))
return 0;
for (itmp = 0; itmp < psize; itmp++) {
p = pw_qindex_2_buf(channel, tmpa[itmp]);
/* if(p->post_proc_flag == 0){ */
+ #ifdef HIS_CODE
if (p->type == VFRAME_TYPE_IN) {
ready_di_buf->post_proc_flag = -1;
ready_di_buf->new_format_flag = 1;
}
+ #endif
if (p->is_eos)
flg_eos = true;
i++;
}
}
if (ready_count == 1 && ready_di_buf->is_eos) {
- PR_INF("only eos:do noting\n");
- ready_di_buf->is_eos = 0;
- queue_out(channel, ready_di_buf);
- di_que_in(channel, QUE_PRE_NO_BUF, ready_di_buf);
- PR_INF("eos:que out only one :t[%d]idx[%d]\n",
- ready_di_buf->type,
- ready_di_buf->index);
+ PR_INF("%s:only eos\n", __func__);
+ dim_pst_vfm_bypass(pch, ready_di_buf);
return 1;
}
+ if (ready_di_buf->is_nbypass) {
+ dbg_bypass("%s:bypass?\n", __func__);
+ dim_pst_vfm_bypass(pch, NULL);
+ return 1;
+ }
+
if (ready_di_buf->post_proc_flag > 0) {
if ((ready_count >= buffer_keep_count) && flg_eos) {
for (i = 0; i < 3; i++)
PR_ERR("%s: eos pst null\n", __func__);
return 0;
}
- dim_print("%s:eos:post_buf:t[%d]idx[%d]\n",
+ dbg_bypass("%s:eos:post_buf:t[%d]idx[%d]\n",
__func__, di_buf->type,
di_buf->index);
memcpy(di_buf->vframe,
di_buf->di_buf[0] = tmp_buf[0];
di_buf->di_buf[1] = tmp_buf[1];
+ di_buf->di_buf[0]->pre_ref_count = 0;
+ di_buf->di_buf[1]->pre_ref_count = 0;
queue_out(channel, tmp_buf[0]);
queue_out(channel, tmp_buf[1]);
PR_INF("eos:que out 0:t[%d]idx[%d]\n",
}
if (tmp_buf[2] && tmp_buf[2]->is_eos) {
+ #ifdef HIS_CODE
tmp_buf[2]->is_eos = 0;
queue_out(channel, tmp_buf[2]);
di_que_in(channel, QUE_PRE_NO_BUF, tmp_buf[2]);
+ #endif
+ dim_pst_vfm_bypass(pch, tmp_buf[2]);
PR_INF("eos:que out 2:t[%d]idx[%d]\n",
tmp_buf[2]->type, tmp_buf[2]->index);
} else {
PR_ERR("tmp_buf[2] is not eos\n");
}
} else if (ready_count >= buffer_keep_count) {/* i ?*/
-#ifdef MARK_SC2
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = di_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dim_check_di_buf(di_buf, 17, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-#else
-
-#endif
i = 0;
di_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
di_buf->vframe->private_data = di_buf;
di_buf->afbc_sgn_cfg =
di_buf->di_buf_dup_p[1]->afbc_sgn_cfg;
+ memcpy(&di_buf->pq_rpt,
+ &di_buf->di_buf_dup_p[1]->pq_rpt,
+ sizeof(di_buf->pq_rpt));
if (di_buf->di_buf_dup_p[1]->post_proc_flag == 3) {
/* dummy, not for display */
inc_post_ref_count(di_buf);
di_buf->di_buf[0] = di_buf->di_buf_dup_p[0];
di_buf->di_buf[1] = NULL;
queue_out(channel, di_buf->di_buf[0]);
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
queue_in(channel, di_buf, QUEUE_TMP);
recycle_vframe_type_post(di_buf, channel);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
dim_print("%s <dummy>: ", __func__);
} else {
pw_vf_notify_receiver(channel,
VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
}
+ if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
+ dim_dbg_buffer2(di_buf->c.buffer, 5);
ret = 1;
}
} else {
//dim_print("%s:p as p\n", __func__);
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
queue_out(channel, ready_di_buf);
di_buf = pp_local_2_post(pch, ready_di_buf);
//di_que_out_to_di_buf(channel, QUE_POST_FREE);
if (dim_check_di_buf(di_buf, 19, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
return 0;
}
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
+ memcpy(&di_buf->pq_rpt, &ready_di_buf->pq_rpt,
+ sizeof(di_buf->pq_rpt));
di_buf->di_buf_dup_p[0] = di_buf;//ready_di_buf;
di_buf->di_buf_dup_p[1] = NULL;
di_buf->di_buf_dup_p[2] = NULL;
frame_count++;
ret = 1;
+#ifdef MARK_HIS
pw_vf_notify_receiver
(channel,
VFRAME_EVENT_PROVIDER_VFRAME_READY,
NULL);
-
+#endif
/******************************************************************************/
} else if (is_progressive(ready_di_buf->vframe) ||
if (ready_count >= vframe_process_count) {
struct di_buf_s *di_buf_i;
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
#ifdef MARK_SC2
di_buf = di_que_out_to_di_buf(channel, QUE_POST_FREE);
#else
di_buf = di_que_out_to_di_buf(channel, QUE_PST_NO_BUF);
#endif
if (dim_check_di_buf(di_buf, 19, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
return 0;
}
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
i = 0;
di_buf->dw_height_bk =
ready_di_buf->dw_height_bk;
di_buf->vframe->private_data = di_buf;
-
+ di_buf->is_nbypass = di_buf_i->is_nbypass;
+ if (dimp_get(edi_mp_bypass_post_state)) {
+ di_buf->is_bypass_pst = 1;
+ di_buf_i->pre_ref_count = 0;
+ di_buf->process_fun_index = 0;
+ //PROCESS_FUN_NULL;
+ PR_INF("%s:pst bypass buf[%d:%d]\n",
+ __func__,
+ di_buf->type, di_buf->index);
+ }
if (ready_di_buf->new_format_flag &&
ready_di_buf->type == VFRAME_TYPE_IN) {
pr_info("DI:ch[%d],%d disable post.\n",
do_pre_only_fun;
}
dim_print("%s:2\n", __func__);
- if (ready_di_buf->post_proc_flag == -2) {
+ if (di_buf->is_bypass_pst) {
+ di_buf->vframe->process_fun =
+ NULL;
+ } else if (ready_di_buf->post_proc_flag == -2) {
di_buf->vframe->type |=
VIDTYPE_VIU_FIELD;
di_buf->vframe->type &=
dim_print("%s <prog by frame>: ", __func__);
#endif
ret = 1;
+#ifdef MARK_HIS
pw_vf_notify_receiver
(channel,
VFRAME_EVENT_PROVIDER_VFRAME_READY,
NULL);
+#endif
}
} else if (ready_count >= 2) {
/*for progressive input,type
*/
unsigned char prog_tb_field_proc_type =
(dimp_get(edi_mp_prog_proc_config) >> 1) & 0x3;
-#ifdef MARK_SC2
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = di_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dim_check_di_buf(di_buf, 20, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
- di_unlock_irqfiq_restore(irq_flag2);
-#endif
i = 0;
di_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
dim_print("%s <prog by field>: ", __func__);
#endif
ret = 1;
+#ifdef MARK_HIS
pw_vf_notify_receiver
(channel,
VFRAME_EVENT_PROVIDER_VFRAME_READY,
NULL);
+#endif
}
}
{
/*unsigned int mirror_disable = get_blackout_policy();*/
unsigned int mirror_disable = 0;
+ struct di_dev_s *de_devp = get_dim_de_devp();
if (!get_hw_reg_flg()) {
PR_ERR("%s:have unsetting?do nothing\n", __func__);
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu()) {
dim_pre_gate_control(false, dimp_get(edi_mp_mcpre_en));
get_ops_nr()->nr_gate_control(false);
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu()) {
dimh_enable_di_post_mif(GATE_OFF);
dim_post_gate_control(false);
get_hw_pre()->pre_top_cfg.d32 = 0;
get_hw_pst()->last_pst_size = 0;
disp_frame_count = 0;/* debug only*/
+
+ /*set clkb to low ratio*/
+ if (DIM_IS_IC(T5) || DIM_IS_IC(T5D)) {
+ #ifdef CLK_TREE_SUPPORT
+ if (dimp_get(edi_mp_clock_low_ratio))
+ clk_set_rate(de_devp->vpu_clkb,
+ dimp_get(edi_mp_clock_low_ratio));
+ #endif
+ }
+ dbg_pl("%s:end\n", __func__);
}
void di_unreg_variable(unsigned int channel)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
unsigned int mirror_disable = 0;
struct di_pre_stru_s *ppre = get_pre_stru(channel);
struct di_dev_s *de_devp = get_dim_de_devp();
struct di_ch_s *pch = get_chdata(channel);
enum EDI_CMA_ST cma_st;
struct mtsk_cmd_s blk_cmd;
+ struct div2_mm_s *mm = dim_mm_get(channel);
#if (defined ENABLE_SPIN_LOCK_ALWAYS)
- ulong flags = 0;
+// ulong flags = 0;
+#endif
- spin_lock_irqsave(&plist_lock, flags);
+#if (defined ENABLE_SPIN_LOCK_ALWAYS)
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
#endif
pr_info("%s:\n", __func__);
set_init_flag(channel, false); /*init_flag = 0;*/
+ pch->itf.op_m_unreg(pch);
dim_sumx_clear(channel);
dim_polic_unreg(pch);
+ mm->sts.flg_realloc = 0;
+ dim_recycle_post_back(channel);// ?
/*mirror_disable = get_blackout_policy();*/
- mirror_disable = 0;
- di_lock_irqfiq_save(irq_flag2);
- dim_print("%s: dim_uninit_buf\n", __func__);
+ if ((cfgg(KEEP_CLEAR_AUTO) == 2) || dip_itf_is_ins_exbuf(pch))
+ mirror_disable = 1;
+ else
+ mirror_disable = 0;
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
+ //dim_print("%s: dim_uninit_buf\n", __func__);
pch->src_type = 0;
+ pch->ponly = 0;
dim_uninit_buf(mirror_disable, channel);
+ ndrd_reset(pch);
#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
if (di_pre_rdma_enable)
rdma_clear(de_devp->rdma_handle);
#endif
get_ops_mtn()->adpative_combing_exit();
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
#if (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plist_lock, flags);
+// spin_unlock_irqrestore(&plist_lock, flags);
#endif
dimh_patch_post_update_mc_sw(DI_MC_SW_REG, false);
+ sct_sw_off(pch);
ppre->force_unreg_req_flag = 0;
ppre->disable_req_flag = 0;
sum_p_clear(channel);
sum_pst_g_clear(channel);
sum_pst_p_clear(channel);
+ pch->sum_pre = 0;
+ pch->sum_pst = 0;
+ pch->sum_ext_buf_in = 0;
+ pch->sum_ext_buf_in2 = 0;
+ dbg_reg("ndis_used[%d], nout[%d],flg_realloc[%d]\n",
+ ndis_cnt(pch, QBF_NDIS_Q_USED),
+ ndrd_cnt(pch), mm->sts.flg_realloc);
dbg_reg("%s:end\n", __func__);
}
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu() ||
DIM_IS_IC_EF(SC2))
dim_film_mode_win_config(width, height);
dim_nr_ds_init(width, height);
if (de_devp->pps_enable && dimp_get(edi_mp_pps_position)) {
pps_w = ppre->cur_width;
- pps_h = ppre->cur_height >> 1;
- dim_pps_config(1, pps_w, pps_h,
- dimp_get(edi_mp_pps_dstw),
- (dimp_get(edi_mp_pps_dsth) >> 1));
+ if (vf_type & VIDTYPE_TYPEMASK) {
+ pps_h = ppre->cur_height >> 1;
+ dim_pps_config(1, pps_w, pps_h,
+ dimp_get(edi_mp_pps_dstw),
+ (dimp_get(edi_mp_pps_dsth) >> 1));
+ } else {
+ pps_h = ppre->cur_height;
+ dim_pps_config(1, pps_w, pps_h,
+ dimp_get(edi_mp_pps_dstw),
+ (dimp_get(edi_mp_pps_dsth)));
+ }
}
if (is_meson_sm1_cpu() || is_meson_tm2_cpu() ||
- DIM_IS_IC(T5) || DIM_IS_IC_EF(SC2)) {
+ DIM_IS_IC(T5) || DIM_IS_IC(T5D) || DIM_IS_IC_EF(SC2)) {
if (de_devp->h_sc_down_en) {
pps_w = ppre->cur_width;
tmp = di_mp_uit_get(edi_mp_pre_hsc_down_width);
#define DIM_BYPASS_VF_TYPE (VIDTYPE_MVC | VIDTYPE_VIU_444 | \
VIDTYPE_PIC | VIDTYPE_RGB_444)
+
+void dim_vf_x_y(struct vframe_s *vf, unsigned int *x, unsigned int *y)
+{
+ *x = 0;
+ *y = 0;
+
+ if (!vf)
+ return;
+ *x = vf->width;
+ *y = vf->height;
+
+ if (IS_COMP_MODE(vf->type)) {
+ *x = vf->compWidth;
+ *y = vf->compHeight;
+ }
+}
+
static unsigned int dim_bypass_check(struct vframe_s *vf)
{
unsigned int reason = 0;
+ unsigned int x, y;
if ((dimp_get(edi_mp_di_debug_flag) >> 20) & 0x1)
reason = 1;
if (reason || !vf)
return reason;
+ dim_vf_x_y(vf, &x, &y);
/*check vf*/
if (vf->type & DIM_BYPASS_VF_TYPE) {
reason = 2;
(vf->height > 1088))) {
reason = 9;
} else if (VFMT_IS_P(vf->type) &&
- (vf->width > default_width ||
- vf->height > (default_height + 8))) {
+ (x > default_width ||
+ y > (default_height + 8))) {
reason = 4;
#ifdef P_NOT_SUPPORT
} else if (VFMT_IS_P(vf->type)) {
if (dim_afds() && !dim_afds()->is_supported()) {
reason = 3;
} else {
- if ((vf->compHeight > (default_height + 8)) ||
- vf->compWidth > default_width) {
+ if ((y > (default_height + 8)) ||
+ x > default_width) {
reason = 5;
}
}
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu() ||
DIM_IS_IC_EF(SC2)) {
#ifdef CLK_TREE_SUPPORT
*********************************/
void di_reg_variable(unsigned int channel, struct vframe_s *vframe)
{
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
#ifndef RUN_DI_PROCESS_IN_IRQ
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
#endif
struct di_pre_stru_s *ppre = get_pre_stru(channel);
struct di_dev_s *de_devp = get_dim_de_devp();
struct di_ch_s *pch;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
#ifdef HIS_CODE
if (pre_run_flag != DI_RUN_FLAG_RUN &&
// di_set_default();
dip_init_value_reg(channel, vframe);/*add 0404 for post*/
dim_ddbg_mod_save(EDI_DBG_MOD_RVB, channel, 0);
- if (dim_need_bypass(channel, vframe)) {
- if (!ppre->bypass_flag) {
- PR_INF("%ux%u-0x%x.\n",
- vframe->width,
- vframe->height,
- vframe->type);
+ //if (!dip_itf_is_ins_exbuf(pch)) {
+ if (dip_itf_is_vfm(pch)) {
+ if (dim_need_bypass(channel, vframe)) {
+ if (!ppre->bypass_flag) {
+ PR_INF("%ux%u-0x%x.\n",
+ vframe->width,
+ vframe->height,
+ vframe->type);
+ }
+ ppre->bypass_flag = true;
+ ppre->sgn_lv = EDI_SGN_OTHER;
+ dimh_patch_post_update_mc_sw
+ (DI_MC_SW_OTHER, false);
+ return;
}
- ppre->bypass_flag = true;
- ppre->sgn_lv = EDI_SGN_OTHER;
- dimh_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- return;
}
dim_mp_update_reg();
ppre->bypass_flag = false;
/*(is_progressive(vframe) && (prog_proc_config & 0x10)) {*/
if (0) {
#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
#endif
- di_lock_irqfiq_save(irq_flag2);
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
/*
* 10 bit mode need 1.5 times buffer size of
* 8 bit mode, init the buffer size as 10 bit
*/
// di_init_buf(default_width, default_height, 1, channel);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
#endif
} else {
#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
#endif
- di_lock_irqfiq_save(irq_flag2);
+ //ary 2020-12-09 di_lock_irqfiq_save(irq_flag2);
/*
* 10 bit mode need 1.5 times buffer size of
* 8 bit mode, init the buffer size as 10 bit
#else
// di_init_buf(default_width, default_height, 0, channel);
#endif
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
#endif
}
+
+ if (mm->cfg.pbuf_flg.b.typ == EDIM_BLK_TYP_PSCT)
+ sct_sw_on(pch,
+ mm->cfg.num_post,
+ mm->cfg.pbuf_flg.b.tvp,
+ mm->cfg.pst_buf_size);
+
pre_sec_alloc(pch, mm->cfg.dat_idat_flg.d32);
pst_sec_alloc(pch, mm->cfg.dat_pafbct_flg.d32);
ppre->mtn_status =
- get_ops_mtn()->adpative_combing_config(vframe->width,
- (vframe->height >> 1),
- (vframe->source_type),
- is_progressive(vframe),
- vframe->sig_fmt);
+ get_ops_mtn()->adpative_combing_config
+ (vframe->width,
+ (vframe->height >> 1),
+ (vframe->source_type),
+ is_progressive(vframe),
+ vframe->sig_fmt);
dimh_patch_post_update_mc_sw(DI_MC_SW_REG, true);
di_sum_reg_init(channel);
*/
/*************************/
+void di_block_set(int val)
+{
+ di_blocking = val;
+}
+int di_block_get(void)
+{
+ return di_blocking;
+}
+
+#ifdef MARK_HIS//move to di_vframe
int di_ori_event_qurey_vdin2nr(unsigned int channel)
{
struct di_pre_stru_s *ppre = get_pre_stru(channel);
if (disp_frame_count == 1 && kpi_frame_num > 0) {
pr_dbg("[di_kpi] %s: 1st frame get success. %s[%d]:0x%p %u ms\n",
- __func__,
- vframe_type_name[di_buf->type],
- di_buf->index,
- vframe_ret,
- jiffies_to_msecs(jiffies_64 -
- vframe_ret->ready_jiffies64));
+ __func__,
+ vframe_type_name[di_buf->type],
+ di_buf->index,
+ vframe_ret,
+ jiffies_to_msecs(jiffies_64 -
+ vframe_ret->ready_jiffies64));
}
dim_tr_ops.post_get(vframe_ret->index_disp);
} else {
task_send_ready();
}
-
+#endif
void dim_recycle_post_back(unsigned int channel)
{
struct di_buf_s *di_buf = NULL;
- ulong irq_flag2 = 0;
+//ary 2020-12-09 ulong irq_flag2 = 0;
unsigned int i = 0;
if (di_que_is_empty(channel, QUE_POST_BACK))
}
dim_print("di_back:%d\n", di_buf->index);
- di_lock_irqfiq_save(irq_flag2); /**/
+//ary 2020-12-09 di_lock_irqfiq_save(irq_flag2); /**/
+ #ifdef MARK_HIS /*@ary_note: */
di_que_out(channel, QUE_POST_BACK, di_buf);
di_buf->queue_index = QUEUE_DISPLAY;
-
+ #endif
/*dec vf keep*/
if (di_buf->in_buf) {
dim_print("dim:dec vf:b:p[%d],i[%d]\n",
//di_buf->invert_top_bot_flag = 0;
//di_que_in(channel, QUE_POST_FREE, di_buf);
- di_unlock_irqfiq_restore(irq_flag2);
+//ary 2020-12-09 di_unlock_irqfiq_restore(irq_flag2);
}
if (di_cfg_top_get(EDI_CFG_KEEP_CLEAR_AUTO))
- dim_post_keep_release_all_2free(channel);
+ ;//dim_post_keep_release_all_2free(channel);
}
+#ifdef MARK_HIS
struct vframe_s *di_vf_l_peek(unsigned int channel)
{
struct vframe_s *vframe_ret = NULL;
/**************************/
dim_log_buffer_state("pek", channel);
-
if (!di_que_is_empty(channel, QUE_POST_READY)) {
di_buf = di_que_peek(channel, QUE_POST_READY);
if (di_buf)
int di_vf_l_states(struct vframe_states *states, unsigned int channel)
{
- struct di_mm_s *mm = dim_mm_get(channel);
+ struct div2_mm_s *mm = dim_mm_get(channel);
struct dim_sum_s *psumx = get_sumx(channel);
/*pr_info("%s: ch[%d]\n", __func__, channel);*/
}
return 0;
}
-
+#endif
/**********************************************/
/*****************************
PR_ERR("set pq parm errors\n");
return -EFAULT;
}
- if (tmp_pq_s.table_len >= TABLE_LEN_MAX) {
+ if (tmp_pq_s.table_len >= DIMTABLE_LEN_MAX) {
PR_ERR("load 0x%x wrong pq table_len.\n",
tmp_pq_s.table_len);
return -EFAULT;
tab_flag = TABLE_NAME_DI | TABLE_NAME_NR | TABLE_NAME_MCDI |
TABLE_NAME_DEBLOCK | TABLE_NAME_DEMOSQUITO;
- //tab_flag |= TABLE_NAME_SMOOTHPLUS; mark for t5 decont
+ //tab_flag |= TABLE_NAME_SMOOTHPLUS;//mark for undefine
if (tmp_pq_s.table_name & tab_flag) {
PR_INF("load 0x%x pq table len %u %s.\n",
tmp_pq_s.table_name, tmp_pq_s.table_len,
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu() ||
DIM_IS_IC_EF(SC2)) {
dimp_set(edi_mp_mcpre_en, 1);
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu() ||
DIM_IS_IC_EF(SC2)) {
dimp_set(edi_mp_full_422_pack, 1);
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D) ||
is_meson_sm1_cpu() ||
DIM_IS_IC_EF(SC2)) ? 10 : 17);
} else {
pldn_dly1 = 2;
}
- if (DIM_IS_IC(T5) || DIM_IS_IC(TM2B))
+ if (DIM_IS_IC(T5) || DIM_IS_IC(TM2B) || DIM_IS_IC(T5D) ||
+ DIM_IS_IC(T7))
di_cfg_set(ECFG_DIM_BYPASS_P, 0);//for t5 enable p
get_ops_mtn()->mtn_int_combing_glbmot();
if (DIM_IS_IC_EF(SC2))
vpu_clk = clk_get(dev, "vpu_clkb_tmp_mux");
- else if (DIM_IS_IC(T5))
+ else if (DIM_IS_IC(T5) || DIM_IS_IC(T5D))
vpu_clk = clk_get(dev, "t5_vpu_clkb_tmp_gate");
else
vpu_clk = clk_get(dev, "vpu_mux");
#ifdef CLK_TREE_SUPPORT
if (DIM_IS_IC_EF(SC2))
pdev->vpu_clkb = clk_get(dev, "vpu_clkb_gate");
- else if (DIM_IS_IC(T5))
+ else if (DIM_IS_IC(T5) || DIM_IS_IC(T5D))
pdev->vpu_clkb = clk_get(dev, "t5_vpu_clkb_gate");
else
pdev->vpu_clkb = clk_get(dev, "vpu_clkb_composite");
#include <linux/types.h>
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/vfm/vframe_provider.h>
+#include <linux/amlogic/media/di/di.h>
//#include "../di_local/di_local.h"
#include "di_local.h"
***********************************************/
#define DIM_OUT_NV21 (1)
//#define TEST_PIP (1)
+/************************************************
+ * from t7 cvs address is ulong
+ ************************************************/
+#define CVS_UINT (1)
/*trigger_pre_di_process param*/
#define TRIGGER_PRE_BY_PUT 'p'
};
#define pulldown_mode_t enum pulldown_mode_e
+
+struct dsub_bufv_s {
+ void *in; /* struct dim_nins_s */
+ bool in_noback; /* this is for dec reset */
+ bool src_is_i;
+ void *buffer; /*for new interface */
+};
+
struct di_buf_s {
struct vframe_s *vframe;
int index; /* index in vframe_in_dup[] or vframe_in[],
unsigned int width_bk; /*move from ppre*/
unsigned int dw_width_bk;
unsigned int dw_height_bk;
+ unsigned int buf_hsize; /* for t7 */
// unsigned int flg_tvp;
unsigned int afbc_info; /*bit 0: src is i; bit 1: src is real i */
unsigned char afbc_sgn_cfg;
struct di_win_s win; /*post write*/
struct di_buf_s *di_buf_post; /*07-27 */
unsigned long jiff; // for wait
+ struct dim_rpt_s pq_rpt;
enum EDI_SGN sgn_lv;
- void *pat_buf; /*2020-10-05*/
+// void *pat_buf; /*2020-10-05*/
void *iat_buf; /*2020-10-13*/
unsigned int buf_is_i : 1; /* 1: i; 0: p */
unsigned int flg_nr : 1;
unsigned int flg_null : 1;
- unsigned int flg_nv21 : 1;
+ unsigned int flg_nv21 : 2;
unsigned int is_4k : 1;
unsigned int is_eos : 1;
unsigned int is_lastp : 1;
unsigned int flg_afbce_set : 1;
unsigned int trig_post_update : 1;
- unsigned int rev1 : 7;
+ unsigned int afbce_out_yuv420_10 : 1; /* 2020-11-26*/
+ unsigned int is_nbypass : 1; /*2020-12-07*/
+ unsigned int is_bypass_pst : 1; /*2021-01-07*/
+ unsigned int rev1 : 4;
+
unsigned int rev2 : 16;
+ struct dsub_bufv_s c;
+ unsigned int datacrc;
};
#define RDMA_DET3D_IRQ 0x20
struct pst_cfg_afbc_s afbc_cfg;/* ary add for afbc dec*/
/*frame cnt*/
unsigned int frame_cnt; /*cnt for post process*/
+ unsigned int seq; /* 2021-01-13 */
// unsigned int last_pst_size;
union hw_sc2_ctr_pst_s pst_top_cfg;
union afbc_blk_s en_cfg;
};
unsigned char dim_is_bypass(vframe_t *vf_in, unsigned int channel);
-bool dim_bypass_first_frame(unsigned int ch);
+//bool dim_bypass_first_frame(unsigned int ch);
int di_cnt_buf(int width, int height, int prog_flag, int mc_mm,
int bit10_support, int pack422);
bool dim_need_bypass(unsigned int ch, struct vframe_s *vf);
/*--------------------------*/
-int di_ori_event_qurey_vdin2nr(unsigned int channel);
-int di_ori_event_reset(unsigned int channel);
-int di_ori_event_light_unreg(unsigned int channel);
-int di_ori_event_light_unreg_revframe(unsigned int channel);
-int di_ori_event_ready(unsigned int channel);
-int di_ori_event_qurey_state(unsigned int channel);
-void di_ori_event_set_3D(int type, void *data, unsigned int channel);
+//int di_ori_event_qurey_vdin2nr(unsigned int channel);
+//int di_ori_event_reset(unsigned int channel);
+//int di_ori_event_light_unreg(unsigned int channel);
+//int di_ori_event_light_unreg_revframe(unsigned int channel);
+//int di_ori_event_ready(unsigned int channel);
+//int di_ori_event_qurey_state(unsigned int channel);
+//void di_ori_event_set_3D(int type, void *data, unsigned int channel);
+void di_block_set(int val);
+int di_block_get(void);
+void di_lock_irqfiq_save(ulong irq_flag);
+void di_unlock_irqfiq_restore(ulong irq_flag);
+void di_lock_irq(void);
+void di_unlock_irq(void);
+
+int dump_state_flag_get(void);
+int di_get_kpi_frame_num(void);
/*--------------------------*/
extern int pre_run_flag;
unsigned char pre_p_asi_de_buf_config(unsigned int ch);
void dim_dbg_release_keep_all(unsigned int ch);
-void dim_post_keep_back_recycle(unsigned int ch);
+//void dim_post_keep_back_recycle(unsigned int ch);
void dim_post_re_alloc(unsigned int ch);
//void dim_post_release(unsigned int ch);
unsigned int dim_cfg_nv21(void);
char *buf);
ssize_t
store_kpi_frame_num(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len);
+ const char *buf, size_t len);
ssize_t dim_read_log(char *buf);
bool sc2_dbg_is_en_pst_irq(void);
void sc2_dbg_pre_info(unsigned int val);
void sc2_dbg_pst_info(unsigned int val);
-void hpre_timout_read(void);
+void hpre_timeout_read(void);
#define TEST_4K_NR (1)
//#define DBG_TEST_CRC (1)
//#define DBG_TEST_CRC_P (1)
/*split buffer alloc to i, p , idata, iafbc xxx */
#define CFG_BUF_ALLOC_SP (1)
+/*@ary_note: 2020-12-17*/
+/* */
+//#define TST_NEW_INS_INTERFACE (1)
+
+//#define TMP_TEST (1)
+
+//#define TMP_MASK_FOR_T7 (1)
#endif
mif->canvas0_addr0,
mif->canvas0_addr1,
mif->canvas0_addr2);
+ pr_info("linear:%d:addr <0x%lx 0x%lx 0x%lx>.\n",
+ mif->linear,
+ mif->addr0,
+ mif->addr1,
+ mif->addr2);
+}
+
+void dim_dump_mif_state(struct DI_MIF_S *mif, char *name)
+{
+ pr_info("%s:%s\n", __func__, name);
+ dump_mif_state(mif);
}
/*2018-08-17 add debugfs*/
mif->canvas0_addr0,
mif->canvas0_addr1,
mif->canvas0_addr2);
+ seq_printf(seq, "\tlinear[%d] addr <0x%lx 0x%lx 0x%lx>.\n",
+ mif->linear,
+ mif->addr0,
+ mif->addr1,
+ mif->addr2);
+ seq_printf(seq, "\tbuf_crop_en[%d] buf_hsize <%d> blk<%d>.\n",
+ mif->buf_crop_en,
+ mif->buf_hsize,
+ mif->block_mode);
seq_printf(seq, "\tbit_mode [%u] set_separate_en[%u]\n",
mif->bit_mode,
mif->set_separate_en);
seq_printf(seq, "\tsrc_field_mode [%u] output_field_num[%u]\n",
mif->src_field_mode,
mif->output_field_num);
+ seq_printf(seq, "\tl_endian [%d] cbcr_swap[%d] reg_swap[%d]\n",
+ mif->l_endian,
+ mif->cbcr_swap,
+ mif->reg_swap);
}
static void dump_simple_mif_state(struct DI_SIM_MIF_s *simp_mif)
simp_mif->start_y, simp_mif->end_y);
seq_printf(seq, "\tcanvas num <%u>.\n",
simp_mif->canvas_num);
+ seq_printf(seq, "\tlinear[%d] <0x%lx 0x%lx>.\n",
+ simp_mif->linear,
+ simp_mif->addr,
+ simp_mif->addr1);
+ seq_printf(seq, "\tper_bits[%d]\n",
+ simp_mif->per_bits);
+ seq_printf(seq, "\tbuf_crop_en[%d] buf_hsize <%d>.\n",
+ simp_mif->buf_crop_en,
+ simp_mif->buf_hsize);
seq_printf(seq, "\tbit_mode [%u] set_separate_en[%u]\n",
simp_mif->bit_mode,
simp_mif->set_separate_en);
simp_mif->ddr_en, simp_mif->src_i);
seq_printf(seq, "\ten [%u], cbcr_swap[%u]\n",
simp_mif->en, simp_mif->cbcr_swap);
+ seq_printf(seq, "\tl_endian [%d] cbcr_swap[%d] reg_swap[%d]\n",
+ simp_mif->l_endian,
+ simp_mif->cbcr_swap,
+ simp_mif->reg_swap);
}
static void dump_mc_mif_state(struct DI_MC_MIF_s *mc_mif)
mc_mif->start_x, mc_mif->start_y,
mc_mif->end_y, mc_mif->size_x,
mc_mif->size_y);
+ seq_printf(seq, "\tlinear[%d],addr[0x%lx]\n",
+ mc_mif->linear,
+ mc_mif->addr);
+ seq_printf(seq, "\tper_bits[%d]\n",
+ mc_mif->per_bits);
}
void dim_dump_pre_stru(struct di_pre_stru_s *ppre)
void dim_dump_crc_state(void)
{
- if (IS_IC(dil_get_cpuver_flag(), T5)) {
+ if (IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
pr_info("CRC_NRWR=0x%x\n", RD(DI_T5_RO_CRC_NRWR));
pr_info("CRC_MTNWR=0x%x\n", RD(DI_T5_RO_CRC_MTNWR));
pr_info("CRC_DEINT=0x%x\n", RD(DI_T5_RO_CRC_DEINT));
void dim_dump_pulldown_state(void)
{
- if (IS_IC(dil_get_cpuver_flag(), T5)) {
+ if (IS_IC(dil_get_cpuver_flag(), T5) ||
+ IS_IC(dil_get_cpuver_flag(), T5D)) {
pr_info("SUM_P=0x%x\n", RD(DI_T5_PD_RO_SUM_P));
pr_info("SUM_N=0x%x\n", RD(DI_T5_PD_RO_SUM_N));
pr_info("CNT_P=0x%x\n", RD(DI_T5_PD_RO_CNT_P));
/*2018-08-17 add debugfs*/
/*same as print_di_buf*/
-static void print_di_buf_seq(struct di_buf_s *di_buf, int format,
+void print_di_buf_seq(struct di_buf_s *di_buf, int format,
struct seq_file *seq)
{
if (!di_buf)
di_buf->vframe->duration,
di_buf->vframe->pts,
di_buf->vframe->bitdepth);
+ seq_printf(seq, "afbce 420 10 %d\n",
+ di_buf->afbce_out_yuv420_10);
if (di_buf->di_wr_linked_buf) {
seq_printf(seq, "linked index %d, 0x%p, type %d\n",
di_buf->di_wr_linked_buf->index,
di_buf->blk_buf->header.index,
di_buf->blk_buf->mem_start);
}
+ if (di_buf->pq_rpt.spt_bits) {
+ seq_printf(seq, "bits[0x%x], map0[0x%x], map1[0x%x],map2[0x%x],map3[0x%x],map15[0x%x],bld_2[0x%x]\n",
+ di_buf->pq_rpt.spt_bits,
+ di_buf->pq_rpt.dct_map_0,
+ di_buf->pq_rpt.dct_map_1,
+ di_buf->pq_rpt.dct_map_2,
+ di_buf->pq_rpt.dct_map_3,
+ di_buf->pq_rpt.dct_map_15,
+ di_buf->pq_rpt.dct_bld_2);
+ }
}
}
struct di_hpre_s *pre = get_hw_pre();
struct di_hpst_s *post = get_hw_pst();
char *splt = "---------------------------";
- struct di_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
+ struct div2_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
struct di_ch_s *pch = get_chdata(channel);
struct di_mng_s *pbm = get_bufmng();
seq_printf(seq, "bypass:is:%d,0x%x\n",
pch->bypass.b.is_bypass,
pch->bypass.b.reason_i);
-
+ seq_printf(seq, "cfg:4k:%d\n",
+ cfggch(pch, 4K));
seq_printf(seq, "recovery_flag = %d, reason=%d, di_blocking=%d",
recovery_flag, recovery_log_reason, di_blocking);
seq_printf(seq, "recovery_log_q_idx=%d, recovery_log_di_buf=0x%p\n",
print_di_buf_seq(p, 2, seq);
}
seq_printf(seq, "%s\n", splt);
+ /********************************/
+ /* pre_no_buf_list */
+ /********************************/
+ di_que_list(channel, QUE_PRE_NO_BUF, &tmpa[0], &psize); /*new que*/
+ seq_printf(seq, "pre_no_buf_list (max %d) (crr %d):\n",
+ MAX_LOCAL_BUF_NUM * 2, psize);
+ for (itmp = 0; itmp < psize; itmp++) { /*new que*/
+ p = pw_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
+ seq_printf(seq, "index %2d, 0x%p, type %d, vframetype 0x%x\n",
+ p->index, p, p->type, p->vframe->type);
+ if (p->blk_buf)
+ dbg_blk(seq, p->blk_buf);
+ }
+ seq_printf(seq, "%s\n", splt);
+
+ /********************************/
+ /* pst_no_buf_list */
+ /********************************/
+ di_que_list(channel, QUE_PST_NO_BUF, &tmpa[0], &psize); /*new que*/
+ seq_printf(seq, "pst_no_buf_list (max %d) (crr %d):\n",
+ MAX_POST_BUF_NUM, psize);
+ for (itmp = 0; itmp < psize; itmp++) { /*new que*/
+ p = pw_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
+
+ seq_printf(seq, "index %2d, 0x%p, type %d, vframetype 0x%x\n",
+ p->index, p, p->type, p->vframe->type);
+ if (p->blk_buf)
+ dbg_blk(seq, p->blk_buf);
+ }
+ seq_printf(seq, "%s\n", splt);
+ /********************************/
+ /* QUE_PST_NO_BUF_WAIT */
+ /********************************/
+ di_que_list(channel, QUE_PST_NO_BUF_WAIT, &tmpa[0], &psize); /*new que*/
+ seq_printf(seq, "pst_no_buf_wait_list (max %d) (crr %d):\n",
+ MAX_POST_BUF_NUM, psize);
+ for (itmp = 0; itmp < psize; itmp++) { /*new que*/
+ p = pw_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
+
+ seq_printf(seq, "index %2d, 0x%p, type %d, vframetype 0x%x\n",
+ p->index, p, p->type, p->vframe->type);
+ if (p->blk_buf)
+ dbg_blk(seq, p->blk_buf);
+ }
+ seq_printf(seq, "%s\n", splt);
/********************************/
/* post_free_list */
/********************************/
/********************************/
/* post_ready_list */
/********************************/
- di_que_list(channel, QUE_POST_READY, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
+ //di_que_list(channel, QUE_POST_READY, &tmpa[0], &psize); /*new que*/
+ seq_printf(seq, "post_ready_list: curr(%d)\n", ndrd_cnt(pch));
+ #ifdef MARK_HIS
for (itmp = 0; itmp < psize; itmp++) { /*new que*/
p = pw_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
print_di_buf_seq(p->di_buf[0], 1, seq);
print_di_buf_seq(p->di_buf[1], 1, seq);
}
+ #endif
+ //crash ndrd_dbg_list_buf(seq, pch);
seq_printf(seq, "%s\n", splt);
/********************************/
}
seq_printf(seq, "%s\n", splt);
+#ifdef MARK_HIS
/********************************/
/* post keep */
/********************************/
seq_printf(seq, "\ttype[%d],index[%d]\n", p->type, p->index);
}
seq_printf(seq, "%s\n", splt);
-
+#endif
+#ifdef MARK_HIS
/********************************
* post keep back
********************************/
seq_printf(seq, "\ttype[%d],index[%d]\n", p->type, p->index);
}
seq_printf(seq, "%s\n", splt);
-
+#endif
/********************************
* post keep back release alloc
********************************/
get_sum_pst_g(channel));
seq_printf(seq, "%-15s=%d\n", "pst_put_sum",
get_sum_pst_p(channel));
+ seq_printf(seq, "%-15s=%d\n", "sum_pre",
+ pch->sum_pre);
+ seq_printf(seq, "%-15s=%d\n", "sum_pst",
+ pch->sum_pst);
+ seq_printf(seq, "%-15s=%d\n", "sum_ext_buf_in",
+ pch->sum_ext_buf_in);
+ seq_printf(seq, "%-15s=%d\n", "sum_ext_buf_in2",
+ pch->sum_ext_buf_in2);
seq_printf(seq, "%-15s=%d\n", "sum_alloc_release",
get_mtask()->fcmd[channel].sum_alloc);
+ seq_printf(seq, "%-15s=%d\n", "npst_cnt",
+ npst_cnt(pch));
dump_state_flag = 0;
return 0;
}
static unsigned int ctrl_regs[SKIP_CTRE_NUM];
-#if 1 /*ary move to di_hw_v2.c */
+/*ary move to di_hw_v2.c */
static void set_di_inp_fmt_more(unsigned int repeat_l0_en,
int hz_yc_ratio, /* 2bit */
int hz_ini_phase, /* 4bit */
static void set_di_if0_mif_g12(struct DI_MIF_S *mif, int urgent,
int hold_line, int vskip_cnt, int wr_en);
-#endif
static void ma_di_init(void)
{
DIM_DI_WR(MCDI_CHK_EDGE_GAIN_OFFST, 0x4f6124);
DIM_DI_WR(MCDI_LMV_RT, 0x7455);
/*fix jira SWPL-32194,modify bit[31:24] to 0x20*/
- if (DIM_IS_IC_BF(SC2))
+ if (!DIM_IS_IC(SC2))
DIM_DI_WR(MCDI_LMV_GAINTHD, 0x2014d409);
DIM_DI_WR(MCDI_REL_DET_LPF_MSK_22_30, 0x0a010001);
DIM_DI_WR(MCDI_REL_DET_LPF_MSK_31_34, 0x01010101);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) && (DIM_IS_IC_BF(SC2)))
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) && (!DIM_IS_IC(SC2)))
DIM_DI_WR_REG_BITS(MCDI_REF_MV_NUM, 2, 0, 2);
}
DIM_DI_WR_REG_BITS(MCDI_REF_MV_NUM, 2, 0, 2);
}
+static void crc_init(void)//debug crc init
+{
+ if (DIM_IS_IC_BF(T5))
+ return;
+ if (DIM_IS_IC_EF(SC2))
+ DIM_DI_WR_REG_BITS(DI_CRC_CHK0, 0x7, 0, 3);
+ else if ((DIM_IS_IC(T5)) || (DIM_IS_IC(T5D)))
+ DIM_DI_WR_REG_BITS(DI_T5_CRC_CHK0, 0x7, 0, 3);
+}
+
void dimh_init_field_mode(unsigned short height)
{
DIM_DI_WR(DIPD_COMB_CTRL0, 0x02400210);
ctrl_regs[15] = MCDI_REF_MV_NUM;
}
-#if 1 /* move to di_hw_v2.c */
+/* move to di_hw_v2.c */
void dim_hw_init_reg(void)
{
unsigned short fifo_size_post = 0x120;/*feijun 08-02*/
PR_INF("%s, 0x%x\n", __func__, DIM_RDMA_RD(DI_IF0_LUMA_FIFO_SIZE));
}
-#endif
+
void dimh_hw_init(bool pd_enable, bool mc_enable)
{
-#if 1
unsigned short fifo_size_vpp = 0xc0;
unsigned short fifo_size_di = 0xc0;
-#endif
+
diext_clk_b_sw(true);
if (is_meson_txlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_tl1_cpu() ||
is_meson_sm1_cpu() ||
is_meson_tm2_cpu() ||
- DIM_IS_IC(T5)) {
+ DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D)) {
dim_top_gate_control(true, true);
} else if (DIM_IS_IC_EF(SC2)) {
dim_top_gate_control_sc2(true, true);
DIM_DI_WR(DI_CLKG_CTRL, 0x1); /* di no clock gate */
}
-#if 1
if (is_meson_txl_cpu() ||
is_meson_txlx_cpu() ||
is_meson_gxlx_cpu() ||
is_meson_sm1_cpu() ||
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
- DIM_IS_IC(T5)) {
+ DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D)) {
/* vpp fifo max size on txl :128*3=384[0x180] */
/* di fifo max size on txl :96*3=288[0x120] */
fifo_size_vpp = 0x180;
fifo_size_di = 0x120;
}
-#endif
+
/*enable lock win, suggestion from vlsi zheng.bao*/
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
dimp_set(edi_mp_lmv_lock_win_en, 0);/*lmv_lock_win_en = 0;*/
is_meson_sm1_cpu() ||
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
- DIM_IS_IC(T5)) {
+ DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D)) {
dim_pre_gate_control(true, true);
dim_post_gate_control(true);
} else if (DIM_IS_IC_EF(SC2)) {
set_skip_ctrl_size_regs();
ma_di_init();
ei_hw_init();
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC(SC2))
mc_blend_sc2_init();
+ crc_init();
get_ops_nr()->nr_hw_init();
if (pd_enable)
dimh_init_field_mode(288);
is_meson_g12b_cpu() ||
is_meson_tl1_cpu() ||
is_meson_tm2_cpu() ||
- DIM_IS_IC(T5)) {
+ DIM_IS_IC(T5) ||
+ DIM_IS_IC(T5D)) {
dim_pre_gate_control(false, true);
dim_post_gate_control(false);
dim_top_gate_control(false, false);
struct DI_SIM_MIF_s *di_contwr_mif,
unsigned char madi_en,
unsigned char pre_field_num,
- unsigned char pre_vdin_link)
+ unsigned char pre_vdin_link,
+ void *pre)
{
bool mem_bypass = false, chan2_disable = false;
unsigned short nrwr_hsize = 0, nrwr_vsize = 0;
unsigned short chan2_hsize = 0, chan2_vsize = 0;
unsigned short mem_hsize = 0, mem_vsize = 0;
unsigned int sc2_tfbf = 0; /* DI_PRE_CTRL bit [12:11] */
+ struct di_pre_stru_s *ppre = (struct di_pre_stru_s *)pre;
if (DIM_IS_IC(T5))
mem_bypass = (pre_vdin_link & DI_BIT4) ? true : false;
else
sc2_tfbf = 0;
+ /*
+ * the bit define is not same with before ,
+ * from sc2 DI_PRE_CTRL 0x1700,
+ * bit5/6/8/9/10/11/12
+ */
+
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
if (madi_en) {
- set_ma_pre_mif_g12(di_mtnwr_mif,
- di_contprd_mif,
- di_contp2rd_mif,
- di_contwr_mif,
- dimp_get(edi_mp_pre_urgent));
+ if (DIM_IS_IC_EF(T7) && opl1()->pre_ma_mif_set)
+ opl1()->pre_ma_mif_set(ppre,
+ dimp_get(edi_mp_pre_urgent));
+ else
+ set_ma_pre_mif_g12(di_mtnwr_mif,
+ di_contprd_mif,
+ di_contp2rd_mif,
+ di_contwr_mif,
+ dimp_get(edi_mp_pre_urgent));
} else {
chan2_disable = true;
}
else
DIM_RDMA_WR_BITS(DI_PRE_GL_THD,
dimp_get(edi_mp_pre_hold_line), 16, 6);
- if (dimp_get(edi_mp_pre_ctrl))
+ if (dimp_get(edi_mp_pre_ctrl)) {
DIM_RDMA_WR_BITS(DI_PRE_CTRL,
dimp_get(edi_mp_pre_ctrl), 0, 29);
- else
- DIM_RDMA_WR(DI_PRE_CTRL,
- 1 | /* nr wr en */
- (madi_en << 1) | /* mtn en */
- (madi_en << 2) | /* check3:2pulldown*/
- (madi_en << 3) | /* check2:2pulldown*/
- (1 << 4) |
- (madi_en << 5) | /*hist check enable*/
- /* hist check use chan2. */
- (madi_en << 6) |
- /*hist check use data before noise reduction.*/
- ((chan2_disable ? 0 : 1) << 8) |
- /* chan 2 enable for 2:2 pull down check.*/
- /* line buffer 2 enable */
- ((chan2_disable ? 0 : 1) << 9) |
- (0 << 10) | /* pre drop first. */
- //(1 << 11) | /* nrds mif enable */
- (sc2_tfbf << 11) | /* nrds mif enable */
- (0 << 12) | /* pre viu link */
- (pre_vdin_link << 13) |
- /* pre go line link */
- (pre_vdin_link << 14) |
- (1 << 21) | /*invertNRfield num*/
- (1 << 22) | /* MTN after NR. */
- (0 << 25) | /* contrd en */
- ((mem_bypass ? 1 : 0) << 28) |
- pre_field_num << 29);
+ } else {
+ if (DIM_IS_IC_EF(SC2))
+ DIM_RDMA_WR(DI_PRE_CTRL,
+ 1 | /* nr wr en */
+ (madi_en << 1) | /* mtn en */
+ (madi_en << 2) |
+ /*check3:2pulldown*/
+ (madi_en << 3) |
+ /*check2:2pulldown*/
+ (1 << 4) |
+ (madi_en << 5) |
+ /*hist check enable*/
+ (1 << 6) | /* MTN after NR. */
+ (1 << 8) | /* mem en. */
+ /* chan 2 enable */
+ ((chan2_disable ? 0 : 1) << 9) |
+ (sc2_tfbf << 11) |
+ /* nrds mif enable */
+ (pre_vdin_link << 13) |
+ /* pre go line link */
+ (pre_vdin_link << 14) |
+ (0 << 25) |
+ /* contrd en */
+ ((mem_bypass ? 1 : 0) << 28) |
+ pre_field_num << 29);
+ else
+ DIM_RDMA_WR(DI_PRE_CTRL,
+ 1 |
+ /* nr wr en */
+ (madi_en << 1) |
+ /* mtn en */
+ (madi_en << 2) |
+ /* check3:2pulldown*/
+ (madi_en << 3) |
+ /* check2:2pulldown*/
+ (1 << 4) |
+ (madi_en << 5) |
+ /*hist check enable*/
+ /* hist check use chan2. */
+ (madi_en << 6) |
+ //hist check use data
+ //before noise reduction
+ ((chan2_disable ? 0 : 1) << 8) |
+ /* chan 2 enable 2:2 pulldown check*/
+ /* line buffer 2 enable */
+ ((chan2_disable ? 0 : 1) << 9) |
+ (0 << 10) | /* pre drop first. */
+ //(1 << 11) | /* nrds mif enable */
+ (sc2_tfbf << 11) |
+ /* nrds mif enable */
+ (0 << 12) | /* pre viu link */
+ (pre_vdin_link << 13) |
+ /* pre go line link */
+ (pre_vdin_link << 14) |
+ (1 << 21) | /*invertNRfield num*/
+ (1 << 22) | /* MTN after NR. */
+ (0 << 25) | /* contrd en */
+ ((mem_bypass ? 1 : 0) << 28) |
+ pre_field_num << 29);
+ }
} else {
if (madi_en) {
set_ma_pre_mif(di_mtnwr_mif,
} else {
DIM_RDMA_WR(MCDI_CTRL_MODE, 0);
}
- } else
+ } else {
DIM_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfff7ff : 0));
+ }
DIM_RDMA_WR_BITS(DI_PRE_CTRL, (mcdi_en ? 3 : 0), 16, 2);
{
unsigned int end_x;
- DIM_VSYNC_WR_MPEG_REG(MCVECRD_CTRL1,
- mcvecrd_mif->canvas_num << 16 |
- 2 << 8 |
- (reverse ? 3 : 0) << 4 |
- 2);
+ if (mcvecrd_mif->linear) {
+ DIM_VSYNC_WR_MPEG_REG(MCVECRD_CTRL1,
+ 2 << 8 | //burst len = 2
+ 0 << 6 |
+ //little endian //ary ??bit and revers?
+ 2 << 0);//pack mode
+ di_mcmif_linear_rd_cfg(mcvecrd_mif,
+ MCVECRD_CTRL1,
+ MCVECRD_CTRL2,
+ MCVECRD_BADDR);
+ } else {
+ DIM_VSYNC_WR_MPEG_REG(MCVECRD_CTRL1,
+ mcvecrd_mif->canvas_num << 16 |
+ 2 << 8 |
+ (reverse ? 3 : 0) << 4 |
+ 2);
+ }
end_x = mcvecrd_mif->size_x + mcvecrd_mif->start_x;
DIM_VSYNC_WR_MPEG_REG(MCVECRD_SCOPE_X,
mcvecrd_mif->start_x |
DIM_VSC_WR_MPG_BT(MCDI_MC_CRTL, dimp_get(edi_mp_mcdebug_mode), 2, 3);
}
-#if 1 /* ary move to di_hw_v2.c */
+/* ary move to di_hw_v2.c */
static void set_di_inp_fmt_more(unsigned int repeat_l0_en,
int hz_yc_ratio, /* 2bit */
int hz_ini_phase, /* 4bit */
(1 << 12) | /*burst_size_cr*/
(1 << 10) | /*burst_size_cb*/
(3 << 8) | /*burst_size_y*/
+ (mif->l_endian << 4) |
(chro_rpt_lastl_ctrl << 6) |
((mif->set_separate_en != 0) << 1) |
(0 << 0)/* cntl_enable */
);
if (mif->set_separate_en == 2) {
/* Enable NV12 Display */
- DIM_RDMA_WR_BITS(DI_INP_GEN_REG2, 1, 0, 1);
+ if (mif->cbcr_swap)
+ DIM_RDMA_WR_BITS(DI_INP_GEN_REG2, 2, 0, 2);
+ else
+ DIM_RDMA_WR_BITS(DI_INP_GEN_REG2, 1, 0, 2);
} else {
- DIM_RDMA_WR_BITS(DI_INP_GEN_REG2, 0, 0, 1);
+ DIM_RDMA_WR_BITS(DI_INP_GEN_REG2, 0, 0, 2);
}
+ if (mif->reg_swap == 1)
+ DIM_RDMA_WR_BITS(DI_INP_GEN_REG3, 1, 0, 1);
+ else
+ DIM_RDMA_WR_BITS(DI_INP_GEN_REG3, 0, 0, 1);
if (mif->canvas_w % 32)
burst_len = 0;
(1 << 12) | /*burst_size_cr*/
(1 << 10) | /*burst_size_cb*/
(3 << 8) | /*burst_size_y*/
+ (mif->l_endian << 4) |
(chro_rpt_lastl_ctrl << 6) |
((mif->set_separate_en != 0) << 1) |
(0 << 0) /* cntl_enable */
);
if (mif->set_separate_en == 2) {
/* Enable NV12 Display */
- DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 1, 0, 1);
+ //DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 1, 0, 2);
+ if (mif->cbcr_swap)
+ DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 2, 0, 2);
+ else
+ DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 1, 0, 2);
} else {
- DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 0, 0, 1);
+ DIM_RDMA_WR_BITS(DI_MEM_GEN_REG2, 0, 0, 2);
}
DIM_RDMA_WR_BITS(DI_MEM_GEN_REG3, mif->bit_mode & 0x3, 8, 2);
+ if (mif->reg_swap == 1)
+ DIM_RDMA_WR_BITS(DI_MEM_GEN_REG3, 1, 0, 1);
+ else
+ DIM_RDMA_WR_BITS(DI_MEM_GEN_REG3, 0, 0, 1);
/* ---------------------- */
/* Canvas */
/* ---------------------- */
(1 << 12) | /*burst_size_cr*/
(1 << 10) | /*burst_size_cb*/
(3 << 8) | /*burst_size_y*/
+ (mif->l_endian << 4) |
(chro_rpt_lastl_ctrl << 6) |
((mif->set_separate_en != 0) << 1) |
(0 << 0) /* cntl_enable */
/* ---------------------- */
if (mif->set_separate_en == 2) {
/* Enable NV12 Display */
- DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 1, 0, 1);
+ //DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 1, 0, 2);
+ if (mif->cbcr_swap)
+ DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 2, 0, 2);
+ else
+ DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 1, 0, 2);
} else {
- DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 0, 0, 1);
+ DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 0, 0, 2);
}
DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG3, mif->bit_mode & 0x3, 8, 2);
+ if (mif->reg_swap == 1)
+ DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG3, 1, 0, 1);
+ else
+ DIM_RDMA_WR_BITS(DI_CHAN2_GEN_REG3, 0, 0, 1);
+
DIM_RDMA_WR(DI_CHAN2_CANVAS0, (mif->canvas0_addr2 << 16) |
(mif->canvas0_addr1 << 8) |
(mif->canvas0_addr0 << 0));
(mif->canvas0_addr0 << 0));
if (mif->set_separate_en == 2) {
/* Enable NV12 Display */
- DIM_RDMA_WR_BITS(DI_IF0_GEN_REG2, 1, 0, 1);
+ DIM_RDMA_WR_BITS(DI_IF0_GEN_REG2, 1, 0, 2);
} else {
- DIM_RDMA_WR_BITS(DI_IF0_GEN_REG2, 0, 0, 1);
+ DIM_RDMA_WR_BITS(DI_IF0_GEN_REG2, 0, 0, 2);
}
/* ---------------------- */
0); /* hz repeat */
}
}
-#endif /*ary move to di_hw_v2.c */
+
+/*ary move to di_hw_v2.c */
+
static unsigned int di_mc_update;
void dimh_patch_post_update_mc(void)
{
DIM_VSC_WR_MPG_BT(DI_EI_CTRL3, 1, 31, 1);
/* DI_VSYNC_WR_MPEG_REG(DI_BLEND_REG0_Y, (vsize_post >> 2) - 1); */
- if (DIM_IS_IC_EF(SC2)) {
+ if (DIM_IS_IC(SC2)) {
DIM_VSC_WR_MPG_BT(MCDI_REF_MV_NUM,
0, 16, 13);
DIM_VSC_WR_MPG_BT(MCDI_REF_MV_NUM,
}
}
-#if 1 /* move to di_hw_v2.c */
+/* move to di_hw_v2.c */
static void post_bit_mode_config(unsigned char if0,
unsigned char if1,
unsigned char if2,
DIM_DI_WR_REG_BITS(DI_DIWR_CTRL, 0x3, 22, 2);
#endif
}
-#endif
+
void dimh_post_switch_buffer(struct DI_MIF_S *di_buf0_mif,
struct DI_MIF_S *di_buf1_mif,
struct DI_MIF_S *di_buf2_mif,
buf1_en = (!ei_only && (di_ddr_en || di_vpp_en));
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC_EF(SC2)) {
opl1()->pst_mif_update_csv(di_buf0_mif,
DI_MIF0_ID_IF0, NULL);
+ if (di_ddr_en)
+ opl1()->wrmif_set(di_diwr_mif, NULL,
+ EDI_MIFSM_WR);
+ }
else
DIM_VSYNC_WR_MPEG_REG
(DI_IF0_CANVAS0,
if (!di_ddr_en)
DIM_VSC_WR_MPG_BT(VD1_IF0_GEN_REG, 0, 0, 1);
if (mc_enable) {
- DIM_VSC_WR_MPG_BT(MCVECRD_CTRL1,
- di_mcvecrd_mif->canvas_num, 16, 8);
+ if (di_mcvecrd_mif->linear)
+ di_mcmif_linear_rd_cfg(di_mcvecrd_mif,
+ MCVECRD_CTRL1,
+ MCVECRD_CTRL2,
+ MCVECRD_BADDR);
+ else
+ DIM_VSC_WR_MPG_BT(MCVECRD_CTRL1,
+ di_mcvecrd_mif->canvas_num,
+ 16, 8);
}
/*motion for current display field.*/
if (blend_mtn_en) {
- DIM_VSC_WR_MPG_BT(MTNRD_CTRL1,
- di_mtnprd_mif->canvas_num, 16, 8);
+ if (di_mtnprd_mif->linear)
+ di_mif1_linear_rd_cfg(di_mtnprd_mif,
+ MTNRD_CTRL1,
+ MTNRD_CTRL2,
+ MTNRD_BADDR);
+ else
+ DIM_VSC_WR_MPG_BT(MTNRD_CTRL1,
+ di_mtnprd_mif->canvas_num,
+ 16, 8);
/* current field mtn canvas index.*/
}
} else {
if (di_ddr_en) {
}
- if (DIM_IS_IC_EF(SC2)) {
+
+ if (DIM_IS_IC_EF(SC2))
DIM_VSC_WR_MPG_BT(DI_POST_CTRL, blend_en, 1, 1);
- DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD, blend_mode, 20, 2);
- } else {
+ else
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, blend_en, 31, 1);
+
+ if (DIM_IS_IC(SC2))
+ DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD, blend_mode, 20, 2);
+ else
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, blend_mode, 20, 2);
- }
+
if ((dimp_get(edi_mp_pldn_ctrl_rflsh) == 1) && pd_enable)
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, 7, 22, 3);
di_vpp_en, hold_line, vskip_cnt);
}
/* motion for current display field. */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+ if (di_mtnprd_mif->linear && opl1()->post_mtnrd_mif_set)
+ opl1()->post_mtnrd_mif_set(di_mtnprd_mif);
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
set_post_mtnrd_mif_g12(di_mtnprd_mif);
else
set_post_mtnrd_mif(di_mtnprd_mif, urgent);
#endif
}
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, 7, 22, 3);
- if (DIM_IS_IC_EF(SC2)) {
+
+ if (DIM_IS_IC_EF(SC2))
DIM_VSC_WR_MPG_BT(DI_POST_CTRL, blend_en & 0x1, 1, 1);
- DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD, blend_mode & 0x3, 20, 2);
- } else {
+ else
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, blend_en & 0x1, 31, 1);
+
+ if (DIM_IS_IC(SC2))
+ DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD, blend_mode & 0x3, 20, 2);
+ else
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, blend_mode & 0x3, 20, 2);
- }
+
if (!is_meson_txlx_cpu())
invert_mv = 0;
cfg->buf_o->vframe);
/* motion for current display field. */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+ if (cfg->di_mtnprd_mif->linear && opl1()->post_mtnrd_mif_set)
+ opl1()->post_mtnrd_mif_set(cfg->di_mtnprd_mif);
+ else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
set_post_mtnrd_mif_g12(cfg->di_mtnprd_mif);
else
set_post_mtnrd_mif(cfg->di_mtnprd_mif, cfg->urgent);
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, 7, 22, 3);
- #if 1
+ if (DIM_IS_IC_EF(SC2))
DIM_VSC_WR_MPG_BT(DI_POST_CTRL, cfg->blend_en & 0x1, 1, 1);
+ else
+ DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, cfg->blend_en & 0x1, 31, 1);
+ if (DIM_IS_IC(SC2))
DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD,
cfg->blend_mode & 0x3, 20, 2);
- #else
- DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, cfg->blend_en & 0x1, 31, 1);
+ else
DIM_VSC_WR_MPG_BT(DI_BLEND_CTRL, cfg->blend_mode & 0x3, 20, 2);
- #endif
- if (!is_meson_txlx_cpu())
+
+ //if (!is_meson_txlx_cpu())
//invert_mv = 0; /* ary ?? */
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
dimh_enable_di_pre_mif(false, mc_enable);
DIM_DI_WR(DI_POST_SIZE, (32 - 1) | ((128 - 1) << 16));
-#if 1 /* ary: have set in pst_mif_sw*/
+/* ary: have set in pst_mif_sw*/
if (DIM_IS_IC_BF(SC2)) {
DIM_DI_WR_REG_BITS(DI_IF1_GEN_REG, 0, 0, 1);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
DIM_DI_WR_REG_BITS(DI_IF2_GEN_REG, 0, 0, 1);
}
-#endif
+
/* disable ma,enable if0 to vpp,enable afbc to vpp */
if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
if (rd_reg_bits(VIU_MISC_CTRL0, 16, 4) != 0)
{
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
DIM_RDMA_WR_BITS(DI_PRE_CTRL, 1, 30, 1);
+ dbg_ic("%s:\n", __func__);
+}
+
+void dbg_reg_mem(unsigned int dbgid)
+{
+ const struct reg_acc *op = &di_pre_regset;
+ unsigned int val;
+
+ val = op->rd(0x551e);
+ dbg_ic("%s:[%d], 0x%x\n", __func__, dbgid, val);
+ val = op->rd(0x5538);
+ dbg_ic("%s:[%d], reg:[0x5538]0x%x\n", __func__, dbgid, val);
}
/*
}
}
-#if 1 /* move to di_hw_v2.c */
+/* move to di_hw_v2.c */
/*2019-12-25 by feijun*/
void hpre_gl_sw(bool on)
{
else
DIM_RDMA_WR(DI_PRE_GL_CTRL, 0xc0000000);
}
-#endif
+
/*
* frame + soft reset for the pre modules
*/
/* enable mtn wr mif external gate */
//DIM_DI_WR_REG_BITS(VIUB_GCLK_CTRL1, 2, 24, 2);
if (mc_enable) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD)) {
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
DIM_DI_WR_REG_BITS(VIUB_GCLK_CTRL2, 0, 12, 2);
- }
- else{
+ else
/* enable me clk always run vlsi issue */
DIM_DI_WR_REG_BITS(VIUB_GCLK_CTRL2, 3, 12, 2);
- }
+
/*
* enable mc pre mv(wr) mcinfo w/r
* mif external gate
static void di_async_reset(void)/*2019-01-17 add for debug*/
{
+ if (DIM_IS_IC_EF(T7)) {
+ DIM_RDMA_WR_BITS(VIUB_SW_RESET, 1, 4, 1);
+ DIM_RDMA_WR_BITS(VIUB_SW_RESET, 0, 4, 1);
+ } else {
/*wrmif async reset*/
- DIM_RDMA_WR_BITS(VIUB_SW_RESET, 1, 14, 1);
- DIM_RDMA_WR_BITS(VIUB_SW_RESET, 0, 14, 1);
+ DIM_RDMA_WR_BITS(VIUB_SW_RESET, 1, 14, 1);
+ DIM_RDMA_WR_BITS(VIUB_SW_RESET, 0, 14, 1);
+ }
}
static void di_pre_rst_frame(void)
DIM_RDMA_WR_BITS(DI_CANVAS_URGENT0, 0, 0, 1);
}
-#if 1 /*move to di_hw_v2.c */
+/*move to di_hw_v2.c */
void dim_rst_protect(bool on)/*2019-01-22 by VLSI feng.wang*/
{
if (on)
else
DIM_RDMA_WR_BITS(DI_NRWR_Y, 0, 15, 1);
}
-#endif
+
/*bit 10,12,16,18 [3:1]*/
/*#define PRE_ID_MASK (0x5140e) */
#define PRE_ID_MASK (0x51400)
/*bit 8,10,14,16*/
#define PRE_ID_MASK_TL1 (0x14500)
+#define PRE_ID_MASK_T5 (0x28a00) //add decontour and shift 1bit
+
static bool di_pre_idle(void)
{
bool ret = false;
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
+ if (DIM_IS_IC(T5)) {
+ if ((DIM_RDMA_RD(DI_ARB_DBG_STAT_L1C1) &
+ PRE_ID_MASK_T5) == PRE_ID_MASK_T5)
+ ret = true;
+ } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
if ((DIM_RDMA_RD(DI_ARB_DBG_STAT_L1C1) &
PRE_ID_MASK_TL1) == PRE_ID_MASK_TL1)
ret = true;
DIM_DI_WR(DI_NOP_REG2, valb);
}
-#if 1 /*ary move to di_hw_v2.c*/
+/*ary move to di_hw_v2.c*/
/*below for post */
void post_mif_sw(bool on)
{
}
dim_print("%s:%d\n", __func__, on);
}
-#endif
+
void post_close_new(void)
{
unsigned int data32;
pr_info("%s\n", __func__);
}
-#if 1 /* move to di_hw_v2.c */
+/* move to di_hw_v2.c */
void post_dbg_contr(void)
{
/* bit [11:10]:cntl_dbg_mode*/
break;
}
}
-#endif
/*add 2019-04-25 for post crash debug*/
void hpst_power_ctr(bool on)
}
/* ary move to di_hw_v2.c*/
-#if 1
/*
* enable/disable inp&chan2&mem&nrwr mif
*/
}
}
-#endif
+
static atomic_t mif_flag;
void dimh_enable_di_pre_mif(bool en, bool mc_enable)
{
void dimh_pulldown_vof_win_config(struct pulldown_detected_s *wins)
{
- if (DIM_IS_IC_EF(SC2)) {
+ if (DIM_IS_IC(SC2)) {
DIM_VSC_WR_MPG_BT(MCDI_REF_MV_NUM,
wins->regs[0].win_vs, 17, 12);
DIM_VSC_WR_MPG_BT(MCDI_REF_MV_NUM,
DIM_VSC_WR_MPG_BT(DI_BLEND_REG3_Y, wins->regs[3].win_vs, 17, 12);
DIM_VSC_WR_MPG_BT(DI_BLEND_REG3_Y, wins->regs[3].win_ve, 1, 12);
- if (DIM_IS_IC_EF(SC2)) {
+ if (DIM_IS_IC(SC2)) {
DIM_VSC_WR_MPG_BT(MCDI_LMV_GAINTHD,
(wins->regs[0].win_ve > wins->regs[0].win_vs)
? 1 : 0, 19, 1);
wins->regs[3].blend_mode, 14, 2);
}
+static bool pq_save_db(unsigned int addr, unsigned int val, unsigned int mask)
+{
+ bool ret = false;
+ int i;
+ struct db_save_s *p;
+
+ for (i = 0; i < DIM_DB_SAVE_NUB; i++) {
+ p = &get_datal()->db_save[i];
+
+ if (!p->support)
+ continue;
+
+ if (addr == p->addr) {
+ p->val_db = val;
+ p->mask = mask;
+ p->en_db = true;
+ ret = true;
+ dbg_pq("%s:reg:0x%x,val:0x%x,mask:0x%x\n",
+ __func__, p->addr, p->val_db, p->mask);
+ break;
+ }
+ }
+ return ret;
+}
+
void dimh_load_regs(struct di_pq_parm_s *di_pq_ptr)
{
unsigned int i = 0, j = 0, addr = 0, value = 0, mask = 0, len;
unsigned int table_name = 0, nr_table = 0;
bool ctrl_reg_flag = false;
+ bool save_db = false;
struct am_reg_s *regs_p = NULL;
if (dimp_get(edi_mp_pq_load_dbg) == 1)
if (table_name & nr_table)
ctrl_reg_flag =
get_ops_nr()->set_nr_ctrl_reg_table(addr, value);
+ if (table_name & (TABLE_NAME_NR))//mark for undefine
+ //if (table_name & (TABLE_NAME_NR | TABLE_NAME_SMOOTHPLUS))
+ save_db = pq_save_db(addr, value, mask);
- if (!ctrl_reg_flag)
+ if ((!ctrl_reg_flag) && (!save_db))
DIM_DI_WR(addr, value);
if (dimp_get(edi_mp_pq_load_dbg) == 2)
pr_info("[%u][0x%x] = [0x%x] %s\n", i, addr,
/*rgb mode =0, 422 YCBCR to one canvas.*/
(0 << 22) |
(0 << 24) |
- (cfg_mif->ddr_en << 30));
+ (cfg_mif->reg_swap << 30));
if (cfg_mif->set_separate_en == 0) {
ctr |= (cfg_mif->canvas_num & 0xff); /* canvas index.*/
/*rgb mode =0, 422 YCBCR to one canvas.*/
(0 << 22) |
(0 << 24) |
- (cfg_mif->ddr_en << 30);
+ (cfg_mif->reg_swap << 30);
if (cfg_mif->set_separate_en == 0) {
ctr |= (cfg_mif->canvas_num & 0xff); /* canvas index.*/
} else if (cfg_mif->set_separate_en == 2) {
//cfg_mif->ddr_en = ddr_en;
cfg_mif->urgent = urgent;
- cfg_mif->cbcr_swap = 0;
- cfg_mif->l_endian = 0;
+ //cfg_mif->cbcr_swap = 0;
+ //cfg_mif->l_endian = 0;
dimh_wrmif_set(cfg_mif, &di_pst_regset, NULL, EDI_MIFSM_WR);
}
cfg_mif->ddr_en = ddr_en;
cfg_mif->urgent = urgent;
- cfg_mif->cbcr_swap = 0;
- cfg_mif->l_endian = 0;
+ //cfg_mif->cbcr_swap = 0;
+ //cfg_mif->l_endian = 0;
dimh_wrmif_set(cfg_mif, &di_pst_regset, NULL, EDI_MIFSM_NR);
}
{
struct cfg_mifset_s mifset;
- mifset.ddr_en = ddr_en;
- mifset.urgent = urgent;
- mifset.cbcr_swap = 0;
- mifset.l_endian = 0;
+ //mifset.ddr_en = ddr_en;
+ //mifset.urgent = urgent;
+ //mifset.cbcr_swap = 0;
+ //mifset.l_endian = 0;
dimh_wrmif_switch_buf(cfg_mif, &di_pst_regset, &mifset, EDI_MIFSM_WR);
}
"IF2",
};
-const char *dim_get_mif_id_name(enum EDI_MIF_REG_INDEX idx)
+const char *dim_get_mif_id_name(enum DI_MIF0_ID idx)
{
if (idx < ARRAY_SIZE(mif_id_name))
return mif_id_name[idx];
seq_printf(seq, "%-15s:%d\n", "pd22_flg_calc_en", pd22_flg_calc_en);
/***********************/
- seq_printf(seq, "%-15s:%d\n", "mcen_mode", mcen_mode);
+ seq_printf(seq, "%-15s:%d\n", "dimmcen_mode", dimmcen_mode);
seq_printf(seq, "%-15s:%d\n", "mcuv_en", mcuv_en);
seq_printf(seq, "%-15s:%d\n", "mcdebug_mode", mcdebug_mode);
seq_printf(seq, "%-15s:%d\n", "pldn_ctrl_rflsh", pldn_ctrl_rflsh);
EDPST_MODE_422_10BIT_PACK,
EDPST_MODE_422_10BIT,
EDPST_MODE_422_8BIT,
+ EDPST_MODE_420_10BIT /* add 2020-11-26 */
};
struct AFBCD_S {
u32 mmu_info_baddr ;//mmu_linear_addr
u32 reg_init_ctrl ;//pip init frame flag
u32 reg_pip_mode ;//pip open bit
- u32 reg_ram_comb ;//ram split bit open in di mult write case case
+ u32 reg_ram_comb ;//ram split bit open in di mult write case
u32 reg_format_mode;//0:444 1:422 2:420
u32 reg_compbits_y ;//bits num after compression
u32 reg_compbits_c ;//bits num after compression
unsigned int canvas0_addr0:8;
unsigned int canvas0_addr1:8;
unsigned int canvas0_addr2:8;
+ ulong addr0; //for t7
+ ulong addr1; //for t7
+ ulong addr2; //for t7
+
/* canvas_w: for input not 64 align*/
unsigned int canvas_w;
/* ary move from parameter to here from sc2 */
/* ary no use*/
unsigned int nocompress :1;
unsigned int output_field_num:1;
- unsigned int reseved :8;
+ unsigned int l_endian : 1; //2020-12-21
+ unsigned int reg_swap : 1;
+ unsigned int cbcr_swap: 1;
+ unsigned int linear : 1;
+ unsigned int buf_crop_en : 1;
+ unsigned int block_mode : 1;
+ unsigned int dbg_from_dec: 1; //
+ unsigned int reserved :1;
+ unsigned int buf_hsize;
+ unsigned int cvs0_w;
+ unsigned int cvs1_w;
+ unsigned int cvs2_w;
/**/
enum DI_MIF0_ID mif_index; /* */
unsigned int en :1; /* add for sc2*/
unsigned int src_i :1; /* ary add for sc2 */
- unsigned int reserved : 15;
-
+ unsigned int reg_swap :1;
+ unsigned int linear : 1;
+ unsigned int buf_crop_en : 1;
+ unsigned int reserved : 3;
+ unsigned int per_bits : 8; /* for t7 */
+
+ unsigned int buf_hsize;
+ ulong addr; //for t7
+ ulong addr1;
+ ulong addr2;
enum DI_MIFS_ID mif_index; /* */
};
unsigned short canvas_num;
unsigned short blend_en;
unsigned short vecrd_offset;
+ unsigned int per_bits; /* for t7 */
+ ulong addr; //for t7
+ bool linear;
};
enum gate_mode_e {
struct DI_SIM_MIF_s *di_contwr_mif,
unsigned char madi_en,
unsigned char pre_field_num,
- unsigned char pre_vdin_link);
+ unsigned char pre_vdin_link,
+ void *ppre);
//void dimh_enable_afbc_input(struct vframe_s *vf);
void dimh_mc_pre_mv_irq(void);
void (*wrmif_sw_buf)(struct DI_SIM_MIF_s *cfg_mif,
const struct reg_acc *ops,
enum EDI_MIFSM mifsel);
+ /* for t7 */
+ void (*pre_ma_mif_set)(void *ppre,
+ unsigned short urgent);
+ void (*post_mtnrd_mif_set)(struct DI_SIM_MIF_s *mtnprd_mif);
+ void (*pre_enable_mc)(struct DI_MC_MIF_s *mcinford_mif,
+ struct DI_MC_MIF_s *mcinfowr_mif,
+ struct DI_MC_MIF_s *mcvecwr_mif,
+ unsigned char mcdi_en);
+
void (*wrmif_trig)(enum EDI_MIFSM mifsel);
void (*wr_rst_protect)(bool on);
void (*hw_init)(void);
void (*pre_gl_thd)(void);
void (*pst_gl_thd)(unsigned int hold_line);
const unsigned int *reg_mif_tab[MIF_NUB];
+ /*debug*/
+ const unsigned int *reg_mif_wr_tab[EDI_MIFS_NUB];
+ const struct regs_t *reg_mif_wr_bits_tab;
const struct reg_t *rtab_contr_bits_tab;
};
enum DI_MIF0_ID mif_index,
const struct reg_acc *op);//debug only
-const char *dim_get_mif_id_name(enum EDI_MIF_REG_INDEX idx);
+const char *dim_get_mif_id_name(enum DI_MIF0_ID idx);
/*********************************************************/
struct SHRK_S {
unsigned int hsize_in;
struct di_buf_s *di_buf);
unsigned int dw_get_h(void);
+void di_mif1_linear_rd_cfg(struct DI_SIM_MIF_s *mif,
+ unsigned int CTRL1,
+ unsigned int CTRL2,
+ unsigned int BADDR);
+void di_mcmif_linear_rd_cfg(struct DI_MC_MIF_s *mif,
+ unsigned int CTRL1,
+ unsigned int CTRL2,
+ unsigned int BADDR);
+bool dip_is_linear(void);
+bool dim_dbg_cfg_post_byapss(void);
+void dbg_reg_mem(unsigned int dbgid);
+
#endif
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/vfm/vframe_provider.h>
#include <linux/amlogic/media/vfm/vframe_receiver.h>
+#include <linux/amlogic/media/di/di_interface.h>
#include <linux/kfifo.h> /*ary add*/
#include "../deinterlace/di_pqa.h"
//#include "di_pqa.h"
-#define DI_CHANNEL_NUB (2)
+#define DI_CHANNEL_NUB (4)
#define DI_CHANNEL_MAX (4)
/* for vfm mode limit input vf */
#define DIM_K_VFM_IN_LIMIT (2)
#define TABLE_FLG_END (0xfffffffe)
-#define TABLE_LEN_MAX (1000)
+#define DIMTABLE_LEN_MAX (1000)
#define F_IN(x, a, b) (((x) > (a)) && ((x) < (b)))
#define COM_M(m, a, b) (((a) & (m)) == ((b) & (m)))
#define COM_MV(a, m, v) (((a) & (m)) == (v))
EDI_CFG_4K,
EDI_CFG_POUT_FMT,
EDI_CFG_DAT,
- EDI_CFG_ALLOC_WAIT, /* alloc wait */
+ EDI_CFG_ALLOC_SCT, /* alloc sct */
EDI_CFG_KEEP_DEC_VF,
EDI_CFG_POST_NUB,
EDI_CFG_BYPASS_MEM,
+ EDI_CFG_IOUT_FMT,
+ EDI_CFG_TMODE_1, /*EDIM_TMODE_1_PW_VFM*/
+ EDI_CFG_TMODE_2, /*EDIM_TMODE_2_PW_OUT*/
+ EDI_CFG_TMODE_3, /*EDIM_TMODE_3_PW_LOCAL*/
+ EDI_CFG_LINEAR,
+ EDI_CFG_PONLY_BP_THD,
EDI_CFG_END,
};
+struct di_ch_s;
+struct dim_wmode_s;
+
+enum EDIM_NIN_TYPE {
+ EDIM_NIN_TYPE_NONE,
+ EDIM_NIN_TYPE_VFM,
+ EDIM_NIN_TYPE_INS,
+};
+
#define cfgeq(a, b) ((di_cfg_top_get(EDI_CFG_##a) == (b)) ? true : false)
#define cfgnq(a, b) ((di_cfg_top_get(EDI_CFG_##a) != (b)) ? true : false)
#define cfgg(a) di_cfg_top_get(EDI_CFG_##a)
#define cfgs(a, b) di_cfg_top_set(EDI_CFG_##a, b)
+#define cfggch(pch, a) di_cfg_cp_get(pch, EDI_CFG_##a)
+#define cfgsch(pch, a, b) di_cfg_cp_set(pch, EDI_CFG_##a, b)
+
#define K_DI_CFG_NUB (EDI_CFG_END - EDI_CFG_BEGIN + 1)
#define K_DI_CFG_T_FLG_NOTHING (0x00)
#define K_DI_CFG_T_FLG_DTS (0x01)
EDI_DBG_F_06,
EDI_DBG_F_07,
EDI_DBG_F_08,
+ EDI_DBG_F_09,
};
struct di_dbg_func_s {
unsigned int v;
};
+struct dim_wmode_s {
+ //enum EDIM_TMODE tmode;
+ unsigned int buf_type; /*add this to split kinds */
+ unsigned int is_afbc :1,
+ is_vdin :1,
+ is_i :1,
+ need_bypass :1,
+ is_bypass :1,
+ pre_bypass :1,
+ post_bypass :1,
+ flg_keep :1, /*keep buf*/
+
+ trick_mode :1,
+ prog_proc_config :1, /*debug only: proc*/
+ /**************************************
+ *prog_proc_config: same as p_as_i?
+ *1: process p from decoder as field
+ *0: process p from decoder as frame
+ ***************************************/
+ is_invert_tp :1,
+ p_as_i :1,
+ p_as_p :1,
+ p_use_2i :1,
+ is_angle :1,
+ is_top :1, /*include */
+ is_eos :1,
+ is_eos_insert :1, /* this is internal eos */
+ bypass :1, /* is_bypass | need_bypass*/
+ reserved :13;
+ unsigned int vtype; /*vfm->type*/
+ //unsigned int h; /*taget h*/
+ //unsigned int w; /*taget w*/
+ unsigned int src_h;
+ unsigned int src_w;
+ unsigned int tgt_h;
+ unsigned int tgt_w;
+ unsigned int o_h;
+ unsigned int o_w;
+ unsigned int seq;
+ unsigned int seq_sgn;
+};
+
/**************************************/
/* PRE */
/**************************************/
unsigned int dbg_f_cnt;
union hw_sc2_ctr_pre_s pre_top_cfg;
+ unsigned int self_trig_mask;
};
/**************************************/
EDIM_BLK_TYP_BUFP,
EDIM_BLK_TYP_DATI,
EDIM_BLK_TYP_PAFBCT,
+ EDIM_BLK_TYP_PSCT,
+ EDIM_BLK_TYP_POUT = 0x08 /* not di buffer */
};
struct blk_flg_s {
QUE_POST_READY, /*8*/
QUE_POST_BACK, /*new*/
QUE_POST_DOING,
- QUE_POST_KEEP, /*below use pw_queue_in*/
- QUE_POST_KEEP_BACK,
+// QUE_POST_KEEP, /*below use pw_queue_in*/
+// QUE_POST_KEEP_BACK,
QUE_POST_KEEP_RE_ALLOC, /*need*/
QUE_PRE_NO_BUF_WAIT, //
QUE_PST_NO_BUF_WAIT, //
edi_mp_mcuv_en,
edi_mp_mcdebug_mode,
edi_mp_pldn_ctrl_rflsh,
+ edi_mp_pstcrc_ctrl,
EDI_MP_SUB_DI_E,
/**************************************/
EDI_MP_SUB_3D_E,
/**************************************/
+ edi_mp_clock_low_ratio,//set low ratio of vpu clkb
EDI_MP_UI_T_END,
};
struct di_dat_s {
// struct dim_mm_blk_s *blk_buf;
- void *virt;
+ void *virt; //for cma: (struct page *)
+ unsigned int cnt; //for cma
bool flg_alloc;
struct blk_flg_s flg;
unsigned long addr_end;
};
+/* new interface */
+/* @ary_note: for vfm option only */
+struct dev_vfm_s {
+ bool (*vf_m_fill_polling)(struct di_ch_s *pch);
+ void (*vf_m_fill_ready)(struct di_ch_s *pch);
+ bool (*vf_m_bypass_first_frame)(struct di_ch_s *pch);
+};
+
+struct dev_instance {
+ struct di_init_parm parm;
+//n struct di_buffer *in[DIM_K_BUF_IN_LIMIT];
+//n struct di_buffer *out[DIM_K_BUF_OUT_LIMIT];
+};
+
+struct dim_itf_ops_s {
+ void *(*peek)(struct di_ch_s *pch);
+ void *(*get)(struct di_ch_s *pch);
+ void (*put)(void *data, struct di_ch_s *pch);
+};
+
+//n struct dim_inter_s {
+struct dim_itf_s {
+ enum EDIM_NIN_TYPE etype;
+ unsigned int tmode;
+ const char *name;
+ unsigned int ch;
+ /*status:*/
+ bool bypass_complete;
+ bool reg;
+ struct mutex lock_reg; /* for reg */
+ struct dim_itf_ops_s opsi;
+ struct dim_itf_ops_s opso;
+ void (*op_post_done)(struct di_ch_s *pch);
+ struct dim_dvfm_s *(*op_dvfm_fill)(struct di_ch_s *pch);
+ void (*op_ins_2_doing)(struct di_ch_s *pch,
+ bool bypass,
+ struct di_buf_s *di_buf);
+ void (*opins_m_back_in)(struct di_ch_s *pch);
+ void (*op_m_unreg)(struct di_ch_s *pch);
+ bool (*op_fill_ready)(struct di_ch_s *pch, struct di_buf_s *di_buf);
+ void (*op_ready_out)(struct di_ch_s *pch);
+ /* @ary_note: vfm only */
+ struct dev_vfram_t dvfm; /* for vfm prob fix */
+
+ union {
+ struct dev_vfm_s dvfmc; /* for vfm option */
+ struct dev_instance dinst;
+ } u;
+};
+
struct di_ores_s {
/* same as ori */
struct di_pre_stru_s di_pre_stru;
unsigned int dis_afbce : 1;
unsigned int rev1 : 30;
unsigned int pre_inser_size;
+ unsigned int ibuf_hsize;
+ unsigned int pbuf_hsize;
};
struct dim_mm_t_s {
/* use for reserved and alloc all*/
int cnt_alloc; /* debug only */
};
-struct di_mm_s {
+struct div2_mm_s {
struct di_mm_cfg_s cfg; /* clear in dip_init_value */
struct di_mm_st_s sts;
};
unsigned int b_pre_ready;
unsigned int b_pst_free;
unsigned int b_display;
+ unsigned int b_nin;
};
struct dim_bypass_s {
#define CODE_MEMN (DIM_DATA_MASK | 0x06)
#define CODE_PAT (DIM_DATA_MASK | 0x07)
#define CODE_IAT (DIM_DATA_MASK | 0x08)
+#define CODE_SCT (DIM_DATA_MASK | 0x09)
+#define CODE_NIN (DIM_DATA_MASK | 0x0a)
+#define CODE_NDIS (DIM_DATA_MASK | 0x0b)
#define CODE_OUT (0xff123402)
+#define CODE_IN (0xff123406)
#define CODE_OUT_MODE2 (0xff123403)
#define CODE_BYPASS (0xff123405)
+#define CODE_INS_LBF (DIM_DATA_MASK | 0x0c)
#define NONE_QUE (0xff)
QS_FUNC_N_LIST,
QS_FUNC_N_PEEK,
QS_FUNC_N_SOME,
+ QS_FUNC_N_IS_IN,
QS_FUNC_F_IN,// = 0x100,
QS_FUNC_F_O,
union q_buf_u *pbuf);
bool (*out_some)(struct buf_que_s *pqb, struct qs_cls_s *q,
union q_buf_u pbuf);
+ bool (*is_in)(struct buf_que_s *pqb,
+ struct qs_cls_s *p, union q_buf_u ubuf);
+ bool (*n_get_marsk)(struct buf_que_s *pqb, struct qs_cls_s *q,
+ unsigned int *marsk);
};
struct qs_cls_s {
unsigned int reg_cnt;
//unsigned long jiff;
// bool tvp;
+ void *pat_buf;
+ void *sct;
+ unsigned int sct_keep; //keep number
+ void *buffer; //new_interface
};
/*que buf block end*/
enum QBF_PAT_Q_TYPE {
QBF_PAT_Q_IDLE,
QBF_PAT_Q_READY, /* multi wr, multi rd */
+ QBF_PAT_Q_READY_SCT, /* for sct ? */
QBF_PAT_Q_IN_USED,
QBF_PAT_Q_NUB,
};
struct qs_buf_s header;
unsigned long mem_start;
+
+ /* for sct */
+ void *vaddr;
+ bool flg_vmap;
+ bool flg_mode; /* 0: for normal; 1: sct */
+ unsigned int crc;/*ary 2020-11-09 for sct */
};
/*que post afbc tabl end*/
};
/*que loacal buffer exit data end*/
+/************************************************/
+/* que buf sct data */
+enum QBF_SCT_Q_TYPE {
+ QBF_SCT_Q_IDLE,
+ QBF_SCT_Q_READY, /* */
+ QBF_SCT_Q_REQ,
+ QBF_SCT_Q_USED,
+ QBF_SCT_Q_RECYCLE,
+ QBF_SCT_Q_KEEP,
+ QBF_SCT_Q_NUB,
+};
+
+#define DIM_SCT_NUB (POST_BUF_NUM) /* buf number*/
+struct dim_sct_s {
+ struct qs_buf_s header;
+ struct dim_pat_s *pat_buf;
+ unsigned long tab_addr;
+ unsigned int *tab_vaddr;
+ unsigned int tail_cnt;
+ union {
+ unsigned int d32;
+ struct {
+ unsigned int box : 1,
+ pat : 1,
+ vbit : 1, /*vmap flg*/
+ tab : 1,
+ tab_resize : 1,
+ tab_keep : 1,
+ flg_rev : 26;
+ } b;
+ } flg_act;
+};
+
+/* < 33 for dim_mscttop_s flg_err*/
+enum EDIM_SCT_ERR {
+ EDIM_SCT_ERR_BOX,
+ EDIM_SCT_ERR_PAT,
+ EDIM_SCT_ERR_VMAP,
+ EDIM_SCT_ERR_ALLOC,
+ EDIM_SCT_ERR_RESIZE,
+ EDIM_SCT_ERR_FREE,
+ EDIM_SCT_ERR_QUE_2USED,
+ EDIM_SCT_ERR_QUE_2REQ
+};
+
+struct dim_msc_sum_s {
+ unsigned int curr_tt_size;
+ unsigned int max_size; /* max for one frame */
+// unsigned int sum_max_tt_size;
+ unsigned int max_tt_size2;
+ unsigned char curr_nub;
+ unsigned char max_nub;
+
+ unsigned char mts_pst_ready;
+ unsigned char mts_pst_dispaly;
+ unsigned char mts_pst_back;
+ unsigned char mts_pst_free;
+ unsigned char mts_sct_rcc;
+ unsigned char mts_sct_ready;
+ unsigned char mts_sct_used;
+
+};
+
+struct dim_mscttop_s {
+ void *box;
+ unsigned int flg_err;
+ unsigned int max_nub;
+ unsigned int buffer_size;
+ unsigned int buffer_size_nub;
+ /*test*/
+ unsigned int cnt_alloc;
+ unsigned long jiff_no_buf; // for wait
+ bool flg_support;
+ bool flg_no_buf;
+ bool flg_act_box;
+ bool flg_trig_dis;
+ bool flg_allocing;
+ struct mutex lock_ready; /* for sct ready */
+ struct dim_msc_sum_s sum;
+};
+
+/*que sct data end*/
+/************************************************/
+/* que buf for input data mng */
+enum QBF_NINS_Q_TYPE {
+ QBF_NINS_Q_IDLE,
+ QBF_NINS_Q_CHECK,
+ QBF_NINS_Q_USED,
+ QBF_NINS_Q_RECYCL,
+ /*for vfm clear, not back dec vf */
+ /* when reset, move used to usedb */
+ QBF_NINS_Q_USEDB,
+ QBF_NINS_Q_NUB,
+};
+
+#define DIM_NINS_NUB (11) /* buf number*/
+
+struct dsub_nins_s {
+ void *ori;
+ struct vframe_s vfm_cp;
+ struct dim_wmode_s wmode; /*tmp*/
+};
+
+struct dim_nins_s {
+ struct qs_buf_s header;
+ enum EDIM_NIN_TYPE etype; /* this is same for one reg */
+ struct dsub_nins_s c;
+};
+
+/*que buf for input data mng end*/
+/************************************************/
+/* que buf for display data mng */
+enum QBF_NDIS_Q_TYPE {
+ QBF_NDIS_Q_IDLE,
+ QBF_NDIS_Q_USED,
+ QBF_NDIS_Q_DISPLAY,
+// QBF_NDIS_Q_BACK,
+ QBF_NDIS_Q_KEEP,
+ QBF_NDIS_Q_NUB,
+};
+
+#define DIM_NDIS_NUB (12) /* buf number*/
+
+struct dsub_ndis_s {
+ struct di_buf_s *di_buf;
+ struct dim_mm_blk_s *blk;
+
+ struct vframe_s vfm;/* this is for feature */
+ struct di_buffer dbuff; /* @ary_note new interface 1 */
+ struct di_buffer *pbuff; /* @ary_note: new interface 2 */
+ /* maybe others */
+ /* @ary_note: mode1: vfm: used vfm */
+ /* @ary_note: mode2: di local buffer: */
+ /* @ary_note: used dbuff + vfm */
+ /* @ary_note: mode3: di use out buffer */
+ /* used pbuff */
+};
+
+struct dim_ndis_s {
+ struct qs_buf_s header;
+ enum EDIM_NIN_TYPE etype; /* this is same for one reg */
+ struct dsub_ndis_s c;
+};
+
+/*que buf for display data mng end*/
/************************************************/
/* que buf mem config */
enum QBF_MEM_Q_TYPE {
* 2020-06-16 test
************************************************/
+#ifdef MARK_HIS //move up
struct dim_wmode_s {
//enum EDIM_TMODE tmode;
unsigned int buf_type; /*add this to split kinds */
unsigned int seq;
unsigned int seq_sgn;
};
+#endif
enum EDIM_TMODE {
EDIM_TMODE_NONE,
unsigned int mp_uix[K_DI_MP_UIX_NUB];/*module para x*/
struct di_dbg_datax_s dbg_data;
-
- struct dev_vfram_t vfm;
+ unsigned char cfg_cp[EDI_CFG_END];/*2020-12-15*/
+ //n struct dev_vfram_t vfm;
enum vframe_source_type_e src_type;
+ bool ponly;
struct dentry *dbg_rootx; /*dbg_fs*/
unsigned int ch_id;
unsigned int sum_reg_cnt;
unsigned int sum_pst_get;
unsigned int sum_pst_put;
+ unsigned int sum_ext_buf_in;
+ unsigned int sum_ext_buf_in2;
+ unsigned int sum_pre;
+ unsigned int sum_pst;
+ /*@ary_note:*/
+ unsigned int self_trig_mask;
+ unsigned int self_trig_need;
+ unsigned int sum_releas;
+ unsigned int disp_frame_count;
struct dim_sum_s sumx;
struct dim_bypass_s bypass; /*state only*/
enum EDPST_MODE mode;
+// struct pre_ext_s pree;
+ union {
+ unsigned int d32;
+ struct {
+ unsigned int no_buf : 1,
+ scr_err : 1,
+ rev1 : 2,
+ ponly_fst_cnt : 4,
+ rev : 24;
+ } b;
+ } rsc_bypass; /* 2020-11-03 for sct */
+ struct dim_mscttop_s msct_top;
+
/* qb: blk */
struct buf_que_s blk_qb;
struct qs_cls_s blk_q[QBF_BLK_Q_NUB];
//0: unknown, 1: non secure, 2: secure
unsigned int is_secure_pst :2;
//0: unknown, 1: non secure, 2: secure
+ /* qb: sct 2020-11-03 */
+ struct buf_que_s sct_qb;
+ struct qs_cls_s sct_q[QBF_SCT_Q_NUB];
+ struct dim_sct_s sct_bf[DIM_SCT_NUB];
+
+ /* qb: in 2020-12-02 */
+ struct buf_que_s nin_qb;
+ struct qs_cls_s nin_q[QBF_NINS_Q_NUB];
+ struct dim_nins_s nin_bf[DIM_NINS_NUB];
+ /* qb: in 2020-12-02 */
+ struct buf_que_s ndis_qb;
+ struct qs_cls_s ndis_q[QBF_NDIS_Q_NUB];
+ struct dim_ndis_s ndis_bf[DIM_NDIS_NUB];
+
+ struct qs_cls_s ndis_que_ready;
+ struct qs_cls_s ndis_que_kback;
+ struct qs_cls_s npst_que; /*new interface */
+ struct dim_itf_s itf;
};
struct dim_policy_s {
struct di_task tsk;
struct di_mtask mtsk;
+ enum EDIM_TMODE tmode_pre[DI_CHANNEL_MAX];
/*channel state: use enum eDI_TOP_STATE */
atomic_t ch_state[DI_CHANNEL_NUB];
bool flg_hw_int; /*only once*/
struct dim_policy_s policy;
struct dim_mm_t_s mmt;
- struct di_mm_s mm[DI_CHANNEL_NUB];
+ struct div2_mm_s mm[DI_CHANNEL_NUB];
/*new reg/unreg*/
atomic_t trig_reg[DI_CHANNEL_NUB];
atomic_t trig_unreg[DI_CHANNEL_NUB];
unsigned int err_cnt;
};
+struct db_save_s {
+ bool support;
+ bool en_db;
+ bool en_pq;
+ bool update;
+ int mode;/*-1 : not set; 0: set from db, 1: set from pq*/
+ unsigned int addr;
+ unsigned int val_db;
+ unsigned int val_pq;
+ unsigned int mask;
+};
+
struct di_data_l_s {
/*bool cfg_en[K_DI_CFG_NUB];*/ /*cfg_top*/
union di_cfg_tdata_u cfg_en[K_DI_CFG_NUB];
struct di_mng_s mng;
struct di_hpre_s hw_pre;
struct di_hpst_s hw_pst;
+ struct db_save_s db_save[DIM_DB_SAVE_NUB];
const struct dim_hw_opsv_s *hop_l1; /* from sc2 */
struct afd_s di_afd;
const struct hw_ops_s *hop_l2;
#define DBG_M_PL DI_BIT15
#define DBG_M_AFBC DI_BIT16
#define DBG_M_COPY DI_BIT17
-
+#define DBG_M_PQ DI_BIT18
+#define DBG_M_SCT DI_BIT19
+#define DBG_M_NQ DI_BIT20
+#define DBG_M_BPASS DI_BIT21
+#define DBG_M_DCT DI_BIT22
+#define DBG_M_IC DI_BIT28
#define DBG_M_RESET_PRE DI_BIT29
extern unsigned int di_dbg;
#define dbg_mem2(fmt, args ...) dbg_m(DBG_M_MEM2, fmt, ##args)
#define dbg_afbc(fmt, args ...) dbg_m(DBG_M_AFBC, fmt, ##args)
#define dbg_copy(fmt, args ...) dbg_m(DBG_M_COPY, fmt, ##args)
-
+#define dbg_pq(fmt, args ...) dbg_m(DBG_M_PQ, fmt, ##args)
+#define dbg_sct(fmt, args ...) dbg_m(DBG_M_SCT, fmt, ##args)
+#define dbg_nq(fmt, args ...) dbg_m(DBG_M_NQ, fmt, ##args)
+#define dbg_bypass(fmt, args ...) dbg_m(DBG_M_BPASS, fmt, ##args)
+#define dbg_ic(fmt, args ...) dbg_m(DBG_M_IC, fmt, ##args)
char *di_cfgx_get_name(enum EDI_CFGX_IDX idx);
bool di_cfgx_get(unsigned int ch, enum EDI_CFGX_IDX idx);
void di_cfgx_set(unsigned int ch, enum EDI_CFGX_IDX idx, bool en);
static inline void sum_pst_p_clear(unsigned int ch)
{
- get_datal()->ch_data[ch].sum_pst_put = 0;
+ //get_datal()->ch_data[ch].sum_pst_put = 0;
+}
+
+static inline unsigned int get_sum_release(unsigned int ch)
+{
+ return get_datal()->ch_data[ch].sum_releas;
+}
+
+static inline void sum_release_inc(unsigned int ch)
+{
+ get_datal()->ch_data[ch].sum_releas++;
}
/*********************/
/******************************************
* mm
*****************************************/
-static inline struct di_mm_s *dim_mm_get(unsigned int ch)
+static inline struct div2_mm_s *dim_mm_get(unsigned int ch)
{
return &get_datal()->mng.mm[ch];
}
#include "di_pre.h"
#include "di_post.h"
#include "di_dbg.h"
+#include "di_sys.h"
/********************************
*trace:
return &get_datal()->ch_data[ch].dbg_data.vfm_input;
}
+#ifdef MARK_HIS
static struct vframe_s **di_get_dbg_vframe_out(unsigned int ch)
{
return &get_datal()->ch_data[ch].dbg_data.pfm_out;
}
+#endif
/********************************
*timer:
trace_dim_pst_peekx("PST-PEEK-8", index, ustime);
}
+static void trace_slef_trig(unsigned int index)
+{
+ u64 ustime;
+
+ if (di_get_disp_cnt() > DI_TRACE_LIMIT)
+ return;
+
+ ustime = cur_to_usecs();
+ trace_dim_self_trig("P-TRIG", index, ustime);
+}
+
+static void trace_msct(unsigned int index, u64 timer_begin)
+{
+ u64 ustime;
+
+ ustime = cur_to_usecs();
+ trace_dim_sct_alloc("SCT-ALLOC", index, ustime - timer_begin);
+}
+
+static void trace_msct_tail(unsigned int index, unsigned int used_cnt)
+{
+ trace_dim_sct_tail("SCT-TAILX", index, (u64)used_cnt);
+}
+
const struct dim_tr_ops_s dim_tr_ops = {
.pre = trace_pre,
.post = trace_post,
.post_ir = trace_post_irq,
.post_do = trace_post_doing,
.post_peek = trace_post_peek,
+ .sct_alloc = trace_msct,
+ .sct_tail = trace_msct_tail,
+ .self_trig = trace_slef_trig,
};
void dbg_timer(unsigned int ch, enum EDBG_TIMER item)
{
int i;
struct canvas_config_s *pcvs;
+ struct dim_rpt_s *rpt;
if (!pvfm) {
seq_puts(seq, "war: dump vframe NULL\n");
return 0;
}
- seq_printf(seq, "%-15s:0x%p\n", "addr", pvfm);
+ seq_printf(seq, "%-15s:0x%px\n", "addr", pvfm);
seq_printf(seq, "%-15s:%d\n", "index", pvfm->index);
seq_printf(seq, "%-15s:%d\n", "index_disp", pvfm->index_disp);
seq_printf(seq, "%-15s:%d\n", "omx_index", pvfm->omx_index);
seq_printf(seq, "%-15s:%d\n", "disp_pts", pvfm->disp_pts);
seq_printf(seq, "%-15s:%lld\n", "disp_pts_us64", pvfm->disp_pts_us64);
seq_printf(seq, "%-15s:%lld\n", "timestamp", pvfm->timestamp);
- seq_printf(seq, "%-15s:%d\n", "flag", pvfm->flag);
+ seq_printf(seq, "%-15s:0x%x\n", "flag", pvfm->flag);
seq_printf(seq, "\t%-15s:%d\n", "flag:VFRAME_FLAG_DOUBLE_FRAM",
pvfm->flag & VFRAME_FLAG_DOUBLE_FRAM);
seq_printf(seq, "%-15s:0x%x\n", "canvas0Addr", pvfm->canvas0Addr);
seq_printf(seq, "%-15s:0x%p\n", "early_process_fun",
pvfm->early_process_fun);
seq_printf(seq, "%-15s:0x%p\n", "process_fun",
- pvfm->early_process_fun);
+ pvfm->process_fun);
seq_printf(seq, "%-15s:0x%p\n", "private_data",
- pvfm->early_process_fun);
+ pvfm->private_data);
/* vframe properties */
for (i = 0; i < pvfm->plane_num; i++) {
pcvs = &pvfm->canvas0_config[i];
seq_printf(seq, "%-15s:%d\n", "canvas0_cfg", i);
+ #ifdef CVS_UINT
seq_printf(seq, "\t%-15s:0x%x\n", "phy_addr",
pcvs->phy_addr);
+ #else
+ seq_printf(seq, "\t%-15s:0x%lx\n", "phy_addr",
+ pcvs->phy_addr);
+ #endif
seq_printf(seq, "\t%-15s:%d\n", "width",
pcvs->width);
seq_printf(seq, "\t%-15s:%d\n", "height",
seq_printf(seq, "%-15s\n", "vf_ext");
else
seq_printf(seq, "%-15s\n", "vf_ext:none");
+ rpt = dim_api_getrpt(pvfm);
+ if (rpt) {
+ if (rpt->spt_bits) {
+ seq_printf(seq, "bits[0x%x], map0[0x%x], map1[0x%x],map2[0x%x],map3[0x%x],map15[0x%x], bld2[0x%x]\n",
+ rpt->spt_bits,
+ rpt->dct_map_0,
+ rpt->dct_map_1,
+ rpt->dct_map_2,
+ rpt->dct_map_3,
+ rpt->dct_map_15,
+ rpt->dct_bld_2);
+ }
+ }
return 0;
}
/***********************/
/* debug output vframe */
/***********************/
-void didbg_vframe_out_save(unsigned int ch, struct vframe_s *pvfm)
+void didbg_vframe_out_save(unsigned int ch,
+ struct vframe_s *pvfm, unsigned int id)
{
//unsigned int ch;
- struct vframe_s **pvfm_t;
+ //struct vframe_s **pvfm_t;
//ch = DI_SUB_ID_S0;
if (!di_cfgx_get(ch, EDI_DBG_CFGX_IDX_VFM_OT))
return;
- pvfm_t = di_get_dbg_vframe_out(ch);
- *pvfm_t = pvfm;
+ //pvfm_t = di_get_dbg_vframe_out(ch);
+ /* *pvfm_t = pvfm; */
+ get_datal()->ch_data[ch].dbg_data.pfm_out = pvfm;
+ if (dimp_get(edi_mp_bypass_post_state)) {
+ PR_INF("%s:pvfm:0x%px\n", __func__,
+ get_datal()->ch_data[ch].dbg_data.pfm_out);
+ }
}
static int seq_file_vframe_out_show(struct seq_file *seq, void *v)
return 0;
}
- seq_file_vframe(seq, v, *di_get_dbg_vframe_out(ch));
+ //seq_file_vframe(seq, v, *di_get_dbg_vframe_out(ch));
+ seq_file_vframe(seq,
+ v,
+ get_datal()->ch_data[ch].dbg_data.pfm_out);
return 0;
}
return count;
}
+static int dbg_q_sct_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ dbg_q_listid(s, &pch->sct_qb);
+
+ return 0;
+}
+
+static int dbg_sct_peek_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+ struct dim_sct_s *qsct;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ qsct = qsct_peek(pch, QBF_SCT_Q_IDLE);
+ if (!qsct) {
+ seq_printf(s, "%s:\n", "null");
+ return 0;
+ }
+
+ seq_printf(s, "\t%d:\n", qsct->header.index);
+
+ return 0;
+}
+
+static int dbg_sct_used_pat_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+// struct dim_sct_s *qsct;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ dbg_sct_used(s, pch);
+ return 0;
+}
+
+static int dbg_q_nins_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ dbg_q_listid(s, &pch->nin_qb);
+
+ dbg_q_list_qbuf(s, &pch->nin_qb);
+
+ //qbuf_dbg_checkid(&pch->nin_qb, 10);
+ return 0;
+}
+
+static int dbg_nins_peek_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+ struct dim_nins_s *nin;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ nin = nins_peek(pch);
+ if (!nin) {
+ seq_printf(s, "%s:\n", "null");
+ return 0;
+ }
+
+ seq_printf(s, "\t%d:\n", nin->header.index);
+
+ return 0;
+}
+
+static int dbg_q_ndis_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ dbg_q_listid(s, &pch->ndis_qb);
+
+ //dbg_q_list_qbuf(s, &pch->ndis_qb);
+ ndis_dbg_qbuf_detail(s, pch);
+
+ //qbuf_dbg_checkid(&pch->nin_qb, 10);
+ return 0;
+}
+
+static int dbg_q_ndkb_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ ndkb_dbg_list(s, pch);
+ return 0;
+}
+
/**************************************
*
* show vframe current
/********************************/
/* post_ready_list */
/********************************/
+ #ifdef MARK_HIS //@ary_note: todo
di_que_list(ch, QUE_POST_READY, &tmpa[0], &psize);
seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
seq_printf(seq, "%s\n", splt2);
}
seq_printf(seq, "%s\n", splt);
-
+ #endif
/********************************/
/* display_list */
/********************************/
return 0;
}
+static int hw_info_show(struct seq_file *s, void *v)
+{
+ seq_printf(s, "hw_infor:%s:\n", get_datal()->hop_l1->info.name);
+ seq_printf(s, "\tupdate:%s:\n", get_datal()->hop_l1->info.update);
+ return 0;
+}
+
static ssize_t dbg_crc_store(struct file *file, const char __user *userbuf,
size_t count, loff_t *ppos)
{
return 0;
}
- dim_dbg_release_keep_all(ch);
+ //dim_dbg_release_keep_all(ch);
return count;
}
task_send_ready();
}
+void dbg_f_pq_sel(unsigned int para)
+{
+ unsigned int data[2];
+ static unsigned int cnt;
+
+ if (para == 0) {
+ dim_pq_db_sel(DIM_DB_SV_DCT_BL2, 0, NULL);
+ } else if (para == 1) {
+ data[0] = cnt << 16;
+ data[1] = 0x1ff0000;
+ dim_pq_db_sel(DIM_DB_SV_DCT_BL2, 1, &data[0]);
+ PR_INF("%s:data[0x%x],data[0x%x],cnt[0x%x]\n",
+ __func__, data[0], data[1], cnt);
+ cnt++;
+ }
+}
+
const struct di_dbg_func_s di_func_tab[] = {
{EDI_DBG_F_00, dbg_f_post_disable,
"dimh_disable_post_deinterlace_2", "no para"},
"trig post gate off/on", "no para"},
{EDI_DBG_F_07, hpst_dbg_trig_mif,
"trig post mif off/free", "no para"},
+ {EDI_DBG_F_08, dbg_f_pq_sel,
+ "trig pq set", "no para"},
};
static ssize_t wfunc_store(struct file *file, const char __user *userbuf,
return 0;
}
+static int dbg_afde0_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afe_reg_v3(s, EAFBC_ENC0);
+ return 0;
+}
+
+static int dbg_afde1_reg_show(struct seq_file *s, void *v)
+{
+ dbg_afe_reg_v3(s, EAFBC_ENC1);
+ return 0;
+}
+
static int dbg_afd_bits_afbc0_show(struct seq_file *s, void *v)
{
//struct reg_afbs_s *pafbc = get_afbc(0);
return 0;
}
+static int dbg_afd_bits_afbce0_show(struct seq_file *s, void *v)
+{
+ dbg_afbce_bits_show(s, EAFBC_ENC0);
+
+ return 0;
+}
+
+static int dbg_afd_bits_afbce1_show(struct seq_file *s, void *v)
+{
+ dbg_afbce_bits_show(s, EAFBC_ENC1);
+ return 0;
+}
+
/* mif */
static int mif_inp_reg_show(struct seq_file *s, void *v)
{
return 0;
}
+static int mif_nr_reg_show(struct seq_file *s, void *v)
+{
+ dbg_mif_wr_bits_show(s, EDI_MIFSM_NR);
+ return 0;
+}
+
+static int mif_wr_reg_show(struct seq_file *s, void *v)
+{
+ dbg_mif_wr_bits_show(s, EDI_MIFSM_WR);
+ return 0;
+}
+
static int dbg_mif_print_show(struct seq_file *s, void *v)
{
if (DIM_IS_IC_EF(SC2)) {
DEFINE_SEQ_SHOW_ONLY(dbg_afd_bits_afbc5);
DEFINE_SEQ_SHOW_ONLY(dbg_afd_bits_afbc6);
DEFINE_SEQ_SHOW_ONLY(dbg_afd_bits_afbc7);
+DEFINE_SEQ_SHOW_ONLY(dbg_afd_bits_afbce0);
+DEFINE_SEQ_SHOW_ONLY(dbg_afd_bits_afbce1);
+
+DEFINE_SEQ_SHOW_ONLY(dbg_afde0_reg);
+DEFINE_SEQ_SHOW_ONLY(dbg_afde1_reg);
/* mif */
DEFINE_SEQ_SHOW_ONLY(mif_inp_reg);
DEFINE_SEQ_SHOW_ONLY(mif_if0_reg);
DEFINE_SEQ_SHOW_ONLY(mif_if1_reg);
DEFINE_SEQ_SHOW_ONLY(mif_if2_reg);
+DEFINE_SEQ_SHOW_ONLY(mif_nr_reg);
+DEFINE_SEQ_SHOW_ONLY(mif_wr_reg);
DEFINE_SEQ_SHOW_ONLY(reg_contr);
+/* hw */
+DEFINE_SEQ_SHOW_ONLY(hw_info);
+
DEFINE_SEQ_SHOW_ONLY(dbg_mif_print);
DEFINE_STORE_ONLY(dbg_crc);
DEFINE_STORE_ONLY(dbg_pip);
DEFINE_SEQ_SHOW_ONLY(dbg_dct_mif);
DEFINE_SEQ_SHOW_ONLY(dbg_dct_contr);
DEFINE_SEQ_SHOW_ONLY(dbg_dct_core);
-
+DEFINE_SEQ_SHOW_ONLY(dbg_q_sct);
+DEFINE_SEQ_SHOW_ONLY(dbg_sct_peek);
+DEFINE_SEQ_SHOW_ONLY(dbg_sct_used_pat);
+DEFINE_SEQ_SHOW_ONLY(dim_dbg_sct_top);
+DEFINE_SEQ_SHOW_ONLY(dbg_q_nins);
+DEFINE_SEQ_SHOW_ONLY(dbg_nins_peek);
+DEFINE_SEQ_SHOW_ONLY(dbg_q_ndis);
+DEFINE_SEQ_SHOW_ONLY(dbg_q_ndkb);
+
+//test:
+#ifdef TST_NEW_INS_INTERFACE
+DEFINE_SEQ_SHOW_ONLY(dim_dbg_tst_in);
+#endif
/**********************/
struct di_dbgfs_files_t {
{"reg_afd5", S_IFREG | 0644, &dbg_afd5_reg_fops},
{"reg_afd6", S_IFREG | 0644, &dbg_afd6_reg_fops},
{"reg_afd7", S_IFREG | 0644, &dbg_afd7_reg_fops},
+ {"reg_afe0", S_IFREG | 0644, &dbg_afde0_reg_fops},
+ {"reg_afe1", S_IFREG | 0644, &dbg_afde1_reg_fops},
{"bits_afd0", S_IFREG | 0644, &dbg_afd_bits_afbc0_fops},
{"bits_afd1", S_IFREG | 0644, &dbg_afd_bits_afbc1_fops},
{"bits_afd2", S_IFREG | 0644, &dbg_afd_bits_afbc2_fops},
{"bits_afd5", S_IFREG | 0644, &dbg_afd_bits_afbc5_fops},
{"bits_afd6", S_IFREG | 0644, &dbg_afd_bits_afbc6_fops},
{"bits_afd7", S_IFREG | 0644, &dbg_afd_bits_afbc7_fops},
+ {"bits_afe0", S_IFREG | 0644, &dbg_afd_bits_afbce0_fops},
+ {"bits_afe1", S_IFREG | 0644, &dbg_afd_bits_afbce1_fops},
{"reg_mif_inp", S_IFREG | 0644, &mif_inp_reg_fops},
{"reg_mif_mem", S_IFREG | 0644, &mif_mem_reg_fops},
{"reg_mif_ch2", S_IFREG | 0644, &mif_chan2_reg_fops},
{"reg_mif_if0", S_IFREG | 0644, &mif_if0_reg_fops},
{"reg_mif_if1", S_IFREG | 0644, &mif_if1_reg_fops},
{"reg_mif_if2", S_IFREG | 0644, &mif_if2_reg_fops},
+ {"reg_mif_nr", S_IFREG | 0644, &mif_nr_reg_fops},
+ {"reg_mif_wr", S_IFREG | 0644, &mif_wr_reg_fops},
{"regmif", S_IFREG | 0644, &dbg_mif_print_fops},
+ {"hw_info", S_IFREG | 0644, &hw_info_fops},
{"dct_mif", S_IFREG | 0644, &dbg_dct_mif_fops},
{"dct_ctr", S_IFREG | 0644, &dbg_dct_contr_fops},
{"dct_other", S_IFREG | 0644, &dbg_dct_core_fops},
+#ifdef TST_NEW_INS_INTERFACE
+ {"tst_list_in", S_IFREG | 0644, &dim_dbg_tst_in_fops},
+#endif
};
{"mpxw", S_IFREG | 0644, &mpxw_fops},
{"vfmc", S_IFREG | 0644, &seq_file_curr_vframe_fops},
{"dbg_crc", S_IFREG | 0644, &dbg_crc_fops},
- {"dbg_pip", S_IFREG | 0644, &dbg_pip_fops}
+ {"dbg_pip", S_IFREG | 0644, &dbg_pip_fops},
+ {"sct_top", S_IFREG | 0644, &dim_dbg_sct_top_fops},
+ {"list_sct", S_IFREG | 0644, &dbg_q_sct_fops},
+ {"list_sct_peek", S_IFREG | 0644, &dbg_sct_peek_fops},
+ {"list_sct_used", S_IFREG | 0644, &dbg_sct_used_pat_fops},
+ {"list_ndis", S_IFREG | 0644, &dbg_q_ndis_fops},
+ {"list_ndkb", S_IFREG | 0644, &dbg_q_ndkb_fops},
+ {"list_nin", S_IFREG | 0644, &dbg_q_nins_fops},
+ {"list_nin_peek", S_IFREG | 0644, &dbg_nins_peek_fops}
};
void didbg_fs_init(void)
void di_cfgx_init_val(void);
void didbg_vframe_in_copy(unsigned int ch, struct vframe_s *pvfm);
-void didbg_vframe_out_save(unsigned int ch, struct vframe_s *pvfm);
+void didbg_vframe_out_save(unsigned int ch,
+ struct vframe_s *pvfm, unsigned int id);
/********************************
*debug register:
void (*post_ir)(unsigned int index);
void (*post_do)(unsigned int index);
void (*post_peek)(unsigned int index);
+ void (*sct_alloc)(unsigned int index, u64 timer_begin);
+ void (*sct_tail)(unsigned int index, unsigned int used_cnt);
+ void (*self_trig)(unsigned int index);
};
extern const struct dim_tr_ops_s dim_tr_ops;
void dbg_timer(unsigned int ch, enum EDBG_TIMER item);
+void dim_dump_mif_state(struct DI_MIF_S *mif, char *name);
#endif /*__DI_DBG_H__*/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* drivers/amlogic/media/di_multi/di_decont.c
*
return false;
}
+/* dcntr dynamic used dbg_dct BIT:6-8*/
+bool dcntr_dynamic_alpha_1(void)
+{
+ if (dbg_dct & DI_BIT6)
+ return true;
+ return false;
+}
+
+bool dcntr_dynamic_alpha_2(void)
+{
+ if (dbg_dct & DI_BIT7)
+ return true;
+ return false;
+}
+
+bool dcntr_dynamic_disable(void)
+{
+ if (dbg_dct & DI_BIT8)
+ return true;
+ return false;
+}
+
enum ECNTR_MIF_IDX {
ECNTR_MIF_IDX_DIVR,
ECNTR_MIF_IDX_GRID,
st_off : 1,
n_set : 1,
n_up : 1,
- rev1 : 1,
+ n_rp : 1,
cvs_y : 8,
cvs_uv : 8,
{
if (!pcore)
return;
+ if (!(di_dbg & DBG_M_DCT))
+ return;
dim_print("%s:\n", __func__);
dim_print("\tlsize<%d,%d,%d,%d>:\n",
if (!pin)
return;
+ if (!(di_dbg & DBG_M_DCT))
+ return;
dim_print("%s:\n", __func__);
dim_print("\tsize<%d,%d,%d,%d>:\n", pin->x_size, pin->y_size,
pin->ds_x, pin->ds_y);
{
if (!pmif)
return;
+ if (!(di_dbg & DBG_M_DCT))
+ return;
dim_print("%s:\n", __func__);
dim_print("\tsize<%d,%d,%d,%d>:\n",
pmif->mif_x_start, pmif->mif_x_end,
};
static unsigned int get_mif_addr(unsigned int mif_index,
- enum E1INT_RMIF_REG reg_index)
+ enum E1INT_RMIF_REG reg_index)
{
unsigned int reg_addr = DCNTR_DIVR_RMIF_CTRL4;
const unsigned int *reg;
((ysize >> pcfg->in.DS_RATIO) << 16) |
(ysize >> (pcfg->in.DS_RATIO + 1)));
pcfg->st_set = 1;
- pcfg->st_pause = 1;
+ //pcfg->st_pause = 1;
pcfg->n_set = 0;
dim_print("rd:0x%x,0x%x\n", DCNTR_GRID_RMIF_CTRL2,
op->rd(DCNTR_GRID_RMIF_CTRL2));
dim_print("rd:0x%x,0x%x\n",
DCNTR_GRID_RMIF_CTRL2, op->rd(DCNTR_GRID_RMIF_CTRL2));
- if (pcfg->st_pause && ((dbg_dct & DI_BIT0) == 0))
+ if ((dbg_dct & DI_BIT0) == 0) {
+ if ((dbg_dct & DI_BIT2) == 0)
+ di_pq_db_setting(DIM_DB_SV_DCT_BL2);
+
op->bwr(DI_PRE_CTRL, 1, 15, 1);// decontour enable
+ }
pcfg->n_up = 0;
}
+void dcntr_dynamic_setting(struct dim_rpt_s *rpt)
+{
+ u64 map_0;
+ u64 map_1;
+ u64 map_2;
+ u64 map_3;
+ u64 map_15;
+ u64 map_count;
+ unsigned int bld_2;
+ unsigned int val_db;
+ unsigned int pdate[2];
+ unsigned int alpha;
+ unsigned int thr = 60; /* map_count default 60*/
+ unsigned int target = 256; /*max 256*/
+ struct db_save_s *dbp;
+ const struct reg_acc *op = &di_pre_regset;
+
+ if (!rpt || dcntr_dynamic_disable()) {
+ dbg_pq("%s rpt is null or suspend dcntr dynamic.\n", __func__);
+ return;
+ }
+ /*get val form db*/
+ dbp = &get_datal()->db_save[DIM_DB_SV_DCT_BL2];
+ if (!dbp) {
+ dbg_pq("val form db failed, default set 0.\n");
+ val_db = 0;
+ } else {
+ /*bits[16-24] is bld value*/
+ val_db = (dbp->val_db & dbp->mask) >> 16;
+ dbg_pq("val:%d form db.\n", val_db);
+ }
+ /*debug alpha dtc bit6:1, bit7:9*/
+ if (dcntr_dynamic_alpha_1())
+ alpha = 1;
+ else if (dcntr_dynamic_alpha_2())
+ alpha = 9;
+ else
+ alpha = 3;
+
+ map_0 = rpt->dct_map_0;
+ map_1 = rpt->dct_map_1;
+ map_2 = rpt->dct_map_2;
+ map_3 = rpt->dct_map_3;
+ map_15 = rpt->dct_map_15;
+ bld_2 = rpt->dct_bld_2;
+ map_count = (map_0 + map_1 + map_2 + map_3) * 10000;
+ dbg_pq("bits[0x%x],mp0-3[%lld,%lld,%lld,%lld]\n",
+ rpt->spt_bits, map_0, map_1, map_2, map_3);
+ dbg_pq("mp15[%lld],count[%lld],bld[0x%x]\n",
+ map_15, map_count, rpt->dct_bld_2 << 16);
+ if (map_count < thr * map_15) {
+ if (bld_2 == target)
+ return;
+ /*+7 is compensation for loss of accuracy*/
+ bld_2 = alpha * target + (10 - alpha) * bld_2 + 7;
+ pdate[0] = (bld_2 / 10);
+
+ if (pdate[0] > target)
+ pdate[0] = target;
+ dbg_pq("case:1, pdate:%x\n", pdate[0]);
+ } else {
+ if (bld_2 == val_db)
+ return;
+ /*db value default 0, function:bld2 = db_val*a + (10-a)*bld_2 */
+ bld_2 = val_db * alpha + (10 - alpha) * bld_2;
+ pdate[0] = (bld_2 / 10);
+
+ if (pdate[0] < val_db)
+ pdate[0] = val_db;
+ dbg_pq("case:0, pdate:%x\n", pdate[0]);
+ }
+ op->bwr(DCTR_BLENDING2, pdate[0], 16, 9);
+}
+
+void dcntr_pq_tune(struct dim_rpt_s *rpt)
+{
+ const struct reg_acc *op = &di_pre_regset;
+// unsigned int tmp[3];
+ struct dcntr_core_s *pcfg = &di_dcnt;
+
+ if (!pcfg->n_rp)
+ return;
+ rpt->spt_bits |= DI_BIT0;
+ rpt->dct_map_0 = op->rd(DCTR_MAP_HIST_0);
+ rpt->dct_map_1 = op->rd(DCTR_MAP_HIST_1);
+ rpt->dct_map_2 = op->rd(DCTR_MAP_HIST_2);
+ rpt->dct_map_3 = op->rd(DCTR_MAP_HIST_3);
+ rpt->dct_map_15 = op->rd(DCTR_MAP_HIST_15);
+ rpt->dct_bld_2 = op->brd(DCTR_BLENDING2, 16, 9);
+ pcfg->n_rp = 0;
+ dim_print("%s:0x%x\n", __func__, rpt->dct_map_0);
+
+ dcntr_dynamic_setting(rpt);
+}
+
void dcntr_dis(void)
{
const struct reg_acc *op = &di_pre_regset;
struct dcntr_core_s *pcfg = &di_dcnt;
- if (pcfg->st_pause)
+ if (pcfg->st_pause) {
+ dim_print("%s\n", __func__);
op->bwr(DI_PRE_CTRL, 0, 15, 1);// decontour enable
+ pcfg->st_pause = 0;
+ pcfg->n_rp = 1;
+ }
}
void dcntr_set(void)
(pcfg->in.x_size >> 1));
pcfg->n_demo = 0;
}
- if (pcfg->n_set)
+ if (pcfg->n_set) {
dcntr_post();
- else if (pcfg->n_up)
+ pcfg->st_pause = 1;
+ } else if (pcfg->n_up) {
dcntr_update();
+ pcfg->st_pause = 1;
+ }
}
static void dbg_pre_cfg(struct dcntr_mem_s *pprecfg)
return;
dim_print("use_org[%d],ration[%d]\n",
- pprecfg->use_org, pprecfg->ds_ratio);
+ pprecfg->use_org, pprecfg->ds_ratio);
dim_print("grd_addr[0x%x],y_addr[0x%x], c_addr[0x%x]\n",
- pprecfg->grd_addr,
- pprecfg->yds_addr,
- pprecfg->cds_addr);
+ pprecfg->grd_addr,
+ pprecfg->yds_addr,
+ pprecfg->cds_addr);
dim_print("out_fmt[0x%x],y_len[%d],c_len[%d]\n",
pprecfg->pre_out_fmt,
pprecfg->yflt_wrmif_length,
if (!pcfg->flg_int)
return;
/*dbg*/
- if (dbg_dct & 0x10)
+ if (dbg_dct & DI_BIT4)
pcfg->in.grid_use_fix = 1;
pcfg->n_set = 0;
if (pcfg->in.use_cvs) {
cvss = &get_datal()->cvs;
- cvs_y = cvss->post_idx[1][1]; //note: use by copy funct
+ cvs_y = cvss->post_idx[1][1];
+ //note: use by copy function
cvs_uv = cvss->post_idx[1][5];
pcfg->cvs_y = (unsigned char)cvs_y;
pcfg->cvs_uv = (unsigned char)cvs_uv;
pcfg->n_set = 0;
pcfg->n_up = 0;
} else {
- if (chg || (dbg_dct & 0x20))
+ if (chg || (dbg_dct & DI_BIT5))
pcfg->n_set = 1;
else
pcfg->n_up = 1;
pcfg->st_pause = 0;
pcfg->n_set = 0;
pcfg->n_up = 0;
+ pcfg->n_rp = 0;
pcfg->in.grd_num_mode = 2;
pcfg->in.use_cvs = 1;
int dbg_dct_core_show(struct seq_file *s, void *v)
{
struct dcntr_core_s *pcore;
+ struct db_save_s *dbp;
pcore = &di_dcnt;
seq_printf(s, "%s:\n", __func__);
seq_printf(s, "\tlsize<%d,%d,%d,%d>:\n",
- pcore->l_xsize, pcore->l_ysize,
- pcore->l_ds_x, pcore->l_ds_y);
+ pcore->l_xsize, pcore->l_ysize,
+ pcore->l_ds_x, pcore->l_ds_y);
seq_printf(s, "\tint[%d],sup[%d],st_set[%d],st_pause[%d]\n",
- pcore->flg_int, pcore->support, pcore->st_set,
- pcore->st_pause);
+ pcore->flg_int, pcore->support, pcore->st_set,
+ pcore->st_pause);
seq_printf(s, "\tst_off[%d],n_set[%d],n_up[%d],cvs_y[%d],cvs_uv[%d]\n",
- pcore->st_off, pcore->n_set, pcore->n_up,
- pcore->cvs_y, pcore->cvs_uv);
+ pcore->st_off, pcore->n_set, pcore->n_up,
+ pcore->cvs_y, pcore->cvs_uv);
seq_printf(s, "\t:bypass:%d\n", pcore->n_bypass);
+ seq_printf(s, "%s:\n", "dct_bl2");
+ dbp = &get_datal()->db_save[DIM_DB_SV_DCT_BL2];
+ seq_printf(s, "\t:spt:%d;update:%d;add[0x%x];mask[0x%x]\n",
+ dbp->support,
+ dbp->update,
+ dbp->addr,
+ dbp->mask);
+ seq_printf(s, "\t:db:en:%d,val[0x%x],pq:%d,0x%x\n",
+ dbp->en_db,
+ dbp->val_db,
+ dbp->en_pq,
+ dbp->val_pq);
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * drivers/amlogic/media/di_multi/di_interlace.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/semaphore.h>
+#include <linux/kfifo.h>
+#include <linux/spinlock.h>
+
+#include "deinterlace.h"
+#include "di_data_l.h"
+#include "di_pre.h"
+#include "di_prc.h"
+#include "di_dbg.h"
+#include "di_que.h"
+#include "di_task.h"
+
+#include "di_vframe.h"
+
+#ifdef MARK_HIS
+const struct di_init_parm dim_cfg_parm_default = {
+ .work_mode = WORK_MODE_PRE_POST,
+ .buffer_mode = BUFFER_MODE_ALLOC_BUF,
+ .ops = {
+ .empty_input_done = NULL,
+ .fill_output_done = NULL,
+ },
+};
+#endif
+#ifdef MARK_HIS //@ary_note to-do
+/**********************************************************
+ * ops
+ **********************************************************/
+static void *ins_peek(struct di_ch_s *pch)
+{
+ unsigned int index;
+
+ if (!qued_ops.peek(pch, QUED_T_IS_IN, &index))
+ return NULL;
+ return (void *)pch->interf.u.dinst.in[index];
+}
+
+static void *ins_get(struct di_ch_s *pch)
+{
+ unsigned int index;
+ struct di_buffer *dbuf;
+ unsigned int dbg_cnt1, dbg_cnt2;
+
+ if (!qued_ops.move(pch,
+ QUED_T_IS_IN,
+ QUED_T_IS_FREE, &index)) {
+ dbg_cnt1 = qued_ops.list_count(pch, QUED_T_IS_IN);
+ dbg_cnt2 = qued_ops.list_count(pch, QUED_T_IS_FREE);
+ PR_ERR("%s:no space,%d,%d\n", __func__, dbg_cnt1, dbg_cnt2);
+ return NULL;
+ }
+ sum_g_inc(pch->ch_id);
+ dbuf = pch->interf.u.dinst.in[index];
+ pch->interf.u.dinst.in[index] = NULL;
+ return (void *)dbuf;
+}
+
+static void ins_put(void *data, struct di_ch_s *pch)
+{
+ struct dim_inter_s *pintf = &pch->interf;
+ struct di_operations_s *ops;
+
+ ops = &pintf->u.dinst.parm.ops;
+ if (ops->empty_input_done) {
+ sum_p_inc(pch->ch_id);
+ ops->empty_input_done((struct di_buffer *)data);
+ //debug only dump_stack();
+ }
+}
+
+const struct dim_itf_ops_s inst_in_ops = {
+ .peek = ins_peek,
+ .get = ins_get,
+ .put = ins_put,
+};
+
+/* mode 2 for drop */
+void ins_2_doing(struct di_ch_s *pch, bool bypass, struct di_buf_s *pstdi_buf)
+{
+ unsigned int ch = pch->ch_id;
+ struct di_buf_s *di_buf = NULL; /*post nobuf buffer*/
+ bool ret;
+ struct di_buffer *ins_buf, *ins_in;
+ unsigned int idx;
+ struct dim_inter_s *pintf;
+ struct vframe_s *vfmin, *vfmout;
+ struct canvas_config_s cvs[2];
+
+ if (di_que_is_empty(ch, QUE_POST_NOBUF))
+ return;
+
+ if (qued_ops.is_empty(pch, QUED_T_IS_PST_DOBEF))
+ return;
+
+ di_buf = di_que_peek(ch, QUE_POST_NOBUF);
+ dim_print("%s:1:%p,buf[%d],t[%d]\n", __func__, di_buf,
+ di_buf->index, di_buf->type);
+ trace_buf(di_buf, DIM_QUE_PEEK, QUE_POST_NOBUF,
+ (DIM_DBG_MARK | 0x00000001));
+ ret = di_que_out(ch, QUE_POST_NOBUF, di_buf);
+ if (!ret) {
+ PR_ERR("%s:no buf?\n", __func__);
+ return;
+ }
+
+ pintf = &pch->interf;
+ qued_ops.out(pch, QUED_T_IS_PST_DOBEF, &idx);
+
+ ins_buf = pintf->u.dinst.out[idx];
+ if (!ins_buf) {
+ PR_ERR("%s:out is null\n", __func__);
+ return;
+ }
+ di_buf->c.pdvfm->vfm_out = pintf->u.dinst.out[idx];
+ pintf->u.dinst.out[idx] = NULL;
+ qued_ops.in(pch, QUED_T_IS_PST_FREE, idx);
+
+ trace_buf(di_buf, DIM_QUE_OUT, QUE_POST_NOBUF,
+ (DIM_DBG_MARK | 0x00000002));
+
+ dbg_dbg("%s:ch[%d],type[%d], id[%d]\n", __func__, pch->ch_id,
+ di_buf->type, di_buf->index);
+ dbg_dbg("ins_buf,type[%d], id[%d]\n",
+ ins_buf->mng.type,
+ ins_buf->mng.index);
+ if (!ins_buf)
+ PR_ERR("%s:out2 is null\n", __func__);
+
+ /*in*/
+ ins_in = (struct di_buffer *)di_buf->c.pdvfm->vfm_in;
+ vfmin = ins_in->vf;
+ vfmout = ins_buf->vf;
+ if (!di_buf->c.wmode.is_eos) {
+ /*copy vfm */
+ memcpy(&cvs[0], &vfmout->canvas0_config[0], sizeof(cvs));
+ memcpy(vfmout, vfmin, sizeof(*vfmout));
+ memcpy(&vfmout->canvas0_config[0],
+ &cvs[0], sizeof(cvs));
+ }
+
+ if (!di_buf->c.wmode.is_bypass) {
+ //di_buf->nr_adr = ins_buf->phy_addr;
+ //di_buf->nr_adr
+ //= ins_buf->vf->canvas0_config[0].phy_addr;
+ //ins_buf->phy_addr;
+ dim_ins_cnt_post_cvs_size2(di_buf, ins_buf, ch);
+ } else {
+ /* bypass */
+ if (di_buf->c.wmode.is_eos) {
+ ins_buf->flag |= DI_FLAG_EOS;
+ PR_INF("%s:eos\n", __func__);
+ } else {
+ ins_buf->flag |= DI_FLAG_BUF_BY_PASS;
+ }
+ dim_print("%s:%p bypass\n", __func__, ins_buf);
+ }
+ dbg_vfm(vfmout, 1);
+ trace_buf(di_buf, DIM_QUE_IN, QUE_POST_DOING,
+ (DIM_DBG_MARK | 0x00000003));
+ dim_print("%s:%p,buf[%d],t[%d]\n", __func__,
+ di_buf, di_buf->index, di_buf->type);
+ di_que_in(ch, QUE_POST_DOING, di_buf);
+}
+#endif //@ary_note todo
+
+/**************************************
+ * bit 0: force no release
+ * bit 1: dbg for buffer
+ **************************************/
+
+static unsigned int new_int;
+module_param_named(new_int, new_int, uint, 0664);
+
+bool dim_dbg_new_int(unsigned int id)
+{
+ bool ret = false;
+ /* id is 1 ~ 32 */
+
+ if (id > 32 || id == 0)
+ return false;
+
+ if (bget(&new_int, id - 1))
+ ret = true;
+
+ return ret;
+}
+
+static void nins_m_unreg_new(struct di_ch_s *pch)
+{
+}
+
+/**************************************
+ * nins_m_recycle
+ * op_back_input
+ * _RECYCL -> _IDLE
+ * back vfm to dec
+ * run in main
+ **************************************/
+
+static void nins_m_recycle_ins(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ int i;
+ unsigned int cnt, ch;
+ struct dim_nins_s *ins;
+ //struct vframe_s *vfm;
+ struct di_buffer *buffer;
+
+ if (!pch || pch->itf.etype != EDIM_NIN_TYPE_INS) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ ch = pch->ch_id;
+ pbufq = &pch->nin_qb;
+
+ cnt = qbufp_count(pbufq, QBF_NINS_Q_RECYCL);
+
+ if (!cnt)
+ return;
+ //qbuf_dbg_check_in_buffer_id(1);
+
+ for (i = 0; i < cnt; i++) {
+ ins = nins_move(pch, QBF_NINS_Q_RECYCL, QBF_NINS_Q_IDLE);
+ // vfm = (struct vframe_s *)ins->c.ori;
+ buffer = (struct di_buffer *)ins->c.ori;
+ ins->c.ori = NULL;
+ if (buffer) {
+// dim_dbg_buffer(buffer, 10);
+ //pw_vf_put(vfm, ch);
+ //pw_vf_notify_provider(ch,
+ // VFRAME_EVENT_RECEIVER_PUT, NULL);
+ pch->itf.u.dinst.parm.ops.empty_input_done(buffer);
+ sum_p_inc(ch);
+ }
+
+ memset(&ins->c, 0, sizeof(ins->c));
+ }
+ //qbuf_dbg_check_in_buffer_id(2);
+}
+
+static int reg_idle_ch(void)
+{
+ unsigned int ch;
+ struct dim_itf_s *pintf;
+ int ret = -1;
+ //int i;
+ struct di_ch_s *pch;
+ struct di_mng_s *pbm = get_bufmng();
+
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+
+ pintf = &pch->itf;//get_dev_intf(ch);
+ mutex_lock(&pch->itf.lock_reg);
+
+ if ((pbm->tmode_pre[ch] == EDIM_TMODE_2_PW_OUT ||
+ pbm->tmode_pre[ch] == EDIM_TMODE_3_PW_LOCAL) &&
+ !pintf->reg) {
+ /*set reg flg*/
+ pintf->reg = true;
+ ret = (int)ch;
+ mutex_unlock(&pch->itf.lock_reg);
+ dbg_dbg("%s:ch[%d], ret[%d]\n", __func__, ch, ret);
+ break;
+ }
+ dbg_dbg("%s:ch[%d], tmode[%d], reg[%d]\n", __func__,
+ ch, pbm->tmode_pre[ch], pintf->reg);
+
+ mutex_unlock(&pch->itf.lock_reg);
+ }
+ dbg_dbg("%s:%d\n", __func__, ret);
+
+ return ret;
+}
+
+#define ERR_INDEX (0xffff)
+static unsigned int index_2_ch(int index)
+{
+ unsigned int ret;
+
+ if (index >= DI_CHANNEL_NUB || index < 0) {
+ PR_ERR("instance index is overflow:%d\n", index);
+ ret = ERR_INDEX;
+ } else {
+ ret = (unsigned int)index;
+ }
+
+ return ret;
+}
+
+void dim_dbg_buffer(struct di_buffer *buffer, unsigned int id)
+{
+ PR_INF("%s:%d:%px\n", __func__, id, buffer);
+ PR_INF("\t:code:0x%x,ch[%d],indx[%d], type[%d]\n",
+ buffer->mng.code, buffer->mng.ch,
+ buffer->mng.index, buffer->mng.type);
+ if (buffer->vf)
+ PR_INF("\t:vf:0x%px, 0x%x\n", buffer->vf, buffer->vf->index);
+ else
+ PR_INF("\t:%s\n", "no vf");
+}
+
+void dim_dbg_buffer2(struct di_buffer *buffer, unsigned int id)
+{
+ if (!buffer) {
+ dbg_nq("%s:%d:no buffer\n", __func__, id);
+ return;
+ }
+ dbg_nq("%s:%d:%px\n", __func__, id, buffer);
+ if (buffer->vf) {
+ dbg_nq("\t:0x%px, 0x%x,0x%x\n", buffer,
+ buffer->vf->canvas0_config[0].phy_addr,
+ buffer->vf->canvas0_config[1].phy_addr);
+ } else {
+ dbg_nq("\t:%s\n", "no vf");
+ }
+}
+
+static void cfg_ch_set(struct di_ch_s *pch)
+{
+ struct di_init_parm *parm;
+ unsigned int out_format;
+
+ parm = &pch->itf.u.dinst.parm;
+ out_format = parm->output_format & 0xffff;
+
+ switch (out_format) {
+ case DI_OUTPUT_422:
+ cfgsch(pch, POUT_FMT, 0);
+ cfgsch(pch, IOUT_FMT, 0);
+ break;
+ case DI_OUTPUT_NV12:
+ cfgsch(pch, POUT_FMT, 2);
+ cfgsch(pch, IOUT_FMT, 2);
+ break;
+ case DI_OUTPUT_NV21:
+ cfgsch(pch, POUT_FMT, 1);
+ cfgsch(pch, IOUT_FMT, 1);
+ break;
+ default:
+ PR_INF("%s:format not set\n", __func__);
+ break;
+ }
+
+ cfgsch(pch, KEEP_DEC_VF, 0); // for all new_interface
+ if (dip_itf_is_ins_exbuf(pch)) {
+ //cfgsch(pch, KEEP_DEC_VF, 0);
+ cfgsch(pch, ALLOC_SCT, 0);
+ cfgsch(pch, 4K, 0);
+ }
+
+ PR_INF("%s:ch[%d]\n",
+ __func__, pch->ch_id);
+ PR_INF("\tkeep_dec_vf[%d]\n", cfggch(pch, KEEP_DEC_VF));
+ PR_INF("\tout_fmt[%d][%d]\n", cfggch(pch, POUT_FMT),
+ cfggch(pch, IOUT_FMT));
+ PR_INF("\talloc_sct[%d],4K[%d]\n", cfggch(pch, ALLOC_SCT),
+ cfggch(pch, 4K));
+ PR_INF("\ttvp:%d\n",
+ parm->output_format & DI_OUTPUT_TVP ? 1 : 0);
+}
+
+/**********************************************************
+ * @brief di_create_instance creat di instance
+ * @param[in] parm Pointer of parm structure
+ * @return di index for success, or fail type if < 0
+ **********************************************************/
+int di_create_instance(struct di_init_parm parm)
+{
+ int ret;
+ unsigned int ch;
+ struct di_ch_s *pch;
+ struct dim_itf_s *itf;
+
+ PR_INF("%s:", __func__);
+ ret = reg_idle_ch();
+ if (ret < 0) {
+ PR_ERR("%s:no idle ch\n", __func__);
+ return DI_ERR_REG_NO_IDLE_CH;
+ }
+
+ if ((parm.output_format & 0xffff) == DI_OUTPUT_422)
+ parm.output_format &= ~DI_OUTPUT_LINEAR;
+
+ ch = (unsigned int)ret;
+ pch = get_chdata(ch);
+ itf = &pch->itf;
+ itf->etype = EDIM_NIN_TYPE_INS;
+ /*parm*/
+ memcpy(&itf->u.dinst.parm, &parm, sizeof(struct di_init_parm));
+
+ itf->tmode = EDIM_TMODE_2_PW_OUT;
+ if (itf->u.dinst.parm.work_mode == WORK_MODE_PRE_POST) {
+ switch (itf->u.dinst.parm.buffer_mode) {
+ case BUFFER_MODE_ALLOC_BUF:
+ itf->tmode = EDIM_TMODE_3_PW_LOCAL;
+ break;
+ case BUFFER_MODE_USE_BUF:
+ itf->tmode = EDIM_TMODE_2_PW_OUT;
+ break;
+ default:
+ PR_ERR("%s:bmode[%d]\n", __func__,
+ itf->u.dinst.parm.buffer_mode);
+ break;
+ }
+ } else {
+ PR_ERR("%s:wmode[%d]\n", __func__,
+ itf->u.dinst.parm.work_mode);
+ }
+
+ //option:
+ #ifdef MARK_HIS//ary 2020-12-10 tmp
+ /*ops in*/
+ memcpy(&pintf->opsi, &inst_in_ops, sizeof(struct dim_itf_ops_s));
+ pintf->op_dvfm_fill = dvfm_fill_in_ins;
+ if (pintf->tmode == EDIM_TMODE_2_PW_OUT) {
+ pintf->op_post_done = dim_post_de_done_buf_config_ins;
+ pintf->op_ins_2_doing = ins_2_doing;
+ } else if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL) {
+ pintf->op_post_done = dim_post_de_done_buf_config_ins_local;
+ pintf->op_ins_2_doing = NULL;
+ } else {
+ pintf->op_ins_2_doing = NULL;
+ }
+ #endif
+ //reg:
+ mutex_lock(&pch->itf.lock_reg);
+ pch->sum_reg_cnt++;
+ dim_api_reg(DIME_REG_MODE_NEW, pch);
+ npst_reset(pch);
+ pch->itf.opins_m_back_in = nins_m_recycle_ins;
+ pch->itf.op_m_unreg = nins_m_unreg_new;
+ if (itf->tmode == EDIM_TMODE_3_PW_LOCAL) {
+ itf->op_fill_ready = ndis_fill_ready;
+ itf->op_ready_out = dip_itf_ndrd_ins_m2_out;
+ } else {
+ itf->op_fill_ready = ndrd_m1_fill_ready;
+ itf->op_ready_out = dip_itf_ndrd_ins_m1_out;
+ }
+
+ cfg_ch_set(pch);
+ mutex_unlock(&pch->itf.lock_reg);
+ PR_INF("%s:ch[%d],tmode[%d]\n", __func__, ch, itf->tmode);
+ PR_INF("\tout:%d\n", itf->u.dinst.parm.output_format);
+ return ch;
+}
+EXPORT_SYMBOL(di_create_instance);
+
+/**********************************************************
+ **
+ * @brief di_set_parameter set parameter to di for init
+ *
+ * @param[in] index instance index
+ *
+ * @return 0 for success, or fail type if < 0
+ *
+ **********************************************************/
+int di_destroy_instance(int index)
+{
+ struct dim_itf_s *pintf;
+ unsigned int ch;
+ struct di_ch_s *pch;
+
+ PR_INF("%s:\n", __func__);
+ ch = index_2_ch(index);
+ if (ch == ERR_INDEX) {
+ PR_ERR("%s:index overflow\n", __func__);
+ return DI_ERR_INDEX_OVERFLOW;
+ }
+
+ pch = get_chdata(ch);
+
+ pintf = &pch->itf;
+ mutex_lock(&pch->itf.lock_reg);
+ if (!pintf->reg) {
+ PR_WARN("%s:double unreg\n", __func__);
+ mutex_unlock(&pch->itf.lock_reg);
+ return 0;
+ }
+
+ pintf->reg = 0;
+ //dip_event_unreg_chst(ch);
+ dim_trig_unreg(ch);
+ dim_api_unreg(DIME_REG_MODE_NEW, pch);
+ mutex_unlock(&pch->itf.lock_reg);
+ PR_INF("%s:end\n", __func__);
+ return 0;
+}
+EXPORT_SYMBOL(di_destroy_instance);
+
+/**********************************************************
+ **
+ * @brief di_empty_input_buffer send input date to di
+ *
+ * @param[in] index instance index
+ * @param[in] buffer Pointer of buffer structure
+ *
+ * @return Success or fail type
+ **********************************************************/
+enum DI_ERRORTYPE di_empty_input_buffer(int index, struct di_buffer *buffer)
+{
+ struct dim_itf_s *pintf;
+ unsigned int ch;
+ struct di_ch_s *pch;
+// unsigned int buf_index = 0xff;
+ //2020-12-10:
+ unsigned int free_nub;
+ struct buf_que_s *pbufq;
+ struct dim_nins_s *pins;
+ bool flg_q;
+// unsigned int err;
+
+ ch = index_2_ch(index);
+ if (ch == ERR_INDEX) {
+ PR_ERR("%s:index overflow\n", __func__);
+ return DI_ERR_INDEX_OVERFLOW;
+ }
+ pch = get_chdata(ch);
+ pintf = &pch->itf;
+ if (!pintf->reg) {
+ PR_WARN("%s:ch[%d] not reg\n", __func__, ch);
+ return DI_ERR_INDEX_NOT_ACTIVE;
+ }
+
+ #ifdef MARK_HIS
+ qued_ops.peek(pch, QUED_T_IS_FREE, &buf_index);
+ if (buf_index == 0xff) {
+ PR_ERR("%s:no free\n", __func__);
+ return DI_ERR_IN_NO_SPACE;
+ }
+ qued_ops.out(pch, QUED_T_IS_FREE, &buf_index);
+ pintf->u.dinst.in[buf_index] = buffer;
+ qued_ops.in(pch, QUED_T_IS_IN, buf_index);
+ #endif
+
+ //2020-12-10:
+ pbufq = &pch->nin_qb;
+ free_nub = qbufp_count(pbufq, QBF_NINS_Q_IDLE);
+ if (!free_nub) {
+ PR_WARN("%s:no nins idle\n", __func__);
+ return DI_ERR_IN_NO_SPACE;
+ }
+
+ /* get ins */
+ flg_q = qbuf_out(pbufq, QBF_NINS_Q_IDLE, &index);
+ if (!flg_q) {
+ PR_ERR("%s:qout\n", __func__);
+ return DI_ERR_IN_NO_SPACE;
+ }
+ pins = (struct dim_nins_s *)pbufq->pbuf[index].qbc;
+ pins->c.ori = buffer;
+ //pins->c.etype = EDIM_NIN_TYPE_VFM;
+ if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
+ dim_dbg_buffer2(buffer, 0);
+
+ if (buffer->flag & DI_FLAG_EOS) {
+ pins->c.vfm_cp.type |= VIDTYPE_V4L_EOS;
+ PR_INF("%s:eos\n", __func__);
+ } else {
+ /* @ary_note: eos may be no vf */
+ memcpy(&pins->c.vfm_cp, buffer->vf, sizeof(pins->c.vfm_cp));
+ }
+
+ flg_q = qbuf_in(pbufq, QBF_NINS_Q_CHECK, index);
+ sum_g_inc(ch);
+ if (!flg_q) {
+ PR_ERR("%s:qin check\n", __func__);
+ qbuf_in(pbufq, QBF_NINS_Q_IDLE, index);
+ }
+ //dbg_itf_tmode(pch,1);
+ task_send_ready();
+ return DI_ERR_NONE;
+}
+EXPORT_SYMBOL(di_empty_input_buffer);
+
+//@ary_note mem alloc by outside
+static enum DI_ERRORTYPE di_fill_output_buffer_mode2(struct di_ch_s *pch,
+ struct di_buffer *buffer)
+{
+ //bool ret;
+
+ #ifdef MARK_HIS //@ary_note todo
+ /*from QUED_T_IS_PST_FREE to QUED_T_IS_PST_DOBEF */
+ struct di_ch_s *pch;
+ unsigned int buf_index = 0xff;
+ struct dim_itf_s *pintf;
+
+ pch = get_chdata(pintf->ch);
+ #ifdef MARK_HIS
+ /*que IS_PST*/
+ if (!qued_ops.move(pch,
+ QUED_T_IS_PST_FREE,
+ QUED_T_IS_PST_DOBEF, &buf_index)) {
+ PR_WARN("%s:ch[%d]:no space for 0x%p\n", __func__, ch, buffer);
+ return DI_ERR_IN_NO_SPACE;
+ }
+
+ pintf->u.dinst.out[buf_index] = buffer;
+ #else
+ qued_ops.peek(pch, QUED_T_IS_PST_FREE, &buf_index);
+ if (buf_index == 0xff) {
+ PR_ERR("%s: NO PST_FREE\n", __func__);
+ return DI_ERR_IN_NO_SPACE;
+ }
+ qued_ops.out(pch, QUED_T_IS_PST_FREE, &buf_index);
+ pintf->u.dinst.out[buf_index] = buffer;
+ qued_ops.in(pch, QUED_T_IS_PST_DOBEF, buf_index);
+
+ #endif
+ #endif //@ary_note todo
+ if (dip_itf_is_ins(pch) && dim_dbg_new_int(2))
+ dim_dbg_buffer2(buffer, 1);
+ npst_qin(pch, buffer);
+
+ pch->sum_ext_buf_in2++;
+ return DI_ERR_NONE;
+}
+
+/* @ary_note: buffer alloc by di */
+/* @ary_note: use this api to put back display buffer */
+/* @ary_note: same as vfm put */
+static enum DI_ERRORTYPE di_fill_output_buffer_mode3(struct di_ch_s *pch,
+ struct di_buffer *buffer)
+{
+ /*back buf to di */
+ struct dim_itf_s *pintf;
+// unsigned int buf_index = 0xff;
+ //struct di_buf_s *di_buf = NULL;
+//tmp ulong irq_flag2 = 0;
+ unsigned int ch;
+ struct dim_ndis_s *ndis1;
+
+ //pch = get_chdata(ch);
+ ch = pch->ch_id;
+ pintf = &pch->itf;
+
+ sum_pst_p_inc(ch);
+ ndis1 = (struct dim_ndis_s *)buffer->private_data;
+ if (IS_ERR_OR_NULL(pintf)) {
+ /* bypass */
+ PR_WARN("%s:bypass?\n", __func__);
+ pintf->u.dinst.parm.ops.empty_input_done(buffer);
+ sum_p_inc(ch);//
+ return DI_ERR_NONE;
+ }
+
+ task_send_cmd2(ch,
+ LCMD2(ECMD_RL_KEEP,
+ ch,
+ ndis1->header.index));
+ //task_send_ready();
+ return DI_ERR_NONE;
+}
+
+/**********************************************************
+ * @brief di_fill_output_buffer send output buffer to di
+ *
+ * @param[in] index instance index
+ * @param[in] buffer Pointer of buffer structure
+ *
+ * @return Success or fail type
+ *********************************************************/
+enum DI_ERRORTYPE di_fill_output_buffer(int index, struct di_buffer *buffer)
+{
+ struct dim_itf_s *pintf;
+ unsigned int ch;
+ struct di_ch_s *pch;
+ enum DI_ERRORTYPE ret = DI_ERR_NONE;
+
+ /*check channel*/
+ ch = index_2_ch(index);
+ if (ch == ERR_INDEX) {
+ PR_ERR("%s:index overflow\n", __func__);
+ return DI_ERR_INDEX_OVERFLOW;
+ }
+ pch = get_chdata(ch);
+ pintf = &pch->itf;
+ dim_print("%s:ch[%d],ptf ch[%d]\n", __func__, ch, pintf->ch);
+ if (!pintf->reg) {
+ PR_WARN("%s:ch[%d] not reg\n", __func__, ch);
+ return DI_ERR_INDEX_NOT_ACTIVE;
+ }
+
+ if (pintf->tmode == EDIM_TMODE_2_PW_OUT)
+ ret = di_fill_output_buffer_mode2(pch, buffer);
+ else if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL)
+ ret = di_fill_output_buffer_mode3(pch, buffer);
+ task_send_ready();
+ return ret;
+}
+EXPORT_SYMBOL(di_fill_output_buffer);
+
+int di_release_keep_buf(struct di_buffer *buffer)
+{
+ /*back buf to di */
+// struct dim_itf_s *pintf;
+ struct di_ch_s *pch;
+ unsigned int ch;
+ struct dim_ndis_s *ndis1;
+
+ if (!buffer || !buffer->private_data) {
+ PR_INF("%s:no di data\n", __func__);
+ return -1;
+ }
+ ndis1 = (struct dim_ndis_s *)buffer->private_data;
+
+ ch = buffer->mng.ch;
+ pch = get_chdata(ch);
+
+ sum_pst_p_inc(ch);
+
+ task_send_cmd2(ch,
+ LCMD2(ECMD_RL_KEEP,
+ ch,
+ ndis1->header.index));
+ return 0;
+}
+EXPORT_SYMBOL(di_release_keep_buf);
+
+/**********************************************************
+ * @brief di_get_buffer_num get output buffer num
+ *
+ * @param[in] index instance index
+ * @param[in] buffer Pointer of buffer structure
+ *
+ * @return number or fail type
+ *********************************************************/
+int di_get_buffer_num(int index)
+{
+ struct dim_itf_s *pintf;
+ unsigned int ch = 0;
+ struct di_ch_s *pch;
+ int ret = -1;
+
+ PR_INF("%s:\n", __func__);
+ ch = index_2_ch(index);
+ if (ch == ERR_INDEX) {
+ PR_ERR("%s:index overflow\n", __func__);
+ return DI_ERR_INDEX_OVERFLOW;
+ }
+
+ pch = get_chdata(ch);
+ pintf = &pch->itf;
+ if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL)
+ ret = DIM_NDIS_NUB;
+ PR_INF("%s:end\n", __func__);
+ return ret;
+}
+EXPORT_SYMBOL(di_get_buffer_num);
+
--- /dev/null
+/*
+ * drivers/amlogic/media/di_multi/di_mem_scatter.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/semaphore.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/major.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+#include <linux/proc_fs.h>
+#include <linux/list.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/of_irq.h>
+#include <linux/uaccess.h>
+#include <linux/of_fdt.h>
+#include <linux/cma.h>
+#include <linux/dma-contiguous.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/of_device.h>
+
+#include <linux/amlogic/media/vfm/vframe.h>
+
+/*dma_get_cma_size_int_byte*/
+#include <linux/amlogic/media/codec_mm/codec_mm.h>
+#include <linux/amlogic/media/codec_mm/codec_mm_keeper.h>
+
+#include "deinterlace_dbg.h"
+#include "deinterlace.h"
+#include "di_data_l.h"
+#include "di_data.h"
+#include "di_dbg.h"
+#include "di_vframe.h"
+#include "di_task.h"
+#include "di_prc.h"
+#include "di_sys.h"
+#include "di_api.h"
+#include "di_que.h"
+//#include "sc2/di_hw_ex_v3.h"
+
+#include "register.h"
+#include "di_mem_sct_def.h"
+
+/************************************
+ * bit0: no tail
+ * bit1: some information for each frame
+ * bit2: clear for first
+ * bit3: clear for each frame
+ * bit4: used decoder buffer;
+ * bit5: to sum;
+ ************************************/
+
+static u32 dbg_sct_cfg = DI_BIT5 | DI_BIT6;// = BITS_EAFBC_CFG_4K;
+
+module_param_named(dbg_sct_cfg, dbg_sct_cfg, uint, 0664);
+
+bool dbg_sct_used_decoder_buffer(void)
+{
+ if (dbg_sct_cfg & DI_BIT4)
+ return true;
+ return false;
+}
+
+bool dbg_sct_printa(void)
+{
+ if (dbg_sct_cfg & DI_BIT1)
+ return true;
+ return false;
+}
+
+static bool dbg_sct_clear_first(void)
+{
+ if (dbg_sct_cfg & DI_BIT2)
+ return true;
+ return false;
+}
+
+bool dbg_sct_clear_by_frame(void)
+{
+ if (dbg_sct_cfg & DI_BIT3)
+ return true;
+ return false;
+}
+
+static bool dbg_sct_sum(void)
+{
+ if (dbg_sct_cfg & DI_BIT5)
+ return true;
+ return false;
+}
+
+static bool dbg_limit_ready(void)
+{
+ if (dbg_sct_cfg & DI_BIT6)
+ return true;
+ return false;
+}
+
+struct dim_msct_s {
+ void *box;
+ unsigned int flg_err;
+ unsigned int max_nub;
+ /*test*/
+ unsigned int cnt_alloc;
+ struct dim_pat_s *pat_buf;
+ unsigned long tab_addr;
+ unsigned int *tab_vaddr;
+ union {
+ unsigned int d32;
+ struct {
+ unsigned int box : 1,
+ pat : 1,
+ vbit : 1, /*vmap flg*/
+ tab : 1,
+ tab_resize : 1,
+ flg_rev :27;
+ } b;
+ } flg_act;
+};
+
+static struct dim_msct_s dim_sct;
+
+static struct dim_msct_s *get_msct(void)
+{
+ return &dim_sct;
+}
+
+static void sct_alloc(struct di_ch_s *pch,
+ unsigned int buffer_size,
+ unsigned int idx)
+{
+ int ret;
+ struct dim_msct_s *psct = get_msct();
+ int cur_mmu_4k_number;
+ //unsigned int *vaddr;
+ //struct di_mm_s *mm;
+ //bool flg_vmap;
+ u64 timer_st, timer_end, diff;
+
+ timer_st = cur_to_usecs();
+
+ cur_mmu_4k_number = ((buffer_size + (1 << 12) - 1) >> 12);
+
+ ret = di_mmu_box_alloc_idx(
+ psct->box,
+ idx,
+ cur_mmu_4k_number,
+ psct->tab_vaddr);
+ if (ret == 0) {
+ psct->flg_act.b.tab = 1;
+ psct->flg_act.b.tab_resize = 0;
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_ALLOC);
+ PR_ERR("%s:\n", __func__);
+ }
+
+ timer_end = cur_to_usecs();
+ diff = timer_end - timer_st;
+ dbg_sct("%s:use %uus\n", __func__, (unsigned int)diff);
+ dim_tr_ops.sct_alloc(idx, timer_st);
+}
+
+static void sct_free_tail(struct di_ch_s *pch,
+ unsigned int buffer_used,
+ unsigned int idx)
+
+{
+ struct dim_msct_s *psct = get_msct();
+ int ret;
+ u64 timer_st, timer_end, diff;
+
+ timer_st = cur_to_usecs();
+ ret = di_mmu_box_free_idx_tail(
+ psct->box,
+ idx,
+ buffer_used);
+ if (ret == 0) {
+ psct->flg_act.b.tab_resize = 1;
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_RESIZE);
+ PR_ERR("%s:\n", __func__);
+ }
+ timer_end = cur_to_usecs();
+ diff = timer_end - timer_st;
+ dbg_sct("%s:use %uus\n", __func__, (unsigned int)diff);
+}
+
+static void sct_free(unsigned int idx)
+{
+ int ret;
+ struct dim_msct_s *psct = get_msct();
+ u64 timer_st, timer_end, diff;
+
+ timer_st = cur_to_usecs();
+
+ ret = di_mmu_box_free_idx(psct->box, idx);
+ if (ret == 0) {
+ psct->flg_act.b.tab_resize = 0;
+ psct->flg_act.b.tab = 0;
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_FREE);
+ PR_ERR("%s:\n", __func__);
+ }
+
+ timer_end = cur_to_usecs();
+ diff = timer_end - timer_st;
+ dbg_sct("%s:use %uus\n", __func__, (unsigned int)diff);
+}
+
+static void sct_reg(struct di_ch_s *pch)
+{
+ unsigned int ch;
+ struct dim_msct_s *psct = get_msct();
+ int buf_size = 64; /*?*/
+ unsigned int max_num;
+ bool tvp;
+ struct dim_pat_s *pat_buf;
+ struct div2_mm_s *mm;
+ bool flg_vmap = false;
+
+ ch = pch->ch_id;
+ max_num = 2;
+ psct->max_nub = max_num;
+ tvp = 0;
+ psct->box = di_mmu_box_alloc_box(DEVICE_NAME,
+ ch,
+ max_num,
+ buf_size * SZ_1M,
+ tvp);
+ if (!psct->box) {
+ bset(&psct->flg_err, EDIM_SCT_ERR_BOX);
+ PR_ERR("%s\n", __func__);
+ return;
+ }
+ pat_buf = qpat_out_ready(pch);
+ if (!pat_buf) {
+ bset(&psct->flg_err, EDIM_SCT_ERR_PAT);
+ di_mmu_box_free(psct->box);
+ psct->box = NULL;
+ return;
+ }
+ /*vmap*/
+ mm = dim_mm_get(ch);
+ psct->tab_vaddr = (unsigned int *)dim_vmap(psct->tab_addr,
+ mm->cfg.size_pafbct_one,
+ &flg_vmap);
+ if (!psct->tab_vaddr) {
+ bset(&psct->flg_err, EDIM_SCT_ERR_VMAP);
+ PR_ERR("%s:vmap:0x%lx\n", __func__, psct->tab_addr);
+ return;
+ }
+ psct->flg_act.b.vbit = flg_vmap;
+
+ psct->tab_addr = pat_buf->mem_start;
+ psct->pat_buf = pat_buf;
+
+ psct->flg_act.b.box = 1;
+ psct->flg_act.b.pat = 1;
+}
+
+static void sct_unreg(struct di_ch_s *pch)
+{
+ struct dim_msct_s *psct = get_msct();
+
+ /**/
+ if (psct->flg_act.b.tab)
+ sct_free(0);
+
+ /* vmap */
+ if (psct->flg_act.b.vbit) {
+ dim_unmap_phyaddr((u8 *)psct->tab_vaddr);
+ psct->tab_vaddr = NULL;
+ }
+
+ if (psct->flg_act.b.pat) {
+ qpat_in_ready(pch, psct->pat_buf);
+ psct->pat_buf = NULL;
+ psct->flg_act.b.pat = 0;
+ }
+
+ if (psct->flg_act.b.box) {
+ di_mmu_box_free(psct->box);
+ psct->box = NULL;
+ psct->flg_act.b.box = 0;
+ }
+ PR_INF("%s:end\n", __func__);
+}
+
+void tst_alloc(struct di_ch_s *pch)
+{
+ struct dim_msct_s *psct = get_msct();
+ struct div2_mm_s *mm;
+ unsigned int ch;
+
+ ch = pch->ch_id;
+ mm = dim_mm_get(ch);
+
+ if (psct->flg_err) {
+ dbg_sct("%s:0x%x\n", __func__, psct->flg_err);
+ return;
+ }
+ if (psct->flg_act.b.tab)
+ return;
+ sct_alloc(pch, mm->cfg.pst_buf_size, 0);
+}
+
+void tst_resize(struct di_ch_s *pch, unsigned int used_size)
+{
+ struct dim_msct_s *psct = get_msct();
+ struct div2_mm_s *mm;
+ unsigned int ch;
+
+ ch = pch->ch_id;
+ mm = dim_mm_get(ch);
+
+ if (psct->flg_err) {
+ dbg_sct("%s:0x%x\n", __func__, psct->flg_err);
+ return;
+ }
+
+ if ((!psct->flg_act.b.tab) || (psct->flg_act.b.tab_resize))
+ return;
+ sct_free_tail(pch, used_size, 0);
+}
+
+void tst_release(struct di_ch_s *pch)
+{
+ struct dim_msct_s *psct = get_msct();
+
+ if (psct->flg_err) {
+ dbg_sct("%s:0x%x\n", __func__, psct->flg_err);
+ return;
+ }
+
+ if (!psct->flg_act.b.tab)
+ return;
+ if (!psct->flg_act.b.tab_resize)
+ return;
+
+ sct_free(0);
+}
+
+void tst_unreg(struct di_ch_s *pch)
+{
+ sct_unreg(pch);
+}
+
+void tst_reg(struct di_ch_s *pch)
+{
+// struct dim_msct_s *psct = get_msct();
+ sct_reg(pch);
+}
+
+void sct_max_check(struct di_ch_s *pch)
+{
+ unsigned int ch;
+ struct dim_mscttop_s *psct;
+ struct dim_msc_sum_s *psum;
+ //unsigned int i;
+ //struct qs_cls_s *p;
+ //unsigned int psize;
+ //unsigned int cnt_pst_ready, cnt_pst_dis, cnt_pst_back;
+ //unsigned int cnt_sct_ready, cnt_sct_used,cnt_sct_re;
+ struct buf_que_s *pbufq;
+ //struct dim_sct_s *sct;
+ //unsigned int tt_size;
+
+ if (!dbg_sct_sum())
+ return;
+
+ ch = pch->ch_id;
+ psct = &pch->msct_top;
+ psum = &psct->sum;
+ if (!psct->box)
+ return;
+
+ pbufq = &pch->sct_qb;
+ psum->mts_sct_rcc = qbufp_count(pbufq, QBF_SCT_Q_RECYCLE);
+ psum->mts_sct_used = qbufp_count(pbufq, QBF_SCT_Q_USED);
+ psum->mts_sct_ready = qbufp_count(pbufq, QBF_SCT_Q_READY);
+
+ psum->mts_pst_free = di_que_list_count(ch, QUE_POST_FREE);
+ psum->mts_pst_ready = ndrd_cnt(pch);
+ //di_que_list_count(ch, QUE_POST_READY);
+ psum->mts_pst_ready = di_que_list_count(ch, QUE_POST_READY);
+ psum->mts_pst_back = di_que_list_count(ch, QUE_POST_BACK);
+ psum->mts_pst_dispaly = list_count(ch, QUEUE_DISPLAY);
+}
+
+/*because sct is not sync with reg/unreg */
+void sct_sw_on(struct di_ch_s *pch,
+ unsigned int max_num,
+ bool tvp,
+ unsigned int buffer_size)
+{
+ unsigned int ch;
+ struct dim_mscttop_s *psct;
+ int buf_size = 64; /*?*/
+
+// struct dim_pat_s *pat_buf;
+// struct di_mm_s *mm;
+// bool flg_vmap = false;
+
+ ch = pch->ch_id;
+ psct = &pch->msct_top;
+ if (psct->box) {
+ PR_WARN("%s:box is exist\n", __func__);
+ return;
+ }
+ /*int*/
+ memset(&psct->sum, 0, sizeof(psct->sum));
+
+ psct->max_nub = max_num;
+
+ psct->box = di_mmu_box_alloc_box(DEVICE_NAME,
+ ch,
+ max_num,
+ buf_size * SZ_1M,
+ tvp);
+ if (!psct->box) {
+ bset(&psct->flg_err, EDIM_SCT_ERR_BOX);
+ PR_ERR("%s\n", __func__);
+ return;
+ }
+ psct->buffer_size = buffer_size;
+ psct->buffer_size_nub = ((psct->buffer_size + (1 << 12) - 1) >> 12);
+ psct->flg_act_box = 1;
+
+ dbg_sct("%s:ch[%d], nub[%d] tvp[%d], buf_size[0x%x]\n",
+ __func__, ch, max_num, tvp, buffer_size);
+}
+
+void sct_sw_off(struct di_ch_s *pch)
+{
+ unsigned int ch;
+ struct dim_mscttop_s *psct;
+ struct buf_que_s *pbufq;
+ //union q_buf_u q_buf;// = NULL;
+ struct dim_sct_s *sct;
+ int i;
+ unsigned int len;
+ bool ret;
+
+ ch = pch->ch_id;
+ psct = &pch->msct_top;
+ if (!psct->box) {
+ PR_INF("%s:no box\n", __func__);
+ return;
+ }
+
+ pbufq = &pch->sct_qb;
+ /* ready clear */
+ len = qbufp_count(pbufq, QBF_SCT_Q_READY);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qsct_any_to_recycle(pch, QBF_SCT_Q_READY, &sct);
+ if (!ret) {
+ PR_ERR("%s:used[%d][%d]\n", __func__, len, i);
+ break;
+ }
+ }
+ }
+ /* used clear */
+ len = qbufp_count(pbufq, QBF_SCT_Q_USED);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qsct_any_to_recycle(pch, QBF_SCT_Q_USED, &sct);
+ if (!ret) {
+ PR_ERR("%s:used[%d][%d]\n", __func__, len, i);
+ break;
+ }
+ }
+ }
+ /* recycle clear */
+ len = qbufp_count(pbufq, QBF_SCT_Q_RECYCLE);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qsct_recycle_to_idle(pch, &sct);
+ if (!ret) {
+ PR_ERR("%s:rcy[%d][%d]\n", __func__, len, i);
+ break;
+ }
+// if (!sct->flg_act.b.tab_keep)
+ /* pat */
+// pat_release_vaddr(sct->pat_buf);
+// qpat_in_ready(pch,sct->pat_buf);
+// sct->pat_buf = NULL;
+ sct_free_l(pch, sct);
+ }
+ }
+ bufq_sct_rest(pch);
+
+ di_mmu_box_free(psct->box);
+ psct->box = NULL;
+ psct->flg_act_box = 0;
+ psct->max_nub = 0;
+ PR_INF("%s:release\n", __func__);
+}
+
+//static
+unsigned int sct_cnt_crc(struct device *dev,
+ unsigned int *p,
+ unsigned int buf_size)
+{
+ //bool flg = false; /*dbg*/
+
+ int i, cnt;
+// unsigned int body;
+ unsigned int crc = 0;
+ unsigned long crc_tmp = 0;
+
+ cnt = (buf_size + 0xfff) >> 12;
+
+ for (i = 0; i < cnt; i++) {
+ crc_tmp += *(p + i);
+ /*debug*/
+ if ((dbg_sct_cfg & DI_BIT8) && (i < 5))
+ PR_INF("\t:0x%x\n", *(p + i));
+ }
+ //PR_INF("%s:3\n", __func__);
+ crc = (unsigned int)crc_tmp;
+ if (dbg_sct_cfg & DI_BIT8)
+ PR_INF("%s:0x%px:crc:0x%x, cnt[0x%x]\n", __func__, p, crc, cnt);
+
+ return crc;
+}
+
+static void sct_alloc_l(struct di_ch_s *pch,
+ struct dim_sct_s *sct)
+{
+ int ret;
+ struct dim_mscttop_s *psct;
+ int cur_mmu_4k_number;
+ //unsigned int *vaddr;
+ //struct di_mm_s *mm;
+ //bool flg_vmap;
+ u64 timer_st, timer_end, diff;
+ struct dim_msc_sum_s *psum;
+
+ psct = &pch->msct_top;
+ psum = &psct->sum;
+ timer_st = cur_to_usecs();
+
+ cur_mmu_4k_number = psct->buffer_size_nub;
+ //((psct->buffer_size + (1 << 12) - 1) >> 12);
+
+ ret = di_mmu_box_alloc_idx(
+ psct->box,
+ sct->header.index,
+ cur_mmu_4k_number,
+ sct->pat_buf->vaddr);
+ if (ret == 0) {
+ sct->flg_act.b.tab = 1;
+ sct->tail_cnt = cur_mmu_4k_number;
+ /* sum */
+ psum->curr_nub++;
+ if (psum->curr_nub > psum->max_nub)
+ psum->max_nub = psum->curr_nub;
+ psum->curr_tt_size += cur_mmu_4k_number;
+ if (psum->max_tt_size2 < psum->curr_tt_size) {
+ psum->max_tt_size2 = psum->curr_tt_size;
+ sct_max_check(pch);
+ }
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_ALLOC);
+ PR_ERR("%s:\n", __func__);
+ }
+ #ifdef HIS_CODE
+ sct->pat_buf->crc = sct_cnt_crc(NULL,
+ (unsigned int *)sct->pat_buf->vaddr,
+ psct->buffer_size);
+ #endif
+ timer_end = cur_to_usecs();
+ diff = timer_end - timer_st;
+ #ifdef HIS_CODE
+ dbg_sct("%s:pat:[idx=%d]:addr=0x%lx, vaddr=0x%px\n",
+ __func__,
+ sct->pat_buf->header.index,
+ sct->pat_buf->mem_start,
+ sct->pat_buf->vaddr);
+ dbg_sct("%s:use %uus\n", __func__, (unsigned int)diff);
+ #endif
+ dim_tr_ops.sct_alloc(sct->header.index, timer_st);
+}
+
+void sct_free_tail_l(struct di_ch_s *pch,
+ unsigned int buffer_used,
+ struct dim_sct_s *sct)
+
+{
+ struct dim_mscttop_s *psct;
+ int ret;
+ u64 timer_st, timer_end, diff;
+ struct dim_msc_sum_s *psum;
+
+ if ((!sct) || (!pch)) {
+ PR_ERR("%s:no sct\n", __func__);
+ return;
+ }
+
+ if (dbg_sct_cfg & DI_BIT0)
+ return;
+
+ timer_st = cur_to_usecs();
+ psct = &pch->msct_top;
+ psum = &psct->sum;
+ buffer_used += 3;
+ if (buffer_used > psct->buffer_size_nub) {
+ PR_ERR("%s:overflow:0x%x\n", __func__, buffer_used);
+ return;
+ }
+ ret = di_mmu_box_free_idx_tail(
+ psct->box,
+ sct->header.index,
+ buffer_used);
+ if (ret == 0) {
+ sct->flg_act.b.tab_resize = 1;
+ /*sum*/
+ //psum->max_nub--;
+ psum->curr_tt_size -= (psct->buffer_size_nub - buffer_used);
+ if (buffer_used > psum->max_size)
+ psum->max_size = buffer_used;
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_RESIZE);
+ PR_ERR("%s:\n", __func__);
+ }
+ sct->tail_cnt = buffer_used;
+ timer_end = cur_to_usecs();
+ diff = timer_end - timer_st;
+ dim_tr_ops.sct_tail(sct->header.index, buffer_used);
+ //dbg_sct("%s:use %uus 0x%x\n", __func__,
+ //(unsigned int)diff, buffer_used);
+}
+
+void sct_free_l(struct di_ch_s *pch, struct dim_sct_s *sct)
+{
+ int ret;
+ struct dim_mscttop_s *psct;
+ //u64 timer_st, timer_end, diff;
+ struct dim_msc_sum_s *psum;
+
+ if ((!pch) || (!sct))
+ return;
+ psct = &pch->msct_top;
+ psum = &psct->sum;
+ //timer_st = cur_to_usecs();
+ if (sct->header.index > psct->max_nub) {
+ PR_ERR("%s:sct[%d]\n", __func__, sct->header.index);
+ return;
+ }
+ ret = di_mmu_box_free_idx(psct->box, sct->header.index);
+ if (ret == 0) {
+ sct->flg_act.b.tab_resize = 0;
+ sct->flg_act.b.tab = 0;
+
+ psum->curr_nub--;
+ psum->curr_tt_size -= sct->tail_cnt;
+ } else {
+ bset(&psct->flg_err, EDIM_SCT_ERR_FREE);
+ PR_ERR("%s:\n", __func__);
+ }
+
+ //timer_end = cur_to_usecs();
+ //diff = timer_end - timer_st;
+ #ifdef HIS_CODE
+ dbg_sct("%s:ch[%d], index[%d]\n",
+ __func__,
+ pch->ch_id,
+ sct->header.index);
+ dbg_sct("%s:use %uus\n", __func__, (unsigned int)diff);
+ #endif
+}
+
+unsigned int sct_keep(struct di_ch_s *pch, struct dim_sct_s *sct)
+{
+ struct dim_mscttop_s *psct;
+ void *mem_handle;
+ int ret;
+
+ if ((!pch) || (!sct))
+ return 0xff;
+ psct = &pch->msct_top;
+
+ mem_handle =
+ di_mmu_box_get_mem_handle(
+ psct->box, sct->header.index);
+ ret = codec_mm_keeper_mask_keep_mem(mem_handle,
+ MEM_TYPE_CODEC_MM_SCATTER);
+ #ifdef HIS_CODE
+ vf->mem_head_handle =
+ decoder_bmmu_box_get_mem_handle(
+ hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
+ #endif
+ if (ret >= 0)
+ return ret;
+ return 0xff;
+}
+
+void sct_alloc_in_poling(unsigned int ch)
+{
+ struct di_ch_s *pch;
+ struct dim_mscttop_s *psct;
+ unsigned int cnt_sct_req;
+ struct buf_que_s *pbufq;
+ int i;
+ struct dim_sct_s *sct, *sct2;
+ //struct dim_pat_s *pat_buf = NULL;
+
+ pch = get_chdata(ch);
+ if (!pch)
+ return;
+ psct = &pch->msct_top;
+ if (!psct->box)
+ return;
+ pbufq = &pch->sct_qb;
+ cnt_sct_req = qbufp_count(pbufq, QBF_SCT_Q_REQ);
+
+ if (!cnt_sct_req)
+ return;
+ psct->flg_allocing = 1;
+ for (i = 0; i < cnt_sct_req; i++) {
+ /* peek */
+
+ mutex_lock(&psct->lock_ready);
+ sct = qsct_req_peek(pch);
+ mutex_unlock(&psct->lock_ready);
+ if (!sct)
+ break;
+
+ /* alloc */
+ sct_alloc_l(pch, sct);
+
+ /* req to ready */
+ mutex_lock(&psct->lock_ready);
+ if (sct->flg_act.b.tab) {
+ qsct_req_to_ready(pch, &sct2);
+ if (sct != sct2)
+ PR_ERR("%s:not same\n", __func__);
+ }
+ mutex_unlock(&psct->lock_ready);
+
+ /* to-do list */
+ /* if unreg or change mode */
+ if (psct->flg_trig_dis) {
+ psct->flg_trig_dis = 0;
+ break;
+ }
+ }
+ psct->flg_allocing = 0;
+}
+
+static void pat_set_vaddr(struct dim_pat_s *pat, unsigned int buf_size)
+{
+ bool flg_vmap = false;
+
+ if (!pat)
+ return;
+
+ if (pat->vaddr) {
+ PR_WARN("%s:vaddr exist[%d]\n", __func__, pat->header.index);
+ return;
+ }
+
+ pat->vaddr = (unsigned int *)dim_vmap(pat->mem_start,
+ buf_size,
+ &flg_vmap);
+ if (!pat->vaddr) {
+ //bset(&psct->flg_err, EDIM_SCT_ERR_VMAP);
+ PR_ERR("%s:vmap:0x%lx\n", __func__, pat->mem_start);
+ return;
+ }
+ pat->flg_vmap = flg_vmap;
+}
+
+void pat_release_vaddr(struct dim_pat_s *pat)
+{
+ if (!pat)
+ return;
+ if (pat->vaddr && pat->flg_vmap)
+ dim_unmap_phyaddr((u8 *)pat->vaddr);
+ pat->vaddr = NULL;
+}
+
+/* when from 4k to other size use this to recycle 4k buffer */
+void sct_mng_working_recycle(struct di_ch_s *pch)
+{
+ struct div2_mm_s *mm;
+ unsigned int cnt_recycle, cnt_idle;
+ struct buf_que_s *pbufq;
+ struct dim_sct_s *sct;
+ struct dim_mscttop_s *pmsct;
+ int i;
+
+ pmsct = &pch->msct_top;
+
+ if (!pmsct->box)
+ return;
+
+ mm = dim_mm_get(pch->ch_id);
+ if (mm->cfg.pbuf_flg.b.typ == EDIM_BLK_TYP_PSCT)
+ return;
+
+ pbufq = &pch->sct_qb;
+ /* recycle */
+ cnt_recycle = qbufp_count(pbufq, QBF_SCT_Q_RECYCLE);
+ if (!cnt_recycle)
+ return;
+
+ for (i = 0; i < cnt_recycle; i++) {
+ qsct_recycle_to_idle(pch, &sct);
+
+ /* pat */
+ pat_release_vaddr(sct->pat_buf);
+ qpat_in_ready(pch, sct->pat_buf);
+ sct->pat_buf = NULL;
+ sct_free_l(pch, sct);
+ }
+
+ cnt_idle = qbufp_count(pbufq, QBF_SCT_Q_IDLE);
+
+ if ((cnt_idle == DIM_SCT_NUB) &&
+ (pmsct->box)) {
+ di_mmu_box_free(pmsct->box);
+ pmsct->box = NULL;
+ pmsct->flg_act_box = 0;
+ pmsct->max_nub = 0;
+ dbg_sct("%s:release\n", __func__);
+ } else {
+ dbg_sct("%s:cnt_idle=%d\n", __func__, cnt_idle);
+ }
+}
+
+#define DIM_SCT_KEEP_READY (1)
+void sct_mng_working(struct di_ch_s *pch)
+{
+ unsigned int ch;
+ unsigned int cnt_pst_free, cnt_sct_ready, cnt_sct_req;
+ unsigned int cnt_idle, cnt_wait, need_req, req_new = 0;
+ unsigned int cnt_recycle, ready_set, cnt_pst_ready;
+ struct buf_que_s *pbufq;
+ struct dim_mscttop_s *pmsct;
+ struct dim_sct_s *sct;
+ //bool f_no_res = false;
+ bool f_req = false;
+ bool f_no_wbuf = false;
+ bool ret;
+ int i;
+ unsigned int err = 0;
+ struct di_mng_s *pbm = get_bufmng();
+ struct dim_pat_s *pat_buf = NULL;
+ struct div2_mm_s *mm;
+ struct di_buf_s *di_buf = NULL;
+ struct di_dev_s *devp = get_dim_de_devp();
+ struct di_pre_stru_s *ppre;
+ unsigned int frame_nub;
+
+ if (!pch)
+ return;
+
+ pmsct = &pch->msct_top;
+ if (!pmsct->box)
+ return;
+
+ ch = pch->ch_id;
+
+ if (atomic_read(&pbm->trig_unreg[ch]))
+ return;
+
+ mm = dim_mm_get(pch->ch_id);
+ if (mm->cfg.pbuf_flg.b.typ != EDIM_BLK_TYP_PSCT)
+ return;
+
+ pbufq = &pch->sct_qb;
+
+ ppre = get_pre_stru(ch);
+ if (!ppre) {
+ PR_ERR("%s:no ppre\n", __func__);
+ return;
+ }
+
+ frame_nub = ppre->field_count_for_cont;
+
+ /* recycle */
+ cnt_recycle = qbufp_count(pbufq, QBF_SCT_Q_RECYCLE);
+ for (i = 0; i < cnt_recycle; i++) {
+ qsct_recycle_to_idle(pch, &sct);
+
+ /* pat */
+ pat_release_vaddr(sct->pat_buf);
+ qpat_in_ready(pch, sct->pat_buf);
+ sct->pat_buf = NULL;
+ sct_free_l(pch, sct);
+ }
+
+ /*summary */
+ cnt_pst_free = di_que_list_count(ch, QUE_POST_FREE);
+ cnt_pst_ready = ndrd_cnt(pch);//di_que_list_count(ch, QUE_POST_READY);
+ cnt_idle = qbufp_count(pbufq, QBF_SCT_Q_IDLE);
+ cnt_wait = di_que_list_count(ch, QUE_PST_NO_BUF_WAIT);
+ mutex_lock(&pmsct->lock_ready);
+ cnt_sct_ready = qbufp_count(pbufq, QBF_SCT_Q_READY);
+ cnt_sct_req = qbufp_count(pbufq, QBF_SCT_Q_REQ);
+ mutex_unlock(&pmsct->lock_ready);
+
+ ready_set = cnt_sct_ready;
+ if (cnt_sct_ready && (cnt_wait < cnt_sct_ready)) {
+ //PR_INF("cnt_wait:%d->%d\n", cnt_wait, cnt_sct_ready);
+ //cnt_sct_ready = cnt_wait;
+ ready_set = cnt_wait;
+ if (!cnt_wait)
+ f_no_wbuf = true;
+ }
+
+ if (ready_set) {
+ /* ready to used */
+ for (i = 0; i < ready_set; i++) {
+ ret = qsct_ready_to_used(pch, &sct);
+ if (!ret) {
+ bset(&pmsct->flg_err, EDIM_SCT_ERR_QUE_2USED);
+ err++;
+ PR_ERR("%s:ready 2 used no sct\n", __func__);
+ break;
+ }
+ /*flash*/
+ pat_frash(&devp->pdev->dev,
+ pch,
+ sct->pat_buf);
+ /* set free buffer*/
+ di_buf = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF_WAIT);
+ if (!di_buf) {
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ break;
+ }
+ di_buf->blk_buf->pat_buf = sct->pat_buf;
+ di_buf->blk_buf->sct = sct;
+
+ di_buf->afbct_adr = sct->pat_buf->mem_start;
+ di_que_in(ch, QUE_POST_FREE, di_buf);
+ cnt_pst_free++;
+ cnt_sct_ready--;
+ }
+ //cnt_sct_ready = 0;
+ }
+
+ if ((cnt_pst_free >= DIM_SCT_KEEP_READY) ||
+ (dbg_limit_ready() && (cnt_pst_ready >= 3))) {
+ if (pmsct->flg_no_buf) {
+ pmsct->flg_no_buf = 0;
+ pch->rsc_bypass.b.no_buf = 0;/*tmp*/
+ PR_WARN("no buffer:recover[%d]\n", frame_nub);
+ }
+ return;
+ }
+ if ((cnt_pst_free + cnt_sct_req + cnt_sct_ready) >= DIM_SCT_KEEP_READY)
+ return;
+
+ need_req = DIM_SCT_KEEP_READY - cnt_pst_free - cnt_sct_req -
+ cnt_sct_ready;
+
+ if (cnt_idle >= need_req) {
+ f_req = true;
+ } else if (cnt_idle > 0) {
+ need_req = cnt_idle;
+ f_req = true;
+ }
+
+ if (f_req /*&& pat_buf && pat_buf->vaddr*/) {
+ /* required */
+
+ for (i = 0; i < need_req; i++) {
+ pat_buf = qpat_out_ready(pch);
+ //mm = dim_mm_get(pch->ch_id);
+ if (pat_buf) {
+ pat_set_vaddr(pat_buf,
+ mm->cfg.pst_afbct_size);
+ #if 1
+ /* cash */
+ if ((dbg_sct_clear_first() &&
+ (!pat_buf->flg_mode)) ||
+ dbg_sct_clear_by_frame()) {
+ pat_clear_mem(&devp->pdev->dev,
+ pch,
+ pat_buf);
+ pat_buf->flg_mode = 1;
+ }
+ #endif
+ } else {
+ PR_ERR("%s:no pat\n", __func__);
+ err++;
+ break;
+ }
+
+ mutex_lock(&pmsct->lock_ready);
+ ret = qsct_idle_to_req(pch, &sct);
+ sct->pat_buf = pat_buf;
+ sct->flg_act.b.pat = 1;
+
+ mutex_unlock(&pmsct->lock_ready);
+ if (!ret) {
+ bset(&pmsct->flg_err, EDIM_SCT_ERR_QUE_2REQ);
+ err++;
+ break;
+ }
+ cnt_sct_req++;
+ req_new++;
+ }
+ //if (req_new)
+ // mtask_wake_for_sct();
+ } else if (cnt_pst_ready >= 1) {
+ } else {
+ /* no resource */
+ if (f_no_wbuf)
+ PR_WARN("no_buf:0:cnt_wait:%d[%d]\n", cnt_sct_ready,
+ frame_nub);
+
+ if (pch->rsc_bypass.b.no_buf) {
+ if (time_after_eq(jiffies,
+ pmsct->jiff_no_buf + HZ * 3)) {
+ //print:
+ PR_WARN("no buffer:3:[%d]\n", frame_nub);
+ pmsct->jiff_no_buf = jiffies;
+ }
+ } else if (pmsct->flg_no_buf) {
+ if (time_after_eq(jiffies,
+ pmsct->jiff_no_buf + HZ)) {
+ pch->rsc_bypass.b.no_buf = 1;
+ PR_WARN("no_buf:2:[%d]\n", frame_nub);
+ }
+ } else {
+ pmsct->flg_no_buf = 1;
+ pmsct->jiff_no_buf = jiffies;
+ PR_WARN("no_buf:1:[%d:%d:%d:%d]\n",
+ frame_nub,
+ cnt_pst_free,
+ cnt_idle,
+ cnt_sct_req);
+ }
+ }
+ if (err)
+ pch->rsc_bypass.b.scr_err = 1;
+}
+
+/* now no use */
+void sct_mng_idle(struct di_ch_s *pch)
+{
+ struct dim_mscttop_s *pmsct;
+ unsigned int cnt_recycle, cnt_idle;
+ struct buf_que_s *pbufq;
+ struct dim_sct_s *sct;
+ int i;
+
+ pmsct = &pch->msct_top;
+
+ if (!pmsct->box)
+ return;
+
+ /* recycle */
+ pbufq = &pch->sct_qb;
+ cnt_recycle = qbufp_count(pbufq, QBF_SCT_Q_RECYCLE);
+ if (!cnt_recycle)
+ return;
+ for (i = 0; i < cnt_recycle; i++) {
+ qsct_recycle_to_idle(pch, &sct);
+
+ /* pat */
+ pat_release_vaddr(sct->pat_buf);
+ qpat_in_ready(pch, sct->pat_buf);
+ sct->pat_buf = NULL;
+ sct_free_l(pch, sct);
+ }
+
+ cnt_idle = qbufp_count(pbufq, QBF_SCT_Q_IDLE);
+
+ if ((cnt_idle == DIM_SCT_NUB) &&
+ (pmsct->box)) {
+ di_mmu_box_free(pmsct->box);
+ pmsct->box = NULL;
+ pmsct->flg_act_box = 0;
+ pmsct->max_nub = 0;
+ PR_INF("%s:release\n", __func__);
+ } else {
+ PR_INF("%s:cnt_idle=%d\n", __func__, cnt_idle);
+ }
+}
+
+/* sw off when rebuild */
+void sct_sw_off_rebuild(struct di_ch_s *pch)
+{
+ unsigned int ch;
+ struct dim_mscttop_s *psct;
+ struct buf_que_s *pbufq;
+ //union q_buf_u q_buf;// = NULL;
+ struct dim_sct_s *sct;
+// struct di_buf_s *di_buf;
+ int i;
+ unsigned int len;
+ bool ret;
+
+ psct = &pch->msct_top;
+ if (!psct->box) {
+ PR_WARN("%s:box is not exist\n", __func__);
+ return;
+ }
+ ch = pch->ch_id;
+
+ #ifdef HIS_CODE
+ /* clear QUE_POST_FREE */
+ for (i = 0; i < 2; i++) {
+ di_buf = di_que_peek(ch, QUE_POST_FREE);
+ if (di_buf->blk_buf && di_buf->blk_buf->sct) {
+ di_buf = di_que_out_to_di_buf(ch, QUE_POST_FREE);
+ sct = (struct dim_sct_s *)di_buf->blk_buf->sct;
+ qsct_used_some_to_recycle(pch, sct);
+ di_buf->afbct_adr = 0;
+ di_buf->blk_buf->sct = NULL;
+ di_buf->blk_buf->pat_buf = NULL;
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ } else {
+ break;
+ }
+ }
+ #endif
+ pbufq = &pch->sct_qb;
+ /* clear req */
+ len = qbufp_count(pbufq, QBF_SCT_Q_REQ);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qsct_req_to_idle(pch, &sct);
+ if (!ret) {
+ PR_ERR("%s:clear req[%d][%d]\n", __func__,
+ len, i);
+ break;
+ }
+ /*pat*/
+ if (sct->pat_buf) {
+ pat_release_vaddr(sct->pat_buf);
+ qpat_in_ready(pch, sct->pat_buf);
+ sct->pat_buf = NULL;
+ }
+ }
+ }
+
+ /* ready clear */
+ len = qbufp_count(pbufq, QBF_SCT_Q_READY);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qsct_any_to_recycle(pch, QBF_SCT_Q_READY, &sct);
+ if (!ret) {
+ PR_ERR("%s:used[%d][%d]\n", __func__, len, i);
+ break;
+ }
+ }
+ }
+}
+
+int dim_dbg_sct_top_show(struct seq_file *s, void *what)
+{
+ int *chp;
+ struct di_ch_s *pch;
+ struct dim_mscttop_s *psct;
+ struct dim_msc_sum_s *psum;
+
+ chp = (int *)s->private;
+
+ seq_printf(s, "%s:ch[%d]\n", __func__, *chp);
+ pch = get_chdata(*chp);
+
+ psct = &pch->msct_top;
+ psum = &psct->sum;
+ seq_printf(s, "\t%s:0x%x\n", "err", psct->flg_err);
+ seq_printf(s, "\t%s:%d\n", "max_nub", psct->max_nub);
+
+ seq_printf(s, "\t%s:%d\n", "flg_support", psct->flg_support);
+ seq_printf(s, "\t%s:%d\n", "flg_no_buf", psct->flg_no_buf);
+ seq_printf(s, "\t%s:%d\n", "flg_act_box", psct->flg_act_box);
+ seq_printf(s, "\t%s:%d\n", "flg_trig_dis", psct->flg_trig_dis);
+ seq_printf(s, "\t%s:%d\n", "flg_allocing", psct->flg_allocing);
+ seq_printf(s, "%s:\n", "sum");
+ seq_printf(s, "\t%s:%d\n", "max_nub", psum->max_nub);
+ seq_printf(s, "\t%s:%d\n", "max_size", psum->max_size);
+ //seq_printf(s, "\t%s:%d\n", "sum_max_tt_size", psct->sum_max_tt_size);
+ seq_printf(s, "\t%s:%d\n", "max_tt_size2", psum->max_tt_size2);
+ seq_printf(s, "\t%s:%d\n", "curr_tt_size", psum->curr_tt_size);
+ seq_printf(s, "\t%s:%d\n", "curr_nub", psum->curr_nub);
+ seq_printf(s, "\t%s:\n", "pst");
+ seq_printf(s, "\t\t%s:%d\n", "free", psum->mts_pst_free);
+ seq_printf(s, "\t\t%s:%d\n", "back", psum->mts_pst_back);
+ seq_printf(s, "\t\t%s:%d\n", "display", psum->mts_pst_dispaly);
+ seq_printf(s, "\t\t%s:%d\n", "ready", psum->mts_pst_ready);
+ seq_printf(s, "\t%s:\n", "sct");
+ seq_printf(s, "\t\t%s:%d\n", "rcc", psum->mts_sct_rcc);
+ seq_printf(s, "\t\t%s:%d\n", "ready", psum->mts_sct_ready);
+ seq_printf(s, "\t\t%s:%d\n", "used", psum->mts_sct_used);
+ return 0;
+}
+
+void sct_prob(struct di_ch_s *pch)
+{
+ struct dim_mscttop_s *psct;
+
+ psct = &pch->msct_top;
+
+ psct->flg_support = 1;
+ mutex_init(&psct->lock_ready);
+ di_mmu_box_init();
+ dbg_sct("%s:ch[%d]\n", __func__, pch->ch_id);
+}
--- /dev/null
+/*
+ * drivers/amlogic/media/di_multi/di_mem_sct_def.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __DI_MEM_SCT_DEF_H__
+#define __DI_MEM_SCT_DEF_H__
+
+//#define USE_DECODER_BOX (1)
+
+#ifdef USE_DECODER_BOX
+void *decoder_mmu_box_alloc_box(const char *name,
+ int channel_id,
+ int max_num,
+ int min_size_M,
+ int mem_flags);
+
+//int decoder_mmu_box_sc_check(void *handle, int is_tvp);
+
+int decoder_mmu_box_alloc_idx(
+ void *handle, int idx, int num_pages,
+ unsigned int *mmu_index_adr);
+
+int decoder_mmu_box_free_idx_tail(void *handle, int idx,
+ int start_release_index);
+
+int decoder_mmu_box_free_idx(void *handle, int idx);
+void *decoder_mmu_box_get_mem_handle(void *box_handle, int idx);
+
+int decoder_mmu_box_free(void *handle);
+#endif
+
+int codec_mm_keeper_unmask_keeper(int keep_id, int delayms);
+
+/*-------------------------*/
+int di_mmu_box_init(void);
+void di_mmu_box_exit(void);
+
+void *di_mmu_box_alloc_box(const char *name,
+ int channel_id,
+ int max_num,
+ int min_size_M,
+ int mem_flags);
+
+//int decoder_mmu_box_sc_check(void *handle, int is_tvp);
+
+int di_mmu_box_alloc_idx(
+ void *handle, int idx, int num_pages,
+ unsigned int *mmu_index_adr);
+
+int di_mmu_box_free_idx_tail(void *handle, int idx,
+ int start_release_index);
+
+int di_mmu_box_free_idx(void *handle, int idx);
+void *di_mmu_box_get_mem_handle(void *box_handle, int idx);
+
+int di_mmu_box_free(void *handle);
+
+#endif /*__DI_MEM_SCT_DEF_H__*/
--- /dev/null
+/*
+ * drivers/amlogic/media/di_multi/di_mmu_box.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/semaphore.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/kfifo.h>
+#include <linux/kthread.h>
+#include <linux/slab.h>
+#include <linux/amlogic/media/codec_mm/codec_mm_scatter.h>
+#include <linux/platform_device.h>
+
+#define PR_ERR(fmt, args ...) pr_err("dim:err:" fmt, ##args)
+
+struct di_mmu_box {//decoder_mmu_box
+ int max_sc_num;
+ const char *name;
+ int channel_id;
+ int tvp_mode;
+ int box_ref_cnt;
+ struct mutex mutex; /* for box */
+ struct list_head list;
+ struct codec_mm_scatter *sc_list[1];
+};
+
+#define MAX_KEEP_FRAME 4
+#define START_KEEP_ID 0x9
+#define MAX_KEEP_ID (INT_MAX - 1)
+struct di_mmu_box_mgr {//decoder_mmu_box_mgr
+ int num;
+ struct mutex mutex; /* for mgr */
+ struct codec_mm_scatter *keep_sc[MAX_KEEP_FRAME];
+ int keep_id[MAX_KEEP_FRAME];
+ int next_id;/*id for keep & free.*/
+ struct list_head box_list;
+};
+
+static struct di_mmu_box_mgr global_mgr;
+static struct di_mmu_box_mgr *get_decoder_mmu_box_mgr(void)
+{
+ return &global_mgr;
+}
+
+//decoder_mmu_box_mgr_add_box
+static int di_mmu_box_mgr_add_box(struct di_mmu_box *box)
+{
+ struct di_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr();
+
+ mutex_lock(&mgr->mutex);
+ list_add_tail(&box->list, &mgr->box_list);
+ mutex_unlock(&mgr->mutex);
+ return 0;
+}
+
+//decoder_mmu_box_mgr_del_box
+static int di_mmu_box_mgr_del_box(struct di_mmu_box *box)
+{
+ struct di_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr();
+
+ mutex_lock(&mgr->mutex);
+ list_del(&box->list);
+ mutex_unlock(&mgr->mutex);
+ return 0;
+}
+
+//ary no use now: decoder_xxx, and add 'e' after valid
+bool di_mmu_box_valid_check(void *box)
+{
+ struct di_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr();
+ struct di_mmu_box *mmu_box = NULL;
+ bool is_valid = false;
+
+ mutex_lock(&mgr->mutex);
+ list_for_each_entry(mmu_box, &mgr->box_list, list) {
+ if (mmu_box && mmu_box == box) {
+ is_valid = true;
+ break;
+ }
+ }
+ mutex_unlock(&mgr->mutex);
+
+ return is_valid;
+}
+
+//ary EXPORT_SYMBOL(decoder_mmu_box_valid_check);
+
+//decoder_mmu_try_to_release_box
+//ary no use now
+void di_mmu_try_to_release_box(void *handle)
+{
+ struct di_mmu_box *box = handle;
+ bool is_keep = false;
+ int i;
+
+ if (!box || box->box_ref_cnt)
+ return;
+
+ mutex_lock(&box->mutex);
+ for (i = 0; i < box->max_sc_num; i++) {
+ if (box->sc_list[i]) {
+ is_keep = true;
+ break;
+ }
+ }
+ mutex_unlock(&box->mutex);
+
+ if (!is_keep) {
+ di_mmu_box_mgr_del_box(box);
+ codec_mm_scatter_mgt_delay_free_swith(0, 0, 0, box->tvp_mode);
+ kfree(box);
+ }
+}
+
+//ary EXPORT_SYMBOL(decoder_mmu_try_to_release_box);
+//decoder_mmu_box_sc_check
+int di_mmu_box_sc_check(void *handle, int is_tvp)
+{
+ struct di_mmu_box *box = handle;
+
+ if (!box) {
+ PR_ERR("mmu box NULL !!!\n");
+ return 0;
+ }
+ return codec_mm_scatter_size(is_tvp);
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_sc_check);
+
+//decoder_mmu_box_alloc_box
+void *di_mmu_box_alloc_box(const char *name,
+ int channel_id,
+ int max_num,
+ int min_size_M,
+ int mem_flags)
+/*min_size_M:wait alloc this size*/
+{
+ struct di_mmu_box *box;
+ int size;
+
+ //PR_INF("di_mmu_box_alloc_box, mem_flags = 0x%x\n", mem_flags);
+
+ size = sizeof(struct di_mmu_box) +
+ sizeof(struct codec_mm_scatter *) *
+ max_num;
+ box = kmalloc(size, GFP_KERNEL);
+ if (!box) {
+ PR_ERR("can't alloc decoder buffers box!!!\n");
+ return NULL;
+ }
+ memset(box, 0, size);
+ box->max_sc_num = max_num;
+ box->name = name;
+ box->channel_id = channel_id;
+ box->tvp_mode = mem_flags;
+
+ mutex_init(&box->mutex);
+ INIT_LIST_HEAD(&box->list);
+ di_mmu_box_mgr_add_box(box);
+ codec_mm_scatter_mgt_delay_free_swith(1, 2000,
+ min_size_M, box->tvp_mode);
+ return (void *)box;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_alloc_box);
+
+//decoder_mmu_box_alloc_idx
+int di_mmu_box_alloc_idx(
+ void *handle, int idx, int num_pages,
+ unsigned int *mmu_index_adr)
+{
+ struct di_mmu_box *box = handle;
+ struct codec_mm_scatter *sc;
+ int ret;
+ int i;
+
+ if (!box || idx < 0 || idx >= box->max_sc_num) {
+ PR_ERR("can't alloc mmu box(%p),idx:%d\n",
+ box, idx);
+ return -1;
+ }
+ mutex_lock(&box->mutex);
+ sc = box->sc_list[idx];
+ if (sc) {
+ if (sc->page_max_cnt >= num_pages)
+ ret = codec_mm_scatter_alloc_want_pages(sc,
+ num_pages);
+ else {
+ box->box_ref_cnt--;
+ codec_mm_scatter_dec_owner_user(sc, 0);
+ box->sc_list[idx] = NULL;
+ sc = NULL;
+ }
+ }
+ if (!sc) {
+ sc = codec_mm_scatter_alloc(num_pages + 64, num_pages,
+ box->tvp_mode);
+ if (!sc) {
+ mutex_unlock(&box->mutex);
+ PR_ERR("alloc mmu failed, need pages=%d\n",
+ num_pages);
+ return -1;
+ }
+ box->sc_list[idx] = sc;
+ box->box_ref_cnt++;
+ }
+
+ for (i = 0; i < num_pages; i++)
+ mmu_index_adr[i] = PAGE_INDEX(sc->pages_list[i]);
+
+ mutex_unlock(&box->mutex);
+
+ return 0;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_alloc_idx);
+
+//decoder_mmu_box_free_idx_tail
+int di_mmu_box_free_idx_tail(
+ void *handle, int idx,
+ int start_release_index)
+{
+ struct di_mmu_box *box = handle;
+ struct codec_mm_scatter *sc;
+
+ if (!box || idx < 0 || idx >= box->max_sc_num) {
+ PR_ERR("can't free tail mmu box(%p),idx:%d in (%d-%d)\n",
+ box, idx, 0,
+ box ? (box->max_sc_num - 1) : 0);
+ return -1;
+ }
+ mutex_lock(&box->mutex);
+ sc = box->sc_list[idx];
+ if (sc && start_release_index < sc->page_cnt)
+ codec_mm_scatter_free_tail_pages_fast(sc,
+ start_release_index);
+ mutex_unlock(&box->mutex);
+ return 0;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_free_idx_tail);
+
+//decoder_mmu_box_free_idx
+int di_mmu_box_free_idx(void *handle, int idx)
+{
+ struct di_mmu_box *box = handle;
+ struct codec_mm_scatter *sc;
+
+ if (!box || idx < 0 || idx >= box->max_sc_num) {
+ PR_ERR("can't free idx of box(%p),idx:%d in (%d-%d)\n",
+ box, idx, 0,
+ box ? (box->max_sc_num - 1) : 0);
+ return -1;
+ }
+ mutex_lock(&box->mutex);
+ sc = box->sc_list[idx];
+ if (sc && sc->page_cnt > 0) {
+ codec_mm_scatter_dec_owner_user(sc, 0);
+ box->sc_list[idx] = NULL;
+ box->box_ref_cnt--;
+ }
+ mutex_unlock(&box->mutex);
+
+ if (sc && box->box_ref_cnt == 0)
+ codec_mm_scatter_mgt_delay_free_swith(0, 0, 0, box->tvp_mode);
+
+ return 0;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_free_idx);
+//decoder_mmu_box_free
+int di_mmu_box_free(void *handle)
+{
+ struct di_mmu_box *box = handle;
+ struct codec_mm_scatter *sc;
+ int i;
+
+ if (!box) {
+ PR_ERR("can't free box of NULL box!\n");
+ return -1;
+ }
+ mutex_lock(&box->mutex);
+ for (i = 0; i < box->max_sc_num; i++) {
+ sc = box->sc_list[i];
+ if (sc) {
+ codec_mm_scatter_dec_owner_user(sc, 0);
+ box->sc_list[i] = NULL;
+ }
+ }
+ mutex_unlock(&box->mutex);
+ di_mmu_box_mgr_del_box(box);
+ codec_mm_scatter_mgt_delay_free_swith(0, 0, 0, box->tvp_mode);
+ kfree(box);
+ return 0;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_free);
+
+//decoder_mmu_box_get_mem_handle
+void *di_mmu_box_get_mem_handle(void *box_handle, int idx)
+{
+ struct di_mmu_box *box = box_handle;
+
+ if (!box || idx < 0 || idx >= box->max_sc_num)
+ return NULL;
+ return box->sc_list[idx];
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_get_mem_handle);
+
+//decoder_mmu_box_dump
+static int di_mmu_box_dump(struct di_mmu_box *box,
+ void *buf, int size)
+{
+ char *pbuf = buf;
+ char sbuf[512];
+ int tsize = 0;
+ int s;
+ int i;
+
+ if (!buf) {
+ pbuf = sbuf;
+ size = 512;
+ }
+ #define BUFPRINT(args...) \
+ do {\
+ s = snprintf(pbuf, size - tsize, args);\
+ tsize += s;\
+ pbuf += s; \
+ } while (0)
+
+ for (i = 0; i < box->max_sc_num; i++) {
+ struct codec_mm_scatter *sc = box->sc_list[i];
+
+ if (sc) {
+ BUFPRINT("sc mem[%d]:%p, size=%d\n",
+ i, sc,
+ sc->page_cnt << PAGE_SHIFT);
+ }
+ }
+#undef BUFPRINT
+ if (!buf)
+ pr_info("%s", sbuf);
+
+ return tsize;
+}
+
+//decoder_mmu_box_dump_all
+int di_mmu_box_dump_all(void *buf, int size)
+{
+ struct di_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr();
+ char *pbuf = buf;
+ char sbuf[512];
+ int tsize = 0;
+ int s;
+ int i;
+ struct list_head *head, *list;
+
+ if (!pbuf) {
+ pbuf = sbuf;
+ size = 512;
+ }
+
+ #define BUFPRINT(args...) \
+ do {\
+ s = snprintf(pbuf, size - tsize, args);\
+ tsize += s;\
+ pbuf += s; \
+ } while (0)
+
+ mutex_lock(&mgr->mutex);
+ head = &mgr->box_list;
+ list = head->next;
+ i = 0;
+ while (list != head) {
+ struct di_mmu_box *box;
+
+ box = list_entry(list, struct di_mmu_box,
+ list);
+ BUFPRINT("box[%d]: %s, %splayer_id:%d, max_num:%d\n",
+ i,
+ box->name,
+ box->tvp_mode ? "TVP mode " : "",
+ box->channel_id,
+ box->max_sc_num);
+ if (buf) {
+ s += di_mmu_box_dump(box, pbuf, size - tsize);
+ if (s > 0) {
+ tsize += s;
+ pbuf += s;
+ }
+ } else {
+ pr_info("%s", sbuf);
+ pbuf = sbuf;
+ tsize += di_mmu_box_dump(box, NULL, 0);
+ }
+ list = list->next;
+ i++;
+ }
+ mutex_unlock(&mgr->mutex);
+
+#undef BUFPRINT
+ if (!buf)
+ pr_info("%s", sbuf);
+ return tsize;
+}
+
+#ifdef TMP_NO_USED //ary
+
+static ssize_t
+box_dump_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ ssize_t ret = 0;
+
+ ret = decoder_mmu_box_dump_all(buf, PAGE_SIZE);
+ return ret;
+}
+
+static struct class_attribute decoder_mmu_box_class_attrs[] = {
+ __ATTR_RO(box_dump),
+ __ATTR_NULL
+};
+
+static struct class decoder_mmu_box_class = {
+ .name = "decoder_mmu_box",
+ .class_attrs = decoder_mmu_box_class_attrs
+};
+#endif
+
+//decoder_mmu_box_init
+
+int di_mmu_box_init(void)
+{
+ int r = 0; //ary set 0
+
+ memset(&global_mgr, 0, sizeof(global_mgr));
+ INIT_LIST_HEAD(&global_mgr.box_list);
+ mutex_init(&global_mgr.mutex);
+ global_mgr.next_id = START_KEEP_ID;
+ //ary r = class_register(&decoder_mmu_box_class);
+ return r;
+}
+
+//EXPORT_SYMBOL(decoder_mmu_box_init);
+
+//decoder_mmu_box_exit
+void di_mmu_box_exit(void)
+{
+ // class_unregister(&decoder_mmu_box_class);
+ pr_info("dec mmu box exit.\n");
+}
+
+#ifdef TMP_NO_USED
+static int __init decoder_mmu_box_init(void)
+{
+ int r;
+
+ memset(&global_mgr, 0, sizeof(global_mgr));
+ INIT_LIST_HEAD(&global_mgr.box_list);
+ mutex_init(&global_mgr.mutex);
+ global_mgr.next_id = START_KEEP_ID;
+ r = class_register(&decoder_mmu_box_class);
+ return r;
+}
+
+module_init(decoder_mmu_box_init);
+#endif
struct di_hpst_s *pst = get_hw_pst();
unsigned int ch;
bool reflesh = false;
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
+ struct di_ch_s *pch;
ch = pst->curr_ch;
ppost = get_post_stru(ch);
vf_p = di_buf->vframe;
+ pch = get_chdata(ch);
dim_print("%s:pr_index=%d\n", __func__, di_buf->process_fun_index);
if (di_buf->process_fun_index) { /*not bypass?*/
ppost->post_wr_cnt++;
- spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
dim_post_process(di_buf, 0, vf_p->width - 1,
0, vf_p->height - 1, vf_p);
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
/*begin to count timer*/
di_tout_contr(EDI_TOUT_CONTR_EN, &pst->tout);
unsigned int ch;
struct di_post_stru_s *ppost;
bool reflesh = false;
- ulong flags = 0;
+ //ary 2020-12-07 ulong flags = 0;
ch = pst->curr_ch;
if (pst->flg_int_done) {
/*finish to count timer*/
di_tout_contr(EDI_TOUT_CONTR_FINISH, &pst->tout);
- spin_lock_irqsave(&plist_lock, flags);
+ //ary 2020-12-07 spin_lock_irqsave(&plist_lock, flags);
dim_post_de_done_buf_config(ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+ //ary 2020-12-07 spin_unlock_irqrestore(&plist_lock, flags);
pst->flg_int_done = false;
/*state*/
pst->state = EDI_PST_ST_IDLE;
struct di_hpst_s *pst = get_hw_pst();
unsigned int ch;
bool reflesh = false;
- ulong flags = 0;
+ //ary 2020-12-07 ulong flags = 0;
ch = pst->curr_ch;
dpst_timeout(ch);
- spin_lock_irqsave(&plist_lock, flags);
+ //ary 2020-12-07 spin_lock_irqsave(&plist_lock, flags);
dim_post_de_done_buf_config(ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+ //ary 2020-12-07 spin_unlock_irqrestore(&plist_lock, flags);
pst->flg_int_done = false;
pst->flg_have_set = false;
#include <linux/err.h>
#include <linux/amlogic/media/registers/regs/di_regs.h>
#include <linux/amlogic/media/vfm/vframe.h>
+#include "deinterlace.h"
+#include "di_data_l.h"
#include "di_pps.h"
#include "register.h"
unsigned short top_vphase, bot_vphase;
unsigned char is_frame;
int vert_bank_length = 4;
-
+ bool last_line_repeat = false; /* feijun.fan 2021-02-19 */
const unsigned int *filt_coef0 = di_filt_coef0;
/*unsigned int *filt_coef1 = di_filt_coef1;*/
const unsigned int *filt_coef2 = di_filt_coef2;
WR(DI_HSC_REGION1_PHASE_SLOPE, 0);
WR(DI_HSC_REGION3_PHASE_SLOPE, 0);
WR(DI_HSC_REGION4_PHASE_SLOPE, 0);
-
+ /* from vlsi feijun.fan 2021-02-19 begin: green line */
+ if (DIM_IS_IC_EF(TL1)) {
+ WR(DI_SC_DUMMY_DATA, 0x4080200);
+ wr_reg_bits(DI_SC_TOP_CTRL, 0, 27, 1); //default is 0
+ last_line_repeat = true;
+ }
+ /* from vlsi feijun.fan 2021-02-19 end */
WR(DI_HSC_PHASE_CTRL, (1 << 21) | (4 << 16) | 0);
wr_reg_bits(DI_SC_TOP_CTRL, (path ? 3 : 0), 29, 2);
WR(DI_SC_MISC,
+ (last_line_repeat << 24) | /* 2021-02-19*/
(prevsc_en << 21) |
(prehsc_en << 20) | /* prehsc_en */
(prevsc_en << 19) | /* prevsc_en */
#include "di_post.h"
#include "di_api.h"
#include "sc2/di_hw_v3.h"
+#include "reg_decontour.h"
+#include "deinterlace_dbg.h"
#include <linux/amlogic/media/di/di.h>
//#include "../deinterlace/di_pqa.h"
+unsigned int di_dbg = DBG_M_EVENT/*|DBG_M_IC|DBG_M_MEM2|DBG_M_RESET_PRE*/;
+module_param(di_dbg, uint, 0664);
+MODULE_PARM_DESC(di_dbg, "debug print");
+
/************************************************
* dim_cfg
* [0] bypass_all_p
#endif
module_param_named(dim_cfg, dim_cfg, uint, 0664);
+bool dim_dbg_cfg_post_byapss(void)
+{
+ if (dim_cfg & DI_BIT8)
+ return true;
+ return false;
+}
+
+bool dim_dbg_cfg_disable_arb(void)
+{
+ if (dim_cfg & DI_BIT9)
+ return true;
+ return false;
+}
+
+static unsigned int dim_dbg_dec21;
+
+module_param_named(dim_dbg_dec21, dim_dbg_dec21, uint, 0644);
+unsigned int dim_get_dbg_dec21(void)
+{
+ return dim_dbg_dec21;
+}
+
+bool dim_in_linear(void)
+{
+ return (dim_dbg_dec21 & 0x200) ? true : false;
+}
/**************************************
*
* cfg ctr top
* bool
**************************************/
+static unsigned int dbg_unreg_flg;
const struct di_cfg_ctr_s di_cfg_top_ctr[K_DI_CFG_NUB] = {
/*same order with enum eDI_DBG_CFG*/
1,
K_DI_CFG_T_FLG_NOTHING},
[EDI_CFG_KEEP_CLEAR_AUTO] = {"keep_buf clear auto",
+ /* 0: default */
+ /* 1: releas keep buffer when next reg */
+ /* 2: not keep buffer */
EDI_CFG_KEEP_CLEAR_AUTO,
0,
K_DI_CFG_T_FLG_NOTHING},
/* 0:default; 1: nv21; 2: nv12; 3:afbce */
/* 4: dynamic change p out put; 4k:afbce, other:yuv422 10*/
/* 5: dynamic: 4k: nv21, other yuv422 10bit */
+ /* 6: dynamic: like 4: 4k: afbce yuv420, other:yuv422 10 */
EDI_CFG_POUT_FMT,
3,
K_DI_CFG_T_FLG_DTS},
EDI_CFG_DAT,
0,
K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_ALLOC_WAIT] = {"alloc waite", /* 0:not wait; 1: wait */
- EDI_CFG_ALLOC_WAIT,
- 0, //1, //
- K_DI_CFG_T_FLG_NOTHING},
+ [EDI_CFG_ALLOC_SCT] = {"alloc_sct",
+ /* 0:not support; */
+ /* bit 0: for 4k */
+ /* bit 1: for 1080p */
+ EDI_CFG_ALLOC_SCT,
+ 1,
+ K_DI_CFG_T_FLG_DTS},
[EDI_CFG_KEEP_DEC_VF] = {"keep_dec_vf",
/* 0:not keep; 1: keep dec vf for p; 2: dynamic*/
EDI_CFG_KEEP_DEC_VF,
/* 0:not bypass; */
/* 1:bypass; */
/* 2: when 4k bypass */
+ /* 3: when 4k bypass,but not from vdin */
EDI_CFG_BYPASS_MEM,
0,
K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_IOUT_FMT] = {"io_fmt",
+ /* 0:default; 1: nv21; 2: nv12; 3:afbce */
+ EDI_CFG_IOUT_FMT,
+ 0,
+ K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_TMODE_1] = {"tmode1",
+ EDI_CFG_TMODE_1,
+ 2,
+ K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_TMODE_2] = {"tmode2",
+ EDI_CFG_TMODE_2,
+ 2,
+ K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_TMODE_3] = {"tmode3",
+ EDI_CFG_TMODE_3,
+ 0,
+ K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_LINEAR] = {"linear",
+ /* 0:canvans; */
+ /* 1:linear; */
+ EDI_CFG_LINEAR,
+ 0,
+ K_DI_CFG_T_FLG_DTS},
+ [EDI_CFG_PONLY_BP_THD] = {"bp_thd",
+ /**/
+ EDI_CFG_PONLY_BP_THD,
+ 2,
+ K_DI_CFG_T_FLG_DTS},
[EDI_CFG_END] = {"cfg top end ", EDI_CFG_END, 0,
K_DI_CFG_T_FLG_NONE},
}
//PR_INF("%s end\n", __func__);
- if (cfgg(4K) && DIM_IS_IC_BF(TM2)) {
+ if (cfgg(4K) && (DIM_IS_IC_BF(TM2) || DIM_IS_IC(T5D))) {
cfgs(4K, 0);
- PR_INF("not support 4k\n");
+ PR_WARN("not support 4k\n");
+ }
+ if (DIM_IS_IC_EF(T7)) {
+ cfgs(LINEAR, 1);
+ PR_INF("t7 linear mode\n");
}
/* dat */
/*bit 0: pst dat; bit 1: idat */
pd = &get_datal()->cfg_en[EDI_CFG_DAT];
pt = &di_cfg_top_ctr[EDI_CFG_DAT];
if (DIM_IS_IC(TM2B) ||
- DIM_IS_IC(SC2)) {// DIM_IS_IC(T5)
+ DIM_IS_IC(SC2) || DIM_IS_IC(T5) ||
+ DIM_IS_IC(T7)) {
if (!pd->b.dts_have) {
pd->b.val_c = 0x3;
//pd->b.val_c = 0x0;//test
pd->b.val_c = 0;
}
PR_INF("%s:%s:0x%x\n", __func__, pt->dts_name, pd->b.val_c);
+ /* afbce and pout */
+ if (!DIM_IS_IC(TM2B) &&
+ !DIM_IS_IC(T5) &&
+ DIM_IS_IC_EF(SC2)) {
+ if (cfgg(ALLOC_SCT)) {
+ PR_WARN("alloc_sct:not support:%d->0\n",
+ cfgg(ALLOC_SCT));
+ cfgs(ALLOC_SCT, 0);
+ }
+ if (cfgg(POUT_FMT) >= 3) {
+ PR_WARN("pout:from:%d->0\n", cfgg(POUT_FMT));
+ cfgs(POUT_FMT, 0);
+ }
+ }
}
static void di_cfgt_show_item_one(struct seq_file *s, unsigned int index)
pd->b.val_c = val;
}
+void di_cfg_cp_ch(struct di_ch_s *pch)
+{
+ int i;
+
+ for (i = 0; i < EDI_CFG_END; i++)
+ pch->cfg_cp[i] = di_cfg_top_get(i);
+}
+
+unsigned char di_cfg_cp_get(struct di_ch_s *pch, enum EDI_CFG_TOP_IDX id)
+{
+ return pch->cfg_cp[id];
+}
+
+void di_cfg_cp_set(struct di_ch_s *pch,
+ enum EDI_CFG_TOP_IDX id,
+ unsigned char val)
+{
+ pch->cfg_cp[id] = val;
+}
/**************************************
*
* cfg ctr x
edi_mp_mcdebug_mode, 0},
[edi_mp_pldn_ctrl_rflsh] = {"pldn_ctrl_rflsh:uint:1",
edi_mp_pldn_ctrl_rflsh, 1},
+ [edi_mp_pstcrc_ctrl] = {"edi_mp_pstcrc_ctrl:uint:1",
+ edi_mp_pstcrc_ctrl, 1},
[EDI_MP_SUB_DI_E] = {"di end-------",
EDI_MP_SUB_DI_E, 0},
EDI_MP_SUB_3D_E, 0},
/**************************************/
+ [edi_mp_clock_low_ratio] = {"clock_low_ratio:long?",
+ edi_mp_clock_low_ratio, 60000000},
[EDI_MP_UI_T_END] = {"module para top end ", EDI_MP_UI_T_END, 0},
};
/************************************************
* asked by pq tune
************************************************/
-static bool pulldown_enable = true;
-module_param_named(pulldown_enable, pulldown_enable, bool, 0664);
+static bool dimpulldown_enable = true;
+module_param_named(dimpulldown_enable, dimpulldown_enable, bool, 0664);
-static bool mcpre_en = true;
-module_param_named(mcpre_en, mcpre_en, bool, 0664);
+static bool dimmcpre_en = true;
+module_param_named(dimmcpre_en, dimmcpre_en, bool, 0664);
-static unsigned int mcen_mode = 1;
-module_param_named(mcen_mode, mcen_mode, uint, 0664);
+static unsigned int dimmcen_mode = 1;
+module_param_named(dimmcen_mode, dimmcen_mode, uint, 0664);
/************************************************/
void dim_mp_update_reg(void)
int val;
val = dimp_get(edi_mp_pulldown_enable);
- if (pulldown_enable != val) {
+ if (dimpulldown_enable != val) {
PR_INF("mp:pulldown_enable: %d -> %d\n",
- val, pulldown_enable);
- dimp_set(edi_mp_pulldown_enable, pulldown_enable);
+ val, dimpulldown_enable);
+ dimp_set(edi_mp_pulldown_enable, dimpulldown_enable);
}
val = dimp_get(edi_mp_mcpre_en);
- if (mcpre_en != val) {
- PR_INF("mp:mcpre_en: %d -> %d\n",
- val, mcpre_en);
- dimp_set(edi_mp_mcpre_en, mcpre_en);
+ if (dimmcpre_en != val) {
+ PR_INF("mp:dimmcpre_en: %d -> %d\n",
+ val, dimmcpre_en);
+ dimp_set(edi_mp_mcpre_en, dimmcpre_en);
}
val = dimp_get(edi_mp_mcen_mode);
- if (mcen_mode != val) {
- PR_INF("mp:mcen_mode: %d -> %d\n",
- val, mcen_mode);
- dimp_set(edi_mp_mcen_mode, mcen_mode);
+ if (dimmcen_mode != val) {
+ PR_INF("mp:dimmcen_mode: %d -> %d\n",
+ val, dimmcen_mode);
+ dimp_set(edi_mp_mcen_mode, dimmcen_mode);
}
}
int val;
val = dimp_get(edi_mp_mcen_mode);
- if (mcen_mode != val) {
- PR_INF("mp:mcen_mode: %d -> %d\n",
- val, mcen_mode);
- dimp_set(edi_mp_mcen_mode, mcen_mode);
+ if (dimmcen_mode != val) {
+ PR_INF("mp:dimmcen_mode: %d -> %d\n",
+ val, dimmcen_mode);
+ dimp_set(edi_mp_mcen_mode, dimmcen_mode);
}
}
memset(psumx, 0, sizeof(*psumx));
}
-void dim_sumx_set(unsigned int ch)
+void dim_sumx_set(struct di_ch_s *pch)
{
- struct dim_sum_s *psumx = get_sumx(ch);
+ //struct di_ch_s *pch;
+ struct dim_sum_s *psumx;// = get_sumx(ch);
+ unsigned int ch;
+ //pch = get_chdata(ch);
+ psumx = &pch->sumx;
+ ch = pch->ch_id;
psumx->b_pre_free = list_count(ch, QUEUE_LOCAL_FREE);
psumx->b_pre_ready = di_que_list_count(ch, QUE_PRE_READY);
psumx->b_pst_free = di_que_list_count(ch, QUE_POST_FREE);
- psumx->b_pst_ready = di_que_list_count(ch, QUE_POST_READY);
+ psumx->b_pst_ready = ndrd_cnt(pch);
+ //di_que_list_count(ch, QUE_POST_READY);
psumx->b_recyc = list_count(ch, QUEUE_RECYCLE);
psumx->b_display = list_count(ch, QUEUE_DISPLAY);
+ psumx->b_nin = nins_cnt(pch, QBF_NINS_Q_CHECK);
+
+ if (psumx->b_nin && psumx->b_pst_free)
+ bset(&pch->self_trig_need, 0);
+ else
+ bclr(&pch->self_trig_need, 0);
}
/****************************/
pbm->cma_flg_run = 0;
}
-#ifdef MARK_SC2
-static void dip_wq_cma_handler(struct work_struct *work)
-{
- struct di_mng_s *pbm = get_bufmng();
- enum EDI_CMA_ST cma_st;
- bool do_flg;
- struct dim_wq_s *wq;
- ulong flags = 0;
-
- unsigned int ch;
- unsigned int cma_cmd;
-
- spin_lock_irqsave(&plist_lock, flags);
- pbm->cma_flg_run |= DI_BIT0;
- wq = container_of(work, struct dim_wq_s, wq_work);
- do_flg = false;
- ch = wq->ch;
- cma_cmd = wq->cmd;
- spin_unlock_irqrestore(&plist_lock, flags);
- cma_st = dip_cma_get_st(ch);
-
- dbg_wq("%s:ch[%d],cmd[%d],st[%d][%d]\n",
- "k:h:", ch, cma_cmd, cma_st, wq->cnt);
-
- /* release alloc one ******************************/
- if (cma_cmd == ECMA_CMD_ONE_RE_AL) {
- dpst_cma_re_alloc_re_alloc(ch);
-
- spin_lock_irqsave(&plist_lock, flags);
- pbm->cma_flg_run &= (~DI_BIT0);
- pbm->cma_flg_run &= (~DI_BIT3);
- task_send_ready();
- spin_unlock_irqrestore(&plist_lock, flags);
- return;
- } else if (cma_cmd == ECMA_CMD_ONE_RELEAS) {
- dpst_cma_r_back_unreg(ch);
-
- spin_lock_irqsave(&plist_lock, flags);
- pbm->cma_flg_run &= (~DI_BIT0);
- pbm->cma_flg_run &= (~DI_BIT3);
- task_send_ready();
- spin_unlock_irqrestore(&plist_lock, flags);
- return;
- }
- /**************************************************/
- switch (cma_st) {
- case EDI_CMA_ST_IDL:
- if (cma_cmd == ECMA_CMD_ALLOC) {
- do_flg = true;
- /*set:alloc:*/
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_ALLOC);
- if (dim_cma_top_alloc(ch)) {
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_READY);
- }
- }
- break;
- case EDI_CMA_ST_READY:
- if ((cma_cmd == ECMA_CMD_RELEASE) ||
- (cma_cmd == ECMA_CMD_BACK)) {
- do_flg = true;
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_RELEASE);
- dim_cma_top_release(ch);
- if (di_que_is_empty(ch, QUE_POST_KEEP))
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_IDL);
- else
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_PART);
- dpst_cma_re_alloc_unreg(ch);
- }
- break;
- case EDI_CMA_ST_PART:
- if (cma_cmd == ECMA_CMD_ALLOC) {
- do_flg = true;
- /*set:alloc:*/
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_ALLOC);
- if (dim_cma_top_alloc(ch)) {
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_READY);
- }
- } else if ((cma_cmd == ECMA_CMD_RELEASE) ||
- (cma_cmd == ECMA_CMD_BACK)) {
- do_flg = true;
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_RELEASE);
- dim_cma_top_release(ch);
- if (di_que_is_empty(ch, QUE_POST_KEEP))
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_IDL);
- else
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_PART);
- }
-
- break;
- case EDI_CMA_ST_ALLOC: /*do*/
- case EDI_CMA_ST_RELEASE:/*do*/
- default:
- break;
- }
- if (!do_flg)
- PR_INF("\tch[%d],do nothing[%d]\n", ch, cma_st);
-
- dbg_wq("%s:end\n", __func__);
- spin_lock_irqsave(&plist_lock, flags);
- pbm->cma_flg_run &= (~DI_BIT0);
- pbm->cma_flg_run &= (~DI_BIT3);
- task_send_ready();
- spin_unlock_irqrestore(&plist_lock, flags);
-}
-
-static void dip_wq_prob(void)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- pbm->wq.wq_cma = create_singlethread_workqueue("deinterlace");
- INIT_WORK(&pbm->wq.wq_work, dip_wq_cma_handler);
-}
-
-static void dip_wq_ext(void)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- cancel_work_sync(&pbm->wq.wq_work);
- destroy_workqueue(pbm->wq.wq_cma);
- pr_info("%s:finish\n", __func__);
-}
-#endif
-#ifdef MARK_SC2
-static void dip_wq_check(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
- enum EDI_CMA_ST cma_st;
-
- /* for reg */
- if (pbm->cma_wqsts[ch] & DI_BIT0) {
- PR_WARN("k:cma_check:ch[%d] release lost\n", ch);
- pbm->cma_wqsts[ch] &= (~DI_BIT0);
- }
- if (pbm->cma_wqsts[ch] & DI_BIT1) {
- pbm->cma_wqsts[ch] &= (~DI_BIT1);
- cma_st = dip_cma_get_st(ch);
- if (cma_st == EDI_CMA_ST_IDL ||
- cma_st == EDI_CMA_ST_PART) {
- dip_wq_cma_run(ch, ECMA_CMD_ALLOC);
- PR_WARN("k:cma_re:ch[%d]\n", ch);
- }
- }
-}
-
-void dip_wq_check_unreg(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- if (pbm->cma_wqsts[ch] & DI_BIT0) {
- PR_WARN("k:unreg\n");
- /* after unreg */
- cancel_work_sync(&pbm->wq.wq_work);
- pbm->cma_wqsts[ch] &= (~DI_BIT0);
- dip_wq_cma_run(ch, ECMA_CMD_RELEASE);
- }
-}
-
-void dip_wq_cma_run(unsigned char ch, unsigned int reg_cmd)
-{
- struct di_mng_s *pbm = get_bufmng();
- bool ret = true;
-
- dbg_wq("%s:ch[%d] [%d][%d]\n",
- "k:u", ch, reg_cmd, pbm->cma_wqcnt);
- pbm->cma_flg_run |= DI_BIT2;
- if (pbm->cma_flg_run & DI_BIT0) {
- if (reg_cmd == ECMA_CMD_ALLOC)
- pbm->cma_wqsts[ch] |= DI_BIT1;
- else if (reg_cmd == ECMA_CMD_RELEASE)
- pbm->cma_wqsts[ch] |= DI_BIT0;
- else if (reg_cmd == ECMA_CMD_ONE_RE_AL)
- pbm->cma_wqsts[ch] |= DI_BIT3;
- else if (reg_cmd == ECMA_CMD_ONE_RELEAS)
- pbm->cma_wqsts[ch] |= DI_BIT4;
- PR_WARN("k:cma:2 ch[%d][%d]\n", ch, reg_cmd);
- pbm->cma_flg_run &= (~DI_BIT2);
- return;
- }
-
- pbm->wq.cmd = reg_cmd;
-
- pbm->wq.ch = ch;
- pbm->wq.cnt = pbm->cma_wqcnt;
- ret = queue_work(pbm->wq.wq_cma, &pbm->wq.wq_work);
- if (!ret) {
- PR_WARN("k:cma:ch[%d] [%d]\n", ch, reg_cmd);
- if (reg_cmd == ECMA_CMD_ALLOC)
- pbm->cma_wqsts[ch] |= DI_BIT1;
- else if (reg_cmd == ECMA_CMD_RELEASE)
- pbm->cma_wqsts[ch] |= DI_BIT0;
- else if (reg_cmd == ECMA_CMD_ONE_RE_AL)
- pbm->cma_wqsts[ch] |= DI_BIT3;
- else if (reg_cmd == ECMA_CMD_ONE_RELEAS)
- pbm->cma_wqsts[ch] |= DI_BIT4;
- } else {
- pbm->cma_flg_run |= DI_BIT3;
- }
- pbm->cma_wqcnt++;
- pbm->cma_flg_run &= (~DI_BIT2);
- dbg_wq("%s:end\n", "k:u");
-}
-
-bool dip_cma_st_is_ready(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
- bool ret = false;
-
- if (atomic_read(&pbm->cma_mem_state[ch]) == EDI_CMA_ST_READY)
- ret = true;
-
- return ret;
-}
-#endif
-
bool dip_cma_st_is_idle(unsigned int ch)
{
struct di_mng_s *pbm = get_bufmng();
struct vframe_s *vframe;
struct di_pre_stru_s *ppre;// = get_pre_stru(ch);
// struct di_mng_s *pbm = get_bufmng();
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
struct di_ch_s *pch;
struct di_mng_s *pbm = get_bufmng();
for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
pch = get_chdata(ch);
- if (atomic_read(&pbm->trig_reg[ch]))
- dim_process_reg(pch);
if (atomic_read(&pbm->trig_unreg[ch]))
dim_process_unreg(pch);
+ else if (atomic_read(&pbm->trig_reg[ch]))
+ dim_process_reg(pch);
+
dip_process_reg_after(pch);
break;
case EDI_TOP_STATE_READY:
- spin_lock_irqsave(&plist_lock, flags);
- dim_post_keep_back_recycle(ch);
- spin_unlock_irqrestore(&plist_lock, flags);
- dim_sumx_set(ch);
+ dip_itf_vf_op_polling(pch);
+ dip_itf_back_input(pch);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
+ dim_post_keep_back_recycle(pch);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
+ //move dim_sumx_set(ch);
+ //dbg_nins_check_id(pch);
+// tst_release(pch);
#ifdef SC2_NEW_FLOW
ins_in_vf(pch);
#endif
break;
case EDI_TOP_STATE_BYPASS:
- vframe = pw_vf_peek(ch);
+ if (dip_itf_is_ins_exbuf(pch)) {
+ PR_ERR("%s:bypss:extbuf\n", __func__);
+ break;
+ }
+ vframe = pw_vf_peek(pch->ch_id);//nins_peekvfm(pch);
+
if (!vframe)
break;
if (dim_need_bypass(ch, vframe))
}
}
+void dip_sum_post_ch(void)
+{
+ unsigned int ch;
+ unsigned int chst;
+ struct di_ch_s *pch;
+ unsigned int cnt;
+
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+ chst = dip_chst_get(ch);
+ switch (chst) {
+ case EDI_TOP_STATE_READY:
+ dim_sumx_set(pch);
+ bclr(&pch->self_trig_mask, 30);
+ break;
+ default:
+ bset(&pch->self_trig_mask, 30);
+ break;
+ }
+ cnt = ndkb_cnt(pch);
+ if (cnt)
+ task_send_ready();
+ }
+}
+
#ifdef MARK_SC2
bool dip_chst_change_2unreg(void)
{
case EDI_TOP_STATE_IDLE:
queue_init2(ch);
di_que_init(ch);
+ bufq_nin_reg(pch);
//move to event di_vframe_reg(ch);
+ di_cfg_cp_ch(pch);
dip_chst_set(ch, EDI_TOP_STATE_REG_STEP1);
task_send_cmd(LCMD1(ECMD_REG, ch));
unsigned int ch = pch->ch_id;
struct di_pre_stru_s *ppre = get_pre_stru(ch);
bool reflesh = true;
- struct di_mng_s *pbm = get_bufmng();
+// struct di_mng_s *pbm = get_bufmng();
// ulong flags = 0;
while (reflesh) {
case EDI_TOP_STATE_IDLE:
break;
case EDI_TOP_STATE_REG_STEP1:/*wait peek*/
- vframe = pw_vf_peek(ch);
+ dip_itf_vf_op_polling(pch);
+ vframe = nins_peekvfm(pch);
if (vframe) {
dbg_timer(ch, EDBG_TIMER_FIRST_GET);
}
break;
case EDI_TOP_STATE_REG_STEP1_P1:
- vframe = pw_vf_peek(ch);
+ vframe = nins_peekvfm(pch);
if (!vframe) {
PR_ERR("%s:p1 vfm nop\n", __func__);
dip_chst_set(ch, EDI_TOP_STATE_REG_STEP1);
reflesh = true;
break;
}
+ #ifdef MARK_HIS
if (pbm->cma_flg_run & DI_BIT0)
break;
-
+ #endif
di_reg_variable(ch, vframe);
/*di_reg_process_irq(ch);*/ /*check if bypass*/
set_reg_setting(ch, true);
mem_alloc_check(pch)) {
mem_cfg(pch);
#endif
- mem_cfg_realloc_wait(pch);
- if (di_cfg_top_get(EDI_CFG_FIRST_BYPASS)) {
- if (get_sum_g(ch) == 0)
- dim_bypass_first_frame(ch);
- else
+ //mem_cfg_realloc_wait(pch);
+ sct_mng_working(pch);
+ sct_alloc_in_poling(pch->ch_id);
+ if (di_cfg_top_get(EDI_CFG_FIRST_BYPASS) &&
+ (pch->itf.etype == EDIM_NIN_TYPE_VFM)) {
+ if (get_sum_g(ch) == 0) {
+ if (dip_itf_vf_sop(pch) &&
+ dip_itf_vf_sop(pch)->vf_m_bypass_first_frame)
+ dip_itf_vf_sop(pch)->vf_m_bypass_first_frame(pch);
+ } else {
PR_INF("ch[%d],g[%d]\n",
ch, get_sum_g(ch));
+ }
}
+
dip_chst_set(ch, EDI_TOP_STATE_READY);
set_reg_flag(ch, true);
}
}
}
+/****************************************************************
+ * tmode
+ ****************************************************************/
+void dim_tmode_preset(void)
+{
+ struct di_mng_s *pbm = get_bufmng();
+ unsigned int ch;
+ unsigned int cnt;
+
+ /*EDIM_TMODE_1_PW_VFM*/
+ cnt = min_t(size_t, DI_CHANNEL_NUB, cfgg(TMODE_1));
+ cnt = min_t(size_t, DIM_K_VFM_IN_LIMIT, cnt);
+ for (ch = 0; ch < cnt; ch++)
+ pbm->tmode_pre[ch] = EDIM_TMODE_1_PW_VFM;
+
+ /*EDIM_TMODE_2_PW_OUT*/
+ cnt += cfgg(TMODE_2);
+ cnt = min_t(size_t, DI_CHANNEL_NUB, cnt);
+ for (; ch < cnt; ch++)
+ pbm->tmode_pre[ch] = EDIM_TMODE_2_PW_OUT;
+
+ /*EDIM_TMODE_3_PW_LOCAL*/
+ cnt += cfgg(TMODE_3);
+ cnt = min_t(size_t, DI_CHANNEL_NUB, cnt);
+ for (; ch < cnt; ch++)
+ pbm->tmode_pre[ch] = EDIM_TMODE_3_PW_LOCAL;
+
+ /*dbg*/
+ PR_INF("%s:\n", __func__);
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++)
+ PR_INF("\tch[%d]:tmode[%d]\n", ch, pbm->tmode_pre[ch]);
+}
+
+void dim_tmode_set(unsigned int ch, enum EDIM_TMODE tmode)
+{
+ struct di_mng_s *pbm = get_bufmng();
+
+ if (ch >= DI_CHANNEL_NUB)
+ return;
+
+ pbm->tmode_pre[ch] = tmode;
+}
+
+bool dim_tmode_is_localpost(unsigned int ch)
+{
+// struct di_mng_s *pbm = get_bufmng();
+ struct di_ch_s *pch;
+
+ if (ch >= DI_CHANNEL_NUB) {
+ PR_ERR("%s:ch[%d]\n", __func__, ch);
+ return false;
+ }
+ pch = get_chdata(ch);
+
+ if (pch->itf.tmode == EDIM_TMODE_2_PW_OUT)
+ return false;
+ return true;
+}
+
+/************************************************/
void dip_hw_process(void)
{
di_dbg_task_flg = 5;
di_dbg_task_flg = 7;
dpst_process();
di_dbg_task_flg = 8;
+ dpre_after_do_table();
}
const char * const di_top_state_name[] = {
.num_step1_post = 1,
};
+static const struct di_mm_cfg_s c_mm_cfg_normal_ponly = {
+ .di_h = 1088,
+ .di_w = 1920,
+ .num_local = 0,
+ .num_post = POST_BUF_NUM,
+ .num_step1_post = 1,
+};
+
static const struct di_mm_cfg_s c_mm_cfg_4k = {
.di_h = 2160,
.di_w = 3840,
.num_step1_post = 0,
};
-const struct di_mm_cfg_s *di_get_mm_tab(unsigned int is_4k)
+const struct di_mm_cfg_s *di_get_mm_tab(unsigned int is_4k,
+ struct di_ch_s *pch)
{
if (is_4k)
return &c_mm_cfg_4k;
+ else if (pch->ponly)
+ return &c_mm_cfg_normal_ponly;
else
return &c_mm_cfg_normal;
}
{
const struct do_table_ops_s *pcrr;
unsigned int ret = 0;
- unsigned int next;
+ unsigned int next = 0;
bool flash = false;
unsigned int cnt = 0; /*proction*/
unsigned int lst_id; /*dbg only*/
/*pause?*/
if (pdo->op_crr == K_DO_TABLE_ID_STOP ||
- pdo->op_crr == K_DO_TABLE_ID_PAUSE)
+ pdo->op_crr == K_DO_TABLE_ID_PAUSE) {
+ lst_id = pdo->op_crr;
return;
+ }
do {
flash = false;
}
pcrr = pdo->ptab + pdo->op_crr;
+ dbg_dt("next[%d] op[%d] flash[%d]\n", next, pdo->op_crr, flash);
} while (flash && !pdo->do_step);
/*debug 2:*/
pp->std = DIM_POLICY_STD;
else
pp->std = DIM_POLICY_STD_OLD;
+ } else if (DIM_IS_IC(T5D)) {
+#ifdef TEST_DISABLE_BYPASS_P
+ pp->std = DIM_POLICY_NOT_LIMIT;
+#else
+ if (de_devp->clkb_max_rate >= 334000000)
+ pp->std = DIM_POLICY_STD;
+ else
+ pp->std = DIM_POLICY_STD_OLD;
+#endif
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
#ifdef TEST_DISABLE_BYPASS_P
pp->std = DIM_POLICY_NOT_LIMIT;
unsigned int reason = 0;
unsigned int ptt, pcu, i;
unsigned int ch;
+ unsigned int x, y;
ch = pch->ch_id;
dump_stack();
return reason;
}
+ dim_vf_x_y(vf, &x, &y);
/*count total*/
ptt = 0;
for (i = 0; i < DI_CHANNEL_NUB; i++)
ptt -= pp->ch[ch];
/*count current*/
- pcu = (vf->height >> DIM_POLICY_SHIFT_H) *
- (vf->width >> DIM_POLICY_SHIFT_W);
+ pcu = (y >> DIM_POLICY_SHIFT_H) *
+ (x >> DIM_POLICY_SHIFT_W);
if (VFMT_IS_I(vf->type))
pcu >>= 1;
{
struct di_ch_s *pch = get_chdata(ch);
- if ((cfgg(4K) == 1) ||
- ((cfgg(4K) == 2) && IS_VDIN_SRC(pch->src_type)))
+ if ((cfggch(pch, 4K) == 1) ||
+ ((cfggch(pch, 4K) == 2) && IS_VDIN_SRC(pch->src_type)))
+ return true;
+ return false;
+}
+
+bool dip_is_support_nv2110(unsigned int ch)
+{
+ struct di_ch_s *pch = get_chdata(ch);
+
+ if ((cfggch(pch, POUT_FMT) == 6) && (!IS_VDIN_SRC(pch->src_type)))
+ return true;
+ return false;
+}
+
+bool dip_is_4k_sct_mem(struct di_ch_s *pch)
+{
+ if ((cfggch(pch, ALLOC_SCT) & DI_BIT0))
+ return true;
+
+ return false;
+}
+
+bool dip_is_ponly_sct_mem(struct di_ch_s *pch)
+{
+ if ((cfggch(pch, ALLOC_SCT) & DI_BIT1))
return true;
+
return false;
}
struct di_post_stru_s *ppost;
struct di_pre_stru_s *ppre = get_pre_stru(ch);
struct di_ch_s *pch = get_chdata(ch);
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
enum EDI_SGN sgn;
unsigned int post_nub;
dim_bypass_st_clear(pch);
/* dw */
dw_int();
+ /* check format */
+ if (!dip_itf_is_ins_exbuf(pch)) {
+ if (cfggch(pch, POUT_FMT) <= 3 && cfggch(pch, IOUT_FMT) <= 3) {
+ cfgsch(pch, ALLOC_SCT, 0);
+ PR_INF("%s:chang alloc_sct\n", __func__);
+ }
+ }
if (cfgg(PMODE) == 2) {
//prog_proc_config = 3;
dimp_set(edi_mp_use_2_interlace_buff, 1);
}
pch->src_type = vframe->source_type;
+ if ((vframe->flag & VFRAME_FLAG_DI_P_ONLY) || bget(&dim_cfg, 1)) {
+ pch->ponly = true;
+ pch->rsc_bypass.b.ponly_fst_cnt = cfggch(pch, PONLY_BP_THD);
+ } else {
+ pch->ponly = false;
+ pch->rsc_bypass.b.ponly_fst_cnt = 0;
+ }
+
if (dim_afds())
di_set_default(ch);
if (cfgg(FIX_BUF)) {
if (dim_afds() &&
- cfgg(4K)) {
+ cfggch(pch, 4K)) {
memcpy(&mm->cfg, &c_mm_cfg_fix_4k,
sizeof(struct di_mm_cfg_s));
} else {
sizeof(struct di_mm_cfg_s));
}
mm->cfg.fix_buf = 1;
- } else if (!cfgg(4K)) {
+ } else if (pch->ponly && dip_is_ponly_sct_mem(pch)) {
+ if (!cfggch(pch, 4K))
+ memcpy(&mm->cfg, &c_mm_cfg_normal,
+ sizeof(struct di_mm_cfg_s));
+ else
+ memcpy(&mm->cfg, &c_mm_cfg_4k,
+ sizeof(struct di_mm_cfg_s));
+ } else if (!cfggch(pch, 4K)) {
memcpy(&mm->cfg, &c_mm_cfg_normal, sizeof(struct di_mm_cfg_s));
} else if (sgn <= EDI_SGN_HD) {
memcpy(&mm->cfg, &c_mm_cfg_normal, sizeof(struct di_mm_cfg_s));
- if (cfgg(POUT_FMT) == 4)
+ if ((cfggch(pch, POUT_FMT) == 4) ||
+ (cfggch(pch, POUT_FMT) == 6))
mm->cfg.dis_afbce = 1;
} else if ((sgn <= EDI_SGN_4K) &&
dim_afds() &&
memcpy(&mm->cfg, &c_mm_cfg_bypass, sizeof(struct di_mm_cfg_s));
}
+ if (pch->ponly && dip_is_ponly_sct_mem(pch))
+ mm->cfg.dis_afbce = 0;
+ else if ((cfggch(pch, POUT_FMT) <= 2))
+ mm->cfg.dis_afbce = 1;
+
if (cfgg(FIX_BUF))
mm->cfg.fix_buf = 1;
else
mm->cfg.fix_buf = 0;
- post_nub = cfgg(POST_NUB);
+ if (pch->ponly) {
+ PR_INF("%s:ponly\n", __func__);
+ mm->cfg.num_local = 0;
+ }
+
+ post_nub = cfggch(pch, POST_NUB);
if ((post_nub) && (post_nub < POST_BUF_NUM))
mm->cfg.num_post = post_nub;
unsigned int h, v;
enum EDI_SGN sgn;
+#ifdef HIS_CODE
if (IS_COMP_MODE(vframe->type)) {
h = vframe->compWidth;
v = vframe->compHeight;
h = vframe->width;
v = vframe->height;
}
+#endif
+ dim_vf_x_y(vframe, &h, &v);
if (h <= 1280 && v <= 720) {
sgn = EDI_SGN_SD;
return sgn;
}
-static bool dip_init_value(void)
+/************************************************
+ *
+ ************************************************/
+static void pq_sv_db_ini(void)
{
- unsigned int ch;
- struct di_post_stru_s *ppost;
- struct di_mm_s *mm;
- struct dim_mm_t_s *mmt = dim_mmt_get();
- struct di_ch_s *pch;
- bool ret = false;
+ struct db_save_s *dbp;
+ /* dct */
+ if (DIM_IS_IC(T5)) {
+ dbp = &get_datal()->db_save[DIM_DB_SV_DCT_BL2];
+ dbp->support = 1;
+ dbp->addr = DCTR_BLENDING2;
+ }
+}
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pch = get_chdata(ch);
- pch->ch_id = ch;
- ppost = get_post_stru(ch);
- memset(ppost, 0, sizeof(struct di_post_stru_s));
- ppost->next_canvas_id = 1;
+void dim_pq_db_setreg(unsigned int nub, unsigned int *preg)
+{
+ unsigned int i;
+ struct db_save_s *dbp;
+ unsigned int nubl;
- /*que*/
- ret = di_que_alloc(ch);
- if (ret) {
- pw_queue_clear(ch, QUE_POST_KEEP);
- pw_queue_clear(ch, QUE_POST_KEEP_BACK);
- }
- mm = dim_mm_get(ch);
- memcpy(&mm->cfg, &c_mm_cfg_normal, sizeof(struct di_mm_cfg_s));
- }
+ if (dil_get_diffver_flag() != 1)
+ return;
+
+ nubl = nub;
+ if (nubl > DIM_DB_SAVE_NUB) {
+ PR_ERR("%s:nub is overflow %d\n",
+ __func__, nub);
+ nubl = DIM_DB_SAVE_NUB;
+ }
+
+ for (i = 0; i < nubl; i++) {
+ dbp = &get_datal()->db_save[i];
+ dbp->addr = preg[i];
+ PR_INF("%s:reg:0x%x\n", __func__, preg[i]);
+ }
+}
+EXPORT_SYMBOL(dim_pq_db_setreg);
+
+/**************************************************
+ * pdate:
+ * value / mask
+ * need keep same order with di_patch_mov_setreg
+ **************************************************/
+bool dim_pq_db_sel(unsigned int idx, unsigned int mode, unsigned int *pdate)
+{
+ struct db_save_s *dbp;
+ //int i;
+ bool ret = true;
+
+ if (dil_get_diffver_flag() != 1)
+ return false;
+
+ if (idx >= DIM_DB_SAVE_NUB)
+ return false;
+
+ dbp = &get_datal()->db_save[idx];
+
+ if (!dbp->support)
+ return false;
+
+ switch (mode) {
+ case 0:/*setting from db*/
+ dbp->mode = 0;
+ dbp->update = 1;
+ break;
+ case 1:/*setting from pq*/
+ dbp->update = 0;
+
+ dbp->val_pq = pdate[0];
+ dbp->mask = pdate[1];
+ dbp->en_pq = true;
+
+ dbp->mode = 1;
+ dbp->update = true;
+
+ break;
+ default:
+ ret = false;
+ break;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(dim_pq_db_sel);
+
+void di_pq_db_setting(enum DIM_DB_SV idx)
+{
+ unsigned int val, vall;
+ struct db_save_s *dbp;
+ const struct reg_acc *op = &di_pre_regset;
+
+ if (idx >= DIM_DB_SAVE_NUB)
+ return;
+
+ dbp = &get_datal()->db_save[idx];
+
+ if (!dbp->support ||
+ dbp->mode < 0 ||
+ dbp->mode > 1 ||
+ !dbp->update)
+ return;
+ dbg_pq("%s:1\n", __func__);
+ if ((dbp->mode == 0) && dbp->en_db) {
+ val = dbp->val_db;
+ } else if ((dbp->mode == 1) && (dbp->en_pq)) {
+ val = dbp->val_pq;
+ } else {
+ dbg_pq("%s:mode[%d], en[%d,%d]\n",
+ __func__, dbp->mode,
+ dbp->en_db,
+ dbp->en_pq);
+ return;
+ }
+
+ if (dbp->mask != 0xffffffff) {
+ vall = ((op->rd(dbp->addr) &
+ (~(dbp->mask))) |
+ (val & dbp->mask));
+ } else {
+ vall = val;
+ }
+ op->wr(dbp->addr, vall);
+ dbg_pq("%s:0x%x,0x%x\n", __func__, dbp->addr, val);
+ dbp->update = 0;
+}
+
+struct dim_rpt_s *dim_api_getrpt(struct vframe_s *vfm)
+{
+ struct di_buf_s *di_buf;
+
+ if (dil_get_diffver_flag() != 1)
+ return NULL;
+
+ if (!vfm)
+ return NULL;
+ if ((!vfm->private_data) ||
+ ((vfm->type & VIDTYPE_DI_PW) == 0))
+ return NULL;
+
+ di_buf = (struct di_buf_s *)vfm->private_data;
+ return &di_buf->pq_rpt;
+}
+EXPORT_SYMBOL(dim_api_getrpt);
+
+void dim_pqrpt_init(struct dim_rpt_s *rpt)
+{
+ if (!rpt)
+ return;
+
+ dim_print("%s:\n", __func__);
+ memset(rpt, 0, sizeof(*rpt));
+ rpt->version = 1;
+}
+
+/*******************************************/
+static bool dip_init_value(void)
+{
+ unsigned int ch;
+ struct di_post_stru_s *ppost;
+ struct div2_mm_s *mm;
+ struct dim_mm_t_s *mmt = dim_mmt_get();
+ struct di_ch_s *pch;
+ bool ret = false;
+
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+ pch->ch_id = ch;
+ ppost = get_post_stru(ch);
+ memset(ppost, 0, sizeof(struct di_post_stru_s));
+ ppost->next_canvas_id = 1;
+
+ /*que*/
+ ret = di_que_alloc(ch);
+ if (ret) {
+// pw_queue_clear(ch, QUE_POST_KEEP);
+// pw_queue_clear(ch, QUE_POST_KEEP_BACK);
+ }
+ mm = dim_mm_get(ch);
+ memcpy(&mm->cfg, &c_mm_cfg_normal, sizeof(struct di_mm_cfg_s));
+ }
mmt->mem_start = 0;
mmt->mem_size = 0;
mmt->total_pages = NULL;
return ret;
}
+/************************************************
+ * ins
+ ************************************************/
+static const struct que_creat_s qbf_nin_cfg_q[] = {//TST_Q_IN_NUB
+ [QBF_NINS_Q_IDLE] = {
+ .name = "QBF_NINS_Q_IDLE",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NINS_Q_CHECK] = {
+ .name = "QBF_NINS_Q_CHECK",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NINS_Q_USED] = {
+ .name = "QBF_NINS_Q_USED",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NINS_Q_RECYCL] = {
+ .name = "QBF_NINS_Q_RECYCL",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NINS_Q_USEDB] = {
+ .name = "QBF_NINS_Q_USEDB",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ }
+};
+
+static const struct qbuf_creat_s qbf_nin_cfg_qbuf = {
+ .name = "qbuf_nin",
+ .nub_que = QBF_NINS_Q_NUB,
+ .nub_buf = DIM_NINS_NUB,
+ .code = CODE_NIN,
+};
+
+void bufq_nin_int(struct di_ch_s *pch)
+{
+ struct dim_nins_s *nin;
+ struct buf_que_s *pbufq;
+ int i;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+
+ /* clear buf*/
+ nin = &pch->nin_bf[0];
+ memset(nin, 0, sizeof(*nin) * DIM_NINS_NUB);
+
+ /* set buf's header */
+ for (i = 0; i < DIM_NINS_NUB; i++) {
+ nin = &pch->nin_bf[i];
+
+ nin->header.code = CODE_NIN;
+ nin->header.index = i;
+ nin->header.ch = pch->ch_id;
+ }
+
+ pbufq = &pch->nin_qb;
+ /*clear bq */
+ memset(pbufq, 0, sizeof(*pbufq));
+
+ /* point to resource */
+ for (i = 0; i < QBF_NINS_Q_NUB; i++)
+ pbufq->pque[i] = &pch->nin_q[i];
+
+ for (i = 0; i < DIM_NINS_NUB; i++)
+ pbufq->pbuf[i].qbc = &pch->nin_bf[i].header;
+
+ qbuf_int(pbufq, &qbf_nin_cfg_q[0], &qbf_nin_cfg_qbuf);
+
+ /* all to idle */
+ qbuf_in_all(pbufq, QBF_NINS_Q_IDLE);
+ PR_INF("%s:\n", __func__);
+}
+
+void bufq_nin_exit(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+
+ PR_INF("%s:\n", __func__);
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ pbufq = &pch->nin_qb;
+
+ qbuf_release_que(pbufq);
+}
+
+/*********************************
+ * dependent:
+ * pch->itf->etype
+ * Be dependent:
+ * vfm input
+ *********************************/
+void bufq_nin_reg(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ int i;
+ struct dim_nins_s *nin;
+
+ PR_INF("%s:\n", __func__);
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ pbufq = &pch->nin_qb;
+
+ qbuf_reset(pbufq);
+ /* all to idle */
+ qbuf_in_all(pbufq, QBF_NINS_Q_IDLE);
+
+ for (i = 0; i < DIM_NINS_NUB; i++) {
+ nin = &pch->nin_bf[i];
+ /* set etype */
+ nin->etype = pch->itf.etype;
+ memset(&nin->c, 0, sizeof(nin->c));
+ }
+ //qbuf_dbg_checkid(pbufq, 1);
+}
+
+struct dim_nins_s *nins_peek(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_nins_s *ins;
+ bool ret;
+
+ pbufq = &pch->nin_qb;
+ //qbuf_peek_s(pbufq, QBF_INS_Q_IN, q_buf);
+ ret = qbufp_peek(pbufq, QBF_NINS_Q_CHECK, &q_buf);
+ if ((!ret) || (!q_buf.qbc))
+ return NULL;
+ ins = (struct dim_nins_s *)q_buf.qbc;
+
+ return ins;
+}
+
+struct vframe_s *nins_peekvfm(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_nins_s *ins;
+ struct vframe_s *vfm;
+ bool ret;
+
+ pbufq = &pch->nin_qb;
+ //qbuf_peek_s(pbufq, QBF_INS_Q_IN, q_buf);
+ ret = qbufp_peek(pbufq, QBF_NINS_Q_CHECK, &q_buf);
+ if ((!ret) || (!q_buf.qbc))
+ return NULL;
+ ins = (struct dim_nins_s *)q_buf.qbc;
+ vfm = &ins->c.vfm_cp;
+
+ return vfm;
+}
+
+/* from check to used */
+struct dim_nins_s *nins_get(struct di_ch_s *pch)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_nins_s *ins;
+
+ pbufq = &pch->nin_qb;
+
+ ret = qbuf_out(pbufq, QBF_NINS_Q_CHECK, &index);
+ if (!ret)
+ return NULL;
+
+ q_buf = pbufq->pbuf[index];
+ ins = (struct dim_nins_s *)q_buf.qbc;
+
+ qbuf_in(pbufq, QBF_NINS_Q_USED, index);
+ //qbuf_dbg_checkid(pbufq, 2);
+
+ return ins;
+}
+
+/* in_used to recycle*/
+bool nins_out_some(struct di_ch_s *pch,
+ struct dim_nins_s *ins,
+ unsigned int q)
+{
+// unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->nin_qb;
+ q_buf.qbc = &ins->header;
+
+ ret = qbuf_out_some(pbufq, q, q_buf);
+ if (!ret) {
+ PR_ERR("%s:\n", __func__);
+// dbg_hd_print(&ins->header);
+// dbg_q_listid_print(pbufq);
+ }
+ //qbuf_dbg_checkid(pbufq, 3);
+
+ return ret;
+}
+
+/* in_used to recycle*/
+bool nins_used_some_to_recycle(struct di_ch_s *pch, struct dim_nins_s *ins)
+{
+// unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->nin_qb;
+ q_buf.qbc = &ins->header;
+ //qbuf_dbg_checkid(pbufq, 5);
+
+ if (ins->header.index >= DIM_NINS_NUB) {
+ PR_ERR("%s:%d:overflow\n", "nin_some", ins->header.index);
+ return false;
+ }
+ ret = qbuf_out_some(pbufq, QBF_NINS_Q_USED, q_buf);
+ if (!ret) {
+ PR_ERR("%s:\n", __func__);
+ dbg_hd_print(&ins->header);
+// dbg_q_listid_print(pbufq);
+ return false;
+ }
+ #ifdef MARK_HIS
+ PR_INF("%s:%d:0x%x\n", __func__,
+ ins->header.index,
+ ins->header.code);
+ #endif
+ ret = qbuf_in(pbufq, QBF_NINS_Q_RECYCL, ins->header.index);
+ if (!ret) {
+ PR_ERR("%s:in failed\n", __func__);
+ return false;
+ }
+ //qbuf_dbg_checkid(pbufq, 4);
+
+ return true;
+}
+
+/* from check to used */
+struct dim_nins_s *nins_move(struct di_ch_s *pch,
+ unsigned int qf,
+ unsigned int qt)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_nins_s *ins;
+
+ pbufq = &pch->nin_qb;
+ if ((qf >= pbufq->nub_que) ||
+ (qt >= pbufq->nub_que) ||
+ (qf == qt)) {
+ PR_ERR("%s:%d->%d\n", __func__, qf, qt);
+ return NULL;
+ }
+ ret = qbuf_out(pbufq, qf, &index);
+ if (!ret) {
+ PR_ERR("%s:out:%d->%d\n", __func__, qf, qt);
+ return NULL;
+ }
+
+ q_buf = pbufq->pbuf[index];
+ ins = (struct dim_nins_s *)q_buf.qbc;
+
+ qbuf_in(pbufq, qt, index);
+ qbuf_dbg_checkid(pbufq, 5);
+
+ return ins;
+}
+
+unsigned int nins_cnt_used_all(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ unsigned int len_check, len_used, len_rc;
+
+ pbufq = &pch->nin_qb;
+ len_check = qbufp_count(pbufq, QBF_NINS_Q_CHECK);
+ len_used = qbufp_count(pbufq, QBF_NINS_Q_USED);
+ len_rc = qbufp_count(pbufq, QBF_NINS_Q_RECYCL);
+
+ return len_check + len_used + len_rc;
+}
+
+unsigned int nins_cnt(struct di_ch_s *pch, unsigned int q)
+{
+ struct buf_que_s *pbufq;
+
+ pbufq = &pch->nin_qb;
+ return qbufp_count(pbufq, q);
+}
+
+void dbg_nins_log_buf(struct di_buf_s *di_buf, unsigned int dbgid)
+{
+ struct dim_nins_s *ins;
+
+ if (di_buf && di_buf->c.in) {
+ ins = (struct dim_nins_s *)di_buf->c.in;
+ } else {
+ PR_INF("no in\n");
+ return;
+ }
+
+ PR_INF("%s:%d:%d->%d,0x%x,0x%px\n", "nins",
+ dbgid, di_buf->index,
+ ins->header.index,
+ ins->header.code,
+ ins);
+}
+
+void dbg_nins_check_id(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+
+ pbufq = &pch->nin_qb;
+ qbuf_dbg_checkid(pbufq, 10);
+}
+
+static bool di_buf_clear(struct di_ch_s *pch, struct di_buf_s *di_buf);
+
+/************************************************
+ * new display
+ ************************************************/
+static const struct que_creat_s qbf_ndis_cfg_q[] = {//TST_Q_IN_NUB
+ [QBF_NDIS_Q_IDLE] = {
+ .name = "QBF_NDIS_Q_IDLE",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NDIS_Q_USED] = {
+ .name = "QBF_NDIS_Q_USED",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_NDIS_Q_DISPLAY] = {
+ .name = "QBF_NDIS_Q_DISPLAY",
+ .type = Q_T_N,
+ .lock = 1,
+ },
+#ifdef MARK_HIS
+ [QBF_NDIS_Q_BACK] = {
+ .name = "QBF_NDIS_Q_BACK",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+#endif
+ [QBF_NDIS_Q_KEEP] = {
+ .name = "QBF_NDIS_Q_KEEP",
+ .type = Q_T_N,
+ .lock = 0,
+ }
+};
+
+static const struct qbuf_creat_s qbf_ndis_cfg_qbuf = {
+ .name = "qbuf_ndis",
+ .nub_que = QBF_NDIS_Q_NUB,
+ .nub_buf = DIM_NDIS_NUB,
+ .code = CODE_NDIS,
+};
+
+void bufq_ndis_int(struct di_ch_s *pch)
+{
+ struct dim_ndis_s *dis;
+ struct buf_que_s *pbufq;
+ int i;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+
+ /* clear buf*/
+ dis = &pch->ndis_bf[0];
+ memset(dis, 0, sizeof(*dis) * DIM_NDIS_NUB);
+
+ /* set buf's header */
+ for (i = 0; i < DIM_NDIS_NUB; i++) {
+ dis = &pch->ndis_bf[i];
+
+ dis->header.code = CODE_NDIS;
+ dis->header.index = i;
+ dis->header.ch = pch->ch_id;
+ }
+
+ pbufq = &pch->ndis_qb;
+ /*clear bq */
+ memset(pbufq, 0, sizeof(*pbufq));
+
+ /* point to resource */
+ for (i = 0; i < QBF_NDIS_Q_NUB; i++)
+ pbufq->pque[i] = &pch->ndis_q[i];
+
+ for (i = 0; i < DIM_NDIS_NUB; i++)
+ pbufq->pbuf[i].qbc = &pch->ndis_bf[i].header;
+
+ qbuf_int(pbufq, &qbf_ndis_cfg_q[0], &qbf_ndis_cfg_qbuf);
+
+ /* all to idle */
+ qbuf_in_all(pbufq, QBF_NDIS_Q_IDLE);
+ PR_INF("%s:\n", __func__);
+}
+
+void bufq_ndis_exit(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+
+ PR_INF("%s:\n", __func__);
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ pbufq = &pch->ndis_qb;
+
+ qbuf_release_que(pbufq);
+}
+
+struct dim_ndis_s *ndisq_peek(struct di_ch_s *pch, unsigned int que)
+{
+// unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_ndis_s *ndis;
+
+ pbufq = &pch->ndis_qb;
+
+ ret = qbufp_peek(pbufq, que, &q_buf);
+ if (!ret)
+ return NULL;
+
+ ndis = (struct dim_ndis_s *)q_buf.qbc;
+
+ return ndis;
+}
+
+unsigned int ndis_cnt(struct di_ch_s *pch, unsigned int que)
+{
+ struct buf_que_s *pbufq;
+ unsigned int len;
+
+ pbufq = &pch->ndis_qb;
+ len = qbufp_count(pbufq, que);
+
+ return len;
+}
+
+struct dim_ndis_s *ndisq_out(struct di_ch_s *pch, unsigned int que)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_ndis_s *ndis;
+
+ pbufq = &pch->ndis_qb;
+
+ ret = qbuf_out(pbufq, que, &index);
+ if (!ret)
+ return NULL;
+
+ q_buf = pbufq->pbuf[index];
+ ndis = (struct dim_ndis_s *)q_buf.qbc;
+
+ return ndis;
+}
+
+struct dim_ndis_s *ndis_get_fromid(struct di_ch_s *pch, unsigned int idx)
+{
+ struct dim_ndis_s *ndis;
+ struct buf_que_s *pbufq;
+
+ pbufq = &pch->ndis_qb;
+ if (idx >= pbufq->nub_buf) {
+ PR_ERR("%s:ch[%d], %d, overflow\n", __func__, pch->ch_id, idx);
+ return NULL;
+ }
+
+ ndis = (struct dim_ndis_s *)pbufq->pbuf[idx].qbc;
+ dbg_nq("%s:%d\n", __func__, idx);
+
+ return ndis;
+}
+
+struct dim_ndis_s *ndis_move(struct di_ch_s *pch,
+ unsigned int qf,
+ unsigned int qt)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_ndis_s *ndis;
+
+ pbufq = &pch->ndis_qb;
+ if ((qf >= pbufq->nub_que) ||
+ (qt >= pbufq->nub_que) ||
+ (qf == qt)) {
+ PR_ERR("%s:%d->%d\n", __func__, qf, qt);
+ return NULL;
+ }
+ ret = qbuf_out(pbufq, qf, &index);
+ if (!ret) {
+ PR_ERR("%s:out:%d->%d\n", __func__, qf, qt);
+ return NULL;
+ }
+
+ q_buf = pbufq->pbuf[index];
+ ndis = (struct dim_ndis_s *)q_buf.qbc;
+
+ qbuf_in(pbufq, qt, index);
+ if (dbg_unreg_flg)
+ PR_WARN("%s:after unreg:%d->%d,%d\n", __func__, qf, qt, index);
+
+ //qbuf_dbg_checkid(pbufq, 5);
+
+ return ndis;
+}
+
+/* @ary_note: this will clear, and not used back */
+bool ndis_move_display2idle(struct di_ch_s *pch, struct dim_ndis_s *ndis)
+{
+ //unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->ndis_qb;
+
+ q_buf.qbc = &ndis->header;
+ ret = qbuf_out_some(pbufq, QBF_NDIS_Q_DISPLAY, q_buf);
+ if (!ret) {
+ PR_ERR("%s:out:%d\n", __func__, ndis->header.index);
+ return NULL;
+ }
+
+ /*clear */
+ memset(&ndis->c, 0, sizeof(ndis->c));
+
+ qbuf_in(pbufq, QBF_NDIS_Q_IDLE, ndis->header.index);
+ //qbuf_dbg_checkid(pbufq, 5);
+ dbg_nq("%s:%d\n", __func__, ndis->header.index);
+ return ret;
+}
+
+bool ndis_is_in_display(struct di_ch_s *pch, struct dim_ndis_s *ndis)
+{
+ struct buf_que_s *pbufq;
+ bool ret;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->ndis_qb;
+ q_buf.qbc = &ndis->header;
+
+ ret = qbuf_n_is_in(pbufq, QBF_NDIS_Q_DISPLAY, q_buf);
+ return ret;
+}
+
+bool ndis_is_in_keep(struct di_ch_s *pch, struct dim_ndis_s *ndis)
+{
+ struct buf_que_s *pbufq;
+ bool ret;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->ndis_qb;
+ q_buf.qbc = &ndis->header;
+
+ ret = qbuf_n_is_in(pbufq, QBF_NDIS_Q_KEEP, q_buf);
+ return ret;
+}
+
+bool ndis_move_keep2idle(struct di_ch_s *pch, struct dim_ndis_s *ndis)
+{
+ //unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->ndis_qb;
+
+ q_buf.qbc = &ndis->header;
+ ret = qbuf_out_some(pbufq, QBF_NDIS_Q_KEEP, q_buf);
+ if (!ret) {
+ PR_ERR("%s:out:%d\n", __func__, ndis->header.index);
+ return NULL;
+ }
+
+ /*clear */
+ memset(&ndis->c, 0, sizeof(ndis->c));
+
+ qbuf_in(pbufq, QBF_NDIS_Q_IDLE, ndis->header.index);
+ //qbuf_dbg_checkid(pbufq, 5);
+ PR_INF("%s:%d\n", __func__, ndis->header.index);
+ return ret;
+}
+
+#ifdef MARK_HIS//no used
+/* */
+void ndis_back2_idle(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ int i;
+ struct dim_ndis_s *ndis;
+ unsigned int len;
+ bool ret;
+// unsigned int index;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->ndis_qb;
+
+ len = qbufp_count(pbufq, QBF_NDIS_Q_BACK);
+ if (!len)
+ return;
+
+ for (i = 0; i < len; i++) {
+ /* clear */
+ ndis = ndisq_out(pch, QBF_NDIS_Q_BACK);
+ if (!ndis) {
+ PR_ERR("%s:no dis[%d]\n", __func__, i);
+ continue;
+ }
+ q_buf.qbc = &ndis->header;
+ ret = qbuf_out_some(pbufq, QBF_NDIS_Q_DISPLAY, q_buf);
+ if (!ret)
+ PR_ERR("%s, o some [%d]\n", __func__, i);
+ qbuf_in(pbufq, QBF_NDIS_Q_IDLE, ndis->header.index);
+ }
+}
+#endif
+/* this keep is tmp will clear when unreg */
+unsigned int ndis_2keep(struct di_ch_s *pch,
+ struct dim_mm_blk_s **blk,
+ unsigned int len_max,
+ unsigned int disable_mirror)
+{
+ struct buf_que_s *pbufq;
+ int i;
+ struct dim_ndis_s *ndis;
+ unsigned int len;
+// unsigned int mask;
+ bool ret;
+ unsigned int index;
+ struct di_buf_s *p;
+ unsigned int ch;
+ unsigned int cnt = 0;
+
+ pbufq = &pch->ndis_qb;
+
+ len = qbufp_count(pbufq, QBF_NDIS_Q_DISPLAY);
+
+ ch = pch->ch_id;
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ret = qbuf_out(pbufq, QBF_NDIS_Q_DISPLAY, &index);
+ if (!ret) {
+ PR_ERR("%s:out display [%d]\n", __func__, i);
+ continue;
+ }
+ //PR_INF("%s:out from display %d\n", __func__, index);
+ ndis = (struct dim_ndis_s *)pbufq->pbuf[index].qbc;
+ p = ndis->c.di_buf;
+ ndis->c.blk = p->blk_buf;
+ ndis->c.di_buf = NULL;
+
+ if (!p->blk_buf) {
+ PR_ERR("%s:no blk:%d\n", __func__, p->index);
+ continue;
+ }
+ //blk[i] = p->blk_buf;
+ /* dec vf keep */
+ if (p->in_buf) {
+ if (p->in_buf->c.in) {
+ //nins_used_some_to_recycle(pch,
+ //(struct dim_nins_s*)p->in_buf->c.in);
+ p->in_buf->c.in = NULL;
+ }
+
+ queue_in(ch, p->in_buf, QUEUE_RECYCLE);
+ p->in_buf = NULL;
+ }
+
+ /* @ary_note: clear di_buf */
+ di_buf_clear(pch, p);
+ di_que_in(pch->ch_id, QUE_PST_NO_BUF, p);
+
+ //memset(&ndis->c, 0, sizeof(ndis->c));
+ //PR_INF("%s:to keep %d\n", __func__,
+ // ndis->header.index);
+ if (disable_mirror) {
+ /* clear */
+ memset(&ndis->c, 0, sizeof(ndis->c));
+ ndis->etype = EDIM_NIN_TYPE_NONE;
+ qbuf_in(pbufq, QBF_NDIS_Q_IDLE,
+ ndis->header.index);
+ } else {
+ ndis_dbg_print2(ndis, "to keep");
+ qbuf_in(pbufq, QBF_NDIS_Q_KEEP,
+ ndis->header.index);
+ cnt++;
+ }
+ }
+ }
+ len = qbufp_count(pbufq, QBF_NDIS_Q_KEEP);
+
+ if (!len)
+ return 0;
+
+ if (len > len_max)
+ len = len_max;
+ qbufp_list(pbufq, QBF_NDIS_Q_KEEP);
+ cnt = 0;
+ for (i = 0; i < len; i++) {
+ if (pbufq->list_id[i] >= pbufq->nub_buf) {
+ PR_ERR("%s:cnt list err:%d,%d\n", __func__,
+ len, i);
+ break;
+ }
+ index = pbufq->list_id[i];
+ ndis = (struct dim_ndis_s *)pbufq->pbuf[index].qbc;
+ if (!ndis->c.blk) {
+ PR_ERR("%s:no blk %d, %d\n", __func__, len, i);
+ continue;
+ }
+
+ blk[i] = ndis->c.blk;
+ cnt++;
+ }
+
+ PR_INF("%s:cnt[%d]\n", __func__, cnt);
+ return cnt;
+}
+
+void bufq_ndis_unreg(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ int i;
+ struct dim_ndis_s *ndis;
+ unsigned int len;
+// union q_buf_u q_buf;
+// bool ret;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ pbufq = &pch->ndis_qb;
+
+ /* clear used */
+ len = qbufp_count(pbufq, QBF_NDIS_Q_USED);
+ if (len) {
+ for (i = 0; i < len; i++) {
+ ndis = ndisq_out(pch, QBF_NDIS_Q_USED);
+ if (!ndis) {
+ PR_ERR("%s:no dis[%d]\n", __func__, i);
+ continue;
+ }
+ /* clear */
+ memset(&ndis->c, 0, sizeof(ndis->c));
+ ndis->etype = EDIM_NIN_TYPE_NONE;
+ qbuf_in(pbufq, QBF_NDIS_Q_IDLE, ndis->header.index);
+ PR_INF("%s:used 2 idle %d\n", __func__,
+ ndis->header.index);
+ }
+ }
+ //dbg_unreg_flg = 1;
+ PR_INF("%s:%d\n", __func__, len);
+
+ /* check keep */
+
+ //qbuf_reset(pbufq);
+ /* all to idle */
+ //qbuf_in_all(pbufq, QBF_NDIS_Q_IDLE);
+#ifdef MARK_HIS
+ for (i = 0; i < DIM_NDIS_NUB; i++) {
+ ndis = &pch->ndis_bf[i];
+ /* set etype */
+ ndis->etype = EDIM_NIN_TYPE_NONE;
+ memset(&ndis->c, 0, sizeof(ndis->c));
+ }
+#endif
+ //qbuf_dbg_checkid(pbufq, 1);
+}
+
+void ndis_dbg_content(struct seq_file *s, struct dim_ndis_s *ndis)
+{
+ if (!ndis) {
+ seq_printf(s, "\t%s\n", "no_ndis");
+ return;
+ }
+ if (ndis->c.di_buf) {
+ seq_printf(s, "\t%s\n", "have di_buf");
+ seq_printf(s, "\t\t type[%d] index[%d]\n",
+ ndis->c.di_buf->type, ndis->c.di_buf->index);
+ } else {
+ seq_printf(s, "\t%s\n", "no di_buf");
+ }
+ if (ndis->c.blk) {
+ seq_printf(s, "\t%s\n", "have blk");
+ seq_printf(s, "\t\t index[%d]\n",
+ ndis->c.blk->header.index);
+ } else {
+ seq_printf(s, "\t%s\n", "no blk");
+ }
+}
+
+void ndis_dbg_print2(struct dim_ndis_s *ndis, char *name)
+{
+ struct dim_pat_s *pat_buf;//dbg only
+
+ if (!ndis) {
+ PR_INF("%s:no ndis\n", __func__);
+ return;
+ }
+ PR_INF("%s:%d\n", name, ndis->header.index);
+ if (ndis->c.di_buf) {
+ PR_INF("di_buf:t[%d]:%d\n",
+ ndis->c.di_buf->type,
+ ndis->c.di_buf->index);
+ }
+ if (ndis->c.blk) {
+ PR_INF("blk:%d\n", ndis->c.blk->header.index);
+ if (ndis->c.blk->pat_buf) {
+ pat_buf = ndis->c.blk->pat_buf;
+ PR_INF("pat:%d\n", pat_buf->header.index);
+ }
+ }
+}
+
+void ndis_dbg_qbuf_detail(struct seq_file *s, struct di_ch_s *pch)
+{
+ unsigned int j;
+ union q_buf_u pbuf;
+ //struct qs_buf_s *header;
+ struct buf_que_s *pqbuf;
+ struct dim_ndis_s *ndis;
+ char *splt = "---------------------------";
+
+ pqbuf = &pch->ndis_qb;
+
+ seq_printf(s, "%s:\n", pqbuf->name);
+ for (j = 0; j < pqbuf->nub_buf; j++) {
+ pbuf = pqbuf->pbuf[j];
+ if (!pbuf.qbc)
+ break;
+ //header = pbuf->qbc;
+ dbg_hd(s, pbuf.qbc);
+ ndis = (struct dim_ndis_s *)pbuf.qbc;
+ ndis_dbg_content(s, ndis);
+ seq_printf(s, "%s\n", splt);
+ }
+}
+
+void ndrd_int(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_ready;
+
+ qfp_int(pq, "np_ready", 0); /* unlock */
+
+ pq = &pch->ndis_que_kback;
+ qfp_int(pq, "np_kback", 0); /* unlock */
+}
+
+void ndrd_exit(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_ready;
+ qfp_release(pq);
+
+ pq = &pch->ndis_que_kback;
+ qfp_release(pq);
+}
+
+void ndrd_reset(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_ready;
+ pq->ops.reset(NULL, pq);
+}
+
+/* vfm is vframe or di_buffer */
+void ndrd_qin(struct di_ch_s *pch, void *vfm)
+{
+ struct qs_cls_s *pq;
+ union q_buf_u ubuf;
+
+ if (!vfm)
+ return;
+ pq = &pch->ndis_que_ready;
+ ubuf.qbc = (struct qs_buf_s *)vfm;
+ pq->ops.in(NULL, pq, ubuf);
+}
+
+/* @ary_note: only one caller: vfm peek */
+struct vframe_s *ndrd_qpeekvfm(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct vframe_s *vfm;
+
+ pq = &pch->ndis_que_ready;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ vfm = (struct vframe_s *)pbuf.qbc;
+ return vfm;
+}
+
+/* @ary_note: debug ? */
+struct di_buf_s *ndrd_qpeekbuf(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct vframe_s *vfm;
+ struct dim_ndis_s *ndis;
+ struct di_buf_s *di_buf;
+ struct di_buffer *buffer;
+
+ pq = &pch->ndis_que_ready;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ if (dip_itf_is_vfm(pch)) {
+ vfm = (struct vframe_s *)pbuf.qbc;
+ if (!vfm->private_data)
+ return NULL;
+ ndis = (struct dim_ndis_s *)vfm->private_data;
+ if (!ndis->c.di_buf)
+ return NULL;
+
+ di_buf = ndis->c.di_buf;
+ } else {
+ buffer = (struct di_buffer *)pbuf.qbc;
+ ndis = (struct dim_ndis_s *)buffer->private_data;
+ if (!ndis || !ndis->c.di_buf)
+ return NULL;
+ di_buf = ndis->c.di_buf;
+ }
+
+ return di_buf;
+}
+
+/* */
+struct vframe_s *ndrd_qout(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct vframe_s *vfm;
+
+ pq = &pch->ndis_que_ready;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ ret = pq->ops.out(NULL, pq, &pbuf);
+
+ vfm = (struct vframe_s *)pbuf.qbc;
+ return vfm;
+}
+
+void dip_itf_ndrd_ins_m2_out(struct di_ch_s *pch)
+{
+ unsigned int cnt_ready;
+ int i;
+ struct qs_cls_s *pq;
+ union q_buf_u pbuf;
+ bool ret;
+ struct di_buffer *buffer;
+ struct dim_ndis_s *ndis1, *ndis2;
+
+ if (dip_itf_is_vfm(pch))
+ return;
+ cnt_ready = ndrd_cnt(pch);
+ if (!cnt_ready)
+ return;
+
+ pq = &pch->ndis_que_ready;
+ for (i = 0; i < cnt_ready; i++) {
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret) {
+ //return NULL;
+ PR_ERR("%s:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ ret = pq->ops.out(NULL, pq, &pbuf);
+ if ((!ret) || (!pbuf.qbc)) {
+ //return NULL;
+ PR_ERR("%s:out:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ buffer = (struct di_buffer *)pbuf.qbc;
+ ndis1 = (struct dim_ndis_s *)buffer->private_data;
+ if (ndis1) {
+ ndis2 = ndis_move(pch, QBF_NDIS_Q_USED,
+ QBF_NDIS_Q_DISPLAY);
+ if (ndis1 != ndis2)
+ PR_ERR("%s:\n", __func__);
+ }
+ #ifdef MARK_HIS
+ if (dip_itf_is_ins_exbuf(pch)) {
+ buffer->private_data = NULL;
+ ndis1->c.pbuff = NULL;
+ task_send_cmd2(pch->ch_id,
+ LCMD2(ECMD_RL_KEEP,
+ pch->ch_id,
+ ndis1->header.index));
+ }
+ #endif
+ didbg_vframe_out_save(pch->ch_id, buffer->vf, 1);
+ pch->itf.u.dinst.parm.ops.fill_output_done(buffer);
+ sum_pst_g_inc(pch->ch_id);
+ }
+}
+
+void dip_itf_ndrd_ins_m1_out(struct di_ch_s *pch)
+{
+ unsigned int cnt_ready;
+ int i;
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct di_buffer *buffer;
+
+ if (!dip_itf_is_ins_exbuf(pch))
+ return;
+ cnt_ready = ndrd_cnt(pch);
+ if (!cnt_ready)
+ return;
+
+ pq = &pch->ndis_que_ready;
+ for (i = 0; i < cnt_ready; i++) {
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret) {
+ //return NULL;
+ PR_ERR("%s:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ ret = pq->ops.out(NULL, pq, &pbuf);
+ if ((!ret) || (!pbuf.qbc)) {
+ //return NULL;
+ PR_ERR("%s:out:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ buffer = (struct di_buffer *)pbuf.qbc;
+ didbg_vframe_out_save(pch->ch_id, buffer->vf, 2);
+ pch->itf.u.dinst.parm.ops.fill_output_done(buffer);
+ sum_pst_g_inc(pch->ch_id);
+ }
+}
+
+#ifdef MARK_HIS
+void dip_itf_ndrd_ins_m1_out(struct di_ch_s *pch)
+{
+ unsigned int cnt_ready;
+ int i;
+ struct qs_cls_s *pq;
+ union q_buf_u pbuf;
+ bool ret;
+ struct di_buffer *buffer;
+ struct dim_ndis_s *ndis1, *ndis2;
+ struct di_buf_s *di_buf;
+
+ if (dip_itf_is_vfm(pch))
+ return;
+ cnt_ready = ndrd_cnt(pch);
+ if (!cnt_ready)
+ return;
+
+ pq = &pch->ndis_que_ready;
+ for (i = 0; i < cnt_ready; i++) {
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret) {
+ //return NULL;
+ PR_ERR("%s:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ ret = pq->ops.out(NULL, pq, &pbuf);
+ if ((!ret) || (!pbuf.qbc)) {
+ //return NULL;
+ PR_ERR("%s:out:%d:%d\n", __func__, cnt_ready, i);
+ break;
+ }
+ buffer = (struct di_buffer *)pbuf.qbc;
+ ndis1 = (struct dim_ndis_s *)buffer->private_data;
+ if (ndis1) {
+ buffer->private_data = NULL;
+ //di_buf:
+ di_buf = ndis1->c.di_buf;
+ if (di_buf) {
+ di_buf_clear(pch, di_buf);
+ di_que_in(pch->ch_id,
+ QUE_PST_NO_BUF_WAIT, di_buf);
+ }
+ ndis2 = ndis_move(pch,
+ QBF_NDIS_Q_USED, QBF_NDIS_Q_IDLE);
+ if (ndis1 != ndis2)
+ PR_ERR("%s:\n", __func__);
+ }
+ pch->itf.u.dinst.parm.ops.fill_output_done(buffer);
+ sum_pst_g_inc(pch->ch_id);
+ }
+}
+#endif
+unsigned int ndrd_cnt(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_ready;
+
+ return pq->ops.count(NULL, pq);
+}
+
+/* crash ?? */
+void ndrd_dbg_list_buf(struct seq_file *s, struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ void *list[MAX_FIFO_SIZE];
+ unsigned int len;
+ int i;
+ struct dim_ndis_s *ndis;
+ struct di_buf_s *p;
+
+ pq = &pch->ndis_que_ready;
+
+ len = qfp_list(pq, MAX_FIFO_SIZE, &list[0]);
+ if (!len) {
+ seq_printf(s, "%s:non\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < len; i++) {
+ ndis = (struct dim_ndis_s *)list[i];
+ ndis_dbg_content(s, ndis);
+ if (ndis->c.di_buf) {
+ p = ndis->c.di_buf;
+ print_di_buf_seq(p, 2, s);
+ print_di_buf_seq(p->di_buf[0], 1, s);
+ print_di_buf_seq(p->di_buf[1], 1, s);
+ }
+ }
+}
+
+/****/
+/* @ary_note keep back que */
+
+void ndkb_reset(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_kback;
+ pq->ops.reset(NULL, pq);
+}
+
+void ndkb_qin(struct di_ch_s *pch, struct dim_ndis_s *ndis)
+{
+ struct qs_cls_s *pq;
+ union q_buf_u ubuf;
+
+ if (!ndis)
+ return;
+ pq = &pch->ndis_que_kback;
+ ubuf.qbc = &ndis->header;
+ pq->ops.in(NULL, pq, ubuf);
+ PR_INF("%s:%d\n", __func__, ndis->header.index);
+}
+
+void ndkb_qin_byidx(struct di_ch_s *pch, unsigned int idx)
+{
+ struct qs_cls_s *pq;
+ union q_buf_u ubuf;
+ struct buf_que_s *pbufq;
+// int i;
+ struct dim_ndis_s *ndis;
+
+ pbufq = &pch->ndis_qb;
+ if (idx >= pbufq->nub_buf) {
+ PR_ERR("%s:overflow %d\n", __func__, idx);
+ return;
+ }
+ ndis = (struct dim_ndis_s *)pbufq->pbuf[idx].qbc;
+
+ pq = &pch->ndis_que_kback;
+ ubuf.qbc = &ndis->header;
+ pq->ops.in(NULL, pq, ubuf);
+ PR_INF("%s:%d\n", __func__, ndis->header.index);
+}
+
+struct dim_ndis_s *ndkb_qout(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct dim_ndis_s *ndis;
+
+ pq = &pch->ndis_que_kback;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ ret = pq->ops.out(NULL, pq, &pbuf);
+
+ ndis = (struct dim_ndis_s *)pbuf.qbc;
+ PR_INF("%s:%d\n", __func__, ndis->header.index);
+ return ndis;
+}
+
+unsigned int ndkb_cnt(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->ndis_que_kback;
+ return pq->ops.count(NULL, pq);
+}
+
+void ndkb_dbg_list(struct seq_file *s, struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ void *list[MAX_FIFO_SIZE];
+ unsigned int len;
+ int i;
+ struct dim_ndis_s *ndis;
+
+ pq = &pch->ndis_que_kback;
+
+ len = qfp_list(pq, MAX_FIFO_SIZE, &list[0]);
+ if (!len) {
+ seq_printf(s, "%s:non\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < len; i++) {
+ ndis = (struct dim_ndis_s *)list[i];
+ ndis_dbg_content(s, ndis);
+ }
+}
+
+void npst_int(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->npst_que;
+
+ qfp_int(pq, "npst", 0); /* unlock */
+}
+
+void npst_exit(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->npst_que;
+ qfp_release(pq);
+}
+
+void npst_reset(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->npst_que;
+ pq->ops.reset(NULL, pq);
+}
+
+/* */
+void npst_qin(struct di_ch_s *pch, void *buffer)
+{
+ struct qs_cls_s *pq;
+ union q_buf_u ubuf;
+ bool ret;
+
+ if (!buffer) {
+ PR_ERR("%s:no buffer\n", __func__);
+ return;
+ }
+ pq = &pch->npst_que;
+ ubuf.qbc = (struct qs_buf_s *)buffer;
+ ret = pq->ops.in(NULL, pq, ubuf);
+ if (!ret)
+ PR_ERR("%s:in\n", __func__);
+}
+
+/* @ary_note: only one caller: vfm peek */
+struct di_buffer *npst_qpeek(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct di_buffer *buffer;
+
+ pq = &pch->npst_que;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ buffer = (struct di_buffer *)pbuf.qbc;
+ return buffer;
+}
+
+struct di_buffer *npst_qout(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct di_buffer *buffer;
+
+ pq = &pch->npst_que;
+
+ ret = pq->ops.peek(NULL, pq, &pbuf);
+ if (!ret)
+ return NULL;
+ ret = pq->ops.out(NULL, pq, &pbuf);
+
+ buffer = (struct di_buffer *)pbuf.qbc;
+ return buffer;
+}
+
+unsigned int npst_cnt(struct di_ch_s *pch)
+{
+ struct qs_cls_s *pq;
+
+ pq = &pch->npst_que;
+
+ return pq->ops.count(NULL, pq);
+}
+
+void dbg_log_pst_buffer(struct di_buf_s *di_buf, unsigned int dbgid)
+{
+// struct di_buffer *buffer;
+
+ PR_INF("log_pst:%d:di_buf[%d],cvsw[%d]\n",
+ dbgid, di_buf->flg_null,
+ di_buf->canvas_width[0]);
+ if (di_buf->c.buffer)
+ PR_INF("log_pst:%d:%px\n", dbgid, di_buf->c.buffer);
+ else
+ PR_INF("log_pst:%d:no\n", dbgid);
+}
+
+static bool di_buf_clear(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ struct vframe_s *vfm;
+ int index;
+ int type, queue_index;
+ unsigned int canvas_config_flag;
+ unsigned int canvas_height;
+ unsigned int canvas_width[3];/* nr/mtn/mv */
+ unsigned int channel;
+ int i;
+
+ /* back */
+ vfm = di_buf->vframe;
+ index = di_buf->index;
+ type = di_buf->type;
+ canvas_config_flag = di_buf->canvas_config_flag;
+ canvas_height = di_buf->canvas_height;
+ channel = di_buf->channel;
+ queue_index = di_buf->queue_index;
+// is_i = di_buf->buf_is_i;
+ for (i = 0; i < 3; i++)
+ canvas_width[i] = di_buf->canvas_width[i];
+
+ memset(di_buf, 0, sizeof(*di_buf));
+ di_buf->vframe = vfm;
+ di_buf->index = index;
+ di_buf->type = type;
+ di_buf->canvas_config_flag = canvas_config_flag;
+
+ di_buf->canvas_height = canvas_height;
+ di_buf->channel = channel;
+ di_buf->queue_index = queue_index;
+// di_buf->buf_is_i = is_i;
+ for (i = 0; i < 3; i++)
+ di_buf->canvas_width[i] = canvas_width[i];
+
+ return true;
+}
+
+static bool ndis_fill_ready_bypass(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ struct dim_nins_s *nins;
+ void *in_ori;
+ struct di_buf_s *ibuf;
+// struct dim_nins_s *nins =NULL;
+ struct di_buffer *buffer;
+
+ if (di_buf->is_nbypass) {
+ //check:
+ if (di_buf->type != VFRAME_TYPE_POST) {
+ PR_ERR("%s:bypass not post ?\n", __func__);
+ return true;
+ }
+ ibuf = di_buf->di_buf_dup_p[0];
+ if (!ibuf) {
+ PR_ERR("%s:bypass no in ?\n", __func__);
+ return true;
+ }
+ nins = (struct dim_nins_s *)ibuf->c.in;
+ if (!nins) {
+ PR_ERR("%s:no in ori ?\n", __func__);
+ return true;
+ }
+ in_ori = nins->c.ori;
+
+ /* recycle */
+ nins->c.ori = NULL;
+ nins_used_some_to_recycle(pch, nins);
+
+ ibuf->c.in = NULL;
+ //di_buf->queue_index = -1;
+ //di_que_in(pch->ch_id, QUE_POST_BACK, di_buf);
+ di_buf_clear(pch, di_buf);
+ di_que_in(pch->ch_id, QUE_PST_NO_BUF, di_buf);
+ queue_in(pch->ch_id, ibuf, QUEUE_RECYCLE);
+
+ /* to ready buffer */
+ if (dip_itf_is_ins(pch)) {
+ /* need mark bypass flg*/
+ buffer = (struct di_buffer *)in_ori;
+ buffer->flag |= DI_FLAG_BUF_BY_PASS;
+ }
+
+ ndrd_qin(pch, in_ori);
+ return true;
+ }
+ return false;
+}
+
+static bool ndis_fill_ready_pst(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ struct dim_ndis_s *dis;
+ struct di_buffer *buffer;
+
+ //dis = ndisq_peek(pch, QBF_NDIS_Q_IDLE);
+ dis = ndis_move(pch, QBF_NDIS_Q_IDLE, QBF_NDIS_Q_USED);
+ if (!dis) {
+ PR_ERR("%s:no idle\n", __func__);
+ return false;
+ }
+ /* clear dis */
+ memset(&dis->c, 0, sizeof(dis->c));
+ dis->etype = pch->itf.etype;
+
+ atomic_set(&di_buf->di_cnt, 1);
+ dis->c.di_buf = di_buf;
+ if (dis->etype == EDIM_NIN_TYPE_VFM) {
+ memcpy(&dis->c.vfm, di_buf->vframe, sizeof(dis->c.vfm));
+ dis->c.vfm.private_data = dis;
+ if (di_buf->is_bypass_pst) {
+ PR_INF("%s:vfm:%px,t:0x%x\n",
+ __func__, &dis->c.vfm, dis->c.vfm.type);
+ }
+ /* to ready buffer */
+ ndrd_qin(pch, &dis->c.vfm);
+ } else {
+ /* @ary_note: only for new_interface mode self buff */
+ if (dip_itf_is_ins_lbuf(pch)) {
+ //PR_INF("%s:lbuf\n", __func__);
+ /*int dis's buffer*/
+ dis->c.dbuff.mng.ch = pch->ch_id;
+ dis->c.dbuff.mng.code = CODE_INS_LBF;
+ dis->c.dbuff.mng.index = dis->header.index;
+ /* */
+ memcpy(&dis->c.vfm, di_buf->vframe, sizeof(dis->c.vfm));
+ dis->c.dbuff.vf = &dis->c.vfm;
+ dis->c.dbuff.private_data = dis;
+ dis->c.dbuff.caller_data =
+ pch->itf.u.dinst.parm.caller_data;
+ if (di_buf->c.src_is_i)
+ dis->c.dbuff.flag |= DI_FLAG_I;
+ else
+ dis->c.dbuff.flag |= DI_FLAG_P;
+ dis->c.dbuff.crcout = di_buf->datacrc;
+ //dbg_post_ref("00%s: %d\n", __func__, di_buf->datacrc);
+ //dbg_post_ref("fill p= 0x%p\n",di_buf);
+ ndrd_qin(pch, &dis->c.dbuff);
+ dim_tr_ops.post_get(dis->c.dbuff.vf->index_disp);
+ } else {
+ PR_INF("%s:ext buf\n", __func__);
+ dis->c.pbuff = di_buf->c.buffer;
+ if (!dis->c.pbuff) {
+ PR_ERR("%s:no out buffer\n", __func__);
+ return false;
+ }
+ di_buf->c.buffer = NULL;
+ buffer = dis->c.pbuff;
+ if (!buffer->vf) {
+ PR_WARN("%s:no buffer vf\n", __func__);
+ return false;
+ }
+ memcpy(dis->c.pbuff->vf,
+ di_buf->vframe, sizeof(*buffer->vf));
+ //memcpy(&dis->c.pbuff->vf,
+ //di_buf->vframe, sizeof(*dis->c.pbuff->vf));
+ dis->c.pbuff->private_data = dis;
+ dis->c.pbuff->caller_data =
+ pch->itf.u.dinst.parm.caller_data;
+ //dbg_post_ref("%s: %d\n", __func__, di_buf->datacrc);
+ dis->c.dbuff.crcout = di_buf->datacrc;
+ ndrd_qin(pch, &dis->c.pbuff);
+ }
+ }
+ return true;
+}
+
+bool ndis_fill_ready(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ bool ret;
+ struct dim_itf_s *itf;
+ struct dev_vfm_s *pvfmc;
+
+ ret = ndis_fill_ready_bypass(pch, di_buf);
+
+ if (!ret)
+ ret = ndis_fill_ready_pst(pch, di_buf);
+
+ itf = &pch->itf;
+ if (itf->etype == EDIM_NIN_TYPE_VFM) {
+ pvfmc = &itf->u.dvfmc;
+ if (pvfmc->vf_m_fill_ready)
+ pvfmc->vf_m_fill_ready(pch);
+ }
+
+ return true;
+}
+
+static bool ndrd_m1_fill_ready_bypass(struct di_ch_s *pch,
+ struct di_buf_s *di_buf)
+{
+ struct di_buffer *buffer_in, *buffer_o;
+ struct di_buf_s *buf_pst;
+ struct di_buf_s *ibuf;
+ struct dim_nins_s *nins;
+ //void *in_ori;
+ struct vframe_s *dec_vfm;
+
+ if (!di_buf->is_nbypass)
+ return false;
+ //check:
+ if (di_buf->type != VFRAME_TYPE_POST) {
+ PR_ERR("%s:bypass not post ?\n", __func__);
+ return true;
+ }
+ ibuf = di_buf->di_buf_dup_p[0];
+ if (!ibuf) {
+ PR_ERR("%s:bypass no in ?\n", __func__);
+ return true;
+ }
+ nins = (struct dim_nins_s *)ibuf->c.in;
+ if (!nins) {
+ PR_ERR("%s:no in ori ?\n", __func__);
+ return true;
+ }
+ /* get out buffer */
+ buf_pst = di_que_out_to_di_buf(pch->ch_id, QUE_POST_FREE);
+ if (!buf_pst) {
+ PR_ERR("%s:no post free\n", __func__);
+ return true;
+ }
+
+ buffer_o = buf_pst->c.buffer;
+ if (!buffer_o) {
+ PR_ERR("%s:no buffer_o\n", __func__);
+ return true;
+ }
+
+ buffer_in = (struct di_buffer *)nins->c.ori;
+ buffer_in->flag |= DI_FLAG_BUF_BY_PASS;
+ dec_vfm = buffer_in->vf;
+ /* recycle nins */
+ //no need nins->c.ori = NULL;
+ //nins_used_some_to_recycle(pch, nins);
+
+ //ibuf->c.in = NULL;
+ queue_in(pch->ch_id, ibuf, QUEUE_RECYCLE);
+
+ di_buf_clear(pch, di_buf);
+ di_que_in(pch->ch_id, QUE_PST_NO_BUF, di_buf);
+ di_buf_clear(pch, buf_pst);
+ di_que_in(pch->ch_id, QUE_PST_NO_BUF_WAIT, buf_pst);
+
+ buffer_o->vf->vf_ext = dec_vfm;
+ if (!dec_vfm)
+ dbg_bypass("%s:no in vfm\n", __func__);
+ else
+ dim_print("%s:vfm:0x%px, %d\n", __func__,
+ dec_vfm, dec_vfm->index);
+
+ buffer_o->flag |= DI_FLAG_BUF_BY_PASS;
+ if (di_buf->is_eos)
+ buffer_o->flag |= DI_FLAG_EOS;
+
+ ndrd_qin(pch, buffer_o);
+
+ return true;
+}
+
+/* @ary_note: use exbuf only */
+static bool ndrd_m1_fill_ready_pst(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ struct di_buffer *buffer;
+ struct canvas_config_s *cvp_ori, *cvp_di;
+
+ if (!dip_itf_is_ins_exbuf(pch))
+ return false;
+ if (!di_buf->c.buffer) {
+ PR_WARN("%s:no buffer\n", __func__);
+ return false;
+ }
+ buffer = di_buf->c.buffer;
+ if (!buffer->vf) {
+ PR_WARN("%s:no buffer vf\n", __func__);
+ return false;
+ }
+ di_buf->c.buffer = NULL;
+ cvp_di = &di_buf->vframe->canvas0_config[0];
+ cvp_ori = &buffer->vf->canvas0_config[0];
+
+ if (cvp_di->phy_addr != cvp_ori->phy_addr) {
+ #ifdef CVS_UINT
+ PR_ERR("%s:0x%x->0x%x\n", __func__,
+ cvp_ori->phy_addr, cvp_di->phy_addr);
+ #else
+ PR_ERR("%s:0x%lx->0x%lx\n", __func__,
+ cvp_ori->phy_addr, cvp_di->phy_addr);
+ #endif
+ return false;
+ }
+ memcpy(buffer->vf, di_buf->vframe, sizeof(*buffer->vf));
+ buffer->caller_data = pch->itf.u.dinst.parm.caller_data;
+ if (di_buf->c.src_is_i)
+ buffer->flag |= DI_FLAG_I;
+ else
+ buffer->flag |= DI_FLAG_P;
+ buffer->crcout = di_buf->datacrc;
+ dbg_post_ref("%s: %d\n", __func__, di_buf->datacrc);
+ di_buf_clear(pch, di_buf);
+ di_que_in(pch->ch_id, QUE_PST_NO_BUF_WAIT, di_buf);
+ ndrd_qin(pch, buffer);
+ dim_tr_ops.post_get(buffer->vf->index_disp);
+ return true;
+}
+
+bool ndrd_m1_fill_ready(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ if (!dip_itf_is_ins_exbuf(pch))
+ return false;
+
+ if (ndrd_m1_fill_ready_bypass(pch, di_buf))
+ return true;
+ ndrd_m1_fill_ready_pst(pch, di_buf);
+
+ return true;
+}
+
+/******************************************
+ * new interface
+ *****************************************/
+static void dip_itf_prob(struct di_ch_s *pch)
+{
+ struct dim_itf_s *itf;
+
+ if (!pch)
+ return;
+ itf = &pch->itf;
+ mutex_init(&itf->lock_reg);
+}
+
+void dip_itf_vf_op_polling(struct di_ch_s *pch)
+{
+ struct dev_vfm_s *vfmc;
+
+ if (!pch || (pch->itf.etype != EDIM_NIN_TYPE_VFM))
+ return;
+
+ vfmc = &pch->itf.u.dvfmc;
+ vfmc->vf_m_fill_polling(pch);
+}
+
+void dip_itf_back_input(struct di_ch_s *pch)
+{
+ if ((!pch) ||
+ (!pch->itf.opins_m_back_in))
+ return;
+
+ pch->itf.opins_m_back_in(pch);
+}
+
+bool dip_itf_is_vfm(struct di_ch_s *pch)
+{
+ return (pch->itf.etype == EDIM_NIN_TYPE_VFM) ? true : false;
+}
+
+bool dip_itf_is_ins(struct di_ch_s *pch)
+{
+ return (pch->itf.etype == EDIM_NIN_TYPE_INS) ? true : false;
+}
+
+bool dip_itf_is_ins_lbuf(struct di_ch_s *pch)
+{
+ bool ret = false;
+
+ if ((pch->itf.etype == EDIM_NIN_TYPE_INS) &&
+ (pch->itf.tmode == EDIM_TMODE_3_PW_LOCAL))
+ ret = true;
+
+ return ret;
+}
+
+bool dip_itf_is_o_linear(struct di_ch_s *pch)
+{
+ bool ret = false;
+
+ if (dip_itf_is_ins(pch)) {
+ if (pch->itf.u.dinst.parm.output_format & DI_OUTPUT_LINEAR)
+ ret = true;
+ }
+
+ if (dim_dbg_dec21 & 0x100)
+ ret = true;
+ return ret;
+}
+
+void dbg_itf_tmode(struct di_ch_s *pch, unsigned int pos)
+{
+ PR_INF("%s:ch[%d]:%d:%d\n", __func__,
+ pch->ch_id, pos, pch->itf.tmode);
+}
+
+bool dip_itf_is_ins_exbuf(struct di_ch_s *pch)
+{
+ bool ret = false;
+
+ if ((pch->itf.etype == EDIM_NIN_TYPE_INS) &&
+ (pch->itf.tmode == EDIM_TMODE_2_PW_OUT))
+ ret = true;
+ return ret;
+}
+
+struct dev_vfm_s *dip_itf_vf_sop(struct di_ch_s *pch)
+{
+ if (pch->itf.etype != EDIM_NIN_TYPE_VFM)
+ return NULL;
+ return &pch->itf.u.dvfmc;
+}
+
+void set_bypass2_complete(unsigned int ch, bool on)
+{
+ struct di_ch_s *pch;
+
+ pch = get_chdata(ch);
+
+ //set_bypass_complete(pvfm, on);
+ if (on)
+ pch->itf.bypass_complete = true;
+ else
+ pch->itf.bypass_complete = false;
+}
+
+bool is_bypss2_complete(unsigned int ch)
+{
+ struct di_ch_s *pch;
+
+ pch = get_chdata(ch);
+
+ return pch->itf.bypass_complete;
+}
+
/******************************************
* pq ops
*****************************************/
/* hw l1 ops*/
if (IS_IC_EF(ic_id, SC2)) {
- get_datal()->hop_l1 = &dim_ops_l1_v3;
+ if (IS_IC(ic_id, T7))
+ get_datal()->hop_l1 = &dim_ops_l1_v4;
+ else
+ get_datal()->hop_l1 = &dim_ops_l1_v3;
di_attach_ops_v3(&get_datal()->hop_l2);
#ifdef MARK_SC2
if (get_datal()->hop_l2)
PR_INF("%s\n", "op12 failed");
#endif
}
+ PR_INF("%s:%d:%s\n", __func__, ic_id, opl1()->info.name);
+ pq_sv_db_ini();
}
+bool dip_is_linear(void)
+{
+ bool ret = false;
+
+ if (cfgg(LINEAR))
+ ret = true;
+
+ return ret;
+}
/**********************************/
void dip_clean_value(void)
{
di_mp_uit_init_val();
di_mp_uix_init_val();
+ dim_tmode_preset(); /*need before vframe*/
dev_vframe_init();
didbg_fs_init();
// dip_wq_prob();
bufq_mem_exit(pch);
bufq_pat_exit(pch);
bufq_iat_exit(pch);
+ bufq_sct_exit(pch);
+
+ bufq_nin_exit(pch);
+ bufq_ndis_exit(pch);
+ ndrd_exit(pch);
+ npst_exit(pch);
}
dim_release_canvas();
// dip_wq_ext();
dev_vframe_exit();
dip_clean_value();
didbg_fs_exit();
+ #ifdef TST_NEW_INS_INTERFACE
+ dtst_exit();
+ #endif
+}
+
+void dip_prob_ch(void)
+{
+ unsigned int ch;
+ struct di_ch_s *pch;
+
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+ bufq_sct_int(pch);
+ sct_prob(pch);
+
+ /**/
+ bufq_nin_int(pch);
+ bufq_ndis_int(pch);
+ ndrd_int(pch);
+ npst_int(pch);
+ dip_itf_prob(pch);
+ }
+
+ #ifdef TST_NEW_INS_INTERFACE
+ dtst_prob();
+ #endif
+}
+
+bool dbg_src_change_simple(unsigned int ch/*struct di_ch_s *pch*/)
+{
+ struct vframe_s *vfm;
+ //unsigned int ch;
+ static unsigned int last_w;
+ static enum EDI_SGN sgn;
+ struct di_ch_s *pch;
+ unsigned int x, y;
+
+ if (!cfgg(PAUSE_SRC_CHG))
+ return false;
+
+ //ch = pch->ch_id;
+ pch = get_chdata(ch);
+ vfm = nins_peekvfm(pch);//pw_vf_peek(ch);
+ if (!vfm)
+ return false;
+
+ dim_vf_x_y(vfm, &x, &y);
+ if (cfgg(PAUSE_SRC_CHG) == 1) {
+ if (last_w != x) {
+ PR_INF("%s:%d->%d,0x%x\n", __func__,
+ last_w, x, vfm->type);
+ last_w = x;
+ pre_run_flag = DI_RUN_FLAG_PAUSE;
+ }
+ } else if (cfgg(PAUSE_SRC_CHG) == 2) {
+ /**/
+ sgn = di_vframe_2_sgn(vfm);
+ if (last_w != sgn) {
+ PR_INF("%s:%d->%d\n", __func__, last_w, sgn);
+ last_w = sgn;
+ pre_run_flag = DI_RUN_FLAG_PAUSE;
+ }
+ }
+
+ return true;
}
/**********************************************/
cfg_cpy->opin = &di_pre_regset;
dbg_copy("is_4k[%d]\n", is_4k);
- #if 1
+
if (is_4k)
dim_sc2_4k_set(2);
else
dim_sc2_4k_set(0);
- #endif
+
cfg.d32 = 0;
dim_sc2_contr_pre(&cfg);
if (cfg_cpy->in_afbcd)
}
/*
- * input use use vframe set
+ * input use vframe set
* out use pst cfg
*/
int dim_post_process_copy_only(struct di_ch_s *pch,
cfg_cpy->opin = &di_pre_regset;
dbg_copy("is_4k[%d]\n", is_4k);
- #if 1
+
if (is_4k)
dim_sc2_4k_set(2);
else
dim_sc2_4k_set(0);
- #endif
+
cfg.d32 = 0;
dim_sc2_contr_pre(&cfg);
if (cfg_cpy->in_afbcd)
int i;
unsigned int flg_mode, mode_rotation, mode_copy;
char *mname = "nothing";
+ struct dim_nins_s *nins;
// struct di_hpst_s *pst = get_hw_pst();
if (mode & 0x0f) {
pst->cfg_rot = (mode_rotation & (DI_BIT1 | DI_BIT2)) >> 1;
/**********************/
/* vfm */
- vfm_in = pw_vf_peek(ch);
+ vfm_in = nins_peekvfm(pch);//pw_vf_peek(ch);
if (!vfm_in) {
dbg_copy("no input");
return;
return;
/**********************/
t_st = cur_to_usecs();
- vfm_in = pw_vf_get(ch);
+ //vfm_in = pw_vf_get(ch);
+ nins = nins_get(pch);
+ vfm_in = &nins->c.vfm_cp;
di_buf = di_que_out_to_di_buf(ch, QUE_POST_FREE);
t_c = cur_to_usecs();
us_diff[0] = (unsigned int)(t_c - t_st);
time_cnt++;
}
if (!pst->flg_int_done) {
- //PR_ERR("%s:copy failed\n", __func__);
- pw_vf_put(vfm_in, ch);
+ PR_ERR("%s:copy failed\n", __func__);
+ pw_vf_put(nins->c.ori, ch);
+ nins_move(pch, QBF_NINS_Q_USED, QBF_NINS_Q_IDLE);
return;
}
t_c = cur_to_usecs();
us_diff[2] = (unsigned int)(t_c - t_st);
- di_que_in(ch, QUE_POST_READY, di_buf);
+ //di_que_in(ch, QUE_POST_READY, di_buf);
+ pch->itf.op_fill_ready(pch, di_buf);
dbg_copy("di:typ2[0x%x]:\n", di_buf->vframe->type);
- pw_vf_put(vfm_in, ch);
+ pw_vf_put(nins->c.ori, ch);
+ nins_move(pch, QBF_NINS_Q_USED, QBF_NINS_Q_IDLE);
dbg_copy("%s:timer:%d:%px:%s\n", __func__, time_cnt, vfm_in, mname);
diffa = 0;
in_buf->vframe = &ppost->in_buf_vf;
memcpy(in_buf->vframe, vfm_in, sizeof(struct vframe_s));
in_buf->vframe->private_data = in_buf;
-
+ i_mif->dbg_from_dec = 1; //data from decoder, tmp
pre_cfg_cvs(in_buf->vframe);
- config_di_mif_v3(i_mif, DI_MIF0_ID_IF1, in_buf, ch);
+ pre_inp_mif_w(i_mif, in_buf->vframe);
+ //config_di_mif_v3_test_pip(i_mif, DI_MIF0_ID_IF1, in_buf, ch);
+ opl1()->pre_cfg_mif(i_mif, DI_MIF0_ID_IF1, in_buf, ch);
i_mif->mif_index = DI_MIF0_ID_IF1;
+ i_mif->burst_size_y = 3;
+ i_mif->burst_size_cb = 1;
+ i_mif->burst_size_cr = 1;
+ i_mif->hold_line = 0x0a;
+ if (di_dbg & DBG_M_COPY)
+ dim_dump_mif_state(i_mif, "if1");
}
/* set vf */
o_afbce->enc_win_end_v = o_afbce->enc_win_bgn_v + v - 1;
//o_afbce->rot_en = pst->cfg_rot;
- #if 1
//sync with afbce
if (o_afbce->rot_en && cfg_cpy->in_afbcd) {
/*sync with afbce 422*/
else/* if (o_afbce->reg_compbits_y == 10) */
in_afbcd->rot_ocompbit = 2;
}
- #endif
+
//di_buf->vframe->compHeight = v;
//di_buf->vframe->compWidth = h;
//di_buf->vframe->height = v;
cfg_cpy->opin = &di_pre_regset;
dbg_copy("is_4k[%d]\n", is_4k);
- #if 1
if (is_4k)
dim_sc2_4k_set(2);
else
dim_sc2_4k_set(0);
- #endif
cfg.d32 = 0;
dim_sc2_contr_pre(&cfg);
if (cfg_cpy->in_afbcd)
struct di_buf_s *di_buf;
unsigned int ch;
struct di_hpst_s *pst = get_hw_pst();
+ struct dim_nins_s *nins;
ch = pch->ch_id;
/**********************/
pst->cfg_out_fmt = 1;
/**********************/
/* vfm */
- vfm_in = pw_vf_peek(ch);
+ vfm_in = nins_peekvfm(pch);//pw_vf_peek(ch);
if (!vfm_in) {
dbg_copy("no input");
return;
if (di_que_is_empty(ch, QUE_POST_FREE))
return;
/**********************/
- vfm_in = pw_vf_get(ch);
+ //vfm_in = pw_vf_get(ch);
+ nins = nins_get(pch);
+ vfm_in = &nins->c.vfm_cp;
di_buf = di_que_out_to_di_buf(ch, QUE_POST_FREE);
/**********************/
pst->cfg_pip_nub = (mode & 0xf);
dim_post_copy_pip(pch, vfm_in, di_buf, (mode & 0xf0) >> 4);
- di_que_in(ch, QUE_POST_READY, di_buf);
+ //di_que_in(ch, QUE_POST_READY, di_buf);
+ pch->itf.op_fill_ready(pch, di_buf);
dbg_copy("di:typ2[0x%x]:\n", di_buf->vframe->type);
- pw_vf_put(vfm_in, ch);
+ //pw_vf_put(vfm_in, ch);
+ pw_vf_put(nins->c.ori, ch);
+ nins_move(pch, QBF_NINS_Q_USED, QBF_NINS_Q_IDLE);
}
#else
{
}
#endif
+
+static unsigned int dbg_trig_eos;
+module_param_named(dbg_trig_eos, dbg_trig_eos, uint, 0664);
+
+bool dbg_is_trig_eos(unsigned int ch)
+{
+ bool ret = false;
+ struct di_pre_stru_s *ppre = get_pre_stru(ch);
+
+ if ((dbg_trig_eos & DI_BIT0) && ppre->field_count_for_cont >= 1) {
+ ret = true;
+ dbg_trig_eos &= ~DI_BIT0;
+ PR_INF("%s:%d\n", __func__, dbg_trig_eos);
+ }
+
+ return ret;
+}
+
+void dbg_q_listid(struct seq_file *s, struct buf_que_s *pqbuf)
+{
+ unsigned int j, i;
+ struct qs_cls_s *p;
+ unsigned int psize;
+ char *splt = "---------------------------";
+
+ seq_printf(s, "%s:\n", pqbuf->name);
+ for (j = 0; j < pqbuf->nub_que; j++) {
+ p = pqbuf->pque[j];
+ p->ops.list(pqbuf, p, &psize);
+
+ seq_printf(s, "%s (crr %d):\n", p->name, psize);
+ for (i = 0; i < psize; i++)
+ seq_printf(s, "\t%2d,\n", pqbuf->list_id[i]);
+
+ seq_printf(s, "%s\n", splt);
+ }
+}
+
+void dbg_q_listid_print(struct buf_que_s *pqbuf)
+{
+ unsigned int j, i;
+ struct qs_cls_s *p;
+ unsigned int psize;
+ char *splt = "---------------------------";
+
+ PR_INF("%s:\n", pqbuf->name);
+ for (j = 0; j < pqbuf->nub_que; j++) {
+ p = pqbuf->pque[j];
+ p->ops.list(pqbuf, p, &psize);
+
+ PR_INF("%s (crr %d):\n", p->name, psize);
+ for (i = 0; i < psize; i++)
+ PR_INF("\t%2d,\n", pqbuf->list_id[i]);
+
+ PR_INF("%s\n", splt);
+ }
+}
+
+void dbg_hd(struct seq_file *s, struct qs_buf_s *header)
+{
+ seq_printf(s, "%s\n", "header");
+ if (!header) {
+ seq_puts(s, "\tnone\n");
+ return;
+ }
+ seq_printf(s, "\t%s:%d\n", "index", header->index);
+ seq_printf(s, "\t%s:0x%x\n", "code", header->code);
+ //seq_printf(s, "\t%s:%d:%s\n", "dbg_id", header->dbg_id,
+ // dbgid_name(header->dbg_id));
+}
+
+void dbg_hd_print(struct qs_buf_s *header)
+{
+ PR_INF("%s\n", "header");
+ if (!header) {
+ PR_INF("\tnone\n");
+ return;
+ }
+ PR_INF("\t%s:%d\n", "index", header->index);
+ PR_INF("\t%s:0x%x\n", "code", header->code);
+ //PR_INF("\t%s:%d:%s\n", "dbg_id", header->dbg_id,
+ // dbgid_name(header->dbg_id));
+ PR_INF("%px\n", header);
+}
+
+void dbg_blk(struct seq_file *s, struct dim_mm_blk_s *blk_buf)
+{
+ seq_printf(s, "%s\n", "blk");
+ if (!blk_buf) {
+ seq_puts(s, "\tnone\n");
+ return;
+ }
+ dbg_hd(s, &blk_buf->header);
+
+ seq_printf(s, "\t%s:0x%lx\n", "mem_start", blk_buf->mem_start);
+ seq_printf(s, "\t%s:0x%x\n", "size_page", blk_buf->flg.b.page);
+ seq_printf(s, "\t%s:0x%x\n", "size_page", blk_buf->flg.b.typ);
+ seq_printf(s, "\t%s:%d\n", "flg_alloc", blk_buf->flg_alloc);
+ seq_printf(s, "\t%s:%d\n", "tvp", blk_buf->flg.b.tvp);
+}
+
+/* @ary_note: */
+void dbg_q_list_qbuf(struct seq_file *s, struct buf_que_s *pqbuf)
+{
+ unsigned int j;
+ union q_buf_u pbuf;
+ //struct qs_buf_s *header;
+
+ char *splt = "---------------------------";
+
+ seq_printf(s, "%s:\n", pqbuf->name);
+ for (j = 0; j < pqbuf->nub_buf; j++) {
+ pbuf = pqbuf->pbuf[j];
+ if (!pbuf.qbc)
+ break;
+ //header = pbuf->qbc;
+ dbg_hd(s, pbuf.qbc);
+
+ seq_printf(s, "%s\n", splt);
+ }
+}
+
+void dbg_q_list_qbuf_print(struct buf_que_s *pqbuf)
+{
+ unsigned int j;
+ union q_buf_u pbuf;
+ //struct qs_buf_s *header;
+
+ char *splt = "---------------------------";
+
+ PR_INF("%s:\n", pqbuf->name);
+ for (j = 0; j < pqbuf->nub_buf; j++) {
+ pbuf = pqbuf->pbuf[j];
+ if (!pbuf.qbc)
+ break;
+ //header = pbuf->qbc;
+ dbg_hd_print(pbuf.qbc);
+
+ PR_INF("%s\n", splt);
+ }
+}
+
+void dbg_buffer(struct seq_file *s, void *in)
+{
+ struct di_buffer *buffer;
+
+ buffer = (struct di_buffer *)in;
+ seq_printf(s, "%s:%px\n", "dbg_buffer", buffer);
+ seq_printf(s, "\t:code:0x%x,ch[%d],indx[%d], type[%d]\n",
+ buffer->mng.code, buffer->mng.ch,
+ buffer->mng.index, buffer->mng.type);
+ if (buffer->vf)
+ seq_printf(s, "\t:vf:0x%px, 0x%x\n",
+ buffer->vf, buffer->vf->index);
+ else
+ seq_printf(s, "\t:%s\n", "no vf");
+}
+
+void dbg_buffer_print(void *in)
+{
+ struct di_buffer *buffer;
+
+ buffer = (struct di_buffer *)in;
+ PR_INF("%s:%px\n", "dbg_buffer", buffer);
+ PR_INF("\t:code:0x%x,ch[%d],indx[%d], type[%d]\n",
+ buffer->mng.code, buffer->mng.ch,
+ buffer->mng.index, buffer->mng.type);
+ if (buffer->vf)
+ PR_INF("\t:vf:0x%px, 0x%x\n", buffer->vf, buffer->vf->index);
+ else
+ PR_INF("\t:%s\n", "no vf");
+}
+
+void dbg_vfm_w(struct vframe_s *vfm, unsigned int dbgid)
+{
+ dbg_ic("%s:%d:\n", __func__, dbgid);
+ if (!vfm) {
+ dbg_ic("\t:no vmf\n");
+ return;
+ }
+ dbg_ic("\t0x%px:id[%d];t[0x%x]\n", vfm, vfm->index_disp, vfm->type);
+ dbg_ic("\t xy<%d,%d><%d, %d>\n", vfm->width,
+ vfm->height, vfm->compWidth, vfm->compHeight);
+ dbg_ic("\t ph:<%d %d>\n", vfm->canvas0_config[0].width,
+ vfm->canvas0_config[0].height);
+}
+
bool dip_prob(void);
void dip_exit(void);
+void dip_prob_ch(void);
void dip_even_reg_init_val(unsigned int ch);
void dip_even_unreg_val(unsigned int ch);
void di_cfgt_show_val_sel(struct seq_file *s);
void di_cfgt_show_val_all(struct seq_file *s);
void di_cfgt_set_sel(unsigned int dbg_mode, unsigned int id);
+void di_cfg_cp_ch(struct di_ch_s *pch);
+unsigned char di_cfg_cp_get(struct di_ch_s *pch,
+ enum EDI_CFG_TOP_IDX id);
+void di_cfg_cp_set(struct di_ch_s *pch,
+ enum EDI_CFG_TOP_IDX id,
+ unsigned char val);
/**************************************
*
void dip_init_value_reg(unsigned int ch, struct vframe_s *vframe);
enum EDI_SGN di_vframe_2_sgn(struct vframe_s *vframe);
-const struct di_mm_cfg_s *di_get_mm_tab(unsigned int is_4k);
+const struct di_mm_cfg_s *di_get_mm_tab(unsigned int is_4k,
+ struct di_ch_s *pch);
+
+/************************************************
+ * sct
+ ************************************************/
+void tst_alloc(struct di_ch_s *pch);
+void tst_resize(struct di_ch_s *pch, unsigned int used_size);
+void tst_release(struct di_ch_s *pch);
+void tst_unreg(struct di_ch_s *pch);
+void tst_reg(struct di_ch_s *pch);
+
+void sct_prob(struct di_ch_s *pch);
+void sct_sw_on(struct di_ch_s *pch,
+ unsigned int max_num,
+ bool tvp,
+ unsigned int buffer_size);
+void sct_sw_off_rebuild(struct di_ch_s *pch);
+
+void sct_alloc_in_poling(unsigned int ch);
+void sct_mng_working(struct di_ch_s *pch);
+void sct_mng_working_recycle(struct di_ch_s *pch);
+
+void sct_mng_idle(struct di_ch_s *pch);
+void sct_free_l(struct di_ch_s *pch, struct dim_sct_s *sct);
+void sct_free_tail_l(struct di_ch_s *pch,
+ unsigned int buffer_used,
+ struct dim_sct_s *sct);
+unsigned int sct_keep(struct di_ch_s *pch, struct dim_sct_s *sct);
+void sct_sw_off(struct di_ch_s *pch);
+int dim_dbg_sct_top_show(struct seq_file *s, void *what);
+
+void bufq_nin_int(struct di_ch_s *pch);
+void bufq_nin_exit(struct di_ch_s *pch);
+void bufq_nin_reg(struct di_ch_s *pch);
+struct dim_nins_s *nins_peek(struct di_ch_s *pch);
+struct dim_nins_s *nins_get(struct di_ch_s *pch);
+struct vframe_s *nins_peekvfm(struct di_ch_s *pch);
+bool nins_out_some(struct di_ch_s *pch,
+ struct dim_nins_s *ins,
+ unsigned int q);
+bool nins_used_some_to_recycle(struct di_ch_s *pch,
+ struct dim_nins_s *ins);
+struct dim_nins_s *nins_move(struct di_ch_s *pch,
+ unsigned int qf,
+ unsigned int qt);
+unsigned int nins_cnt_used_all(struct di_ch_s *pch);
+unsigned int nins_cnt(struct di_ch_s *pch, unsigned int q);
+
+struct vframe_s *ndrd_qout(struct di_ch_s *pch);
+void dbg_nins_log_buf(struct di_buf_s *di_buf, unsigned int dbgid);
+void dbg_nins_check_id(struct di_ch_s *pch);
+
+void bufq_ndis_int(struct di_ch_s *pch);
+void bufq_ndis_exit(struct di_ch_s *pch);
+
+bool ndis_fill_ready(struct di_ch_s *pch, struct di_buf_s *di_buf);
+bool ndrd_m1_fill_ready(struct di_ch_s *pch, struct di_buf_s *di_buf);
+bool ndis_is_in_display(struct di_ch_s *pch, struct dim_ndis_s *ndis);
+bool ndis_move_display2idle(struct di_ch_s *pch, struct dim_ndis_s *ndis);
+struct dim_ndis_s *ndis_get_fromid(struct di_ch_s *pch, unsigned int idx);
+unsigned int ndis_cnt(struct di_ch_s *pch, unsigned int que);
+struct dim_ndis_s *ndis_move(struct di_ch_s *pch,
+ unsigned int qf,
+ unsigned int qt);
+unsigned int ndis_2keep(struct di_ch_s *pch,
+ struct dim_mm_blk_s **blk,
+ unsigned int len_max,
+ unsigned int disable_mirror);
+void bufq_ndis_unreg(struct di_ch_s *pch);
+bool ndis_is_in_keep(struct di_ch_s *pch, struct dim_ndis_s *ndis);
+bool ndis_move_keep2idle(struct di_ch_s *pch, struct dim_ndis_s *ndis);
+void ndis_dbg_qbuf_detail(struct seq_file *s, struct di_ch_s *pch);
+void ndis_dbg_print2(struct dim_ndis_s *ndis, char *name);
+
+void ndrd_int(struct di_ch_s *pch);
+void ndrd_exit(struct di_ch_s *pch);
+unsigned int ndrd_cnt(struct di_ch_s *pch);
+
+struct vframe_s *ndrd_qpeekvfm(struct di_ch_s *pch);
+struct di_buf_s *ndrd_qpeekbuf(struct di_ch_s *pch);
+void ndrd_dbg_list_buf(struct seq_file *s, struct di_ch_s *pch);
+void ndrd_qin(struct di_ch_s *pch, void *vfm);
+void ndrd_reset(struct di_ch_s *pch);
+
+void dip_itf_ndrd_ins_m2_out(struct di_ch_s *pch);
+void dip_itf_ndrd_ins_m1_out(struct di_ch_s *pch);
+
+void ndkb_qin(struct di_ch_s *pch, struct dim_ndis_s *ndis);
+struct dim_ndis_s *ndkb_qout(struct di_ch_s *pch);
+unsigned int ndkb_cnt(struct di_ch_s *pch);
+void ndkb_qin_byidx(struct di_ch_s *pch, unsigned int idx);
+void ndkb_dbg_list(struct seq_file *s, struct di_ch_s *pch);
+void npst_int(struct di_ch_s *pch);
+void npst_exit(struct di_ch_s *pch);
+void npst_reset(struct di_ch_s *pch);
+/* */
+void npst_qin(struct di_ch_s *pch, void *buffer);
+/* @ary_note: */
+struct di_buffer *npst_qpeek(struct di_ch_s *pch);
+struct di_buffer *npst_qout(struct di_ch_s *pch);
+unsigned int npst_cnt(struct di_ch_s *pch);
+void dbg_log_pst_buffer(struct di_buf_s *di_buf, unsigned int dbgid);
+
+void dip_itf_vf_op_polling(struct di_ch_s *pch);
+void dip_itf_back_input(struct di_ch_s *pch);
+struct dev_vfm_s *dip_itf_vf_sop(struct di_ch_s *pch);
+bool dip_itf_is_vfm(struct di_ch_s *pch);
+bool dip_itf_is_ins(struct di_ch_s *pch);
+bool dip_itf_is_ins_lbuf(struct di_ch_s *pch);
+bool dip_itf_is_ins_exbuf(struct di_ch_s *pch);
+bool dip_itf_is_o_linear(struct di_ch_s *pch);
+void dbg_itf_tmode(struct di_ch_s *pch, unsigned int pos);
+void dim_dbg_buffer(struct di_buffer *buffer, unsigned int id);
+
+unsigned int nins_cnt_used_all(struct di_ch_s *pch);
bool di_is_pause(unsigned int ch);
void di_pause_step_done(unsigned int ch);
void di_pause(unsigned int ch, bool on);
void dim_sumx_clear(unsigned int ch);
-void dim_sumx_set(unsigned int ch);
+void dim_sumx_set(struct di_ch_s *pch);
void dim_mp_update_reg(void);
void dim_mp_update_post(void);
void dip_init_pq_ops(void);
+bool dbg_src_change_simple(unsigned int ch);
bool dbg_checkcrc(struct di_buf_s *di_buf, unsigned int cnt);
void dbg_cp_4k(struct di_ch_s *pch, unsigned int mode);
void pre_cfg_cvs(struct vframe_s *vf);//debug only
void dbg_pip_func(struct di_ch_s *pch, unsigned int mode);
bool dip_is_support_4k(unsigned int ch);
+bool dip_is_support_nv2110(unsigned int ch);
+bool dip_is_4k_sct_mem(struct di_ch_s *pch);
+bool dip_is_ponly_sct_mem(struct di_ch_s *pch);
+
+void dim_vf_x_y(struct vframe_s *vf, unsigned int *x, unsigned int *y);
/************************************************/
void dcntr_prob(void);
void dcntr_check(struct vframe_s *vfm);
void dcntr_dis(void);
void dcntr_set(void);
+void dcntr_pq_tune(struct dim_rpt_s *rpt);
+struct dim_rpt_s *dim_api_getrpt(struct vframe_s *vfm);
+void dim_pqrpt_init(struct dim_rpt_s *rpt);
+
+void di_pq_db_setting(enum DIM_DB_SV idx);
int dbg_dct_mif_show(struct seq_file *s, void *v);
int dbg_dct_core_show(struct seq_file *s, void *v);
int dbg_dct_contr_show(struct seq_file *s, void *v);
void dbg_regs_tab(struct seq_file *s, const struct regs_t *pregtab,
- const unsigned int *padd);//debug only
+ const unsigned int *padd);//debug only
void dbg_reg_tab(struct seq_file *s, const struct reg_t *pregtab);//debug only
+void dbg_q_listid(struct seq_file *s, struct buf_que_s *pqbuf);
+void dbg_blk(struct seq_file *s, struct dim_mm_blk_s *blk_buf);
+bool dbg_sct_used_decoder_buffer(void);
+bool dbg_sct_clear_by_frame(void);
+void dbg_q_list_qbuf(struct seq_file *s, struct buf_que_s *pqbuf);
+void dbg_q_list_qbuf_print(struct buf_que_s *pqbuf);
+void dbg_q_list_qbuf_buffer(struct seq_file *s, struct buf_que_s *pqbuf);
+void vfmtst_init(void);
+void vfmtst_exit(void);
+void dtst_prob(void);
+void dtst_exit(void);
+
+void dbg_buffer(struct seq_file *s, void *in);
+void dbg_buffer_print(void *in);
+//int dim_dbg_tst_in_show(struct seq_file *s, void *what);
+//void qbuf_dbg_check_in_buffer_id(unsigned int dbgid);
+bool tst_tmp_is_extbuf(void);
+bool dim_is_dbg_tabe(void);
+void dip_sum_post_ch(void);
+
+void dbg_hd(struct seq_file *s, struct qs_buf_s *header);
+void dbg_hd_print(struct qs_buf_s *header);
+void print_di_buf_seq(struct di_buf_s *di_buf, int format,
+ struct seq_file *seq);
+void dbg_q_listid_print(struct buf_que_s *pqbuf);
+void dim_dbg_buffer2(struct di_buffer *buffer, unsigned int id);
+bool dim_dbg_new_int(unsigned int id);
+#ifdef TST_NEW_INS_INTERFACE
+int dim_dbg_tst_in_show(struct seq_file *s, void *what);
+
+#endif
+unsigned int dim_get_dbg_dec21(void);
+bool dim_in_linear(void);
+bool dim_dbg_cfg_disable_arb(void);
+void dbg_vfm_w(struct vframe_s *vfm, unsigned int dbgid);
+bool dbg_is_trig_eos(unsigned int ch);
+void pre_inp_mif_w(struct DI_MIF_S *di_mif, struct vframe_s *vf);
#endif /*__DI_PRC_H__*/
{/*reg:*/
struct di_hpre_s *pre = get_hw_pre();
- pre->pre_st = EDI_PRE_ST_IDLE;
+ pre->pre_st = EDI_PRE_ST4_IDLE;
+ //bset(&pre->self_trig_mask, 2);//
/*timer out*/
di_tout_int(&pre->tout, 40); /*ms*/
{
struct di_hpre_s *pre = get_hw_pre();
unsigned int ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);//K_DO_R_NOT_FINISH;
+ unsigned int cfg_val;
+ dbg_src_change_simple(pre->curr_ch);/*dbg only*/
+#ifdef MARK_HIS
if (pre_run_flag == DI_RUN_FLAG_RUN ||
pre_run_flag == DI_RUN_FLAG_STEP) {
if (pre_run_flag == DI_RUN_FLAG_STEP)
dim_dbg_pre_cnt(pre->curr_ch, "x");
}
+#else
+ cfg_val = dim_pre_de_buf_config(pre->curr_ch);
+ if (!cfg_val) {/*ok*/
+ ret = K_DO_R_FINISH;
+ } else {
+ dbg_dt("cfg fail:%d\n", cfg_val);
+ ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
+ }
+#endif
return ret;
}
unsigned int dpre_mtotal_set(void *data)
{
struct di_hpre_s *pre = get_hw_pre();
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
/*dim_print("%s:\n", __func__);*/
- spin_lock_irqsave(&plist_lock, flags);
+ //trace_printk("%s\n", __func__);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
dim_pre_de_process(pre->curr_ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
/*begin to count timer*/
di_tout_contr(EDI_TOUT_CONTR_EN, &pre->tout);
enum EDI_WAIT_INT di_pre_wait_int(void *data)
{
struct di_hpre_s *pre = get_hw_pre();
- ulong flags = 0;
+ //tmp ulong flags = 0;
struct di_pre_stru_s *ppre;
enum EDI_WAIT_INT ret = EDI_WAIT_INT_NEED_WAIT;
/*di_pre_wait_irq_set(false);*/
/*finish to count timer*/
di_tout_contr(EDI_TOUT_CONTR_FINISH, &pre->tout);
- spin_lock_irqsave(&plist_lock, flags);
+ //tmp spin_lock_irqsave(&plist_lock, flags);
dim_pre_de_done_buf_config(pre->curr_ch, false);
dpre_recyc(pre->curr_ch);
dpre_vdoing(pre->curr_ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+ //tmp spin_unlock_irqrestore(&plist_lock, flags);
ppre = get_pre_stru(pre->curr_ch);
if (di_tout_contr(EDI_TOUT_CONTR_CHECK, &pre->tout)) {
/*di_pre_wait_irq_set(false);*/
if (!atomic_dec_and_test(&get_hw_pre()->flg_wait_int)) {
- PR_WARN("%s:timeout\n", __func__);
+ PR_WARN("%s:ch[%d]timeout\n", __func__,
+ pre->curr_ch);
di_tout_contr(EDI_TOUT_CONTR_EN, &pre->tout);
} else {
/*return K_DO_R_FINISH;*/
/*move from di_pre_trigger_work*/
if (dimp_get(edi_mp_di_dbg_mask) & 4)
dim_dump_mif_size_state(pre->pres, pre->psts);
- hpre_timout_read();
+ hpre_timeout_read();
if (DIM_IS_IC_EF(SC2))
opl1()->pre_gl_sw(false);
unsigned int dpre_mtotal_timeout(void *data)
{
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
- spin_lock_irqsave(&plist_lock, flags);
+ //tmp spin_lock_irqsave(&plist_lock, flags);
dpre_mtotal_timeout_contr();
- spin_unlock_irqrestore(&plist_lock, flags);
+ //tmp spin_unlock_irqrestore(&plist_lock, flags);
return K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
}
if (pre_run_flag == DI_RUN_FLAG_STEP)
pre_run_flag = DI_RUN_FLAG_STEP_DONE;
dim_print("%s:\n", __func__);
- if (dim_pre_de_buf_config(pre->curr_ch)) {
+ if (!dim_pre_de_buf_config(pre->curr_ch)) {
/*pre->flg_wait_int = false;*/
/*pre_p_asi_set_next(pre->curr_ch);*/
ret = K_DO_R_FINISH;
struct di_hpre_s *pre = get_hw_pre();
unsigned int ret = K_DO_R_NOT_FINISH;
- if (dim_pre_de_buf_config(pre->curr_ch)) {
+ if (!dim_pre_de_buf_config(pre->curr_ch)) {
/*pre->flg_wait_int = false;*/
ret = K_DO_R_FINISH;
} else {
{
struct vframe_s *vframe;
unsigned int mode;
+ struct di_ch_s *pch;
- vframe = pw_vf_peek(ch);
+ pch = get_chdata(ch);
+ if (pre_run_flag == DI_RUN_FLAG_RUN ||
+ pre_run_flag == DI_RUN_FLAG_STEP) {
+ if (pre_run_flag == DI_RUN_FLAG_STEP)
+ pre_run_flag = DI_RUN_FLAG_STEP_DONE;
+ vframe = nins_peekvfm(pch);//pw_vf_peek(ch);
+ } else {
+ vframe = NULL;
+ }
if (!vframe)
return EDI_WORK_MODE_NONE;
return reflesh;
}
+bool dpre_after_do_table(void)
+{
+ struct di_hpre_s *pre = get_hw_pre();
+ enum EDI_PRE_ST4 pre_st;
+ bool ret = false;
+
+ if (do_table_is_crr(&pre->sdt_mode, K_DO_TABLE_ID_STOP)) {
+ pre->pre_st = EDI_PRE_ST4_IDLE;
+ ret = true;
+ }
+ pre_st = pre->pre_st;
+ pre->self_trig_mask = 0;
+ if (pre_run_flag == DI_RUN_FLAG_RUN)
+ bclr(&pre->self_trig_mask, 0);
+ else
+ bset(&pre->self_trig_mask, 0);
+
+ if (pre_st == EDI_PRE_ST4_DO_TABLE)
+ bset(&pre->self_trig_mask, 1);
+ else
+ bclr(&pre->self_trig_mask, 1);
+ return ret;
+}
+
const struct di_func_tab_s di_pre_func_tab4[] = {
{EDI_PRE_ST4_EXIT, NULL},
{EDI_PRE_ST4_IDLE, dpre_step4_idle},
{
struct di_hpre_s *pre = get_hw_pre();
enum EDI_PRE_ST4 pre_st = pre->pre_st;
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
if (pre_st > EDI_PRE_ST4_EXIT) {
- spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
dim_recycle_post_back(pre->curr_ch);
dpre_recyc(pre->curr_ch);
dpre_vdoing(pre->curr_ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
}
if (pre_st <= EDI_PRE_ST4_DO_TABLE &&
di_pre_func_tab4[pre_st].func) {
void pre_mode_setting(void);
bool dpre_process_step4(void);
const char *dpre_state4_name_get(enum EDI_PRE_ST4 state);
+bool dpre_after_do_table(void);
#endif /*__DI_PRE_H__*/
"QUE_POST_READY", /*3*/
"QUE_POST_BACK", /*4*/
"QUE_POST_DOING",
- "QUE_POST_KEEP",
- "QUE_POST_KEEP_BACK",
+// "QUE_POST_KEEP",
+// "QUE_POST_KEEP_BACK",
"QUE_DBG",
/* "QUE_NUB",*/
struct di_ch_s *pch = get_chdata(ch);
for (i = 0; i < QUE_NUB; i++) {
- if (i == QUE_POST_KEEP ||
- i == QUE_POST_KEEP_BACK ||
+ if (
+// i == QUE_POST_KEEP ||
+// i == QUE_POST_KEEP_BACK ||
i == QUE_POST_KEEP_RE_ALLOC)
continue;
pw_queue_clear(ch, i);
bool qbuf_reset(struct buf_que_s *pqbuf);
bool qbuf_peek(struct buf_que_s *pqbuf, unsigned int qt,
unsigned int *buf_index);
-bool qbuf_peek_s(struct buf_que_s *pqbuf, unsigned int qt,
- union q_buf_u *pbuf);
+//bool qbuf_peek_s(struct buf_que_s *pqbuf, unsigned int qt,
+// union q_buf_u *pbuf);
bool qbuf_in_all(struct buf_que_s *pqbuf, unsigned int qt);
bool qbuf_out_some(struct buf_que_s *pqbuf,
unsigned int qt, union q_buf_u q_buf);
+void qbuf_dbg_checkid(struct buf_que_s *pqbuf, unsigned int dbgid);
bool qbufp_move_some(struct buf_que_s *pqbuf, unsigned int qf,
unsigned int qt, union q_buf_u q_buf);
bool qbufp_list(struct buf_que_s *pqbuf,
unsigned int qt);
+void qfp_int(struct qs_cls_s *pq,
+ unsigned char *qname,
+ unsigned int lock);
+bool qfp_release(struct qs_cls_s *pq);
+/* dbg only*/
+unsigned int qfp_list(struct qs_cls_s *p,
+ unsigned int size,
+ void **list);
+
+/* only for n type have this function */
+bool qbuf_n_is_in(struct buf_que_s *pqbuf,
+ unsigned int qt,
+ union q_buf_u q_buf);
+
/*************************************************/
#endif /*__DI_QUE_H__*/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* drivers/amlogic/media/di_multi/di_vfm_test.c
*
//#include "di_interface.h"
//#include "di_vfm_test.h"
-#define PR_ERR_Q(fmt, args ...) pr_err("dim:err:"fmt, ## args)
+#define PR_ERR_Q(fmt, args ...) pr_err("dim:err:" fmt, ## args)
//static DEFINE_SPINLOCK(dim_ready);
-
+#ifdef MARK_HIS
unsigned int bypass_flg[] = {
CODE_BYPASS,
};
-
+#endif
/*keep same order with enum QS_FUNC_E*/
const char *qs_func_name[] = {
"n_in",
return true;
}
+static bool n_out(struct buf_que_s *pqb, struct qs_cls_s *p,
+ union q_buf_u *pbuf)
+{
+ int i;
+ //unsigned int index;
+ unsigned int mask;
+ //unsigned int cnt;
+ ulong flags = 0;
+ bool ret = false;
+
+ if (p->flg_lock)
+ spin_lock_irqsave(&p->lock_rd, flags);
+
+ if (!p->n.nub) {
+ /* *pbuf = NULL; */
+ if (p->flg_lock)
+ spin_unlock_irqrestore(&p->lock_rd, flags);
+ return false;
+ }
+
+ mask = p->n.marsk;
+
+ for (i = 0; i < MAX_FIFO_SIZE; i++) {
+ if (mask & 0x01) {
+ //pqb->list_id[cnt] = i;
+ *pbuf = pqb->pbuf[i];
+ bclr(&p->n.marsk, i);
+ p->n.nub--;
+ ret = true;
+ break;
+ }
+ mask >>= 1;
+ }
+
+ if (p->flg_lock)
+ spin_unlock_irqrestore(&p->lock_rd, flags);
+
+ return ret;
+}
+
+/* 2020-12-07 */
+static bool n_is_in(struct buf_que_s *pqb,
+ struct qs_cls_s *p, union q_buf_u ubuf)
+{
+ struct qs_err_msg_s msg;
+ //struct qs_cls_s *p;
+ unsigned int buf_index;
+ ulong flags = 0;
+ bool ret;
+
+ buf_index = ubuf.qbc->index;
+ if (buf_index > 31 ||
+ !is_eq_ubuf(pqb->pbuf[buf_index], ubuf)) {
+ msg.func_id = QS_FUNC_N_IS_IN;
+ msg.err_id = QS_ERR_INDEX_OVERFLOW;
+ msg.qname = p->name;
+ msg.index1 = buf_index;
+ msg.index2 = 0;
+ qs_err_add(p->plog, &msg);
+ PR_ERR_Q("%s can't support %d\n", __func__, buf_index);
+
+ return false;
+ }
+
+ if (p->flg_lock)
+ spin_lock_irqsave(&p->lock_rd, flags);
+
+ if (bget(&p->n.marsk, buf_index))
+ ret = true;
+ else
+ ret = false;
+
+ if (p->flg_lock)
+ spin_unlock_irqrestore(&p->lock_rd, flags);
+
+ return ret;
+}
+
+static bool n_get_marsk(struct buf_que_s *pqb, struct qs_cls_s *p,
+ unsigned int *marsk)
+{
+// int i;
+ //unsigned int index;
+// unsigned int mask;
+// unsigned int cnt;
+ ulong flags = 0;
+// bool ret = false;
+
+ if (p->flg_lock)
+ spin_lock_irqsave(&p->lock_rd, flags);
+
+ *marsk = p->n.marsk;
+ if (p->flg_lock)
+ spin_unlock_irqrestore(&p->lock_rd, flags);
+ return true;
+}
+
/******************************************************************/
static bool np_reset(struct buf_que_s *pqb, struct qs_cls_s *p)
{
.count = f_count,
.reset = f_reset,
.list = f_list,
+ .is_in = NULL,
+ .n_get_marsk = NULL,
},
[Q_T_N] = {
.in = n_in,
- .out = NULL,
+ .out = n_out,
.out_some = n_out_some,
.peek = NULL,
.is_empty = n_empty,
.count = n_count,
.reset = n_reset,
.list = n_list,
+ .is_in = n_is_in,
+ .n_get_marsk = n_get_marsk,
},
[Q_T_FIFO_2] = {
.in = fp_in,
.count = fp_count,
.reset = fp_reset,
.list = fp_list,
+ .is_in = NULL,
+ .n_get_marsk = NULL,
},
[Q_T_N_2] = {
.in = np_in,
.count = np_count,
.reset = np_reset,
.list = np_list,
+ .is_in = NULL,
+ .n_get_marsk = NULL,
}
};
return false;
}
#endif
+/* fp que don't need pbufq */
+void qfp_int(struct qs_cls_s *pq,
+ unsigned char *qname,
+ unsigned int lock)
+{
+// int i;
+// const struct que_creat_s *pcfg;
+
+// bool rsc_flg = true;
+// int ret;
+
+ if (!pq)
+ return;
+
+ /*creat que*/
+ qs_creat(Q_T_FIFO_2, pq, qname);
+ if (!pq->flg) {
+ //rsc_flg = false;
+ //no resource
+ return;
+ }
+ /*reset*/
+ pq->ops.reset(NULL, pq);
+ /*lock ?*/
+ if (lock & DIM_QUE_LOCK_RD) {
+ spin_lock_init(&pq->lock_rd);
+ pq->flg_lock |= DIM_QUE_LOCK_RD;
+ }
+ if (lock & DIM_QUE_LOCK_WR) {
+ spin_lock_init(&pq->lock_wr);
+ pq->flg_lock |= DIM_QUE_LOCK_WR;
+ }
+
+ PR_INF("%s:%s:end\n", __func__, qname);
+}
+
+bool qfp_release(struct qs_cls_s *pq)
+{
+// int i;
+
+ if (!pq)
+ return true;
+ qs_release(pq);
+
+ return true;
+}
+
+/* @ary_note: this need protect */
+unsigned int qfp_list(struct qs_cls_s *p,
+ unsigned int size,
+ void **list)
+{
+ int i;
+ ud index;
+ struct kfifo tmp_kfifo;
+ int ret;
+ unsigned int cnt = 0;
+
+ for (i = 0; i < size; i++)
+ list[i] = NULL;
+
+ if (kfifo_is_empty(&p->f.fifo)) {
+ PR_INF("\t%s:empty\n", p->name);
+ return 0;
+ }
+
+ ret = kfifo_alloc(&tmp_kfifo,
+ tst_quep_ele * MAX_FIFO_SIZE,
+ GFP_KERNEL);
+ if (ret < 0) {
+ PR_ERR_Q("%s:alloc kfifo err:tmp\n", __func__);
+ return false;
+ }
+
+ memcpy(&tmp_kfifo, &p->f.fifo, sizeof(tmp_kfifo));
+
+ while (kfifo_out(&tmp_kfifo, &index, tst_quep_ele) ==
+ tst_quep_ele && (cnt < size)) {
+ list[i] = (void *)index;
+ cnt++;
+ }
+ kfifo_free(&tmp_kfifo);
+ return cnt;
+}
void qbuf_int(struct buf_que_s *pbufq, const struct que_creat_s *cfg,
const struct qbuf_creat_s *cfg_qbuf)
if (!pqbuf->pque[qindex]) {
PR_ERR_Q("%s:pq[%s][%d] is null\n", __func__,
pqbuf->name, qindex);
+ dump_stack();
return true;
}
pq = pqbuf->pque[qindex];
return ret;
}
+#ifdef HIS_CODE
/* pbuf is point */
bool qbuf_peek_s(struct buf_que_s *pqbuf, unsigned int qt,
union q_buf_u *pbuf)
return ret;
}
+#endif
bool qbuf_in_all(struct buf_que_s *pqbuf, unsigned int qt)
{
return true;
}
+bool qbuf_n_is_in(struct buf_que_s *pqbuf,
+ unsigned int qt,
+ union q_buf_u q_buf)
+{
+ struct qs_cls_s *pqt;
+
+ if (!pqbuf->pque[qt]) {
+ PR_ERR("%s:%s: no que %d\n", __func__, pqbuf->name, qt);
+ return false;
+ }
+
+ pqt = pqbuf->pque[qt];
+
+ if (pqt->ops.is_in)
+ return pqt->ops.is_in(pqbuf, pqt, q_buf);
+ PR_ERR("%s:%s:no is_in function:\n", __func__, pqt->name);
+ return false;
+}
+
bool qbuf_out_some(struct buf_que_s *pqbuf,
unsigned int qt,
union q_buf_u q_buf)
return ret;
}
+void qbuf_dbg_checkid(struct buf_que_s *pqbuf, unsigned int dbgid)
+{
+ int i;
+
+ //PR_INF("%s\n", pqbuf->name);
+ for (i = 0; i < pqbuf->nub_buf; i++) {
+ if (!pqbuf->pbuf[i].qbc) {
+ PR_ERR("%s:[%d]:[%d]no\n", pqbuf->name, dbgid, i);
+ break;
+ }
+
+ if (i != pqbuf->pbuf[i].qbc->index) {
+ PR_ERR("%s:[%d]id change [%d][%d]\n",
+ pqbuf->name,
+ dbgid, i, pqbuf->pbuf[i].qbc->index);
+ break;
+ }
+ //PR_INF("\t:%d:%d\n", i, pqbuf->pbuf[i].qbc->index);
+ }
+}
/***********************************************************/
bool qbufp_move_some(struct buf_que_s *pqbuf, unsigned int qf,
unsigned int qt, union q_buf_u q_buf)
{
struct qs_cls_s *pqt;
unsigned int siz;
- int i;
+// int i;
// ud index;
- struct qs_buf_s *qbc;
+// struct qs_buf_s *qbc;
if (!pqbuf->pque[qt]) {
PR_ERR("%s:%s: no que %d\n", __func__, pqbuf->name, qt);
if (pqt->ops.list)
pqt->ops.list(pqbuf, pqt, &siz);
+ #ifdef MARK_HIS
PR_INF("%s:%s:\n", __func__, pqt->name);
for (i = 0; i < MAX_FIFO_SIZE; i++) {
if (pqbuf->list_ud[i]) {
break;
}
}
+ #endif
return true;
}
i++;
creg = pregtab[i];
- if (i > TABLE_LEN_MAX) {
+ if (i > DIMTABLE_LEN_MAX) {
pr_info("warn: too long, stop\n");
break;
}
for (i = 0; i < tabsize; i++) {
if (pl->add == TABLE_FLG_END ||
- i > TABLE_LEN_MAX) {
+ i > DIMTABLE_LEN_MAX) {
break;
}
/* `define DI_BLEND_CTRL2 8'h0f */
/* no use */
-/* crc t5 ,same as sc2*/
+/* crc t5/t5d ,function same as sc2*/
#define DI_T5_CRC_CHK0 ((0x17cB))
#define DI_T5_CRC_CHK1 ((0x17cc))
#define DI_T5_RO_CRC_NRWR ((0x17c3))
#define DI_T5_RO_CRC_MTNWR ((0x17c4))
#define DI_T5_RO_CRC_DEINT ((0x17c5))
-/* new pulldown t5,same as sc2 */
+/* new pulldown t5,function same as sc2 */
#define DI_T5_PD_RO_SUM_P ((0x20f9))
#define DI_T5_PD_RO_SUM_N ((0x20fa))
#define DI_T5_PD_RO_CNT_P ((0x20fb))
//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
//Bit 15:13, reserved
//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
-//
+//t7
+#define DI_NRWR_BADDR0 0x20a0
+//Bit 31:0 wmif_baddr_luma unsigned, default = 0x20000
+#define DI_NRWR_STRIDE0 0x20a1
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_luma unsigned, default = 0x1000;
+#define DI_NRWR_BADDR1 0x20a2
+//Bit 31:0 wmif_baddr_chroma unsigned, default = 0x20000
+#define DI_NRWR_STRIDE1 0x20a3
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_chroma unsigned, default = 0x1000;
/* post wr */
#define DIWR_DBG_AXI_CMD_CNT 0x20f0
//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
//Bit 15:13, reserved
//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
-//
+//t7
+#define DI_DIWR_BADDR0 0x20a8
+//Bit 31:0 wmif_baddr_luma unsigned, default = 0x20000
+#define DI_DIWR_STRIDE0 0x20a9
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_luma unsigned, default = 0x1000;
+#define DI_DIWR_BADDR1 0x20aa
+//Bit 31:0 wmif_baddr_chroma unsigned, default = 0x20000
+#define DI_DIWR_STRIDE1 0x20ab
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_chroma unsigned, default = 0x1000;
/* mif */
-#if 1 /* need move to here */
+/* need move to here */
#define RDMIFXN_GEN_REG 0x5400
#define RDMIFXN_CANVAS0 0x5401
#define RDMIFXN_CANVAS1 0x5402
#define RDMIFXN_GEN_REG3 0x541c
#define RDMIFXN_CFMT_CTRL 0x541d
#define RDMIFXN_CFMT_W 0x541e
-
-#endif
+//t7
+#define RDMIFXN_BADDR_Y 0x5420
+//Bit 31:0 cntl_f0_baddr_y
+//unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CB 0x5421
+//Bit 31:0 cntl_f0_baddr_cb
+//unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CR 0x5422
+//Bit 31:0 cntl_f0_baddr_cr
+//unsigned, RW, default = 0
+#define RDMIFXN_STRIDE_0 0x5423
+//Bit 31:29 reserved
+//Bit 28:16 cntl_f0_stride_cb
+//unsigned, RW, default = 256
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f0_stride_y
+//unsigned, RW, default = 256
+#define RDMIFXN_STRIDE_1 0x5424
+//Bit 31:17 reserved
+//Bit 16 cntl_f0_acc_mode
+//unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f0_stride_cr
+//unsigned, RW, default = 256
#define DI_SC2_INP_GEN_REG 0x5400
#define DI_SC2_INP_CANVAS0 0x5401
#define DI_SC2_INP_CANVAS1 0x5402
#define DI_SC2_INP_GEN_REG3 0x541c
#define DI_SC2_INP_CFMT_CTRL 0x541d
#define DI_SC2_INP_CFMT_W 0x541e
+//t7
+#define DI_T7_INP_BADDR_Y 0x5420
+#define DI_T7_INP_BADDR_CB 0x5421
+#define DI_T7_INP_BADDR_CR 0x5422
+#define DI_T7_INP_STRIDE_0 0x5423
+#define DI_T7_INP_STRIDE_1 0x5424
#define DI_SC2_CHAN2_GEN_REG 0x5480 //off = 0x80
#define DI_SC2_CHAN2_CANVAS0 0x5481
#define DI_SC2_CHAN2_GEN_REG3 0x549c
#define DI_SC2_CHAN2_CFMT_CTRL 0x549d
#define DI_SC2_CHAN2_CFMT_W 0x549e
+//t7:
+#define DI_T7_CHAN2_BADDR_Y 0x54a0
+#define DI_T7_CHAN2_BADDR_CB 0x54a1
+#define DI_T7_CHAN2_BADDR_CR 0x54a2
+#define DI_T7_CHAN2_STRIDE_0 0x54a3
+#define DI_T7_CHAN2_STRIDE_1 0x54a4
#define DI_SC2_MEM_GEN_REG 0x5500 //off = 0x100
#define DI_SC2_MEM_CANVAS0 0x5501
#define DI_SC2_MEM_CFMT_CTRL 0x551d
#define DI_SC2_MEM_CFMT_W 0x551e
+//t7:
+#define DI_T7_MEM_BADDR_Y 0x5520
+#define DI_T7_MEM_BADDR_CB 0x5521
+#define DI_T7_MEM_BADDR_CR 0x5522
+#define DI_T7_MEM_STRIDE_0 0x5523
+#define DI_T7_MEM_STRIDE_1 0x5524
+
#define DI_SC2_IF1_GEN_REG 0x5580 //off = 0x180
#define DI_SC2_IF1_CANVAS0 0x5581
#define DI_SC2_IF1_CANVAS1 0x5582
#define DI_SC2_IF1_GEN_REG3 0x559c
#define DI_SC2_IF1_CFMT_CTRL 0x559d
#define DI_SC2_IF1_CFMT_W 0x559e
+//t7
+#define DI_T7_IF1_BADDR_Y 0x55a0
+#define DI_T7_IF1_BADDR_CB 0x55a1
+#define DI_T7_IF1_BADDR_CR 0x55a2
+#define DI_T7_IF1_STRIDE_0 0x55a3
+#define DI_T7_IF1_STRIDE_1 0x55a4
#define DI_SC2_IF0_GEN_REG 0x5600 //off = 0x200
#define DI_SC2_IF0_CANVAS0 0x5601
#define DI_SC2_IF0_GEN_REG3 0x561c
#define DI_SC2_IF0_CFMT_CTRL 0x561d
#define DI_SC2_IF0_CFMT_W 0x561e
+//t7:
+#define DI_T7_IF0_BADDR_Y 0x5620
+#define DI_T7_IF0_BADDR_CB 0x5621
+#define DI_T7_IF0_BADDR_CR 0x5622
+#define DI_T7_IF0_STRIDE_0 0x5623
+#define DI_T7_IF0_STRIDE_1 0x5624
#define DI_SC2_IF2_GEN_REG 0x5680 //off = 0x280
#define DI_SC2_IF2_CANVAS0 0x5681
#define DI_SC2_IF2_GEN_REG3 0x569c
#define DI_SC2_IF2_CFMT_CTRL 0x569d
#define DI_SC2_IF2_CFMT_W 0x569e
+//t7
+#define DI_T7_IF2_BADDR_Y 0x56a0
+#define DI_T7_IF2_BADDR_CB 0x56a1
+#define DI_T7_IF2_BADDR_CR 0x56a2
+#define DI_T7_IF2_STRIDE_0 0x56a3
+#define DI_T7_IF2_STRIDE_1 0x56a4
+
+//==========================================================================
+// VD_TOP for t7 each afbc add xx38
+//==========================================================================
+#define AFBCDM_VDTOP_CTRL0 0x5438
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
/*afbcd*/
#define AFBCDM_ENABLE 0x5440
#define AFBCDM_VD1_FGRAIN_PARAM_ADDR 0x4878
#define AFBCDM_VD1_FGRAIN_PARAM_DATA 0x4879
+//for t7:
+#define AFBCDM_INP_CTRL0 0x5438
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
/*afbcd add*/
#define AFBCDM_INP_ENABLE 0x5440
#define AFBCDM_INP_MODE 0x5441
#define AFBCDM_INP_FGRAIN_PARAM_ADDR 0x5478
#define AFBCDM_INP_FGRAIN_PARAM_DATA 0x5479
+//for t7:
+#define AFBCDM_CHAN2_CTRL0 0x54b8
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
#define AFBCDM_CHAN2_ENABLE 0x54c0 //0x80
#define AFBCDM_CHAN2_MODE 0x54c1
#define AFBCDM_CHAN2_SIZE_IN 0x54c2
#define AFBCDM_CHAN2_FGRAIN_PARAM_ADDR 0x54f8
#define AFBCDM_CHAN2_FGRAIN_PARAM_DATA 0x54f9
+//for t7:
+#define AFBCDM_MEM_CTRL0 0x5538
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
#define AFBCDM_MEM_ENABLE 0x5540 /*0x100*/
#define AFBCDM_MEM_MODE 0x5541
#define AFBCDM_MEM_SIZE_IN 0x5542
#define AFBCDM_MEM_FGRAIN_PARAM_ADDR 0x5578
#define AFBCDM_MEM_FGRAIN_PARAM_DATA 0x5579
+//for t7:
+#define AFBCDM_IF1_CTRL0 0x55b8
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
#define AFBCDM_IF1_ENABLE 0x55c0 /*0x180*/
#define AFBCDM_IF1_MODE 0x55c1
#define AFBCDM_IF1_SIZE_IN 0x55c2
#define AFBCDM_IF1_FGRAIN_PARAM_ADDR 0x55f8
#define AFBCDM_IF1_FGRAIN_PARAM_DATA 0x55f9
+//for t7:
+#define AFBCDM_IF0_CTRL0 0x5638
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
#define AFBCDM_IF0_ENABLE 0x5640 /*0x200*/
#define AFBCDM_IF0_MODE 0x5641
#define AFBCDM_IF0_SIZE_IN 0x5642
#define AFBCDM_IF0_FGRAIN_PARAM_ADDR 0x5678
#define AFBCDM_IF0_FGRAIN_PARAM_DATA 0x5679
+//for t7:
+#define AFBCDM_IF2_CTRL0 0x56b8
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel
+// unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas
+// unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+
#define AFBCDM_IF2_ENABLE 0x56c0
#define AFBCDM_IF2_MODE 0x56c1
#define AFBCDM_IF2_SIZE_IN 0x56c2
#define DI_POST_SEC_IN 0x2011
#define DI_VIU_DATA_SEC 0x1A50
+//t7
+#define CONTRD_BADDR 0x3729
+#define CONT2RD_BADDR 0x372a
+#define MTNRD_BADDR 0x372b
+#define MCVECRD_BADDR 0x372c
+#define MCINFRD_BADDR 0x372d
+#define CONTWR_BADDR 0x3734
+#define CONTWR_STRIDE 0x3735
+#define MTNWR_BADDR 0x3736
+#define MTNWR_STRIDE 0x3737
+#define MCVECWR_BADDR 0x372e
+#define MCVECWR_STRIDE 0x372f
+#define MCINFWR_BADDR 0x37ce
+#define MCINFWR_STRIDE 0x37cf
+#define NRDSWR_BADDR 0x37fd
+#define NRDSWR_STRIDE 0x37fe
+
#endif /*__DI_REG_V3_H__*/
pgprot_t pgprot;
int i;
- if (!PageHighMem(phys_to_page(phys)))
+ if (!PageHighMem(phys_to_page(phys))) {
+ *bflg = false;
return phys_to_virt(phys);
+ }
if (offset)
npages++;
pages = vmalloc(sizeof(struct page *) * npages);
PR_ERR("%s:%d\n", __func__, idat->header.index);
else
dbg_mem2("mcinfo v [%d], ok 0x%px\n",
- idat->header.index,
- idat->mcinfo_adr_v);
+ idat->header.index,
+ idat->mcinfo_adr_v);
}
void dim_mcinfo_v_release_idat(struct dim_iat_s *idat)
PR_INF("%s [%d], ok\n", __func__, idat->header.index);
}
}
-
#endif
+
/********************************************
* mem
*******************************************/
#endif
bool dim_mm_alloc_api(int cma_mode, size_t count, struct dim_mm_s *o,
- bool tvp_flg)
+ bool tvp_flg)
{
bool ret = false;
#ifdef CONFIG_CMA
struct dim_mm_s omm;
bool flg_release;
unsigned int length;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int size_p;
+ enum EDI_TOP_STATE chst;
//struct di_dev_s *de_devp = get_dim_de_devp();
//blk_buf->size_page = 0;
blk_buf->flg_alloc = false;
blk_buf->flg.d32 = 0;
+ blk_buf->sct = NULL;
+ blk_buf->sct_keep = 0xff;
qbuf_in(pbufq, QBF_BLK_Q_IDLE, index);
cnt++;
fcmd->sum_alloc--;
break;
case ECMD_BLK_ALLOC:
/* alloc */
- dbg_mem2("%s:ch[%d] alloc:nub[%d],size[0x%x]\n",
- __func__, ch, cmd->nub, size_p);
+ chst = dip_chst_get(ch);
+ dbg_mem2("%s:ch[%d] alloc:nub[%d],size[0x%x],top_sts[%d]\n",
+ __func__, ch, cmd->nub, size_p, chst);
cnt = 0;
for (i = 0; i < cmd->nub; i++) {
if (qbuf_is_empty(pbufq, QBF_BLK_Q_IDLE))
blk_buf->header.index);
break;
}
- #if 1
- //mdelay(200);
- //PR_INF("sleep 100\n");
- #else
- dma_sync_single_for_device
- (de_devp->dev,
- omm.addr,
- cmd->flg.b.page << PAGE_SHIFT,
- DMA_TO_DEVICE);
- #endif
+
blk_buf->mem_start = omm.addr;
blk_buf->pages = omm.ppage;
blk_buf->flg.d32 = cmd->flg.d32;
blk_buf->flg.b.tvp = cmd->flg.b.tvp;//omm.flg;
blk_buf->flg_alloc = true;
blk_buf->reg_cnt = pch->sum_reg_cnt;
+ blk_buf->sct = NULL;
+ blk_buf->sct_keep = 0xff;
+ blk_buf->pat_buf = NULL;
if (blk_buf->flg.b.is_i)
mm->sts.num_local++;
else
bool di_pst_afbct_check(struct di_ch_s *pch)
{
//bool ret;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
struct di_dat_s *pdat;
bool di_i_dat_check(struct di_ch_s *pch)
{
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
struct di_dat_s *idat = get_idat(pch);
unsigned int nub)
{
struct di_ch_s *pch;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned long addr;
struct di_dat_s *pdat;
if ((addr + mm->cfg.size_pafbct_one) >
pdat->addr_end) {
PR_ERR("%s:addr is overflow 0x%lx, 0x%lx\n",
- __func__, (addr + mm->cfg.size_pafbct_one),
- pdat->addr_end);
- addr = pdat->addr_st;
+ __func__, (addr + mm->cfg.size_pafbct_one),
+ pdat->addr_end);
+ addr = pdat->addr_st;
}
dbg_mem2("%s:nub[%d], addr[0x%lx]\n", __func__, nub, addr);
return addr;
static void pat_set_addr(struct di_ch_s *pch)
{
int i;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
unsigned long addr;
bool ret;
}
}
+void pat_clear_mem(struct device *dev,
+ struct di_ch_s *pch,
+ struct dim_pat_s *pat_buf)
+{
+ unsigned int pat_size;
+ struct div2_mm_s *mm;
+
+ if ((!dev) ||
+ (!pch) ||
+ (!pat_buf) ||
+ (!pat_buf->vaddr)) {
+ PR_ERR("%s\n", __func__);
+ return;
+ }
+ mm = dim_mm_get(pch->ch_id);
+ pat_size = mm->cfg.size_pafbct_one;
+ dma_sync_single_for_device(dev,
+ pat_buf->mem_start,//src_phys,//
+ pat_size,
+ DMA_TO_DEVICE);
+ //dbg_sct("%s:%d:0x%x\n", __func__, pat_buf->header.index, pat_size);
+ memset(pat_buf->vaddr, 0, pat_size);
+
+ dma_sync_single_for_device(dev,
+ pat_buf->mem_start,//src_phys,//
+ pat_size,
+ DMA_TO_DEVICE);
+}
+
+void pat_frash(struct device *dev,
+ struct di_ch_s *pch,
+ struct dim_pat_s *pat_buf)
+{
+ unsigned int pat_size;
+ struct div2_mm_s *mm;
+
+ if ((!dev) ||
+ (!pch) ||
+ (!pat_buf) ||
+ (!pat_buf->vaddr)) {
+ PR_ERR("%s\n", __func__);
+ return;
+ }
+
+ mm = dim_mm_get(pch->ch_id);
+ pat_size = mm->cfg.size_pafbct_one;
+ dma_sync_single_for_device(dev,
+ pat_buf->mem_start,//src_phys,//
+ pat_size,
+ DMA_TO_DEVICE);
+}
+
/************************************************
* afbc_table
* afbc_info
static void iat_set_addr(struct di_ch_s *pch)
{
int i;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
unsigned int ch;
unsigned long addr_st_afbct/*, addr_st_mcinfo*/;
// unsigned long addr_afbct, addr_mc;
struct di_dat_s *idat;
struct blk_flg_s flgs;
unsigned int idat_size;
+ //for cma:
+ struct dim_mm_s omm;
+ bool ret;
idat = get_idat(pch);
if (idat->flg_alloc)
return;
flgs.d32 = flg;
+#ifdef USE_KALLOC //use kzalloc:
idat_size = flgs.b.page << PAGE_SHIFT;
if (!idat_size) {
idat->addr_st = virt_to_phys(idat->virt);
idat->addr_end = idat->addr_st + idat_size;
+#else //usd cma:
+ idat_size = flgs.b.page;
+
+ if (!idat_size) {
+ PR_INF("%s:no size\n", __func__);
+ return;
+ }
+ ret = mm_cma_alloc(NULL, idat_size, &omm);
+
+ if (!ret) {
+ PR_ERR("%s:cma\n", __func__);
+ return;
+ }
+ idat->addr_st = omm.addr;
+ //idat->ppage = omm.ppage;
+ idat->virt = omm.ppage;
+ idat->cnt = idat_size;
+ idat->addr_end = idat->addr_st + (idat_size << PAGE_SHIFT);
+#endif
+
idat->flg.d32 = flg;
idat->flg_alloc = 1;
- PR_INF("%s:size:%d,0x%px,0x%lx\n",
+ PR_INF("%s:cma size:%d,0x%px,0x%lx\n",
__func__,
idat_size, idat->virt, idat->addr_st);
iat_set_addr(pch);
struct di_dat_s *pdat;
struct blk_flg_s flgs;
unsigned int dat_size;
+ //for cma:
+ struct dim_mm_s omm;
+ bool ret;
pdat = get_pst_afbct(pch);
+
flgs.d32 = flg;
+#ifdef USE_KALLOC
dat_size = flgs.b.page << PAGE_SHIFT;
if (pdat->flg_alloc || (!dat_size)) {
pdat->addr_st = virt_to_phys(pdat->virt);
pdat->addr_end = pdat->addr_st + dat_size;
+#else
+ dat_size = flgs.b.page;
+
+ if (pdat->flg_alloc || (!dat_size)) {
+ PR_INF("%s:not alloc:%d,0x%x\n",
+ __func__,
+ pdat->flg_alloc, flg);
+ return;
+ }
+ ret = mm_cma_alloc(NULL, dat_size, &omm);
+
+ if (!ret) {
+ PR_ERR("%s:cma\n", __func__);
+ return;
+ }
+ pdat->addr_st = omm.addr;
+ //pdat->ppage = omm.ppage;
+ pdat->virt = omm.ppage;
+ pdat->cnt = dat_size;
+ pdat->addr_end = pdat->addr_st + (dat_size << PAGE_SHIFT);
+#endif
pdat->flg.d32 = flg;
pdat->flg_alloc = 1;
- PR_INF("%s:size:%d,0x%px,0x%lx\n",
+ PR_INF("%s:cma:size:%d,0x%px,0x%lx\n",
__func__,
dat_size, pdat->virt, pdat->addr_st);
dat = get_idat(pch);
if (dat->flg_alloc) {
+#ifdef USE_KALLOC
kfree(dat->virt);
+#else
+ dma_release_from_contiguous(NULL,
+ (struct page *)dat->virt,
+ dat->cnt);
+#endif
dat->virt = NULL;
memset(dat, 0, sizeof(*dat));
}
dat = get_pst_afbct(pch);
if (dat->flg_alloc) {
+#ifdef USE_KALLOC
kfree(dat->virt);
+#else
+ dma_release_from_contiguous(NULL,
+ (struct page *)dat->virt,
+ dat->cnt);
+#endif
dat->virt = NULL;
memset(dat, 0, sizeof(*dat));
}
static void dim_buf_set_addr(unsigned int ch, struct di_buf_s *buf_p)
{
/*need have set nr_addr*/
- struct di_mm_s *mm = dim_mm_get(ch);
+ struct div2_mm_s *mm = dim_mm_get(ch);
struct afbce_map_s afbce_map;
struct di_dev_s *devp = get_dim_de_devp();
//struct di_pre_stru_s *ppre = get_pre_stru(channel);
if (buf_p->buf_is_i) {
//buf_p->afbct_adr = buf_p->afbc_adr + mm->cfg.afbci_size;
//buf_p->dw_adr = buf_p->afbct_adr + mm->cfg.afbct_size;
-#ifdef CFG_BUF_ALLOC_SP
+
if (mm->cfg.size_idat_one) {
iat_buf = qiat_out_ready(pch);
if (iat_buf) {
buf_p->afbc_adr = buf_p->adr_start;
buf_p->dw_adr = buf_p->afbc_adr + mm->cfg.afbci_size;
buf_p->nr_adr = buf_p->dw_adr + mm->cfg.dw_size;
-
+ buf_p->buf_hsize = mm->cfg.ibuf_hsize;
/* count afbct setting and crc */
if (dim_afds() && mm->cfg.afbci_size) {
afbce_map.bodyadd = buf_p->nr_adr;
//buf_p->insert_adr = buf_p->mcinfo_adr + mm->cfg.mcinfo_size;
/*}*/
-#else
- buf_p->afbct_adr = buf_p->adr_start;
- buf_p->afbc_adr = buf_p->afbct_adr + mm->cfg.afbct_size;
- buf_p->dw_adr = buf_p->afbc_adr + mm->cfg.afbci_size;
- buf_p->nr_adr = buf_p->dw_adr + mm->cfg.dw_size;
- buf_p->nr_size = mm->cfg.nr_size;
- if (dim_afds() && mm->cfg.afbct_size) {
- afbce_map.bodyadd = buf_p->nr_adr;
- afbce_map.tabadd = buf_p->afbct_adr;
- afbce_map.size_buf = mm->cfg.nr_size;
- afbce_map.size_tab = mm->cfg.afbct_size;
-
- buf_p->afbc_crc =
- dim_afds()->int_tab(&devp->pdev->dev,
- &afbce_map);
- } else {
- buf_p->afbc_crc = 0;
- }
-
- buf_p->tab_size = mm->cfg.afbct_size;
- buf_p->mtn_adr = buf_p->nr_adr +
- mm->cfg.nr_size;
- buf_p->cnt_adr = buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size;
- if (dim_get_mcmem_alloc()) {
- buf_p->mcvec_adr = buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size +
- mm->cfg.count_size;
- buf_p->mcinfo_adr =
- buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size +
- mm->cfg.count_size +
- mm->cfg.mv_size;
- dim_mcinfo_v_alloc(buf_p, mm->cfg.mcinfo_size);
-
- buf_p->insert_adr =
- buf_p->mcinfo_adr + mm->cfg.mcinfo_size;
- }
-#endif
buf_p->nr_size = mm->cfg.nr_size;
buf_p->tab_size = mm->cfg.afbct_size;
dbg_mem2("\t:mcinfo_adr\t[0x%lx]\n", buf_p->mcinfo_adr);
- } else {
+ } else if (buf_p->blk_buf) {
//buf_p->afbct_adr = buf_p->afbc_adr + mm->cfg.pst_afbci_size;
-#ifdef CFG_BUF_ALLOC_SP
- if (mm->cfg.dat_pafbct_flg.b.page) {
+
+ if (buf_p->blk_buf &&
+ buf_p->blk_buf->flg.b.typ == EDIM_BLK_TYP_PSCT) {
+ buf_p->afbc_adr = buf_p->adr_start;
+ buf_p->afbct_adr = 0;
+ buf_p->blk_buf->pat_buf = NULL;
+ } else if (mm->cfg.dat_pafbct_flg.b.page) {
pat_buf = qpat_out_ready(pch);
if (pat_buf) {
addr_afbct = pat_buf->mem_start;
- buf_p->pat_buf = pat_buf;
+ //buf_p->pat_buf = pat_buf;
+ buf_p->blk_buf->pat_buf = pat_buf;
+ pat_buf->flg_mode = 0;
} else {
- buf_p->pat_buf = NULL;
+ buf_p->blk_buf->pat_buf = NULL;
}
buf_p->afbct_adr = addr_afbct;
buf_p->afbc_adr = buf_p->adr_start;
} else {
buf_p->afbct_adr = buf_p->adr_start;
buf_p->afbc_adr = buf_p->adr_start;
- buf_p->pat_buf = NULL;
+ buf_p->blk_buf->pat_buf = NULL;
}
dbg_mem2("%s:pst:flg_afbct[%d], addr[0x%lx]\n",
__func__,
mm->cfg.dat_pafbct_flg.d32, addr_afbct);
-#else
- buf_p->afbct_adr = buf_p->adr_start;
- buf_p->afbc_adr = buf_p->afbct_adr + mm->cfg.pst_afbct_size;
- buf_p->pat_buf = NULL;
-#endif
+
buf_p->dw_adr = buf_p->afbc_adr + mm->cfg.pst_afbci_size;
buf_p->nr_adr = buf_p->dw_adr + mm->cfg.dw_size;
buf_p->tab_size = mm->cfg.pst_afbct_size;
buf_p->nr_size = mm->cfg.pst_buf_size;
-
- if (dim_afds() && mm->cfg.pst_afbct_size) {
+ buf_p->buf_hsize = mm->cfg.pbuf_hsize;
+
+ if (buf_p->blk_buf &&
+ buf_p->blk_buf->flg.b.typ == EDIM_BLK_TYP_PSCT) {
+ /*sct*/
+ //pat_set_vaddr(buf_p->pat_buf,
+ // mm->cfg.pst_afbct_size);
+ buf_p->afbc_crc = 0;
+ buf_p->nr_adr = 0;
+ } else if (dim_afds() && mm->cfg.pst_afbct_size) {
afbce_map.bodyadd = buf_p->nr_adr;
afbce_map.tabadd = buf_p->afbct_adr;
afbce_map.size_buf = mm->cfg.pst_buf_size;
#endif
}
+bool dim_blk_tvp_is_sct(struct dim_mm_blk_s *blk_buf)
+{
+ if ((blk_buf->flg.b.typ & 0x7) == EDIM_BLK_TYP_PSCT)
+ return true;
+ return false;
+}
+
+bool dim_blk_tvp_is_out(struct dim_mm_blk_s *blk_buf)
+{
+ if ((blk_buf->flg.b.typ & 0x8) == EDIM_BLK_TYP_POUT)
+ return true;
+ return false;
+}
+
void bufq_mem_clear(struct di_ch_s *pch)
{
struct buf_que_s *pbf_mem;
bool ret = true;
union q_buf_u q_buf;
bool flg_q;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
struct dim_mm_blk_s *blk_buf;
// struct di_buf_s *di_buf = NULL;
unsigned int ch;
return ret;
}
+void di_buf_no2wait(struct di_ch_s *pch)
+{
+ unsigned int len, ch;
+ int i;
+ struct di_buf_s *di_buf;
+
+ ch = pch->ch_id;
+ len = di_que_list_count(ch, QUE_PST_NO_BUF);
+ if (!len)
+ return;
+ if (len > 11)
+ len = 11;
+ for (i = 0; i < len; i++) {
+ di_buf = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF);
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ }
+
+ PR_INF("%s:%d\n", __func__, len);
+}
+
+/*ary note: for new interface out buffer */
+bool mem_cfg_pst(struct di_ch_s *pch)
+{
+ unsigned int len, ch, len_pst;
+ struct di_buf_s *di_buf;
+ struct di_buffer *buffer;
+ struct div2_mm_s *mm;
+
+ dbg_dt("%s:1\n", __func__);
+ if (!dip_itf_is_ins_exbuf(pch)) {
+ dbg_dt("%s:5\n", __func__);
+ return false;
+ }
+ ch = pch->ch_id;
+
+ len = di_que_list_count(ch, QUE_PST_NO_BUF_WAIT);
+ dbg_dt("%s:2[%d]\n", __func__, len);
+ if (!len)
+ return false;
+
+ len_pst = npst_cnt(pch);
+ dbg_dt("%s:3[%d]\n", __func__, len_pst);
+ if (!len_pst)
+ return false;
+ dbg_dt("%s:4\n", __func__);
+
+ di_buf = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF_WAIT);
+ buffer = npst_qout(pch);
+ if (di_buf->blk_buf) {
+ //@ary_note todo
+ PR_ERR("%s:have blk?", __func__);
+ } else {
+ /* @ary_note: */
+ di_buf->c.buffer = buffer;
+ di_buf->adr_start = buffer->vf->canvas0_config[0].phy_addr;
+ di_buf->nr_adr = di_buf->adr_start;
+ }
+ di_buf->canvas_config_flag = 1;
+ mm = dim_mm_get(ch);
+ di_buf->canvas_width[NR_CANVAS] = mm->cfg.pst_cvs_w;
+ di_buf->flg_null = 0;
+ pch->sum_ext_buf_in++;
+ di_que_in(ch, QUE_POST_FREE, di_buf);
+ //dbg_log_pst_buffer(di_buf, 1);
+ return true;
+}
+
+void mem_resize_buf(struct di_ch_s *pch, struct di_buf_s *di_buf)
+{
+ struct div2_mm_s *mm;
+ struct di_buffer *buf;
+ unsigned int TMPWIDTH;
+
+ //struct vframe_s *vfm;
+
+ if (dip_itf_is_ins_exbuf(pch)) {
+ buf = (struct di_buffer *)di_buf->c.buffer;
+ TMPWIDTH = buf->vf->canvas0_config[0].width;
+ if (buf && buf->vf) {
+ di_buf->canvas_width[NR_CANVAS] = TMPWIDTH;
+ return;
+ }
+ PR_ERR("%s:\n", __func__);
+ }
+
+ mm = dim_mm_get(pch->ch_id);
+ di_buf->canvas_width[NR_CANVAS] = mm->cfg.pst_cvs_w;
+}
+
bool mem_cfg(struct di_ch_s *pch)
{
struct di_mtask *tsk = get_mtask();
// bool ret;
union q_buf_u q_buf;
// bool flg_q;
- struct di_mm_s *mm;
+ struct div2_mm_s *mm;
struct dim_mm_blk_s *blk_buf;
struct di_buf_s *di_buf = NULL;
unsigned int ch;
di_buf->jiff = jiffies;
/* to in used */
qbufp_in(pbf_mem, QBF_MEM_Q_IN_USED, q_buf);
- //queue_in(ch, di_buf, QUEUE_LOCAL_FREE);
+ queue_in(ch, di_buf, QUEUE_LOCAL_FREE);
- di_que_in(ch, QUE_PRE_NO_BUF_WAIT, di_buf);
+ //di_que_in(ch, QUE_PRE_NO_BUF_WAIT, di_buf);
cnt++;
length--;
}
/* to in used */
qbufp_in(pbf_mem, QBF_MEM_Q_IN_USED, q_buf);
//di_que_in(ch, QUE_POST_FREE, di_buf);
- di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ if (dim_blk_tvp_is_out(blk_buf)) /* new interface */
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ else if (dim_blk_tvp_is_sct(blk_buf))
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ else
+ di_que_in(ch, QUE_POST_FREE, di_buf);
cnt++;
length_pst--;
}
bool ret;
union q_buf_u q_buf;
bool flg_q;
- struct di_mm_s *mm = dim_mm_get(pch->ch_id);
+ struct div2_mm_s *mm = dim_mm_get(pch->ch_id);
struct dim_mm_blk_s *blk_buf;
struct di_buf_s *di_buf = NULL;
unsigned int ch;
/* to in used */
qbufp_in(pbf_mem, QBF_MEM_Q_IN_USED, q_buf);
- //queue_in(ch, di_buf, QUEUE_LOCAL_FREE);
- di_que_in(ch, QUE_PRE_NO_BUF_WAIT, di_buf);
+ queue_in(ch, di_buf, QUEUE_LOCAL_FREE);
+ //di_que_in(ch, QUE_PRE_NO_BUF_WAIT, di_buf);
cnt++;
length--;
}
/* to in used */
qbufp_in(pbf_mem, QBF_MEM_Q_IN_USED, q_buf);
//di_que_in(ch, QUE_POST_FREE, di_buf);
- di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ if (blk_buf->flg.b.typ == EDIM_BLK_TYP_PSCT)
+ di_que_in(ch, QUE_PST_NO_BUF_WAIT, di_buf);
+ else
+ di_que_in(ch, QUE_POST_FREE, di_buf);
cnt++;
length--;
}
return true;
}
+#ifdef HIS_CODE
void mem_cfg_realloc_wait(struct di_ch_s *pch)
{
unsigned int length;
int i;
ch = pch->ch_id;
+
/* pre */
length = di_que_list_count(ch, QUE_PRE_NO_BUF_WAIT);
if (length) {
}
}
}
+#endif
void mem_release_one_inused(struct di_ch_s *pch, struct dim_mm_blk_s *blk_buf)
{
struct buf_que_s *pbf_blk, *pbf_mem;
bool ret;
union q_buf_u ubuf;
+ struct dim_sct_s *sct;
+ bool f_sctkeep = false;
+ struct dim_pat_s *pat_buf;
if (!blk_buf) {
PR_WARN("%s:none\n", __func__);
return;
}
+
+ if (blk_buf->sct_keep != 0xff) {
+ codec_mm_keeper_unmask_keeper(blk_buf->sct_keep, 1);
+ PR_INF("%s:sct_keep[0x%x]\n", "release", blk_buf->sct_keep);
+ blk_buf->sct_keep = 0xff;
+ f_sctkeep = true;
+ }
+
+ if (blk_buf->sct) {
+ sct = (struct dim_sct_s *)blk_buf->sct;
+ sct->pat_buf->flg_mode = 0;
+ qsct_used_some_to_recycle(pch, sct);
+ blk_buf->sct = NULL;
+ blk_buf->pat_buf = NULL;
+ } else if (blk_buf->pat_buf) {
+ /* recycl pat*/
+ pat_buf = (struct dim_pat_s *)blk_buf->pat_buf;
+ if (blk_buf->sct_keep) {
+ pat_buf->flg_mode = 0;
+ pat_release_vaddr(pat_buf);
+ }
+ qpat_in_ready(pch, pat_buf);
+ blk_buf->pat_buf = NULL;
+ }
pbf_blk = &pch->blk_qb;
pbf_mem = &pch->mem_qb;
if (!ret) {
PR_WARN("%s:no [%d] in in_used\n",
__func__, blk_buf->header.index);
+ dump_stack();
+// dbg_q_listid_print(pbf_blk);
return;
}
}
}
+#ifdef MARK_HIS
void mem_release_keep_back(struct di_ch_s *pch)
{
// struct buf_que_s *pbf_blk, *pbf_mem;
for (itmp = 0; itmp < psize; itmp++) {
p = pw_qindex_2_buf(ch, tmpa[itmp]);
- if (p->pat_buf) {
- qpat_in_ready(pch, (struct dim_pat_s *)p->pat_buf);
- p->pat_buf = NULL;
- }
+
mem_release_one_inused(pch, p->blk_buf);
di_que_out(ch, QUE_POST_KEEP_BACK, p);
di_que_out_not_fifo(ch, QUE_POST_KEEP, p);
}
dbg_mem2("%s:[%d]\n", __func__, cnt);
}
+#else
+/* @ary_note: only one caller, release all keep back buffer */
+/* return: release nub */
+unsigned int mem_release_keep_back(struct di_ch_s *pch)
+{
+// struct buf_que_s *pbf_blk, *pbf_mem;
+
+// unsigned int tmpa[MAX_FIFO_SIZE];
+// unsigned int psize, itmp;
+// struct di_buf_s *p;
+ //struct di_dev_s *de_devp = get_dim_de_devp();
+// int retr;
+// ulong flags = 0;
+ unsigned int cnt = 0;
+// unsigned int ch;
+ unsigned int len_keep;
+ int i;
+ struct qs_cls_s *pq;
+ bool ret;
+ union q_buf_u pbuf;
+ struct dim_ndis_s *ndis;
+
+ pq = &pch->ndis_que_kback;
+
+ len_keep = pq->ops.count(NULL, pq);
+ if (!len_keep)
+ return 0;
+ for (i = 0; i < len_keep; i++) {
+ ret = pq->ops.out(NULL, pq, &pbuf);
+ if (!ret) {
+ PR_ERR("%s:o err:%d\n", __func__, i);
+ continue;
+ }
+ ndis = (struct dim_ndis_s *)pbuf.qbc;
+ if (!ndis) {
+ PR_ERR("%s:no ndis ?:%d\n", __func__, i);
+ continue;
+ }
+ if (!ndis->c.blk) {
+ PR_ERR("%s:no ndis blk?:%d\n", __func__, i);
+ continue;
+ }
+ PR_INF("%s:keep back out %d\n", __func__, ndis->header.index);
+
+ mem_release_one_inused(pch, ndis->c.blk);
+ ndis_move_keep2idle(pch, ndis);
+ cnt++;
+ }
+ dbg_mem2("%s:[%d]\n", __func__, cnt);
+ return cnt;
+}
+#endif
+/* @ary_note: process keep back buffer when ready */
+/* @ary_note: only one caller */
+/* @ary_note: */
+void dim_post_keep_back_recycle(struct di_ch_s *pch)
+{
+ unsigned int cnt;
+ struct div2_mm_s *mm = dim_mm_get(pch->ch_id);
+
+ cnt = mem_release_keep_back(pch);
+ mm->sts.flg_realloc += cnt;
+}
-void mem_release(struct di_ch_s *pch)
+/* @ary_note: unreg buf only */
+void mem_release(struct di_ch_s *pch,
+ struct dim_mm_blk_s **blks, unsigned int blk_nub)
{
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize, itmp;
- struct di_buf_s *p;
+ //unsigned int tmpa[MAX_FIFO_SIZE];
+ //unsigned int psize, itmp;
+ //struct di_buf_s *p;
unsigned int blk_mst;
unsigned int pat_mst;
unsigned int ch = pch->ch_id;
unsigned int length;
// unsigned int ch = pch->ch_id;
struct di_buf_s *pbuf_local;
- struct di_mm_s *mm = dim_mm_get(ch);
+ struct div2_mm_s *mm = dim_mm_get(ch);
int i;
struct di_buf_s *di_buf;
struct dim_pat_s *pat_buf;
+ struct dim_mm_blk_s *blk_buf;
+ struct dim_sct_s *sct;
/* clear local */
- #if 1 //def HIS_CODE
pbuf_local = get_buf_local(ch);
for (i = 0; i < mm->cfg.num_local; i++) {
di_buf = &pbuf_local[i];
if (di_buf->mcinfo_alloc_flg)
dim_mcinfo_v_release(di_buf);
}
- #endif
+// #endif
/***********/
/* mask blk */
blk_mst = 0;
pat_mst = 0;
- di_que_list(ch, QUE_POST_KEEP, &tmpa[0], &psize);
- dbg_keep("post_keep: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pw_qindex_2_buf(ch, tmpa[itmp]);
- dbg_keep("\ttype[%d],index[%d]\n", p->type, p->index);
- if (p->type != VFRAME_TYPE_POST)
- continue;
+ //di_que_list(ch, QUE_POST_KEEP, &tmpa[0], &psize);
+ //dbg_keep("post_keep: curr(%d)\n", psize);
- if (!p->blk_buf) {
- PR_ERR("%s:no blk_buf?[%d][%d]\n",
- __func__,
- p->type,
- p->index);
- continue;
+ for (i = 0; i < blk_nub; i++) {
+ blk_buf = blks[i];
+ if (!blk_buf) {
+ PR_ERR("%s:null %d\n", __func__, i);
+ break;
}
- bset(&blk_mst, p->blk_buf->header.index);
+ bset(&blk_mst, blk_buf->header.index);
/* 2010-10-05 */
- if (p->pat_buf) {
- pat_buf = (struct dim_pat_s *)p->pat_buf;
+ if (blk_buf->pat_buf) {
+ pat_buf = (struct dim_pat_s *)blk_buf->pat_buf;
bset(&pat_mst, pat_buf->header.index);
}
+ /* sct */
+ if (blk_buf->sct) {
+ sct = (struct dim_sct_s *)blk_buf->sct;
+ blk_buf->sct_keep = sct_keep(pch, sct);
+ sct->flg_act.b.tab_keep = 1;
+ qsct_used_some_to_recycle(pch, sct);
+ blk_buf->sct = NULL;
+ }
}
qpat_in_ready_msk(pch, pat_mst);
continue;
}
//qbufp_in(pbf_blk, QBF_BLK_Q_RCYCLE2, bufq);
+ blk_buf = (struct dim_mm_blk_s *)bufq.qbc;
+ if (blk_buf->sct) {
+ sct = (struct dim_sct_s *)blk_buf->sct;
+ qsct_used_some_to_recycle(pch, sct);
+ blk_buf->sct = NULL;
+ blk_buf->pat_buf = NULL;
+ }
qbufp_in(pbf_mem, QBF_MEM_Q_RECYCLE, bufq);
cnt++;
return true;
}
+unsigned int mem_release_sct_wait(struct di_ch_s *pch)
+{
+ struct di_buf_s *p = NULL;
+ unsigned int ch;
+ unsigned int length, rls_pst;
+
+ ch = pch->ch_id;
+ /* post */
+ length = di_que_list_count(ch, QUE_PST_NO_BUF_WAIT);
+ rls_pst = length;
+ dbg_mem2("%s: pst free[%d]\n", __func__, rls_pst);
+ while (length) {
+ p = di_que_out_to_di_buf(ch, QUE_PST_NO_BUF_WAIT);
+ if (!p) {
+ PR_ERR("%s:post out:%d\n", __func__, length);
+ break;
+ }
+
+ mem_release_one_inused(pch, p->blk_buf);
+ dbg_mem2("%s:pst:[%d]\n", __func__, p->index);
+ p->blk_buf = NULL;
+ di_que_in(ch, QUE_PST_NO_BUF, p);
+ length--;
+ }
+ return rls_pst;
+}
+
unsigned int mem_release_free(struct di_ch_s *pch)
{
struct di_buf_s *p = NULL;
PR_ERR("%s:post out:%d\n", __func__, length);
break;
}
- if (p->pat_buf) {
- qpat_in_ready(pch, (struct dim_pat_s *)p->pat_buf);
- p->pat_buf = NULL;
- }
-
mem_release_one_inused(pch, p->blk_buf);
dbg_mem2("%s:pst:[%d]\n", __func__, p->index);
p->blk_buf = NULL;
.type = Q_T_FIFO,
.lock = 0,
},
+ [QBF_PAT_Q_READY_SCT] = {
+ .name = "QBF_PAT_READY_SCT",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
[QBF_PAT_Q_IN_USED] = {
.name = "QBF_PAT_Q_IN_USED",
.type = Q_T_FIFO,
int i;
if (!pch) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
return;
}
PR_INF("%s:\n", __func__);
if (!pch) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
return;
}
pbufq = &pch->pat_qb;
return pat_buf;
}
+/* ready to in ready_sct ???*/
+struct dim_pat_s *qpat_out_ready_sct(struct di_ch_s *pch)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_pat_s *pat_buf;
+
+ pbufq = &pch->pat_qb;
+
+ ret = qbuf_out(pbufq, QBF_PAT_Q_READY, &index);
+ if (!ret)
+ return NULL;
+ q_buf = pbufq->pbuf[index];
+ pat_buf = (struct dim_pat_s *)q_buf.qbc;
+ qbuf_in(pbufq, QBF_PAT_Q_IN_USED, index);
+
+ return pat_buf;
+}
+
/* in_used to ready*/
bool qpat_in_ready(struct di_ch_s *pch, struct dim_pat_s *pat_buf)
{
q_buf.qbc = &pat_buf->header;
ret = qbuf_out_some(pbufq, QBF_PAT_Q_IN_USED, q_buf);
- if (!ret)
- PR_ERR("%s:\n", __func__);
+ if (!ret) {
+ PR_ERR("%s:[%d]\n", __func__, pat_buf->header.index);
+ dbg_q_listid_print(pbufq);
+ dump_stack();
+ return false;
+ }
ret = qbuf_in(pbufq, QBF_PAT_Q_READY, pat_buf->header.index);
if (!ret)
return false;
break;
}
pat_buf = (struct dim_pat_s *)pbufq->pbuf[index].qbc;
- if (bget(&msk, index))
+ if (bget(&msk, index)) {
qbuf_in(pbufq, QBF_PAT_Q_IN_USED,
pat_buf->header.index);
- else
+ } else {
+ if (pat_buf->vaddr)
+ pat_release_vaddr(pat_buf);
qbuf_in(pbufq, QBF_PAT_Q_READY,
pat_buf->header.index);
+ }
}
+ PR_INF("%s:0x%x\n", __func__, msk);
if (err)
return false;
return true;
}
-/********************************************/
-/* local buffer exit table */
-static const struct que_creat_s qbf_iat_cfg_q[] = {//TST_Q_IN_NUB
- [QBF_IAT_Q_IDLE] = {
- .name = "QBF_IAT_IDLE",
- .type = Q_T_FIFO,
- .lock = 0,
- },
- [QBF_IAT_Q_READY] = {
- .name = "QBF_IAT_READY",
+void dbg_pat(struct seq_file *s, struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ struct dim_pat_s *pat_buf;
+ int i;
+ char *splt = "---------------------------";
+
+ pbufq = &pch->pat_qb;
+
+ seq_printf(s, "%s\n", splt);
+ for (i = 0; i < DIM_PAT_NUB; i++) {
+ pat_buf = (struct dim_pat_s *)pbufq->pbuf[i].qbc;
+ seq_printf(s, "%s:%d\n", "idx", i);
+ seq_printf(s, "\t%s:0x%lx\n", "mem_start", pat_buf->mem_start);
+ if (pat_buf->vaddr)
+ seq_printf(s, "\t%s:0x%px\n", "vaddr", pat_buf->vaddr);
+ else
+ seq_printf(s, "\t%s\n", "vaddr_none");
+ seq_printf(s, "\t%s:%d\n", "flg_vmap", pat_buf->flg_vmap);
+ seq_printf(s, "\t%s:0x%x\n", "crc", pat_buf->crc);
+ seq_printf(s, "%s\n", splt);
+ }
+}
+
+/********************************************/
+/* local buffer exit table */
+static const struct que_creat_s qbf_iat_cfg_q[] = {//TST_Q_IN_NUB
+ [QBF_IAT_Q_IDLE] = {
+ .name = "QBF_IAT_IDLE",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_IAT_Q_READY] = {
+ .name = "QBF_IAT_READY",
.type = Q_T_FIFO,
.lock = 0,
},
int i;
if (!pch) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
return;
}
PR_INF("%s:\n", __func__);
if (!pch) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
return;
}
pbufq = &pch->iat_qb;
int i;
if (!pch) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
return;
}
ret = qbuf_out_some(pbufq, QBF_IAT_Q_IN_USED, q_buf);
if (!ret) {
- //PR_ERR("%s:\n", __func__);
+ PR_ERR("%s:\n", __func__);
//dbg_hd_print(&iat_buf->header);
//dbg_q_listid_print(pbufq);
}
qbuf_in(pbufq, QBF_IAT_Q_READY, index);
}
len = qbufp_count(pbufq, QBF_IAT_Q_READY);
- PR_INF("%s:len[%d]", __func__, len);
+ PR_INF("%s:len[%d]\n", __func__, len);
return true;
}
}
#endif
+/********************************************/
+/* sct table */
+
+static const struct que_creat_s qbf_sct_cfg_q[] = {//TST_Q_IN_NUB
+ [QBF_SCT_Q_IDLE] = {
+ .name = "QBF_SCT_IDLE",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_SCT_Q_READY] = {
+ .name = "QBF_SCT_READY",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_SCT_Q_REQ] = {
+ .name = "QBF_SCT_REQ",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_SCT_Q_USED] = {
+ .name = "QBF_SCT_Q_USED",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_SCT_Q_RECYCLE] = {
+ .name = "QBF_SCT_Q_RECYCLE",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ },
+ [QBF_SCT_Q_KEEP] = {
+ .name = "QBF_SCT_Q_KEEP",
+ .type = Q_T_FIFO,
+ .lock = 0,
+ }
+};
+
+static const struct qbuf_creat_s qbf_sct_cfg_qbuf = {
+ .name = "qbuf_sct",
+ .nub_que = QBF_SCT_Q_NUB,
+ .nub_buf = DIM_SCT_NUB,
+ .code = CODE_SCT
+};
+
+void bufq_sct_int(struct di_ch_s *pch)
+{
+ struct dim_sct_s *sct_buf;
+ struct buf_que_s *pbufq;
+ int i;
+ unsigned int post_nub, sct_nub;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+
+ /* clear buf*/
+ sct_buf = &pch->sct_bf[0];
+ memset(sct_buf, 0, sizeof(*sct_buf) * DIM_SCT_NUB);
+
+ /* set buf's header */
+ for (i = 0; i < DIM_SCT_NUB; i++) {
+ sct_buf = &pch->sct_bf[i];
+
+ sct_buf->header.code = CODE_SCT;
+ sct_buf->header.index = i;
+ sct_buf->header.ch = pch->ch_id;
+ }
+
+ pbufq = &pch->sct_qb;
+ /*clear bq */
+ memset(pbufq, 0, sizeof(*pbufq));
+
+ /* point to resource */
+ for (i = 0; i < QBF_SCT_Q_NUB; i++)
+ pbufq->pque[i] = &pch->sct_q[i];
+
+ for (i = 0; i < DIM_SCT_NUB; i++)
+ pbufq->pbuf[i].qbc = &pch->sct_bf[i].header;
+
+ qbuf_int(pbufq, &qbf_sct_cfg_q[0], &qbf_sct_cfg_qbuf);
+
+ post_nub = cfgg(POST_NUB);
+ if ((post_nub) && (post_nub < POST_BUF_NUM))
+ sct_nub = post_nub;
+ else
+ sct_nub = DIM_SCT_NUB;
+
+ pbufq->nub_buf = sct_nub;
+
+ /* all to idle */
+ qbuf_in_all(pbufq, QBF_SCT_Q_IDLE);/*ary:this number must be total?*/
+}
+
+void bufq_sct_exit(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+
+ PR_INF("%s:\n", __func__);
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ pbufq = &pch->sct_qb;
+
+ qbuf_release_que(pbufq);
+}
+
+void bufq_sct_rest(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ int i;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+
+ pbufq = &pch->sct_qb;
+
+ for (i = 0; i < QBF_SCT_Q_NUB; i++)
+ qbufp_restq(pbufq, i);
+
+ /* all to idle */
+ qbuf_in_all(pbufq, QBF_SCT_Q_IDLE);
+}
+
+/* idle to req*/
+bool qsct_idle_to_req(struct di_ch_s *pch,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, QBF_SCT_Q_IDLE, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_REQ, index);
+
+ return true;
+}
+
+/* req to ready */
+bool qsct_req_to_ready(struct di_ch_s *pch,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, QBF_SCT_Q_REQ, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_READY, index);
+
+ return true;
+}
+
+/* ready to used */
+bool qsct_ready_to_used(struct di_ch_s *pch,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, QBF_SCT_Q_READY, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_USED, index);
+
+ return true;
+}
+
+bool qsct_recycle_to_idle(struct di_ch_s *pch,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, QBF_SCT_Q_RECYCLE, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_IDLE, index);
+
+ return true;
+}
+
+bool qsct_req_to_idle(struct di_ch_s *pch,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, QBF_SCT_Q_REQ, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_IDLE, index);
+
+ return true;
+}
+
+/* in_used to recycle*/
+bool qsct_used_some_to_recycle(struct di_ch_s *pch, struct dim_sct_s *sct_buf)
+{
+// unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->sct_qb;
+ q_buf.qbc = &sct_buf->header;
+
+ ret = qbuf_out_some(pbufq, QBF_SCT_Q_USED, q_buf);
+ if (!ret) {
+ PR_ERR("%s:\n", __func__);
+ //dbg_hd_print(&sct_buf->header);
+ //dbg_q_listid_print(pbufq);
+ }
+ ret = qbuf_in(pbufq, QBF_SCT_Q_RECYCLE, sct_buf->header.index);
+ if (!ret)
+ return false;
+
+ return true;
+}
+
+bool qsct_any_to_recycle(struct di_ch_s *pch,
+ enum QBF_SCT_Q_TYPE qtype,
+ struct dim_sct_s **sct)
+{
+ unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+ struct dim_sct_s *sct_buf;
+
+ pbufq = &pch->sct_qb;
+
+ ret = qbuf_out(pbufq, qtype, &index);
+ if (!ret)
+ return false;
+
+ q_buf = pbufq->pbuf[index];
+ sct_buf = (struct dim_sct_s *)q_buf.qbc;
+
+ *sct = sct_buf;
+ qbuf_in(pbufq, QBF_SCT_Q_RECYCLE, index);
+
+ return true;
+}
+
+/* in_used to keep */
+bool qsct_used_some_to_keep(struct di_ch_s *pch, struct dim_sct_s *sct_buf)
+{
+// unsigned int index;
+ bool ret;
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;
+
+ pbufq = &pch->sct_qb;
+ q_buf.qbc = &sct_buf->header;
+
+ ret = qbuf_out_some(pbufq, QBF_SCT_Q_USED, q_buf);
+ if (!ret) {
+ PR_ERR("%s:\n", __func__);
+ //dbg_hd_print(&sct_buf->header);
+ //dbg_q_listid_print(pbufq);
+ }
+ ret = qbuf_in(pbufq, QBF_SCT_Q_KEEP, sct_buf->header.index);
+ if (!ret)
+ return false;
+
+ return true;
+}
+
+struct dim_sct_s *qsct_req_peek(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;// = NULL;
+ struct dim_sct_s *sct;
+ bool ret;
+
+ pbufq = &pch->sct_qb;
+ //ret = qbuf_peek_s(pbufq, QBF_SCT_Q_REQ, q_buf);
+ ret = qbufp_peek(pbufq, QBF_SCT_Q_REQ, &q_buf);
+ if ((!ret) || (!q_buf.qbc))
+ return NULL;
+ sct = (struct dim_sct_s *)q_buf.qbc;
+
+ return sct;
+}
+
+struct dim_sct_s *qsct_peek(struct di_ch_s *pch, unsigned int q)
+{
+ struct buf_que_s *pbufq;
+ union q_buf_u q_buf;// = NULL;
+ struct dim_sct_s *sct;
+ bool ret;
+
+ pbufq = &pch->sct_qb;
+ //ret = qbuf_peek_s(pbufq, q, &q_buf);
+ ret = qbufp_peek(pbufq, q, &q_buf);
+ if ((!ret))
+ return NULL;
+ sct = (struct dim_sct_s *)q_buf.qbc;
+
+ return sct;
+}
+
+void dbg_sct_used(struct seq_file *s, struct di_ch_s *pch)
+{
+ unsigned int i;
+ struct qs_cls_s *p;
+ unsigned int psize;
+ char *splt = "---------------------------";
+// union q_buf_u q_buf;
+
+ struct buf_que_s *pbufq;
+ struct dim_sct_s *sct;
+
+ pbufq = &pch->sct_qb;
+ p = pbufq->pque[QBF_SCT_Q_USED];
+
+ p->ops.list(pbufq, p, &psize);
+ //seq_printf(s, "%s:\n", pqbuf->name);
+ if (psize == 0) {
+ seq_printf(s, "%s", "no list\n");
+ return;
+ }
+ seq_printf(s, "%s\n", __func__);
+ for (i = 0; i < psize; i++) {
+ sct = (struct dim_sct_s *)pbufq->pbuf[pbufq->list_id[i]].qbc;
+ seq_printf(s, "[%d]\n", i);
+ seq_printf(s, "\t:tail:%d:0x%x\n",
+ sct->flg_act.b.tab_resize, sct->tail_cnt);
+ if (sct->pat_buf) {
+ seq_printf(s, "\t\tpat:[%d],0x%lx, 0x%px\n",
+ sct->pat_buf->header.index,
+ sct->pat_buf->mem_start,
+ sct->pat_buf->vaddr);
+ }
+ seq_printf(s, "%s\n", splt);
+ }
+}
+
static ssize_t
show_config(struct device *dev,
struct device_attribute *attr, char *buf)
.ic_id = DI_IC_ID_T5,
};
+static const struct di_meson_data data_t7 = {
+ .name = "dim_t7",
+ .ic_id = DI_IC_ID_T7,
+};
+
+static const struct di_meson_data data_t5d = {
+ .name = "dim_t5d",
+ .ic_id = DI_IC_ID_T5D,
+};
+
/* #ifdef CONFIG_USE_OF */
static const struct of_device_id amlogic_deinterlace_dt_match[] = {
/*{ .compatible = "amlogic, deinterlace", },*/
.data = &data_sc2,
}, { .compatible = "amlogic, dim-t5",
.data = &data_t5,
+ }, { .compatible = "amlogic, dim-t7",
+ .data = &data_t7,
+ }, { .compatible = "amlogic, dim-t5d",
+ .data = &data_t5d,
+ }, { .compatible = "amlogic, dimv3-g12a",
+ .data = &data_g12a,
+ }, { .compatible = "amlogic, dimv3-g12b",
+ .data = &data_g12b,
+ }, { .compatible = "amlogic, dimv3-sm1",
+ .data = &data_sm1,
+ }, { .compatible = "amlogic, dimv3-tm2vb",
+ .data = &data_tm2_vb,
+ }, { .compatible = "amlogic, dimv3-t5",
+ .data = &data_t5,
+ }, { .compatible = "amlogic, dimv3-t5d",
+ .data = &data_t5d,
+ }, { .compatible = "amlogic, dimv3-sc2",
+ .data = &data_sc2,
}, {}
};
#endif
dim_set_di_flag();
dim_polic_prob();
dcntr_prob();
+ dip_prob_ch();
task_start();
mtask_start();
};
bool dim_mm_alloc_api(int cma_mode, size_t count, struct dim_mm_s *o,
- bool tvp_flg);
+ bool tvp_flg);
bool dim_mm_release_api(int cma_mode,
struct page *pages,
int count,
struct dim_pat_s *qpat_out_ready(struct di_ch_s *pch);
bool qpat_in_ready(struct di_ch_s *pch, struct dim_pat_s *pat_buf);
bool qpat_in_ready_msk(struct di_ch_s *pch, unsigned int msk);
+bool qpat_sct_2_ready(struct di_ch_s *pch, struct dim_pat_s *pat_buf);
+void pat_release_vaddr(struct dim_pat_s *pat);
+void pat_clear_mem(struct device *dev,
+ struct di_ch_s *pch,
+ struct dim_pat_s *pat_buf);
+void pat_frash(struct device *dev,
+ struct di_ch_s *pch,
+ struct dim_pat_s *pat_buf);
+
+void dbg_pat(struct seq_file *s, struct di_ch_s *pch);
void bufq_iat_int(struct di_ch_s *pch);
void bufq_iat_exit(struct di_ch_s *pch);
bool qiat_in_ready(struct di_ch_s *pch, struct dim_iat_s *iat_buf);
bool qiat_all_back2_ready(struct di_ch_s *pch);
+void bufq_sct_int(struct di_ch_s *pch);
+void bufq_sct_exit(struct di_ch_s *pch);
+void bufq_sct_rest(struct di_ch_s *pch);
+bool qsct_idle_to_req(struct di_ch_s *pch,
+ struct dim_sct_s **sct);
+bool qsct_req_to_idle(struct di_ch_s *pch,
+ struct dim_sct_s **sct);
+
+bool qsct_req_to_ready(struct di_ch_s *pch,
+ struct dim_sct_s **sct);
+bool qsct_ready_to_used(struct di_ch_s *pch,
+ struct dim_sct_s **sct);
+bool qsct_used_some_to_recycle(struct di_ch_s *pch, struct dim_sct_s *sct_buf);
+bool qsct_used_some_to_keep(struct di_ch_s *pch, struct dim_sct_s *sct_buf);
+//bool qsct_used_to_recycle(struct di_ch_s *pch,
+// struct dim_sct_s **sct);
+bool qsct_any_to_recycle(struct di_ch_s *pch,
+ enum QBF_SCT_Q_TYPE qtype,
+ struct dim_sct_s **sct);
+
+struct dim_sct_s *qsct_req_peek(struct di_ch_s *pch);
+struct dim_sct_s *qsct_peek(struct di_ch_s *pch, unsigned int q);
+bool qsct_recycle_to_idle(struct di_ch_s *pch,
+ struct dim_sct_s **sct);
+
+void dbg_sct_used(struct seq_file *s, struct di_ch_s *pch);
+
void bufq_mem_int(struct di_ch_s *pch);
void bufq_mem_exit(struct di_ch_s *pch);
bool mem_cfg_pre(struct di_ch_s *pch);
bool mem_cfg(struct di_ch_s *pch);
-void mem_release(struct di_ch_s *pch);
+void mem_release(struct di_ch_s *pch,
+ struct dim_mm_blk_s **blks, unsigned int blk_nub);
bool mem_2_blk(struct di_ch_s *pch);
void mem_release_all_inused(struct di_ch_s *pch);
void mem_release_one_inused(struct di_ch_s *pch, struct dim_mm_blk_s *blk_buf);
-void mem_release_keep_back(struct di_ch_s *pch);
+unsigned int mem_release_keep_back(struct di_ch_s *pch);
+void dim_post_keep_back_recycle(struct di_ch_s *pch);
+
bool mem_cfg_realloc(struct di_ch_s *pch); /*temp for re-alloc mem*/
unsigned int mem_release_free(struct di_ch_s *pch);
+unsigned int mem_release_sct_wait(struct di_ch_s *pch);
+
void mem_cfg_realloc_wait(struct di_ch_s *pch);
void bufq_mem_clear(struct di_ch_s *pch);
void pre_sec_alloc(struct di_ch_s *pch, unsigned int flg);
void pst_sec_alloc(struct di_ch_s *pch, unsigned int flg);
+
+int codec_mm_keeper_unmask_keeper(int keep_id, int delayms);
+bool dim_blk_tvp_is_sct(struct dim_mm_blk_s *blk_buf);
+bool dim_blk_tvp_is_out(struct dim_mm_blk_s *blk_buf);
+void di_buf_no2wait(struct di_ch_s *pch);
+bool mem_cfg_pst(struct di_ch_s *pch);
+void mem_resize_buf(struct di_ch_s *pch, struct di_buf_s *di_buf);
+
/*-------------------------*/
#endif /*__DI_SYS_H__*/
#include "di_sys.h"
#include "di_task.h"
#include "di_vframe.h"
+#include "di_dbg.h"
static void task_wakeup(struct di_task *tsk);
unsigned int di_dbg_task_flg; /*debug only*/
+module_param_named(di_dbg_task_flg, di_dbg_task_flg, uint, 0664);
bool task_send_cmd(unsigned int cmd)
{
task_wakeup(tsk);
}
+static void task_self_trig(void)
+{
+ int ch;
+ struct di_ch_s *pch;
+ bool ret = false;
+ struct di_hpre_s *pre = get_hw_pre();
+
+ if (pre->self_trig_mask) {
+ //dim_tr_ops.self_trig(DI_BIT28 | pre->self_trig_mask);
+ return;
+ }
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+ if (pch->self_trig_mask) {
+ //dim_tr_ops.self_trig(DI_BIT30 | pch->self_trig_mask);
+ continue;
+ }
+ if (pch->self_trig_need) {
+ ret = true;
+ break;
+ }
+ //dim_tr_ops.self_trig(DI_BIT29 | pch->self_trig_need);
+ }
+ if (ret) {
+ dbg_tsk("trig[0x%x]\n", pch->self_trig_need);
+ task_send_ready();
+ }
+}
bool task_get_cmd(unsigned int *cmd)
{
struct di_task *tsk = get_task();
union DI_L_CMD_BITS cmdbyte;
// struct di_mng_s *pbm = get_bufmng();
struct di_task *tsk = get_task();
- ulong flags = 0;
+//ary 2020-12-09 ulong flags = 0;
struct di_ch_s *pch;
+ struct di_mng_s *pbm;// = get_bufmng();
// if (pbm->cma_flg_run)
// return;
if (top_sts == EDI_TOP_STATE_READY) {
pch = get_chdata(ch);
mem_cfg_realloc(pch);
- mem_cfg_realloc_wait(pch);
+ mem_cfg_pst(pch);//2020-12-17
+ //mem_cfg_realloc_wait(pch);
+ pbm = get_bufmng();
+ if (!atomic_read(&pbm->trig_unreg[ch])) {
+ sct_mng_working(pch);
+ sct_mng_working_recycle(pch);
+ sct_alloc_in_poling(pch->ch_id);
+ }
}
if ((top_sts != EDI_TOP_STATE_IDLE) &&
(top_sts != EDI_TOP_STATE_READY) &&
(top_sts != EDI_TOP_STATE_BYPASS))
return;
- spin_lock_irqsave(&plist_lock, flags);
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
dim_post_re_alloc(ch);
//dim_post_release(ch);
- spin_unlock_irqrestore(&plist_lock, flags);
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
if (kfifo_is_empty(&tsk->fifo_cmd2[ch]))
return;
else
PR_ERR("%s\n", __func__);
}
-#ifdef MARK_HIS
- spin_lock_irqsave(&plist_lock, flags);
- dim_post_re_alloc(ch);
- dim_post_release(ch);
- spin_unlock_irqrestore(&plist_lock, flags);
-#endif
}
static int task_is_exiting(struct di_task *tsk)
dip_hw_process();
di_dbg_task_flg = 0;
+ dip_sum_post_ch();
+ task_self_trig();
}
tsk->thread = NULL;
}
}
+void mtask_wake_m(void)
+{
+ struct di_mtask *tsk = get_mtask();
+
+ mtask_wakeup(tsk);
+}
+
+static void mtask_polling_sct(struct di_ch_s *pch)
+{
+ //sct_alloc_in_poling(ch);
+ if (pch->itf.op_ready_out)
+ pch->itf.op_ready_out(pch);
+}
+
static int di_mem_thread(void *data)
{
struct di_mtask *tsk = data;
bool semheld = false;
int i;
+ struct di_ch_s *pch;
tsk->delay = HZ;
tsk->status = 0;
/**/
for (i = 0; i < DI_CHANNEL_NUB; i++) {
+ pch = get_chdata(i);
mtask_polling_cmd(i);
//blk_polling(i);
+ mtask_polling_sct(pch);
}
}
bool mtsk_release_block(unsigned int ch, unsigned int cmd);
bool mtask_send_cmd(unsigned int ch, struct mtsk_cmd_s *cmd);
bool mtsk_release(unsigned int ch, unsigned int cmd);
+void mtask_wake_m(void);
#endif /*__DI_TASK_H__*/
#include "di_pre.h"
#include "di_prc.h"
#include "di_dbg.h"
+#include "di_que.h"
#include "di_vframe.h"
+#include "di_task.h"
+#include "di_sys.h"
struct dev_vfram_t *get_dev_vframe(unsigned int ch)
{
if (ch < DI_CHANNEL_NUB)
- return &get_datal()->ch_data[ch].vfm;
+ return &get_datal()->ch_data[ch].itf.dvfm;
pr_info("err:%s ch overflow %d\n", __func__, ch);
- return &get_datal()->ch_data[0].vfm;
+ return &get_datal()->ch_data[0].itf.dvfm;
}
const char * const di_rev_name[4] = {
"dimulti.3",
};
-void dev_vframe_reg(struct dev_vfram_t *pvfm)
+/**************************************
+ * nins_m_recycle
+ * op_back_input
+ * _RECYCL -> _IDLE
+ * back vfm to dec
+ * run in main
+ **************************************/
+static void nins_m_recycle(struct di_ch_s *pch)
{
- if (pvfm->reg) {
- PR_WARN("duplicate reg\n");
+ struct buf_que_s *pbufq;
+ int i;
+ unsigned int cnt, ch;
+ struct dim_nins_s *ins;
+ struct vframe_s *vfm;
+
+ if ((!pch) || (pch->itf.etype != EDIM_NIN_TYPE_VFM)) {
+ PR_ERR("%s:\n", __func__);
return;
}
+ ch = pch->ch_id;
+ pbufq = &pch->nin_qb;
+
+ cnt = qbufp_count(pbufq, QBF_NINS_Q_RECYCL);
+
+ if (!cnt)
+ return;
+
+ for (i = 0; i < cnt; i++) {
+ ins = nins_move(pch, QBF_NINS_Q_RECYCL, QBF_NINS_Q_IDLE);
+ vfm = (struct vframe_s *)ins->c.ori;
+ if (vfm) {
+ pw_vf_put(vfm, ch);
+ pw_vf_notify_provider(ch,
+ VFRAME_EVENT_RECEIVER_PUT, NULL);
+ }
+ memset(&ins->c, 0, sizeof(ins->c));
+ }
+}
+
+static void nins_m_unreg(struct di_ch_s *pch)
+{
+ //clear all input
+ bufq_nin_reg(pch);
+}
+
+/************************************************
+ * for clear q,
+ * from used to idle,
+ * not back to dec
+ * ??
+ ************************************************/
+
+void nins_used2idle_one(struct di_ch_s *pch, struct dim_nins_s *ins)
+{
+ if ((!pch) || (pch->itf.etype != EDIM_NIN_TYPE_VFM)) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+}
+
+/**************************************
+ * bufq_ins_in_vf
+ * get vf from pre driver
+ * _IDLE -> _CHECK
+ * set ins
+ * *pvf
+ * vf_copy
+ **************************************/
+
+static bool nins_m_in_vf(struct di_ch_s *pch)
+{
+ struct buf_que_s *pbufq;
+ unsigned int in_nub, free_nub;
+ int i;
+ unsigned int ch;
+ struct vframe_s *vf;
+ struct dim_nins_s *pins;
+ unsigned int index;
+ bool flg_q;
+ unsigned int err_cnt = 0;
+
+ if (!pch) {
+ PR_ERR("%s:\n", __func__);
+ return false;
+ }
+ ch = pch->ch_id;
+ pbufq = &pch->nin_qb;
+
+ in_nub = qbufp_count(pbufq, QBF_NINS_Q_CHECK);
+ free_nub = qbufp_count(pbufq, QBF_NINS_Q_IDLE);
+
+ if ((in_nub >= DIM_K_VFM_IN_LIMIT) ||
+ (free_nub < (DIM_K_VFM_IN_LIMIT - in_nub))) {
+ return false;
+ }
+
+ for (i = 0; i < (DIM_K_VFM_IN_LIMIT - in_nub); i++) {
+ vf = pw_vf_peek(ch);
+ if (!vf)
+ break;
+
+ vf = pw_vf_get(ch);
+ if (!vf)
+ break;
+
+ /* get ins */
+ flg_q = qbuf_out(pbufq, QBF_NINS_Q_IDLE, &index);
+ if (!flg_q) {
+ PR_ERR("%s:qout\n", __func__);
+ err_cnt++;
+ pw_vf_put(vf, ch);
+ break;
+ }
+ pins = (struct dim_nins_s *)pbufq->pbuf[index].qbc;
+ pins->c.ori = vf;
+ //pins->c.etype = EDIM_NIN_TYPE_VFM;
+ memcpy(&pins->c.vfm_cp, vf, sizeof(pins->c.vfm_cp));
+ flg_q = qbuf_in(pbufq, QBF_NINS_Q_CHECK, index);
+ if (!flg_q) {
+ PR_ERR("%s:qin\n", __func__);
+ err_cnt++;
+ pw_vf_put(vf, ch);
+ qbuf_in(pbufq, QBF_NINS_Q_IDLE, index);
+ break;
+ }
+ }
+
+ if (err_cnt)
+ return false;
+ return true;
+}
+
+static void vfm_m_fill_ready(struct di_ch_s *pch)
+{
+ pw_vf_notify_receiver(pch->ch_id,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+}
+
+/*for first frame no need to ready buf*/
+/* @ary_note: this only used for vfm */
+static bool dim_bypass_first_frame(struct di_ch_s *pch)
+{
+ struct vframe_s *vframe;
+ struct dim_nins_s *nins;
+ unsigned int ch;
+ //struct di_ch_s *pch;
+
+ ch = pch->ch_id;
+ nins = nins_peek(pch);
+ if (!nins)
+ return false;
+
+ nins = nins_get(pch);
+ vframe = nins->c.ori;
+ nins->c.ori = NULL;
+ nins_used_some_to_recycle(pch, nins);
+
+ ndrd_qin(pch, vframe);
+
+ pw_vf_notify_receiver(ch,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+
+ PR_INF("%s:ok\n", __func__);
+ return true;
+}
+
+static struct vframe_s *dim_nbypass_get(struct di_ch_s *pch)
+{
+ struct vframe_s *vframe;
+ struct dim_nins_s *nins;
+
+ nins = nins_peek(pch);
+ if (!nins)
+ return NULL;
+
+ nins = nins_get(pch);
+ vframe = nins->c.ori;
+ nins->c.ori = NULL;
+ nins_used_some_to_recycle(pch, nins);
+
+ pw_vf_notify_receiver(pch->ch_id,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+
+ //PR_INF("%s:ok\n", __func__);
+ return vframe;
+}
+
+static struct vframe_s *dim_nbypass_peek(struct di_ch_s *pch)
+{
+ struct vframe_s *vframe;
+
+ vframe = nins_peekvfm(pch);
+ return vframe;
+}
+
+/* @ary_note: api for release */
+void dim_post_keep_cmd_release2_local(struct vframe_s *vframe)
+{
+ //struct di_buf_s *di_buf;
+ struct dim_ndis_s *ndis;
+
+ if (!dil_get_diffver_flag())
+ return;
+ if (!vframe) {
+ PR_ERR("%s:no vfm\n", __func__);
+ return;
+ }
+
+//#ifdef TST_NEW_INS_INTERFACE
+ //@ary_note:temp:
+ if (dim_dbg_new_int(1)) {
+ PR_ERR("%s:extbuff\n", __func__);
+ return;
+ }
+//#endif
+ ndis = (struct dim_ndis_s *)vframe->private_data;
+ //di_buf = (struct di_buf_s *)vframe->private_data;
+
+ if (!ndis) {
+ /* for bypass mode, di no need back vf buffer */
+ //PR_WARN("%s:no di_buf\n", __func__);
+ /* bypass mode */
+ return;
+ }
+
+ sum_release_inc(ndis->header.ch);
+ dbg_keep("release keep ch[%d],index[%d]\n",
+ ndis->header.ch,
+ ndis->header.index);
+ //dbg_wq("k:c[%d]\n", di_buf->index);
+ task_send_cmd2(ndis->header.ch,
+ LCMD2(ECMD_RL_KEEP,
+ ndis->header.ch,
+ ndis->header.index));
+}
+
+static void dev_vframe_reg_first(struct dim_itf_s *itf)
+{
+ //struct dev_vfram_t *pvfm;
+ struct dev_vfm_s *pvfmc;
+
+ itf->etype = EDIM_NIN_TYPE_VFM;
+ //pvfm = &itf->dvfm;
+ pvfmc = &itf->u.dvfmc;
+
+ /* clear */
+ memset(pvfmc, 0, sizeof(*pvfmc));
+ pvfmc->vf_m_fill_polling = nins_m_in_vf;
+ pvfmc->vf_m_fill_ready = vfm_m_fill_ready;
+ pvfmc->vf_m_bypass_first_frame = dim_bypass_first_frame;
+ itf->opins_m_back_in = nins_m_recycle;
+ itf->op_fill_ready = ndis_fill_ready;
+ itf->op_m_unreg = nins_m_unreg;
+ itf->op_ready_out = NULL;
+}
+
+static void dev_vframe_reg(struct dim_itf_s *itf)
+{
+ struct dev_vfram_t *pvfm;
+
+ pvfm = &itf->dvfm;
vf_reg_provider(&pvfm->di_vf_prov);
vf_notify_receiver(pvfm->name, VFRAME_EVENT_PROVIDER_START, NULL);
- pvfm->reg = 1;
}
-void dev_vframe_unreg(struct dev_vfram_t *pvfm)
+#ifdef MARK_HIS
+static void dev_vframe_unreg(struct dim_itf_s *itf)
{
- if (pvfm->reg) {
+ struct dev_vfram_t *pvfm;
+
+ pvfm = &itf->dvfm;
+ if (itf->reg) {
pr_debug("%s:ch[%s]:begin\n", __func__, pvfm->name);
vf_unreg_provider(&pvfm->di_vf_prov);
pr_debug("%s:ch[%s]:end\n", __func__, pvfm->name);
- pvfm->reg = 0;
+ itf->reg = 0;
+ }
+}
+#endif
+
+static int di_ori_event_qurey_vdin2nr(unsigned int channel)
+{
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+
+ return ppre->vdin2nr;
+}
+
+static int di_ori_event_reset(unsigned int channel)
+{
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+ struct vframe_s **pvframe_in = get_vframe_in(channel);
+ int i;
+//ary 2020-12-09 ulong flags;
+
+ /*block*/
+ di_block_set(1);//di_blocking = 1;
+
+ /*dbg_ev("%s: VFRAME_EVENT_PROVIDER_RESET\n", __func__);*/
+ if (dim_is_bypass(NULL, channel) ||
+ di_bypass_state_get(channel) ||
+ ppre->bypass_flag) {
+ pw_vf_notify_receiver(channel,
+ VFRAME_EVENT_PROVIDER_RESET,
+ NULL);
+ }
+
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
+ for (i = 0; i < MAX_IN_BUF_NUM; i++) {
+ if (pvframe_in[i])
+ pr_dbg("DI:clear vframe_in[%d]\n", i);
+
+ pvframe_in[i] = NULL;
+ }
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
+ di_block_set(0);//di_blocking = 0;
+
+ return 0;
+}
+
+static int di_ori_event_light_unreg(unsigned int channel)
+{
+ struct vframe_s **pvframe_in = get_vframe_in(channel);
+ int i;
+//ary 2020-12-09 ulong flags;
+
+ di_block_set(1);//di_blocking = 1;
+
+ pr_dbg("%s: vf_notify_receiver ligth unreg\n", __func__);
+
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
+ for (i = 0; i < MAX_IN_BUF_NUM; i++) {
+ if (pvframe_in[i])
+ pr_dbg("DI:clear vframe_in[%d]\n", i);
+
+ pvframe_in[i] = NULL;
+ }
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
+ di_block_set(0);//di_blocking = 0;
+
+ return 0;
+}
+
+static int di_ori_event_light_unreg_revframe(unsigned int channel)
+{
+ struct vframe_s **pvframe_in = get_vframe_in(channel);
+ int i;
+//ary 2020-12-09 ulong flags;
+
+ unsigned char vf_put_flag = 0;
+
+ pr_info("%s:VFRAME_EVENT_PROVIDER_LIGHT_UNREG_RETURN_VFRAME\n",
+ __func__);
+/*
+ * do not display garbage when 2d->3d or 3d->2d
+ */
+//ary 2020-12-09 spin_lock_irqsave(&plist_lock, flags);
+ for (i = 0; i < MAX_IN_BUF_NUM; i++) {
+ if (pvframe_in[i]) {
+ pw_vf_put(pvframe_in[i], channel);
+ pr_dbg("DI:clear vframe_in[%d]\n", i);
+ vf_put_flag = 1;
+ }
+ pvframe_in[i] = NULL;
+ }
+ if (vf_put_flag)
+ pw_vf_notify_provider(channel,
+ VFRAME_EVENT_RECEIVER_PUT, NULL);
+
+//ary 2020-12-09 spin_unlock_irqrestore(&plist_lock, flags);
+
+ return 0;
+}
+
+static int di_irq_ori_event_ready(unsigned int channel)
+{
+ return 0;
+}
+
+static int di_ori_event_ready(unsigned int channel)
+{
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+
+ if (ppre->bypass_flag)
+ pw_vf_notify_receiver(channel,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY,
+ NULL);
+
+ if (dip_chst_get(channel) == EDI_TOP_STATE_REG_STEP1)
+ task_send_cmd(LCMD1(ECMD_READY, channel));
+ else
+ task_send_ready();
+
+ di_irq_ori_event_ready(channel);
+ return 0;
+}
+
+static int di_ori_event_qurey_state(unsigned int channel)
+{
+ /*int in_buf_num = 0;*/
+ struct vframe_states states;
+
+ if (dim_vcry_get_flg())
+ return RECEIVER_INACTIVE;
+
+ /*fix for ucode reset method be break by di.20151230*/
+ di_vf_l_states(&states, channel);
+ if (states.buf_avail_num > 0)
+ return RECEIVER_ACTIVE;
+
+ if (pw_vf_notify_receiver(channel,
+ VFRAME_EVENT_PROVIDER_QUREY_STATE,
+ NULL) == RECEIVER_ACTIVE)
+ return RECEIVER_ACTIVE;
+
+ return RECEIVER_INACTIVE;
+}
+
+static void di_ori_event_set_3D(int type, void *data, unsigned int channel)
+{
+#ifdef DET3D
+
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+
+ if (type == VFRAME_EVENT_PROVIDER_SET_3D_VFRAME_INTERLEAVE) {
+ int flag = (long)data;
+
+ ppre->vframe_interleave_flag = flag;
+ }
+
+#endif
+}
+
+/*************************/
+/************************************/
+/************************************/
+#ifdef MARK_HIS
+struct vframe_s *di_vf_l_get(unsigned int channel)
+{
+ vframe_t *vframe_ret = NULL;
+ struct di_buf_s *di_buf = NULL;
+ struct di_ch_s *pch;
+#ifdef DI_DEBUG_POST_BUF_FLOW
+ struct di_buf_s *nr_buf = NULL;
+#endif
+ struct vframe_s *vfm_dbg;
+ ulong irq_flag2 = 0;
+// struct di_post_stru_s *ppost = get_post_stru(channel);
+
+ dim_print("%s:ch[%d]\n", __func__, channel);
+
+ pch = get_chdata(channel);
+
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ di_block_get() ||
+ !get_reg_flag(channel) ||
+ dump_state_flag_get()) {
+ dim_tr_ops.post_get2(1);
+ return NULL;
+ }
+
+ /**************************/
+ if (list_count(channel, QUEUE_DISPLAY) > DI_POST_GET_LIMIT) {
+ dim_tr_ops.post_get2(2);
+ return NULL;
+ }
+ /**************************/
+
+ if (!di_que_is_empty(channel, QUE_POST_READY)) {
+ dim_log_buffer_state("ge_", channel);
+ di_lock_irqfiq_save(irq_flag2);
+
+ di_buf = di_que_out_to_di_buf(channel, QUE_POST_READY);
+ if (dim_check_di_buf(di_buf, 21, channel)) {
+ di_unlock_irqfiq_restore(irq_flag2);
+ return NULL;
+ }
+ if (di_buf->type != VFRAME_TYPE_POST)
+ PR_ERR("%s:t[%d][%d]\n", __func__, di_buf->type,
+ di_buf->index);
+
+ #ifdef MARK_HIS
+ if (!di_buf->blk_buf)
+ PR_ERR("%s:no blk:t[%d][%d]\n", __func__,
+ di_buf->type, di_buf->index);
+ #endif
+ /* add it into display_list */
+ queue_in(channel, di_buf, QUEUE_DISPLAY);
+
+ di_unlock_irqfiq_restore(irq_flag2);
+
+ if (di_buf) {
+ vframe_ret = di_buf->vframe;
+
+ di_buf->seq = pch->disp_frame_count;
+ atomic_set(&di_buf->di_cnt, 1);
+ #ifdef MARK_HIS
+ if (di_buf->in_buf)
+ dbg_nins_log_buf(di_buf->in_buf, 2);
+ #endif
+ }
+ pch->disp_frame_count++;
+
+ dim_log_buffer_state("get", channel);
+ }
+ if (vframe_ret) {
+ dim_print("%s: %s[%d]:vtype[0x%x],0x%px [%d] %u ms\n", __func__,
+ dim_get_vfm_type_name(di_buf->type),
+ di_buf->index,
+ vframe_ret->type,
+ vframe_ret,
+ vframe_ret->index_disp,
+ jiffies_to_msecs(jiffies_64 -
+ vframe_ret->ready_jiffies64));
+ dbg_buf_log_save(pch, di_buf, 12);
+ dbg_cvs_log_save(
+ pch,
+ di_buf,
+ 12,
+ 0,
+ vframe_ret->canvas0_config[0].phy_addr);
+ didbg_vframe_out_save(channel, vframe_ret);
+ dim_print("\t:cw=%d,ch=%d\n",
+ vframe_ret->width,
+ vframe_ret->height);
+ if (pch->disp_frame_count == 1 && di_get_kpi_frame_num() > 0) {
+ pr_dbg("[di_kpi] %s: 1st frame get success. %s[%d]:0x%p %u ms\n",
+ __func__,
+ dim_get_vfm_type_name(di_buf->type),
+ di_buf->index,
+ vframe_ret,
+ jiffies_to_msecs(jiffies_64 -
+ vframe_ret->ready_jiffies64));
+ }
+ dim_tr_ops.post_get(vframe_ret->index_disp);
+
+ /*dbg to use dec vf */
+ if (dbg_sct_used_decoder_buffer() && vframe_ret->vf_ext) {
+ vfm_dbg = (struct vframe_s *)vframe_ret->vf_ext;
+ vframe_ret->compBodyAddr = vfm_dbg->compBodyAddr;
+ vframe_ret->compHeadAddr = vfm_dbg->compHeadAddr;
+ vframe_ret->type &= (~0xffff);
+ vframe_ret->type |= (vfm_dbg->type & 0xffff);
+ dim_print("use dec vfm\n");
+ }
+ } else {
+ dim_tr_ops.post_get2(3);
+ }
+
+ return vframe_ret;
+}
+#else
+struct vframe_s *di_vf_l_get(unsigned int channel)
+{
+ vframe_t *vframe_ret = NULL;
+// struct di_buf_s *di_buf = NULL;
+ struct di_ch_s *pch;
+
+// struct vframe_s *vfm_dbg;
+// ulong irq_flag2 = 0;
+ struct dim_ndis_s *ndis1, *ndis2;
+
+ dim_print("%s:ch[%d]\n", __func__, channel);
+
+ pch = get_chdata(channel);
+
+ /* special case */
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ di_block_get() ||
+ !get_reg_flag(channel) ||
+ dump_state_flag_get()) {
+ dim_tr_ops.post_get2(1);
+ return NULL;
+ }
+
+ /**************************/
+ if (ndis_cnt(pch, QBF_NDIS_Q_DISPLAY) > DI_POST_GET_LIMIT) {
+ dim_tr_ops.post_get2(2);
+ return NULL;
+ }
+ /**************************/
+ vframe_ret = ndrd_qout(pch);
+ if ((!vframe_ret) || (!vframe_ret->private_data)) {
+ dbg_nq("%s:bypass?\n", __func__);
+ didbg_vframe_out_save(channel, vframe_ret, 3);
+ return vframe_ret;
+ }
+ ndis1 = (struct dim_ndis_s *)vframe_ret->private_data;
+ if (!ndis1) /*is bypass*/
+ return vframe_ret;
+ ndis2 = ndis_move(pch, QBF_NDIS_Q_USED, QBF_NDIS_Q_DISPLAY);
+ if (ndis1 != ndis2)
+ PR_ERR("%s:\n", __func__);
+ didbg_vframe_out_save(channel, vframe_ret, 4);
+ dim_tr_ops.post_get(vframe_ret->index_disp);
+ return vframe_ret;
+}
+
+#endif
+
+#ifdef MARK_HIS
+void di_vf_l_put(struct vframe_s *vf, unsigned char channel)
+{
+ struct di_buf_s *di_buf = NULL;
+ ulong irq_flag2 = 0;
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+// struct di_post_stru_s *ppost = get_post_stru(channel);
+
+ dim_print("%s:ch[%d]\n", __func__, channel);
+
+ if (ppre->bypass_flag) {
+ pw_vf_put(vf, channel);
+ pw_vf_notify_provider(channel,
+ VFRAME_EVENT_RECEIVER_PUT, NULL);
+
+ //if (!IS_ERR_OR_NULL(ppost->keep_buf))
+ // recycle_keep_buffer(channel);
+ return;
+ }
+/* struct di_buf_s *p = NULL; */
+/* int itmp = 0; */
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ IS_ERR_OR_NULL(vf)) {
+ PR_ERR("%s: 0x%p\n", __func__, vf);
+ return;
+ }
+ if (di_block_get())
+ return;
+ dim_log_buffer_state("pu_", channel);
+ di_buf = (struct di_buf_s *)vf->private_data;
+ if (IS_ERR_OR_NULL(di_buf)) {
+ pw_vf_put(vf, channel);
+ pw_vf_notify_provider(channel,
+ VFRAME_EVENT_RECEIVER_PUT, NULL);
+ PR_WARN("%s: get vframe %p without di buf\n",
+ __func__, vf);
+ return;
+ }
+
+ if (di_buf->type == VFRAME_TYPE_POST) {
+ #ifdef MARK_HIS
+ if (!di_buf->blk_buf) {
+ PR_ERR("%s:no blk_buf ind[%d]\n",
+ __func__, di_buf->index);
+ }
+ #endif
+ #ifdef MARK_HIS
+ if (di_buf->in_buf)
+ dbg_nins_log_buf(di_buf->in_buf, 3);
+ #endif
+ di_lock_irqfiq_save(irq_flag2);
+
+ if (is_in_queue(channel, di_buf, QUEUE_DISPLAY)) {
+ di_buf->queue_index = -1;
+ di_que_in(channel, QUE_POST_BACK, di_buf);
+ di_unlock_irqfiq_restore(irq_flag2);
+
+ } else {
+ task_send_cmd2(channel,
+ LCMD2(ECMD_RL_KEEP,
+ channel,
+ di_buf->index));
+ di_unlock_irqfiq_restore(irq_flag2);
+ PR_WARN("%s:ch[%d]not in display %d\n",
+ __func__, channel,
+ di_buf->index);
+ }
+ } else {
+ PR_ERR("%s:t[%d][%d]\n", __func__, di_buf->type, di_buf->index);
+
+ di_lock_irqfiq_save(irq_flag2);
+ queue_in(channel, di_buf, QUEUE_RECYCLE);
+ di_unlock_irqfiq_restore(irq_flag2);
+
+ dim_print("%s: %s[%d] =>recycle_list\n", __func__,
+ dim_get_vfm_type_name(di_buf->type), di_buf->index);
+ }
+
+ task_send_ready();
+}
+#else
+void di_vf_l_put(struct vframe_s *vf, unsigned char channel)
+{
+// struct di_buf_s *di_buf = NULL;
+// ulong irq_flag2 = 0;
+ //struct di_pre_stru_s *ppre = get_pre_stru(channel);
+// struct di_post_stru_s *ppost = get_post_stru(channel);
+ struct di_ch_s *pch;
+ struct dim_ndis_s *ndis1;
+
+ dim_print("%s:ch[%d]\n", __func__, channel);
+
+ pch = get_chdata(channel);
+
+ /* special case */
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ IS_ERR_OR_NULL(vf)) {
+ PR_ERR("%s: 0x%p\n", __func__, vf);
+ return;
+ }
+ if (di_block_get())
+ return;
+
+ ndis1 = (struct dim_ndis_s *)vf->private_data;
+ if (IS_ERR_OR_NULL(ndis1)) {
+ pw_vf_put(vf, channel);
+ pw_vf_notify_provider(channel,
+ VFRAME_EVENT_RECEIVER_PUT, NULL);
+ //PR_WARN("%s: get vframe %p without di buf\n",
+ // __func__, vf);
+ return;
+ }
+ task_send_cmd2(channel,
+ LCMD2(ECMD_RL_KEEP,
+ channel,
+ ndis1->header.index));
+ task_send_ready();
+}
+
+#endif
+
+#ifdef MARK_HIS
+struct vframe_s *di_vf_l_peek(unsigned int channel)
+{
+ struct vframe_s *vframe_ret = NULL;
+ struct di_buf_s *di_buf = NULL;
+ struct di_pre_stru_s *ppre = get_pre_stru(channel);
+
+ /*dim_print("%s:ch[%d]\n",__func__, channel);*/
+
+ di_sum_inc(channel, EDI_SUM_O_PEEK_CNT);
+ if (ppre->bypass_flag) {
+ dim_tr_ops.post_peek(0);
+ return pw_vf_peek(channel);
+ }
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ di_block_get() ||
+ !get_reg_flag(channel) ||
+ dump_state_flag_get()) {
+ dim_tr_ops.post_peek(1);
+ return NULL;
+ }
+
+ /**************************/
+ if (list_count(channel, QUEUE_DISPLAY) > DI_POST_GET_LIMIT) {
+ dim_tr_ops.post_peek(2);
+ return NULL;
+ }
+ /**************************/
+ dim_log_buffer_state("pek", channel);
+
+ if (!di_que_is_empty(channel, QUE_POST_READY)) {
+ di_buf = di_que_peek(channel, QUE_POST_READY);
+ if (di_buf)
+ vframe_ret = di_buf->vframe;
+ }
+#ifdef DI_BUFFER_DEBUG
+ if (vframe_ret)
+ dim_print("%s: %s[%d]:%x\n", __func__,
+ dim_get_vfm_type_name(di_buf->type),
+ di_buf->index, vframe_ret);
+#endif
+ if (vframe_ret) {
+ dim_tr_ops.post_peek(9);
} else {
- PR_WARN("duplicate ureg\n");
+ task_send_ready();
+ dim_tr_ops.post_peek(4);
}
+ return vframe_ret;
}
+#else
+struct vframe_s *di_vf_l_peek(unsigned int channel)
+{
+ struct vframe_s *vframe_ret = NULL;
+// struct di_buf_s *di_buf = NULL;
+ struct di_ch_s *pch;
+// struct dim_ndis_s *ndis1;
+
+ //struct di_pre_stru_s *ppre = get_pre_stru(channel);
+
+ /*dim_print("%s:ch[%d]\n",__func__, channel);*/
+ pch = get_chdata(channel);
+ di_sum_inc(channel, EDI_SUM_O_PEEK_CNT);
+
+ /* special case */
+ if (!get_init_flag(channel) ||
+ dim_vcry_get_flg() ||
+ di_block_get() ||
+ !get_reg_flag(channel) ||
+ dump_state_flag_get()) {
+ dim_tr_ops.post_peek(1);
+ return NULL;
+ }
+
+ /**************************/
+ if (ndis_cnt(pch, QBF_NDIS_Q_DISPLAY) > DI_POST_GET_LIMIT) {
+ dim_tr_ops.post_peek(2);
+ return NULL;
+ }
+ /**************************/
+ vframe_ret = ndrd_qpeekvfm(pch);
+
+ if (vframe_ret) {
+ dim_tr_ops.post_peek(9);
+ } else {
+ task_send_ready();
+ dim_tr_ops.post_peek(4);
+ }
+ return vframe_ret;
+}
+
+#endif
+int di_vf_l_states(struct vframe_states *states, unsigned int channel)
+{
+ struct div2_mm_s *mm = dim_mm_get(channel);
+ struct dim_sum_s *psumx = get_sumx(channel);
+
+ /*pr_info("%s: ch[%d]\n", __func__, channel);*/
+ if (!states)
+ return -1;
+ states->vf_pool_size = mm->sts.num_local;
+ states->buf_free_num = psumx->b_pre_free;
+
+ states->buf_avail_num = psumx->b_pst_ready;
+ states->buf_recycle_num = psumx->b_recyc;
+ if (dimp_get(edi_mp_di_dbg_mask) & 0x1) {
+ di_pr_info("di-pre-ready-num:%d\n", psumx->b_pre_ready);
+ di_pr_info("di-display-num:%d\n", psumx->b_display);
+ }
+ return 0;
+}
+
/*--------------------------*/
const char * const di_receiver_event_cmd[] = {
switch (type) {
case VFRAME_EVENT_PROVIDER_UNREG:
+ mutex_lock(&pch->itf.lock_reg);
+ if (!pch->itf.reg) {
+ mutex_unlock(&pch->itf.lock_reg);
+ PR_WARN("duplicate ureg\n");
+ break;
+ }
+ mutex_unlock(&pch->itf.lock_reg);
+ vf_unreg_provider(&pch->itf.dvfm.di_vf_prov);
+ mutex_lock(&pch->itf.lock_reg);
+ pch->itf.reg = 0;
+ //dev_vframe_unreg(&pch->itf);
dim_trig_unreg(ch);
- dev_vframe_unreg(&pch->vfm);
dim_api_unreg(DIME_REG_MODE_VFM, pch);
-
+ mutex_unlock(&pch->itf.lock_reg);
break;
case VFRAME_EVENT_PROVIDER_REG:
+
+ mutex_lock(&pch->itf.lock_reg);
+ if (pch->itf.reg) {
+ PR_WARN("duplicate reg\n");
+ mutex_unlock(&pch->itf.lock_reg);
+ break;
+ }
+ dev_vframe_reg_first(&pch->itf);
pch->sum_reg_cnt++;
dbg_ev("reg:%s[%d]\n", provider_name, pch->sum_reg_cnt);
dim_api_reg(DIME_REG_MODE_VFM, pch);
- dev_vframe_reg(&pch->vfm);
+ dev_vframe_reg(&pch->itf);
+ pch->itf.reg = 1;
+ mutex_unlock(&pch->itf.lock_reg);
+
break;
case VFRAME_EVENT_PROVIDER_START:
break;
}
#endif
+#ifdef MARK_HIS
void set_bypass_complete(struct dev_vfram_t *pvfm, bool on)
{
if (on)
else
pvfm->bypass_complete = false;
}
+#endif
+#ifdef MARK_HIS //move to di_prc for interface
void set_bypass2_complete(unsigned int ch, bool on)
{
struct dev_vfram_t *pvfm;
return is_bypss_complete(pvfm);
}
+#endif
static struct vframe_s *di_vf_peek(void *arg)
{
unsigned int ch = *(int *)arg;
+ struct di_ch_s *pch;
+ struct vframe_s *vfm;
/*dim_print("%s:ch[%d]\n",__func__,ch);*/
+ pch = get_chdata(ch);
+
+ if (!pch->itf.reg)
+ return NULL;
+
if (di_is_pause(ch))
return NULL;
- if (is_bypss2_complete(ch))
+ if (is_bypss2_complete(ch)) {
+ vfm = dim_nbypass_peek(pch);
+ if (vfm)
+ return vfm;
return pw_vf_peek(ch);
- else
- return di_vf_l_peek(ch);
+ }
+ return di_vf_l_peek(ch);
}
static struct vframe_s *di_vf_get(void *arg)
{
unsigned int ch = *(int *)arg;
+ struct di_ch_s *pch;
+ struct vframe_s *vfm;
+
/*struct vframe_s *vfm;*/
+ pch = get_chdata(ch);
+
+ if (!pch->itf.reg)
+ return NULL;
dim_tr_ops.post_get2(5);
if (di_is_pause(ch))
/*pvfm = get_dev_vframe(ch);*/
- if (is_bypss2_complete(ch))
- #ifdef MARK_HIS
- vfm = pw_vf_peek(ch);
- if (dim_bypass_detect(ch, vfm))
- return NULL;
-
- #endif
+ if (is_bypss2_complete(ch)) {
+ vfm = dim_nbypass_get(pch);
+ if (vfm)
+ return vfm;
return pw_vf_get(ch);
-
+ }
sum_pst_g_inc(ch);
return di_vf_l_get(ch);
static void di_vf_put(struct vframe_s *vf, void *arg)
{
unsigned int ch = *(int *)arg;
+ struct di_ch_s *pch;
+
+ pch = get_chdata(ch);
+
+ if (!pch->itf.reg) {
+ PR_ERR("%s:ch[%d],unreg?\n", __func__, ch);
+ return;
+ }
if (is_bypss2_complete(ch)) {
pw_vf_put(vf, ch);
{
struct dev_vfram_t *pvfm;
int ch;
+ struct di_ch_s *pch;
+
+#ifdef TST_NEW_INS_INTERFACE
+ vfmtst_exit();
+ PR_INF("new ins interface test end\n");
+ return;
+#endif
for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pvfm = get_dev_vframe(ch);
+ //pvfm = get_dev_vframe(ch);
+ pch = get_chdata(ch);
+ pvfm = &pch->itf.dvfm;
vf_unreg_provider(&pvfm->di_vf_prov);
vf_unreg_receiver(&pvfm->di_vf_recv);
}
{
struct dev_vfram_t *pvfm;
int ch;
-// struct di_ch_s *pch;
+ struct di_ch_s *pch;
+
+#ifdef TST_NEW_INS_INTERFACE
+ struct dim_itf_s *pintf;
+
+ vfmtst_init();
+ for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
+ pch = get_chdata(ch);
+ pintf = &pch->itf;
+ pintf->ch = ch;
+ }
+ PR_INF("new ins interface test enable\n");
+ return;
+#endif
for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pvfm = get_dev_vframe(ch);
+ pch = get_chdata(ch);
+ pch->itf.ch = ch; //2020-12-21
+ pvfm = &pch->itf.dvfm;
pvfm->name = di_rev_name[ch];
pvfm->indx = ch;
/*set_bypass_complete(pvfm, true);*/ /*test only*/
void dev_vframe_init(void);
void dev_vframe_exit(void);
-void dev_vframe_reg(struct dev_vfram_t *pvfm);
-void dev_vframe_unreg(struct dev_vfram_t *pvfm);
+//void dev_vframe_reg(struct dev_vfram_t *pvfm);
+//void dev_vframe_unreg(struct dev_vfram_t *pvfm);
#ifdef MARK_SC2
bool vf_type_is_prog(unsigned int type);
void pw_vf_light_unreg_provider(unsigned int ch);
void set_bypass2_complete(unsigned int ch, bool on);
-bool is_bypss_complete(struct dev_vfram_t *pvfm);
+//no used bool is_bypss_complete(struct dev_vfram_t *pvfm);
bool is_bypss2_complete(unsigned int ch);
#endif /*__DI_VFRAME_H__*/
DEFINE_DI_EVENT(dim_pst_doing);
DEFINE_DI_EVENT(dim_pst_peekx);
DEFINE_DI_EVENT(dim_pst_get2x);
+DEFINE_DI_EVENT(dim_self_trig);
+DEFINE_DI_EVENT(dim_sct_alloc);
+DEFINE_DI_EVENT(dim_sct_tail);
#endif /* _DIM_TRACE_H */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* drivers/amlogic/media/di_multi/dolby_sys.c
*
*
*/
-#if 1
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
}
}
-static int di_dolby_core_set(
- struct di_dolby_hw_s *hw,
- bool lut_endian,
- u32 op_flag,
- u32 update_flag,
- bool reset)
+static int di_dolby_core_set(struct di_dolby_hw_s *hw,
+ bool lut_endian,
+ u32 op_flag,
+ u32 update_flag,
+ bool reset)
{
u32 count;
u32 bypass_flag = 0;
set_lut = true;
DIM_DI_WR(DOLBY_CORE1C_CLKGATE_CTRL, 0);
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL1,
- ((hw->hsize + hw->htotal) << 16) | (hw->vsize + hw->vtotal));
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL3,
- (hw->hwidth << 16) | hw->vwidth);
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL4,
- (hw->hpotch << 16) | hw->vpotch);
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL2,
- (hw->hsize << 16) | hw->vsize);
-
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL5,
- ((hw->el_uv_mode & 3) << 2) | ((hw->bl_uv_mode & 3) << 0));
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL1,
+ ((hw->hsize + hw->htotal) << 16) | (hw->vsize + hw->vtotal));
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL3,
+ (hw->hwidth << 16) | hw->vwidth);
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL4,
+ (hw->hpotch << 16) | hw->vpotch);
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL2,
+ (hw->hsize << 16) | hw->vsize);
+
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL5,
+ ((hw->el_uv_mode & 3) << 2) | ((hw->bl_uv_mode & 3) << 0));
DIM_DI_WR(DOLBY_CORE1C_DMA_CTRL, 0x0);
DIM_DI_WR(DOLBY_CORE1C_REG_START + 4, 4);
count = dm_count;
for (i = 0; i < count; i++)
if (reset ||
- (dm_regs[i] !=
- last_dm[i])) {
- DIM_DI_WR(
- DOLBY_CORE1C_REG_START + 6 + i,
- dm_regs[i]);
+ dm_regs[i] != last_dm[i]) {
+ DIM_DI_WR(DOLBY_CORE1C_REG_START + 6 + i,
+ dm_regs[i]);
}
if (comp_count == 0)
count = comp_count;
for (i = 0; i < count; i++)
if (reset ||
- (comp_regs[i] !=
- last_comp[i])) {
- DIM_DI_WR(
- DOLBY_CORE1C_REG_START + 6 + 44 + i,
- comp_regs[i]);
+ comp_regs[i] != last_comp[i]) {
+ DIM_DI_WR(DOLBY_CORE1C_REG_START + 6 + 44 + i,
+ comp_regs[i]);
}
/* metadata program done */
DIM_DI_WR(DOLBY_CORE1C_REG_START + 3, 1);
2, 2, 2);
}
DIM_DI_WR(DOLBY_CORE1C_DMA_CTRL, 0x1401);
- if (lut_endian)
+ if (lut_endian) {
for (i = 0; i < count; i += 4) {
DIM_DI_WR(DOLBY_CORE1C_DMA_PORT,
lut_regs[i + 3]);
DIM_DI_WR(DOLBY_CORE1C_DMA_PORT,
lut_regs[i]);
}
- else {
+ } else {
for (i = 0; i < count; i++)
DIM_DI_WR(DOLBY_CORE1C_DMA_PORT,
lut_regs[i]);
DIM_DI_WR(DI_HDR_IN_HSIZE, hw->hsize);
DIM_DI_WR(DI_HDR_IN_VSIZE, hw->vsize);
- DIM_DI_WR(
- DOLBY_CORE1C_SWAP_CTRL0,
- ((hw->roundup_output ? 1 : 0) << 12) |
- ((hw->bl_lay_line_delay & 0xf) << 8) |
- ((hw->el_lay_line_delay & 0xf) << 4) |
- ((hw->el_41_mode ? 1 : 0) << 2) |
- ((hw->el_enable ? 1 : 0) << 1) |
- ((hw->bl_enable ? 1 : 0) << 0));
+ DIM_DI_WR(DOLBY_CORE1C_SWAP_CTRL0,
+ ((hw->roundup_output ? 1 : 0) << 12) |
+ ((hw->bl_lay_line_delay & 0xf) << 8) |
+ ((hw->el_lay_line_delay & 0xf) << 4) |
+ ((hw->el_41_mode ? 1 : 0) << 2) |
+ ((hw->el_enable ? 1 : 0) << 1) |
+ ((hw->bl_enable ? 1 : 0) << 0));
return 0;
}
return 0;
}
-int di_dolby_update_setting(
- struct didm_register_ipcore_1_s *dm_reg,
- struct dicomposer_register_ipcore_s *comp_reg,
- struct didm_lut_ipcore_s *dm_lut,
- u32 dm_count,
- u32 comp_count,
- u32 lut_count,
- u32 update_flag,
- u32 hsize,
- u32 vsize)
+int di_dolby_update_setting(struct didm_register_ipcore_1_s *dm_reg,
+ struct dicomposer_register_ipcore_s *comp_reg,
+ struct didm_lut_ipcore_s *dm_lut,
+ u32 dm_count,
+ u32 comp_count,
+ u32 lut_count,
+ u32 update_flag,
+ u32 hsize,
+ u32 vsize)
{
struct didm_register_ipcore_1_s *new_dm_reg;
struct dicomposer_register_ipcore_s *new_comp_reg;
{
di_dolby = vmalloc(sizeof(*di_dolby));
if (!di_dolby) {
- pr_info("di_dolby_sw_init fail\n");
+ //pr_info("di_dolby_sw_init fail\n");
return;
}
memset(di_dolby, 0, sizeof(struct di_dolby_dev_s));
di_dolby->cur_tbl_id = 1;
di_dolby->next_tbl_id = 0xff;
}
-
-#endif
*/
#ifndef __DOLBY_SYS_H__
-#define __DOLBY_SYS_H_
-#if 1
+#define __DOLBY_SYS_H__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
u32 el_nlq_offset_v;
u32 el_coefficient_v[3];
};
-#endif
#define DOLBY_CORE1C_REG_START 0x1800
#define DOLBY_CORE1C_CLKGATE_CTRL 0x18f2
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* drivers/amlogic/media/di_multi/reg_decontour.h
*
/* Bit 28, reg_NM_reset Reset to the status of the Loop filter.
* Bit 27:24, reg_NM_calc_length Length mode of the Noise
* measurement sample number for statistics.
- * 0: 256 samples; 1: 512 samples; 2: 1024 samples;
- * ¡X: 2^(8+x) samples
+ * 0: 256 samples; 1: 512 samples; 2: 1024 samples;
* Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
* Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
* Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion
}
//static
- void dbg_regs_tab(struct seq_file *s, const struct regs_t *pregtab,
- const unsigned int *padd)
+void dbg_regs_tab(struct seq_file *s, const struct regs_t *pregtab,
+ const unsigned int *padd)
{
struct regs_t creg;
int i;
i++;
creg = pregtab[i];
- if (i > TABLE_LEN_MAX) {
+ if (i > DIMTABLE_LEN_MAX) {
pr_info("too long, stop\n");
break;
}
}
EXPORT_SYMBOL(dbg_afbce_bits_show);
+void dbg_mif_wr_bits_show(struct seq_file *s, enum EDI_MIFSM mifsel)
+{
+ seq_printf(s, "dump bits:wr[%d]\n", mifsel);
+ dbg_regs_tab(s, opl1()->reg_mif_wr_bits_tab,
+ opl1()->reg_mif_wr_tab[mifsel]);
+}
+EXPORT_SYMBOL(dbg_mif_wr_bits_show);
+
case EAFBC_CFG_FORCE_NR:
if (afbc_cfg & BITS_EAFBC_CFG_FORCE_NR)
ret = true;
+ break;
case EAFBC_CFG_FORCE_IF1:
if (afbc_cfg & BITS_EAFBC_CFG_FORCE_IF1)
ret = true;
case EAFBC_MEMI_NEED:
ret = pafd_ctr->fb.mem_alloci;
break;
+ case EAFBC_EN_6CH:
+ if (pafd_ctr->fb.mode >= AFBC_WK_6D)
+ ret = true;
+ break;
+ case EAFBC_EN_ENC:
+ if (pafd_ctr->fb.mode >= AFBC_WK_P)
+ ret = true;
+ break;
}
return ret;
}
};
+#ifdef HIS_CODE
static void afbc_sgn_mode_set(unsigned int sgn_mode)
{
struct afbcd_ctr_s *pafd_ctr;
pafd_ctr->en_sgn.d8 = 0;
}
}
+#else
+static void afbc_sgn_mode_set(unsigned char *sgn_mode, enum EAFBC_SNG_SET cmd)
+{
+ union afbc_blk_s *en_cfg;
+
+ en_cfg = (union afbc_blk_s *)sgn_mode;
+ switch (cmd) {
+ case EAFBC_SNG_CLR_NR:
+ en_cfg->b.enc_nr = 0;
+ break;
+ case EAFBC_SNG_CLR_WR:
+ en_cfg->b.enc_wr = 0;
+ break;
+ case EAFBC_SNG_SET_NR:
+ en_cfg->b.enc_nr = 1;
+ break;
+ case EAFBC_SNG_SET_WR:
+ en_cfg->b.enc_wr = 1;
+ break;
+ };
+}
+#endif
static unsigned char afbc_cnt_sgn_mode(unsigned int sgn)
{
// struct afbcd_ctr_s *pafd_ctr;
/*******************************
* cfg for debug:
******************************/
+ if (!afbc_cfg)
+ return;
if (is_cfg(EAFBC_CFG_DISABLE)) {
pafd_ctr->fb.mode = 0;
} else if (afbc_cfg & (BITS_EAFBC_CFG_INP_AFBC |
//afbc_cfg = BITS_EAFBC_CFG_4K;
afbc_cfg = 0;
memcpy(&pafd_ctr->fb, &cafbc_v5_sc2, sizeof(pafd_ctr->fb));
- pafd_ctr->fb.mode = AFBC_WK_6D_NV21;
+ pafd_ctr->fb.mode = AFBC_WK_P;//AFBC_WK_6D_NV21;
//AFBC_WK_6D_ALL;//AFBC_WK_IN;//
+ } else if (IS_IC_EF(cid, T5D)) { //unsupport afbc
+ pafd_ctr->fb.ver = AFBCD_NONE;
+ pafd_ctr->fb.sp.b.inp = 0;
+ pafd_ctr->fb.sp.b.mem = 0;
+ pafd_ctr->fb.pre_dec = EAFBC_DEC0;
+ pafd_ctr->fb.mode = AFBC_WK_NONE;
} else if (IS_IC_EF(cid, T5)) { //afbc config same with tm2b
afbc_cfg = 0;
memcpy(&pafd_ctr->fb, &cafbc_v4_tm2, sizeof(pafd_ctr->fb));
pafd_ctr->fb.mem_alloci = 0;
}
- afbc_cfg = BITS_EAFBC_CFG_DISABLE;
- di_pr_info("%s:ver[%d],%s\n", __func__, pafd_ctr->fb.ver,
- afbc_get_version());
+ //afbc_cfg = BITS_EAFBC_CFG_DISABLE;
+ di_pr_info("%s:ver[%d],%s,mode[%d]\n", __func__, pafd_ctr->fb.ver,
+ afbc_get_version(), pafd_ctr->fb.mode);
}
/*
reg_wr(reg[EAFBC_VD_CFMT_H], /*out_height*/cvfm_h);
reg_wr(reg[EAFBC_SIZE_IN], (vf->height) | w_aligned << 16);
- di_print("%s:size:%d\n", __func__, vf->height);
+ di_print("\t:size:%d\n", vf->height);
if (pafd_ctr->fb.ver <= AFBCD_V4)
reg_wr(reg[EAFBC_SIZE_OUT], out_height | w_aligned << 16);
pafd_ctr->b.chg_chan2 == 3) {
if (pafd_ctr->fb.ver == AFBCD_V4) {
if (pafd_ctr->en_set.b.inp)
- afbc_tm2_sw_inp(true);
- if (mem_vf2 && pafd_ctr->en_set.b.mem)
- afbc_tm2_sw_mem(true);
+ afbc_tm2_sw_inp(true);
+ else
+ afbc_tm2_sw_inp(false);
+ if (mem_vf2 && pafd_ctr->en_set.b.mem)
+ afbc_tm2_sw_mem(true);
else
afbc_tm2_sw_mem(false);
- if (pafd_ctr->en_set.b.enc_nr)
- afbce_tm2_sw(true);
+ if (pafd_ctr->en_set.b.enc_nr)
+ afbce_tm2_sw(true);
else
afbce_tm2_sw(false);
}
struct afbcd_ctr_s *pafd_ctr = di_get_afd_ctr();
if (!pafd_ctr->fb.mode)
-
- PR_INF("%s:%d\n", __func__, en);
+ PR_INF("%s:%d\n", __func__, en);
#endif
}
vf->compWidth = vf->width;
vf->bitdepth |= (BITDEPTH_U10 | BITDEPTH_V10);
+ if (di_buf->afbce_out_yuv420_10) {
+ vf->type &= ~VFMT_COLOR_MSK;
+ vf->type |= VIDTYPE_VIU_FIELD;
+ vf->bitdepth &= ~(FULL_PACK_422_MODE);
+ }
//dim_print("%s:%px:0x%x\n", __func__, vf, vf->type);
#ifdef DBG_AFBC
#endif
}
-#if 1
struct enc_cfg_s {
int enable;
int loosy_mode;
/*from sc2*/
u32 reg_init_ctrl;//pip init frame flag
u32 reg_pip_mode;//pip open bit
- u32 reg_ram_comb;//ram split bit open in di mult write case case
+ u32 reg_ram_comb;//ram split bit open in di mult write case
u32 hsize_bgnd;//hsize of background
u32 vsize_bgnd;//hsize of background
u32 rev_mode;//0:normal mode
int cur_mmu_used = 0;/*mmu info linear addr*/
int reg_fmt444_comb;
- int uncmp_size ;/*caculate*/
- int uncmp_bits ;/*caculate*/
- int sblk_num ;/*caculate*/
+ int uncmp_size ;/*calculate*/
+ int uncmp_bits ;/*calculate*/
+ int sblk_num ;/*calculate*/
struct afbcd_ctr_s *pafd_ctr = di_get_afd_ctr();
bool flg_v5 = false;
unsigned int hsize_buf;
((hblksize_out & 0x1fff) << 16) |
((vblksize_out & 0x1fff) << 0)
);
-
+ if (DIM_IS_IC_EF(T7))
+ op->wr(reg[EAFBCE_HEAD_BADDR], cfg->head_baddr >> 4);
+ else
/*head addr of compressed data*/
- op->wr(reg[EAFBCE_HEAD_BADDR], cfg->head_baddr);
+ op->wr(reg[EAFBCE_HEAD_BADDR], cfg->head_baddr);
/*uncmp_size*/
op->bwr(reg[EAFBCE_MIF_SIZE], (uncmp_size & 0x1fff), 16, 5);
- /* scope of hsize_in ,should be a integer multipe of 32*/
- /* scope of vsize_in ,should be a integer multipe of 4*/
+ /* scope of hsize_in ,should be a integer multiple of 32*/
+ /* scope of vsize_in ,should be a integer multiple of 4*/
op->wr(reg[EAFBCE_PIXEL_IN_HOR_SCOPE],
((cfg->enc_win_end_h & 0x1fff) << 16) |
((cfg->enc_win_bgn_h & 0x1fff) << 0));
- /* scope of hsize_in ,should be a integer multipe of 32*/
- /* scope of vsize_in ,should be a integer multipe of 4*/
+ /* scope of hsize_in ,should be a integer multiple of 32*/
+ /* scope of vsize_in ,should be a integer multiple of 4*/
op->wr(reg[EAFBCE_PIXEL_IN_VER_SCOPE],
((cfg->enc_win_end_v & 0x1fff) << 16) |
((cfg->enc_win_bgn_v & 0x1fff) << 0)
/*4k addr have used in every frame;*/
/*cur_mmu_used += Rd(DI_AFBCE_MMU_NUM);*/
- op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], cfg->mmu_info_baddr);
+ if (DIM_IS_IC_EF(T7))
+ op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], cfg->mmu_info_baddr >> 4);
+ else
+ op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], cfg->mmu_info_baddr);
/**/
if (flg_v5)
/* ary : not setting DI_AFBCE_CTRL ?*/
} else {
+ if (DIM_IS_IC(TM2B))//dis afbce mode from vlsi xianjun.fan
+ op->bwr(reg[EAFBCE_MODE_EN], 0x01, 18, 1);
op->bwr(reg[EAFBCE_ENABLE], cfg->enable, 8, 1);//enable afbce
op->bwr(DI_AFBCE_CTRL, cfg->enable, 0, 1);//di pre to afbce
//op->bwr(DI_AFBCE_CTRL, cfg->enable, 4, 1);//di pre to afbce
}
}
+unsigned int afbce_read_used(enum EAFBC_ENC enc)
+{
+ const unsigned int *reg;
+ const struct reg_acc *op = &di_normal_regset;
+ unsigned int nub;
+
+ reg = ®_afbc_e[enc][0];
+
+ nub = op->rd(reg[EAFBCE_MMU_NUM]);
+ return nub;
+}
+
/* set_di_afbce_cfg */
static void afbce_set(struct vframe_s *vf, enum EAFBC_ENC enc)
{
cfg->head_baddr,
cfg->mmu_info_baddr);
#endif
- cfg->reg_format_mode = 1;/*0:444 1:422 2:420*/
+ if (di_buf->afbce_out_yuv420_10)
+ cfg->reg_format_mode = 2;
+ else
+ cfg->reg_format_mode = 1;/*0:444 1:422 2:420*/
cfg->reg_compbits_y = 10;//8;/*bits num after compression*/
cfg->reg_compbits_c = 10;//8;/*bits num after compression*/
#ifdef MARK_SC2
flg_v5 = true;
#ifdef MARK_SC2
if (enc == 1) {
- cfg->reg_init_ctrl = 1;//pip init frame flag
- cfg->reg_pip_mode = 1;//pip open bit
- cfg->hsize_bgnd = 1920;//hsize of background
- cfg->vsize_bgnd = 1080;//hsize of background
+ cfg->reg_init_ctrl = 1;//pip init frame flag
+ cfg->reg_pip_mode = 1;//pip open bit
+ cfg->hsize_bgnd = 1920;//hsize of background
+ cfg->vsize_bgnd = 1080;//hsize of background
} else {
- cfg->reg_init_ctrl = 0;//pip init frame flag
- cfg->reg_pip_mode = 0;//pip open bit
- cfg->hsize_bgnd = 0;//hsize of background
- cfg->vsize_bgnd = 0;//hsize of background
+ cfg->reg_init_ctrl = 0;//pip init frame flag
+ cfg->reg_pip_mode = 0;//pip open bit
+ cfg->hsize_bgnd = 0;//hsize of background
+ cfg->vsize_bgnd = 0;//hsize of background
}
#endif
cfg->reg_init_ctrl = 0;//pip init frame flag
cfg->reg_pip_mode = 0;//pip open bit
cfg->hsize_bgnd = 0;//hsize of background
cfg->vsize_bgnd = 0;//hsize of background
- cfg->reg_ram_comb = 0;//ram split bit open in di mult write case case
+ cfg->reg_ram_comb = 0;//ram split bit open in di mult write case
cfg->rev_mode = 0;//0:normal mode
cfg->def_color_0 = 0;//def_color
vf_set_for_com(di_buf);
//head addr of compressed data
- op->wr(reg[EAFBCE_HEAD_BADDR], di_buf->afbc_adr);
- op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], di_buf->afbct_adr);
+ if (DIM_IS_IC_EF(T7)) {
+ op->wr(reg[EAFBCE_HEAD_BADDR], di_buf->afbc_adr >> 4);
+ op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], di_buf->afbct_adr >> 4);
+
+ } else {
+ op->wr(reg[EAFBCE_HEAD_BADDR], di_buf->afbc_adr);
+ op->wr(reg[EAFBCE_MMU_RMIF_CTRL4], di_buf->afbct_adr);
+ }
op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], cur_mmu_used, 0, 12);
op->bwr(reg[EAFBCE_MMU_RMIF_SCOPE_X], 0x1ffe, 16, 13);
op->bwr(reg[EAFBCE_MMU_RMIF_CTRL3], 0x1fff, 0, 13);
{
afbce_update_level1(vf, op, enc);
}
-#endif
//const unsigned int *afbce_get_addrp(enum EAFBC_ENC eidx);
/*define in vpp*/
s32 di_request_afbc_hw(u8 id, bool on);
+unsigned int afbce_read_used(enum EAFBC_ENC enc);
//bool cfg_pmode(void);
//bool cfg_test4k(void);
//bool dbg_di_prelink(void);
return ret;
}
+static unsigned int di_mif_add_get_offset_v3(enum DI_MIF0_ID mif_index);
+
+/*********************************
+ ******* linear address *******
+ ********************************/
+/* DI_MIF0_t -> DI_MIF_S*/
+static void di_mif0_stride(struct DI_MIF_S *mif,
+ unsigned int *stride_y,
+ unsigned int *stride_cb,
+ unsigned int *stride_cr
+ )
+{
+ unsigned int burst_stride_0;
+ unsigned int burst_stride_1;
+ unsigned int burst_stride_2;
+
+ //if support scope,need change this to real hsize
+ //unsigned int pic_hsize = mif->luma_x_end0 - mif->luma_x_start0 + 1;
+ unsigned int pic_hsize = mif->buf_crop_en ?
+ mif->buf_hsize : mif->luma_x_end0 - mif->luma_x_start0 + 1;
+
+ // 0:8 bits 1:10 bits 422(old mode,12bit)
+ // 2: 10bit 444 3:10bit 422(full pack) or 444
+ unsigned int comp_bits = (mif->bit_mode == 0) ? 8 :
+ (mif->bit_mode == 1) ? 12 : 10;
+
+ //00: 4:2:0; 01: 4:2:2; 10: 4:4:4
+ unsigned int comp_num = (mif->video_mode == 2) ? 3 : 2;
+
+ // 00 : one canvas; 01 : 3 canvas(old 4:2:0). 10: 2 canvas. (NV21).
+ if (mif->set_separate_en == 0) {
+ burst_stride_0 = (pic_hsize * comp_num * comp_bits + 127) >> 7;
+ //burst
+ burst_stride_1 = 0;
+ burst_stride_2 = 0;
+ } else if (mif->set_separate_en == 1) {
+ burst_stride_0 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_1 = (((pic_hsize + 1) >> 1) *
+ comp_bits + 127) >> 7;//burst
+ burst_stride_2 = (((pic_hsize + 1) >> 1) *
+ comp_bits + 127) >> 7;//burst
+ } else {
+ burst_stride_0 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_1 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_2 = 0;
+ }
+ //stimulus_display("di_mif0_burst_stride_0 = %x\n",burst_stride_0);
+
+ *stride_y = ((burst_stride_0 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+ *stride_cb = ((burst_stride_1 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+ *stride_cr = ((burst_stride_2 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+
+ //stimulus_display("di_mif0_stride: stride_y = %x\n",*stride_y);
+}
+
+static void di_mif0_stride_input(struct DI_MIF_S *mif,
+ unsigned int *stride_y,
+ unsigned int *stride_cb,
+ unsigned int *stride_cr)
+{
+ if (mif->set_separate_en == 2) {
+ //nv21 ?
+ *stride_y = (mif->cvs0_w + 15) >> 4;
+ *stride_cb = (mif->cvs1_w + 15) >> 4;
+ *stride_cr = 0;
+ } else if (mif->set_separate_en == 1) {
+ *stride_y = (mif->cvs0_w + 15) >> 4;
+ *stride_cb = (mif->cvs1_w + 15) >> 4;
+ *stride_cr = (mif->cvs2_w + 15) >> 4;
+ } else {
+ *stride_y = (mif->cvs0_w + 15) >> 4;
+ *stride_cb = 0;
+ *stride_cr = 0;
+ }
+
+ dim_print("%s: stride_y = %d %d %d\n",
+ __func__,
+ *stride_y,
+ *stride_cb,
+ *stride_cr);
+}
+
+/* DI_MIF0_t -> DI_MIF_S*/
+void di_mif0_linear_rd_cfg(struct DI_MIF_S *mif,
+ int mif_index, const struct reg_acc *ops)
+{
+ unsigned int stride_y;
+ unsigned int stride_cb;
+ unsigned int stride_cr;
+ const struct reg_acc *op;
+ unsigned int off;
+
+ if (!ops)
+ op = &di_pre_regset;
+ else
+ op = ops;
+
+ off = di_mif_add_get_offset_v3(mif_index);
+ if (off == DIM_ERR) {
+ PR_ERR("%s:\n", __func__);
+ return;
+ }
+ dbg_ic("%s:%d:off[0x%x],0x%lx,0x%lx,0x%lx\n",
+ __func__,
+ mif_index,
+ off,
+ mif->addr0,
+ mif->addr1,
+ mif->addr2);
+ if (mif_index == DI_MIF0_ID_INP)
+ di_mif0_stride_input(mif, &stride_y, &stride_cb, &stride_cr);
+ else
+ di_mif0_stride(mif, &stride_y, &stride_cb, &stride_cr);
+
+ op->bwr(off + RDMIFXN_STRIDE_1, 1, 16, 1);//linear mode
+
+ op->bwr(off + RDMIFXN_BADDR_Y, mif->addr0 >> 4, 0, 32);//linear address
+ op->bwr(off + RDMIFXN_BADDR_CB, mif->addr1 >> 4, 0, 32);//linear address
+ op->bwr(off + RDMIFXN_BADDR_CR, mif->addr2 >> 4, 0, 32);//linear address
+
+ dbg_ic("\ty[%d]cb[%d]cr[%d]\n", stride_y, stride_cb, stride_cr);
+ dbg_ic("\ty[0x%lx]cb[0x%lx]cr[0x%lx]\n", mif->addr0,
+ mif->addr1, mif->addr2);
+
+// op->bwr(off + RDMIFXN_STRIDE_0, stride_y, 0, 13);//stride
+// op->bwr(off + RDMIFXN_STRIDE_0, stride_cb, 16, 13);//stride
+// op->bwr(off + RDMIFXN_STRIDE_1, stride_cr, 0, 13);//stride
+ op->bwr(off + RDMIFXN_STRIDE_0, (stride_cb << 16) | stride_y, 0, 32);
+ //stride
+ op->bwr(off + RDMIFXN_STRIDE_1, (1 << 16) | stride_cr, 0, 32);//stride
+
+ dbg_ic("\t:reg:0x%x= 0x%x\n", off + RDMIFXN_BADDR_Y,
+ op->rd(off + RDMIFXN_BADDR_Y));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", off + RDMIFXN_BADDR_CB,
+ op->rd(off + RDMIFXN_BADDR_CB));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", off + RDMIFXN_BADDR_CR,
+ op->rd(off + RDMIFXN_BADDR_CR));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", off + RDMIFXN_STRIDE_0,
+ op->rd(off + RDMIFXN_STRIDE_0));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", off + RDMIFXN_STRIDE_1,
+ op->rd(off + RDMIFXN_STRIDE_1));
+}
+
+/* DI_MIF0_t -> DI_MIF_S*/
+void di_mif0_linear_wr_cfg(struct DI_MIF_S *mif,
+ int mif_index, const struct reg_acc *ops)
+{
+ unsigned int WRMIF_BADDR0;
+ unsigned int WRMIF_BADDR1;
+ unsigned int WRMIF_STRIDE0;
+ unsigned int WRMIF_STRIDE1;
+ unsigned int stride_y;
+ unsigned int stride_cb;
+ unsigned int stride_cr;
+ const struct reg_acc *op;
+
+ if (!ops)
+ op = &di_pre_regset;
+ else
+ op = ops;
+
+ dbg_ic("%s:%d:0x%lx,0x%lx,0x%lx\n",
+ __func__,
+ mif_index,
+ mif->addr0,
+ mif->addr1,
+ mif->addr2);
+
+ if (mif_index == 0) {
+ WRMIF_BADDR0 = DI_NRWR_BADDR0;
+ WRMIF_BADDR1 = DI_NRWR_BADDR1;
+ WRMIF_STRIDE0 = DI_NRWR_STRIDE0;
+ WRMIF_STRIDE1 = DI_NRWR_STRIDE1;
+ } else if (mif_index == 1) {
+ WRMIF_BADDR0 = DI_DIWR_BADDR0;
+ WRMIF_BADDR1 = DI_DIWR_BADDR1;
+ WRMIF_STRIDE0 = DI_DIWR_STRIDE0;
+ WRMIF_STRIDE1 = DI_DIWR_STRIDE1;
+ } else {
+ PR_ERR("ERROR:WR_MIF WRONG!!!\n");
+ return;
+ }
+
+ di_mif0_stride(mif, &stride_y, &stride_cb, &stride_cr);
+
+ op->wr(WRMIF_BADDR0, mif->addr0 >> 4);
+ op->wr(WRMIF_BADDR1, mif->addr1 >> 4);
+ op->wr(WRMIF_STRIDE0, stride_y);
+ op->wr(WRMIF_STRIDE1, stride_cb);
+}
+
+static void di_mif0_stride2(struct DI_SIM_MIF_s *mif,
+ unsigned int *stride_y,
+ unsigned int *stride_cb,
+ unsigned int *stride_cr)
+{
+ unsigned int burst_stride_0;
+ unsigned int burst_stride_1;
+ unsigned int burst_stride_2;
+
+ //if support scope,need change this to real hsize
+ //unsigned int pic_hsize = mif->luma_x_end0 - mif->luma_x_start0 + 1;
+ //unsigned int pic_hsize = mif->end_x - mif->start_x + 1;
+ unsigned int pic_hsize = mif->buf_crop_en ?
+ mif->buf_hsize : mif->end_x - mif->start_x + 1;
+ // 0:8 bits 1:10 bits 422(old mode,12bit)
+ // 2: 10bit 444 3:10bit 422(full pack) or 444
+ unsigned int comp_bits = (mif->bit_mode == 0) ? 8 :
+ (mif->bit_mode == 1) ? 12 : 10;
+
+ //00: 4:2:0; 01: 4:2:2; 10: 4:4:4
+ unsigned int comp_num = (mif->video_mode == 2) ? 3 : 2;
+
+ // 00 : one canvas; 01 : 3 canvas(old 4:2:0). 10: 2 canvas. (NV21).
+ if (mif->set_separate_en == 0) {
+ burst_stride_0 = (pic_hsize * comp_num * comp_bits + 127) >> 7;
+ //burst
+ burst_stride_1 = 0;
+ burst_stride_2 = 0;
+ } else if (mif->set_separate_en == 1) {
+ burst_stride_0 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_1 = (((pic_hsize + 1) >> 1) *
+ comp_bits + 127) >> 7;//burst
+ burst_stride_2 = (((pic_hsize + 1) >> 1) *
+ comp_bits + 127) >> 7;//burst
+ } else {
+ burst_stride_0 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_1 = (pic_hsize * comp_bits + 127) >> 7;//burst
+ burst_stride_2 = 0;
+ }
+ dbg_ic("di_mif0_stride: burst_stride_0 = %x\n", burst_stride_0);
+
+ *stride_y = ((burst_stride_0 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+ *stride_cb = ((burst_stride_1 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+ *stride_cr = ((burst_stride_2 + 3) >> 2) << 2;
+ //now need 64bytes aligned
+
+ dbg_ic("\t: y[%d] cb[%d] cr[%d]\n", *stride_y, *stride_cb, *stride_cr);
+}
+
+/* DI_MIF0_t -> DI_SIM_MIF_s*/
+void di_mif0_linear_wr_cfg2(struct DI_SIM_MIF_s *mif, int mif_index)
+{
+ unsigned int WRMIF_BADDR0;
+ unsigned int WRMIF_BADDR1;
+ unsigned int WRMIF_STRIDE0;
+ unsigned int WRMIF_STRIDE1;
+ unsigned int stride_y;
+ unsigned int stride_cb;
+ unsigned int stride_cr;
+ const struct reg_acc *op = &di_pre_regset;
+
+ dbg_ic("%s:%d:0x%lx,0x%lx,0x%lx\n",
+ __func__,
+ mif_index,
+ mif->addr,
+ mif->addr1,
+ mif->addr2);
+
+ if (mif_index == 0) {
+ WRMIF_BADDR0 = DI_NRWR_BADDR0;
+ WRMIF_BADDR1 = DI_NRWR_BADDR1;
+ WRMIF_STRIDE0 = DI_NRWR_STRIDE0;
+ WRMIF_STRIDE1 = DI_NRWR_STRIDE1;
+ } else if (mif_index == 1) {
+ WRMIF_BADDR0 = DI_DIWR_BADDR0;
+ WRMIF_BADDR1 = DI_DIWR_BADDR1;
+ WRMIF_STRIDE0 = DI_DIWR_STRIDE0;
+ WRMIF_STRIDE1 = DI_DIWR_STRIDE1;
+ } else {
+ PR_ERR("ERROR:WR_MIF WRONG!!!\n");
+ return;
+ }
+
+ di_mif0_stride2(mif, &stride_y, &stride_cb, &stride_cr);
+
+ op->wr(WRMIF_BADDR0, mif->addr >> 4);
+ op->wr(WRMIF_BADDR1, mif->addr1 >> 4);
+ op->wr(WRMIF_STRIDE0, stride_y);
+ op->wr(WRMIF_STRIDE1, stride_cb);
+ dbg_ic("\t:reg:0x%x= 0x%x\n", WRMIF_BADDR0, op->rd(WRMIF_BADDR0));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", WRMIF_BADDR1, op->rd(WRMIF_BADDR1));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", WRMIF_STRIDE0, op->rd(WRMIF_STRIDE0));
+ dbg_ic("\t:reg:0x%x= 0x%x\n", WRMIF_STRIDE1, op->rd(WRMIF_STRIDE1));
+}
+
+/* struct DI_MIF1_t -> DI_SIM_MIF_s*/
+static void di_mif1_stride2(unsigned int per_bits,
+ unsigned int pic_hsize,
+ unsigned int *stride)
+{
+ //if support scope,need change this to real hsize
+ //unsigned int pic_hsize = mif->end_x - mif->start_x + 1;
+
+ *stride = (pic_hsize * per_bits + 511) >> 9;//burst
+ *stride = (*stride) << 2;
+ //now need 64bytes aligned,
+ //just set 32bytes aligned(DDR change to burst2 align)
+ //because of previous data are 32bytes aligned
+}
+
+void di_mif1_linear_rd_cfg(struct DI_SIM_MIF_s *mif,
+ unsigned int CTRL1,
+ unsigned int CTRL2,
+ unsigned int BADDR)
+{
+ unsigned int stride;
+ const struct reg_acc *op = &di_pre_regset;
+
+ dbg_ic("%s:\n", __func__);
+ //di_mif1_stride(mif, &stride);
+ di_mif1_stride2(mif->per_bits,
+ (mif->end_x - mif->start_x + 1), &stride);
+ op->bwr(CTRL1, 1, 3, 1);//linear_mode
+ op->bwr(CTRL2, stride, 0, 13);//stride
+ op->wr(BADDR, mif->addr >> 4);//base_addr
+ dbg_ic("stride[%d],per_bits[%d]\n", stride, mif->per_bits);
+ dbg_ic("reg[0x%x] = 0x%x\n", CTRL1, op->rd(CTRL1));
+ dbg_ic("reg[0x%x] = 0x%x\n", CTRL2, op->rd(CTRL2));
+ dbg_ic("reg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR));
+}
+
+static void di_mif1_linear_wr_cfg(struct DI_SIM_MIF_s *mif,
+ unsigned int STRIDE,
+ unsigned int BADDR)
+{
+ unsigned int stride;
+ const struct reg_acc *op = &di_pre_regset;
+
+ dbg_ic("%s:\n", __func__);
+ //di_mif1_stride(mif, &stride);
+ di_mif1_stride2(mif->per_bits,
+ (mif->end_x - mif->start_x + 1), &stride);
+ op->wr(STRIDE, (0 << 31) | stride);//stride
+ op->wr(BADDR, mif->addr >> 4);//base_addr
+ dbg_ic("\tstride[%d],per_bits[%d]\n", stride, mif->per_bits);
+ dbg_ic("\treg[0x%x] = 0x%x\n", STRIDE, op->rd(STRIDE));
+ dbg_ic("\treg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR));
+}
+
+void di_mcmif_linear_rd_cfg(struct DI_MC_MIF_s *mif,
+ unsigned int CTRL1,
+ unsigned int CTRL2,
+ unsigned int BADDR)
+{
+ unsigned int stride;
+ const struct reg_acc *op = &di_pre_regset;
+
+ dbg_ic("%s:\n", __func__);
+ //di_mif1_stride(mif, &stride);
+ di_mif1_stride2(mif->per_bits, mif->size_x, &stride);
+ op->bwr(CTRL1, 1, 3, 1);//linear_mode
+ op->bwr(CTRL2, stride, 0, 13);//stride
+ op->wr(BADDR, mif->addr >> 4);//base_addr
+
+ dbg_ic("stride[%d],per_bits[%d]\n", stride, mif->per_bits);
+ dbg_ic("reg[0x%x] = 0x%x\n", CTRL1, op->rd(CTRL1));
+ dbg_ic("reg[0x%x] = 0x%x\n", CTRL2, op->rd(CTRL2));
+ dbg_ic("reg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR));
+}
+
+static void di_mcmif_linear_wr_cfg(struct DI_MC_MIF_s *mif,
+ unsigned int STRIDE,
+ unsigned int BADDR)
+{
+ unsigned int stride;
+ const struct reg_acc *op = &di_pre_regset;
+
+ dbg_ic("%s:\n", __func__);
+ //di_mif1_stride(mif, &stride);
+ di_mif1_stride2(mif->per_bits, mif->size_x, &stride);
+ op->wr(STRIDE, (0 << 31) | stride);//stride
+ op->wr(BADDR, mif->addr >> 4);//base_addr
+ dbg_ic("\tstride[%d],per_bits[%d]\n", stride, mif->per_bits);
+ dbg_ic("\treg[0x%x] = 0x%x\n", STRIDE, op->rd(STRIDE));
+ dbg_ic("\treg[0x%x] = 0x%x\n", BADDR, op->rd(BADDR));
+}
+
+//set_ma_pre_mif_g12
+static void set_ma_pre_mif_t7(void *pre,
+ unsigned short urgent)
+{
+ struct DI_SIM_MIF_s *mtnwr_mif;
+ struct DI_SIM_MIF_s *contprd_mif;
+ struct DI_SIM_MIF_s *contp2rd_mif;
+ struct DI_SIM_MIF_s *contwr_mif;
+ const struct reg_acc *op = &di_pre_regset;
+ struct di_pre_stru_s *ppre = (struct di_pre_stru_s *)pre;
+
+ dbg_ic("%s:\n", __func__);
+ mtnwr_mif = &ppre->di_mtnwr_mif;
+ contp2rd_mif = &ppre->di_contp2rd_mif;
+ contprd_mif = &ppre->di_contprd_mif;
+ contwr_mif = &ppre->di_contwr_mif;
+
+ mtnwr_mif->per_bits = 4;
+ contp2rd_mif->per_bits = 4;
+ contprd_mif->per_bits = 4;
+ contwr_mif->per_bits = 4;
+
+ op->bwr(CONTRD_SCOPE_X, contprd_mif->start_x, 0, 13);
+ op->bwr(CONTRD_SCOPE_X, contprd_mif->end_x, 16, 13);
+ op->bwr(CONTRD_SCOPE_Y, contprd_mif->start_y, 0, 13);
+ op->bwr(CONTRD_SCOPE_Y, contprd_mif->end_y, 16, 13);
+ //DIM_RDMA_WR_BITS(CONTRD_CTRL1, contprd_mif->canvas_num, 16, 8);
+ op->bwr(CONTRD_CTRL1, 2, 8, 2);
+ op->bwr(CONTRD_CTRL1, 0, 0, 3);
+ di_mif1_linear_rd_cfg(contprd_mif,
+ CONTRD_CTRL1,
+ CONTRD_CTRL2,
+ CONTRD_BADDR);
+
+ op->bwr(CONT2RD_SCOPE_X, contp2rd_mif->start_x, 0, 13);
+ op->bwr(CONT2RD_SCOPE_X, contp2rd_mif->end_x, 16, 13);
+ op->bwr(CONT2RD_SCOPE_Y, contp2rd_mif->start_y, 0, 13);
+ op->bwr(CONT2RD_SCOPE_Y, contp2rd_mif->end_y, 16, 13);
+ //DIM_RDMA_WR_BITS(CONT2RD_CTRL1, contp2rd_mif->canvas_num, 16, 8);
+ op->bwr(CONT2RD_CTRL1, 2, 8, 2);
+ op->bwr(CONT2RD_CTRL1, 0, 0, 3);
+ di_mif1_linear_rd_cfg(contp2rd_mif,
+ CONT2RD_CTRL1,
+ CONT2RD_CTRL2,
+ CONT2RD_BADDR);
+
+ /* current field mtn canvas index. */
+ op->bwr(MTNWR_X, mtnwr_mif->start_x, 16, 13);
+ op->bwr(MTNWR_X, mtnwr_mif->end_x, 0, 13);
+ op->bwr(MTNWR_X, 2, 30, 2);
+ op->bwr(MTNWR_Y, mtnwr_mif->start_y, 16, 13);
+ op->bwr(MTNWR_Y, mtnwr_mif->end_y, 0, 13);
+ //DIM_RDMA_WR_BITS(MTNWR_CTRL, mtnwr_mif->canvas_num, 0, 8);
+ op->bwr(MTNWR_CAN_SIZE,
+ (mtnwr_mif->end_y - mtnwr_mif->start_y), 0, 13);
+ op->bwr(MTNWR_CAN_SIZE,
+ (mtnwr_mif->end_x - mtnwr_mif->start_x), 16, 13);
+ di_mif1_linear_wr_cfg(mtnwr_mif, MTNWR_STRIDE, MTNWR_BADDR);
+
+ op->bwr(CONTWR_X, contwr_mif->start_x, 16, 13);
+ op->bwr(CONTWR_X, contwr_mif->end_x, 0, 13);
+ op->bwr(CONTWR_X, 2, 30, 2);
+ op->bwr(CONTWR_Y, contwr_mif->start_y, 16, 13);
+ op->bwr(CONTWR_Y, contwr_mif->end_y, 0, 13);
+ //DIM_RDMA_WR_BITS(CONTWR_CTRL, contwr_mif->canvas_num, 0, 8);
+ op->bwr(CONTWR_CAN_SIZE,
+ (contwr_mif->end_y - contwr_mif->start_y), 0, 13);
+ op->bwr(CONTWR_CAN_SIZE,
+ (contwr_mif->end_x - contwr_mif->start_x), 16, 13);
+ di_mif1_linear_wr_cfg(contwr_mif, CONTWR_STRIDE, CONTWR_BADDR);
+}
+
+//set_post_mtnrd_mif_g12
+static void set_post_mtnrd_mif_t7(struct DI_SIM_MIF_s *mtnprd_mif)
+{
+ dbg_ic("%s:", __func__);
+ DIM_VSYNC_WR_MPEG_REG(MTNRD_SCOPE_X,
+ (mtnprd_mif->end_x << 16) |
+ (mtnprd_mif->start_x));
+ DIM_VSYNC_WR_MPEG_REG(MTNRD_SCOPE_Y,
+ (mtnprd_mif->end_y << 16) |
+ (mtnprd_mif->start_y));
+ //DIM_VSC_WR_MPG_BT(MTNRD_CTRL1, mtnprd_mif->canvas_num, 16, 8);
+ DIM_VSC_WR_MPG_BT(MTNRD_CTRL1, 0, 0, 3);
+ di_mif1_linear_rd_cfg(mtnprd_mif,
+ MTNRD_CTRL1, MTNRD_CTRL2, MTNRD_BADDR);
+}
+
+//dimh_enable_mc_di_pre_g12
+static void pre_enable_mc_t7(struct DI_MC_MIF_s *mcinford_mif,
+ struct DI_MC_MIF_s *mcinfowr_mif,
+ struct DI_MC_MIF_s *mcvecwr_mif,
+ unsigned char mcdi_en)
+{
+ dbg_ic("%s:", __func__);
+ DIM_RDMA_WR_BITS(MCDI_MOTINEN, (mcdi_en ? 3 : 0), 0, 2);
+
+ if (is_meson_g12a_cpu() ||
+ is_meson_g12b_cpu() ||
+ is_meson_sm1_cpu()) {
+ DIM_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfef7ff : 0));
+ } else if (DIM_IS_IC_EF(SC2)) {//from vlsi yanling
+ if (mcdi_en) {
+ DIM_RDMA_WR_BITS(MCDI_CTRL_MODE, 0xf7ff, 0, 16);
+ DIM_RDMA_WR_BITS(MCDI_CTRL_MODE, 0xdff, 17, 15);
+ } else {
+ DIM_RDMA_WR(MCDI_CTRL_MODE, 0);
+ }
+ } else {
+ DIM_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfff7ff : 0));
+ }
+
+ mcinford_mif->per_bits = 16;
+ mcinfowr_mif->per_bits = 16;
+ mcvecwr_mif->per_bits = 16;
+ DIM_RDMA_WR_BITS(DI_PRE_CTRL, (mcdi_en ? 3 : 0), 16, 2);
+
+ DIM_RDMA_WR_BITS(MCINFRD_SCOPE_X, mcinford_mif->size_x, 16, 13);
+ DIM_RDMA_WR_BITS(MCINFRD_SCOPE_Y, mcinford_mif->size_y, 16, 13);
+ //DIM_RDMA_WR_BITS(MCINFRD_CTRL1, mcinford_mif->canvas_num, 16, 8);
+ DIM_RDMA_WR_BITS(MCINFRD_CTRL1, 2, 0, 3);
+ di_mcmif_linear_rd_cfg(mcinford_mif,
+ MCINFRD_CTRL1,
+ MCINFRD_CTRL2,
+ MCINFRD_BADDR);
+
+ DIM_RDMA_WR_BITS(MCVECWR_X, mcvecwr_mif->size_x, 0, 13);
+ DIM_RDMA_WR_BITS(MCVECWR_Y, mcvecwr_mif->size_y, 0, 13);
+ //DIM_RDMA_WR_BITS(MCVECWR_CTRL, mcvecwr_mif->canvas_num, 0, 8);
+ DIM_RDMA_WR_BITS(MCVECWR_CAN_SIZE, mcvecwr_mif->size_y, 0, 13);
+ DIM_RDMA_WR_BITS(MCVECWR_CAN_SIZE, mcvecwr_mif->size_x, 16, 13);
+ di_mcmif_linear_wr_cfg(mcvecwr_mif, MCVECWR_STRIDE, MCVECWR_BADDR);
+
+ DIM_RDMA_WR_BITS(MCINFWR_X, mcinfowr_mif->size_x, 0, 13);
+ DIM_RDMA_WR_BITS(MCINFWR_Y, mcinfowr_mif->size_y, 0, 13);
+ //DIM_RDMA_WR_BITS(MCINFWR_CTRL, mcinfowr_mif->canvas_num, 0, 8);
+ DIM_RDMA_WR_BITS(MCINFWR_CAN_SIZE, mcinfowr_mif->size_y, 0, 13);
+ DIM_RDMA_WR_BITS(MCINFWR_CAN_SIZE, mcinfowr_mif->size_x, 16, 13);
+ di_mcmif_linear_wr_cfg(mcinfowr_mif, MCINFWR_STRIDE, MCINFWR_BADDR);
+}
+
unsigned int dw_get_h(void)
{ //bit 15: enable dw
//bit 14: show
int lossy_luma_en;
int lossy_chrm_en;
- int reg_fmt444_comb;//caculate
- int uncmp_size;//caculate
- int uncmp_bits;//caculate
- int sblk_num;//caculate
+ int reg_fmt444_comb;//calculate
+ int uncmp_size;//calculate
+ int uncmp_bits;//calculate
+ int sblk_num;//calculate
int cur_mmu_used = 0;//mmu info linear addr
const struct reg_acc *op;
((hblksize_buf & 0x1fff) << 16) | // out blk hsize
((vblksize_buf & 0x1fff) << 0) // out blk vsize
);
+ if (DIM_IS_IC(T7))
+ op->wr(reg[AFBCEX_HEAD_BADDR], afbce->head_baddr >> 4);
+ else
+ op->wr(reg[AFBCEX_HEAD_BADDR], afbce->head_baddr);
- op->wr(reg[AFBCEX_HEAD_BADDR], afbce->head_baddr);
//head addr of compressed data
op->bwr(reg[AFBCEX_MIF_SIZE],
op->wr(reg[AFBCEX_PIXEL_IN_HOR_SCOPE],
((afbce->enc_win_end_h & 0x1fff) << 16) |
- // scope of hsize_in ,should be a integer multipe of 32
+ // scope of hsize_in ,should be a integer multiple of 32
((afbce->enc_win_bgn_h & 0x1fff) << 0)
- // scope of vsize_in ,should be a integer multipe of 4
+ // scope of vsize_in ,should be a integer multiple of 4
);
op->wr(reg[AFBCEX_PIXEL_IN_VER_SCOPE],
((afbce->enc_win_end_v & 0x1fff) << 16) |
- // scope of hsize_in ,should be a integer multipe of 32
+ // scope of hsize_in ,should be a integer multiple of 32
((afbce->enc_win_bgn_v & 0x1fff) << 0));
- // scope of vsize_in ,should be a integer multipe of 4
+ // scope of vsize_in ,should be a integer multiple of 4
op->wr(reg[AFBCEX_CONV_CTRL], lbuf_depth);//fix 256
//ary temp cur_mmu_used += op->rd(AFBCE_MMU_NUM);
//4k addr have used in every frame;
-
- op->wr(reg[AFBCEX_MMU_RMIF_CTRL4], afbce->mmu_info_baddr);
+ if (DIM_IS_IC(T7))
+ op->wr(reg[AFBCEX_MMU_RMIF_CTRL4], afbce->mmu_info_baddr >> 4);
+ else
+ op->wr(reg[AFBCEX_MMU_RMIF_CTRL4], afbce->mmu_info_baddr);
op->bwr(reg[AFBCEX_MMU_RMIF_CTRL1], 0x1, 6, 1);//litter_endia
if (afbce->reg_pip_mode)
op->bwr(reg[AFBCEX_MMU_RMIF_SCOPE_X], 0x0, 0, 13);
op->wr(MCDI_BLKTOTAL, blkhsize * vsize);
op->wr(MCDI_MOTINEN, 1 << 1);
//enable motin refinement ary:in dimh_enable_mc_di_pre_g12
- //op->wr(MCDI_REF_MV_NUM, 2);
+ if (!DIM_IS_IC(SC2))
+ op->wr(MCDI_REF_MV_NUM, 2);
//ary : in mc_di_param_init
op->wr(MCDI_CTRL_MODE, op->rd(MCDI_CTRL_MODE) |
//ary : dimh_mc_pre_mv_irq
return &mif_contr_reg[mif_index][0];
}
-#if 1
static void set_di_mif_v1(struct DI_MIF_S *mif,
enum DI_MIF0_ID mif_index, const struct reg_acc *op)
{
// ----------------------
// Canvas
// ----------------------
- op->wr(off + RDMIFXN_CANVAS0, (mif->canvas0_addr2 << 16) |
- // cntl_canvas0_addr2
- (mif->canvas0_addr1 << 8) | // cntl_canvas0_addr1
- (mif->canvas0_addr0 << 0) // cntl_canvas0_addr0
- );
+ if (mif->linear)
+ di_mif0_linear_rd_cfg(mif, mif_index, op);
+ else
+ op->wr(off + RDMIFXN_CANVAS0, (mif->canvas0_addr2 << 16) |
+ // cntl_canvas0_addr2
+ (mif->canvas0_addr1 << 8) | // cntl_canvas0_addr1
+ (mif->canvas0_addr0 << 0) // cntl_canvas0_addr0
+ );
// ----------------------
// Picture 0 X/Y start,end
// Dummy pixel value
op->wr(off + RDMIFXN_DUMMY_PIXEL, 0x00808000);
- if ((mif->video_mode == 0)) {// 4:2:0 block mode.
+ if (mif->video_mode == 0) {// 4:2:0 block mode.
hfmt_en = 1;
hz_yc_ratio = 1;
hz_ini_phase = 0;
(c_length << 0) //vt format width
);
}
-#endif
static const unsigned int reg_wrmif_v3
[DIM_WRMIF_MIF_V3_NUB][DIM_WRMIF_SET_V3_NUB] = {
//////Afbce addreess mux
////////////////////////////
if (mifsel > (DIM_WRMIF_MIF_V3_NUB - 1)) {
- stimulus_print("ERROR:WR_MIF WRONG!!!\n");
+ PR_ERR("%s:%d\n", __func__, mifsel);
return;
}
if (!ops)
//printf("wr_mif_scope = %d %d %d %d",wr_mif->luma_x_start0,
//wr_mif->luma_x_end0,wr_mif->luma_y_start0,
//wr_mif->luma_y_end0);
-
- op->wr(reg[WRMIF_CANVAS], mif->canvas_num);
+ if (mif->linear)
+ di_mif0_linear_wr_cfg2(mif, mifsel);
+ else
+ op->wr(reg[WRMIF_CANVAS], mif->canvas_num);
if (mif->set_separate_en == 2) {
op->wr(reg[WRMIF_CTRL],
(mif->en << 0) | // write mif en.
(0 << 24) | // no gate clock
(0 << 25) | // canvas_sync enable
(2 << 26) | // burst lim
- (1 << 30)); // 64-bits swap enable
+ (mif->reg_swap << 30)); // 64-bits swap enable
} else {
- op->wr(reg[WRMIF_CTRL],
- (mif->en << 0) | // write mif en.
- (bits_mode << 1) | // bit10 mode
- (mif->l_endian << 2) | // little endian
- (0 << 3) | // data ext enable
- (5 << 4) | // word limit ?
- (mif->urgent << 16) | // urgent // ary default is 0 ?
- (mif->cbcr_swap << 17) |
- // swap cbcrworking in rgb mode =2: swap cbcr
- (0 << 18) | // vconv working in rgb mode =2:
- (0 << 20) | // hconv. output even pixel
- (rgb_mode << 22) |
- // rgb mode =0, 422 YCBCR to one canvas.
- (0 << 24) | // no gate clock
- (0 << 25) | // canvas_sync enable
- (2 << 26) | // burst lim
- (1 << 30)); // 64-bits swap enable
+ op->wr(reg[WRMIF_CTRL],
+ (mif->en << 0) | // write mif en.
+ (bits_mode << 1) | // bit10 mode
+ (mif->l_endian << 2) | // little endian
+ (0 << 3) | // data ext enable
+ (5 << 4) | // word limit ?
+ (mif->urgent << 16) | // urgent // ary default is 0 ?
+ (mif->cbcr_swap << 17) |
+ // swap cbcrworking in rgb mode =2: swap cbcr
+ (0 << 18) | // vconv working in rgb mode =2:
+ (0 << 20) | // hconv. output even pixel
+ (rgb_mode << 22) |
+ // rgb mode =0, 422 YCBCR to one canvas.
+ (0 << 24) | // no gate clock
+ (0 << 25) | // canvas_sync enable
+ (2 << 26) | // burst lim
+ (mif->reg_swap << 30)); // 64-bits swap enable
}
}
} else {
vf = (struct vframe_s *)di_vf;
+ di_buf = (struct di_buf_s *)vf->private_data;
+ if (!di_buf) {
+ PR_ERR("%s:no di_buf\n", __func__);
+ return;
+ }
}
wr_mif->start_x = 0;
wr_mif->end_x = vf->width - 1;
wr_mif->start_y = 0;
+ //tmp for t7:
+ wr_mif->buf_crop_en = 1;
+ //wr_mif->buf_hsize = 1920;
+ wr_mif->buf_hsize = di_buf->buf_hsize;
if (vf->bitdepth & BITDEPTH_Y10) {
if (vf->type & VIDTYPE_VIU_444) {
else
wr_mif->end_y = vf->height - 1;
} else {
- wr_mif->end_y = vf->height - 1;
+ if (dim_dbg_cfg_post_byapss())
+ wr_mif->end_y = vf->height / 2 - 1;
+ else
+ wr_mif->end_y = vf->height - 1;
}
}
////////////////////////////////
if (pre_wrmif_enable) {
- set_wrmif_simple(
- 0,
- //int index ,
- pre_wrmif_enable,
- //int enable ,
- pre_mif,
- //DI_MIF0_t *wr_mif
- op
- );
+ set_wrmif_simple(0,
+ //int index ,
+ pre_wrmif_enable,
+ //int enable ,
+ pre_mif,
+ //DI_MIF0_t *wr_mif
+ op);
}
if (pre_afbce_enable) {
- set_afbce_cfg_v1(
- 1,
- //int index ,
- //0:vdin_afbce 1:di_afbce0 2:di_afbce1
- pre_afbce_enable,
- //int enable ,
- //open nbit of afbce
- pre_afbce,
- //AFBCE_t *afbce
- op
- );
+ set_afbce_cfg_v1(1,
+ //int index ,
+ //0:vdin_afbce 1:di_afbce0 2:di_afbce1
+ pre_afbce_enable,
+ //int enable ,
+ //open nbit of afbce
+ pre_afbce,
+ //AFBCE_t *afbce
+ op);
}
}
////////////////////////////////
if (post_wrmif_enable) {
- set_wrmif_simple(
- 1,//int index ,
- post_wrmif_enable,//int enable ,
- post_mif, //DI_MIF0_t *wr_mif
- op
- );
+ set_wrmif_simple(1,//int index ,
+ post_wrmif_enable,//int enable ,
+ post_mif, //DI_MIF0_t *wr_mif
+ op);
}
if (post_afbce_enable) {
- set_afbce_cfg_v1(
- 2,//int index ,
+ set_afbce_cfg_v1(2, post_afbce_enable, post_afbce, op);
+ //int index ,
//0:vdin_afbce 1:di_afbce0 2:di_afbce1
- post_afbce_enable,//int enable ,
+ //int enable ,
//open nbit of afbce
- post_afbce, //AFBCE_t *afbce
- op
- );
+ //AFBCE_t *afbce
}
}
////////////////////////////////
//////Cofigure Wrmif and Afbce
////////////////////////////////
- set_di_pre_write(
- mwcfg->pre_path_sel,//uint32_t pre_path_sel ,
- mwcfg->pre_mif,//DI_MIF0_t *pre_mif ,
- mwcfg->pre_afbce, //AFBCE_t *pre_afbce ,
- op);
-
- set_di_post_write(
- mwcfg->post_path_sel,//uint32_t pre_path_sel ,
-
- mwcfg->post_mif,//DI_MIF0_t *pre_mif ,
- mwcfg->post_afbce,//AFBCE_t *pre_afbce ,
- op);
+ set_di_pre_write(mwcfg->pre_path_sel,//uint32_t pre_path_sel ,
+ mwcfg->pre_mif,//DI_MIF0_t *pre_mif ,
+ mwcfg->pre_afbce, //AFBCE_t *pre_afbce ,
+ op);
+
+ set_di_post_write(mwcfg->post_path_sel,//uint32_t pre_path_sel ,
+ mwcfg->post_mif,//DI_MIF0_t *pre_mif ,
+ mwcfg->post_afbce,//AFBCE_t *pre_afbce ,
+ op);
}
static void set_di_pre(struct DI_PRE_S *pcfg, const struct reg_acc *opin)
p2_mif_en = p2_en && (p2_hsize == pre_hsize_o) &&
(p2_vsize == pre_vsize_o);
- set_afbcd_mult_simple(
- EAFBC_DEC2_DI,//di_inp_afbc->index,
- pcfg->inp_afbc,
- op);//AFBCD_t *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC2_DI,//di_inp_afbc->index,
+ pcfg->inp_afbc,
+ op);//AFBCD_t *afbcd
if (p2_mif_en) {
- set_afbcd_mult_simple(
- EAFBC_DEC3_MEM,//di_mem_afbc->index,
- pcfg->mem_afbc,
- op); //AFBCD_t *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC3_MEM,
+ //di_mem_afbc->index,
+ pcfg->mem_afbc,
+ op); //AFBCD_t *afbcd
}
if (p1_mif_en) {
- set_afbcd_mult_simple(
- EAFBC_DEC_CHAN2,//di_chan2_afbc->index,
- pcfg->chan2_afbc,
- op);//AFBCD_t *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC_CHAN2,
+ //di_chan2_afbc->index,
+ pcfg->chan2_afbc,
+ op);//AFBCD_t *afbcd
}
if (pcfg->nr_en) {
- set_afbce_cfg_v1(
- 1,//int index ,
+ set_afbce_cfg_v1(1, 1, pcfg->nrwr_afbc, op);
+ //int index ,
//0:vdin_afbce 1:di_afbce0 2:di_afbce1
- 1,//int enable ,
+ //int enable ,
//open nbit of afbce
- pcfg->nrwr_afbc,
- op);//AFBCE_t *afbce
+ //AFBCE_t *afbce
}
} else {
pre_hsize_i = pcfg->inp_mif->luma_x_end0 -
(pcfg->nrwr_mif->luma_y_start0 << 16) |
(pcfg->nrwr_mif->luma_y_end0));
// start_y 0 end_y 239.
- op->wr(DI_NRWR_CANVAS,
- pcfg->nrwr_mif->canvas0_addr0 |
- (pcfg->nrwr_mif->canvas0_addr1 << 8));
+ if (pcfg->nrwr_mif->linear)
+ di_mif0_linear_wr_cfg(pcfg->nrwr_mif, 0, op);
+ else
+ op->wr(DI_NRWR_CANVAS,
+ pcfg->nrwr_mif->canvas0_addr0 |
+ (pcfg->nrwr_mif->canvas0_addr1 << 8));
bits_mode = pcfg->nrwr_mif->bit_mode != 0;
//1: 10bits 422(old mode)
// 0:8bits 2:10bit 444 3:10bit full-pack
if (ptcfg->post_en) {
if (ptcfg->afbc_en) {
- set_afbcd_mult_simple(
- EAFBC_DEC_IF0,//di_buf0_afbc->index,
- ptcfg->buf0_afbc, op);//AFBCD *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC_IF0,
+ //di_buf0_afbc->index,
+ ptcfg->buf0_afbc, op);
+ //AFBCD *afbcd
if (weave_en || ptcfg->blend_en) {
- set_afbcd_mult_simple(
- EAFBC_DEC_IF1,//di_buf1_afbc->index,
- ptcfg->buf1_afbc, op);//AFBCD *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC_IF1,
+ //di_buf1_afbc->index,
+ ptcfg->buf1_afbc, op);
+ //AFBCD *afbcd
}
if (ptcfg->blend_en) {
- set_afbcd_mult_simple(
- EAFBC_DEC_IF2,//di_buf2_afbc->index,
- ptcfg->buf2_afbc, op);//AFBCD *afbcd
+ set_afbcd_mult_simple(EAFBC_DEC_IF2,
+ //di_buf2_afbc->index,
+ ptcfg->buf2_afbc, op);
+ //AFBCD *afbcd
}
post_hsize1 = ptcfg->buf0_afbc->hsize;
}
// motion for current display field.
if (ptcfg->blend_en) {
- op->wr(MCDI_LMV_GAINTHD, (3 << 20)); //normal di
+ if (DIM_IS_IC(SC2))
+ op->wr(MCDI_LMV_GAINTHD, (3 << 20));//normal di
+ else
+ op->wr(DI_BLEND_CTRL, (3 << 20));//normal di
op->wr(MTNRD_SCOPE_X,
(ptcfg->mtn_mif->start_x) |
if (ptcfg->ddr_en) {
if (ptcfg->afbc_en) {
- set_afbce_cfg_v1(
- 2,
+ set_afbce_cfg_v1(2, 1, ptcfg->wr_afbc, op);
//int index ,
//0:vdin_afbce 1:di_afbce0 2:di_afbce1
- 1,
//int enable ,
//open nbit of afbce
- ptcfg->wr_afbc, op);//AFBCE_t *afbce
+ //AFBCE_t *afbce
post_hsize2 = ptcfg->wr_afbc->hsize_in;
post_vsize2 = ptcfg->wr_afbc->vsize_in;
} else {
(ptcfg->wr_mif->luma_y_start0 << 16) |
(ptcfg->wr_mif->luma_y_end0));
// start_y 0 end_y 239.
- op->wr(DI_DIWR_CANVAS, ptcfg->wr_mif->canvas0_addr0 |
- (ptcfg->wr_mif->canvas0_addr1 << 8));
+ if (ptcfg->wr_mif->linear)
+ di_mif0_linear_wr_cfg(ptcfg->wr_mif, 1, op);
+ else
+ op->wr(DI_DIWR_CANVAS,
+ ptcfg->wr_mif->canvas0_addr0 |
+ (ptcfg->wr_mif->canvas0_addr1 << 8));
bits_mode = ptcfg->wr_mif->bit_mode != 0;
//1: 10bits 0:8bits
// rgb_mode 0: 422 to one canvas
op->wr(DI_SC2_NRWR_Y, op->rd(DI_SC2_NRWR_Y) |
(ppcfg->nrwr_mif->luma_y_start0 << 16) |
(ppcfg->nrwr_mif->luma_y_end0)); // start_y 0 end_y 239.
- op->wr(DI_NRWR_CANVAS, ppcfg->nrwr_mif->canvas0_addr0);
+ if (ppcfg->nrwr_mif->linear)
+ di_mif0_linear_wr_cfg(ppcfg->nrwr_mif, 0, op);
+ else
+ op->wr(DI_NRWR_CANVAS, ppcfg->nrwr_mif->canvas0_addr0);
op->wr(DI_SC2_NRWR_CTRL, (1 << 0) | // write mif en.
(0 << 1) | // bit10 mode
(0 << 2) | // little endian
(ppcfg->diwr_mif->luma_x_end0)); // start_x 0 end_x 719.
op->wr(DI_SC2_DIWR_Y, (ppcfg->diwr_mif->luma_y_start0 << 16) |
(ppcfg->diwr_mif->luma_y_end0)); // start_y 0 end_y 239.
- op->wr(DI_DIWR_CANVAS,
- ppcfg->diwr_mif->canvas0_addr0 |
- (ppcfg->diwr_mif->canvas0_addr1 << 8));
+ if (ppcfg->diwr_mif->linear)
+ di_mif0_linear_wr_cfg(ppcfg->diwr_mif, 1, op);
+ else
+ op->wr(DI_DIWR_CANVAS,
+ ppcfg->diwr_mif->canvas0_addr0 |
+ (ppcfg->diwr_mif->canvas0_addr1 << 8));
op->wr(DI_SC2_DIWR_CTRL, (1 << 0) | // write mif en.
(0 << 1) | // bit10 mode
(0 << 2) | // little endian
(ppcfg->pre_field_num << 29));
// pre_field_num = pre_ctrl[29];
- op->wr(MCDI_LMV_GAINTHD, (3 << 20));
+ if (DIM_IS_IC(SC2))
+ op->wr(MCDI_LMV_GAINTHD, (3 << 20));
+ else
+ op->wr(DI_BLEND_CTRL, (3 << 20));
op->wr(DI_POST_CTRL,
(1 << 0) | // di_post_en = post_ctrl[0];
set_afbcd_mult_simple(EAFBC_DEC_IF1, pafcfg->if1_afbc, op);
// set nr wr mif interface.
- set_afbce_cfg_v1(
- 1,
+ set_afbce_cfg_v1(1, 1, pafcfg->nrwr_afbc, op);
//int index,
//0:vdin_afbce 1:di_afbce0 2:di_afbce1
- 1,
//int enable ,//open afbce
- pafcfg->nrwr_afbc, //AFBCE_t *afbce
- op);
+ //AFBCE_t *afbce
op->wr(NR4_TOP_CTRL,
(0 << 20) | //reg_gclk_ctrl = reg_top_ctrl[31:20];
// start_y 0 end_y 239.
//Wr(DI_DIWR_CANVAS,di_diwr_mif->canvas0_addr0 |
//(di_diwr_mif->canvas0_addr1<<8));
- set_afbce_cfg_v1(
- 2,//int index ,
+ set_afbce_cfg_v1(2, 1, pafcfg->diwr_afbc, op);
+ //int index ,
//0:vdin_afbce 1:di_afbce0 2:di_afbce1
- 1,//int enable ,
+ //int enable ,
//open afbce
- pafcfg->diwr_afbc, //AFBCE_t *afbce
- op);
+ //AFBCE_t *afbce
op->wr(DI_SC2_DIWR_CTRL, (1 << 0) | // write mif en.
(0 << 1) | // bit10 mode
// pre_frm_sel = top_pre_ctrl[31:30];
//0:internal 1:pre-post link 2:viu 3:vcp(vdin)
- op->wr(MCDI_LMV_GAINTHD, (3 << 20));
+ if (DIM_IS_IC(SC2))
+ op->wr(MCDI_LMV_GAINTHD, (3 << 20));
+ else
+ op->wr(DI_BLEND_CTRL, (3 << 20));
op->wr(DI_POST_CTRL,
(1 << 0) | // di_post_en = post_ctrl[0];
is_4k = true;
//set_afbcd_mult_simple_v1(3,in_afbcd);
//set_afbcd_mult_simple_v1(in_afbcd->index,in_afbcd);
- #if 1
+
opl2()->afbcd_set(in_afbcd->index, in_afbcd, op);
- #else
- dim_afds()->afbcd_set(cfg->afbcd_vf,
- cfg->afbcd_dec,
- cfg->afbcd_cfg);
- #endif
+
afbcd_rot = in_afbcd->rot_en;
- set_afbce_cfg_v1(
+ set_afbce_cfg_v1(2, 1, out_afbce, op);
/*index, //0:vdin_afbce 1:di_afbce0 2:di_afbce1 */
- 2,
/*enable, //open afbce */
- 1,
- out_afbce,
- op);
} else {
set_di_mif_v1(in_rdmif, in_rdmif->mif_index, op);
(0 << 20) |
/* post_frm_sel =top_post_ctrl[3];//0:viu 1:internal */
(1 << 30));
+
+ if (DIM_IS_IC_EF(T7) && (!IS_ERR_OR_NULL(in_afbcd))) {
+ if (in_afbcd->index == EAFBC_DEC_IF0) {
+ //op->bwr(AFBCDM_IF0_CTRL0,cfg->b.is_if0_4k,14,1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF0_CTRL0, 1, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+ } else if (in_afbcd->index == EAFBC_DEC_IF1) {
+ //op->bwr(AFBCDM_IF1_CTRL0,cfg->b.is_if1_4k,14,1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF1_CTRL0, 1, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+ } else if (in_afbcd->index == EAFBC_DEC_IF2) {
+ //op->bwr(AFBCDM_IF2_CTRL0,cfg->b.is_if2_4k,14,1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF2_CTRL0, 1, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+ }
+ }
+
if (is_4k)
dim_sc2_4k_set(2);
#ifdef ARY_MARK
opl2()->afbcd_set(in_afbcd->index, in_afbcd, op);
} else {
dbg_copy("inp:mif:%d\n", in_rdmif->mif_index);
- set_di_mif_v1(in_rdmif, in_rdmif->mif_index, op);
+ //set_di_mif_v1(in_rdmif, in_rdmif->mif_index, op);
+ opl1()->pre_mif_set(in_rdmif, in_rdmif->mif_index, NULL);
}
if (out_afbce) {
vsize_int = out_afbce->enc_win_end_v -
out_afbce->enc_win_bgn_v + 1;
- set_afbce_cfg_v1(
+ set_afbce_cfg_v1(2, 1, out_afbce, op);
/* index, 0:vdin_afbce 1:di_afbce0 2:di_afbce1 */
- 2,
/* enable, open afbce */
- 1,
- out_afbce,
- op);
} else {
dbg_copy("out:mif:\n");
hsize_int = out_wrmif->end_x - out_wrmif->start_x + 1;
reg = mif_reg_get_v3();
off = di_mif_add_get_offset_v3(mif_index);
- if ((off == DIM_ERR) || (!reg)) {
+ if (off == DIM_ERR || !reg) {
PR_ERR("%s:\n", __func__);
return;
}
-
+ dbg_ic("%s:id[%d]\n", __func__, mif_index);
if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
if (mif->video_mode == 0)
chro_rpt_lastl_ctrl = 1;
// ----------------------
// General register
// ----------------------
- if (mif_index == DI_MIF0_ID_INP) {
+ if (mif_index == DI_MIF0_ID_INP || mif->dbg_from_dec) {
if (mif->canvas_w % 32)
burst_len = 0;
else if (mif->canvas_w % 64)
burst_len = 1;
+
+ if (mif->block_mode) {
+ if (burst_len >= 1)
+ burst_len = 1;
+ } else {
+ if (burst_len >= 2)
+ burst_len = 2;
+ }
}
dim_print("burst_len=%d\n", burst_len);
+ if (mif->linear) {
+ op->wr(off + reg[MIF_GEN_REG3],
+ 7 << 24 |
+ mif->block_mode << 22 |
+ mif->block_mode << 20 |
+ mif->block_mode << 18 |
+ burst_len << 14 | //2 << 1 | // use bst4
+ burst_len << 12 | //2 << 1 | // use bst4
+ mif->bit_mode << 8 | // bits_mode
+ 3 << 4 | // block length
+ burst_len << 1 | //2 << 1 | // use bst4
+ mif->reg_swap << 0); //64 bit swap
+ } else {
+ op->wr(off + reg[MIF_GEN_REG3],
+ mif->bit_mode << 8 | // bits_mode
+ 3 << 4 | // block length
+ burst_len << 1 | //2 << 1 | // use bst4
+ mif->reg_swap << 0); //64 bit swap
+ }
- op->wr(off + reg[MIF_GEN_REG3],
- mif->bit_mode << 8 | // bits_mode
- 3 << 4 | // block length
- burst_len << 1 | //2 << 1 | // use bst4
- 1 << 0); //64 bit swap
if (!is_mask(SC2_REG_MSK_GEN_PRE)) {
op->wr(off + reg[MIF_GEN_REG],
(reset_bit << 29) | // reset on go field
(mif->burst_size_cb << 10) |
(mif->burst_size_y << 8) |
(chro_rpt_lastl_ctrl << 6) |
+ (mif->l_endian << 4) | /* 2020-12-29 ?*/
((mif->set_separate_en != 0) << 1) |
(1 << 0) // cntl_enable
);
if (mif->set_separate_en == 2) {
// Enable NV12 Display
op->wr(off + reg[MIF_GEN_REG2], 1);
+ if (mif->cbcr_swap)
+ op->bwr(off + reg[MIF_GEN_REG2], 2, 0, 2);
} else {
op->wr(off + reg[MIF_GEN_REG2], 0);
}
// ----------------------
// Canvas
// ----------------------
- op->wr(off + reg[MIF_CANVAS0], (mif->canvas0_addr2 << 16) |
- // cntl_canvas0_addr2
- (mif->canvas0_addr1 << 8) | // cntl_canvas0_addr1
- (mif->canvas0_addr0 << 0) // cntl_canvas0_addr0
- );
+ if (mif->linear)
+ di_mif0_linear_rd_cfg(mif, mif_index, op);
+ else
+ op->wr(off + reg[MIF_CANVAS0], (mif->canvas0_addr2 << 16) |
+ // cntl_canvas0_addr2
+ (mif->canvas0_addr1 << 8) | // cntl_canvas0_addr1
+ (mif->canvas0_addr0 << 0) // cntl_canvas0_addr0
+ );
// ----------------------
// Picture 0 X/Y start,end
// Dummy pixel value
op->wr(off + reg[MIF_DUMMY_PIXEL], 0x00808000);
- if ((mif->video_mode == 0)) {// 4:2:0 block mode.
+ if (mif->video_mode == 0) {// 4:2:0 block mode.
hfmt_en = 1;
hz_yc_ratio = 1;
hz_ini_phase = 0;
return;
}
+ if (mif->linear) {
+ di_mif0_linear_rd_cfg(mif, mif_index, op);
+ dbg_ic("%s:linar\n", __func__);
+ return;
+ }
switch (mif_index) {
case DI_MIF0_ID_IF1:
op->wr(DI_SC2_IF1_CANVAS0,
di_mif->canvas0_addr2 =
(di_buf->vframe->canvas0Addr >> 16) & 0xff;
+ if (dip_is_linear()) {//ary tmp, need add nv21
+ //dbg_ic("%s:%d:linear\n", __func__, );
+ di_mif->linear = 1;
+ //di_mif->addr0 = di_buf->nr_adr;
+ if (mif_index == DI_MIF0_ID_INP || di_mif->dbg_from_dec) {
+ dbg_ic("%s:inp not change addr\n", __func__);
+ } else {
+ di_mif->addr0 = di_buf->nr_adr;
+ di_mif->buf_crop_en = 1;
+ //di_mif->buf_hsize = 1920; //tmp
+ di_mif->buf_hsize = di_buf->buf_hsize;
+
+ di_mif->block_mode = 0;
+ dbg_ic("%s:addr:0x%lx,hsize[%d]\n", __func__,
+ di_mif->addr0,
+ di_mif->buf_hsize);
+ }
+ }
+ //dbg_ic("%s:%d:linear:%d\n", __func__, mif_index, di_mif->linear);
di_mif->nocompress = (di_buf->vframe->type & VIDTYPE_COMPRESS) ? 0 : 1;
if (di_buf->vframe->bitdepth & BITDEPTH_Y10) {
di_mif->canvas0_addr2 =
(di_buf->vframe->canvas0Addr >> 16) & 0xff;
}
+ di_mif->reg_swap = 1;
+ di_mif->l_endian = 0;
+ di_mif->cbcr_swap = 0;
} else {
if (di_buf->vframe->type & VIDTYPE_VIU_444)
di_mif->video_mode = 2;
else
di_mif->video_mode = 0;
- if (di_buf->vframe->type & VIDTYPE_VIU_NV21)
+ if (di_buf->vframe->type &
+ (VIDTYPE_VIU_NV21 | VIDTYPE_VIU_NV12))
di_mif->set_separate_en = 2;
else
di_mif->set_separate_en = 1;
op->wr(DI_SC2_PRE_GL_CTRL, 0xc0000000);
}
-void hpre_timout_read(void)
+void hpre_timeout_read(void)
{
if (!DIM_IS_IC_EF(SC2))
return;
DI_TOP_PRE_CTRL,
val);
op->wr(DI_TOP_PRE_CTRL, val);
+ if (DIM_IS_IC(T7)) {
+ op->bwr(AFBCDM_INP_CTRL0, cfg->b.is_inp_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_INP_CTRL0, cfg->b.afbc_inp, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+
+ op->bwr(AFBCDM_CHAN2_CTRL0, cfg->b.is_chan2_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_CHAN2_CTRL0, cfg->b.afbc_chan2, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+
+ op->bwr(AFBCDM_MEM_CTRL0, cfg->b.is_mem_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_MEM_CTRL0, cfg->b.afbc_mem, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+ }
+ dbg_ic("%s:afbc_mem[%d]\n", __func__, cfg->b.afbc_mem);
+ //dbg_reg_mem(40);
}
/*
void dim_secure_pre_en(unsigned char ch)
{
if (get_datal()->ch_data[ch].is_tvp == 2) {
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC_EF(SC2)) {
DIM_DI_WR(DI_PRE_SEC_IN, 0x3F);//secure
- else
- tee_config_device_state(16, 1);
+ } else {
+ #ifdef CONFIG_AMLOGIC_TEE
+ tee_config_device_state(16, 1);
+ #endif
+ }
get_datal()->ch_data[ch].is_secure_pre = 2;
//dbg_mem2("%s:tvp3 pre SECURE:%d\n", __func__, ch);
} else {
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC_EF(SC2)) {
DIM_DI_WR(DI_PRE_SEC_IN, 0x0);
- else
- tee_config_device_state(16, 0);
+ } else {
+ #ifdef CONFIG_AMLOGIC_TEE
+ tee_config_device_state(16, 0);
+ #endif
+ }
get_datal()->ch_data[ch].is_secure_pre = 1;
//dbg_mem2("%s:tvp3 pre NOSECURE:%d\n", __func__, ch);
}
{
if (DIM_IS_IC_BF(G12A))
return;
- dbg_mem2("%s:tvp3 pre:%d\n", __func__, ch);
+ //dbg_mem2("%s:tvp3 pre:%d\n", __func__, ch);
if (get_datal()->ch_data[ch].is_secure_pre == 0)//first set
dim_secure_pre_en(ch);
void dim_secure_pst_en(unsigned char ch)
{
if (get_datal()->ch_data[ch].is_tvp == 2) {
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC_EF(SC2)) {
DIM_DI_WR(DI_POST_SEC_IN, 0x1F);//secure
- else
- tee_config_device_state(17, 1);
+ } else {
+ #ifdef CONFIG_AMLOGIC_TEE
+ tee_config_device_state(17, 1);
+ #endif
+ }
get_datal()->ch_data[ch].is_secure_pst = 2;
//dbg_mem2("%s:tvp4 PST SECURE:%d\n", __func__, ch);
} else {
- if (DIM_IS_IC_EF(SC2))
+ if (DIM_IS_IC_EF(SC2)) {
DIM_DI_WR(DI_POST_SEC_IN, 0x0);
- else
- tee_config_device_state(17, 0);
+ } else {
+ #ifdef CONFIG_AMLOGIC_TEE
+ tee_config_device_state(17, 0);
+ #endif
+ }
get_datal()->ch_data[ch].is_secure_pst = 1;
//dbg_mem2("%s:tvp4 pST NOSECURE:%d\n", __func__, ch);
}
{
if (DIM_IS_IC_BF(G12A))
return;
- dbg_mem2("%s:tvp4 post:%d\n", __func__, ch);
+ //dbg_mem2("%s:tvp4 post:%d\n", __func__, ch);
if (get_datal()->ch_data[ch].is_secure_pst == 0)//first set
dim_secure_pst_en(ch);
"DI_TOP_POST_CTRL",
DI_TOP_POST_CTRL,
val);
+ if (DIM_IS_IC(T7)) {
+ op->bwr(AFBCDM_IF0_CTRL0, cfg->b.is_if0_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF0_CTRL0, cfg->b.afbc_if0, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+
+ op->bwr(AFBCDM_IF1_CTRL0, cfg->b.is_if1_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF1_CTRL0, cfg->b.afbc_if1, 13, 1);
+ //reg_afbc_vd_sel //1:afbc_dec 0:nor_rdmif
+
+ op->bwr(AFBCDM_IF2_CTRL0, cfg->b.is_if2_4k, 14, 1);
+ //reg_use_4kram
+ op->bwr(AFBCDM_IF2_CTRL0, cfg->b.afbc_if2, 13, 1);
+ //reg_afbc_vd_sel
+ //1:afbc_dec 0:nor_rdmif
+ }
}
int cnt_mm_info_simple_p(struct mm_size_out_s *info)
[DI_MIF0_ID_IF0] = &mif_contr_reg[DI_MIF0_ID_IF0][0],
[DI_MIF0_ID_IF2] = &mif_contr_reg[DI_MIF0_ID_IF2][0],
},
+};
+const struct dim_hw_opsv_s dim_ops_l1_v4 = { //for t7
+ .info = {
+ .name = "l1_t7",
+ .update = "2020-12-28",
+ .main_version = 4,
+ .sub_version = 1,
+ },
+ .pre_mif_set = set_di_mif_v3,
+ .pst_mif_set = set_di_mif_v3,
+ .pst_mif_update_csv = pst_mif_update_canvasid_v3,
+ .pre_mif_sw = di_pre_data_mif_ctrl_v3,
+ .pst_mif_sw = post_mif_sw_v3,
+ .pst_mif_rst = post_mif_rst_v3,
+ .pst_mif_rev = post_mif_rev_v3,
+ .pst_dbg_contr = post_dbg_contr_v3,
+ .pst_set_flow = di_post_set_flow_v3,
+ .pst_bit_mode_cfg = post_bit_mode_cfg_v3,
+ .wr_cfg_mif = wr_mif_cfg_v3,
+ .wrmif_set = set_wrmif_simple_v3,
+ .wrmif_sw_buf = NULL,
+ .pre_ma_mif_set = set_ma_pre_mif_t7,
+ .post_mtnrd_mif_set = set_post_mtnrd_mif_t7,
+ .pre_enable_mc = pre_enable_mc_t7,
+ .wrmif_trig = NULL,
+ .wr_rst_protect = NULL,
+ .hw_init = hw_init_v3,
+ .pre_hold_block_txlx = NULL,
+ .pre_cfg_mif = config_di_mif_v3,
+ .dbg_reg_pre_mif_print = dbg_reg_pre_mif_print_v3,
+ .dbg_reg_pst_mif_print = dbg_reg_pst_mif_print_v3,
+ .dbg_reg_pre_mif_print2 = dbg_reg_pre_mif_print2_v3,
+ .dbg_reg_pst_mif_print2 = dbg_reg_pst_mif_print2_v3,
+ .dbg_reg_pre_mif_show = dbg_reg_pre_mif_v3_show,
+ .dbg_reg_pst_mif_show = dbg_reg_pst_mif_v3_show,
+ /*contrl*/
+ .pre_gl_sw = hpre_gl_sw_v3,
+ .pre_gl_thd = hpre_gl_thd_v3,
+ .pst_gl_thd = hpost_gl_thd_v3,
+ .reg_mif_tab = {
+ [DI_MIF0_ID_INP] = &mif_contr_reg[DI_MIF0_ID_INP][0],
+ [DI_MIF0_ID_CHAN2] = &mif_contr_reg[DI_MIF0_ID_CHAN2][0],
+ [DI_MIF0_ID_MEM] = &mif_contr_reg[DI_MIF0_ID_MEM][0],
+ [DI_MIF0_ID_IF1] = &mif_contr_reg[DI_MIF0_ID_IF1][0],
+ [DI_MIF0_ID_IF0] = &mif_contr_reg[DI_MIF0_ID_IF0][0],
+ [DI_MIF0_ID_IF2] = &mif_contr_reg[DI_MIF0_ID_IF2][0],
+ },
+ .reg_mif_wr_tab = {
+ [EDI_MIFSM_NR] = ®_wrmif_v3[EDI_MIFSM_NR][0],
+ [EDI_MIFSM_WR] = ®_wrmif_v3[EDI_MIFSM_WR][0],
+ },
+ .reg_mif_wr_bits_tab = ®_bits_wr[0],
.rtab_contr_bits_tab = &rtab_sc2_contr_bits_tab[0],
};
};
extern const struct dim_hw_opsv_s dim_ops_l1_v3;
+extern const struct dim_hw_opsv_s dim_ops_l1_v4;
struct hw_ops_s {
struct di_hw_ops_info_s info;
void dim_sc2_4k_set(unsigned int mode_4k);
void dim_sc2_afbce_rst(unsigned int ec_nub);
void afbce_sw(enum EAFBC_ENC enc, bool on);//tmp
+unsigned int afbce_read_used(enum EAFBC_ENC enc);//tmp
void hpre_gl_read(void);
void cvsi_cfg(struct dim_cvsi_s *pcvsi);
+++ /dev/null
-#
-# Deinterlace driver configuration
-#
-
-menu "DI_MULTI_V3 driver"
-
-config AMLOGIC_MEDIA_DEINTERLACE
- tristate "DI_MULTI_V3 driver"
- default n
- help
- Select to enable AMLOGIC DEINTERLACE driver
- process interlace source need three continueed fields,
- wave progressive source with two interlace fields from
- one progreesive fields
-endmenu
+++ /dev/null
-# # Makefile for the Post Process Manager device #
-ifeq ($(TARGET_BUILD_VARIANT),userdebug)
-ccflags-y := -D DEBUG_SUPPORT
-ccflags-y := -DDEBUG
-else
-ccflags-y := -DDEBUG
-endif
-ccflags-y += -I.
-CFLAGS_dimv3.o := -I$(src)
-obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += dimv3.o
-dimv3-objs += deinterlace.o
-dimv3-objs += deinterlace_hw.o
-#dimv3-objs += deinterlace_mtn.o
-dimv3-objs += deinterlace_dbg.o
-#dimv3-objs += nr_drv.o
-#dimv3-objs += pulldown_drv.o
-#dimv3-objs += detect3d.o
-dimv3-objs += nr_downscale.o
-dimv3-objs += di_pps.o
-dimv3-objs += di_vframe.o
-dimv3-objs += di_prc.o
-dimv3-objs += di_pre.o
-dimv3-objs += di_pres.o
-dimv3-objs += di_pre_hw.o
-dimv3-objs += di_post.o
-dimv3-objs += di_reg_tab.o
-dimv3-objs += di_dbg.o
-dimv3-objs += di_que.o
-dimv3-objs += di_sys.o
-dimv3-objs += di_task.o
-dimv3-objs += di_interface.o
-dimv3-objs += di_api.o
-#dimv3-objs += di_que_buf.o
-#dimv3-objs += film_mode_fmw/vof_soft_top.o
-#dimv3-objs += film_mode_fmw/flm_mod_xx.o
-#dimv3-objs += film_mode_fmw/film_fw1.o
-ccflags-y += -Idrivers/amlogic/media/common/rdma/
-ccflags-y += -I$(src)
\ No newline at end of file
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/semaphore.h>
-#include <linux/workqueue.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/major.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/cdev.h>
-#include <linux/proc_fs.h>
-#include <linux/list.h>
-#include <linux/of_reserved_mem.h>
-#include <linux/of_irq.h>
-#include <linux/uaccess.h>
-#include <linux/of_fdt.h>
-#include <linux/cma.h>
-#include <linux/dma-contiguous.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/amlogic/iomap.h>
-#include <linux/amlogic/media/codec_mm/codec_mm.h>
-#include <linux/amlogic/cpu_version.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-#include <linux/amlogic/media/canvas/canvas.h>
-#include <linux/amlogic/media/canvas/canvas_mgr.h>
-#include <linux/amlogic/media/frame_provider/tvin/tvin_v4l2.h>
-#include <linux/amlogic/media/vout/vinfo.h>
-#include <linux/amlogic/media/vout/vout_notify.h>
-#include <linux/amlogic/media/vpu/vpu.h>
-#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
-#include <linux/amlogic/media/rdma/rdma_mgr.h>
-#endif
-#include <linux/amlogic/media/video_sink/video.h>
-#include "register.h"
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-#include "nr_downscale.h"
-
-
-#include "di_data_l.h"
-#include "di_dbg.h"
-#include "di_pps.h"
-#include "di_pre.h"
-#include "di_pres.h"
-#include "di_prc.h"
-#include "di_task.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_api.h"
-#include "di_sys.h"
-#include "di_pre_hw.h"
-
-/*2018-07-18 add debugfs*/
-#include <linux/seq_file.h>
-#include <linux/debugfs.h>
-/*2018-07-18 -----------*/
-
-#ifdef DET3D
-#include "detect3d.h"
-#endif
-#define ENABLE_SPIN_LOCK_ALWAYS
-
-static DEFINE_SPINLOCK(di_lock2);
-
-#define di_lock_irqfiq_save(irq_flag) \
- spin_lock_irqsave(&di_lock2, irq_flag)
-
-#define di_unlock_irqfiq_restore(irq_flag) \
- spin_unlock_irqrestore(&di_lock2, irq_flag)
-
-#ifdef HIS_V3
-void dim_lock_irqfiq_save(ulong flg)
-{
- spin_lock_irqsave(&di_lock2, flg);
-}
-
-void dim_unlock_irqfiq_restore(ulong flg)
-{
- spin_unlock_irqrestore(&di_lock2, flg);
-}
-#endif
-
-#ifdef SUPPORT_MPEG_TO_VDIN
-static int mpeg2vdin_flag;
-static int mpeg2vdin_en;
-#endif
-
-static int di_reg_unreg_cnt = 40;
-static bool overturn;
-
-bool dimv3_get_overturn(void)
-{
- return overturn;
-}
-
-int dimv3_get_reg_unreg_cnt(void)
-{
- return di_reg_unreg_cnt;
-}
-
-static bool mc_mem_alloc;
-bool dimv3_get_mcmem_alloc(void)
-{
- return mc_mem_alloc;
-}
-
-//static unsigned int di_pre_rdma_enable;
-
-/**************************************
- *
- *
- *************************************/
-unsigned int div3_dbg = DBG_M_EVENT;//|DBG_M_DBG;//DBG_M_QUED|
-module_param(div3_dbg, uint, 0664);
-MODULE_PARM_DESC(div3_dbg, "debug print");
-
-/* destroy unnecessary frames before display */
-
-/*static unsigned int hold_video; change to EDI_CFGX_HOLD_VIDEO*/
-
-DEFINE_SPINLOCK(plistv3_lock);
-
-static const char version_s[] = "2019-04-25ma";
-
-/*1:enable bypass pre,ei only;
- * 2:debug force bypass pre,ei for post
- */
-static int bypass_pre;
-/**************************
- * ary:
- * invert_top_bot
- * [0]:control post
- * [1]:control pre?
- */
-static int invert_top_bot;
-
-/* add avoid vframe put/get error */
-static int di_blocking;
-/*
- * bit[2]: enable bypass all when skip
- * bit[1:0]: enable bypass post when skip
- */
-/*static int di_vscale_skip_enable;*/
-
-/* 0: not support nr10bit, 1: support nr10bit */
-/*static unsigned int nr10bit_support;*/
-
-#ifdef RUN_DI_PROCESS_IN_IRQ
-/*
- * di_process() run in irq,
- * dim_reg_process(), dim_unreg_process() run in kernel thread
- * dim_reg_process_irq(), di_unreg_process_irq() run in irq
- * di_vf_put(), di_vf_peek(), di_vf_get() run in irq
- * di_receiver_event_fun() run in task or irq
- */
-/*
- * important:
- * to set input2pre, VFRAME_EVENT_PROVIDER_VFRAME_READY of
- * vdin should be sent in irq
- */
-
-static int input2pre;
-/*false:process progress by field;
- * true: process progress by frame with 2 interlace buffer
- */
-static int input2pre_buf_miss_count;
-static int input2pre_proc_miss_count;
-static int input2pre_throw_count;
-static int input2pre_miss_policy;
-/* 0, do not force pre_de_busy to 0, use di_wr_buf after dim_irq happen;
- * 1, force pre_de_busy to 0 and call
- * dim_pre_de_done_buf_clear to clear di_wr_buf
- */
-#endif
-/*false:process progress by field;
- * bit0: process progress by frame with 2 interlace buffer
- * bit1: temp add debug for 3d process FA,1:bit0 force to 1;
- */
-/*static int use_2_interlace_buff;*/
-/* prog_proc_config,
- * bit[2:1]: when two field buffers are used,
- * 0 use vpp for blending ,
- * 1 use post_di module for blending
- * 2 debug mode, bob with top field
- * 3 debug mode, bot with bot field
- * bit[0]:
- * 0 "prog vdin" use two field buffers,
- * 1 "prog vdin" use single frame buffer
- * bit[4]:
- * 0 "prog frame from decoder/vdin" use two field buffers,
- * 1 use single frame buffer
- * bit[5]:
- * when two field buffers are used for decoder (bit[4] is 0):
- * 1,handle prog frame as two interlace frames
- * bit[6]:(bit[4] is 0,bit[5] is 0,use_2_interlace_buff is 0): 0,
- * process progress frame as field,blend by post;
- * 1, process progress frame as field,process by normal di
- */
-/*static int prog_proc_config = (1 << 5) | (1 << 1) | 1;*/
-/*
- * for source include both progressive and interlace pictures,
- * always use post_di module for blending
- */
-#define is_handle_prog_frame_as_interlace(vframe) \
- (((dimp_get(eDI_MP_prog_proc_config) & 0x30) == 0x20) && \
- (((vframe)->type & VIDTYPE_VIU_422) == 0))
-
-static int frame_count;
-static int disp_frame_count;
-int div3_get_disp_cnt(void)
-{
- return disp_frame_count;
-}
-
-int dimv3_get_invert_tb(void)
-{
- return invert_top_bot;
-}
-static unsigned long reg_unreg_timeout_cnt;
-#ifdef DET3D
-static unsigned int det3d_mode;
-static void set3d_view(enum tvin_trans_fmt trans_fmt, struct vframe_s *vf);
-#endif
-
-static void di_pq_parm_destroy(struct di_pq_parm_s *pq_ptr);
-static struct di_pq_parm_s *di_pq_parm_create(struct am_pq_parm_s *);
-
-//static unsigned int unreg_cnt;/*cnt for vframe unreg*/
-//static unsigned int reg_cnt;/*cnt for vframe reg*/
-
-static unsigned char recovery_flag;
-
-static unsigned int recovery_log_reason;
-static unsigned int recovery_log_queue_idx;
-static struct di_buf_s *recovery_log_di_buf;
-
-unsigned char dimv3_vcry_get_flg(void)
-{
- return recovery_flag;
-}
-
-void dimv3_vcry_flg_inc(void)
-{
- recovery_flag++;
-}
-
-void dimv3_vcry_set_flg(unsigned char val)
-{
- recovery_flag = val;
-}
-
-void dimv3_reg_timeout_inc(void)
-{
- reg_unreg_timeout_cnt++;
-}
-
-/********************************/
-unsigned int dimv3_vcry_get_log_reason(void)
-{
- return recovery_log_reason;
-}
-
-void dimv3_vcry_set_log_reason(unsigned int val)
-{
- recovery_log_reason = val;
-}
-
-/********************************/
-unsigned char dimv3_vcry_get_log_q_idx(void)
-{
- return recovery_log_queue_idx;
-}
-
-void dimv3_vcry_set_log_q_idx(unsigned int val)
-{
- recovery_log_queue_idx = val;
-}
-
-/********************************/
-struct di_buf_s **dimv3_vcry_get_log_di_buf(void)
-{
- return &recovery_log_di_buf;
-}
-
-void dimv3_vcry_set_log_di_buf(struct di_buf_s *di_bufp)
-{
- recovery_log_di_buf = di_bufp;
-}
-
-void dimv3_vcry_set(unsigned int reason, unsigned int idx,
- struct di_buf_s *di_bufp)
-{
- recovery_log_reason = reason;
- recovery_log_queue_idx = idx;
- recovery_log_di_buf = di_bufp;
-}
-
-static long same_field_top_count;
-static long same_field_bot_count;
-/* bit 0:
- * 0, keep 3 buffers in pre_ready_list for checking;
- * 1, keep 4 buffers in pre_ready_list for checking;
- */
-
-static struct queue_s *get_queue_by_idx(unsigned int channel, int idx);
-//static void dump_state(unsigned int channel);
-static void recycle_keep_buffer(unsigned int channel);
-
-#define DI_PRE_INTERVAL (HZ / 100)
-
-/*
- * progressive frame process type config:
- * 0, process by field;
- * 1, process by frame (only valid for vdin source whose
- * width/height does not change)
- */
-
-static struct di_buf_s *cur_post_ready_di_buf;
-
-/************For Write register**********************/
-
-static unsigned int num_di_stop_reg_addr = 4;
-static unsigned int di_stop_reg_addr[4] = {0};
-
-static unsigned int is_need_stop_reg(unsigned int addr)
-{
- int idx = 0;
-
- if (dimp_get(eDI_MP_di_stop_reg_flag)) {
- for (idx = 0; idx < num_di_stop_reg_addr; idx++) {
- if (addr == di_stop_reg_addr[idx]) {
- pr_dbg("stop write addr: %x\n", addr);
- return 1;
- }
- }
- }
-
- return 0;
-}
-
-void dimv3_DI_Wr(unsigned int addr, unsigned int val)
-{
- if (is_need_stop_reg(addr))
- return;
- ddbgv3_reg_save(addr, val, 0, 32);
- Wr(addr, val);
-}
-
-void dimv3_DI_Wr_reg_bits(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len)
-{
- if (is_need_stop_reg(adr))
- return;
- ddbgv3_reg_save(adr, val, start, len); /*ary add for debug*/
- Wr_reg_bits(adr, val, start, len);
-}
-
-void dimv3_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val)
-{
- if (is_need_stop_reg(addr))
- return;
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support))
- dimv3_DI_Wr(addr, val);
- else
- VSYNC_WR_MPEG_REG(addr, val);
-}
-
-unsigned int dimv3_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, unsigned int val,
- unsigned int start, unsigned int len)
-{
- if (is_need_stop_reg(addr))
- return 0;
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support))
- dimv3_DI_Wr_reg_bits(addr, val, start, len);
- else
- VSYNC_WR_MPEG_REG_BITS(addr, val, start, len);
- return 0;
-}
-
-#ifdef DI_V2
-unsigned int DI_POST_REG_RD(unsigned int addr)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (IS_ERR_OR_NULL(de_devp))
- return 0;
- if (de_devp->flags & DI_SUSPEND_FLAG) {
- PR_ERR("REG 0x%x access prohibited.\n", addr);
- return 0;
- }
- return VSYNC_RD_MPEG_REG(addr);
-}
-EXPORT_SYMBOL(DI_POST_REG_RD);
-
-int DI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (IS_ERR_OR_NULL(de_devp))
- return 0;
- if (de_devp->flags & DI_SUSPEND_FLAG) {
- PR_ERR("REG 0x%x access prohibited.\n", adr);
- return -1;
- }
- return VSYNC_WR_MPEG_REG_BITS(adr, val, start, len);
-}
-EXPORT_SYMBOL(DI_POST_WR_REG_BITS);
-#else
-unsigned int l_DIV3_POST_REG_RD(unsigned int addr)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (IS_ERR_OR_NULL(de_devp))
- return 0;
- if (de_devp->flags & DI_SUSPEND_FLAG) {
- PR_ERR("REG 0x%x access prohibited.\n", addr);
- return 0;
- }
- return VSYNC_RD_MPEG_REG(addr);
-}
-
-int l_DIV3_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (IS_ERR_OR_NULL(de_devp))
- return 0;
- if (de_devp->flags & DI_SUSPEND_FLAG) {
- PR_ERR("REG 0x%x access prohibited.\n", adr);
- return -1;
- }
- return VSYNC_WR_MPEG_REG_BITS(adr, val, start, len);
-}
-
-#endif
-/**********************************/
-
-/*****************************
- * di attr management :
- * enable
- * mode
- * reg
- ******************************/
-/*config attr*/
-
-int prev3_run_flag = DI_RUN_FLAG_RUN;
-static int dump_state_flag;
-
-const char *dimv3_get_version_s(void)
-{
- return version_s;
-}
-
-int dimv3_get_blocking(void)
-{
- return di_blocking;
-}
-
-unsigned long dimv3_get_reg_unreg_timeout_cnt(void)
-{
- return reg_unreg_timeout_cnt;
-}
-
-struct di_buf_s *dimv3_get_recovery_log_di_buf(void)
-{
- return recovery_log_di_buf;
-}
-#if 0
-struct vframe_s **dim_get_vframe_in(unsigned int ch)
-{
- return getv3_vframe_in(ch);
-}
-#endif
-int dimv3_get_dump_state_flag(void)
-{
- return dump_state_flag;
-}
-
-/*--------------------------*/
-
-ssize_t
-storev3_dbg(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- unsigned int channel = get_current_channel(); /* debug only*/
- struct di_buf_s *pbuf_local = get_buf_local(channel);
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_post_stru_s *ppost = get_post_stru(channel);
- struct di_ch_s *pch;
-
- pch = get_chdata(channel);
-
- if (strncmp(buf, "buf", 3) == 0) {
- struct di_buf_s *di_buf_tmp = 0;
-
- if (kstrtoul(buf + 3, 16, (unsigned long *)&di_buf_tmp))
- return count;
- dimv3_dump_di_buf(di_buf_tmp);
- } else if (strncmp(buf, "vframe", 6) == 0) {
- vframe_t *vf = 0;
-
- if (kstrtoul(buf + 6, 16, (unsigned long *)&vf))
- return count;
- dimv3_dump_vframe(vf);
- } else if (strncmp(buf, "pool", 4) == 0) {
- unsigned long idx = 0;
-
- if (kstrtoul(buf + 4, 10, &idx))
- return count;
- dimv3_dump_pool(get_queue_by_idx(channel, idx));
- } else if (strncmp(buf, "state", 4) == 0) {
- //dump_state(channel);
- pr_info("add new debugfs: cat /sys/kernel/debug/di/state\n");
- } else if (strncmp(buf, "prog_proc_config", 16) == 0) {
- if (buf[16] == '1')
- dimp_set(eDI_MP_prog_proc_config, 1);
- else
- dimp_set(eDI_MP_prog_proc_config, 0);
- } else if (strncmp(buf, "init_flag", 9) == 0) {
- if (buf[9] == '1')
- set_init_flag(0, true);/*init_flag = 1;*/
- else
- set_init_flag(0, false);/*init_flag = 0;*/
- } else if (strncmp(buf, "prun", 4) == 0) {
- prev3_run_flag = DI_RUN_FLAG_RUN;
- } else if (strncmp(buf, "ppause", 6) == 0) {
- prev3_run_flag = DI_RUN_FLAG_PAUSE;
- } else if (strncmp(buf, "pstep", 5) == 0) {
- prev3_run_flag = DI_RUN_FLAG_STEP;
- } else if (strncmp(buf, "dumpreg", 7) == 0) {
- pr_info("add new debugfs: cat /sys/kernel/debug/di/dumpreg\n");
- } else if (strncmp(buf, "dumpmif", 7) == 0) {
- dimv3_dump_mif_size_state(ppre, ppost);
- } else if (strncmp(buf, "recycle_buf", 11) == 0) {
- recycle_keep_buffer(channel);
- } else if (strncmp(buf, "recycle_post", 12) == 0) {
- if (div3_vf_l_peek(pch))
- div3_vf_l_put(div3_vf_l_get(pch), pch);
- } else if (strncmp(buf, "mem_map", 7) == 0) {
- dimv3_dump_buf_addr(pbuf_local, MAX_LOCAL_BUF_NUM * 2);
- } else {
- pr_info("DI no support cmd %s!!!\n", buf);
- }
-
- return count;
-}
-
-#ifdef ARY_TEMP
-static int __init di_read_canvas_reverse(char *str)
-{
- unsigned char *ptr = str;
-
- pr_dbg("%s: bootargs is %s.\n", __func__, str);
- if (strstr(ptr, "1")) {
- invert_top_bot |= 0x1;
- overturn = true;
- } else {
- invert_top_bot &= (~0x1);
- overturn = false;
- }
-
- return 0;
-}
-
-__setup("video_reverse=", di_read_canvas_reverse);
-#endif
-
-static unsigned char *di_log_buf;
-static unsigned int di_log_wr_pos;
-static unsigned int di_log_rd_pos;
-static unsigned int di_log_buf_size;
-
-static unsigned int buf_state_log_start;
-/* set to 1 by condition of "post_ready count < buf_state_log_threshold",
- * reset to 0 by set buf_state_log_threshold as 0
- */
-
-static DEFINE_SPINLOCK(di_print_lock);
-
-#define PRINT_TEMP_BUF_SIZE 128
-
-static int di_print_buf(char *buf, int len)
-{
- unsigned long flags;
- int pos;
- int di_log_rd_pos_;
-
- if (di_log_buf_size == 0)
- return 0;
-
- spin_lock_irqsave(&di_print_lock, flags);
- di_log_rd_pos_ = di_log_rd_pos;
- if (di_log_wr_pos >= di_log_rd_pos)
- di_log_rd_pos_ += di_log_buf_size;
-
- for (pos = 0; pos < len && di_log_wr_pos < (di_log_rd_pos_ - 1);
- pos++, di_log_wr_pos++) {
- if (di_log_wr_pos >= di_log_buf_size)
- di_log_buf[di_log_wr_pos - di_log_buf_size] = buf[pos];
- else
- di_log_buf[di_log_wr_pos] = buf[pos];
- }
- if (di_log_wr_pos >= di_log_buf_size)
- di_log_wr_pos -= di_log_buf_size;
- spin_unlock_irqrestore(&di_print_lock, flags);
- return pos;
-}
-
-/* static int log_seq = 0; */
-int dimv3_print(const char *fmt, ...)
-{
- va_list args;
- int avail = PRINT_TEMP_BUF_SIZE;
- char buf[PRINT_TEMP_BUF_SIZE];
- int pos, len = 0;
-
- if (dimp_get(eDI_MP_di_printk_flag) & 1) {
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_PRECISE_TIMESTAMP)
- pr_dbg("%llu ms:", curv3_to_msecs());
- va_start(args, fmt);
- vprintk(fmt, args);
- va_end(args);
- return 0;
- }
-
- if (di_log_buf_size == 0)
- return 0;
-
-/* len += snprintf(buf+len, avail-len, "%d:",log_seq++); */
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_TIMESTAMP)
- len += snprintf(buf + len, avail - len, "%u:",
- dim_get_timerms(0));
-
- va_start(args, fmt);
- len += vsnprintf(buf + len, avail - len, fmt, args);
- va_end(args);
-
- if ((avail - len) <= 0)
- buf[PRINT_TEMP_BUF_SIZE - 1] = '\0';
-
- pos = di_print_buf(buf, len);
-/* pr_dbg("dim_print:%d %d\n", di_log_wr_pos, di_log_rd_pos); */
- return pos;
-}
-
-ssize_t dimv3_read_log(char *buf)
-{
- unsigned long flags;
- ssize_t read_size = 0;
-
- if (di_log_buf_size == 0)
- return 0;
-/* pr_dbg("show_log:%d %d\n", di_log_wr_pos, di_log_rd_pos); */
- spin_lock_irqsave(&di_print_lock, flags);
- if (di_log_rd_pos < di_log_wr_pos)
- read_size = di_log_wr_pos - di_log_rd_pos;
-
- else if (di_log_rd_pos > di_log_wr_pos)
- read_size = di_log_buf_size - di_log_rd_pos;
-
- if (read_size > PAGE_SIZE)
- read_size = PAGE_SIZE;
- if (read_size > 0)
- memcpy(buf, di_log_buf + di_log_rd_pos, read_size);
-
- di_log_rd_pos += read_size;
- if (di_log_rd_pos >= di_log_buf_size)
- di_log_rd_pos = 0;
- spin_unlock_irqrestore(&di_print_lock, flags);
- return read_size;
-}
-
-ssize_t
-storev3_log(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- unsigned long flags, tmp;
-
- if (strncmp(buf, "bufsize", 7) == 0) {
- if (kstrtoul(buf + 7, 10, &tmp))
- return count;
- spin_lock_irqsave(&di_print_lock, flags);
- kfree(di_log_buf);
- di_log_buf = NULL;
- di_log_buf_size = 0;
- di_log_rd_pos = 0;
- di_log_wr_pos = 0;
- if (tmp >= 1024) {
- di_log_buf_size = 0;
- di_log_rd_pos = 0;
- di_log_wr_pos = 0;
- di_log_buf = kmalloc(tmp, GFP_KERNEL);
- if (di_log_buf)
- di_log_buf_size = tmp;
- }
- spin_unlock_irqrestore(&di_print_lock, flags);
- pr_dbg("di_store:set bufsize tmp %lu %u\n",
- tmp, di_log_buf_size);
- } else if (strncmp(buf, "printk", 6) == 0) {
- if (kstrtoul(buf + 6, 10, &tmp))
- return count;
-
- dimp_set(eDI_MP_di_printk_flag, tmp);
- } else {
- dimv3_print("%s", buf);
- }
- return 16;
-}
-
-ssize_t
-showv3_vframe_status(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret = 0;
- int get_ret = 0;
-
- struct vframe_states states;
- int ch;
- struct di_mng_s *pbm = get_bufmng();
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- if (!pbm->sub_act_flg[ch])
- continue;
- else
- ret += sprintf(buf + ret, "ch[%d]\n", ch);
-
- get_ret = vf_get_states_by_name(div3_rev_name[ch], &states);
-
- if (get_ret == 0) {
- ret += sprintf(buf + ret, "vframe_pool_size=%d\n",
- states.vf_pool_size);
- ret += sprintf(buf + ret, "vframe buf_free_num=%d\n",
- states.buf_free_num);
- ret += sprintf(buf + ret, "vframe buf_recycle_num=%d\n",
- states.buf_recycle_num);
- ret += sprintf(buf + ret, "vframe buf_avail_num=%d\n",
- states.buf_avail_num);
- } else {
- ret += sprintf(buf + ret, "vframe no states\n");
- }
- }
- return ret;
-}
-
-/***************************
- * di buffer management
- ***************************/
-
-static const char * const vframe_type_name[] = {
- "", "di_buf_in", "di_buf_loc", "di_buf_post"
-};
-
-const char *dimv3_get_vfm_type_name(unsigned int nub)
-{
- if (nub < 4)
- return vframe_type_name[nub];
-
- return "";
-}
-
-static unsigned int default_width = 1920;
-static unsigned int default_height = 1080;
-
-/***********************************************
- * test input 4k mode
- ***********************************************/
-void dimv3_tst_4k_reg_val(void)
-{
- static bool flg_4k;
-
- if (dimp_get(eDI_MP_4k_test)) {
- flg_4k = true;
- default_width = 3840;
- default_height = 2160;
- pr_info("%s:4k\n", __func__);
- return;
- }
-
- if (flg_4k) {
- default_width = 1920;
- default_height = 1080;
-
- flg_4k = false;
- pr_info("%s:disable 4k\n", __func__);
- }
-
-}
-
-/*
- * all buffers are in
- * 1) list of local_free_list,in_free_list,pre_ready_list,recycle_list
- * 2) di_pre_stru.di_inp_buf
- * 3) di_pre_stru.di_wr_buf
- * 4) cur_post_ready_di_buf
- * 5) (struct di_buf_s*)(vframe->private_data)->di_buf[]
- *
- * 6) post_free_list_head
- * 8) (struct di_buf_s*)(vframe->private_data)
- */
-
-/*move to deinterlace .h #define queue_t struct queue_s*/
-
-static struct queue_s *get_queue_by_idx(unsigned int channel, int idx)
-{
- struct queue_s *pqueue = get_queue(channel);
-
- if (idx < QUEUE_NUM)
- return &pqueue[idx];
- else
- return NULL;
-}
-
-struct di_buf_s *dimv3_get_buf(unsigned int channel, int queue_idx,
- int *start_pos)
-{
- struct queue_s *pqueue = get_queue(channel);
- queue_t *q = &pqueue[queue_idx];
- int idx = 0;
- unsigned int pool_idx, di_buf_idx;
- struct di_buf_s *di_buf = NULL;
- int start_pos_init = *start_pos;
- struct di_buf_pool_s *pbuf_pool = get_buf_pool(channel);
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s:<%d:%d,%d,%d> %d\n", __func__, queue_idx,
- q->num, q->in_idx, q->out_idx, *start_pos);
-
- if (q->type == 0) {
- if ((*start_pos) < q->num) {
- idx = q->out_idx + (*start_pos);
- if (idx >= MAX_QUEUE_POOL_SIZE)
- idx -= MAX_QUEUE_POOL_SIZE;
-
- (*start_pos)++;
- } else {
- idx = MAX_QUEUE_POOL_SIZE;
- }
- } else if ((q->type == 1) || (q->type == 2)) {
- for (idx = (*start_pos); idx < MAX_QUEUE_POOL_SIZE; idx++) {
- if (q->pool[idx] != 0) {
- *start_pos = idx + 1;
- break;
- }
- }
- }
- if (idx < MAX_QUEUE_POOL_SIZE) {
- pool_idx = ((q->pool[idx] >> 8) & 0xff) - 1;
- di_buf_idx = q->pool[idx] & 0xff;
- if (pool_idx < VFRAME_TYPE_NUM) {
- if (di_buf_idx < pbuf_pool[pool_idx].size)
- di_buf =
- &(pbuf_pool[pool_idx].di_buf_ptr[
- di_buf_idx]);
- }
- }
-
- if ((di_buf) && ((((pool_idx + 1) << 8) | di_buf_idx)
- != ((di_buf->type << 8) | (di_buf->index)))) {
- PR_ERR("%s:(%x,%x)\n", __func__,
- (((pool_idx + 1) << 8) | di_buf_idx),
- ((di_buf->type << 8) | (di_buf->index)));
- if (recovery_flag == 0) {
- recovery_log_reason = 1;
- recovery_log_queue_idx =
- (start_pos_init << 8) | queue_idx;
- recovery_log_di_buf = di_buf;
- }
- recovery_flag++;
- di_buf = NULL;
- }
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE) {
- if (di_buf)
- dimv3_print("%s: %p(%d,%d)\n", __func__, di_buf,
- pool_idx, di_buf_idx);
- else
- dimv3_print("%s: %p\n", __func__, di_buf);
- }
-
- return di_buf;
-}
-
-/*--------------------------*/
-#if 0 /*move to di_sys.c*/
-u8 *dimv3_vmap(ulong addr, u32 size, bool *bflg)
-{
- u8 *vaddr = NULL;
- ulong phys = addr;
- u32 offset = phys & ~PAGE_MASK;
- u32 npages = PAGE_ALIGN(size) / PAGE_SIZE;
- struct page **pages = NULL;
- pgprot_t pgprot;
- int i;
-
- if (!PageHighMem(phys_to_page(phys)))
- return phys_to_virt(phys);
-
- if (offset)
- npages++;
-
- pages = vmalloc(sizeof(struct page *) * npages);
- if (!pages)
- return NULL;
-
- for (i = 0; i < npages; i++) {
- pages[i] = phys_to_page(phys);
- phys += PAGE_SIZE;
- }
-
- /*nocache*/
- pgprot = pgprot_writecombine(PAGE_KERNEL);
-
- vaddr = vmap(pages, npages, VM_MAP, pgprot);
- if (!vaddr) {
- PR_ERR("the phy(%lx) vmaped fail, size: %d\n",
- addr - offset, npages << PAGE_SHIFT);
- vfree(pages);
- return NULL;
- }
-
- vfree(pages);
-#if 0
- if (debug_mode & 0x20) {
- dimv3_print("[HIGH-MEM-MAP] %s, pa(%lx) to va(%p), size: %d\n",
- __func__, addr, vaddr + offset,
- npages << PAGE_SHIFT);
- }
-#endif
- *bflg = true;
-
- return vaddr + offset;
-}
-
-void dimv3_unmap_phyaddr(u8 *vaddr)
-{
- void *addr = (void *)(PAGE_MASK & (ulong)vaddr);
-
- vunmap(addr);
-}
-#endif
-
-/*--------------------------*/
-ssize_t
-storev3_dump_mem(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len)
-{
- unsigned int n = 0, canvas_w = 0, canvas_h = 0;
- unsigned long nr_size = 0, dump_adr = 0;
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *post_vf = NULL;
- char *buf_orig, *ps, *token;
- char *parm[5] = { NULL };
- char delim1[3] = " ";
- char delim2[2] = "\n";
- struct file *filp = NULL;
- loff_t pos = 0;
- void *buff = NULL;
- mm_segment_t old_fs;
- bool bflg_vmap = false;
- unsigned int channel = get_current_channel();/* debug only*/
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- /*ary add 2019-07-2 being*/
- unsigned int indx;
- struct di_buf_s *pbuf_post;
- struct di_buf_s *pbuf_local;
- struct di_post_stru_s *ppost;
- struct di_mm_s *mm;
- struct di_ch_s *pch;
- /*************************/
-
- pch = get_chdata(channel);
- buf_orig = kstrdup(buf, GFP_KERNEL);
- ps = buf_orig;
- strcat(delim1, delim2);
- while (1) {
- token = strsep(&ps, delim1);
- if (!token)
- break;
- if (*token == '\0')
- continue;
- parm[n++] = token;
- }
- if (strcmp(parm[0], "capture") == 0) {
- di_buf = ppre->di_mem_buf_dup_p;
- } else if (strcmp(parm[0], "c_post") == 0) {
- /*ary add 2019-07-2*/
- /*p2: channel*/
- /*p3: index */
- if (kstrtouint(parm[2], 0, &channel)) {
- PR_ERR("c_post:ch is not number\n");
- kfree(buf_orig);
- return 0;
- }
- if (kstrtouint(parm[3], 0, &indx)) {
- PR_ERR("c_post:ch is not number\n");
- kfree(buf_orig);
- return 0;
- }
- di_pr_info("c_post:ch[%d],index[%d]\n", channel, indx);
- mm = dim_mm_get(channel);
-
- ppre = get_pre_stru(channel);
- ppost = get_post_stru(channel);
- /*mm-0705 if (indx >= ppost->di_post_num) {*/
- if (indx >= /*mm->sts.num_post*/mm->cfg.num_post) {
- PR_ERR("c_post:index is overflow:%d[%d]\n", indx,
- mm->cfg.num_post);
- kfree(buf_orig);
- return 0;
- }
- pbuf_post = get_buf_post(channel);
- di_buf = &pbuf_post[indx];
- } else if (strcmp(parm[0], "c_local") == 0) {
- /*ary add 2019-07-2*/
- /*p2: channel*/
- /*p3: index */
- if (kstrtouint(parm[2], 0, &channel)) {
- PR_ERR("c_local:ch is not number\n");
- kfree(buf_orig);
- return 0;
- }
- if (kstrtouint(parm[3], 0, &indx)) {
- PR_ERR("c_local:ch is not number\n");
- kfree(buf_orig);
- return 0;
- }
- di_pr_info("c_local:ch[%d],index[%d]\n", channel, indx);
-
- ppre = get_pre_stru(channel);
- ppost = get_post_stru(channel);
- #if 0
- if (indx >= ppost->di_post_num) {
- PR_ERR("c_local:index is overflow:%d[%d]\n",
- indx, ppost->di_post_num);
- kfree(buf_orig);
- return 0;
- }
- #endif
- pbuf_local = get_buf_local(channel);
- di_buf = &pbuf_local[indx];
- } else if (strcmp(parm[0], "capture_pready") == 0) { /*ary add*/
-
- if (!div3_que_is_empty(channel, QUE_POST_READY)) {
- di_buf = div3_que_peek(channel, QUE_POST_READY);
- pr_info("get post ready di_buf:%d:0x%p\n",
- di_buf->index, di_buf);
- } else {
- pr_info("war:no post ready buf\n");
- }
- } else if (strcmp(parm[0], "capture_post") == 0) {
- if (div3_vf_l_peek(pch)) {
- post_vf = div3_vf_l_get(pch);
- if (!IS_ERR_OR_NULL(post_vf)) {
- di_buf = post_vf->private_data;
- div3_vf_l_put(post_vf, pch);
- pr_info("get post di_buf:%d:0x%p\n",
- di_buf->index, di_buf);
- } else {
- pr_info("war:peek no post buf, vfm[0x%p]\n",
- post_vf);
- }
-
- post_vf = NULL;
- } else {
- pr_info("war:can't peek post buf\n");
- }
- } else if (strcmp(parm[0], "capture_nrds") == 0) {
- dimv3_get_nr_ds_buf(&dump_adr, &nr_size);
- } else {
- PR_ERR("wrong dump cmd\n");
- kfree(buf_orig);
- return len;
- }
- if (nr_size == 0) {
- if (unlikely(!di_buf)) {
- pr_info("war:di_buf is null\n");
- kfree(buf_orig);
- return len;
- }
- canvas_w = di_buf->canvas_width[NR_CANVAS];
- canvas_h = di_buf->canvas_height;
- nr_size = canvas_w * canvas_h * 2;
- dump_adr = di_buf->nr_adr;
-
- pr_info("w=%d,h=%d,size=%ld,addr=%lu\n",
- canvas_w, canvas_h, nr_size, dump_adr);
- }
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- /* pr_dbg("dump path =%s\n",dump_path); */
- filp = filp_open(parm[1], O_RDWR | O_CREAT, 0666);
- if (IS_ERR(filp)) {
- PR_ERR("create %s error.\n", parm[1]);
- kfree(buf_orig);
- return len;
- }
- dump_state_flag = 1;
- if (de_devp->flags & DI_MAP_FLAG) {
- /*buff = (void *)phys_to_virt(dump_adr);*/
- buff = dimv3_vmap(dump_adr, nr_size, &bflg_vmap);
- if (!buff) {
- if (nr_size <= 5222400) {
- pr_info("di_vap err\n");
- filp_close(filp, NULL);
- kfree(buf_orig);
- return len;
-
- /*try again:*/
- #ifdef HIS_V3
- PR_INF("vap err,size to 5222400, try again\n");
- nr_size = 5222400;
- buff = dimv3_vmap(dump_adr,
- nr_size, &bflg_vmap);
- if (!buff) {
- filp_close(filp, NULL);
- kfree(buf_orig);
- return len;
- }
- #endif
- }
- }
- } else {
- buff = ioremap(dump_adr, nr_size);
- }
- if (IS_ERR_OR_NULL(buff))
- PR_ERR("%s: ioremap error.\n", __func__);
- vfs_write(filp, buff, nr_size, &pos);
-/* pr_dbg("di_chan2_buf_dup_p:\n nr:%u,mtn:%u,cnt:%u\n",
- * di_pre_stru.di_chan2_buf_dup_p->nr_adr,
- * di_pre_stru.di_chan2_buf_dup_p->mtn_adr,
- * di_pre_stru.di_chan2_buf_dup_p->cnt_adr);
- * pr_dbg("di_inp_buf:\n nr:%u,mtn:%u,cnt:%u\n",
- * di_pre_stru.di_inp_buf->nr_adr,
- * di_pre_stru.di_inp_buf->mtn_adr,
- * di_pre_stru.di_inp_buf->cnt_adr);
- * pr_dbg("di_wr_buf:\n nr:%u,mtn:%u,cnt:%u\n",
- * di_pre_stru.di_wr_buf->nr_adr,
- * di_pre_stru.di_wr_buf->mtn_adr,
- * di_pre_stru.di_wr_buf->cnt_adr);
- * pr_dbg("di_mem_buf_dup_p:\n nr:%u,mtn:%u,cnt:%u\n",
- * di_pre_stru.di_mem_buf_dup_p->nr_adr,
- * di_pre_stru.di_mem_buf_dup_p->mtn_adr,
- * di_pre_stru.di_mem_buf_dup_p->cnt_adr);
- * pr_dbg("di_mem_start=%u\n",di_mem_start);
- */
- vfs_fsync(filp, 0);
- pr_info("write buffer 0x%lx to %s.\n", dump_adr, parm[1]);
- if (bflg_vmap)
- dimv3_unmap_phyaddr(buff);
-
- if (!(de_devp->flags & DI_MAP_FLAG))
- iounmap(buff);
- dump_state_flag = 0;
- filp_close(filp, NULL);
- set_fs(old_fs);
- kfree(buf_orig);
- return len;
-}
-
-#ifdef HIS_V3
-/*ary add 2019-12-16*/
-void dbg_dump_pic(void)
-{
- unsigned int n = 0, canvas_w = 0, canvas_h = 0;
- unsigned long nr_size = 0, dump_adr = 0;
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *post_vf = NULL;
- char *buf_orig, *ps, *token;
- char *parm[5] = { NULL };
- char delim1[3] = " ";
- char delim2[2] = "\n";
- struct file *filp = NULL;
- loff_t pos = 0;
- void *buff = NULL;
- mm_segment_t old_fs;
- bool bflg_vmap = false;
- unsigned int channel = get_current_channel();/* debug only*/
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- /*ary add 2019-07-2 being*/
- unsigned int indx;
- struct di_buf_s *pbuf_post;
- struct di_buf_s *pbuf_local;
- struct di_post_stru_s *ppost;
- struct di_mm_s *mm;
- struct di_ch_s *pch;
-
- if (nr_size == 0) {
- if (unlikely(!di_buf)) {
- pr_info("war:di_buf is null\n");
- kfree(buf_orig);
- return len;
- }
- canvas_w = di_buf->canvas_width[NR_CANVAS];
- canvas_h = di_buf->canvas_height;
- nr_size = canvas_w * canvas_h * 2;
- dump_adr = di_buf->nr_adr;
-
- pr_info("w=%d,h=%d,size=%ld,addr=%lu\n",
- canvas_w, canvas_h, nr_size, dump_adr);
- }
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- /* pr_dbg("dump path =%s\n",dump_path); */
- filp = filp_open(parm[1], O_RDWR | O_CREAT, 0666);
- if (IS_ERR(filp)) {
- PR_ERR("create %s error.\n", parm[1]);
- kfree(buf_orig);
- return len;
- }
- dump_state_flag = 1;
- if (de_devp->flags & DI_MAP_FLAG) {
- /*buff = (void *)phys_to_virt(dump_adr);*/
- buff = dimv3_vmap(dump_adr, nr_size, &bflg_vmap);
- if (!buff) {
- if (nr_size <= 5222400) {
- pr_info("di_vap err\n");
- filp_close(filp, NULL);
- kfree(buf_orig);
- return len;
-
- /*try again:*/
- PR_INF("vap err,size to 5222400, try again\n");
- nr_size = 5222400;
- buff = dimv3_vmap(dump_adr,
- nr_size, &bflg_vmap);
- if (!buff) {
- filp_close(filp, NULL);
- kfree(buf_orig);
- return len;
- }
- }
- }
- } else {
- buff = ioremap(dump_adr, nr_size);
- }
- if (IS_ERR_OR_NULL(buff))
- PR_ERR("%s: ioremap error.\n", __func__);
- vfs_write(filp, buff, nr_size, &pos);
- vfs_fsync(filp, 0);
- pr_info("write buffer 0x%lx to %s.\n", dump_adr, parm[1]);
- if (bflg_vmap)
- dimv3_unmap_phyaddr(buff);
-
- if (!(de_devp->flags & DI_MAP_FLAG))
- iounmap(buff);
- dump_state_flag = 0;
- filp_close(filp, NULL);
- set_fs(old_fs);
- kfree(buf_orig);
- return len;
-}
-#endif
-
-static void recycle_vframe_type_pre(struct di_buf_s *di_buf,
- unsigned int channel);
-static void recycle_vframe_type_post(struct di_buf_s *di_buf,
- unsigned int channel);
-//static void add_dummy_vframe_type_pre(struct di_buf_s *src_buf,
-// unsigned int channel);
-#ifdef DI_BUFFER_DEBUG
-static void
-recycle_vframe_type_post_print(struct di_buf_s *di_buf,
- const char *func,
- const int line);
-#endif
-
-static void dis2_di(void)
-{
- ulong flags = 0, irq_flag2 = 0;
- unsigned int channel = get_current_channel();/* debug only*/
- void **pvframe_in = getv3_vframe_in(channel);
- void *pitf;
-
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_ch_s *pch;
- struct dim_itf_ops_s *pvfmops;
-
- pch = get_chdata(channel);
- pvfmops = &pch->interf.opsi;
-
- set_init_flag(channel, false);/*init_flag = 0;*/
- di_lock_irqfiq_save(irq_flag2);
-/* vf_unreg_provider(&di_vf_prov); */
- pwv3_vf_light_unreg_provider(channel);
- di_unlock_irqfiq_restore(irq_flag2);
- set_reg_flag(channel, false);
- spin_lock_irqsave(&plistv3_lock, flags);
- di_lock_irqfiq_save(irq_flag2);
- if (ppre->di_inp_buf) {
- pitf = pvframe_in[ppre->di_inp_buf->index];
- if (pitf) {
- //pw_vf_put(pvframe_in[ppre->di_inp_buf->index],
- // channel);
-
- //pw_vf_notify_provider(channel,
- // VFRAME_EVENT_RECEIVER_PUT, NULL);
- pvfmops->put(pitf, pch);
- pitf = NULL;
- }
- ppre->di_inp_buf->c.invert_top_bot_flag = 0;
-
- div3_que_in(channel, QUE_IN_FREE, ppre->di_inp_buf);
- ppre->di_inp_buf = NULL;
- }
- dimv3_uninit_buf(0, channel);
- if (get_blackout_policy()) {
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x2);
- if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {
- dimhv3_enable_di_post_mif(GATE_OFF);
- dimv3_post_gate_control(false);
- dimv3_top_gate_control(false, false);
- }
- }
-
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support))
- dimv3_set_power_control(0);
-
- di_unlock_irqfiq_restore(irq_flag2);
- spin_unlock_irqrestore(&plistv3_lock, flags);
-}
-
-ssize_t
-storev3_config(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- /*int rc = 0;*/
- char *parm[2] = { NULL }, *buf_orig;
- unsigned int channel = get_current_channel();/* debug only*/
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- buf_orig = kstrdup(buf, GFP_KERNEL);
- dimv3_parse_cmd_params(buf_orig, (char **)(&parm));
-
- if (strncmp(buf, "disable", 7) == 0) {
- dimv3_print("%s: disable\n", __func__);
-
- if (get_init_flag(channel)) {/*if (init_flag) {*/
- ppre->disable_req_flag = 1;
-
- while (ppre->disable_req_flag)
- usleep_range(1000, 1001);
- }
- } else if (strncmp(buf, "dis2", 4) == 0) {
- dis2_di();
- }
- kfree(buf_orig);
- return count;
-}
-#if 0
-
-static unsigned char is_progressive(vframe_t *vframe)
-{
- unsigned char ret = 0;
-
- ret = ((vframe->type & VIDTYPE_TYPEMASK) == VIDTYPE_PROGRESSIVE);
- return ret;
-}
-
-static unsigned char is_source_change(vframe_t *vframe, unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
-#define VFRAME_FORMAT_MASK \
- (VIDTYPE_VIU_422 | VIDTYPE_VIU_SINGLE_PLANE | VIDTYPE_VIU_444 | \
- VIDTYPE_MVC)
- if ((ppre->cur_width != vframe->width) ||
- (ppre->cur_height != vframe->height) ||
- (((ppre->cur_inp_type & VFRAME_FORMAT_MASK) !=
- (vframe->type & VFRAME_FORMAT_MASK)) &&
- (!is_handle_prog_frame_as_interlace(vframe))) ||
- (ppre->cur_source_type != vframe->source_type)) {
- /* video format changed */
- return 1;
- } else if (((ppre->cur_prog_flag != is_progressive(vframe)) &&
- (!is_handle_prog_frame_as_interlace(vframe))) ||
- ((ppre->cur_inp_type & VIDTYPE_VIU_FIELD) !=
- (vframe->type & VIDTYPE_VIU_FIELD))
- ) {
- /* just scan mode changed */
- if (!ppre->force_interlace)
- pr_dbg("DI I<->P.\n");
- return 2;
- }
- return 0;
-}
-#endif
-/*
- * static unsigned char is_vframe_type_change(vframe_t* vframe)
- * {
- * if(
- * (di_pre_stru.cur_prog_flag!=is_progressive(vframe))||
- * ((di_pre_stru.cur_inp_type&VFRAME_FORMAT_MASK)!=
- * (vframe->type&VFRAME_FORMAT_MASK))
- * )
- * return 1;
- *
- * return 0;
- * }
- */
-/*static int trick_mode; move to wmode*/
-#if 0
-unsigned char dim_is_bypass(struct vframe_s *vf_in, unsigned int channel)
-{
- unsigned int vtype = 0;
- int ret = 0;
- static vframe_t vf_tmp;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (dimp_get(eDI_MP_di_debug_flag) & 0x10000) /* for debugging */ {
- if (cfgg(DBG) & DI_BIT1)
- PR_INF("%s:dbg flg\n", __func__);
- return (dimp_get(eDI_MP_di_debug_flag) >> 17) & 0x1;
- }
-
- if (div3_cfgx_get(channel, eDI_CFGX_BYPASS_ALL)) {
- if (cfgg(DBG) & DI_BIT1)
- PR_INF("%s:flg\n", __func__);
- return 1;
- }
- #if 0
- if (ppre->cur_prog_flag &&
- ((ppre->cur_width > 1920) ||
- (ppre->cur_height > 1080) ||
- (ppre->cur_inp_type & VIDTYPE_VIU_444))
- )
- return 1;
- #else
- if (ppre->cur_prog_flag) {
- if (ppre->cur_inp_type & VIDTYPE_VIU_444) {
- if (cfgg(DBG) & DI_BIT1)
- PR_INF("%s:3\n", __func__);
- return 1;
- }
- if (!dimp_get(eDI_MP_4k_test) &&
- (ppre->cur_width > 1920 ||
- ppre->cur_height > 1080)) {
- if (cfgg(DBG) & DI_BIT1)
- PR_INF("%s:4\n", __func__);
- return 1;
- }
- }
- #endif
- if ((ppre->cur_width < 16) || (ppre->cur_height < 16))
- return 1;
-
- if (ppre->cur_inp_type & VIDTYPE_MVC)
- return 1;
-
- if (ppre->cur_source_type == VFRAME_SOURCE_TYPE_PPMGR)
- return 1;
-
- #if 0
- if (dimp_get(eDI_MP_bypass_trick_mode)) {
- int trick_mode_fffb = 0;
- int trick_mode_i = 0;
-
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x1)
- query_video_status(0, &trick_mode_fffb);
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x2)
- query_video_status(1, &trick_mode_i);
- trick_mode = trick_mode_fffb | (trick_mode_i << 1);
- if (trick_mode)
- return 1;
- }
- #else
- if (dimv3_get_trick_mode())
- return 1;
-
- #endif
- if (dimp_get(eDI_MP_bypass_3d) &&
- (ppre->source_trans_fmt != 0))
- return 1;
-
-/*prot is conflict with di post*/
- if (vf_in && vf_in->video_angle)
- return 1;
- if (vf_in && (vf_in->type & VIDTYPE_PIC))
- return 1;
-#if 0
- if (vf_in && (vf_in->type & VIDTYPE_COMPRESS))
- return 1;
-#endif
- if ((dimp_get(eDI_MP_di_vscale_skip_enable) & 0x4) &&
- vf_in && !dimp_get(eDI_MP_post_wr_en)) {
- /*--------------------------*/
- if (vf_in->type & VIDTYPE_COMPRESS) {
- vf_tmp.width = vf_in->compWidth;
- vf_tmp.height = vf_in->compHeight;
- if (vf_tmp.width > 1920 || vf_tmp.height > 1088)
- return 1;
- }
- /*--------------------------*/
- /*backup vtype,set type as progressive*/
- vtype = vf_in->type;
- vf_in->type &= (~VIDTYPE_TYPEMASK);
- vf_in->type &= (~VIDTYPE_VIU_NV21);
- vf_in->type |= VIDTYPE_VIU_SINGLE_PLANE;
- vf_in->type |= VIDTYPE_VIU_FIELD;
- vf_in->type |= VIDTYPE_PRE_INTERLACE;
- vf_in->type |= VIDTYPE_VIU_422;
- ret = extv3_ops.get_current_vscale_skip_count(vf_in);
- /*di_vscale_skip_count = (ret&0xff);*/
- dimp_set(eDI_MP_di_vscale_skip_count, ret & 0xff);
- /*vpp_3d_mode = ((ret>>8)&0xff);*/
- dimp_set(eDI_MP_vpp_3d_mode, ((ret >> 8) & 0xff));
- vf_in->type = vtype;
- if (dimp_get(eDI_MP_di_vscale_skip_count) > 0 ||
- (dimp_get(eDI_MP_vpp_3d_mode)
- #ifdef DET3D
- && (!dimp_get(eDI_MP_det3d_en))
- #endif
- )
- )
- return 1;
- }
-
- return 0;
-}
-#endif
-//static bool need_bypass(struct vframe_s *vf);
-
-
-static unsigned char is_bypass_post(unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (dimp_get(eDI_MP_di_debug_flag) & 0x40000) /* for debugging */
- return (dimp_get(eDI_MP_di_debug_flag) >> 19) & 0x1;
-
- /*prot is conflict with di post*/
- if (ppre->orientation)
- return 1;
- if (dimp_get(eDI_MP_bypass_post))
- return 1;
-
-#ifdef DET3D
- if (ppre->vframe_interleave_flag != 0)
- return 1;
-
-#endif
- return 0;
-}
-
-
-#ifdef DI_USE_FIXED_CANVAS_IDX
-static int di_post_idx[2][6];
-static int di_pre_idx[2][10];
-#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
-//static unsigned int di_inp_idx[3];
-#else
-static int di_wr_idx;
-#endif
-
-int dimv3_get_canvas(void)
-{
- unsigned int pre_num = 7, post_num = 6;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- struct di_hpre_s *phpre = get_hw_pre();
-
- if (dimp_get(eDI_MP_mcpre_en)) {
- /* mem/chan2/nr/mtn/contrd/contrd2/
- * contw/mcinfrd/mcinfow/mcvecw
- */
- pre_num = 10;
- /* buf0/buf1/buf2/mtnp/mcvec */
- post_num = 6;
- }
- if (extv3_ops.cvs_alloc_table("di_pre",
- &di_pre_idx[0][0],
- pre_num,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s allocate di pre canvas error.\n", __func__);
- return 1;
- }
-
- #if 0
- for (i = 0; i < pre_num; i++)
- di_pre_idx[1][i] = di_pre_idx[0][i];
- #else
- memcpy(&di_pre_idx[1][0],
- &di_pre_idx[0][0], sizeof(int) * pre_num);
- #endif
-
- if (extv3_ops.cvs_alloc_table("di_post",
- &di_post_idx[0][0],
- post_num,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s allocate di post canvas error.\n", __func__);
- return 1;
- }
-
-#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
- if (extv3_ops.cvs_alloc_table("di_post",
- &di_post_idx[1][0],
- post_num,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s allocate di post canvas error.\n", __func__);
- return 1;
- }
-#else
- for (i = 0; i < post_num; i++)
- di_post_idx[1][i] = di_post_idx[0][i];
-#endif
-#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- if (extv3_ops.cvs_alloc_table("di_inp",
- &phpre->di_inp_idx[0], 3,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s allocat di inp canvas error.\n", __func__);
- return 1;
- }
- PR_INF("support multi decoding %u~%u~%u.\n",
- phpre->di_inp_idx[0],
- phpre->di_inp_idx[1],
- phpre->di_inp_idx[2]);
-#endif
- if (de_devp->post_wr_support == 0)
- return 0;
-
-#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- if (extv3_ops.cvs_alloc_table("di_wr",
- &di_wr_idx, 1,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s allocat di write back canvas error.\n",
- __func__);
- return 1;
- }
- PR_INF("support post write back %u.\n", di_wr_idx);
-#endif
- return 0;
-}
-
-static void config_canvas_idx(struct di_buf_s *di_buf, int nr_canvas_idx,
- int mtn_canvas_idx)
-{
- unsigned int height = 0;
-
- if (!di_buf)
- return;
- if (di_buf->c.canvas_config_flag == 1) {
- if (nr_canvas_idx >= 0) {
- /* linked two interlace buffer should double height*/
- if (di_buf->c.di_wr_linked_buf)
- height = (di_buf->canvas_height << 1);
- else
- height = di_buf->canvas_height;
- di_buf->nr_canvas_idx = nr_canvas_idx;
- canvas_config(nr_canvas_idx, di_buf->nr_adr,
- di_buf->canvas_width[NR_CANVAS],
- height, 0, 0);
- }
- } else if (di_buf->c.canvas_config_flag == 2) {
- if (nr_canvas_idx >= 0) {
- di_buf->nr_canvas_idx = nr_canvas_idx;
- canvas_config(nr_canvas_idx, di_buf->nr_adr,
- di_buf->canvas_width[NR_CANVAS],
- di_buf->canvas_height, 0, 0);
- }
- if (mtn_canvas_idx >= 0) {
- di_buf->mtn_canvas_idx = mtn_canvas_idx;
- canvas_config(mtn_canvas_idx, di_buf->mtn_adr,
- di_buf->canvas_width[MTN_CANVAS],
- di_buf->canvas_height, 0, 0);
- }
- } else {
- PR_ERR("%s:do nothing\n", __func__); /*ary add*/
- }
- if (nr_canvas_idx >= 0) {
- di_buf->c.vmode.canvas0Addr = di_buf->nr_canvas_idx;
- di_buf->c.vmode.canvas1Addr = di_buf->nr_canvas_idx;
- }
-}
-
-static void config_cnt_canvas_idx(struct di_buf_s *di_buf,
- unsigned int cnt_canvas_idx)
-{
- if (!di_buf)
- return;
-
- di_buf->cnt_canvas_idx = cnt_canvas_idx;
- canvas_config(cnt_canvas_idx, di_buf->cnt_adr,
- di_buf->canvas_width[MTN_CANVAS],
- di_buf->canvas_height, 0, 0);
-}
-
-static void config_mcinfo_canvas_idx(struct di_buf_s *di_buf,
- int mcinfo_canvas_idx)
-{
- if (!di_buf)
- return;
-
- di_buf->mcinfo_canvas_idx = mcinfo_canvas_idx;
- canvas_config(mcinfo_canvas_idx,
- di_buf->mcinfo_adr,
- di_buf->canvas_height_mc, 2, 0, 0);
-}
-
-static void config_mcvec_canvas_idx(struct di_buf_s *di_buf,
- int mcvec_canvas_idx)
-{
- if (!di_buf)
- return;
-
- di_buf->mcvec_canvas_idx = mcvec_canvas_idx;
- canvas_config(mcvec_canvas_idx,
- di_buf->mcvec_adr,
- di_buf->canvas_width[MV_CANVAS],
- di_buf->canvas_height, 0, 0);
-}
-
-#else
-
-static void config_canvas(struct di_buf_s *di_buf)
-{
- unsigned int height = 0;
-
- if (!di_buf)
- return;
-
- if (di_buf->c.canvas_config_flag == 1) {
- /* linked two interlace buffer should double height*/
- if (di_buf->c.di_wr_linked_buf)
- height = (di_buf->canvas_height << 1);
- else
- height = di_buf->canvas_height;
- canvas_config(di_buf->nr_canvas_idx, di_buf->nr_adr,
- di_buf->canvas_width[NR_CANVAS], height, 0, 0);
- di_buf->c.canvas_config_flag = 0;
- } else if (di_buf->c.canvas_config_flag == 2) {
- canvas_config(di_buf->nr_canvas_idx, di_buf->nr_adr,
- di_buf->canvas_width[MV_CANVAS],
- di_buf->canvas_height, 0, 0);
- canvas_config(di_buf->mtn_canvas_idx, di_buf->mtn_adr,
- di_buf->canvas_width[MTN_CANVAS],
- di_buf->canvas_height, 0, 0);
- di_buf->c.canvas_config_flag = 0;
- }
-}
-
-#endif
-
-#if 0 /*no use*/
-/*******************************************
- *
- *
- ******************************************/
-#define DI_KEEP_BUF_SIZE 3
-static struct di_buf_s *di_keep_buf[DI_KEEP_BUF_SIZE];
-static int di_keep_point;
-
-void keep_buf_clear(void)
-{
- int i;
-
- for (i = 0; i < DI_KEEP_BUF_SIZE; i++)
- di_keep_buf[i] = NULL;
-
- di_keep_point = -1;
-}
-
-void keep_buf_in(struct di_buf_s *ready_buf)
-{
- di_keep_point++;
- if (di_keep_point >= DI_KEEP_BUF_SIZE)
- di_keep_point = 0;
- di_keep_buf[di_keep_point] = ready_buf;
-}
-
-void keep_buf_in_full(struct di_buf_s *ready_buf)
-{
- int i;
-
- keep_buf_in(ready_buf);
- for (i = 0; i < DI_KEEP_BUF_SIZE; i++) {
- if (!di_keep_buf[i])
- di_keep_buf[i] = ready_buf;
- }
-}
-#endif
-
-unsigned int dim_ins_cnt_post_size(unsigned int w, unsigned int h)
-{
-// unsigned int w, h;
- unsigned int nr_width;
- unsigned int nr_canvas_width;
- unsigned int canvas_align_width = 32;
- unsigned int post_size;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- if (dimp_get(eDI_MP_full_422_pack))
- nr_width = (w * 5) / 4;
- else
- nr_width = (w * 3) / 2;
- } else {
- nr_width = w;
- }
- nr_canvas_width = nr_width << 1;
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- nr_width = nr_canvas_width >> 1;
- PR_INF("\t:w[%d]h[%d]\n", nr_width, h);
- post_size = nr_canvas_width * h * 2;
- PR_INF("size:post:0x%x\n", post_size);
- post_size = roundup(post_size, PAGE_SIZE);
-
- return post_size;
-}
-
-int div3_cnt_buf(int width, int height, int prog_flag, int mc_mm,
- int bit10_support, int pack422)
-{
- int canvas_height = height + 8;
- unsigned int di_buf_size = 0, di_post_buf_size = 0, mtn_size = 0;
- unsigned int nr_size = 0, count_size = 0, mv_size = 0, mc_size = 0;
- unsigned int nr_width = width, mtn_width = width, mv_width = width;
- unsigned int nr_canvas_width = width, mtn_canvas_width = width;
- unsigned int mv_canvas_width = width, canvas_align_width = 32;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- if (dimp_get(eDI_MP_full_422_pack))
- nr_width = (width * 5) / 4;
- else
- nr_width = (width * 3) / 2;
- } else {
- nr_width = width;
- }
- /* make sure canvas width must be divided by 256bit|32byte align */
- nr_canvas_width = nr_width << 1;
- mtn_canvas_width = mtn_width >> 1;
- mv_canvas_width = (mv_width << 1) / 5;
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- mtn_canvas_width = roundup(mtn_canvas_width, canvas_align_width);
- mv_canvas_width = roundup(mv_canvas_width, canvas_align_width);
- nr_width = nr_canvas_width >> 1;
- mtn_width = mtn_canvas_width << 1;
- mv_width = (mv_canvas_width * 5) >> 1;
-
- if (prog_flag) {
- di_buf_size = nr_width * canvas_height * 2;
- di_buf_size = roundup(di_buf_size, PAGE_SIZE);
-
- } else {
- /*pr_info("canvas_height=%d\n", canvas_height);*/
-
- /*nr_size(bits)=w*active_h*8*2(yuv422)
- * mtn(bits)=w*active_h*4
- * cont(bits)=w*active_h*4 mv(bits)=w*active_h/5*16
- * mcinfo(bits)=active_h*16
- */
- nr_size = (nr_width * canvas_height) * 8 * 2 / 16;
- mtn_size = (mtn_width * canvas_height) * 4 / 16;
- count_size = (mtn_width * canvas_height) * 4 / 16;
- mv_size = (mv_width * canvas_height) / 5;
- /*mc_size = canvas_height;*/
- mc_size = roundup(canvas_height >> 1, canvas_align_width) << 1;
- if (mc_mm) {
- di_buf_size = nr_size + mtn_size + count_size +
- mv_size + mc_size;
- } else {
- di_buf_size = nr_size + mtn_size + count_size;
- }
- di_buf_size = roundup(di_buf_size, PAGE_SIZE);
- }
-
- PR_INF("size:0x%x\n", di_buf_size);
- PR_INF("\t%-15s:0x%x\n", "nr_size", nr_size);
- PR_INF("\t%-15s:0x%x\n", "count", count_size);
- PR_INF("\t%-15s:0x%x\n", "mtn", mtn_size);
- PR_INF("\t%-15s:0x%x\n", "mv", mv_size);
- PR_INF("\t%-15s:0x%x\n", "mcinfo", mc_size);
- PR_INF("\t%-15s:0x%x\n", "cvs_w", nr_width);
- PR_INF("\t:w[%d]h[%d]\n", nr_width, canvas_height);
- di_post_buf_size = nr_width * canvas_height * 2;
- PR_INF("size:post:0x%x\n", di_post_buf_size);
- di_post_buf_size = roundup(di_post_buf_size, PAGE_SIZE);
- PR_INF("size:post:0x%x\n", di_post_buf_size);
-
- return 0;
-}
-
-int dim_ins_cnt_post_cvs_size(struct di_buf_s *di_buf,
- struct di_buffer *ins_buf)
-{
- unsigned int w, h;
- unsigned int nr_width;
- unsigned int nr_canvas_width;
- unsigned int canvas_align_width = 32;
- unsigned int fmt = 0; /*0: 422; 1: nv21 or nv12*/
-
- w = ins_buf->vf->width;
- h = ins_buf->vf->height;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- //di_buf->vframe->type = ins_buf->vf->type;
- if (ins_buf->vf->type & VIDTYPE_VIU_NV12 ||
- ins_buf->vf->type & VIDTYPE_VIU_NV21)
- fmt = 1;
- else if (ins_buf->vf->type & VIDTYPE_VIU_422)
- fmt = 0;
- else {
- fmt = 0;
- PR_WARN("%s:vtype:0x%x\n", __func__, ins_buf->vf->type);
- }
-#ifdef DIM_OUT_NV21
- /* base on vf */
- if (!fmt) {
- /* 422*/
- if (dimp_get(eDI_MP_nr10bit_support) &&
- (ins_buf->vf->bitdepth & BITDEPTH_Y10)) {
- if ((ins_buf->vf->bitdepth & FULL_PACK_422_MODE))
- nr_width = (w * 5) / 4;
- else
- nr_width = (w * 3) / 2;
- } else {
- nr_width = w;
- }
- } else {
- nr_width = w;
- }
-#else
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- if (dimp_get(eDI_MP_full_422_pack))
- nr_width = (w * 5) / 4;
- else
- nr_width = (w * 3) / 2;
- } else {
- nr_width = w;
- }
-#endif
- if (fmt == 1) {
- /* nv 21 or nv12 */
- nr_canvas_width = nr_width;
- } else {
- /* 422 */
- nr_canvas_width = nr_width << 1;
- }
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- //nr_width = nr_canvas_width >> 1;
-
- di_buf->canvas_width[NR_CANVAS] = nr_canvas_width;
- di_buf->canvas_height = h;
-
- return 0;
-}
-
-/* size is from di_buf*/
-int dim_ins_cnt_post_cvs_size2(struct di_buf_s *di_buf,
- struct di_buffer *ins_buf,
- unsigned int ch)
-{
- unsigned int w, h;
- unsigned int nr_width;
- unsigned int nr_canvas_width;
- unsigned int canvas_align_width = 32;
- struct dim_inter_s *pintf;
- enum di_output_format fmt = 0; /*0: 422; 1: nv21 or nv12*/
- struct vframe_s *vfmout;
-
- pintf = get_dev_intf(ch);
-
- w = ins_buf->vf->width;
- h = ins_buf->vf->height;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- //di_buf->vframe->type = ins_buf->vf->type;
- fmt = pintf->u.dinst.parm.output_format;
-
-#ifdef DIM_OUT_NV21
- /* base on vf */
- if (fmt == DI_OUTPUT_422) {
- /* 422*/
- if (dimp_get(eDI_MP_nr10bit_support) &&
- (ins_buf->vf->bitdepth & BITDEPTH_Y10)) {
- if ((ins_buf->vf->bitdepth & FULL_PACK_422_MODE))
- nr_width = (w * 5) / 4;
- else
- nr_width = (w * 3) / 2;
- } else {
- nr_width = w;
- }
- } else {
- nr_width = w;
- }
-#else
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- if (dimp_get(eDI_MP_full_422_pack))
- nr_width = (w * 5) / 4;
- else
- nr_width = (w * 3) / 2;
- } else {
- nr_width = w;
- }
-#endif
- if ((fmt == DI_OUTPUT_NV12) ||
- (fmt == DI_OUTPUT_NV21)) {
- /* nv 21 or nv12 */
- nr_canvas_width = nr_width;
- } else {
- /* 422 */
- nr_canvas_width = nr_width << 1;
- }
- /* set out format */
- vfmout = ins_buf->vf;
- vfmout->type &= ~(VIDTYPE_VIU_NV12 |
- VIDTYPE_VIU_444 |
- VIDTYPE_VIU_NV21 |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_PRE_INTERLACE);
-
- vfmout->bitdepth &= ~(BITDEPTH_MASK | FULL_PACK_422_MODE);
- if (fmt == DI_OUTPUT_422) {
- vfmout->type |= VIDTYPE_VIU_422;
-
- vfmout->bitdepth |= (FULL_PACK_422_MODE |
- BITDEPTH_Y10 |
- BITDEPTH_U10 |
- BITDEPTH_V10);
- } else if (fmt == DI_OUTPUT_NV21) {
- vfmout->type |= VIDTYPE_VIU_NV21;
- vfmout->bitdepth |= (BITDEPTH_Y8 |
- BITDEPTH_U8 |
- BITDEPTH_V8);
- } else {
- vfmout->type |= VIDTYPE_VIU_NV12;
- vfmout->bitdepth |= (BITDEPTH_Y8 |
- BITDEPTH_U8 |
- BITDEPTH_V8);
- }
-
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- //nr_width = nr_canvas_width >> 1;
-#if 0
- di_buf->canvas_width[NR_CANVAS] = nr_canvas_width;
- di_buf->canvas_height = h;
-
-#endif
- return 0;
-}
-
-
-static int di_init_buf(int width, int height, unsigned char prog_flag,
- unsigned int channel)
-{
- int i;
- int canvas_height = height + 8;
- struct page *tmp_page = NULL;
- unsigned int di_buf_size = 0, di_post_buf_size = 0, mtn_size = 0;
- unsigned int nr_size = 0, count_size = 0, mv_size = 0, mc_size = 0;
- unsigned int nr_width = width, mtn_width = width, mv_width = width;
- unsigned int nr_canvas_width = width, mtn_canvas_width = width;
- unsigned int mv_canvas_width = width, canvas_align_width = 32;
- unsigned long di_post_mem = 0, nrds_mem = 0;
- void **pvframe_in = getv3_vframe_in(channel);
- struct vframe_s *pvframe_in_dup = get_vframe_in_dup(channel);
- struct vframe_s *pvframe_local = get_vframe_local(channel);
- struct vframe_s *pvframe_post = get_vframe_post(channel);
- struct di_buffer *pins = get_post_ins(channel);
- struct di_buf_s *pbuf_local = get_buf_local(channel);
- struct di_buf_s *pbuf_in = get_buf_in(channel);
- struct di_buf_s *pbuf_post = get_buf_post(channel);
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_post_stru_s *ppost = get_post_stru(channel);
- struct di_buf_s *keep_buf = ppost->keep_buf;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- /*struct di_buf_s *keep_buf_post = ppost->keep_buf_post;*/
- struct di_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
- struct dim_inter_s *pintf;
-
- unsigned int mem_st_local;
-
- /**********************************************/
- /* count buf info */
- /**********************************************/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- //PR_INF("%s:begin\n", __func__);
- frame_count = 0;
- disp_frame_count = 0;
- cur_post_ready_di_buf = NULL;
- /* decoder'buffer had been releae no need put */
- for (i = 0; i < MAX_IN_BUF_NUM; i++)
- pvframe_in[i] = NULL;
- /*pre init*/
- memset(ppre, 0, sizeof(struct di_pre_stru_s));
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- if (dimp_get(eDI_MP_full_422_pack))
- nr_width = (width * 5) / 4;
- else
- nr_width = (width * 3) / 2;
- } else {
- nr_width = width;
- }
- /* make sure canvas width must be divided by 256bit|32byte align */
- nr_canvas_width = nr_width << 1;
- mtn_canvas_width = mtn_width >> 1;
- mv_canvas_width = (mv_width << 1) / 5;
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- mtn_canvas_width = roundup(mtn_canvas_width, canvas_align_width);
- mv_canvas_width = roundup(mv_canvas_width, canvas_align_width);
- nr_width = nr_canvas_width >> 1;
- mtn_width = mtn_canvas_width << 1;
- mv_width = (mv_canvas_width * 5) >> 1;
-
- if (prog_flag) {
- ppre->prog_proc_type = 1;
- mm->cfg.buf_alloc_mode = 1;
- di_buf_size = nr_width * canvas_height * 2;
- di_buf_size = roundup(di_buf_size, PAGE_SIZE);
- } else {
- /*pr_info("canvas_height=%d\n", canvas_height);*/
- ppre->prog_proc_type = 0;
- mm->cfg.buf_alloc_mode = 0;
- /*nr_size(bits) = w * active_h * 8 * 2(yuv422)
- * mtn(bits) = w * active_h * 4
- * cont(bits) = w * active_h * 4 mv(bits) = w * active_h / 5*16
- * mcinfo(bits) = active_h * 16
- */
- nr_size = (nr_width * canvas_height) * 8 * 2 / 16;
- mtn_size = (mtn_width * canvas_height) * 4 / 16;
- count_size = (mtn_width * canvas_height) * 4 / 16;
- mv_size = (mv_width * canvas_height) / 5;
- /*mc_size = canvas_height;*/
- mc_size = roundup(canvas_height >> 1, canvas_align_width) << 1;
- if (mc_mem_alloc) {
- di_buf_size = nr_size + mtn_size + count_size +
- mv_size + mc_size;
- } else {
- di_buf_size = nr_size + mtn_size + count_size;
- }
- di_buf_size = roundup(di_buf_size, PAGE_SIZE);
- }
- /*de_devp->buffer_size = di_buf_size;*/
- mm->cfg.size_local = di_buf_size;
- #if 0
- ppre->nr_size = nr_size;
- ppre->count_size = count_size;
- ppre->mtn_size = mtn_size;
- ppre->mv_size = mv_size;
- ppre->mcinfo_size = mc_size;
- #else
- mm->cfg.nr_size = nr_size;
- mm->cfg.count_size = count_size;
- mm->cfg.mtn_size = mtn_size;
- mm->cfg.mv_size = mv_size;
- mm->cfg.mcinfo_size = mc_size;
- #endif
- dimp_set(eDI_MP_same_field_top_count, 0);
- same_field_bot_count = 0;
- dbg_init("size:\n");
- dbg_init("\t%-15s:0x%x\n", "nr_size", mm->cfg.nr_size);
- dbg_init("\t%-15s:0x%x\n", "count", mm->cfg.count_size);
- dbg_init("\t%-15s:0x%x\n", "mtn", mm->cfg.mtn_size);
- dbg_init("\t%-15s:0x%x\n", "mv", mm->cfg.mv_size);
- dbg_init("\t%-15s:0x%x\n", "mcinfo", mm->cfg.mcinfo_size);
-
- /**********************************************/
- /* que init */
- /**********************************************/
-
- queuev3_init(channel, mm->cfg.num_local);
- div3_que_init(channel); /*new que*/
-
- mem_st_local = di_get_mem_start(channel);
-
- /**********************************************/
- /* local buf init */
- /**********************************************/
-
- for (i = 0; i < mm->cfg.num_local; i++) {
- struct di_buf_s *di_buf = &pbuf_local[i];
- int ii = USED_LOCAL_BUF_MAX;
-
- if (!IS_ERR_OR_NULL(keep_buf)) {
- for (ii = 0; ii < USED_LOCAL_BUF_MAX; ii++) {
- if (di_buf == keep_buf->c.di_buf_dup_p[ii]) {
- dimv3_print("%s skip %d\n", __func__,
- i);
- break;
- }
- }
- }
-
- if (ii >= USED_LOCAL_BUF_MAX) {
- /* backup cma pages */
- tmp_page = di_buf->pages;
- /*clean di_buf*/
- memset(di_buf, 0, sizeof(struct di_buf_s));
- di_buf->pages = tmp_page;
- di_buf->type = VFRAME_TYPE_LOCAL;
- di_buf->canvas_width[NR_CANVAS] = nr_canvas_width;
- di_buf->canvas_width[MTN_CANVAS] = mtn_canvas_width;
- di_buf->canvas_width[MV_CANVAS] = mv_canvas_width;
- /* di_buf->c.sts = 0; need set*/
- if (prog_flag) {
- di_buf->canvas_height = canvas_height;
- di_buf->canvas_height_mc = canvas_height;
- di_buf->nr_adr = mem_st_local +
- di_buf_size * i;
- di_buf->c.canvas_config_flag = 1;
- } else {
- di_buf->canvas_height = (canvas_height >> 1);
- di_buf->canvas_height_mc =
- roundup(di_buf->canvas_height,
- canvas_align_width);
- di_buf->nr_adr = mem_st_local +
- di_buf_size * i;
- di_buf->mtn_adr = mem_st_local +
- di_buf_size * i +
- nr_size;
- di_buf->cnt_adr = mem_st_local +
- di_buf_size * i +
- nr_size + mtn_size;
-
- if (mc_mem_alloc) {
- di_buf->mcvec_adr = mem_st_local +
- di_buf_size * i +
- nr_size + mtn_size
- + count_size;
- di_buf->mcinfo_adr =
- mem_st_local +
- di_buf_size * i + nr_size +
- mtn_size + count_size
- + mv_size;
- if (cfgeq(mem_flg, eDI_MEM_M_rev) ||
- cfgeq(mem_flg, eDI_MEM_M_cma_all))
- dimv3_mcinfo_v_alloc(di_buf,
- mm->cfg.mcinfo_size);
- }
- di_buf->c.canvas_config_flag = 2;
- }
- di_buf->code_name = DIM_K_CODE_LOCAL;
- di_buf->channel = channel;
- di_buf->index = i;
- di_buf->queue_index = -1;
- di_buf->vframe = &pvframe_local[i];
- di_buf->vframe->private_data = di_buf;
-
- #if 0
- di_buf->c.invert_top_bot_flag = 0; /*ary:no use*/
- di_buf->c.pre_ref_count = 0; /*ary:no use*/
- di_buf->c.post_ref_count = 0; /*ary:no use*/
- #endif
- queuev3_in(channel, di_buf, QUEUE_LOCAL_FREE);
- dbg_init("buf[%d], addr=0x%lx\n", di_buf->index,
- di_buf->nr_adr);
-
- }
- }
-
- if (cfgeq(mem_flg, eDI_MEM_M_cma) ||
- cfgeq(mem_flg, eDI_MEM_M_codec_a) ||
- cfgeq(mem_flg, eDI_MEM_M_codec_b)) { /*trig cma alloc*/
- dipv3_wq_cma_run(channel, true);
- }
-
- dbg_init("one local buf size:0x%x\n", di_buf_size);
- /*mm-0705 di_post_mem = mem_st_local +*/
- /*mm-0705 di_buf_size*de_devp->buf_num_avail;*/
- di_post_mem = mem_st_local + di_buf_size * mm->cfg.num_local;
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) {
- di_post_buf_size = nr_width * canvas_height * 2;
- #if 0 /*ary test for vout 25Hz*/
- /* pre buffer must 2 more than post buffer */
- if ((de_devp->buf_num_avail - 2) > MAX_POST_BUF_NUM)
- ppost->di_post_num = MAX_POST_BUF_NUM;
- else
- ppost->di_post_num = (de_devp->buf_num_avail - 2);
- #else
- /*mm-0705 ppost->di_post_num = MAX_POST_BUF_NUM;*/
- #endif
- dbg_init("DI: di post buffer size 0x%x byte.\n",
- di_post_buf_size);
- } else {
- /*mm-0705 ppost->di_post_num = MAX_POST_BUF_NUM;*/
- di_post_buf_size = 0;
- }
- /*de_devp->post_buffer_size = di_post_buf_size;*/
- mm->cfg.size_post = di_post_buf_size;
-
- /**********************************************/
- /* input buf init */
- /**********************************************/
-
- for (i = 0; i < MAX_IN_BUF_NUM; i++) {
- struct di_buf_s *di_buf = &pbuf_in[i];
-
- if (di_buf) {
- memset(di_buf, 0, sizeof(struct di_buf_s));
- di_buf->code_name = DIM_K_CODE_DVFM;
- di_buf->channel = channel;
- di_buf->type = VFRAME_TYPE_IN;
- di_buf->index = i;
- di_buf->queue_index = -1;
- di_buf->vframe = &pvframe_in_dup[i];
- di_buf->vframe->private_data = di_buf;
-
- #if 0
- di_buf->c.invert_top_bot_flag = 0; /*ary: no use*/
- di_buf->c.pre_ref_count = 0; /*ary: no use*/
- di_buf->c.post_ref_count = 0; /*ary: no use*/
- #endif
- div3_que_in(channel, QUE_IN_FREE, di_buf);
- }
- }
- /**********************************************/
- /* post buf init */
- /**********************************************/
- pintf = get_dev_intf(channel);
- /*mm-0705 for (i = 0; i < ppost->di_post_num; i++) {*/
- for (i = 0; i < mm->cfg.num_post; i++) {
- struct di_buf_s *di_buf = &pbuf_post[i];
-
- if (di_buf) {
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) {
- if (div3_que_is_in_que(channel, QUE_POST_KEEP,
- di_buf)) {
- dbg_reg("%s:post keep buf %d\n",
- __func__,
- di_buf->index);
- continue;
- }
- }
- tmp_page = di_buf->pages;
- memset(di_buf, 0, sizeof(struct di_buf_s));
- di_buf->pages = tmp_page;
- di_buf->code_name = DIM_K_CODE_POST;
- di_buf->channel = channel;
- di_buf->type = VFRAME_TYPE_POST;
- di_buf->index = i;
- di_buf->queue_index = -1;
- di_buf->vframe = &pvframe_post[i];
- di_buf->vframe->private_data = di_buf;
-
- //ary: di_buf->c.invert_top_bot_flag = 0; //
-
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) {
- di_buf->canvas_width[NR_CANVAS] =
- (nr_width << 1);
- di_buf->canvas_height = canvas_height;
- di_buf->c.canvas_config_flag = 1;
- di_buf->nr_adr = di_post_mem
- + di_post_buf_size * i;
- dbg_init("[%d]post buf:%d: addr=0x%lx\n", i,
- di_buf->index, di_buf->nr_adr);
- /*ins*/
- if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL) {
- di_buf->ins = &pins[i];
- di_buf->ins->vf = &pvframe_post[i];
- di_buf->ins->mng.ch = channel;
- di_buf->ins->mng.index = i;
- di_buf->ins->private_data = di_buf;
- di_buf->code_name = DIM_K_CODE_INS_POST;
- }
- }
-
- div3_que_in(channel, QUE_POST_FREE, di_buf);
-
- } else {
- PR_ERR("%s:%d:post buf is null\n", __func__, i);
- }
- }
- if (cfgeq(mem_flg, eDI_MEM_M_rev) && de_devp->nrds_enable) {
- nrds_mem = di_post_mem + mm->cfg.num_post * di_post_buf_size;
- /*mm-0705 ppost->di_post_num * di_post_buf_size;*/
- dimv3_nr_ds_buf_init(cfgg(mem_flg), nrds_mem,
- &de_devp->pdev->dev);
- }
- return 0;
-}
-
-#if 0
-void dim_keep_mirror_buffer(unsigned int channel) /*not use*/
-{
- struct di_buf_s *p = NULL;
- int i = 0, ii = 0, itmp;
- struct di_post_stru_s *ppost = get_post_stru(channel);
- struct di_buf_s *pdup = NULL;
-
- queue_for_each_entry(p, channel, QUEUE_DISPLAY, list) {
- if (p->c.di_buf[0]->type != VFRAME_TYPE_IN &&
- (p->c.process_fun_index != PROCESS_FUN_NULL) &&
- (ii < USED_LOCAL_BUF_MAX) &&
- (p->index == ppost->cur_disp_index)) {
- ppost->keep_buf = p;
- for (i = 0; i < USED_LOCAL_BUF_MAX; i++) {
- pdup = p->c.di_buf_dup_p[i];
- if (IS_ERR_OR_NULL(pdup))
- continue;
- /* prepare for recycle
- * the keep buffer
- */
- pdup->c.pre_ref_count = 0;
- pdup->c.post_ref_count = 0;
- if ((pdup->queue_index >= 0) &&
- (pdup->queue_index < QUEUE_NUM)) {
- if (is_in_queue(channel,
- pdup,
- pdup->queue_index
- ))
- queuev3_out(channel, pdup);
- /*which que?*/
- }
- ii++;
- if (pdup->c.di_wr_linked_buf)
- p->c.di_buf_dup_p[i + 1] =
- pdup->c.di_wr_linked_buf;
- }
- queuev3_out(channel, p); /*which que?*/
- break;
- }
- }
-}
-#endif
-void dimv3_post_keep_mirror_buffer(unsigned int channel)
-{
- struct di_buf_s *p = NULL;
- int itmp;
- bool flg = false;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- queue_for_each_entry(p, channel, QUEUE_DISPLAY, list) {
- if (p->type != VFRAME_TYPE_POST ||
- !p->c.process_fun_index) {
- dbg_reg("%s:not post buf:%d\n",
- __func__, p->type);
- continue;
- }
-
- ppost->keep_buf_post = p; /*only keep one*/
- flg = true;
- dbg_reg("%s %d\n", __func__, p->index);
- }
-
- if (flg && ppost->keep_buf_post) {
- ppost->keep_buf_post->queue_index = -1;
- ppost->keep_buf_post->c.invert_top_bot_flag = 0;
- }
-}
-
-void dimv3_post_keep_mirror_buffer2(unsigned int ch)
-{
- struct di_buf_s *p = NULL;
- int itmp;
-
- queue_for_each_entry(p, ch, QUEUE_DISPLAY, list) {
- if (p->type != VFRAME_TYPE_POST ||
- !p->c.process_fun_index) {
- dbg_keep("%s:not post buf:%d\n", __func__, p->type);
- continue;
- }
- if (div3_que_is_in_que(ch, QUE_POST_BACK, p)) {
- dbg_keep("%s:is in back[%d]\n", __func__, p->index);
- continue;
- }
-
- p->queue_index = -1;
- div3_que_in(ch, QUE_POST_KEEP, p);
- p->c.invert_top_bot_flag = 0;
-
- dbg_keep("%s %d\n", __func__, p->index);
- }
-}
-
-bool dimv3_post_keep_is_in(unsigned int ch, struct di_buf_s *di_buf)
-{
- if (div3_que_is_in_que(ch, QUE_POST_KEEP, di_buf))
- return true;
- return false;
-}
-
-bool dimv3_post_keep_release_one(unsigned int ch, unsigned int di_buf_index)
-{
- struct di_buf_s *pbuf_post;
- struct di_buf_s *di_buf;
-
- /*must post or err*/
- pbuf_post = get_buf_post(ch);
- di_buf = &pbuf_post[di_buf_index];
-
- if (!div3_que_is_in_que(ch, QUE_POST_KEEP, di_buf)) {
- PR_ERR("%s:buf[%d] is not in keep\n", __func__, di_buf_index);
- return false;
- }
- div3_que_out_not_fifo(ch, QUE_POST_KEEP, di_buf);
- div3_que_in(ch, QUE_POST_FREE, di_buf);
- dbg_keep("%s:buf[%d]\n", __func__, di_buf_index);
- return true;
-}
-
-bool dimv3_post_keep_release_all_2free(unsigned int ch)
-{
- struct di_buf_s *di_buf;
- struct di_buf_s *pbuf_post;
- unsigned int i = 0;
-
- if (div3_que_is_empty(ch, QUE_POST_KEEP))
- return true;
-
- pbuf_post = get_buf_post(ch);
- dbg_keep("%s:ch[%d]\n", __func__, ch);
-
- while (i <= MAX_POST_BUF_NUM) {
- i++;
- di_buf = div3_que_peek(ch, QUE_POST_KEEP);
- if (!di_buf)
- break;
-
- if (!div3_que_out(ch, QUE_POST_KEEP, di_buf)) {
- PR_ERR("%s:out err\n", __func__);
- break;
- }
- memset(&di_buf->c, 0, sizeof(struct di_buf_c_s));
- div3_que_in(ch, QUE_POST_FREE, di_buf);
-
- dbg_keep("\ttype[%d],index[%d]\n", di_buf->type, di_buf->index);
- }
-
- return true;
-}
-#if 0
-void dim_post_keep_cmd_release(unsigned int ch, struct vframe_s *vframe)
-{
- struct di_buf_s *di_buf;
-
- if (!vframe)
- return;
-
- di_buf = (struct di_buf_s *)vframe->private_data;
-
- if (!di_buf) {
- PR_WARN("%s:ch[%d]:no di_buf\n", __func__, ch);
- return;
- }
-
- if (di_buf->type != VFRAME_TYPE_POST) {
- PR_WARN("%s:ch[%d]:not post\n", __func__, ch);
- return;
- }
- dbg_keep("release keep ch[%d],index[%d]\n",
- di_buf->channel,
- di_buf->index);
- taskv3_send_cmd(LCMD2(ECMD_RL_KEEP, di_buf->channel, di_buf->index));
-}
-EXPORT_SYMBOL(dim_post_keep_cmd_release);
-#endif
-
-void dimv3_post_keep_cmd_release2(struct vframe_s *vframe)
-{
- struct di_buf_s *di_buf;
- struct di_buffer *ins;
-
- if (!vframe)
- return;
-
- di_buf = (struct di_buf_s *)vframe->private_data;
-
- if (!di_buf) {
- PR_WARN("%s:no di_buf\n", __func__);
- return;
- }
-
- if (di_buf->code_name == DIM_K_CODE_INS_POST) {
- ins = vframe->private_data;
- di_buf = ins->private_data;
- if (!di_buf) {
- PR_WARN("%s:no di_buf in ins\n", __func__);
- return;
- }
- }
-
- if (di_buf->type != VFRAME_TYPE_POST) {
- PR_WARN("%s:ch[%d]:not post\n", __func__, di_buf->channel);
- return;
- }
-
- if (!div3_que_is_in_que(di_buf->channel, QUE_POST_KEEP, di_buf)) {
- PR_ERR("%s:not keep buf %d\n", __func__, di_buf->index);
- } else {
- dbg_keep("release keep ch[%d],index[%d]\n",
- di_buf->channel,
- di_buf->index);
- taskv3_send_cmd(LCMD2(ECMD_RL_KEEP, di_buf->channel,
- di_buf->index));
- }
-}
-EXPORT_SYMBOL(dimv3_post_keep_cmd_release2);
-
-void dimv3_dbg_release_keep_all(unsigned int ch)
-{
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize, itmp;
- struct di_buf_s *p;
-
- div3_que_list(ch, QUE_POST_KEEP, &tmpa[0], &psize);
- dbg_keep("post_keep: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- dbg_keep("\ttype[%d],index[%d]\n", p->type, p->index);
- dimv3_post_keep_cmd_release2(p->vframe);
- }
- dbg_keep("%s:end\n", __func__);
-}
-
-void dimv3_post_keep_back_recycle(unsigned int ch)
-{
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize, itmp;
- struct di_buf_s *p;
-
- if (div3_que_is_empty(ch, QUE_POST_KEEP_BACK))
- return;
- div3_que_list(ch, QUE_POST_KEEP_BACK, &tmpa[0], &psize);
- dbg_keep("post_keep_back: curr(%d)\n", psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- dbg_keep("keep back recycle %d\n", p->index);
- dimv3_post_keep_release_one(ch, p->index);
- }
- pwv3_queue_clear(ch, QUE_POST_KEEP_BACK);
-}
-
-void dimv3_post_keep_cmd_proc(unsigned int ch, unsigned int index)
-{
- struct di_dev_s *di_dev;
- enum EDI_TOP_STATE chst;
- unsigned int len_keep, len_back;
- struct di_buf_s *pbuf_post;
- struct di_buf_s *di_buf;
-
- /*must post or err*/
- di_dev = getv3_dim_de_devp();
-
- if (!di_dev || !di_dev->data_l) {
- PR_WARN("%s: no di_dev\n", __func__);
- return;
- }
-
- chst = dipv3_chst_get(ch);
- switch (chst) {
- case EDI_TOP_STATE_READY:
- dimv3_post_keep_release_one(ch, index);
- break;
- case EDI_TOP_STATE_IDLE:
- case eDI_TOP_STATE_BYPASS:
- pbuf_post = get_buf_post(ch);
- if (!pbuf_post) {
- PR_ERR("%s:no pbuf_post\n", __func__);
- break;
- }
-
- di_buf = &pbuf_post[index];
- di_buf->queue_index = -1;
- div3_que_in(ch, QUE_POST_KEEP_BACK, di_buf);
- len_keep = div3_que_list_count(ch, QUE_POST_KEEP);
- len_back = div3_que_list_count(ch, QUE_POST_KEEP_BACK);
- if (len_back >= len_keep) {
- /*release all*/
- pwv3_queue_clear(ch, QUE_POST_KEEP);
- pwv3_queue_clear(ch, QUE_POST_KEEP_BACK);
- dipv3_wq_cma_run(ch, false);
- }
- break;
- case eDI_TOP_STATE_REG_STEP1:
- case eDI_TOP_STATE_REG_STEP1_P1:
- case eDI_TOP_STATE_REG_STEP2:
- pbuf_post = get_buf_post(ch);
- if (!pbuf_post) {
- PR_ERR("%s:no pbuf_post\n", __func__);
- break;
- }
-
- di_buf = &pbuf_post[index];
- di_buf->queue_index = -1;
- div3_que_in(ch, QUE_POST_KEEP_BACK, di_buf);
-
- break;
- case eDI_TOP_STATE_UNREG_STEP1:
- pbuf_post = get_buf_post(ch);
- if (!pbuf_post) {
- PR_ERR("%s:no pbuf_post\n", __func__);
- break;
- }
-
- di_buf = &pbuf_post[index];
- di_buf->queue_index = -1;
- div3_que_in(ch, QUE_POST_KEEP_BACK, di_buf);
- break;
- default:
- PR_ERR("%s:do nothing? %s:%d\n",
- __func__,
- dipv3_chst_get_name(chst),
- index);
- break;
- }
-}
-
-void dimv3_uninit_buf(unsigned int disable_mirror, unsigned int channel)
-{
- /*int i = 0;*/
- void **pvframe_in = getv3_vframe_in(channel);
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_post_stru_s *ppost = get_post_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- struct dim_inter_s *pintf;
-
- pintf = get_dev_intf(channel);
-
- if (!queuev3_empty(channel, QUEUE_DISPLAY) || disable_mirror)
- ppost->keep_buf = NULL;
-#if 0
- if (disable_mirror != 1)
- dim_keep_mirror_buffer();
-
- if (!IS_ERR_OR_NULL(di_post_stru.keep_buf)) {
- keep_buf = di_post_stru.keep_buf;
- pr_dbg("%s keep cur di_buf %d (",
- __func__, keep_buf->index);
- for (i = 0; i < USED_LOCAL_BUF_MAX; i++) {
- if (!IS_ERR_OR_NULL(keep_buf->di_buf_dup_p[i]))
- pr_dbg("%d\t",
- keep_buf->di_buf_dup_p[i]->index);
- }
- pr_dbg(")\n");
- }
-#else
- if (!disable_mirror &&
- (pintf->tmode != EDIM_TMODE_2_PW_OUT))
- dimv3_post_keep_mirror_buffer2(channel);
-#endif
- queuev3_init(channel, 0);
- div3_que_init(channel); /*new que*/
-
- /* decoder'buffer had been releae no need put */
- #if 0
- for (i = 0; i < MAX_IN_BUF_NUM; i++)
- pvframe_in[i] = NULL;
- #else
- memset(pvframe_in, 0, sizeof(*pvframe_in) * MAX_IN_BUF_NUM);
- #endif
- ppre->pre_de_process_flag = 0;
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) {
- ppost->cur_post_buf = NULL;
- ppost->post_de_busy = 0;
- ppost->de_post_process_done = 0;
- ppost->post_wr_cnt = 0;
- }
- if (cfgeq(mem_flg, eDI_MEM_M_rev) && de_devp->nrds_enable) {
- dimv3_nr_ds_buf_uninit(cfgg(mem_flg),
- &de_devp->pdev->dev);
- }
-}
-
-void dimv3_log_buffer_state(unsigned char *tag, unsigned int channel)
-{
- struct di_pre_stru_s *ppre;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_BUFFER_STATE) {
- struct di_buf_s *p = NULL;/* , *ptmp; */
- int itmp;
- int in_free = 0;
- int local_free = 0;
- int pre_ready = 0;
- int post_free = 0;
- int post_ready = 0;
- int post_ready_ext = 0;
- int display = 0;
- int display_ext = 0;
- int recycle = 0;
- int di_inp = 0;
- int di_wr = 0;
- ulong irq_flag2 = 0;
-
- ppre = get_pre_stru(channel);
-
- di_lock_irqfiq_save(irq_flag2);
- in_free = div3_que_list_count(channel, QUE_IN_FREE);
- local_free = listv3_count(channel, QUEUE_LOCAL_FREE);
- pre_ready = div3_que_list_count(channel, QUE_PRE_READY);
- post_free = div3_que_list_count(channel, QUE_POST_FREE);
- post_ready = div3_que_list_count(channel, QUE_POST_READY);
-
- div3_que_list(channel, QUE_POST_READY, &tmpa[0], &psize);
- /*di_que_for_each(channel, p, psize, &tmpa[0]) {*/
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- if (p->c.di_buf[0])
- post_ready_ext++;
-
- if (p->c.di_buf[1])
- post_ready_ext++;
- }
- queue_for_each_entry(p, channel, QUEUE_DISPLAY, list) {
- display++;
- if (p->c.di_buf[0])
- display_ext++;
-
- if (p->c.di_buf[1])
- display_ext++;
- }
- recycle = listv3_count(channel, QUEUE_RECYCLE);
-
- if (ppre->di_inp_buf)
- di_inp++;
- if (ppre->di_wr_buf)
- di_wr++;
-
- if (dimp_get(eDI_MP_buf_state_log_threshold) == 0)
- buf_state_log_start = 0;
- else if (post_ready < dimp_get(eDI_MP_buf_state_log_threshold))
- buf_state_log_start = 1;
-
- if (buf_state_log_start) {
- dimv3_print(
- "[%s]i i_f %d/%d, l_f %d, pre_r %d, post_f %d/%d,",
- tag,
- in_free, MAX_IN_BUF_NUM,
- local_free,
- pre_ready,
- post_free, MAX_POST_BUF_NUM);
- dimv3_print(
- "post_r (%d:%d), disp (%d:%d),rec %d, di_i %d, di_w %d\n",
- post_ready, post_ready_ext,
- display, display_ext,
- recycle,
- di_inp, di_wr
- );
- }
- di_unlock_irqfiq_restore(irq_flag2);
- }
-}
-
-unsigned char dimv3_check_di_buf(struct di_buf_s *di_buf, int reason,
- unsigned int channel)
-{
-// int error = 0;
- //struct vframe_s *pvframe_in_dup = get_vframe_in_dup(channel);
- //struct vframe_s *pvframe_local = get_vframe_local(channel);
- //struct vframe_s *pvframe_post = get_vframe_post(channel);
-
- if (!di_buf) {
- PR_ERR("%s: %d, di_buf is NULL\n", __func__, reason);
- return 1;
- }
-
- #if 0 /*remove vframe 12-03*/
- if (di_buf->type == VFRAME_TYPE_IN) {
- if (di_buf->vframe != &pvframe_in_dup[di_buf->index])
- error = 1;
- } else if (di_buf->type == VFRAME_TYPE_LOCAL) {
- if (di_buf->vframe != &pvframe_local[di_buf->index])
- error = 1;
- } else if (di_buf->type == VFRAME_TYPE_POST) {
- if (di_buf->vframe != &pvframe_post[di_buf->index])
- error = 1;
- } else {
- error = 1;
- }
-
- if (error) {
- PR_ERR("%s: %d, di_buf wrong\n", __func__, reason);
- if (recovery_flag == 0)
- recovery_log_reason = reason;
- recovery_flag++;
- dimv3_dump_di_buf(di_buf);
- return 1;
- }
- #endif
- return 0;
-}
-
-/*
- * di pre process
- */
-static void
-config_di_mcinford_mif(struct DI_MC_MIF_s *di_mcinford_mif,
- struct di_buf_s *di_buf)
-{
- if (di_buf) {
- di_mcinford_mif->size_x = (di_buf->c.vmode.h + 2) / 4 - 1;
- di_mcinford_mif->size_y = 1;
- di_mcinford_mif->canvas_num = di_buf->mcinfo_canvas_idx;
- }
-}
-
-static void
-config_di_pre_mc_mif(struct DI_MC_MIF_s *di_mcinfo_mif,
- struct DI_MC_MIF_s *di_mcvec_mif,
- struct di_buf_s *di_buf)
-{
- unsigned int pre_size_w = 0, pre_size_h = 0;
-
- if (di_buf) {
- //pre_size_w = di_buf->vframe->width;
- //pre_size_h = (di_buf->vframe->height + 1) / 2;
- pre_size_w = di_buf->c.vmode.w;
- pre_size_h = (di_buf->c.vmode.h + 1) / 2;
- #ifdef V_DIV4
- di_mcinfo_mif->size_x = (pre_size_h + 1) / 2 - 1;
- #else
- di_mcinfo_mif->size_x = pre_size_h / 2 - 1;
- #endif
- di_mcinfo_mif->size_y = 1;
- di_mcinfo_mif->canvas_num = di_buf->mcinfo_canvas_idx;
-
- di_mcvec_mif->size_x = (pre_size_w + 4) / 5 - 1;
- di_mcvec_mif->size_y = pre_size_h - 1;
- di_mcvec_mif->canvas_num = di_buf->mcvec_canvas_idx;
- }
-}
-
-static void config_di_cnt_mif(struct DI_SIM_MIF_s *di_cnt_mif,
- struct di_buf_s *di_buf)
-{
- if (di_buf) {
- di_cnt_mif->start_x = 0;
- //di_cnt_mif->end_x = di_buf->vframe->width - 1;
- di_cnt_mif->end_x = di_buf->c.vmode.w - 1;
- di_cnt_mif->start_y = 0;
- //di_cnt_mif->end_y = di_buf->vframe->height / 2 - 1;
- di_cnt_mif->end_y = di_buf->c.vmode.h / 2 - 1;
- di_cnt_mif->canvas_num = di_buf->cnt_canvas_idx;
- }
-}
-
-static void
-config_di_wr_mif(struct DI_SIM_MIF_s *di_nrwr_mif,
- struct DI_SIM_MIF_s *di_mtnwr_mif,
- struct di_buf_s *di_buf, unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- //vframe_t *vf = di_buf->vframe;
-
- di_nrwr_mif->canvas_num = di_buf->nr_canvas_idx;
- di_nrwr_mif->start_x = 0;
- //di_nrwr_mif->end_x = vf->width - 1;
- di_nrwr_mif->end_x = di_buf->c.vmode.w - 1;
- di_nrwr_mif->start_y = 0;
- #if 0
- if (di_buf->vframe->bitdepth & BITDEPTH_Y10)
- di_nrwr_mif->bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- else
- di_nrwr_mif->bit_mode = 0;
- #else
- di_nrwr_mif->bit_mode = di_buf->c.vmode.bit_mode;
- #endif
- if (ppre->prog_proc_type == 0)
- //di_nrwr_mif->end_y = vf->height / 2 - 1;
- di_nrwr_mif->end_y = di_buf->c.vmode.h / 2 - 1;
- else
- //di_nrwr_mif->end_y = vf->height - 1;
- di_nrwr_mif->end_y = di_buf->c.vmode.h - 1;
- if (ppre->prog_proc_type == 0) {
- di_mtnwr_mif->start_x = 0;
- //di_mtnwr_mif->end_x = vf->width - 1;
- di_mtnwr_mif->end_x = di_buf->c.vmode.w - 1;
- di_mtnwr_mif->start_y = 0;
- //di_mtnwr_mif->end_y = vf->height / 2 - 1;
- di_mtnwr_mif->end_y = di_buf->c.vmode.h / 2 - 1;
- di_mtnwr_mif->canvas_num = di_buf->mtn_canvas_idx;
- }
-}
-
-#if 0
-static void config_di_mif(struct DI_MIF_s *di_mif, struct di_buf_s *di_buf,
- unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (!di_buf)
- return;
- di_mif->canvas0_addr0 =
- di_buf->vframe->canvas0Addr & 0xff;
- di_mif->canvas0_addr1 =
- (di_buf->vframe->canvas0Addr >> 8) & 0xff;
- di_mif->canvas0_addr2 =
- (di_buf->vframe->canvas0Addr >> 16) & 0xff;
-
- di_mif->nocompress = (di_buf->vframe->type & VIDTYPE_COMPRESS) ? 0 : 1;
-
- if (di_buf->vframe->bitdepth & BITDEPTH_Y10) {
- if (di_buf->vframe->type & VIDTYPE_VIU_444)
- di_mif->bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- else if (di_buf->vframe->type & VIDTYPE_VIU_422)
- di_mif->bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- } else {
- di_mif->bit_mode = 0;
- }
- if (di_buf->vframe->type & VIDTYPE_VIU_422) {
- /* from vdin or local vframe */
- if ((!is_progressive(di_buf->vframe)) ||
- (ppre->prog_proc_type)) {
- di_mif->video_mode = 0;
- di_mif->set_separate_en = 0;
- di_mif->src_field_mode = 0;
- di_mif->output_field_num = 0;
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 =
- di_buf->vframe->width - 1;
- di_mif->luma_y_start0 = 0;
- if (ppre->prog_proc_type)
- di_mif->luma_y_end0 =
- di_buf->vframe->height - 1;
- else
- di_mif->luma_y_end0 =
- di_buf->vframe->height / 2 - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 = 0;
- di_mif->chroma_y_start0 = 0;
- di_mif->chroma_y_end0 = 0;
- di_mif->canvas0_addr0 =
- di_buf->vframe->canvas0Addr & 0xff;
- di_mif->canvas0_addr1 =
- (di_buf->vframe->canvas0Addr >> 8) & 0xff;
- di_mif->canvas0_addr2 =
- (di_buf->vframe->canvas0Addr >> 16) & 0xff;
- }
- } else {
- if (di_buf->vframe->type & VIDTYPE_VIU_444)
- di_mif->video_mode = 1;
- else
- di_mif->video_mode = 0;
- if (di_buf->vframe->type & VIDTYPE_VIU_NV21)
- di_mif->set_separate_en = 2;
- else
- di_mif->set_separate_en = 1;
-
- if (is_progressive(di_buf->vframe) &&
- (ppre->prog_proc_type)) {
- di_mif->src_field_mode = 0;
- di_mif->output_field_num = 0; /* top */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 =
- di_buf->vframe->width - 1;
- di_mif->luma_y_start0 = 0;
- di_mif->luma_y_end0 =
- di_buf->vframe->height - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 =
- di_buf->vframe->width / 2 - 1;
- di_mif->chroma_y_start0 = 0;
- di_mif->chroma_y_end0 =
- di_buf->vframe->height / 2 - 1;
- } else {
- /*move to mp di_mif->src_prog = force_prog?1:0;*/
- if (ppre->cur_inp_type & VIDTYPE_INTERLACE)
- di_mif->src_prog = 0;
- else
- di_mif->src_prog
- = dimp_get(eDI_MP_force_prog) ? 1 : 0;
- di_mif->src_field_mode = 1;
- if (
- (di_buf->vframe->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP) {
- di_mif->output_field_num = 0; /* top */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 =
- di_buf->vframe->width - 1;
- di_mif->luma_y_start0 = 0;
- di_mif->luma_y_end0 =
- di_buf->vframe->height - 2;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 =
- di_buf->vframe->width / 2 - 1;
- di_mif->chroma_y_start0 = 0;
- di_mif->chroma_y_end0 =
- di_buf->vframe->height / 2
- - (di_mif->src_prog ? 1 : 2);
- } else {
- di_mif->output_field_num = 1;
- /* bottom */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 =
- di_buf->vframe->width - 1;
- di_mif->luma_y_start0 = 1;
- di_mif->luma_y_end0 =
- di_buf->vframe->height - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 =
- di_buf->vframe->width / 2 - 1;
- di_mif->chroma_y_start0 =
- (di_mif->src_prog ? 0 : 1);
- di_mif->chroma_y_end0 =
- di_buf->vframe->height / 2 - 1;
- }
- }
- }
-}
-#else
-static void config_di_mif(struct DI_MIF_s *di_mif, struct di_buf_s *di_buf,
- unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct dim_vmode_s *pvmode;
-
- if (!di_buf)
- return;
- pvmode = &di_buf->c.vmode;
-
- di_mif->canvas0_addr0 =
- pvmode->canvas0Addr & 0xff;
- di_mif->canvas0_addr1 =
- (pvmode->canvas0Addr >> 8) & 0xff;
- di_mif->canvas0_addr2 =
- (pvmode->canvas0Addr >> 16) & 0xff;
-
- di_mif->nocompress = (pvmode->vtype & DIM_VFM_COMPRESS) ? 0 : 1;
-
- #if 0
- if (di_buf->vframe->bitdepth & BITDEPTH_Y10) {
- if (di_buf->vframe->type & VIDTYPE_VIU_444)
- di_mif->bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- else if (di_buf->vframe->type & VIDTYPE_VIU_422)
- di_mif->bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- } else {
- di_mif->bit_mode = 0;
- }
- #else
- di_mif->bit_mode = pvmode->bit_mode;
- #endif
- if (pvmode->vtype & DIM_VFM_VIU_422) {
- /* from vdin or local vframe */
- if (DIM_VFMT_IS_I(pvmode->vtype) ||
- (ppre->prog_proc_type)) {
- di_mif->video_mode = 0;
- di_mif->set_separate_en = 0;
- di_mif->src_field_mode = 0;
- di_mif->output_field_num = 0;
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 = pvmode->w - 1;
- di_mif->luma_y_start0 = 0;
- if (ppre->prog_proc_type)
- di_mif->luma_y_end0 = pvmode->h - 1;
- else
- di_mif->luma_y_end0 = pvmode->h / 2 - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 = 0;
- di_mif->chroma_y_start0 = 0;
- di_mif->chroma_y_end0 = 0;
- #if 0
- di_mif->canvas0_addr0 =
- pvmode->canvas0Addr & 0xff;
- di_mif->canvas0_addr1 =
- (pvmode->canvas0Addr >> 8) & 0xff;
- di_mif->canvas0_addr2 =
- (pvmode->canvas0Addr >> 16) & 0xff;
- #endif
- }
- } else {
- if (pvmode->vtype & DIM_VFM_VIU_444)
- di_mif->video_mode = 1;
- else
- di_mif->video_mode = 0;
- if ((pvmode->vtype & DIM_VFM_VIU_NV21) ||
- (pvmode->vtype & DIM_VFM_VIU_NV12))
- di_mif->set_separate_en = 2;
- else
- di_mif->set_separate_en = 1;
-
- /* TODO: need check the linear flag more */
- if ((pvmode->vtype & DIM_VFM_VIU_NV12) &&
- (di_mif == &ppre->di_inp_mif))
- di_mif->set_separate_en = 3;
-
- if (DIM_VFMT_IS_P(pvmode->vtype) &&
- (ppre->prog_proc_type)) {
- /*ary: p as p or a use 2 i buf mode*/
- di_mif->src_field_mode = 0;
- di_mif->output_field_num = 0; /* top */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 = pvmode->w - 1;
- di_mif->luma_y_start0 = 0;
- di_mif->luma_y_end0 = pvmode->h - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 = pvmode->w / 2 - 1;
- di_mif->chroma_y_start0 = 0;
- #ifdef V_DIV4
- di_mif->chroma_y_end0 = pvmode->h / 2 - 1;
- #else
- di_mif->chroma_y_end0 = (pvmode->h + 1) / 2 - 1;
- #endif
- } else {
- /*move to mp di_mif->src_prog = force_prog?1:0;*/
- if (ppre->cur_inp_type & DIM_VFM_INTERLACE)
- di_mif->src_prog = 0;
- else
- di_mif->src_prog
- = dimp_get(eDI_MP_force_prog) ? 1 : 0;
- di_mif->src_field_mode = 1;
- if (DIM_VFMT_IS_TOP(pvmode->vtype)) {
- di_mif->output_field_num = 0; /* top */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 = pvmode->w - 1;
- di_mif->luma_y_start0 = 0;
- #ifdef V_DIV4
- di_mif->luma_y_end0 = pvmode->h - 2;
- #else
- di_mif->luma_y_end0 = pvmode->h - 1;
- #endif
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 = pvmode->w / 2 - 1;
- di_mif->chroma_y_start0 = 0;
- #ifdef V_DIV4
- di_mif->chroma_y_end0 = pvmode->h / 2
- - (di_mif->src_prog ? 1 : 2);
- #else
- di_mif->chroma_y_end0 = (pvmode->h + 1) / 2 - 1;
- #endif
- } else {
- di_mif->output_field_num = 1;
- /* bottom */
- di_mif->luma_x_start0 = 0;
- di_mif->luma_x_end0 = pvmode->w - 1;
- di_mif->luma_y_start0 = 1;
- di_mif->luma_y_end0 = pvmode->h - 1;
- di_mif->chroma_x_start0 = 0;
- di_mif->chroma_x_end0 = pvmode->w / 2 - 1;
- di_mif->chroma_y_start0 =
- (di_mif->src_prog ? 0 : 1);
- #ifdef V_DIV4
- di_mif->chroma_y_end0 = pvmode->h / 2 - 1;
- #else
- di_mif->chroma_y_end0 = (pvmode->h + 1) / 2
- - 1;
- #endif
- }
- }
- }
-}
-
-#endif
-static void di_pre_size_change(unsigned short width,
- unsigned short height,
- unsigned short vf_type,
- unsigned int channel);
-
-
-
-void dim_dbg_delay_mask_set(unsigned int position)
-{
- if (dimp_get(EDI_MP_SUB_DBG_MODE) & position)
- get_dbg_data()->delay_cnt = 0;
- else
- get_dbg_data()->delay_cnt = dimp_get(EDI_MP_SUB_DELAY);
-}
-
-void dimv3_pre_de_process(unsigned int channel)
-{
- ulong irq_flag2 = 0;
- unsigned short pre_width = 0, pre_height = 0;
- unsigned char chan2_field_num = 1;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- int canvases_idex = ppre->field_count % 2;
- unsigned short cur_inp_field_type = VIDTYPE_TYPEMASK;
- unsigned short int_mask = 0x7f;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- ppre->pre_de_process_flag = 1;
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_SETB, channel, ppre->in_seq);/*dbg*/
-
- #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- prev3_inp_canvas_config(ppre->di_inp_buf);
- #endif
-
- config_di_mif(&ppre->di_inp_mif, ppre->di_inp_buf, channel);
- /* pr_dbg("set_separate_en=%d vframe->type %d\n",
- * di_pre_stru.di_inp_mif.set_separate_en,
- * di_pre_stru.di_inp_buf->vframe->type);
- */
-#ifdef DI_USE_FIXED_CANVAS_IDX
- if (ppre->di_mem_buf_dup_p &&
- ppre->di_mem_buf_dup_p != ppre->di_inp_buf) {
- config_canvas_idx(ppre->di_mem_buf_dup_p,
- di_pre_idx[canvases_idex][0], -1);
- config_cnt_canvas_idx(ppre->di_mem_buf_dup_p,
- di_pre_idx[canvases_idex][1]);
- } else {
- config_cnt_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][1]);
- config_di_cnt_mif(&ppre->di_contp2rd_mif,
- ppre->di_wr_buf);
- }
- if (ppre->di_chan2_buf_dup_p) {
- config_canvas_idx(ppre->di_chan2_buf_dup_p,
- di_pre_idx[canvases_idex][2], -1);
- config_cnt_canvas_idx(ppre->di_chan2_buf_dup_p,
- di_pre_idx[canvases_idex][3]);
- } else {
- config_cnt_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][3]);
- }
-
- /*wr_buf*/
- config_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][4],
- di_pre_idx[canvases_idex][5]);
- config_cnt_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][6]);
-
- /*mc*/
- if (dimp_get(eDI_MP_mcpre_en)) {
- if (ppre->di_chan2_buf_dup_p)
- config_mcinfo_canvas_idx(ppre->di_chan2_buf_dup_p,
- di_pre_idx[canvases_idex][7]);
- else
- config_mcinfo_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][7]);
-
- config_mcinfo_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][8]);
- config_mcvec_canvas_idx(ppre->di_wr_buf,
- di_pre_idx[canvases_idex][9]);
- }
-#endif
- config_di_mif(&ppre->di_mem_mif, ppre->di_mem_buf_dup_p, channel);
- if (!ppre->di_chan2_buf_dup_p) {
- config_di_mif(&ppre->di_chan2_mif,
- ppre->di_inp_buf, channel);
- } else
- config_di_mif(&ppre->di_chan2_mif,
- ppre->di_chan2_buf_dup_p, channel);
- config_di_wr_mif(&ppre->di_nrwr_mif, &ppre->di_mtnwr_mif,
- ppre->di_wr_buf, channel);
-
- if (ppre->di_chan2_buf_dup_p)
- config_di_cnt_mif(&ppre->di_contprd_mif,
- ppre->di_chan2_buf_dup_p);
- else
- config_di_cnt_mif(&ppre->di_contprd_mif,
- ppre->di_wr_buf);
-
- config_di_cnt_mif(&ppre->di_contwr_mif, ppre->di_wr_buf);
- if (dimp_get(eDI_MP_mcpre_en)) {
- if (ppre->di_chan2_buf_dup_p)
- config_di_mcinford_mif(&ppre->di_mcinford_mif,
- ppre->di_chan2_buf_dup_p);
- else
- config_di_mcinford_mif(&ppre->di_mcinford_mif,
- ppre->di_wr_buf);
-
- config_di_pre_mc_mif(&ppre->di_mcinfowr_mif,
- &ppre->di_mcvecwr_mif, ppre->di_wr_buf);
- }
- #if 0
- if ((ppre->di_chan2_buf_dup_p) &&
- ((ppre->di_chan2_buf_dup_p->vframe->type & VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP))
- chan2_field_num = 0;
- #else
- if (ppre->di_chan2_buf_dup_p &&
- ppre->di_chan2_buf_dup_p->c.wmode.is_top)
- chan2_field_num = 0;
- #endif
- pre_width = ppre->di_nrwr_mif.end_x + 1;
- pre_height = ppre->di_nrwr_mif.end_y + 1;
- #if 0
- if (ppre->input_size_change_flag) {
- cur_inp_field_type =
- (ppre->di_inp_buf->vframe->type & VIDTYPE_TYPEMASK);
- cur_inp_field_type =
- ppre->cur_prog_flag ? VIDTYPE_PROGRESSIVE : cur_inp_field_type;
- /*di_async_reset2();*/
- di_pre_size_change(pre_width, pre_height,
- cur_inp_field_type, channel);
- ppre->input_size_change_flag = false;
- }
- #else
- if (ppre->input_size_change_flag) {
- cur_inp_field_type =
- ppre->di_inp_buf->c.vmode.vtype & DIM_VFM_TYPEMASK;
- /*di_async_reset2();*/
- di_pre_size_change(pre_width, pre_height,
- cur_inp_field_type, channel);
- ppre->input_size_change_flag = false;
- }
- #endif
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (de_devp->nrds_enable) {
- dimv3_nr_ds_mif_config();
- dimv3_nr_ds_hw_ctrl(true);
- int_mask = 0x3f;
- } else {
- dimv3_nr_ds_hw_ctrl(false);
- }
- }
-
- /* set interrupt mask for pre module.
- * we need to only leave one mask open
- * to prevent multiple entry for dim_irq
- */
-
- /*dim_dbg_pre_cnt(channel, "s2");*/
-
- dimhv3_enable_di_pre_aml(&ppre->di_inp_mif,
- &ppre->di_mem_mif,
- &ppre->di_chan2_mif,
- &ppre->di_nrwr_mif,
- &ppre->di_mtnwr_mif,
- &ppre->di_contp2rd_mif,
- &ppre->di_contprd_mif,
- &ppre->di_contwr_mif,
- ppre->madi_enable,
- chan2_field_num,
- ppre->vdin2nr);
-
- /*dimh_enable_afbc_input(ppre->di_inp_buf->vframe);*/
-
- if (dimp_get(eDI_MP_mcpre_en)) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimhv3_enable_mc_di_pre_g12(&ppre->di_mcinford_mif,
- &ppre->di_mcinfowr_mif,
- &ppre->di_mcvecwr_mif,
- ppre->mcdi_enable);
- else
- dimhv3_enable_mc_di_pre(&ppre->di_mcinford_mif,
- &ppre->di_mcinfowr_mif,
- &ppre->di_mcvecwr_mif,
- ppre->mcdi_enable);
- }
-
- ppre->field_count++;
- dimhv3_txl_patch_prog(ppre->cur_prog_flag,
- ppre->field_count,
- dimp_get(eDI_MP_mcpre_en));
-
-#ifdef SUPPORT_MPEG_TO_VDIN
- if (mpeg2vdin_flag) {
- struct vdin_arg_s vdin_arg;
- struct vdin_v4l2_ops_s *vdin_ops = get_vdin_v4l2_ops();
-
- vdin_arg.cmd = VDIN_CMD_FORCE_GO_FIELD;
- if (vdin_ops->tvin_vdin_func)
- vdin_ops->tvin_vdin_func(0, &vdin_arg);
- }
-#endif
- /* **************************************************
- * must make sure follow part issue without interrupts,
- * otherwise may cause watch dog reboot
- */
- di_lock_irqfiq_save(irq_flag2);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- /*2019-12-25 from feijun*/
- /*after g12a: enable mif and then reset*/
- /* enable mc pre mif*/
- dimhv3_enable_di_pre_mif(true, dimp_get(eDI_MP_mcpre_en));
- dimv3_pre_frame_reset_g12(ppre->madi_enable,
- ppre->mcdi_enable);
-
- } else {
- dimv3_pre_frame_reset();
- /* enable mc pre mif*/
- dimhv3_enable_di_pre_mif(true, dimp_get(eDI_MP_mcpre_en));
-
- }
-
- di_pre_wait_irq_set(true);
-
- di_unlock_irqfiq_restore(irq_flag2);
- /****************************************************/
- /*reinit pre busy flag*/
- ppre->pre_de_busy = 1;
-
- dimv3_dbg_pre_cnt(channel, "s3");
- ppre->irq_time[0] = curv3_to_msecs();
- ppre->irq_time[1] = curv3_to_msecs();
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_SETE, channel, ppre->in_seq);/*dbg*/
- dimv3_tr_ops.pre_set(ppre->di_wr_buf->c.vmode.omx_index);
-
- ppre->pre_de_process_flag = 0;
-}
-
-void dimv3_pre_de_done_buf_clear(unsigned int channel)
-{
- struct di_buf_s *wr_buf = NULL;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct dim_dvfm_s *pdvfm;
- struct di_ch_s *pch;
-
- if (ppre->di_wr_buf) {
- wr_buf = ppre->di_wr_buf;
- if ((ppre->prog_proc_type == 2) &&
- wr_buf->c.di_wr_linked_buf) {
- wr_buf->c.di_wr_linked_buf->c.pre_ref_count = 0;
- wr_buf->c.di_wr_linked_buf->c.post_ref_count = 0;
- queuev3_in(channel, wr_buf->c.di_wr_linked_buf,
- QUEUE_RECYCLE);
- wr_buf->c.di_wr_linked_buf = NULL;
- }
- wr_buf->c.pre_ref_count = 0;
- wr_buf->c.post_ref_count = 0;
- queuev3_in(channel, wr_buf, QUEUE_RECYCLE);
- ppre->di_wr_buf = NULL;
- }
- if (ppre->di_inp_buf) {
- if (ppre->di_mem_buf_dup_p == ppre->di_inp_buf)
- ppre->di_mem_buf_dup_p = NULL;
-
- queuev3_in(channel, ppre->di_inp_buf, QUEUE_RECYCLE);
- ppre->di_inp_buf = NULL;
- }
-
- if (ppre->dvfm) { /*ary tmp : dvfm recycle*/
- pch = get_chdata(channel);
- pdvfm = dvfmv3_get(pch, QUED_T_PRE);
- if (ppre->dvfm->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- ppre->dvfm->index,
- pdvfm->index);
- return;
- }
-
- qued_ops.in(pch, QUED_T_RECYCL, ppre->dvfm->index);
- ppre->dvfm = NULL;
- } else {
- PR_ERR("%s:no dvfm\n", __func__);
- }
-}
-
-#ifdef HIS_V3
-static void topv3_bot_config(struct di_buf_s *di_buf)
-{
- vframe_t *vframe = di_buf->vframe;
-
- if (((invert_top_bot & 0x1) != 0) && (!is_progressive(vframe))) {
- if (di_buf->invert_top_bot_flag == 0) {
- if ((vframe->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP) {
- vframe->type &= (~VIDTYPE_TYPEMASK);
- vframe->type |= VIDTYPE_INTERLACE_BOTTOM;
- } else {
- vframe->type &= (~VIDTYPE_TYPEMASK);
- vframe->type |= VIDTYPE_INTERLACE_TOP;
- }
- di_buf->invert_top_bot_flag = 1;
- }
- }
-}
-#endif
-
-#if 1 /*move to di_pres.c have di_lock_irqfiq_save can't move*/
-void dimv3_pre_de_done_buf_config(struct di_ch_s *pch,
- bool flg_timeout)
-{
- ulong irq_flag2 = 0;
- int tmp_cur_lev;
- struct di_buf_s *post_wr_buf = NULL;
- unsigned int glb_frame_mot_num = 0;
- unsigned int glb_field_mot_num = 0;
- unsigned int channel = pch->ch_id;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-// struct di_ch_s *pch;
-// struct dim_dvfm_s *pdvfm;
-
- dimv3_dbg_pre_cnt(channel, "d1");
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_DONEB,
- channel, ppre->in_seq);/*dbg*/
- if (ppre->di_wr_buf) {
-
- //dim_tr_ops.pre_ready(ppre->di_wr_buf->vframe->omx_index);
- if (ppre->pre_throw_flag > 0) {
- ppre->di_wr_buf->c.throw_flag = 1;
- ppre->pre_throw_flag--;
- } else {
- ppre->di_wr_buf->c.throw_flag = 0;
- }
-
- /*dec vf keep*/
- if (ppre->di_inp_buf &&
- ppre->di_inp_buf->c.dec_vf_state & DI_BIT0) {
- ppre->di_wr_buf->c.in_buf = ppre->di_inp_buf;
- dimv3_print("dim:dec vf:l[%d],t[%d]\n",
- ppre->di_wr_buf->c.in_buf->index,
- ppre->di_wr_buf->c.in_buf->type);
- dimv3_print("dim:wr[%d],t[%d]\n",
- ppre->di_wr_buf->index,
- ppre->di_wr_buf->type);
- }
-
- ppre->di_post_wr_buf = ppre->di_wr_buf;
- post_wr_buf = ppre->di_post_wr_buf;
-
- if (post_wr_buf && !ppre->cur_prog_flag &&
- !flg_timeout) {/*ary: i mode ?*/
- dimv3_read_pulldown_info(&glb_frame_mot_num,
- &glb_field_mot_num);
- if (dimp_get(eDI_MP_pulldown_enable))
- /*pulldown_detection*/
- get_ops_pd()->detection(&post_wr_buf->c.pd_config,
- ppre->mtn_status,
- overturn,
- /*ppre->di_inp_buf->vframe*/
- &ppre->dvfm->vframe.vfm);
- /*if (combing_fix_en)*/
- //if (di_mpr(combing_fix_en)) {
- if (ppre->combing_fix_en) {
- tmp_cur_lev /*cur_lev*/
- = get_ops_mtn()->adaptive_combing_fixing(
- ppre->mtn_status,
- glb_field_mot_num,
- glb_frame_mot_num,
- dimp_get(eDI_MP_di_force_bit_mode));
- dimp_set(eDI_MP_cur_lev, tmp_cur_lev);
- }
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- get_ops_nr()->adaptive_cue_adjust(
- glb_frame_mot_num,
- glb_field_mot_num);
- dimv3_pulldown_info_clear_g12a();
- }
-
- if (ppre->cur_prog_flag) { /*progressive*/
- if (ppre->prog_proc_type == 0) { /*p as i */
- /* di_mem_buf_dup->vfrme
- * is either local vframe,
- * or bot field of vframe from in_list
- */
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p
- = ppre->di_chan2_buf_dup_p;
- ppre->di_chan2_buf_dup_p
- = ppre->di_wr_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s:set di_mem to di_chan2,", __func__);
- dimv3_print("%s:set di_chan2 to di_wr_buf\n", __func__);
-#endif
- } else {
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- /*recycle the progress throw buffer*/
- if (ppre->di_wr_buf->c.throw_flag) {
- ppre->di_wr_buf->
- c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s set throw %s[%d] pre_ref_count to 0.\n",
- __func__,
- vframe_type_name[ppre->di_wr_buf->type],
- ppre->di_wr_buf->index);
-#endif
- } else {
- ppre->di_mem_buf_dup_p
- = ppre->di_wr_buf;
- }
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to di_wr_buf\n",
- __func__);
-#endif
- }
-
- ppre->di_wr_buf->c.seq
- = ppre->pre_ready_seq++;
- ppre->di_wr_buf->c.post_ref_count = 0;
- ppre->di_wr_buf->c.left_right
- = ppre->left_right;
- if (ppre->source_change_flag) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- ppre->source_change_flag = 0;
- } else {
- ppre->di_wr_buf->c.new_format_flag = 0;
- }
- if (di_bypass_state_get(channel) == 1) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- /*bypass_state = 0;*/
- di_bypass_state_set(channel, false);
-
- }
- if (ppre->di_post_wr_buf)
- div3_que_in(channel, QUE_PRE_READY,
- ppre->di_post_wr_buf);
-
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: %s[%d] => pre_ready_list\n", __func__,
- vframe_type_name[ppre->di_wr_buf->type],
- ppre->di_wr_buf->index);
-#endif
- if (ppre->di_wr_buf) {
- ppre->di_post_wr_buf = NULL;
- ppre->di_wr_buf = NULL;
- }
- } else {
- /*i mode*/
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- if (ppre->di_chan2_buf_dup_p) {
- ppre->di_mem_buf_dup_p =
- ppre->di_chan2_buf_dup_p;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: di_mem_buf_dup_p = di_chan2_buf_dup_p\n",
- __func__);
-#endif
- }
- ppre->di_chan2_buf_dup_p = ppre->di_wr_buf;
-
- if (ppre->source_change_flag) {
- /* add dummy buf, will not be displayed */
- addv3_dummy_vframe_type_pre(post_wr_buf,
- channel);
- }
- ppre->di_wr_buf->c.seq = ppre->pre_ready_seq++;
- ppre->di_wr_buf->c.left_right = ppre->left_right;
- ppre->di_wr_buf->c.post_ref_count = 0;
-
- if (ppre->source_change_flag) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- ppre->source_change_flag = 0;
- } else {
- ppre->di_wr_buf->c.new_format_flag = 0;
- }
- if (di_bypass_state_get(channel) == 1) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- /*bypass_state = 0;*/
- di_bypass_state_set(channel, false);
-
- }
-
- if (ppre->di_post_wr_buf)
- div3_que_in(channel, QUE_PRE_READY,
- ppre->di_post_wr_buf);
-
- dimv3_print("%s: %s[%d] => pre_ready_list\n", __func__,
- vframe_type_name[ppre->di_wr_buf->type],
- ppre->di_wr_buf->index);
-
- if (ppre->di_wr_buf) {
- ppre->di_post_wr_buf = NULL;
-
- ppre->di_wr_buf = NULL;
- }
- }
- }
-
- if (ppre->di_inp_buf) {
- di_lock_irqfiq_save(irq_flag2);
- if (!(ppre->di_inp_buf->c.dec_vf_state & DI_BIT0)) {
- queuev3_in(channel,
- ppre->di_inp_buf, QUEUE_RECYCLE);
- ppre->di_inp_buf = NULL;
- }
- di_unlock_irqfiq_restore(irq_flag2);
- }
- dimv3_print("%s\n", __func__);
- #ifdef HIS_V3
- if (ppre->dvfm) { /*ary tmp : dvfm recycle*/
- pch = get_chdata(channel);
- pdvfm = dvfmv3_get(pch, QUED_T_PRE);
- if (ppre->dvfm->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- ppre->dvfm->index,
- pdvfm->index);
- return;
- }
-
- qued_ops.in(pch, QUED_T_RECYCL, ppre->dvfm->index);
- ppre->dvfm = NULL;
- } else{
- dimv3_print("%s:warn:no dvfm\n", __func__);
- }
- #else
-
- #endif
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_DONEE,
- channel, ppre->in_seq);/*dbg*/
-
- dimv3_dbg_pre_cnt(channel, "d2");
-}
-
-#endif
-static void recycle_vframe_type_pre(struct di_buf_s *di_buf,
- unsigned int channel)
-{
- ulong irq_flag2 = 0;
-
- di_lock_irqfiq_save(irq_flag2);
-
- queuev3_in(channel, di_buf, QUEUE_RECYCLE);
-
- di_unlock_irqfiq_restore(irq_flag2);
-}
-
-#if 0 /*move to di_pres.c*/
-/*
- * add dummy buffer to pre ready queue
- */
-static void addv3_dummy_vframe_type_pre(struct di_buf_s *src_buf,
- unsigned int channel)
-{
- struct di_buf_s *di_buf_tmp = NULL;
-
- if (!queuev3_empty(channel, QUEUE_LOCAL_FREE)) {
- di_buf_tmp = getv3_di_buf_head(channel, QUEUE_LOCAL_FREE);
- if (di_buf_tmp) {
- dimv3_print("%s\n");
- queuev3_out(channel, di_buf_tmp);
- di_buf_tmp->c.pre_ref_count = 0;
- di_buf_tmp->c.post_ref_count = 0;
- di_buf_tmp->c.post_proc_flag = 3;
- di_buf_tmp->c.new_format_flag = 0;
- di_buf_tmp->c.sts |= EDI_ST_DUMMY;
- if (!IS_ERR_OR_NULL(src_buf)) {
- #if 0
- memcpy(di_buf_tmp->vframe, src_buf->vframe,
- sizeof(vframe_t));
- #endif
- di_buf_tmp->c.wmode = src_buf->c.wmode;
- }
- div3_que_in(channel, QUE_PRE_READY, di_buf_tmp);
- #ifdef DI_BUFFER_DEBUG
- dimv3_print("%s: dummy %s[%d] => pre_ready_list\n",
- __func__,
- vframe_type_name[di_buf_tmp->type],
- di_buf_tmp->index);
- #endif
- }
- }
-}
-#endif
-/*
- * it depend on local buffer queue type is 2
- */
-static int peek_free_linked_buf(unsigned int channel)
-{
- struct di_buf_s *p = NULL;
- int itmp, p_index = -2;
-
- if (listv3_count(channel, QUEUE_LOCAL_FREE) < 2)
- return -1;
-
- queue_for_each_entry(p, channel, QUEUE_LOCAL_FREE, list) {
- if (abs(p->index - p_index) == 1)
- return min(p->index, p_index);
- p_index = p->index;
- }
- return -1;
-}
-
-/*
- * it depend on local buffer queue type is 2
- */
-static struct di_buf_s *get_free_linked_buf(int idx, unsigned int channel)
-{
- struct di_buf_s *di_buf = NULL, *di_buf_linked = NULL;
- int pool_idx = 0, di_buf_idx = 0;
- struct queue_s *pqueue = get_queue(channel);
- struct di_buf_pool_s *pbuf_pool = get_buf_pool(channel);
-
- queue_t *q = &pqueue[QUEUE_LOCAL_FREE];
-
- if (listv3_count(channel, QUEUE_LOCAL_FREE) < 2)
- return NULL;
- if (q->pool[idx] != 0 && q->pool[idx + 1] != 0) {
- pool_idx = ((q->pool[idx] >> 8) & 0xff) - 1;
- di_buf_idx = q->pool[idx] & 0xff;
- if (pool_idx < VFRAME_TYPE_NUM) {
- if (di_buf_idx < pbuf_pool[pool_idx].size) {
- di_buf = &(pbuf_pool[pool_idx].
- di_buf_ptr[di_buf_idx]);
- queuev3_out(channel, di_buf);
- di_buf->c.sts |= EDI_ST_AS_LINKA;
- }
- }
- pool_idx = ((q->pool[idx + 1] >> 8) & 0xff) - 1;
- di_buf_idx = q->pool[idx + 1] & 0xff;
- if (pool_idx < VFRAME_TYPE_NUM) {
- if (di_buf_idx < pbuf_pool[pool_idx].size) {
- di_buf_linked = &(pbuf_pool[pool_idx].
- di_buf_ptr[di_buf_idx]);
- queuev3_out(channel, di_buf_linked);
- di_buf_linked->c.sts |= EDI_ST_AS_LINKB;
- }
- }
- if (IS_ERR_OR_NULL(di_buf)) {
- pr_error("%s:err 1\n", __func__);
- //di_buf->c.sts |= EDI_ST_AS_LINK_ERR1;
- return NULL;
- }
- di_buf->c.di_wr_linked_buf = di_buf_linked;
- }
- return di_buf;
-}
-
-#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
-#if 0
-static void pre_inp_canvas_config(struct vframe_s *vf)
-{
- if (vf->canvas0Addr == (u32)-1) {
- canvas_config_config(di_inp_idx[0],
- &vf->canvas0_config[0]);
- canvas_config_config(di_inp_idx[1],
- &vf->canvas0_config[1]);
- vf->canvas0Addr = (di_inp_idx[1] << 8) | (di_inp_idx[0]);
- if (vf->plane_num == 2) {
- vf->canvas0Addr |= (di_inp_idx[1] << 16);
- } else if (vf->plane_num == 3) {
- canvas_config_config(di_inp_idx[2],
- &vf->canvas0_config[2]);
- vf->canvas0Addr |= (di_inp_idx[2] << 16);
- }
- vf->canvas1Addr = vf->canvas0Addr;
- }
-}
-#else
-/*move to di_vframe*/
-#if 0
-static void pre_inp_canvas_config(struct di_buf_s *di_buf)
-{
- struct dim_vmode_s *pvmode;
- struct vframe_s *vf;
-
- pvmode = &di_buf->c.vmode;
- vf = di_buf->vframe;
-
- if (pvmode->canvas0Addr == (u32)-1) {
- canvas_config_config(di_inp_idx[0],
- &vf->canvas0_config[0]);
- canvas_config_config(di_inp_idx[1],
- &vf->canvas0_config[1]);
- pvmode->canvas0Addr = (di_inp_idx[1] << 8) | (di_inp_idx[0]);
-
- if (vf->plane_num == 2) {
- pvmode->canvas0Addr |= (di_inp_idx[1] << 16);
- } else if (vf->plane_num == 3) {
- canvas_config_config(di_inp_idx[2],
- &vf->canvas0_config[2]);
- pvmode->canvas0Addr |= (di_inp_idx[2] << 16);
- }
- pvmode->canvas1Addr = vf->canvas0Addr;
- }
-}
-#endif
-#endif
-#endif
-
-#if 0
-bool di_get_pre_hsc_down_en(void)
-{
- return pre_hsc_down_en;
-}
-#endif
-bool dbgv3_first_frame; /*debug */
-unsigned int dbgv3_first_cnt_pre;
-unsigned int dbgv3_first_cnt_post;
-#define DI_DBG_CNT (2)
-void dimv3_dbg_pre_cnt(unsigned int channel, char *item)
-{
- bool flgs = false;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (ppre->field_count < DI_DBG_CNT) {
- dbgv3_first_frame("%d:%s:%d\n", channel, item,
- ppre->field_count);
- dbgv3_first_frame = true;
- flgs = true;
- dbgv3_first_cnt_pre = DI_DBG_CNT * 5;
- dbgv3_first_cnt_post = DI_DBG_CNT * 4 + 1;
- } else if (ppre->field_count == DI_DBG_CNT) {/*don't use >=*/
- dbgv3_first_frame = false;
- dbgv3_first_cnt_pre = 0;
- dbgv3_first_cnt_post = 0;
- }
-
- if ((dbgv3_first_frame) && !flgs && dbgv3_first_cnt_pre) {
- dbgv3_first_frame("%d:n%s:%d\n", channel, item,
- ppre->field_count);
- dbgv3_first_cnt_pre--;
- }
-}
-
-static void dbg_post_cnt(unsigned int ch, char *item)
-{
- struct di_post_stru_s *ppost = get_post_stru(ch);
-
- if (dbgv3_first_cnt_post) {
- dbgv3_first_frame("%d:%s:%d\n", ch, item,
- ppost->frame_cnt);
- dbgv3_first_cnt_post--;
- }
-}
-
-#if 0
-/*must been called when dim_pre_de_buf_config return true*/
-void pre_p_asi_set_next(unsigned int ch)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
-
- ppre->p_asi_next = ppre->di_inp_buf;
-}
-#endif
-
-/*for first frame no need to ready buf*/
-
-
-/********************************************************
- * for pre local buf's vframe:
- * tbuf: taget local di buf
- * fbuf: input di buf
- ********************************************************/
-
-bool vfm_fill_for_di_pre_local(struct di_buf_s *tbuf, struct di_buf_s *fbuf,
- struct di_ch_s *pch)
-{
-// struct di_ch_s *pch;
- //struct vframe_s *tvfm;
- //struct vframe_s *fvfm;
- struct dim_wmode_s *fwmode;
- struct dim_vmode_s *fvmode;
- struct dim_vmode_s *tvtp;
-
-// pch = get_chdata(ch);
- if (!pch ||
- !tbuf ||
- !fbuf) {
- PR_ERR("%s:no buf\n", __func__);
- return false;
- }
-
- //tvfm = tbuf->vframe;
- //fvfm = fbuf->vframe;
- fwmode = &fbuf->c.wmode;
- fvmode = &fbuf->c.vmode;
- tvtp = &tbuf->c.vmode;
- #if 0 /*remove vframe 12-03*/
- memcpy(tvfm, fbuf->vframe, sizeof(*tvfm));
-
- tvfm->private_data = tbuf;
- #ifdef CAN
- /*CAN ? any use ?*/
- tvfm->canvas0Addr = tbuf->nr_canvas_idx;
- tvfm->canvas1Addr = tbuf->nr_canvas_idx;
- #endif
-
- /* set vframe bit info */
- tvfm->bitdepth &= ~(BITDEPTH_YMASK | FULL_PACK_422_MODE);
- tvfm->bitdepth |= pch->cfgt.vfm_bitdepth;
-
- if (fwmode->is_i || fwmode->p_as_i) {
- if (VFMT_IS_TOP(fvfm->type))
- tvfm->type = VIDTYPE_INTERLACE_TOP |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- else
- tvfm->type = VIDTYPE_INTERLACE_BOTTOM |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- } else {
- tvfm->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
-
- }
- /*add for vpp skip line ref*/
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
- #endif /*remove vframe*/
- /*vtyp*/
- if (fwmode->is_i || fwmode->p_as_i) {
- if (fwmode->is_top)
- tvtp->vtype = DIM_VFM_LOCAL_T;
- else
- tvtp->vtype = DIM_VFM_LOCAL_B;
- } else {
- tvtp->vtype = DIM_VFM_VIU_422;
- }
- if (fwmode->is_afbc)
- tvtp->vtype |= DIM_VFM_COMPRESS;
-
- tvtp->canvas0Addr = tbuf->nr_canvas_idx;
- tvtp->h = fbuf->c.wmode.src_h; /*?*/
- tvtp->w = fbuf->c.wmode.src_w; /*?*/
- tvtp->bitdepth &= ~(BITDEPTH_YMASK | FULL_PACK_422_MODE);
- tvtp->bitdepth |= pch->cfgt.vfm_bitdepth;
- tvtp->omx_index = fvmode->omx_index;
- tvtp->ready_jiffies64 = fvmode->ready_jiffies64;
-
- /*bit_mode copy from config_di_mif*/
- if (tvtp->bitdepth & BITDEPTH_Y10) {
- if (tvtp->vtype & DIM_VFM_VIU_444)
- tvtp->bit_mode =
- (tvtp->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- else if (tvtp->vtype & DIM_VFM_VIU_422)
- tvtp->bit_mode =
- (tvtp->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- } else {
- tvtp->bit_mode = 0;
- }
-
- return true;
-}
-
-/********************************************************
- * dim_pre_cfg_ele_change:
- * check if change or not;
- * set ppre
- * return: 0: not change; 1: change;
- ********************************************************/
-unsigned int dim_pre_cfg_ele_change(struct di_ch_s *pch,
- struct dim_dvfm_s *pdvfm)
-{
- unsigned int ch;
- struct di_pre_stru_s *ppre;
- unsigned int ret;
- unsigned char change_type = 0;
- unsigned char change_type2 = 0;
- struct dim_dvfm_s *plstdvfm;
-
- if (!pch)
- return 0;
-
- /*variable set*/
- ret = 0;
- ch = pch->ch_id;
- ppre = get_pre_stru(ch);
- plstdvfm = &pch->lst_dvfm;
-
- /*check*/
- prev3_vinfo_set(ch, &pdvfm->in_inf);
- change_type = isv3_source_change_dfvm(plstdvfm, pdvfm, ch);
- /*****************************/
- /*source change*/
- /* source change, when i mix p,force p as i*/
- if (change_type == 1 ||
- (change_type == 2 && ppre->cur_prog_flag == 1)) {
- /*last is p £¿*/
- if (ppre->di_mem_buf_dup_p) {
- /*avoid only 2 i field then p field*/
- if ((ppre->cur_prog_flag == 0) &&
- dimp_get(eDI_MP_use_2_interlace_buff))
- ppre->di_mem_buf_dup_p->c.post_proc_flag = -1;
-
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- }
- if (ppre->di_chan2_buf_dup_p) {
- /*avoid only 1 i field then p field*/
- if ((ppre->cur_prog_flag == 0) &&
- dimp_get(eDI_MP_use_2_interlace_buff))
- ppre->di_chan2_buf_dup_p->c.post_proc_flag = -1;
-
- ppre->di_chan2_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_chan2_buf_dup_p = NULL;
- }
- PR_INF("%s:ch[%d]:%ums %dth source change:\n",
- __func__,
- ch,
- dim_get_timerms(pdvfm->vmode.ready_jiffies64),
- ppre->in_seq);
- PR_INF("\t0x%x/%d/%d/%d=>0x%x/%d/%d/%d\n",
- plstdvfm->in_inf.vtype_ori,
- plstdvfm->in_inf.w,
- plstdvfm->in_inf.h,
- plstdvfm->in_inf.src_type,
- pdvfm->in_inf.vtype_ori,
- pdvfm->in_inf.w,
- pdvfm->in_inf.h,
- pdvfm->in_inf.src_type);
-
- ppre->cur_width = pdvfm->in_inf.w;//pdvfm->wmode.w;
- ppre->cur_height = pdvfm->in_inf.h;
-
- ppre->cur_prog_flag = !pdvfm->wmode.is_i;
-
- //this is set by mode ppre->prog_proc_type = 0; /*p as i*/
-
- ppre->cur_source_type = pdvfm->in_inf.src_type;
- ppre->cur_sig_fmt = pdvfm->in_inf.sig_fmt;
- ppre->orientation = pdvfm->wmode.is_angle;
-
- ppre->source_change_flag = 1;
- ppre->input_size_change_flag = true;
-
- ppre->field_count = 0;
- ret = 1;
- /*source change end*/
- /********************************************************/
- }
- ppre->cur_inp_type = pdvfm->in_inf.vtype_ori;
- dimv3_set_pre_dfvm(plstdvfm, pdvfm);
- /********************************************************/
- if (!change_type) {
- change_type2 = isv3_vinfo_change(ch);
- if (change_type2) {
- /*ppre->source_change_flag = 1;*/
- ppre->input_size_change_flag = true;
- }
- }
-
- ppre->source_trans_fmt = pdvfm->in_inf.trans_fmt;
- ppre->left_right = ppre->left_right ? 0 : 1;
-
- ppre->invert_flag = pdvfm->wmode.is_invert_tp;
- return ret;
-}
-
-/********************************************************
- * for prog process as i top:
- ********************************************************/
-unsigned char dim_pre_de_buf_config_p_asi_t(unsigned int ch)
-{
-
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *vframe;
-// unsigned char change_type = 0;
-// unsigned char change_type2 = 0;
- void **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
-
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
- struct dim_dvfm_s *plstdvfm;// = &ppre->lst_dvfm;
- struct di_buf_s *di_buf_tmp = NULL;
-
- if (!dipv3_cma_st_is_ready(ch))
- return 0;
-
- if (div3_que_list_count(ch, QUE_IN_FREE) < 2 ||
- queuev3_empty(ch, QUEUE_LOCAL_FREE))
- return 0;
-
- if (div3_que_list_count(ch, QUE_PRE_READY) >= DI_PRE_READY_LIMIT)
- return 0;
-
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- plstdvfm = &pch->lst_dvfm;
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in) {
- PR_ERR("%s:no pdvfm?\n", __func__);
- return 0;
- }
-
- vframe = &pdvfm->vframe.vfm;
- dimv3_tr_ops.pre_get(pdvfm->vmode.omx_index);
- //didbg_vframe_in_copy(ch, vframe);
- pdvfm->wmode.seq = ppre->in_seq;
- dimv3_print("DI:ch[%d] get %dth vf[0x%p] from frontend %u ms.\n",
- ch,
- ppre->in_seq, vframe,
- dim_get_timerms(vframe->ready_jiffies64));
-
- /*change and set ppre*/
- dim_pre_cfg_ele_change(pch, pdvfm);
- ppre->prog_proc_type = 0; /*p as i*/
- /********************************************************/
-
- //vframe->type = pdvfm->wmode.vtype;
- //ppre->source_trans_fmt = vframe->trans_fmt;
- //ppre->left_right = ppre->left_right ? 0 : 1; /*?*/
- //ppre->invert_flag = 0;
- //ppre->width_bk = vframe->width;
- //vframe->width = pdvfm->wmode.w;
- //vframe->height = pdvfm->wmode.h;
- /* backup frame motion info */
- //vframe->combing_cur_lev = dimp_get(eDI_MP_cur_lev);/*cur_lev;*/
-
- dimv3_print("%s: vf_get => 0x%p\n", __func__, vframe);
- /*buf from IN_FREE************************/
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch))
- return 0;
-
- /*dbg*/
- dimv3_dbg_pre_cnt(ch, "cf1");
- /*****************************************/
- pvframe_in[di_buf->index] = NULL;// for p as i //vframe;
-
- #if 0
- /*di_buf[in] set vframe*/
- memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- di_buf->vframe->width = pdvfm->wmode.src_w;
- di_buf->vframe->height = pdvfm->wmode.src_h;
- di_buf->vframe->combing_cur_lev = dimp_get(eDI_MP_cur_lev);
- #endif
- /**/
- //di_buf->c.width_bk = ppre->width_bk; /*ary.sui 2019-04-23*/
- di_buf->c.width_bk = pdvfm->wmode.o_w;
- di_buf->c.seq = ppre->in_seq;
- /*wmode*/
- di_buf->c.wmode = pdvfm->wmode;
- di_buf->c.sts |= EDI_ST_P_T;
- /*vmode*/
- di_buf->c.vmode = pdvfm->vmode;
- di_buf->c.pdvfm = pdvfm;
- ppre->in_seq++;
-
- /*proc p as i only */
- //pvframe_in[di_buf->index] = NULL;
-
- //di_buf->vframe->type = VFMT_SET_TOP(di_buf->vframe->type);
-
- di_buf->c.post_proc_flag = 0;
-
- /*2sd********************************/
- di_buf_tmp = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
- if (dimv3_check_di_buf(di_buf_tmp, 10, ch)) {
- recycle_vframe_type_pre(di_buf, ch);
- PR_ERR("DI:no free in_buffer for progressive skip.\n");
- return 0;
- }
-
- //di_buf_tmp->vframe->private_data = di_buf_tmp;
- di_buf_tmp->c.seq = ppre->in_seq;
- ppre->in_seq++;
- pvframe_in[di_buf_tmp->index] = pdvfm->vfm_in;
-
- //memcpy(di_buf_tmp->vframe, vframe, sizeof(*di_buf_tmp->vframe));
- ppre->di_inp_buf_next = di_buf_tmp;
- di_buf_tmp->c.wmode = di_buf->c.wmode;
- di_buf_tmp->c.width_bk = di_buf->c.width_bk;
- /*vmode*/
- di_buf_tmp->c.vmode = di_buf->c.vmode;
- di_buf_tmp->c.pdvfm = pdvfm;
- #if 0
- di_buf_tmp->vframe->type &= (~VIDTYPE_TYPEMASK);
- di_buf_tmp->vframe->type |= VIDTYPE_INTERLACE_BOTTOM;
- #else
- //di_buf_tmp->vframe->type = VFMT_SET_BOTTOM(di_buf_tmp->vframe->type);
- #endif
- di_buf_tmp->c.post_proc_flag = 0;
- /*2sd end****************************/
- ppre->di_inp_buf = di_buf;
-
- if (!ppre->di_mem_buf_dup_p) /*ary use ?*/
- ppre->di_mem_buf_dup_p = di_buf;
-
- /*proc p as i end */
- /*******************/
-
- /*is proc end*/
- /********************************************************/
-
-/*main proc end*/
-/*****************************************************************************/
- /*di_buf[local]*/
- di_buf = getv3_di_buf_head(ch, QUEUE_LOCAL_FREE);
- if (dimv3_check_di_buf(di_buf, 11, ch)) {
- /* recycle_keep_buffer();
- * pr_dbg("%s:recycle keep buffer\n", __func__);
- */
- recycle_vframe_type_pre(ppre->di_inp_buf, ch);
- PR_ERR("%s:no local\n", __func__);
- return 0;
- }
- queuev3_out(ch, di_buf);/*QUEUE_LOCAL_FREE*/
-
-
- ppre->di_wr_buf = di_buf;
- //ppre->di_wr_buf->c.pre_ref_count = 1;
- /*set local buf vfram*/
-
- /* set local buf vframe */
- vfm_fill_for_di_pre_local(di_buf, ppre->di_inp_buf, pch);
-
- /*set local buf c*/
- di_buf->c.canvas_config_flag = 2;
- di_buf->c.di_wr_linked_buf = NULL;
- di_buf->c.wmode = ppre->di_inp_buf->c.wmode;
- di_buf->c.pre_ref_count = 1;
-
- //err: vmode have set in vfm_fill_for_di_pre_local
- //di_buf->c.vmode = ppre->di_inp_buf->c.vmode;//new
- //di_buf->c.width_bk = ppre->width_bk; /*ary:2019-04-23*/
- di_buf->c.width_bk = pdvfm->wmode.o_w;
-
- if (is_bypass_post(ch)) {
- if (dimp_get(eDI_MP_bypass_post_state) == 0)
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 1);
- } else {
- if (dimp_get(eDI_MP_bypass_post_state))
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 0);
- }
-
- if (ppre->di_inp_buf->c.post_proc_flag == 0) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- }
-
- if ((ppre->di_mem_buf_dup_p == ppre->di_wr_buf) ||
- (ppre->di_chan2_buf_dup_p == ppre->di_wr_buf)) {
- pr_dbg("+++++++++++++++++++++++\n");
- if (recovery_flag == 0)
- recovery_log_reason = 12;
-
- recovery_flag++;
- return 0;
- }
-
- /**************************************/
- if (pdvfm) {
- pch = get_chdata(ch);
- ppre->dvfm = pdvfm;
- pdvfm->etype = EDIM_DISP_T_PRE;
- qued_ops.in(pch, QUED_T_PRE, pdvfm->index);
-
- di_buf->c.pdvfm = pdvfm; /*2019-12-03*/
- }
- return 1;
-}
-
-
-/********************************************************
- * for prog process as i bottom:
- ********************************************************/
-
-unsigned char dim_pre_de_buf_config_p_asi_b(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;
-
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_ch_s *pch;
-
- if (!dipv3_cma_st_is_ready(ch))
- return 0;
-
- if (queuev3_empty(ch, QUEUE_LOCAL_FREE))
- return 0;
-
- pch = get_chdata(ch);
- if (!pch)
- return 0;
-
- ppre->di_inp_buf = ppre->di_inp_buf_next;
- ppre->di_inp_buf_next = NULL;
-
- if (!ppre->di_mem_buf_dup_p) {/* use n */
- ppre->di_mem_buf_dup_p = ppre->di_inp_buf;
- }
-
- /*di_buf[local]*/
- di_buf = getv3_di_buf_head(ch, QUEUE_LOCAL_FREE);
- if (dimv3_check_di_buf(di_buf, 11, ch)) {
- /* recycle_keep_buffer();
- * pr_dbg("%s:recycle keep buffer\n", __func__);
- */
- recycle_vframe_type_pre(ppre->di_inp_buf, ch);
- PR_ERR("%s:no local\n", __func__);
- return 0;
- }
-
- queuev3_out(ch, di_buf);/*QUEUE_LOCAL_FREE*/
-
- ppre->di_wr_buf = di_buf;
- //ppre->di_wr_buf->c.pre_ref_count = 1;
- /*set local buf vfram*/
-
- /* set local buf vframe */
- vfm_fill_for_di_pre_local(di_buf, ppre->di_inp_buf, pch);
-
- /*set local buf c*/
- di_buf->c.canvas_config_flag = 2;
- di_buf->c.di_wr_linked_buf = NULL;
- di_buf->c.wmode = ppre->di_inp_buf->c.wmode;
- di_buf->c.wmode.is_top = 0; //new
- di_buf->c.pre_ref_count = 1;
- // vmode have set in vfm_fill_for_di_pre_local
- //err di_buf->c.vmode = ppre->di_inp_buf->c.vmode; //new
- di_buf->c.sts |= EDI_ST_P_B;
- di_buf->c.width_bk = ppre->di_inp_buf->c.width_bk;
-
- if (is_bypass_post(ch)) {
- if (dimp_get(eDI_MP_bypass_post_state) == 0)
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 1);
- } else {
- if (dimp_get(eDI_MP_bypass_post_state))
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 0);
- }
-
- if (ppre->di_inp_buf->c.post_proc_flag == 0) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- }
-
- #if 0
- if ((ppre->di_mem_buf_dup_p == ppre->di_wr_buf) ||
- (ppre->di_chan2_buf_dup_p == ppre->di_wr_buf)) {
- pr_dbg("+++++++++++++++++++++++\n");
- if (recovery_flag == 0)
- recovery_log_reason = 12;
-
- recovery_flag++;
- return 0;
- }
- #endif
- /**************************************/
- return 1;
-}
-
-
-unsigned char dim_pre_de_buf_config_bypass(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;
- //struct vframe_s *vframe;
- int i;
- //int i, di_linked_buf_idx = -1;
- //unsigned char change_type = 0;
- //unsigned char change_type2 = 0;
- /*bool bit10_pack_patch = false; move to dim_cfg_init*/
- /*unsigned int width_roundup = 2; move to dim_cfg_init*/
- void **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- //struct di_post_stru_s *ppost = get_post_stru(ch);
- //struct di_dev_s *de_devp = get_dim_de_devp();
- //int cfg_prog_proc = dimp_get(eDI_MP_prog_proc_config);
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
-// struct dim_dvfm_s *plstdvfm;// = &ppre->lst_dvfm;
- int in_buf_num = 0;
- bool flg_eos = false;
-
- /*no local free*/
- if (div3_que_list_count(ch, QUE_IN_FREE) < 1)
- return 0;
-
- /*ary: */
- /* some provider has problem if receiver
- * get all buffers of provider
- */
-
- /*cur_lev = 0;*/
- dimp_set(eDI_MP_cur_lev, 0);
- /*ary: need change to count ready buf*/
- for (i = 0; i < MAX_IN_BUF_NUM; i++)
- if (pvframe_in[i])
- in_buf_num++;
- if (in_buf_num > BYPASS_GET_MAX_BUF_NUM)
- return 0;
-
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);/*?*/
-
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- //plstdvfm = &pch->lst_dvfm;
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in)
- return 0;
- //vframe = pdvfm->vfm_in;
- flg_eos = pdvfm->wmode.is_eos;
- if (flg_eos)
- PR_INF("%s:EOS\n", __func__);
-
- dimv3_set_pre_dfvm_last_bypass(pch);
- /*****************************************/
- dimv3_tr_ops.pre_get(pdvfm->vmode.omx_index);
- ppre->invert_flag = pdvfm->wmode.is_invert_tp;
-
- /*buf from IN_FREE*************/
- /*in buf*/
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch))
- return 0;
- /******************************/
-
- /*di_buf[in] set*/
- //memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
- //di_buf->vframe->private_data = di_buf;
-
- dimv3_dbg_pre_cnt(ch, "cf1");
- //di_buf->c.width_bk = ppre->width_bk; /*ary.sui 2019-04-23*/
-
- pvframe_in[di_buf->index] = pdvfm->vfm_in;
- di_buf->c.seq = ppre->in_seq;
- pdvfm->wmode.seq = ppre->in_seq;
- ppre->in_seq++;
-
- /*is bypass*/
- /* bypass progressive */
- //di_buf->c.seq = ppre->pre_ready_seq++;/*?*/
- di_buf->c.post_ref_count = 0;
- /*cur_lev = 0;*/
- //dimp_set(eDI_MP_cur_lev, 0);
-
- ppre->source_change_flag = 0;
-
- di_buf->c.new_format_flag = 0;
-
- /*from other mode to bypass mode*/
- if (di_bypass_state_get(ch) == 0) {
- if (ppre->di_mem_buf_dup_p) {
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- }
- if (ppre->di_chan2_buf_dup_p) {
- ppre->di_chan2_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_chan2_buf_dup_p = NULL;
- }
-
- if (ppre->di_wr_buf) {
- ppre->di_wr_buf->c.pre_ref_count = 0;
- ppre->di_wr_buf->c.post_ref_count = 0;
- recycle_vframe_type_pre(
- ppre->di_wr_buf, ch);
-
- ppre->di_wr_buf = NULL;
- }
-
- di_buf->c.new_format_flag = 1;
- di_bypass_state_set(ch, true);/*bypass_state:1;*/
-
- dimv3_print(
- "%s:bypass_state = 1\n",
- __func__);
-
- }
- /*di_bypass_state_get(channel) == 0 end*/
- /***************************************/
- //top_bot_config(di_buf);
- //di_buf->vframe.type = pdvfm->in_inf.vtype;
-
- /*if previous isn't bypass post_wr_buf not recycled */
-
- if ((bypass_pre & 0x2) && !ppre->cur_prog_flag)
- di_buf->c.post_proc_flag = -2;
- else
- di_buf->c.post_proc_flag = 0;
-
- di_buf->c.wmode = pdvfm->wmode;
- di_buf->c.vmode = pdvfm->vmode;/*for bypass*/
- di_buf->c.pdvfm = pdvfm;
-
- div3_que_in(ch, QUE_PRE_READY, di_buf);
- dimv3_print("di:cfg:post_proc_flag=%d\n",
- di_buf->c.post_proc_flag);
-
- qued_ops.in(pch, QUED_T_PRE, pdvfm->index);
- return 0;
-}
-
-/********************************************************
- * for prog process use i buf:
- ********************************************************/
-unsigned char dim_pre_de_buf_config_p_use_2ibuf(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *vframe;
-
- int di_linked_buf_idx = -1;
-// unsigned char change_type = 0;
-// unsigned char change_type2 = 0;
-
- void **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
- struct dim_dvfm_s *plstdvfm;// = &ppre->lst_dvfm;
-
- #if 0
- if (!dipv3_cma_st_is_ready(ch))
- return 0;
-
- if (div3_que_list_count(ch, QUE_IN_FREE) < 1)
- return 0;
-
- if (div3_que_list_count(ch, QUE_PRE_READY) >= DI_PRE_READY_LIMIT)
- return 0;
- #endif
-/**************************************************************************/
- if (ppre->prog_proc_type == 2) {
-
- #if 0
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx == -1 &&
- !IS_ERR_OR_NULL(ppost->keep_buf)) { /*ary: ?*/
- recycle_keep_buffer(ch);
- PR_INF("%s: recycle keep buffer null buf\n",
- __func__);
- return 0;
- }
- #else
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx == -1) {
- dimv3_print("%s:check no link buf\n", __func__);
- return 0;
- }
- #endif
- }
-/**************************************************************************/
-
-/*****************************************************************************/
-/*main proce */
-
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- plstdvfm = &pch->lst_dvfm;
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in) {
- PR_ERR("%s:no pdvfm?\n", __func__);
- return 0;
- }
-
- vframe = &pdvfm->vframe.vfm;
-
- /*****************************************/
- dimv3_tr_ops.pre_get(pdvfm->vmode.omx_index);
- //didbg_vframe_in_copy(ch, vframe);
- pdvfm->wmode.seq = ppre->in_seq;
- dimv3_print("DI:ch[%d] get %dth vf[0x%p] from frontend %u ms.\n",
- ch,
- ppre->in_seq, vframe,
- dim_get_timerms(vframe->ready_jiffies64));
- /********************************************************/
- /*change and set ppre*/
- dim_pre_cfg_ele_change(pch, pdvfm);
- ppre->prog_proc_type = 2;
- /*now:cfg_prog_proc is 0x23*/
-
- //vframe->type = pdvfm->wmode.vtype;
-
- //ppre->source_trans_fmt = vframe->trans_fmt;
- //ppre->left_right = ppre->left_right ? 0 : 1; /*?*/
-
- //ppre->invert_flag = 0;
-
- //vframe->type &= ~TB_DETECT_MASK; /*?vfm*/
-
- //ppre->width_bk = vframe->width;
-
- /* backup frame motion info */
- //vframe->combing_cur_lev = dimp_get(eDI_MP_cur_lev);/*cur_lev;*/
-
- dimv3_print("%s: vf_get => 0x%p\n", __func__, vframe);
-
- /*buf from IN_FREE************************/
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch)) {
- PR_ERR("%s no IN_FREE\n", __func__);
- return 0;
- }
- /*dbg*/
- dimv3_dbg_pre_cnt(ch, "cf1");
- /*****************************************/
- pvframe_in[di_buf->index] = pdvfm->vfm_in;
-
- #if 0
- /*di_buf[in] set vframe*/
- memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- di_buf->vframe->width = pdvfm->wmode.src_w;
- di_buf->vframe->height = pdvfm->wmode.src_h;
- #endif
- /**/
- di_buf->c.width_bk = pdvfm->wmode.o_w; /*ary.sui 2019-04-23*/
- di_buf->c.seq = ppre->in_seq;
- di_buf->c.wmode = pdvfm->wmode;
- di_buf->c.sts |= EDI_ST_P_U2I;
- /*vtyp*/
- di_buf->c.vmode = pdvfm->vmode;
- di_buf->c.pdvfm = pdvfm;
- ppre->in_seq++;
-
- /********************************************************/
- /*is proc*/
- if (di_buf->c.wmode.p_use_2i) {
- /*ary: not process prog as i*/
- di_buf->c.post_proc_flag = 0;
-
- ppre->di_inp_buf = di_buf;
-
- dimv3_print("%s: %s[%d] => di_inp_buf\n",
- __func__,
- vframe_type_name[di_buf->type],
- di_buf->index);
-
- if (!ppre->di_mem_buf_dup_p) {
- /* use n */
- ppre->di_mem_buf_dup_p = di_buf;
-
- dimv3_print("%s: set mem to be di_inp_buf\n", __func__);
-
- }
-
- /*is proc end*/
- /********************************************************/
- }
-
-/*main proc end*/
-/*****************************************************************************/
-
- /*dim_dbg_pre_cnt(channel, "cfg");*/
- /* get local buf link buf*/
- if (ppre->prog_proc_type == 2) {
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx != -1)
- di_buf = get_free_linked_buf(di_linked_buf_idx, ch);
- else
- di_buf = NULL;
- if (!di_buf) {
- PR_ERR("%s no link local buf\n", __func__);
- return 0;
- }
- di_buf->c.post_proc_flag = 0;
- di_buf->c.di_wr_linked_buf->c.pre_ref_count = 0;
- di_buf->c.di_wr_linked_buf->c.post_ref_count = 0;
- di_buf->c.canvas_config_flag = 1;
- }
-
- ppre->di_wr_buf = di_buf;
- ppre->di_wr_buf->c.pre_ref_count = 1;
-
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s: %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->type], di_buf->index);
- if (di_buf->c.di_wr_linked_buf)
- dimv3_print("%s: linked %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->c.di_wr_linked_buf->type],
- di_buf->c.di_wr_linked_buf->index);
-#endif
-#if 0
- /*di_buf[local]*/
- if (!di_buf)
- PR_ERR("%s:err1\n", __func__);
- if (!di_buf->vframe)
- PR_ERR("%s:err2\n", __func__);
- if (!ppre->di_inp_buf)
- PR_ERR("%s:err3\n", __func__);
- if (!ppre->di_inp_buf->vframe)
- PR_ERR("%s:err4\n", __func__);
-#endif
-
- vfm_fill_for_di_pre_local(di_buf, ppre->di_inp_buf, pch);
-
- di_buf->c.wmode = ppre->di_inp_buf->c.wmode;
- // vmode have set in vfm_fill_for_di_pre_local
- //err: di_buf->c.vmode = ppre->di_inp_buf->c.vmode; //new
- di_buf->c.width_bk = pdvfm->wmode.o_w; /*ary:2019-04-23*/
-
- if (is_bypass_post(ch)) {
- if (dimp_get(eDI_MP_bypass_post_state) == 0)
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 1);
- } else {
- if (dimp_get(eDI_MP_bypass_post_state))
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 0);
- }
-
- if (ppre->di_inp_buf->c.post_proc_flag == 0) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- }
-
- if ((ppre->di_mem_buf_dup_p == ppre->di_wr_buf) ||
- (ppre->di_chan2_buf_dup_p == ppre->di_wr_buf)) {
- PR_ERR("%s+++++++++++++++++++++++\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 12;
-
- recovery_flag++;
- return 0;
- }
-
- /**************************************/
- if (pdvfm) {
- pch = get_chdata(ch);
- ppre->dvfm = pdvfm;
- pdvfm->etype = EDIM_DISP_T_PRE;
- qued_ops.in(pch, QUED_T_PRE, pdvfm->index);
- dimv3_print("%s:qued in\n", __func__);
- di_buf->c.pdvfm = pdvfm; /*2019-12-03*/
- } else {
- PR_ERR("%s:no pdvfm\n", __func__);
- }
- return 1;
-}
-
-unsigned char dim_pre_de_buf_config_i(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *vframe;
- #ifdef HIS_V3
- unsigned char change_type = 0;
- #endif
- //unsigned char change_type2 = 0;
- unsigned int change = 0;
- void **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
-// struct dim_dvfm_s *plstdvfm;// = &ppre->lst_dvfm;
-
-/*****************************************************************************/
-/*main proce */
-
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- //plstdvfm = &pch->lst_dvfm;
-
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in) {
- PR_ERR("%s:no pdvfm\n", __func__);
- return 0;
- }
- vframe = &pdvfm->vframe.vfm;
-
- /*****************************************/
- dimv3_tr_ops.pre_get(pdvfm->vmode.omx_index);
- //didbg_vframe_in_copy(ch, vframe);
- pdvfm->wmode.seq = ppre->in_seq;
- dimv3_print("DI:ch[%d] get %dth from frontend %u ms.\n",
- ch,
- ppre->in_seq,
- dim_get_timerms(0));
-
- /*change and set ppre*/
- change = dim_pre_cfg_ele_change(pch, pdvfm);
- ppre->prog_proc_type = 0;
- #if 0
- vframe->type = pdvfm->wmode.vtype;
- vframe->type &= ~TB_DETECT_MASK;
-
- /* backup frame motion info */
- vframe->combing_cur_lev = dimp_get(eDI_MP_cur_lev);/*cur_lev;*/
- #endif
- //dim_print("%s: vf_get => 0x%p\n", __func__, vframe);
-
- /*buf from IN_FREE*/
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch)) {
- PR_ERR("%s no IN_FREE\n", __func__);
- return 0;
- }
-
- dimv3_dbg_pre_cnt(ch, "cf1");
- pvframe_in[di_buf->index] = pdvfm->vfm_in;
-
- /*di_buf[in] set*/
- #if 0
- memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
-
- di_buf->vframe->private_data = di_buf;
- di_buf->vframe->width = pdvfm->wmode.src_w;
- di_buf->vframe->height = pdvfm->wmode.src_h;
- #endif
-
- //di_buf->c.width_bk = ppre->width_bk; /*ary.sui 2019-04-23*/
- di_buf->c.seq = ppre->in_seq;
- /*wmode*/
- di_buf->c.wmode = pdvfm->wmode;
- di_buf->c.sts |= EDI_ST_I;
- /*vmode*/
- di_buf->c.vmode = pdvfm->vmode;
- di_buf->c.pdvfm = pdvfm;
- /*keep dec vf*/
- di_buf->c.dec_vf_state = DI_BIT0;
- ppre->in_seq++;
-
- if (ppre->cur_prog_flag == 0) { /*ary??*/
- /* check if top/bot interleaved */
- #ifdef HIS_V3
- if (change_type == 2)
- /* source is i interleaves p fields */
- ppre->force_interlace = true;
- #endif
- if ((ppre->cur_inp_type &
- DIM_VFM_TYPEMASK) == (di_buf->c.vmode.vtype &
- DIM_VFM_TYPEMASK)) {
- if (di_buf->c.wmode.is_top)
- same_field_top_count++;
- else
- same_field_bot_count++;
- }
- }
- ppre->cur_inp_type = vframe->type;
-
- /*********************************/
- if (!ppre->di_chan2_buf_dup_p) {
- ppre->field_count = 0;
- /* ignore contp2rd and contprd */
- }
- di_buf->c.post_proc_flag = 1;
- ppre->di_inp_buf = di_buf;
- dimv3_print("%s: %s[%d] => di_inp_buf\n", __func__,
- vframe_type_name[di_buf->type],
- di_buf->index);
-
- if (!ppre->di_mem_buf_dup_p) {/* use n */
- ppre->di_mem_buf_dup_p = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to be di_inp_buf\n",
- __func__);
-#endif
- }
-
- /*other end*/
- /********************************************************/
-/*main proc end*/
-/*****************************************************************************/
-
- /*dim_dbg_pre_cnt(channel, "cfg");*/
- /* di_wr_buf */
-
- /*di_buf[local]*/
- di_buf = getv3_di_buf_head(ch, QUEUE_LOCAL_FREE);
- if (dimv3_check_di_buf(di_buf, 11, ch)) {
- /* recycle_keep_buffer();
- * pr_dbg("%s:recycle keep buffer\n", __func__);
- */
- recycle_vframe_type_pre(ppre->di_inp_buf, ch);
- PR_ERR("%s no local free\n", __func__);
- return 0;
- }
- queuev3_out(ch, di_buf);/*QUEUE_LOCAL_FREE*/
-
- di_buf->c.canvas_config_flag = 2;
- di_buf->c.di_wr_linked_buf = NULL;
-
- ppre->di_wr_buf = di_buf;
- ppre->di_wr_buf->c.pre_ref_count = 1;
-
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s: %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->type], di_buf->index);
- if (di_buf->c.di_wr_linked_buf)
- dimv3_print("%s: linked %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->c.di_wr_linked_buf->type],
- di_buf->c.di_wr_linked_buf->index);
-#endif
-#if 0
- /*di_buf[local]*/
- if (!di_buf)
- PR_ERR("%s:err1\n", __func__);
- if (!di_buf->vframe)
- PR_ERR("%s:err2\n", __func__);
- if (!ppre->di_inp_buf)
- PR_ERR("%s:err3\n", __func__);
- if (!ppre->di_inp_buf->vframe)
- PR_ERR("%s:err4\n", __func__);
-#endif
-
- vfm_fill_for_di_pre_local(di_buf, ppre->di_inp_buf, pch);
-
- di_buf->c.wmode = ppre->di_inp_buf->c.wmode;
- di_buf->c.wmode.seq_pre = ppre->field_count;
- di_buf->c.width_bk = pdvfm->wmode.o_w;
-
- if (is_bypass_post(ch)) {
- if (dimp_get(eDI_MP_bypass_post_state) == 0)
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 1);
- } else {
- if (dimp_get(eDI_MP_bypass_post_state))
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 0);
- }
-
- if (ppre->di_inp_buf->c.post_proc_flag == 0) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- } else if (dimp_get(eDI_MP_bypass_post_state)) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- } else {/*i :*/
- ppre->madi_enable = (dimp_get(eDI_MP_pre_enable_mask) & 1);
- ppre->mcdi_enable =
- ((dimp_get(eDI_MP_pre_enable_mask) >> 1) & 1);
- di_buf->c.post_proc_flag = 1;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER,
- dimp_get(eDI_MP_mcpre_en));/*en*/
- }
-
- if ((ppre->di_mem_buf_dup_p == ppre->di_wr_buf) ||
- (ppre->di_chan2_buf_dup_p == ppre->di_wr_buf)) {
- PR_ERR("%s+++++++++++++++++++++++\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 12;
-
- recovery_flag++;
- return 0;
- }
-
- /**************************************/
- if (pdvfm) {
- pch = get_chdata(ch);
- ppre->dvfm = pdvfm;
- pdvfm->etype = EDIM_DISP_T_PRE;
- qued_ops.in(pch, QUED_T_PRE, pdvfm->index);
-
- di_buf->c.pdvfm = pdvfm; /*2019-12-03*/
- dimv3_print("%s:qued in\n", __func__);
- } else {
- PR_ERR("%s:no pdvfm\n", __func__);
- }
- return 1;
-}
-
-unsigned char dimv3_pre_de_buf_config(unsigned int ch)
-{
- PR_ERR("%s:ch[%d]\n", __func__, ch);
- #ifdef HIS_V3
- struct di_buf_s *di_buf = NULL;
- struct vframe_s *vframe;
- int i, di_linked_buf_idx = -1;
- unsigned char change_type = 0;
- unsigned char change_type2 = 0;
- /*bool bit10_pack_patch = false; move to dim_cfg_init*/
- /*unsigned int width_roundup = 2; move to dim_cfg_init*/
- struct vframe_s **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
-// struct di_post_stru_s *ppost = get_post_stru(ch);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- int cfg_prog_proc = dimp_get(eDI_MP_prog_proc_config);
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
- struct dim_dvfm_s *plstdvfm;// = &ppre->lst_dvfm;
-
- #ifdef HIS_V3
- if (di_blocking || !dipv3_cma_st_is_ready(ch))
- return 0;
-
- if (div3_que_list_count(ch, QUE_IN_FREE) < 1)
- return 0;
- #endif
- if ((div3_que_list_count(ch, QUE_IN_FREE) < 2 &&
- (!ppre->di_inp_buf_next)) ||
- (queuev3_empty(ch, QUEUE_LOCAL_FREE)))
- return 0;
-
- #ifdef HIS_V3
- if (div3_que_list_count(ch, QUE_PRE_READY) >= DI_PRE_READY_LIMIT)
- return 0;
- #endif
-/**************************************************************************/
- if (dim_is_bypass(NULL, ch)) {
- /*ary: */
- /* some provider has problem if receiver
- * get all buffers of provider
- */
- int in_buf_num = 0;
- /*cur_lev = 0;*/
- dimp_set(eDI_MP_cur_lev, 0);
- for (i = 0; i < MAX_IN_BUF_NUM; i++)
- if (pvframe_in[i])
- in_buf_num++;
- if (in_buf_num > BYPASS_GET_MAX_BUF_NUM)
- return 0;
-
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- } else if (ppre->prog_proc_type == 2) {
-
- #ifdef HIS_V3
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx == -1 &&
- !IS_ERR_OR_NULL(ppost->keep_buf)) { /*ary: ?*/
- recycle_keep_buffer(ch);
- PR_INF("%s: recycle keep buffer null buf\n",
- __func__);
- return 0;
- }
- #else
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx == -1) {
- dimv3_print("%s:check no link buf\n", __func__);
- return 0;
- }
- #endif
- }
-/**************************************************************************/
-/*p's second */
- if (ppre->di_inp_buf_next) {
- ppre->di_inp_buf = ppre->di_inp_buf_next;
- ppre->di_inp_buf_next = NULL;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s: di_inp_buf_next %s[%d] => di_inp_buf\n",
- __func__,
- vframe_type_name[ppre->di_inp_buf->type],
- ppre->di_inp_buf->index);
-#endif
- if (!ppre->di_mem_buf_dup_p) {/* use n */
- ppre->di_mem_buf_dup_p = ppre->di_inp_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to be di_inp_buf\n",
- __func__);
-#endif
- }
- } else {
-/*****************************************************************************/
-/*main proce */
- #ifdef HIS_V3
- /* check if source change */
- vframe = pw_vf_peek(channel);
-
- if (vframe && is_from_vdin(vframe)) {
-#ifdef RUN_DI_PROCESS_IN_IRQ
- ppre->vdin2nr = is_input2pre(channel);
-#endif
- }
-
- vframe = pw_vf_get(channel);
-
- if (!vframe)
- return 0;
- #else
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- plstdvfm = &pch->lst_dvfm;
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in) {
- PR_ERR("%s:no pdvfm\n", __func__);
- return 0;
- }
- vframe = pdvfm->vfm_in;
- #if 0
- /*recycle dvfm temp*/
- pdvfm->vfm_in = NULL;
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
-
- #endif
- #endif /*****************************************/
- dimv3_tr_ops.pre_get(vframe->omx_index);
- didbg_vframe_in_copy(ch, vframe);
- #ifdef HIS_V3 /*no use*/
- if (vframe->type & VIDTYPE_COMPRESS) {
- vframe->width = vframe->compWidth;
- vframe->height = vframe->compHeight;
- }
- #endif
- dimv3_print("DI:ch[%d]get %dth vf[0x%p] from frontend %u ms.\n",
- ch,
- ppre->in_seq, vframe,
- dim_get_timerms(vframe->ready_jiffies64));
-
- vframe->type = pdvfm->wmode.vtype;
- /*ary: no use?*/
- vframe->prog_proc_config
- = (cfg_prog_proc & 0x20) >> 5;
-
- #if 0 /*move to dvfm_fill_in*/
- if (vframe->width > 10000 || vframe->height > 10000 ||
- hold_video || ppre->bad_frame_throw_count > 0) {
- if (vframe->width > 10000 || vframe->height > 10000)
- ppre->bad_frame_throw_count = 10;
- ppre->bad_frame_throw_count--;
- pw_vf_put(vframe, channel);
- pw_vf_notify_provider(
- channel, VFRAME_EVENT_RECEIVER_PUT, NULL);
- return 0;
- }
- #endif
- #if 0 /*ary add cfgt and move to dvfm_fill_in*/
- bit10_pack_patch = (is_meson_gxtvbb_cpu() ||
- is_meson_gxl_cpu() ||
- is_meson_gxm_cpu());
- width_roundup = bit10_pack_patch ? 16 : width_roundup;
-
- if (dimp_get(eDI_MP_di_force_bit_mode) == 10) {
- if (dimp_get(eDI_MP_force_width)) {
- dimp_set(eDI_MP_force_width,
- roundup(dimp_get(eDI_MP_force_width),
- width_roundup));
- } else {
- dimp_set(eDI_MP_force_width,
- roundup(vframe->width,
- width_roundup));
- }
- }
- #endif
- ppre->source_trans_fmt = vframe->trans_fmt;
- ppre->left_right = ppre->left_right ? 0 : 1;
-
- #if 0
- ppre->invert_flag =
- (vframe->type & TB_DETECT_MASK) ? true : false;
- #else
- ppre->invert_flag = pdvfm->wmode.is_invert_tp;
- #endif
- vframe->type &= ~TB_DETECT_MASK;
-
- #if 0 /**/
- if ((((invert_top_bot & 0x2) != 0) ||
- ppre->invert_flag) &&
- (!is_progressive(vframe))) {
- if (
- (vframe->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP) {
- vframe->type &= (~VIDTYPE_TYPEMASK);
- vframe->type |= VIDTYPE_INTERLACE_BOTTOM;
- } else {
- vframe->type &= (~VIDTYPE_TYPEMASK);
- vframe->type |= VIDTYPE_INTERLACE_TOP;
- }
- }
- #else
-
- #endif
- ppre->width_bk = vframe->width;
- #if 0
- if (dimp_get(eDI_MP_force_width))
- vframe->width = dimp_get(eDI_MP_force_width);
- if (dimp_get(eDI_MP_force_height))
- vframe->height = dimp_get(eDI_MP_force_height);
- #else
- //vframe->width = pdvfm->wmode.w;
- //vframe->height = pdvfm->wmode.h;
- #endif
- /* backup frame motion info */
- vframe->combing_cur_lev = dimp_get(eDI_MP_cur_lev);/*cur_lev;*/
-
- dimv3_print("%s: vf_get => 0x%p\n", __func__, vframe);
-
- /*buf from IN_FREE*/
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch)) {
- PR_ERR("%s no IN_FREE\n", __func__);
- return 0;
- }
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_VFRAME)
- dimv3_dump_vframe(vframe);
- /*di_buf[in] set*/
- memcpy(di_buf->vframe, vframe, sizeof(vframe_t));
- dimv3_dbg_pre_cnt(ch, "cf1");
- di_buf->c.width_bk = ppre->width_bk; /*ary.sui 2019-04-23*/
- di_buf->vframe->private_data = di_buf;
- di_buf->vframe->width = pdvfm->wmode.src_w;
- di_buf->vframe->height = pdvfm->wmode.src_h;
- pvframe_in[di_buf->index] = vframe;
- di_buf->c.seq = ppre->in_seq;
- pdvfm->wmode.seq = ppre->in_seq;
- di_buf->c.wmode = pdvfm->wmode;
- ppre->in_seq++;
-
- prev3_vinfo_set(ch, &pdvfm->in_inf);
- change_type = isv3_source_change_dfvm(plstdvfm, pdvfm, ch);
- #if 0
- if (!change_type)
- change_type = isv3_vinfo_change(channel);
- #endif
- /********************************************************/
- /*source change*/
- /* source change, when i mix p,force p as i*/
- if (change_type == 1 ||
- (change_type == 2 && ppre->cur_prog_flag == 1)) {
- /*last is p £¿*/
- if (ppre->di_mem_buf_dup_p) {
- /*avoid only 2 i field then p field*/
- if (
- (ppre->cur_prog_flag == 0) &&
- dimp_get(eDI_MP_use_2_interlace_buff))
- ppre->di_mem_buf_dup_p->
- c.post_proc_flag = -1;
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- }
- if (ppre->di_chan2_buf_dup_p) {
- /*avoid only 1 i field then p field*/
- if (
- (ppre->cur_prog_flag == 0) &&
- dimp_get(eDI_MP_use_2_interlace_buff))
- ppre->di_chan2_buf_dup_p->
- c.post_proc_flag = -1;
- ppre->di_chan2_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_chan2_buf_dup_p = NULL;
- }
- #if 0
- /* channel change will occur between atv and dtv,
- * that need mirror
- */
- if (!IS_ERR_OR_NULL(di_post_stru.keep_buf)) {
- if (di_post_stru.keep_buf->vframe
- ->source_type !=
- di_buf->vframe->source_type) {
- recycle_keep_buffer();
- pr_info("%s: source type changed recycle buffer!!!\n",
- __func__);
- }
- }
- #endif
- PR_INF(
- "%s:ch[%d]:%ums %dth source change: 0x%x/%d/%d/%d=>0x%x/%d/%d/%d\n",
- __func__,
- ch,
- dim_get_timerms(0),
- ppre->in_seq,
- plstdvfm->in_inf.vtype_ori,
- plstdvfm->in_inf.w,
- plstdvfm->in_inf.h,
- plstdvfm->in_inf.src_type,
- pdvfm->in_inf.vtype_ori,
- pdvfm->in_inf.w,
- pdvfm->in_inf.h,
- pdvfm->in_inf.src_type);
- #if 0 /*no use*/
- if (di_buf->type & VIDTYPE_COMPRESS) {
- ppre->cur_width =
- di_buf->vframe->compWidth;
- ppre->cur_height =
- di_buf->vframe->compHeight;
- } else {
- ppre->cur_width = di_buf->vframe->width;
- ppre->cur_height = di_buf->vframe->height;
- }
- #else
- ppre->cur_width = pdvfm->in_inf.w;
- ppre->cur_height = pdvfm->in_inf.h;
- #endif
- ppre->cur_prog_flag = !pdvfm->wmode.is_i;
- //is_progressive(di_buf->vframe);
- if (ppre->cur_prog_flag) {
- if ((dimp_get(eDI_MP_use_2_interlace_buff)) &&
- !(cfg_prog_proc & 0x10))
- ppre->prog_proc_type = 2;
- /*now:cfg_prog_proc is 0x23*/
- else
- ppre->prog_proc_type /*p as i is 0*/
- = cfg_prog_proc & 0x10;
- } else {
- ppre->prog_proc_type = 0;
- }
- #if 0
- ppre->cur_inp_type = di_buf->vframe->type;
- ppre->cur_source_type =
- di_buf->vframe->source_type;
- ppre->cur_sig_fmt = di_buf->vframe->sig_fmt;
- ppre->orientation = di_buf->vframe->video_angle;
- #else
- ppre->cur_source_type = pdvfm->in_inf.src_type;
- ppre->cur_sig_fmt = pdvfm->in_inf.sig_fmt;
- ppre->orientation = pdvfm->wmode.is_angle;
- #endif
- ppre->source_change_flag = 1;
- ppre->input_size_change_flag = true;
-
- ppre->field_count = 0;
- /*source change end*/
- /********************************************************/
- } else if (ppre->cur_prog_flag == 0) {
- /* check if top/bot interleaved */
- if (change_type == 2)
- /* source is i interleaves p fields */
- ppre->force_interlace = true;
- if ((ppre->cur_inp_type &
- VIDTYPE_TYPEMASK) == (di_buf->vframe->type &
- VIDTYPE_TYPEMASK)) {
- if ((di_buf->vframe->type &
- VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP)
- same_field_top_count++;
- else
- same_field_bot_count++;
- }
- }
- ppre->cur_inp_type = pdvfm->in_inf.vtype_ori;
- dimv3_set_pre_dfvm(plstdvfm, pdvfm);
- /********************************************************/
- if (!change_type) {
- change_type2 = isv3_vinfo_change(ch);
- if (change_type2) {
- /*ppre->source_change_flag = 1;*/
- ppre->input_size_change_flag = true;
- }
- }
-
- /********************************************************/
- if (dim_is_bypass(di_buf->vframe, ch)
- /*|| is_bypass_i_p()*/
- /*|| ((ppre->pre_ready_seq % 5)== 0)*/
- /*|| (ppre->pre_ready_seq == 10)*/
- ) {
- /********************************************************/
- /*is bypass*/
- /* bypass progressive */
- di_buf->c.seq = ppre->pre_ready_seq++;
- di_buf->c.post_ref_count = 0;
- /*cur_lev = 0;*/
- dimp_set(eDI_MP_cur_lev, 0);
- if (ppre->source_change_flag) {
- di_buf->c.new_format_flag = 1;
- ppre->source_change_flag = 0;
- } else {
- di_buf->c.new_format_flag = 0;
- }
-
- if (di_bypass_state_get(ch) == 0) {
- if (ppre->di_mem_buf_dup_p) {
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- }
- if (ppre->di_chan2_buf_dup_p) {
- ppre->di_chan2_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_chan2_buf_dup_p = NULL;
- }
-
- if (ppre->di_wr_buf) {
- ppre->di_wr_buf->c.pre_ref_count = 0;
- ppre->di_wr_buf->c.post_ref_count = 0;
- recycle_vframe_type_pre(
- ppre->di_wr_buf, ch);
-
- ppre->di_wr_buf = NULL;
- }
-
- di_buf->c.new_format_flag = 1;
- di_bypass_state_set(ch, true);/*bypass_state:1;*/
-
- dimv3_print(
- "%s:bypass_state = 1, is_bypass() %d\n",
- __func__, dim_is_bypass(NULL, ch));
-
- }
- /*di_bypass_state_get(channel) == 0 end*/
- /***************************************/
- //top_bot_config(di_buf);
- //di_buf->vframe.type = pdvfm->in_inf.vtype;
-
- div3_que_in(ch, QUE_PRE_READY, di_buf);
-
-
- if ((bypass_pre & 0x2) && !ppre->cur_prog_flag)
- di_buf->c.post_proc_flag = -2;
- else
- di_buf->c.post_proc_flag = 0;
-
- dimv3_print("di:cfg:post_proc_flag=%d\n",
- di_buf->c.post_proc_flag);
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: %s[%d] => pre_ready_list\n", __func__,
- vframe_type_name[di_buf->type], di_buf->index);
-#endif
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- dimv3_print("%s is bypass\n", __func__);
- return 0;
- /*is bypass end*/
- /********************************************************/
- /*is proc*/
- } else if (is_progressive(di_buf->vframe)) {
- if (is_handle_prog_frame_as_interlace(vframe) &&
- is_progressive(vframe)) {
- /*proc p as i*/
- struct di_buf_s *di_buf_tmp = NULL;
-
- pvframe_in[di_buf->index] = NULL;
- di_buf->vframe->type &=
- (~VIDTYPE_TYPEMASK);
- di_buf->vframe->type |=
- VIDTYPE_INTERLACE_TOP;
- di_buf->c.post_proc_flag = 0;
-
- di_buf_tmp = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
- if (dimv3_check_di_buf(di_buf_tmp, 10, ch)) {
- recycle_vframe_type_pre(di_buf, ch);
- PR_ERR("%s:DI:no IN_FREE for prog skip.\n", __func__);
- return 0;
- }
-
- di_buf_tmp->vframe->private_data = di_buf_tmp;
- di_buf_tmp->c.seq = ppre->in_seq;
- ppre->in_seq++;
- pvframe_in[di_buf_tmp->index] = vframe;
- memcpy(di_buf_tmp->vframe, vframe,
- sizeof(vframe_t));
- ppre->di_inp_buf_next = di_buf_tmp;
- di_buf_tmp->c.wmode = di_buf->c.wmode;
- di_buf_tmp->vframe->type &=
- (~VIDTYPE_TYPEMASK);
- di_buf_tmp->vframe->type |=
- VIDTYPE_INTERLACE_BOTTOM;
- di_buf_tmp->c.post_proc_flag = 0;
-
- ppre->di_inp_buf = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: %s[%d] => di_inp_buf; %s[%d] => di_inp_buf_next\n",
- __func__,
- vframe_type_name[di_buf->type],
- di_buf->index,
- vframe_type_name[di_buf_tmp->type],
- di_buf_tmp->index);
-#endif
- if (!ppre->di_mem_buf_dup_p) {
- ppre->di_mem_buf_dup_p = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to be di_inp_buf\n",
- __func__);
-#endif
- }
- /*proc p as i end */
- /*******************/
- } else {/*ary: not process prog as i*/
- di_buf->c.post_proc_flag = 0;
- if ((cfg_prog_proc & 0x40) ||
- ppre->force_interlace)
- di_buf->c.post_proc_flag = 1;
-
- ppre->di_inp_buf = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: %s[%d] => di_inp_buf\n",
- __func__,
- vframe_type_name[di_buf->type],
- di_buf->index);
-#endif
- if (!ppre->di_mem_buf_dup_p) {
- /* use n */
- ppre->di_mem_buf_dup_p = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to be di_inp_buf\n",
- __func__);
-#endif
- }
- }
- /*is proc end*/
- /********************************************************/
- } else {
- /********************************************************/
- #if 0
- /* is other : not bypass, not proce*/
- if ((di_buf->vframe->width >= 1920) &&
- (di_buf->vframe->height >= 1080) &&
- is_meson_tl1_cpu()) {
- /*if (combing_fix_en) {*/
- if (dimp_get(eDI_MP_combing_fix_en)) {
- /*combing_fix_en = false;*/
- dimp_set(eDI_MP_combing_fix_en, 0);
- get_ops_mtn()->fix_tl1_1080i_sawtooth_patch();
- }
- } else {
- /*combing_fix_en = true;*/
- dimp_set(eDI_MP_combing_fix_en, 1);
- }
- #endif
- /*********************************/
- if (!ppre->di_chan2_buf_dup_p) {
- ppre->field_count = 0;
- /* ignore contp2rd and contprd */
- }
- di_buf->c.post_proc_flag = 1;
- ppre->di_inp_buf = di_buf;
- dimv3_print("%s: %s[%d] => di_inp_buf\n", __func__,
- vframe_type_name[di_buf->type],
- di_buf->index);
-
- if (!ppre->di_mem_buf_dup_p) {/* use n */
- ppre->di_mem_buf_dup_p = di_buf;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s: set di_mem_buf_dup_p to be di_inp_buf\n",
- __func__);
-#endif
- }
- }
- /*other end*/
- /********************************************************/
-/*main proc end*/
-/*****************************************************************************/
- }
- /*dim_dbg_pre_cnt(channel, "cfg");*/
- /* di_wr_buf */
- if (ppre->prog_proc_type == 2) {
- di_linked_buf_idx = peek_free_linked_buf(ch);
- if (di_linked_buf_idx != -1)
- di_buf = get_free_linked_buf(di_linked_buf_idx,
- ch);
- else
- di_buf = NULL;
- if (!di_buf) {
- /* recycle_vframe_type_pre(di_pre_stru.di_inp_buf);
- *save for next process
- */
- recycle_keep_buffer(ch);
- ppre->di_inp_buf_next = ppre->di_inp_buf;
- PR_ERR("%s no link local buf\n", __func__);
- return 0;
- }
- di_buf->c.post_proc_flag = 0;
- di_buf->c.di_wr_linked_buf->c.pre_ref_count = 0;
- di_buf->c.di_wr_linked_buf->c.post_ref_count = 0;
- di_buf->c.canvas_config_flag = 1;
- } else {
- /*di_buf[local]*/
- di_buf = getv3_di_buf_head(ch, QUEUE_LOCAL_FREE);
- if (dimv3_check_di_buf(di_buf, 11, ch)) {
- /* recycle_keep_buffer();
- * pr_dbg("%s:recycle keep buffer\n", __func__);
- */
- recycle_vframe_type_pre(ppre->di_inp_buf, ch);
- PR_ERR("%s no local free\n", __func__);
- return 0;
- }
- queuev3_out(ch, di_buf);/*QUEUE_LOCAL_FREE*/
- if (ppre->prog_proc_type & 0x10)
- di_buf->c.canvas_config_flag = 1;
- else
- di_buf->c.canvas_config_flag = 2;
- di_buf->c.di_wr_linked_buf = NULL;
- di_buf->c.sts |= EDI_ST_PRE;
- }
-
- ppre->di_wr_buf = di_buf;
- ppre->di_wr_buf->c.pre_ref_count = 1;
-
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s: %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->type], di_buf->index);
- if (di_buf->c.di_wr_linked_buf)
- dimv3_print("%s: linked %s[%d] => di_wr_buf\n", __func__,
- vframe_type_name[di_buf->c.di_wr_linked_buf->type],
- di_buf->c.di_wr_linked_buf->index);
-#endif
- if (ppre->cur_inp_type & VIDTYPE_COMPRESS) {
- ppre->di_inp_buf->vframe->width =
- ppre->di_inp_buf->vframe->compWidth;
- ppre->di_inp_buf->vframe->height =
- ppre->di_inp_buf->vframe->compHeight;
- }
- /*di_buf[local]*/
- if (!di_buf)
- PR_ERR("%s:err1\n", __func__);
- if (!di_buf->vframe)
- PR_ERR("%s:err2\n", __func__);
- if (!ppre->di_inp_buf)
- PR_ERR("%s:err3\n", __func__);
- if (!ppre->di_inp_buf->vframe)
- PR_ERR("%s:err4\n", __func__);
- memcpy(di_buf->vframe,
- ppre->di_inp_buf->vframe, sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- di_buf->c.wmode = ppre->di_inp_buf->c.wmode;
-
- #if 0 /*no use*/
- di_buf->vframe->canvas0Addr = di_buf->nr_canvas_idx;
- di_buf->vframe->canvas1Addr = di_buf->nr_canvas_idx;
- #endif
- /* set vframe bit info */
- di_buf->vframe->bitdepth &= ~(BITDEPTH_YMASK);
- di_buf->vframe->bitdepth &= ~(FULL_PACK_422_MODE);
-
- /*pp scaler*/
- if (de_devp->pps_enable && dimp_get(eDI_MP_pps_position)) {
- if (dimp_get(eDI_MP_pps_dstw) != di_buf->vframe->width) {
- di_buf->vframe->width = dimp_get(eDI_MP_pps_dstw);
- ppre->width_bk = dimp_get(eDI_MP_pps_dstw);
- }
- if (dimp_get(eDI_MP_pps_dsth) != di_buf->vframe->height)
- di_buf->vframe->height = dimp_get(eDI_MP_pps_dsth);
- } else if (de_devp->h_sc_down_en) {
- if (dimp_get(eDI_MP_pre_hsc_down_width)
- != di_buf->vframe->width) {
- PR_INF("hscd %d to %d\n", di_buf->vframe->width,
- dimp_get(eDI_MP_pre_hsc_down_width));
- di_buf->vframe->width =
- dimp_get(eDI_MP_pre_hsc_down_width);
- /*di_pre_stru.width_bk = pre_hsc_down_width;*/
- di_buf->c.width_bk =
- dimp_get(eDI_MP_pre_hsc_down_width);
- }
- }
- /**/
- if (dimp_get(eDI_MP_di_force_bit_mode) == 10) {
- di_buf->vframe->bitdepth |= (BITDEPTH_Y10);
- if (dimp_get(eDI_MP_full_422_pack))
- di_buf->vframe->bitdepth |= (FULL_PACK_422_MODE);
- } else {
- di_buf->vframe->bitdepth |= (BITDEPTH_Y8);
- }
-
- di_buf->c.width_bk = ppre->width_bk; /*ary:2019-04-23*/
-
- if (ppre->prog_proc_type) {
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- if (ppre->cur_inp_type & VIDTYPE_PRE_INTERLACE)
- di_buf->vframe->type |= VIDTYPE_PRE_INTERLACE;
- } else {
- /*i mode: or pasi*/
- if (
- ((ppre->di_inp_buf->vframe->type &
- VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP))
- di_buf->vframe->type = VIDTYPE_INTERLACE_TOP |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- else
- di_buf->vframe->type = VIDTYPE_INTERLACE_BOTTOM |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- /*add for vpp skip line ref*/
- if (di_bypass_state_get(ch) == 0)
- di_buf->vframe->type |= VIDTYPE_PRE_INTERLACE;
- }
-
- if (is_bypass_post(ch)) {
- if (dimp_get(eDI_MP_bypass_post_state) == 0)
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 1);
- } else {
- if (dimp_get(eDI_MP_bypass_post_state))
- ppre->source_change_flag = 1;
-
- dimp_set(eDI_MP_bypass_post_state, 0);
- }
-
- if (ppre->di_inp_buf->c.post_proc_flag == 0) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- } else if (dimp_get(eDI_MP_bypass_post_state)) {
- ppre->madi_enable = 0;
- ppre->mcdi_enable = 0;
- di_buf->c.post_proc_flag = 0;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- } else {
- ppre->madi_enable = (dimp_get(eDI_MP_pre_enable_mask) & 1);
- ppre->mcdi_enable =
- ((dimp_get(eDI_MP_pre_enable_mask) >> 1) & 1);
- di_buf->c.post_proc_flag = 1;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER,
- dimp_get(eDI_MP_mcpre_en));/*en*/
- }
-
- if ((ppre->di_mem_buf_dup_p == ppre->di_wr_buf) ||
- (ppre->di_chan2_buf_dup_p == ppre->di_wr_buf)) {
- PR_ERR("%s+++++++++++++++++++++++\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 12;
-
- recovery_flag++;
- return 0;
- }
-
- /**************************************/
- if (pdvfm) {
- pch = get_chdata(ch);
- ppre->dvfm = pdvfm;
- pdvfm->etype = EDIM_DISP_T_PRE;
- qued_ops.in(pch, QUED_T_PRE, pdvfm->index);
- dimv3_print("%s:qued in\n", __func__);
- } else {
- PR_ERR("%s:no pdvfm\n", __func__);
- }
- #endif
- return 1;
-}
-
-unsigned char dim_pre_de_buf_config_top(unsigned int ch)
-{
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm = NULL;
- unsigned char ret;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- bool flg_1080i = false;
- bool flg_480i = false;
-
- if (di_blocking || !dipv3_cma_st_is_ready(ch))
- return 0;
-
- if (div3_que_list_count(ch, QUE_IN_FREE) < 1)
- return 0;
-
- if ((queuev3_empty(ch, QUEUE_LOCAL_FREE)))
- return 0;
-
- if (div3_que_list_count(ch, QUE_PRE_READY) >= DI_PRE_READY_LIMIT)
- return 0;
-
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- if (!pdvfm)
- return 0;
- if (pdvfm->wmode.p_use_2i)
- ret = dim_pre_de_buf_config_p_use_2ibuf(ch);
- else if (pdvfm->wmode.is_i)
- ret = dim_pre_de_buf_config_i(ch);
- else
- ret = dimv3_pre_de_buf_config(ch);
-
- /*mtn*/
- if (pdvfm->wmode.is_i) {
- if ((pdvfm->in_inf.w >= 1920) &&
- (pdvfm->in_inf.h >= 1080))
- flg_1080i = true;
- else if ((pdvfm->in_inf.w == 720) &&
- (pdvfm->in_inf.h == 480))
- flg_480i = true;
- }
- if (is_meson_tl1_cpu() &&
- //ppre->comb_mode &&
- flg_1080i) {
- ppre->combing_fix_en = false;
- get_ops_mtn()->fix_tl1_1080i_patch_sel(ppre->comb_mode);
- } else {
- ppre->combing_fix_en = di_mpr(combing_fix_en);
- }
-
- if (ppre->combing_fix_en) {
- if (flg_1080i)
- get_ops_mtn()->com_patch_pre_sw_set(1);
- else if (flg_480i)
- get_ops_mtn()->com_patch_pre_sw_set(2);
- else
- get_ops_mtn()->com_patch_pre_sw_set(0);
- }
-
- return ret;
-}
-/******************************************
- * clear buf
- ******************************************/
-void dimv3_buf_clean(struct di_buf_s *di_buf)
-{
-// int i;
- if (!di_buf)
- return;
- memset(&di_buf->c, 0, sizeof(struct di_buf_c_s));
-}
-
-int dimv3_check_recycle_buf(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;/* , *ptmp; */
- struct di_buf_s *di_buf_link = NULL;
- int itmp;
- int ret = 0;
- void **pvframe_in = getv3_vframe_in(ch);
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_ch_s *pch;
- struct dim_itf_ops_s *pvfmops;
-
- if (di_blocking)
- return ret;
- pch = get_chdata(ch);
- pvfmops = &pch->interf.opsi;
- queue_for_each_entry(di_buf, ch, QUEUE_RECYCLE, list) {
- if (di_buf->c.pre_ref_count ||
- di_buf->c.post_ref_count > 0)
- continue;
-
- /*ary maybe <= */
- if (di_buf->type == VFRAME_TYPE_IN) {
- queuev3_out(ch, di_buf);
- if (pvframe_in[di_buf->index]) {
- //pw_vf_put(pvframe_in[di_buf->index], ch);
- //pw_vf_notify_provider(ch,
- // VFRAME_EVENT_RECEIVER_PUT,
- // NULL);
- pvfmops->put(pvframe_in[di_buf->index], pch);
-
- dimv3_print("%s\n", __func__);
- dimv3_print("ch[%d],vf_put(%d) %p, %u ms\n",
- ch,
- ppre->recycle_seq,
- pvframe_in[di_buf->index],
- dim_get_timerms(0));
- pvframe_in[di_buf->index] = NULL;
- }
- //di_buf->c.invert_top_bot_flag = 0;
- dimv3_buf_clean(di_buf);
-
- div3_que_in(ch, QUE_IN_FREE, di_buf);
- ppre->recycle_seq++;
- ret |= 1;
- } else {
- queuev3_out(ch, di_buf);
- di_buf->c.invert_top_bot_flag = 0;
-
- queuev3_in(ch, di_buf, QUEUE_LOCAL_FREE);
- di_buf->c.post_ref_count = 0;/*ary maybe*/
- if (di_buf->c.di_wr_linked_buf) {
- di_buf_link = di_buf->c.di_wr_linked_buf;
- queuev3_in(ch, di_buf_link, QUEUE_LOCAL_FREE);
-
- dimv3_print(
- "%s: linked %s[%d]=>recycle_list\n",
- __func__,
- vframe_type_name[di_buf_link->type],
- di_buf_link->index
- );
-
- di_buf->c.di_wr_linked_buf = NULL;
- dimv3_buf_clean(di_buf_link);
- }
- dimv3_buf_clean(di_buf);
- ret |= 2;
- }
- dimv3_print("%s: recycle %s[%d]\n", __func__,
- vframe_type_name[di_buf->type],
- di_buf->index);
- }
-
- return ret;
-}
-
-#ifdef DET3D
-static void set3d_view(enum tvin_trans_fmt trans_fmt, struct vframe_s *vf)
-{
- struct vframe_view_s *left_eye, *right_eye;
-
- left_eye = &vf->left_eye;
- right_eye = &vf->right_eye;
-
- switch (trans_fmt) {
- case TVIN_TFMT_3D_DET_LR:
- case TVIN_TFMT_3D_LRH_OLOR:
- left_eye->start_x = 0;
- left_eye->start_y = 0;
- left_eye->width = vf->width >> 1;
- left_eye->height = vf->height;
- right_eye->start_x = vf->width >> 1;
- right_eye->start_y = 0;
- right_eye->width = vf->width >> 1;
- right_eye->height = vf->height;
- break;
- case TVIN_TFMT_3D_DET_TB:
- case TVIN_TFMT_3D_TB:
- left_eye->start_x = 0;
- left_eye->start_y = 0;
- left_eye->width = vf->width;
- left_eye->height = vf->height >> 1;
- right_eye->start_x = 0;
- right_eye->start_y = vf->height >> 1;
- right_eye->width = vf->width;
- right_eye->height = vf->height >> 1;
- break;
- case TVIN_TFMT_3D_DET_INTERLACE:
- left_eye->start_x = 0;
- left_eye->start_y = 0;
- left_eye->width = vf->width;
- left_eye->height = vf->height >> 1;
- right_eye->start_x = 0;
- right_eye->start_y = 0;
- right_eye->width = vf->width;
- right_eye->height = vf->height >> 1;
- break;
- case TVIN_TFMT_3D_DET_CHESSBOARD:
-/***
- * LRLRLR LRLRLR
- * LRLRLR or RLRLRL
- * LRLRLR LRLRLR
- * LRLRLR RLRLRL
- */
- break;
- default: /* 2D */
- left_eye->start_x = 0;
- left_eye->start_y = 0;
- left_eye->width = 0;
- left_eye->height = 0;
- right_eye->start_x = 0;
- right_eye->start_y = 0;
- right_eye->width = 0;
- right_eye->height = 0;
- break;
- }
-}
-
-/*
- * static int get_3d_info(struct vframe_s *vf)
- * {
- * int ret = 0;
- *
- * vf->trans_fmt = det3d_fmt_detect();
- * pr_dbg("[det3d..]new 3d fmt: %d\n", vf->trans_fmt);
- *
- * vdin_set_view(vf->trans_fmt, vf);
- *
- * return ret;
- * }
- */
-static unsigned int det3d_frame_cnt = 50;
-module_param_named(det3d_frame_cnt, det3d_frame_cnt, uint, 0644);
-static void det3d_irq(unsigned int channel)
-{
- unsigned int data32 = 0, likely_val = 0;
- unsigned long frame_sum = 0;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (!dimp_get(eDI_MP_det3d_en))
- return;
-
- data32 = get_ops_3d()->det3d_fmt_detect();/*det3d_fmt_detect();*/
- switch (data32) {
- case TVIN_TFMT_3D_DET_LR:
- case TVIN_TFMT_3D_LRH_OLOR:
- ppre->det_lr++;
- break;
- case TVIN_TFMT_3D_DET_TB:
- case TVIN_TFMT_3D_TB:
- ppre->det_tp++;
- break;
- case TVIN_TFMT_3D_DET_INTERLACE:
- ppre->det_la++;
- break;
- default:
- ppre->det_null++;
- break;
- }
-
- if (det3d_mode != data32) {
- det3d_mode = data32;
- dimv3_print("[det3d..]new 3d fmt: %d\n", det3d_mode);
- }
- if (frame_count > 20) {
- frame_sum = ppre->det_lr + ppre->det_tp
- + ppre->det_la
- + ppre->det_null;
- if ((frame_count % det3d_frame_cnt) || (frame_sum > UINT_MAX))
- return;
- likely_val = max3(ppre->det_lr,
- ppre->det_tp,
- ppre->det_la);
- if (ppre->det_null >= likely_val)
- det3d_mode = 0;
- else if (likely_val == ppre->det_lr)
- det3d_mode = TVIN_TFMT_3D_LRH_OLOR;
- else if (likely_val == ppre->det_tp)
- det3d_mode = TVIN_TFMT_3D_TB;
- else
- det3d_mode = TVIN_TFMT_3D_DET_INTERLACE;
- ppre->det3d_trans_fmt = det3d_mode;
- } else {
- ppre->det3d_trans_fmt = 0;
- }
-}
-#endif
-
-static unsigned int ro_mcdi_col_cfd[26];
-static void get_mcinfo_from_reg_in_irq(unsigned int channel)
-{
- unsigned int i = 0, ncolcrefsum = 0, blkcount = 0, *reg = NULL;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct mcinfo_pre_s *pmcinfo;
-
- pmcinfo = &ppre->di_wr_buf->c.curr_field_mcinfo;
-/*get info for current field process by post*/
- pmcinfo->highvertfrqflg =
- (Rd(MCDI_RO_HIGH_VERT_FRQ_FLG) & 0x1);
-/* post:MCDI_MC_REL_GAIN_OFFST_0 */
- pmcinfo->motionparadoxflg =
- (Rd(MCDI_RO_MOTION_PARADOX_FLG) & 0x1);
-/* post:MCDI_MC_REL_GAIN_OFFST_0 */
- reg = pmcinfo->regs;
- for (i = 0; i < 26; i++) {
- ro_mcdi_col_cfd[i] = Rd(0x2fb0 + i);
- pmcinfo->regs[i] = 0;
- if (!dimp_get(eDI_MP_calc_mcinfo_en))
- *(reg + i) = ro_mcdi_col_cfd[i];
- }
- if (dimp_get(eDI_MP_calc_mcinfo_en)) {
- blkcount = (ppre->cur_width + 4) / 5;
- for (i = 0; i < blkcount; i++) {
- ncolcrefsum +=
- ((ro_mcdi_col_cfd[i / 32] >> (i % 32)) & 0x1);
- if (
- ((ncolcrefsum + (blkcount >> 1)) << 8) /
- blkcount > dimp_get(eDI_MP_colcfd_thr))
- for (i = 0; i < blkcount; i++)
- *(reg + i / 32) += (1 << (i % 32));
- }
- }
-}
-
-static unsigned int bit_reverse(unsigned int val)
-{
- unsigned int i = 0, res = 0;
-
- for (i = 0; i < 16; i++) {
- res |= (((val & (1 << i)) >> i) << (31 - i));
- res |= (((val & (1 << (31 - i))) << i) >> (31 - i));
- }
- return res;
-}
-
-static void set_post_mcinfo(struct mcinfo_pre_s *curr_field_mcinfo)
-{
- unsigned int i = 0, value = 0;
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_REL_GAIN_OFFST_0,
- curr_field_mcinfo->highvertfrqflg, 24, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_REL_GAIN_OFFST_0,
- curr_field_mcinfo->motionparadoxflg, 25, 1);
- for (i = 0; i < 26; i++) {
- if (overturn)
- value = bit_reverse(curr_field_mcinfo->regs[i]);
- else
- value = curr_field_mcinfo->regs[i];
- dimv3_VSYNC_WR_MPEG_REG(0x2f78 + i, value);
- }
-}
-
-static unsigned char intr_mode;
-
-irqreturn_t dimv3_irq(int irq, void *dev_instance)
-{
- unsigned int channel;
- struct di_pre_stru_s *ppre;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- struct di_hpre_s *pre = get_hw_pre();
-
-#ifndef CHECK_DI_DONE
- unsigned int data32;
- unsigned int mask32;
- unsigned int flag = 0;
-
-
- data32 = Rd(DI_INTR_CTRL);
- mask32 = (data32 >> 16) & 0x3ff;
-
- channel = pre->curr_ch;
- ppre = pre->pres;
-
- data32 &= 0x3fffffff;
- if ((data32 & 1) == 0 && dimp_get(eDI_MP_di_dbg_mask) & 8)
- PR_INF("irq[%d]pre|post=0 write done.\n", irq);
- if (ppre->pre_de_busy) {
- /* only one inetrrupr mask should be enable */
- if ((data32 & 2) && !(mask32 & 2)) {
- dimv3_print("irq pre MTNWR ==ch[%d]\n", channel);
- flag = 1;
- } else if ((data32 & 1) && !(mask32 & 1)) {
- dimv3_print("irq pre NRWR ==ch[%d]\n", channel);
- flag = 1;
- } else {
- dimv3_print("irq pre DI IRQ 0x%x ==\n", data32);
- flag = 0;
- }
- }
-
-#else
- channel = pre->curr_ch;
- ppre = pre->pres;
-#endif
-
-#ifdef DET3D
- if (dimp_get(eDI_MP_det3d_en)) {
- if ((data32 & 0x100) && !(mask32 & 0x100) && flag) {
- dimv3_DI_Wr(DI_INTR_CTRL, data32);
- det3d_irq(channel);
- } else {
- goto end;
- }
- } else {
- dimv3_DI_Wr(DI_INTR_CTRL, data32);
- }
-#else
- if (flag) {
- hprev3_gl_sw(false);
- dimv3_DI_Wr(DI_INTR_CTRL,
- (data32 & 0xfffffffb) | (intr_mode << 30));
- }
-#endif
-
- /*if (ppre->pre_de_busy == 0) {*/
- if (!di_pre_wait_irq_get()) {
- PR_ERR("%s:ch[%d]:enter:reg[0x%x]= 0x%x,dtab[%d]\n", __func__,
- channel,
- DI_INTR_CTRL,
- Rd(DI_INTR_CTRL),
- pre->sdt_mode.op_crr);
- return IRQ_HANDLED;
- }
-
- if (flag) {
- ppre->irq_time[0] =
- (curv3_to_msecs() - ppre->irq_time[0]);
-
- dimv3_tr_ops.pre(ppre->field_count, ppre->irq_time[0]);
- dimv3_tr_ops.pre_ready(ppre->di_wr_buf->c.vmode.omx_index);
-
- /*add from valsi wang.feng*/
- dimv3_arb_sw(false);
- dimv3_arb_sw(true);
- if (dimp_get(eDI_MP_mcpre_en)) {
- get_mcinfo_from_reg_in_irq(channel);
- if ((is_meson_gxlx_cpu() &&
- ppre->field_count >= 4) ||
- is_meson_txhd_cpu())
- dimhv3_mc_pre_mv_irq();
- dimhv3_calc_lmv_base_mcinfo((ppre->cur_height >> 1),
- ppre->di_wr_buf->mcinfo_adr_v,
- /*ppre->mcinfo_size*/0);
- }
- get_ops_nr()->nr_process_in_irq();
- if ((data32 & 0x200) && de_devp->nrds_enable)
- dimv3_nr_ds_irq();
- /* disable mif */
- dimhv3_enable_di_pre_mif(false, dimp_get(eDI_MP_mcpre_en));
-
- ppre->pre_de_busy = 0;
-
- if (get_init_flag(channel))
- /* pr_dbg("%s:up di sema\n", __func__); */
- taskv3_send_ready();
-
- pre->flg_int_done = 1;
- }
-
- return IRQ_HANDLED;
-}
-
-irqreturn_t dimv3_post_irq(int irq, void *dev_instance)
-{
- unsigned int data32 = Rd(DI_INTR_CTRL);
- unsigned int channel;
- struct di_post_stru_s *ppost;
- struct di_hpst_s *pst = get_hw_pst();
-
- channel = pst->curr_ch;
- ppost = pst->psts;
-
- data32 &= 0x3fffffff;
- if ((data32 & 4) == 0) {
- if (dimp_get(eDI_MP_di_dbg_mask) & 8)
- PR_INF("irq[%d]post write undone.\n", irq);
- return IRQ_HANDLED;
- }
-
- if (pst->state != eDI_PST_ST_WAIT_INT &&
- pst->state != eDI_PST_ST_SET) {
- PR_ERR("%s:ch[%d]:s[%d]\n", __func__, channel, pst->state);
- ddbgv3_sw(eDI_LOG_TYPE_MOD, false);
- return IRQ_HANDLED;
- }
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_IRQB, pst->curr_ch,
- ppost->frame_cnt);
- dimv3_tr_ops.post_ir(0);
-
- if ((dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) &&
- (data32 & 0x4)) {
- ppost->de_post_process_done = 1;
- ppost->post_de_busy = 0;
- ppost->irq_time =
- (curv3_to_msecs() - ppost->irq_time);
-
- dimv3_tr_ops.post(ppost->post_wr_cnt, ppost->irq_time);
-
- dimv3_DI_Wr(DI_INTR_CTRL,
- (data32 & 0xffff0004) | (intr_mode << 30));
- /* disable wr back avoid pps sreay in g12a */
- dimv3_DI_Wr_reg_bits(DI_POST_CTRL, 0, 7, 1);
- div3_post_set_flow(1, eDI_POST_FLOW_STEP1_STOP); /*dbg a*/
- dimv3_print("irq p ch[%d]done\n", channel);
- pst->flg_int_done = true;
- }
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_IRQE, pst->curr_ch,
- ppost->frame_cnt);
-
- if (get_init_flag(channel))
- taskv3_send_ready();
-
- return IRQ_HANDLED;
-}
-
-/*
- * di post process
- */
-static void inc_post_ref_count(struct di_buf_s *di_buf)
-{
- int i; /*debug only:*/
- struct di_buf_s *pbuf_dup;/*debug only:*/
-
- /* int post_blend_mode; */
- if (IS_ERR_OR_NULL(di_buf)) {
- PR_ERR("%s:\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 13;
-
- recovery_flag++;
- return;
- }
-
- if (di_buf->c.di_buf_dup_p[1])
- di_buf->c.di_buf_dup_p[1]->c.post_ref_count++;
-
- if (di_buf->c.di_buf_dup_p[0])
- di_buf->c.di_buf_dup_p[0]->c.post_ref_count++;
-
- if (di_buf->c.di_buf_dup_p[2])
- di_buf->c.di_buf_dup_p[2]->c.post_ref_count++;
-
- /*debug only:*/
- for (i = 0; i < 3; i++) {
- pbuf_dup = di_buf->c.di_buf_dup_p[i];
- if (pbuf_dup)
- dbg_post_ref("%s:pst_buf[%d],dup_p[%d],pref[%d]\n",
- __func__,
- di_buf->index,
- i,
- pbuf_dup->c.post_ref_count);
- }
-}
-
-static void dec_post_ref_count(struct di_buf_s *di_buf)
-{
- int i; /*debug only:*/
- struct di_buf_s *pbuf_dup;/*debug only:*/
-
- if (IS_ERR_OR_NULL(di_buf)) {
- PR_ERR("%s:\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 14;
-
- recovery_flag++;
- return;
- }
-
- if (di_buf->c.pd_config.global_mode == PULL_DOWN_BUF1)
- return;
- if (di_buf->c.di_buf_dup_p[1])
- di_buf->c.di_buf_dup_p[1]->c.post_ref_count--;
-
- if (di_buf->c.di_buf_dup_p[0] &&
- di_buf->c.di_buf_dup_p[0]->c.post_proc_flag != -2)
- di_buf->c.di_buf_dup_p[0]->c.post_ref_count--;
-
- if (di_buf->c.di_buf_dup_p[2])
- di_buf->c.di_buf_dup_p[2]->c.post_ref_count--;
-
- /*debug only:*/
- for (i = 0; i < 3; i++) {
- pbuf_dup = di_buf->c.di_buf_dup_p[i];
- if (pbuf_dup)
- dbg_post_ref("%s:pst_buf[%d],dup_p[%d],pref[%d]\n",
- __func__,
- di_buf->index,
- i,
- pbuf_dup->c.post_ref_count);
- }
-}
-
-#if 0 /*no use*/
-static void vscale_skip_disable_post(struct di_buf_s *di_buf,
- vframe_t *disp_vf, unsigned int channel)
-{
- struct di_buf_s *di_buf_i = NULL;
- int canvas_height = di_buf->di_buf[0]->canvas_height;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- if (di_vscale_skip_enable & 0x2) {/* drop the bottom field */
- if ((di_buf->di_buf_dup_p[0]) && (di_buf->di_buf_dup_p[1]))
- di_buf_i =
- (di_buf->di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP ? di_buf->di_buf_dup_p[1]
- : di_buf->di_buf_dup_p[0];
- else
- di_buf_i = di_buf->di_buf[0];
- } else {
- if ((di_buf->di_buf[0]->post_proc_flag > 0) &&
- (di_buf->di_buf_dup_p[1]))
- di_buf_i = di_buf->di_buf_dup_p[1];
- else
- di_buf_i = di_buf->di_buf[0];
- }
- disp_vf->type = di_buf_i->vframe->type;
- /* pr_dbg("%s (%x %x) (%x %x)\n", __func__,
- * disp_vf, disp_vf->type, di_buf_i->vframe,
- * di_buf_i->vframe->type);
- */
- disp_vf->width = di_buf_i->vframe->width;
- disp_vf->height = di_buf_i->vframe->height;
- disp_vf->duration = di_buf_i->vframe->duration;
- disp_vf->pts = di_buf_i->vframe->pts;
- disp_vf->flag = di_buf_i->vframe->flag;
- disp_vf->canvas0Addr = di_post_idx[ppost->canvas_id][0];
- disp_vf->canvas1Addr = di_post_idx[ppost->canvas_id][0];
- canvas_config(
- di_post_idx[ppost->canvas_id][0],
- di_buf_i->nr_adr, di_buf_i->canvas_width[NR_CANVAS],
- canvas_height, 0, 0);
- dimhv3_disable_post_deinterlace_2();
- ppost->vscale_skip_flag = true;
-}
-#endif
-
-/*early_process_fun*/
-static int early_NONE(void)
-{
- return 0;
-}
-
-int dimv3_do_post_wr_fun(void *arg, vframe_t *disp_vf)
-{
- #if 0
- struct di_post_stru_s *ppost;
- int i;
-
- for (i = 0; i < DI_CHANNEL_NUB; i++) {
- ppost = get_post_stru(i);
-
- ppost->toggle_flag = true;
- }
- return 1;
- #else
- return early_NONE();
- #endif
-}
-#if 0
-static int de_post_disable_fun(void *arg, vframe_t *disp_vf)
-{
- #if 0
- struct di_buf_s *di_buf = (struct di_buf_s *)arg;
- unsigned int channel = di_buf->channel;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- ppost->vscale_skip_flag = false;
- ppost->toggle_flag = true;
-
- PR_ERR("%s------------------------------\n", __func__);
-
- process_vscale_skip(di_buf, disp_vf, channel);
-/* for atv static image flickering */
- if (di_buf->c.process_fun_index == PROCESS_FUN_NULL)
- dimhv3_disable_post_deinterlace_2();
-
- return 1;
-/* called for new_format_flag, make
- * video set video_property_changed
- */
- #else
- return early_NONE();
- #endif
-}
-#endif
-#if 0
-static int do_nothing_fun(void *arg, vframe_t *disp_vf)
-{
- #if 0
- struct di_buf_s *di_buf = (struct di_buf_s *)arg;
- unsigned int channel = di_buf->channel;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- ppost->vscale_skip_flag = false;
- ppost->toggle_flag = true;
-
- PR_ERR("%s------------------------------\n", __func__);
-
- process_vscale_skip(di_buf, disp_vf, channel);
-
- if (di_buf->c.process_fun_index == PROCESS_FUN_NULL) {
- if (Rd(DI_IF1_GEN_REG) & 0x1 || Rd(DI_POST_CTRL) & 0xf)
- dimhv3_disable_post_deinterlace_2();
- /*if(di_buf->pulldown_mode == PULL_DOWN_EI && Rd(DI_IF1_GEN_REG)&0x1)
- * dim_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG, 0x3 << 30);
- */
- }
- return 0;
- #else
- return early_NONE();
- #endif
-}
-#endif
-//static /*ary no use*/
-int do_pre_only_fun(void *arg, vframe_t *disp_vf)
-{
- #if 0
- unsigned int channel;
- struct di_post_stru_s *ppost;
-
- PR_ERR("%s------------------------------\n", __func__);
-#ifdef DI_USE_FIXED_CANVAS_IDX
- if (arg) {
- struct di_buf_s *di_buf = (struct di_buf_s *)arg;
- vframe_t *vf = di_buf->vframe;
- int width, canvas_height;
-
- channel = di_buf->channel;
- ppost = get_post_stru(channel);
-
- ppost->vscale_skip_flag = false;
- ppost->toggle_flag = true;
-
- if (!vf || !di_buf->di_buf[0]) {
- dimv3_print("error:%s,NULL point!!\n", __func__);
- return 0;
- }
- width = di_buf->di_buf[0]->canvas_width[NR_CANVAS];
- /* linked two interlace buffer should double height*/
- if (di_buf->di_buf[0]->di_wr_linked_buf)
- canvas_height =
- (di_buf->di_buf[0]->canvas_height << 1);
- else
- canvas_height =
- di_buf->di_buf[0]->canvas_height;
-#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
- if (is_vsync_rdma_enable()) {
- ppost->canvas_id = ppost->next_canvas_id;
- } else {
- ppost->canvas_id = 0;
- ppost->next_canvas_id = 1;
- if (post_wr_en && post_wr_support)
- ppost->canvas_id = ppost->next_canvas_id;
- }
-#endif
-
- canvas_config(
- di_post_idx[ppost->canvas_id][0],
- di_buf->di_buf[0]->nr_adr,
- di_buf->di_buf[0]->canvas_width[NR_CANVAS],
- canvas_height, 0, 0);
-
- vf->canvas0Addr =
- di_post_idx[ppost->canvas_id][0];
- vf->canvas1Addr =
- di_post_idx[ppost->canvas_id][0];
-#ifdef DET3D
- if (ppre->vframe_interleave_flag && di_buf->di_buf[1]) {
- canvas_config(
- di_post_idx[ppost->canvas_id][1],
- di_buf->di_buf[1]->nr_adr,
- di_buf->di_buf[1]->canvas_width[NR_CANVAS],
- canvas_height, 0, 0);
- vf->canvas1Addr =
- di_post_idx[ppost->canvas_id][1];
- vf->duration <<= 1;
- }
-#endif
- ppost->next_canvas_id = ppost->canvas_id ? 0 : 1;
-
- if (di_buf->process_fun_index == PROCESS_FUN_NULL) {
- if (Rd(DI_IF1_GEN_REG) & 0x1 ||
- Rd(DI_POST_CTRL) & 0x10f)
- dimhv3_disable_post_deinterlace_2();
- }
- }
-#endif
-
- return 0;
-#else
- return early_NONE();
-#endif
-}
-
-static void get_vscale_skip_count(unsigned int par)
-{
- /*di_vscale_skip_count_real = (par >> 24) & 0xff;*/
- dimp_set(eDI_MP_di_vscale_skip_count_real,
- (par >> 24) & 0xff);
-}
-
-#define get_vpp_reg_update_flag(par) (((par) >> 16) & 0x1)
-
-static unsigned int pldn_dly = 1;
-
-#if 0
-enum pulldown_mode_e {
- PULL_DOWN_BLEND_0 = 0,/* buf1=dup[0] */
- PULL_DOWN_BLEND_2 = 1,/* buf1=dup[2] */
- PULL_DOWN_MTN = 2,/* mtn only */
- PULL_DOWN_BUF1 = 3,/* do wave with dup[0] */
- PULL_DOWN_EI = 4,/* ei only */
- PULL_DOWN_NORMAL = 5,/* normal di */
- PULL_DOWN_NORMAL_2 = 6,/* di */
-};
-
-#endif
-
-/******************************************
- *
- ******************************************/
-#define edi_mp_post_wr_en eDI_MP_post_wr_en
-#define edi_mp_post_wr_support eDI_MP_post_wr_support
-
-static unsigned int cfg_nv21/* = DI_BIT0*/;
-module_param_named(cfg_nv21, cfg_nv21, uint, 0664);
-
-#ifdef DIM_OUT_NV21
-#define NV21_DBG (1)
-#ifdef NV21_DBG
-static unsigned int cfg_vf;
-module_param_named(cfg_vf, cfg_vf, uint, 0664);
-
-#endif
-
-/**********************************************************
- * canvans
- * set vfm canvas by config | planes | index
- * set vf->canvas0Addr
- *
- **********************************************************/
-static void dim_canvas_set2(struct vframe_s *vf, u32 *index)
-{
- int i;
- u32 *canvas_index = index;
- unsigned int shift;
- struct canvas_config_s *cfg = &vf->canvas0_config[0];
- u32 planes = vf->plane_num;
-
- if (vf->canvas0Addr != ((u32)-1))
- return;
- if (planes > 3) {
- PR_ERR("%s:planes overflow[%d]\n", __func__, planes);
- return;
- }
- dimv3_print("%s:p[%d]\n", __func__, planes);
-
- vf->canvas0Addr = 0;
- for (i = 0; i < planes; i++, canvas_index++, cfg++) {
- canvas_config_config(*canvas_index, cfg);
- dimv3_print("\tw[%d],h[%d], endian[%d],cid[%d]\n",
- cfg->width, cfg->height, cfg->endian, *canvas_index);
- shift = 8 * i;
- vf->canvas0Addr |= (*canvas_index << shift);
- //vf->plane_num = planes;
- }
-}
-
-static void di_cnt_cvs_nv21(unsigned int mode,
- unsigned int *h,
- unsigned int *v,
- unsigned int ch)
-{
- struct di_mm_s *mm = dim_mm_get(ch); /*mm-0705*/
- int width = mm->cfg.di_w;
- int height = mm->cfg.di_h;
- int canvas_height = height + 8;
- unsigned int nr_width = width;
- unsigned int nr_canvas_width = width;
- unsigned int canvas_align_width = 32;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- nr_width = width;
- nr_canvas_width = nr_width;//nr_width << 1;
- nr_canvas_width = roundup(nr_canvas_width, canvas_align_width);
- *h = nr_canvas_width;
- *v = canvas_height;
-}
-
-void div3_cnt_cvs(enum EDPST_MODE mode,
- struct di_win_s *in,
- struct di_win_s *out)
-{
-
- unsigned int inh, inv, oh, ov;
- unsigned int canvas_align_width = 32;
- unsigned int nr_width = 0;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- canvas_align_width = 64;
-
- inh = in->x_size;
- inv = in->y_size;
-
- switch (mode) {
- case EDPST_MODE_NV21_8BIT:
- nr_width = inh;
- break;
- case EDPST_MODE_422_10BIT_PACK:
- nr_width = (inh * 5) / 4;
- nr_width = nr_width << 1;
- break;
- case EDPST_MODE_422_10BIT:
- nr_width = (inh * 3) / 2;
- nr_width = nr_width << 1;
- break;
- case EDPST_MODE_422_8BIT:
- nr_width = inh;
- nr_width = nr_width << 1;
- break;
- }
-
- oh = roundup(nr_width, canvas_align_width);
- ov = roundup(inv, 32);
- out->x_size = oh;
- out->y_size = ov;
- if (cfg_nv21 & DI_BIT1) {
- PR_INF("%s:mode[%d], inx[%d],iny[%d], ox[%d], oy[%d]\n",
- __func__, mode, inh, inv, out->x_size, out->y_size);
- }
-}
-static void dimpst_fill_outvf(struct vframe_s *vfm,
- struct di_buf_s *di_buf,
- enum di_output_format mode)
-{
- struct canvas_config_s *cvsp;
- unsigned int cvsh, cvsv, csize;
-// struct dim_dvfm_s *pdvfm;
-
-// pdvfm = di_buf->c.pdvfm;
-
-// if (!pdvfm) {
-// PR_ERR("%s:no pdvfm, do nothing\n", __func__);
-// return;
-// }
-
- //memcpy(vfm, di_buf->vframe, sizeof(*vfm));
- vfm->width = di_buf->c.vmode.w;
- vfm->height = di_buf->c.vmode.h;
- vfm->type = di_buf->c.vmode.vtype;
- vfm->bitdepth = di_buf->c.vmode.bitdepth;
- /* canvas */
- vfm->canvas0Addr = (u32)-1;
-
- if (mode == DI_OUTPUT_422) {
- vfm->plane_num = 1;
- cvsp = &vfm->canvas0_config[0];
- cvsp->phy_addr = di_buf->nr_adr;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- cvsp->width = di_buf->canvas_width[NR_CANVAS];
- cvsp->height = di_buf->canvas_height;
- } else {
- vfm->plane_num = 2;
- /* count canvs size */
- di_cnt_cvs_nv21(0, &cvsh, &cvsv, 0);
- /* 0 */
- cvsp = &vfm->canvas0_config[0];
- cvsp->phy_addr = di_buf->nr_adr;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- cvsp->width = cvsh;
- cvsp->height = cvsv;
- csize = roundup((cvsh * cvsv), PAGE_SIZE);
- /* 1 */
- cvsp = &vfm->canvas0_config[1];
- cvsp->width = cvsh;
- cvsp->height = cvsv;
- cvsp->phy_addr = di_buf->nr_adr + csize;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- }
-
- /* type */
- if (mode == DI_OUTPUT_NV21 ||
- mode == DI_OUTPUT_NV12) {
- /*clear*/
- vfm->type &= ~(VIDTYPE_VIU_NV12 |
- VIDTYPE_VIU_444 |
- VIDTYPE_VIU_NV21 |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_PRE_INTERLACE);
- vfm->type |= VIDTYPE_VIU_FIELD;
- vfm->type |= VIDTYPE_DI_PW;
- if (mode == DI_OUTPUT_NV21)
- vfm->type |= VIDTYPE_VIU_NV21;
- else
- vfm->type |= VIDTYPE_VIU_NV12;
-
- /* bit */
- vfm->bitdepth &= ~(BITDEPTH_MASK);
- vfm->bitdepth &= ~(FULL_PACK_422_MODE);
- vfm->bitdepth |= (BITDEPTH_Y8 |
- BITDEPTH_U8 |
- BITDEPTH_V8);
- } else {
- /*temp */
- vfm->bitdepth &= ~(BITDEPTH_MASK);
- vfm->bitdepth &= ~(FULL_PACK_422_MODE);
- vfm->bitdepth |= (FULL_PACK_422_MODE|
- BITDEPTH_Y10 |
- BITDEPTH_U10 |
- BITDEPTH_V10);
-
- }
-
-
-#ifdef NV21_DBG
- if (cfg_vf)
- vfm->type = cfg_vf;
-#endif
- dbg_vfmv3(vfm, 2);
-}
-
-/* when buf is from out, use this function*/
-/* no input mode */
-/* cvsh, cvsv is from di_buf, not */
-/* type clear delet */
-/* vfm from differ */
-static void dimpst_fill_outvf2(struct vframe_s *vfm,
- struct di_buf_s *di_buf)
-{
- struct canvas_config_s *cvsp;
-// unsigned int cvsh, cvsv, csize;
- enum di_output_format mode;
- struct di_buffer *ins_buf;
-
- ins_buf = (struct di_buffer *)di_buf->c.pdvfm->vfm_out;
-
-
- //memcpy(vfm, di_buf->vframe, sizeof(*vfm));
- memcpy(vfm, ins_buf->vf, sizeof(*vfm));
-
- /* canvas */
- vfm->canvas0Addr = (u32)-1;
-
- if (vfm->type & VIDTYPE_VIU_422)
- mode = DI_OUTPUT_422;
- else if (vfm->type & VIDTYPE_VIU_NV21)
- mode = DI_OUTPUT_NV21;
- else if (vfm->type & VIDTYPE_VIU_NV12)
- mode = DI_OUTPUT_NV12;
- else
- mode = DI_OUTPUT_422;
-
- if (mode == DI_OUTPUT_422) {
- vfm->plane_num = 1;
- cvsp = &vfm->canvas0_config[0];
- //cvsp->phy_addr = ins_buf->vf->canvas0_config[0].phy_addr;
- //di_buf->nr_adr;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- //cvsp->width = di_buf->canvas_width[NR_CANVAS];
- //cvsp->height = di_buf->canvas_height;
- } else {
- vfm->plane_num = 2;
- /* count canvs size */
- //di_cnt_cvs_nv21(0, &cvsh, &cvsv, 0);
- //cvsh = di_buf->canvas_width[NR_CANVAS];
- //cvsv = di_buf->canvas_height;
- /* 0 */
- cvsp = &vfm->canvas0_config[0];
- //cvsp->phy_addr = ins_buf->vf->canvas0_config[0].phy_addr;
- //di_buf->nr_adr;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- //cvsp->width = cvsh;
- //cvsp->height = cvsv;
- //csize = roundup((cvsh * cvsv), PAGE_SIZE);
- /* 1 */
- cvsp = &vfm->canvas0_config[1];
- //cvsp->width = cvsh;
- //cvsp->height = cvsv;
- //cvsp->phy_addr = ins_buf->vf->canvas0_config[1].phy_addr;
- //di_buf->nr_adr + csize;
- cvsp->block_mode = 0;
- cvsp->endian = 0;
- }
-
- /* type */
-#if 0
- /*clear*/
- vfm->type &= ~(VIDTYPE_VIU_NV12 |
- VIDTYPE_VIU_444 |
- VIDTYPE_VIU_NV21 |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_PRE_INTERLACE |
- VIDTYPE_TYPEMASK);
-#else
- /*clear*/
- vfm->type &= ~(VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_PRE_INTERLACE |
- VIDTYPE_TYPEMASK |
- VIDTYPE_INTERLACE_FIRST);
-#endif
- vfm->type |= VIDTYPE_VIU_FIELD;
- vfm->type |= VIDTYPE_DI_PW;
-
- if (mode == DI_OUTPUT_NV21 ||
- mode == DI_OUTPUT_NV12) {
-
- #if 0
- if (mode == EDPST_OUT_MODE_NV21)
- vfm->type |= VIDTYPE_VIU_NV21;
- else
- vfm->type |= VIDTYPE_VIU_NV12;
- #endif
- /* bit */
- vfm->bitdepth &= ~(BITDEPTH_MASK);
- vfm->bitdepth &= ~(FULL_PACK_422_MODE);
- vfm->bitdepth |= (BITDEPTH_Y8 |
- BITDEPTH_U8 |
- BITDEPTH_V8);
- } else {
- /* 422*/
- vfm->type |= VIDTYPE_VIU_SINGLE_PLANE;
- }
-#ifdef NV21_DBG
- if (cfg_vf)
- vfm->type = cfg_vf;
-#endif
-
- dbg_vfmv3(vfm, 2);
-}
-
-#define edi_mp_pps_position eDI_MP_pps_position
-#define edi_mp_pps_dstw eDI_MP_pps_dstw
-#define edi_mp_pps_dsth eDI_MP_pps_dsth
-
-static void dim_cfg_s_mif(struct DI_SIM_MIF_s *smif,
- struct vframe_s *vf,
- struct di_win_s *win)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- //vframe_t *vf = di_buf->vframe;
-
- //smif->canvas_num = di_buf->nr_canvas_idx;
- /* bit mode config */
- if (vf->bitdepth & BITDEPTH_Y10) {
- if (vf->type & VIDTYPE_VIU_444) {
- smif->bit_mode = (vf->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- } else {
- smif->bit_mode = (vf->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- }
- } else {
- smif->bit_mode = 0;
- }
-
- /* video mode */
- if (vf->type & VIDTYPE_VIU_444)
- smif->video_mode = 1;
- else
- smif->video_mode = 0;
-
- /* separate */
- if (vf->type & VIDTYPE_VIU_422)
- smif->set_separate_en = 0;
- else
- smif->set_separate_en = 2; /*nv12 ? nv 21?*/
-
- if (vf->type & VIDTYPE_VIU_NV12) {
- smif->cbcr_swap = 1;
- smif->l_endian = 1;
- smif->reg_swap = 0;
- } else {
- smif->cbcr_swap = 0;
- smif->l_endian = 0;
- smif->reg_swap = 1;
- }
-
- /*x,y,*/
- dimv3_print("nv12:vf[%d],sw[%d]\n", (vf->type & VIDTYPE_VIU_NV12),
- smif->cbcr_swap);
- if (de_devp->pps_enable &&
- dimp_get(edi_mp_pps_position) == 0) {
- //dimv3_pps_config(0, di_width, di_height,
- // dimp_get(edi_mp_pps_dstw),
- // dimp_get(edi_mp_pps_dsth));
- if (win) {
- smif->start_x = win->x_st;
- smif->end_x = win->x_st +
- dimp_get(edi_mp_pps_dstw) - 1;
- smif->start_y = win->y_st;
- smif->end_y = win->y_st +
- dimp_get(edi_mp_pps_dsth) - 1;
- } else {
- smif->start_x = 0;
- smif->end_x =
- dimp_get(edi_mp_pps_dstw) - 1;
- smif->start_y = 0;
- smif->end_y =
- dimp_get(edi_mp_pps_dsth) - 1;
- }
- } else {
- if (win) {
- smif->start_x = win->x_st;
- smif->end_x = win->x_st + win->x_size - 1;
- smif->start_y = win->y_st;
- smif->end_y = win->y_st + win->y_size - 1;
-
- } else {
- smif->start_x = 0;
- smif->end_x = vf->width - 1;
- smif->start_y = 0;
- smif->end_y = vf->height - 1;
- }
- }
-}
-
-#endif /* DIM_OUT_NV21 */
-
-void dbg_vfmv3(struct vframe_s *vf, unsigned int dbgpos)
-{
- int i;
- struct canvas_config_s *cvsp;
-
- if (!(cfg_nv21 & DI_BIT1))
- return;
- PR_INF("%d:addr:%p\n", dbgpos, vf);
- PR_INF("type=0x%x\n", vf->type);
- PR_INF("bitdepth=0x%x\n", vf->bitdepth);
- PR_INF("plane_num=0x%x\n", vf->plane_num);
- PR_INF("0Addr=0x%x\n", vf->canvas0Addr);
- PR_INF("1Addr=0x%x\n", vf->canvas1Addr);
- PR_INF("plane_num=0x%x\n", vf->plane_num);
- for (i = 0; i < vf->plane_num; i++) {
- PR_INF("%d:\n", i);
- cvsp = &vf->canvas0_config[i];
- PR_INF("\tph=0x%x\n", cvsp->phy_addr);
- PR_INF("\tw=%d\n", cvsp->width);
- PR_INF("\th=%d\n", cvsp->height);
- PR_INF("\tb=%d\n", cvsp->block_mode);
- PR_INF("\tendian=%d\n", cvsp->endian);
- }
-}
-
-int dimv3_post_process(void *arg, unsigned int zoom_start_x_lines,
- unsigned int zoom_end_x_lines,
- unsigned int zoom_start_y_lines,
- unsigned int zoom_end_y_lines,
- vframe_t *disp_vf)
-{
- struct di_buf_s *di_buf = (struct di_buf_s *)arg;
- struct di_buf_s *di_pldn_buf = NULL;
- unsigned int di_width, di_height, di_start_x, di_end_x, mv_offset;
- unsigned int di_start_y, di_end_y, hold_line;
- unsigned int post_blend_en = 0, post_blend_mode = 0,
- blend_mtn_en = 0, ei_en = 0, post_field_num = 0;
- int di_vpp_en, di_ddr_en;
- unsigned char mc_pre_flag = 0;
- bool invert_mv = false;
- static int post_index = -1;
- unsigned char tmp_idx = 0;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- struct di_hpst_s *pst = get_hw_pst();
- struct dim_vmode_s *pvmode;
-#ifdef DIM_OUT_NV21
- struct dim_inter_s *pintf;
-#endif
- unsigned char channel = pst->curr_ch;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_post_stru_s *ppost = get_post_stru(channel);
-#ifdef DIM_OUT_NV21
- u32 cvs_nv21[2];
-#endif
-
- dimp_inc(eDI_MP_post_cnt);
- if (ppost->vscale_skip_flag)
- return 0;
-
- get_vscale_skip_count(zoom_start_x_lines);
-
- if (IS_ERR_OR_NULL(di_buf))
- return 0;
-
- #if 0
- if (!di_buf->vframe)
- return 0;
-
- else
- #endif
- if (IS_ERR_OR_NULL(di_buf->c.di_buf_dup_p[0]))
- return 0;
-
- hold_line = dimp_get(eDI_MP_post_hold_line);
- di_pldn_buf = di_buf->c.di_buf_dup_p[pldn_dly];
-
- di_buf->c.canvas_config_flag = 1;/*ary add */
- if (div3_que_is_in_que(channel, QUE_POST_FREE, di_buf) &&
- post_index != di_buf->index) {
- post_index = di_buf->index;
- PR_ERR("%s:post_buf[%d] is in post free list.\n",
- __func__, di_buf->index);
- return 0;
- }
- hpstv3_dbg_mem_pd_trig(0);
- pvmode = &di_buf->c.vmode;/* input*/
-#if 0 /*ary: no use?*/
- if (ppost->toggle_flag && di_buf->di_buf_dup_p[1])
- topv3_bot_config(di_buf->di_buf_dup_p[1]);
-
- ppost->toggle_flag = false;
-#endif
-
- ppost->cur_disp_index = di_buf->index;
-
- if (get_vpp_reg_update_flag(zoom_start_x_lines) ||
- dimp_get(eDI_MP_post_refresh))
- ppost->update_post_reg_flag = 1;
-
- zoom_start_x_lines = zoom_start_x_lines & 0xffff;
- zoom_end_x_lines = zoom_end_x_lines & 0xffff;
- zoom_start_y_lines = zoom_start_y_lines & 0xffff;
- zoom_end_y_lines = zoom_end_y_lines & 0xffff;
-
- if (!get_init_flag(channel) && IS_ERR_OR_NULL(ppost->keep_buf)) {
- PR_ERR("%s 2:\n", __func__);
- return 0;
- }
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_SETB, channel, ppost->frame_cnt);
- dbg_post_cnt(channel, "ps1");
- di_start_x = zoom_start_x_lines;
- di_end_x = zoom_end_x_lines;
- di_width = di_end_x - di_start_x + 1;
- di_start_y = zoom_start_y_lines;
- di_end_y = zoom_end_y_lines;
- di_height = di_end_y - di_start_y + 1;
- di_height
- = di_height / (dimp_get(eDI_MP_di_vscale_skip_count_real) + 1);
- /* make sure the height is even number */
- if (di_height % 2) {
- /*for skip mode,post only half line-1*/
- if (!dimp_get(eDI_MP_post_wr_en) &&
- ((di_height > 150) &&
- (di_height < 1080)) &&
- dimp_get(eDI_MP_di_vscale_skip_count_real))
- di_height = di_height - 3;
- else
- di_height++;
- }
- #if 0
- dimhv3_post_ctrl(DI_HW_POST_CTRL_INIT,
- (post_wr_en && post_wr_support));
- #endif
-
-#ifdef DIM_OUT_NV21
- pintf = get_dev_intf(channel);
- if (pintf->tmode == EDIM_TMODE_2_PW_OUT) {
- dimpst_fill_outvf2(&pst->vf_post, di_buf);
- } else {
- /* nv 21*/
- if (cfg_nv21 & DI_BIT0)
- dimpst_fill_outvf(&pst->vf_post,
- di_buf,
- DI_OUTPUT_NV21);
- else
- dimpst_fill_outvf(&pst->vf_post,
- di_buf,
- DI_OUTPUT_422);
- }
- /*************************************************/
-#endif
- if (Rd(DI_POST_SIZE) != ((di_width - 1) | ((di_height - 1) << 16)) ||
- ppost->buf_type != di_buf->c.di_buf_dup_p[0]->type ||
- (ppost->di_buf0_mif.luma_x_start0 != di_start_x) ||
- (ppost->di_buf0_mif.luma_y_start0 != di_start_y / 2)) {
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_RESIZE, channel,
- ppost->frame_cnt);/*dbg*/
- ppost->buf_type = di_buf->c.di_buf_dup_p[0]->type;
-
- dimhv3_initial_di_post_2(di_width, di_height,
- hold_line,
- (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)));
-
- #if 0
- if (!di_buf->c.di_buf_dup_p[0]->vframe ||
- !di_buf->vframe) {
- PR_ERR("%s 3:\n", __func__);
- return 0;
- }
- #endif
-#ifdef DIM_OUT_NV21
- /* nv 21*/
- dim_cfg_s_mif(&ppost->di_diwr_mif, &pst->vf_post, NULL);
-#endif
- /* bit mode config */
- #if 0
- if (di_buf->vframe->bitdepth & BITDEPTH_Y10) {
- if (di_buf->vframe->type & VIDTYPE_VIU_444) {
- ppost->di_buf0_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 2;
- ppost->di_buf1_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 2;
- ppost->di_buf2_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 2;
- ppost->di_diwr_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 2;
-
- } else {
- ppost->di_buf0_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 1;
- ppost->di_buf1_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 1;
- ppost->di_buf2_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 1;
- ppost->di_diwr_mif.bit_mode =
- (di_buf->vframe->bitdepth & FULL_PACK_422_MODE) ? 3 : 1;
- }
- } else {
- ppost->di_buf0_mif.bit_mode = 0;
- ppost->di_buf1_mif.bit_mode = 0;
- ppost->di_buf2_mif.bit_mode = 0;
- ppost->di_diwr_mif.bit_mode = 0;
- }
- #else
- ppost->di_buf0_mif.bit_mode = pvmode->bit_mode;
- ppost->di_buf1_mif.bit_mode = pvmode->bit_mode;
- ppost->di_buf2_mif.bit_mode = pvmode->bit_mode;
-#ifndef DIM_OUT_NV21
- ppost->di_diwr_mif.bit_mode = pvmode->bit_mode;
-#endif
- #endif
-
- #if 0
- if (di_buf->vframe->type & VIDTYPE_VIU_444) {
- ppost->di_buf0_mif.video_mode = 1;
- ppost->di_buf1_mif.video_mode = 1;
- ppost->di_buf2_mif.video_mode = 1;
- } else {
- ppost->di_buf0_mif.video_mode = 0;
- ppost->di_buf1_mif.video_mode = 0;
- ppost->di_buf2_mif.video_mode = 0;
- }
- #else
- if (pvmode->vtype & DIM_VFM_VIU_444) {
- ppost->di_buf0_mif.video_mode = 1;
- ppost->di_buf1_mif.video_mode = 1;
- ppost->di_buf2_mif.video_mode = 1;
- } else {
- ppost->di_buf0_mif.video_mode = 0;
- ppost->di_buf1_mif.video_mode = 0;
- ppost->di_buf2_mif.video_mode = 0;
- }
-
- #endif
- #if 0
- if (ppost->buf_type == VFRAME_TYPE_IN &&
- !(di_buf->c.di_buf_dup_p[0]->vframe->type &
- VIDTYPE_VIU_FIELD)) {
- PR_ERR("%s:type in?\n", __func__);/*ary*/
- if (di_buf->vframe->type & VIDTYPE_VIU_NV21) {
- ppost->di_buf0_mif.set_separate_en = 1;
- ppost->di_buf1_mif.set_separate_en = 1;
- ppost->di_buf2_mif.set_separate_en = 1;
- } else {
- ppost->di_buf0_mif.set_separate_en = 0;
- ppost->di_buf1_mif.set_separate_en = 0;
- ppost->di_buf2_mif.set_separate_en = 0;
- }
- ppost->di_buf0_mif.luma_y_start0 = di_start_y;
- ppost->di_buf0_mif.luma_y_end0 = di_end_y;
- } else { /* from vdin or local vframe process by di pre */
- ppost->di_buf0_mif.set_separate_en = 0;
- ppost->di_buf0_mif.luma_y_start0 =
- di_start_y >> 1;
- ppost->di_buf0_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf1_mif.set_separate_en = 0;
- ppost->di_buf1_mif.luma_y_start0 =
- di_start_y >> 1;
- ppost->di_buf1_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf2_mif.set_separate_en = 0;
- ppost->di_buf2_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf2_mif.luma_y_start0 =
- di_start_y >> 1;
- }
- #else
- ppost->di_buf0_mif.set_separate_en = 0;
- ppost->di_buf0_mif.luma_y_start0 =
- di_start_y >> 1;
- ppost->di_buf0_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf1_mif.set_separate_en = 0;
- ppost->di_buf1_mif.luma_y_start0 =
- di_start_y >> 1;
- ppost->di_buf1_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf2_mif.set_separate_en = 0;
- ppost->di_buf2_mif.luma_y_end0 = di_end_y >> 1;
- ppost->di_buf2_mif.luma_y_start0 =
- di_start_y >> 1;
-
- #endif
- ppost->di_buf0_mif.luma_x_start0 = di_start_x;
- ppost->di_buf0_mif.luma_x_end0 = di_end_x;
- ppost->di_buf1_mif.luma_x_start0 = di_start_x;
- ppost->di_buf1_mif.luma_x_end0 = di_end_x;
- ppost->di_buf2_mif.luma_x_start0 = di_start_x;
- ppost->di_buf2_mif.luma_x_end0 = di_end_x;
-
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) {
- if (de_devp->pps_enable &&
- dimp_get(eDI_MP_pps_position) == 0) {
- dimv3_pps_config(0, di_width, di_height,
- dimp_get(eDI_MP_pps_dstw),
- dimp_get(eDI_MP_pps_dsth));
-#ifndef DIM_OUT_NV21
- ppost->di_diwr_mif.start_x = 0;
- ppost->di_diwr_mif.end_x
- = dimp_get(eDI_MP_pps_dstw) - 1;
- ppost->di_diwr_mif.start_y = 0;
- ppost->di_diwr_mif.end_y
- = dimp_get(eDI_MP_pps_dsth) - 1;
- } else {
- ppost->di_diwr_mif.start_x = di_start_x;
- ppost->di_diwr_mif.end_x = di_end_x;
- ppost->di_diwr_mif.start_y = di_start_y;
- ppost->di_diwr_mif.end_y = di_end_y;
-#endif
- }
- }
-
- ppost->di_mtnprd_mif.start_x = di_start_x;
- ppost->di_mtnprd_mif.end_x = di_end_x;
- ppost->di_mtnprd_mif.start_y = di_start_y >> 1;
- ppost->di_mtnprd_mif.end_y = di_end_y >> 1;
- if (dimp_get(eDI_MP_mcpre_en)) {
- ppost->di_mcvecrd_mif.start_x = di_start_x / 5;
- mv_offset = (di_start_x % 5) ? (5 - di_start_x % 5) : 0;
- ppost->di_mcvecrd_mif.vecrd_offset =
- overturn ? (di_end_x + 1) % 5 : mv_offset;
- ppost->di_mcvecrd_mif.start_y =
- (di_start_y >> 1);
- ppost->di_mcvecrd_mif.size_x =
- (di_end_x + 1 + 4) / 5 - 1 - di_start_x / 5;
- ppost->di_mcvecrd_mif.end_y =
- (di_end_y >> 1);
- }
- ppost->update_post_reg_flag = 1;
- /* if height decrease, mtn will not enough */
- if (di_buf->c.pd_config.global_mode != PULL_DOWN_BUF1 &&
- !dimp_get(eDI_MP_post_wr_en))
- di_buf->c.pd_config.global_mode = PULL_DOWN_EI;
- }
-
-#ifdef DI_USE_FIXED_CANVAS_IDX
-#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
- if (is_vsync_rdma_enable()) {
-#ifdef DIM_OUT_NV21
- if (dimp_get(edi_mp_post_wr_en) &&
- dimp_get(edi_mp_post_wr_support))
- ppost->canvas_id = 0;
- else
- ppost->canvas_id = ppost->next_canvas_id;
-#else
- ppost->canvas_id = ppost->next_canvas_id;
-#endif
- } else {
- ppost->canvas_id = 0;
- ppost->next_canvas_id = 1;
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support))
- ppost->canvas_id =
- ppost->next_canvas_id;
- }
-#endif
- /*post_blend = di_buf->pd_config.global_mode;*/
- dimp_set(eDI_MP_post_blend, di_buf->c.pd_config.global_mode);
- dimv3_print("%s:ch[%d]:blend[%d]\n", __func__, channel,
- dimp_get(eDI_MP_post_blend));
- switch (dimp_get(eDI_MP_post_blend)) {
- case PULL_DOWN_BLEND_0:
- case PULL_DOWN_NORMAL:
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1],
- di_post_idx[ppost->canvas_id][0], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[2], -1,
- di_post_idx[ppost->canvas_id][2]);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[0],
- di_post_idx[ppost->canvas_id][1], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[2],
- di_post_idx[ppost->canvas_id][3], -1);
- if (dimp_get(eDI_MP_mcpre_en))
- config_mcvec_canvas_idx(
- di_buf->c.di_buf_dup_p[2],
- di_post_idx[ppost->canvas_id][4]);
- break;
- case PULL_DOWN_BLEND_2:
- case PULL_DOWN_NORMAL_2:
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[0],
- di_post_idx[ppost->canvas_id][3], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1],
- di_post_idx[ppost->canvas_id][0], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[2], -1,
- di_post_idx[ppost->canvas_id][2]);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[2],
- di_post_idx[ppost->canvas_id][1], -1);
- if (dimp_get(eDI_MP_mcpre_en))
- config_mcvec_canvas_idx(
- di_buf->c.di_buf_dup_p[2],
- di_post_idx[ppost->canvas_id][4]);
- break;
- case PULL_DOWN_MTN:
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1],
- di_post_idx[ppost->canvas_id][0], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[2], -1,
- di_post_idx[ppost->canvas_id][2]);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[0],
- di_post_idx[ppost->canvas_id][1], -1);
- break;
- case PULL_DOWN_BUF1:/* wave with buf1 :ary: p as i*/
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1],
- di_post_idx[ppost->canvas_id][0], -1);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1], -1,
- di_post_idx[ppost->canvas_id][2]);
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[0],
- di_post_idx[ppost->canvas_id][1], -1);
- break;
- case PULL_DOWN_EI:
- if (di_buf->c.di_buf_dup_p[1])
- config_canvas_idx(
- di_buf->c.di_buf_dup_p[1],
- di_post_idx[ppost->canvas_id][0], -1);
- break;
- default:
- break;
- }
- ppost->next_canvas_id = ppost->canvas_id ? 0 : 1;
-#endif
- if (!di_buf->c.di_buf_dup_p[1]) {
- PR_ERR("%s 4:\n", __func__);
- return 0;
- }
- #if 0
- if (!di_buf->c.di_buf_dup_p[1]->vframe ||
- !di_buf->c.di_buf_dup_p[0]->vframe) {
- PR_ERR("%s 5:\n", __func__);
- return 0;
- }
- #endif
- if (is_meson_txl_cpu() && overturn && di_buf->c.di_buf_dup_p[2]) {
- /*sync from kernel 3.14 txl*/
- if (dimp_get(eDI_MP_post_blend) == PULL_DOWN_BLEND_2)
- dimp_set(eDI_MP_post_blend, PULL_DOWN_BLEND_0);
- else if (dimp_get(eDI_MP_post_blend) == PULL_DOWN_BLEND_0)
- dimp_set(eDI_MP_post_blend, PULL_DOWN_BLEND_2);
- }
-
- switch (dimp_get(eDI_MP_post_blend)) {
- case PULL_DOWN_BLEND_0:
- case PULL_DOWN_NORMAL:
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num = (di_buf->c.di_buf_dup_p[1]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- ppost->di_buf0_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- ppost->di_buf1_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- ppost->di_buf2_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[2]->nr_canvas_idx;
- ppost->di_mtnprd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[2]->mtn_canvas_idx;
- /*mc_pre_flag = is_meson_txl_cpu()?2:(overturn?0:1);*/
- if (is_meson_txl_cpu() && overturn) {
- /* swap if1&if2 mean negation of mv for normal di*/
- tmp_idx = ppost->di_buf1_mif.canvas0_addr0;
- ppost->di_buf1_mif.canvas0_addr0 =
- ppost->di_buf2_mif.canvas0_addr0;
- ppost->di_buf2_mif.canvas0_addr0 = tmp_idx;
- }
- mc_pre_flag = overturn ? 0 : 1;
- if (di_buf->c.pd_config.global_mode == PULL_DOWN_NORMAL) {
- post_blend_mode = 3;
- /*if pulldown, mcdi_mcpreflag is 1,*/
- /*it means use previous field for MC*/
- /*else not pulldown,mcdi_mcpreflag is 2*/
- /*it means use forward & previous field for MC*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- mc_pre_flag = 2;
- } else {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- mc_pre_flag = 1;
- post_blend_mode = 1;
- }
- if (is_meson_txl_cpu() && overturn)
- mc_pre_flag = 1;
-
- if (dimp_get(eDI_MP_mcpre_en)) {
- ppost->di_mcvecrd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[2]->mcvec_canvas_idx;
- }
- blend_mtn_en = 1;
- ei_en = 1;
- dimp_set(eDI_MP_post_ei, 1);
- post_blend_en = 1;
- break;
- case PULL_DOWN_BLEND_2:
- case PULL_DOWN_NORMAL_2:
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num = (di_buf->c.di_buf_dup_p[1]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- ppost->di_buf0_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- ppost->di_buf1_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[2]->nr_canvas_idx;
- ppost->di_buf2_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- ppost->di_mtnprd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[2]->mtn_canvas_idx;
- if (is_meson_txl_cpu() && overturn) {
- ppost->di_buf1_mif.canvas0_addr0 =
- ppost->di_buf2_mif.canvas0_addr0;
- }
- if (dimp_get(eDI_MP_mcpre_en)) {
- ppost->di_mcvecrd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[2]->mcvec_canvas_idx;
- mc_pre_flag = is_meson_txl_cpu() ? 0 :
- (overturn ? 1 : 0);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
- invert_mv = true;
- else if (!overturn)
- ppost->di_buf2_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[2]->nr_canvas_idx;
- }
- if (di_buf->c.pd_config.global_mode == PULL_DOWN_NORMAL_2) {
- post_blend_mode = 3;
- /*if pulldown, mcdi_mcpreflag is 1,*/
- /*it means use previous field for MC*/
- /*else not pulldown,mcdi_mcpreflag is 2*/
- /*it means use forward & previous field for MC*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- mc_pre_flag = 2;
- } else {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- mc_pre_flag = 1;
- post_blend_mode = 1;
- }
- blend_mtn_en = 1;
- ei_en = 1;
- dimp_set(eDI_MP_post_ei, 1);
- post_blend_en = 1;
- break;
- case PULL_DOWN_MTN:
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num = (di_buf->c.di_buf_dup_p[1]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- ppost->di_buf0_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- ppost->di_buf1_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- ppost->di_mtnprd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[2]->mtn_canvas_idx;
- post_blend_mode = 0;
- blend_mtn_en = 1;
- ei_en = 1;
- dimp_set(eDI_MP_post_ei, 1);
- post_blend_en = 1;
- break;
- case PULL_DOWN_BUF1: /*wave p as i*/
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num = (di_buf->c.di_buf_dup_p[1]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- ppost->di_buf0_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- ppost->di_mtnprd_mif.canvas_num =
- di_buf->c.di_buf_dup_p[1]->mtn_canvas_idx;
- ppost->di_buf1_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- post_blend_mode = 1;
- blend_mtn_en = 0;
- ei_en = 0;
- dimp_set(eDI_MP_post_ei, 0);
- post_blend_en = 0;
- break;
- case PULL_DOWN_EI:
- if (di_buf->c.di_buf_dup_p[1]) {
- ppost->di_buf0_mif.canvas0_addr0 =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num =
- (di_buf->c.di_buf_dup_p[1]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- } else {
- #if 0
- post_field_num =
- (di_buf->c.di_buf_dup_p[0]->vframe->type &
- VIDTYPE_TYPEMASK)
- == VIDTYPE_INTERLACE_TOP ? 0 : 1;
- #else
- post_field_num =
- (di_buf->c.di_buf_dup_p[0]->c.wmode.is_top) ?
- 0 : 1;
- #endif
- ppost->di_buf0_mif.src_field_mode
- = post_field_num;
- }
- post_blend_mode = 2;
- blend_mtn_en = 0;
- ei_en = 1;
- dimp_set(eDI_MP_post_ei, 1);
- post_blend_en = 0;
- break;
- default:
- break;
- }
-
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) {
- #ifdef DIM_OUT_NV21
- cvs_nv21[0] = di_post_idx[0][5];
- cvs_nv21[1] = di_post_idx[1][0];
- dim_canvas_set2(&pst->vf_post, &cvs_nv21[0]);
- ppost->di_diwr_mif.canvas_num = pst->vf_post.canvas0Addr;
- ppost->di_diwr_mif.ddr_en = 1;
- #else
- config_canvas_idx(di_buf,
- di_post_idx[ppost->canvas_id][5], -1);
- ppost->di_diwr_mif.canvas_num = di_buf->nr_canvas_idx;
- #endif
-
- di_vpp_en = 0;
- di_ddr_en = 1;
- } else {
- di_vpp_en = 1;
- di_ddr_en = 0;
- #ifdef DIM_OUT_NV21
- ppost->di_diwr_mif.ddr_en = 0;
- #endif
- }
-
- /* if post size < MIN_POST_WIDTH, force ei */
- if ((di_width < MIN_BLEND_WIDTH) &&
- (di_buf->c.pd_config.global_mode == PULL_DOWN_BLEND_0 ||
- di_buf->c.pd_config.global_mode == PULL_DOWN_BLEND_2 ||
- di_buf->c.pd_config.global_mode == PULL_DOWN_NORMAL
- )) {
- post_blend_mode = 1;
- blend_mtn_en = 0;
- ei_en = 0;
- dimp_set(eDI_MP_post_ei, 0);
- post_blend_en = 0;
- }
-
- if (dimp_get(eDI_MP_mcpre_en))
- ppost->di_mcvecrd_mif.blend_en = post_blend_en;
- invert_mv = overturn ? (!invert_mv) : invert_mv;
- if (ppost->update_post_reg_flag) {
- dimhv3_enable_di_post_2(
- &ppost->di_buf0_mif,
- &ppost->di_buf1_mif,
- &ppost->di_buf2_mif,
- &ppost->di_diwr_mif,
- &ppost->di_mtnprd_mif,
- ei_en, /* ei enable */
- post_blend_en, /* blend enable */
- blend_mtn_en, /* blend mtn enable */
- post_blend_mode, /* blend mode. */
- di_vpp_en, /* di_vpp_en. */
- di_ddr_en, /* di_ddr_en. */
- post_field_num, /* 1 bottom generate top */
- hold_line,
- dimp_get(eDI_MP_post_urgent),
- (invert_mv ? 1 : 0),
- dimp_get(eDI_MP_di_vscale_skip_count_real)
- );
- if (dimp_get(eDI_MP_mcpre_en)) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimhv3_enable_mc_di_post_g12(
- &ppost->di_mcvecrd_mif,
- dimp_get(eDI_MP_post_urgent),
- overturn, (invert_mv ? 1 : 0));
- else
- dimhv3_enable_mc_di_post(
- &ppost->di_mcvecrd_mif,
- dimp_get(eDI_MP_post_urgent),
- overturn, (invert_mv ? 1 : 0));
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- }
- } else {
- dimhv3_post_switch_buffer(
- &ppost->di_buf0_mif,
- &ppost->di_buf1_mif,
- &ppost->di_buf2_mif,
- &ppost->di_diwr_mif,
- &ppost->di_mtnprd_mif,
- &ppost->di_mcvecrd_mif,
- ei_en, /* ei enable */
- post_blend_en, /* blend enable */
- blend_mtn_en, /* blend mtn enable */
- post_blend_mode, /* blend mode. */
- di_vpp_en, /* di_vpp_en. */
- di_ddr_en, /* di_ddr_en. */
- post_field_num, /* 1 bottom generate top */
- hold_line,
- dimp_get(eDI_MP_post_urgent),
- (invert_mv ? 1 : 0),
- dimp_get(eDI_MP_pulldown_enable),
- dimp_get(eDI_MP_mcpre_en),
- dimp_get(eDI_MP_di_vscale_skip_count_real)
- );
- }
-
- if (is_meson_gxtvbb_cpu() ||
- is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_gxlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) {
- if (div3_cfg_top_get(EDI_CFG_ref_2) &&
- mc_pre_flag &&
- dimp_get(eDI_MP_post_wr_en)) { /*OTT-3210*/
- dbg_once("mc_old=%d\n", mc_pre_flag);
- mc_pre_flag = 1;
- }
- dimv3_post_read_reverse_irq(overturn, mc_pre_flag,
- post_blend_en ? dimp_get(eDI_MP_mcpre_en) : false);
- /* disable mc for first 2 fieldes mv unreliable */
- if (di_buf->c.seq < 2)
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- }
- if (dimp_get(eDI_MP_mcpre_en)) {
- if (di_buf->c.di_buf_dup_p[2])
- set_post_mcinfo(&di_buf->c.di_buf_dup_p[2]
- ->c.curr_field_mcinfo);
- } else if (is_meson_gxlx_cpu() ||
- is_meson_txl_cpu() ||
- is_meson_txlx_cpu()) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- }
-
-/* set pull down region (f(t-1) */
-
- if (di_pldn_buf &&
- dimp_get(eDI_MP_pulldown_enable) &&
- !ppre->cur_prog_flag) {
- unsigned short offset = (di_start_y >> 1);
-
- #if 0
- if (overturn)
- offset = ((di_buf->vframe->height - di_end_y) >> 1);
- else
- offset = 0;
- #else
- if (overturn)
- offset = ((di_buf->c.wmode.o_h - di_end_y) >> 1);
- else
- offset = 0;
-
- #endif
- /*pulldown_vof_win_vshift*/
- get_ops_pd()->vof_win_vshift(&di_pldn_buf->c.pd_config, offset);
- dimhv3_pulldown_vof_win_config(&di_pldn_buf->c.pd_config);
- }
- postv3_mif_sw(true); /*position?*/
- /*dimh_post_ctrl(DI_HW_POST_CTRL_RESET, di_ddr_en);*/
- /*add by wangfeng 2018-11-15*/
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_DIWR_CTRL, 1, 31, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_DIWR_CTRL, 0, 31, 1);
- /*ary add for post crash*/
- div3_post_set_flow((dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)),
- eDI_POST_FLOW_STEP2_START);
-
- if (ppost->update_post_reg_flag > 0)
- ppost->update_post_reg_flag--;
-
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_SETE, channel, ppost->frame_cnt);
- dimv3_tr_ops.post_set(di_buf->c.vmode.omx_index);
- dbg_post_cnt(channel, "ps2");
- ppost->frame_cnt++;
-
- return 0;
-}
-
-#ifndef DI_DEBUG_POST_BUF_FLOW
-//static /*ary no use*/
-void post_ready_buf_set(unsigned int ch, struct di_buf_s *di_buf)
-{
- vframe_t *vframe_ret = NULL;
- struct di_buf_s *nr_buf = NULL;
- unsigned int pw_en = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support));
-
- vframe_ret = di_buf->vframe;
- nr_buf = di_buf->c.di_buf_dup_p[1];
- if (pw_en) {
- if (di_buf->c.process_fun_index != PROCESS_FUN_NULL) {
-#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vframe_ret->canvas0_config[0].phy_addr =
- di_buf->nr_adr;
- vframe_ret->canvas0_config[0].width =
- di_buf->canvas_width[NR_CANVAS],
- vframe_ret->canvas0_config[0].height =
- di_buf->canvas_height;
- vframe_ret->canvas0_config[0].block_mode = 0;
- vframe_ret->plane_num = 1;
- vframe_ret->canvas0Addr = -1;
- vframe_ret->canvas1Addr = -1;
- if (dimp_get(eDI_MP_show_nrwr)) {
- vframe_ret->canvas0_config[0].phy_addr =
- nr_buf->nr_adr;
- vframe_ret->canvas0_config[0].width =
- nr_buf->canvas_width[NR_CANVAS];
- vframe_ret->canvas0_config[0].height =
- nr_buf->canvas_height;
- }
-#else
- config_canvas_idx(di_buf, di_wr_idx, -1);
- vframe_ret->canvas0Addr = di_buf->nr_canvas_idx;
- vframe_ret->canvas1Addr = di_buf->nr_canvas_idx;
- if (dimp_get(eDI_MP_show_nrwr)) {
- config_canvas_idx(nr_buf,
- di_wr_idx, -1);
- vframe_ret->canvas0Addr = di_wr_idx;
- vframe_ret->canvas1Addr = di_wr_idx;
- }
-#endif
- vframe_ret->early_process_fun = dimv3_do_post_wr_fun;
- vframe_ret->process_fun = NULL;
-
- /* 2019-04-22 Suggestions from brian.zhu*/
- vframe_ret->mem_handle = NULL;
- vframe_ret->type |= VIDTYPE_DI_PW;
- /* 2019-04-22 */
- } else {
- /* p use 2 i buf*/
- if (!di_buf->c.wmode.p_use_2i) {
- PR_ERR("%s:not p use 2i\n", __func__);
- return;
- }
- vframe_ret->canvas0_config[0].phy_addr =
- di_buf->c.di_buf[0]->nr_adr;
- vframe_ret->canvas0_config[0].width =
- di_buf->c.di_buf[0]->canvas_width[NR_CANVAS],
- vframe_ret->canvas0_config[0].height =
- di_buf->c.di_buf[0]->canvas_height<<1;
- vframe_ret->canvas0_config[0].block_mode = 0;
- vframe_ret->plane_num = 1;
- vframe_ret->canvas0Addr = -1;
- vframe_ret->canvas1Addr = -1;
-
- vframe_ret->early_process_fun = dimv3_do_post_wr_fun;
- vframe_ret->process_fun = NULL;
-
- /* 2019-04-22 Suggestions from brian.zhu*/
- vframe_ret->mem_handle = NULL;
- vframe_ret->type |= VIDTYPE_DI_PW;
- }
- }
-}
-
-#endif
-void dimv3_post_de_done_buf_config(unsigned int channel)
-{
- ulong irq_flag2 = 0;
- struct di_buf_s *di_buf = NULL;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-// struct di_dev_s *de_devp = get_dim_de_devp();
- struct di_ch_s *pch;
-
- if (!ppost->cur_post_buf)
- return;
- dbg_post_cnt(channel, "pd1");
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DB, channel, ppost->frame_cnt);
-
- di_lock_irqfiq_save(irq_flag2);
- queuev3_out(channel, ppost->cur_post_buf);/*? which que?post free*/
- di_buf = ppost->cur_post_buf;
-
- #if 0 /*no use*/
- if (de_devp->pps_enable && dimp_get(eDI_MP_pps_position) == 0) {
- di_buf->vframe->width = dimp_get(eDI_MP_pps_dstw);
- di_buf->vframe->height = dimp_get(eDI_MP_pps_dsth);
- }
- #endif
- #ifdef DI_DEBUG_POST_BUF_FLOW
- #else
- //post_ready_buf_set(channel, di_buf);
-
- pch = get_chdata(channel);
- vfv3_fill_post_ready(pch, di_buf);
- #endif
- div3_que_in(channel, QUE_POST_READY, ppost->cur_post_buf);
- dimv3_print("post_done:ch[%d],typ[%d],id[%d],omx[%d]\n",
- channel, ppost->cur_post_buf->type,
- ppost->cur_post_buf->index,
- ppost->cur_post_buf->c.vmode.omx_index);
- #ifdef DI_DEBUG_POST_BUF_FLOW
- #else
- /*add by ary:*/
- recyclev3_post_ready_local(ppost->cur_post_buf, channel);
- #endif
- di_unlock_irqfiq_restore(irq_flag2);
- dimv3_tr_ops.post_ready(di_buf->c.vmode.omx_index);
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
- ppost->cur_post_buf = NULL;
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DE, channel, ppost->frame_cnt);
- dbg_post_cnt(channel, "pd2");
-}
-
-void dimv3_post_de_done_buf_config_vfm(struct di_ch_s *pch)
-{
- ulong irq_flag2 = 0;
- struct di_buf_s *di_buf = NULL;
-// struct di_dev_s *de_devp = get_dim_de_devp();
- //struct di_ch_s *pch;
- unsigned int ch = pch->ch_id;
- struct di_post_stru_s *ppost = get_post_stru(ch);
-
- if (!ppost->cur_post_buf)
- return;
- dbg_post_cnt(ch, "pd1");
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DB, ch, ppost->frame_cnt);
-
- di_lock_irqfiq_save(irq_flag2);
- queuev3_out(ch, ppost->cur_post_buf);/*? which que?post free*/
- di_buf = ppost->cur_post_buf;
-
- #if 0 /*no use*/
- if (de_devp->pps_enable && dimp_get(eDI_MP_pps_position) == 0) {
- di_buf->vframe->width = dimp_get(eDI_MP_pps_dstw);
- di_buf->vframe->height = dimp_get(eDI_MP_pps_dsth);
- }
- #endif
- #ifdef DI_DEBUG_POST_BUF_FLOW
- #else
- //post_ready_buf_set(channel, di_buf);
-
- vfv3_fill_post_ready(pch, di_buf);
- #endif
- div3_que_in(ch, QUE_POST_READY, ppost->cur_post_buf);
- dimv3_print("post_done:ch[%d],typ[%d],id[%d],omx[%d]\n",
- ch, ppost->cur_post_buf->type,
- ppost->cur_post_buf->index,
- ppost->cur_post_buf->c.vmode.omx_index);
- #ifdef DI_DEBUG_POST_BUF_FLOW
- #else
- /*add by ary:*/
- recyclev3_post_ready_local(ppost->cur_post_buf, ch);
- #endif
- di_unlock_irqfiq_restore(irq_flag2);
- dimv3_tr_ops.post_ready(di_buf->c.vmode.omx_index);
- pwv3_vf_notify_receiver(ch,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
- ppost->cur_post_buf = NULL;
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DE, ch, ppost->frame_cnt);
- dbg_post_cnt(ch, "pd2");
-}
-
-void dimv3_post_de_done_buf_config_ins(struct di_ch_s *pch)
-{
- ulong irq_flag2 = 0;
- struct di_buf_s *di_buf = NULL;
- unsigned int ch = pch->ch_id;
- struct di_post_stru_s *ppost = get_post_stru(ch);
-// struct di_dev_s *de_devp = get_dim_de_devp();
- //struct di_ch_s *pch;
- struct dim_inter_s *pitf;
- struct di_buffer *ins_buf;
-
- if (!ppost->cur_post_buf)
- return;
- pitf = &pch->interf;
-
- dbg_post_cnt(ch, "pd1");
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DB, ch, ppost->frame_cnt);
-
- di_lock_irqfiq_save(irq_flag2);
- //queue_out(ch, ppost->cur_post_buf);/*? which que?post free*/
- di_buf = ppost->cur_post_buf;
-
- ins_buf = (struct di_buffer *)di_buf->c.pdvfm->vfm_out;
- if (!ins_buf) {
- PR_ERR("%s:no vfm_out\n", __func__);
- PR_ERR("ch[%d]:type[%d], id[%d]\n", ch,
- di_buf->type, di_buf->index);
- return;
- }
- //no use di_que_in(ch, QUE_POST_READY, ppost->cur_post_buf);
- dimv3_print("post_done:ch[%d],typ[%d],id[%d],omx[%d]\n",
- ch, di_buf->type,
- di_buf->index,
- di_buf->c.vmode.omx_index);
- dimv3_print("post_done:%d,%d\n", pch->sum_pst_done, pch->sum_put);
- /*? for bypass mode do what ?*/
- vfv3_fill_post_ready_ins(pch, di_buf, ins_buf);
- /* check */
- if ((ins_buf->flag & DI_FLAG_BUF_BY_PASS) &&
- ((ins_buf->flag & DI_FLAG_EOS) == 0)) {
- if (!ins_buf->vf->vf_ext) {
- PR_ERR("%s:bypass_no ext:%d,t[%d] ins[%d]\n", __func__,
- di_buf->index,
- di_buf->type,
- ins_buf->mng.index);
- }
- }
- ins_buf->caller_data = pitf->u.dinst.parm.caller_data;
- /* check end */
- //pitf->u.dinst.parm.ops.fill_output_done(ins_buf);
- pch->sum_pst_done++;
- recyclev3_post_ready_local(di_buf, ch);
- recycle_vframe_type_post(di_buf, ch);
-
- di_unlock_irqfiq_restore(irq_flag2);
- pitf->u.dinst.parm.ops.fill_output_done(ins_buf);
-
- dimv3_tr_ops.post_ready(di_buf->c.vmode.omx_index);
-
- ppost->cur_post_buf = NULL;
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DE, ch, ppost->frame_cnt);
- dbg_post_cnt(ch, "pd2");
-}
-
-void dimv3_post_de_done_buf_config_ins_local(struct di_ch_s *pch)
-{
- ulong irq_flag2 = 0;
- struct di_buf_s *di_buf = NULL;
- unsigned int ch = pch->ch_id;
- struct di_post_stru_s *ppost = get_post_stru(ch);
-// struct di_dev_s *de_devp = get_dim_de_devp();
- //struct di_ch_s *pch;
- struct dim_inter_s *pitf;
- struct di_buffer *ins_buf;
-
- if (!ppost->cur_post_buf)
- return;
- pitf = &pch->interf;
-
- dbg_post_cnt(ch, "pd1");
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DB, ch, ppost->frame_cnt);
-
- di_lock_irqfiq_save(irq_flag2);
- queuev3_out(ch, ppost->cur_post_buf);/*? which que?post free*/
- di_unlock_irqfiq_restore(irq_flag2);
- di_buf = ppost->cur_post_buf;
-
- ins_buf = di_buf->ins;
-
- //no use di_que_in(ch, QUE_POST_READY, ppost->cur_post_buf);
- dimv3_print("post_done:ch[%d],typ[%d],id[%d],omx[%d]\n",
- ch, di_buf->type,
- di_buf->index,
- di_buf->c.vmode.omx_index);
-
- /*? for bypass mode do what ?*/
- //vf_fill_post_ready_ins(pch, di_buf, ins_buf);
- vfv3_fill_post_ready(pch, di_buf);
- di_buf->vframe->private_data = ins_buf;
- atomic_set(&di_buf->c.di_cnt, 1);
- ins_buf->private_data = di_buf;
- ins_buf->caller_data = pitf->u.dinst.parm.caller_data;
- if (di_buf->c.wmode.is_i)
- ins_buf->flag = DI_FLAG_I;
- else
- ins_buf->flag = DI_FLAG_P;
- pitf->u.dinst.parm.ops.fill_output_done(ins_buf);
- di_lock_irqfiq_save(irq_flag2);
- queuev3_in(ch, di_buf, QUEUE_DISPLAY);
- recyclev3_post_ready_local(di_buf, ch);
- //recycle_vframe_type_post(di_buf, ch);
-
- di_unlock_irqfiq_restore(irq_flag2);
- //pitf->u.dinst.parm.ops.fill_output_done(ins_buf);
- dimv3_tr_ops.post_ready(di_buf->c.vmode.omx_index);
-
- ppost->cur_post_buf = NULL;
- /*dbg*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_DE, ch, ppost->frame_cnt);
- dbg_post_cnt(ch, "pd2");
-}
-
-#if 0
-static void di_post_process(unsigned int channel)
-{
- struct di_buf_s *di_buf = NULL;
- vframe_t *vf_p = NULL;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- if (ppost->post_de_busy)
- return;
- if (queuev3_empty(channel, QUEUE_POST_DOING)) {
- ppost->post_peek_underflow++;
- return;
- }
-
- di_buf = getv3_di_buf_head(channel, QUEUE_POST_DOING);
- if (dimv3_check_di_buf(di_buf, 20, channel))
- return;
- vf_p = di_buf->vframe;
- if (ppost->run_early_proc_fun_flag) {
- if (vf_p->early_process_fun)
- vf_p->early_process_fun = dimv3_do_post_wr_fun;
- }
- if (di_buf->process_fun_index) {
- ppost->post_wr_cnt++;
- dimv3_post_process(di_buf, 0, vf_p->width - 1,
- 0, vf_p->height - 1, vf_p);
- ppost->post_de_busy = 1;
- ppost->irq_time = curv3_to_msecs();
- } else {
- ppost->de_post_process_done = 1;
- }
- ppost->cur_post_buf = di_buf;
-}
-#endif
-
-static void recycle_vframe_type_post(struct di_buf_s *di_buf,
- unsigned int channel)
-{
- int i;
- struct di_buf_s *p;
-
- if (!di_buf) {
- PR_ERR("%s:\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 15;
-
- recovery_flag++;
- return;
- }
- if (di_buf->c.process_fun_index == PROCESS_FUN_DI)
- dec_post_ref_count(di_buf);
-
- for (i = 0; i < 2; i++) {
- if (di_buf->c.di_buf[i]) {
- /*dec vf keep*/
- p = di_buf->c.di_buf[i];
- if (p->c.in_buf) {
- queuev3_in(channel, p->c.in_buf, QUEUE_RECYCLE);
- p->c.in_buf = NULL;
- PR_INF("dec vf;%d,t[%d]\n",
- p->index, p->type);
- }
-
- queuev3_in(channel, di_buf->c.di_buf[i], QUEUE_RECYCLE);
- dimv3_print("%s: ch[%d]:di_buf[%d],type=%d\n", __func__,
- channel, di_buf->c.di_buf[i]->index,
- di_buf->c.di_buf[i]->type);
- }
- }
- dimv3_print("recycle post:typ:[%d],qtype[%d],indx[%d],vfm[%d]\n",
- di_buf->type, di_buf->queue_index, di_buf->index,
- di_buf->c.vmode.omx_index);
- /*QUEUE_DISPLAY*/
- queuev3_out(channel, di_buf); /* remove it from display_list_head */
- if (di_buf->queue_index != -1) {
- PR_ERR("qout err:index[%d],typ[%d],qindex[%d]\n",
- di_buf->index, di_buf->type, di_buf->queue_index);
- /* queue_out_dbg(channel, di_buf);*/
- }
- di_buf->c.invert_top_bot_flag = 0;
-
- dimv3_buf_clean(di_buf);
- div3_que_in(channel, QUE_POST_FREE, di_buf);
-}
-
-void recyclev3_post_ready_local(struct di_buf_s *di_buf, unsigned int channel)
-{
- int i;
-
- if (di_buf->type != VFRAME_TYPE_POST)
- return;
-
- if (di_buf->c.process_fun_index == PROCESS_FUN_NULL) /*bypass?*/
- return;
-
- if (di_buf->c.process_fun_index == PROCESS_FUN_DI)
- dec_post_ref_count(di_buf);
-
- for (i = 0; i < 2; i++) {
- if (di_buf->c.di_buf[i]) {
-
- queuev3_in(channel, di_buf->c.di_buf[i], QUEUE_RECYCLE);
- dimv3_print("%s: ch[%d]:di_buf[%d],type=%d\n",
- __func__,
- channel,
- di_buf->c.di_buf[i]->index,
- di_buf->c.di_buf[i]->type);
- di_buf->c.di_buf[i] = NULL;
- }
- }
-}
-
-#ifdef DI_BUFFER_DEBUG
-static void
-recycle_vframe_type_post_print(struct di_buf_s *di_buf,
- const char *func,
- const int line)
-{
- int i;
-
- dimv3_print("%s:%d ", func, line);
- for (i = 0; i < 2; i++) {
- if (di_buf->c.di_buf[i])
- dimv3_print("%s[%d]<%d>=>recycle_list; ",
- vframe_type_name[di_buf->di_buf[i]->type],
- di_buf->c.di_buf[i]->index, i);
- }
- dimv3_print("%s[%d] =>post_free_list\n",
- vframe_type_name[di_buf->type], di_buf->index);
-}
-#endif
-
-static unsigned int pldn_dly1 = 1;
-static void set_pulldown_mode(struct di_buf_s *di_buf, unsigned int channel)
-{
- struct di_buf_s *pre_buf_p = di_buf->c.di_buf_dup_p[pldn_dly1];
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXBB)) {
- if (dimp_get(eDI_MP_pulldown_enable) &&
- !ppre->cur_prog_flag) {
- if (pre_buf_p) {
- di_buf->c.pd_config.global_mode =
- pre_buf_p->c.pd_config.global_mode;
- } else {
- /* ary add 2019-06-19*/
- di_buf->c.pd_config.global_mode
- = PULL_DOWN_EI;
- PR_ERR("[%s]: index out of range.\n",
- __func__);
- }
- } else {
- di_buf->c.pd_config.global_mode
- = PULL_DOWN_NORMAL;
- }
- }
-}
-
-static void drop_frame(int check_drop, int throw_flag, struct di_buf_s *di_buf,
- unsigned int ch)
-{
- ulong irq_flag2 = 0;
- int /*i = 0,*/drop_flag = 0;
-// struct di_post_stru_s *ppost = get_post_stru(channel);
- bool dbg_flg = false;
- struct di_ch_s *pch;
- struct dim_inter_s *pintf;
-
- pch = get_chdata(ch);
- if (!pch) {
- PR_ERR("%s:no pch\n", __func__);
- return;
- }
-
- pintf = &pch->interf;
- di_lock_irqfiq_save(irq_flag2);
-
- #if 0 /*remove vframe*/
- if ((frame_count == 0) && check_drop)
- ppost->start_pts = di_buf->vframe->pts;
- #endif
- if ((check_drop &&
- (frame_count < dimp_get(eDI_MP_start_frame_drop_count))) ||
- throw_flag) {
- drop_flag = 1;
- } else {
- if (check_drop && (frame_count
- == dimp_get(eDI_MP_start_frame_drop_count))) {
- #if 0 /*ary 2019-10-28*/
- if ((ppost->start_pts) &&
- (di_buf->vframe->pts == 0))
- di_buf->vframe->pts = ppost->start_pts;
- ppost->start_pts = 0;
- #endif
- }
- #if 0
- for (i = 0; i < 3; i++) {
- if (di_buf->c.di_buf_dup_p[i] &&
- (di_buf->c.di_buf_dup_p[i]->vframe->bitdepth !=
- di_buf->vframe->bitdepth)) {
- PR_INF("%s buf[%d] not match bit mode\n",
- __func__, i);
- drop_flag = 1;
- break;
-
- }
- }
- #endif
- }
- if (drop_flag) {
- queuev3_in(ch, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, ch);
-
- PR_INF("%s:recycle post %d\n", __func__, __LINE__);
-
- } else {
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) {
-
- if (dimv3_tmode_is_localpost(ch))
- div3_que_in(ch, QUE_POST_DOING, di_buf);
- else
- div3_que_in(ch, QUE_POST_NOBUF, di_buf);
-
- dimv3_print("%s:%p,%d,t[%d]\n", __func__,
- di_buf, di_buf->index, di_buf->type);
-
- } else {
- div3_que_in(ch, QUE_POST_READY, di_buf);
- }
-
- dimv3_tr_ops.post_do(di_buf->c.vmode.omx_index);
- dbg_flg = true;
- }
- if (pintf->op_ins_2_doing)
- pintf->op_ins_2_doing(pch, 0, di_buf);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- if (dbg_flg)
- dimv3_print("di:ch[%d]:%dth %s[%d] => post ready %u ms.\n",
- ch,
- frame_count,
- vframe_type_name[di_buf->type], di_buf->index,
- dim_get_timerms(di_buf->c.vmode.ready_jiffies64));
-}
-
-/***********************************************
- * split dim_process_post_vframe
- **********************************************/
-static int dim_pst_vframe_i(unsigned int ch, struct di_buf_s *ready_di_buf)
-{
- ulong irq_flag2 = 0;
- int i = 0;
- int ret = 0;
- int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- struct di_buf_s *p = NULL;
- struct di_buf_s *pdup1 = NULL;/*di_duf_dup_p[1]*/
- int itmp;
-
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
-
- /* di_buf: get post free */
- di_lock_irqfiq_save(irq_flag2);
- di_buf = div3_que_out_to_di_buf(ch, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 17, ch)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
- di_unlock_irqfiq_restore(irq_flag2);
- /*****************/
- dimv3_print("%s\n", __func__);
- /* set post_free's di_buf_dup_p[0/1/2] */
- i = 0;
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- dimv3_print("di:keep[%d]:t[%d]:idx[%d]\n",
- i, tmpa[itmp], p->index);
- di_buf->c.di_buf_dup_p[i++] = p;
-
- if (i >= buffer_keep_count)
- break;
- }
- if (i < buffer_keep_count) {
- PR_ERR("%s:3\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 18;
- recovery_flag++;
- return 0;
- }
-
- /* set post_free's vfm by di_buf_dup_p[1]*/
- pdup1 = di_buf->c.di_buf_dup_p[1];
-
- #if 0 /*remove vframe 12-03*/
- memcpy(di_buf->vframe, pdup1->vframe, sizeof(*di_buf->vframe));
- di_buf->vframe->private_data = di_buf;
- #endif
- di_buf->c.wmode = pdup1->c.wmode;
- di_buf->c.vmode = pdup1->c.vmode;
- di_buf->c.pdvfm = pdup1->c.pdvfm; /*2019-12-03*/
-
- if (pdup1->c.post_proc_flag == 3) {
- /* dummy, not for display */
- inc_post_ref_count(di_buf);
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(ch, di_buf->c.di_buf[0]);
- di_buf->c.di_buf[0]->c.sts |= EDI_ST_VFM_RECYCLE;
- di_lock_irqfiq_save(irq_flag2);
- queuev3_in(ch, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, ch);
-
- di_unlock_irqfiq_restore(irq_flag2);
- PR_INF("%s <dummy>: ", __func__);
- } else {
- if (pdup1->c.post_proc_flag == 2) {
- di_buf->c.pd_config.global_mode = PULL_DOWN_BLEND_2;
- /* blend with di_buf->di_buf_dup_p[2] */
- } else if (di_buf->c.wmode.seq_pre < DIM_EI_CNT) {
- /*ary add for first frame*/
- di_buf->c.pd_config.global_mode = PULL_DOWN_EI;
- } else {
- set_pulldown_mode(di_buf, ch);
- }
-
- if (pdup1->type == VFRAME_TYPE_IN) {
- /* next will be bypass */
- PR_ERR("%s:type is in ?\n", __func__);
- #if 0
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
- di_buf->vframe->canvas0Addr = di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx; /* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx;
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- #endif
- } else {
- /*for debug ?*/
- if (dimp_get(eDI_MP_debug_blend_mode) != -1)
- di_buf->c.pd_config.global_mode
- = dimp_get(eDI_MP_debug_blend_mode);
- #if 0 /*remove vframe 12-03*/
- di_buf->vframe->process_fun =
- ((dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ?
- NULL : dimv3_post_process);
- #endif
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- inc_post_ref_count(di_buf);
- }
- /*ary:di_buf_di_buf*/
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
-
- /*dec vf keep*/
- p = di_buf->c.di_buf[0];
- if (p->c.in_buf) {
- queuev3_in(ch, p->c.in_buf, QUEUE_RECYCLE);
- p->c.in_buf = NULL;
- dimv3_print("%s:recycle dec vf;%d,t[%d]\n", __func__,
- p->index, p->type);
- } else {
- PR_INF("%s:p:%d,t[%d]\n", __func__, p->index, p->type);
- }
-
- queuev3_out(ch, di_buf->c.di_buf[0]);
- di_buf->c.di_buf[0]->c.sts |= EDI_ST_VFM_I;
-
- drop_frame(true,
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[2]->c.throw_flag),
- di_buf, ch);
-
- frame_count++;
-
- dimv3_print("%s <i>: blend[%d]:\n", __func__,
- di_buf->c.pd_config.global_mode);
-
- }
- ret = 1;
-
- return ret;
-}
-
-/***********************************************
- * split dim_process_post_vframe
- **********************************************/
-static int dim_pst_vframe_a(unsigned int channel, struct di_buf_s *ready_di_buf)
-{
- int ret = 0;
- #if 0
- ulong irq_flag2 = 0;
- int i = 0;
-
- int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- struct di_buf_s *p = NULL;
- int itmp;
-
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- bool pw_en;
-
- /* get post free */
- di_lock_irqfiq_save(irq_flag2);
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 17, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
- di_unlock_irqfiq_restore(irq_flag2);
-
- pw_en = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ? true : false;
-
- /* set post_free's di_buf_dup_p[0/1/2] */
- i = 0;
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
-
- dimv3_print("%s\n", __func__);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- dimv3_print("di:keep[%d]:t[%d]:idx[%d]\n",
- i, tmpa[itmp], p->index);
- di_buf->c.di_buf_dup_p[i++] = p;
-
- if (i >= buffer_keep_count)
- break;
- }
- if (i < buffer_keep_count) {
- PR_ERR("%s:3\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 18;
- recovery_flag++;
- return 0;
- }
-
- /* set post_free's vfm by di_buf_dup_p[1]*/
- memcpy(di_buf->vframe,
- di_buf->c.di_buf_dup_p[1]->vframe,
- sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- if (di_buf->c.di_buf_dup_p[1]->c.post_proc_flag == 3) {
- /*i mode this will not run*/
- /* dummy, not for display */
- inc_post_ref_count(di_buf);
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, di_buf->c.di_buf[0]);
- di_lock_irqfiq_save(irq_flag2);
- queuev3_in(channel, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
- PR_INF("%s <dummy>: ", __func__);
- } else {
- if (di_buf->c.di_buf_dup_p[1]->c.post_proc_flag == 2) {
- di_buf->c.pd_config.global_mode = PULL_DOWN_BLEND_2;
- /* blend with di_buf->di_buf_dup_p[2] */
- } else {
- set_pulldown_mode(di_buf, channel);
- }
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
-
- di_buf->vframe->width = di_buf->c.di_buf_dup_p[1]->c.width_bk;
-
- if (di_buf->c.di_buf_dup_p[1]->c.new_format_flag) {
- /* if (di_buf->di_buf_dup_p[1]
- * ->post_proc_flag == 2) {
- */
- di_buf->vframe->early_process_fun = de_post_disable_fun;
- } else {
- di_buf->vframe->early_process_fun = do_nothing_fun;
- }
-
- if (di_buf->c.di_buf_dup_p[1]->type == VFRAME_TYPE_IN) {
- /* next will be bypass */
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
- di_buf->vframe->canvas0Addr = di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx; /* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx;
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- } else {
- /*for debug ?*/
- if (dimp_get(eDI_MP_debug_blend_mode) != -1)
- di_buf->c.pd_config.global_mode
- = dimp_get(eDI_MP_debug_blend_mode);
-
- di_buf->vframe->process_fun = (pw_en ?
- NULL : dimv3_post_process);
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- inc_post_ref_count(di_buf);
- }
- /*ary:di_buf_di_buf*/
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, di_buf->c.di_buf[0]);
-
- drop_frame(true,
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[2]->c.throw_flag),
- di_buf, channel);
-
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <interlace>: ", __func__);
-#endif
- if (!pw_en)
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
- }
- #endif
- PR_ERR("%s\n", __func__);
- ret = 1;
-
- return ret;
-}
-
-static int dim_pst_vframe_b(unsigned int channel, struct di_buf_s *ready_di_buf)
-{
- int ret = 0;
- #if 0
- ulong irq_flag2 = 0;
- int i = 0;
-// int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- //struct di_buf_s *ready_di_buf;
- struct di_buf_s *p = NULL;
- int itmp;
- int ready_count = div3_que_list_count(channel, QUE_PRE_READY);
- bool check_drop = false;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
-
- /*p */
- /*bypass_all mode */
- /*?? */
- /*bypass post mode ? */
- if (is_progressive(ready_di_buf->vframe) ||
- // ready_di_buf->type == VFRAME_TYPE_IN ||
- ready_di_buf->c.post_proc_flag < 0 ||
- dimp_get(eDI_MP_bypass_post_state)
- ){
- int vframe_process_count = 1;
-
- if (dimp_get(eDI_MP_skip_top_bot) &&
- (!is_progressive(ready_di_buf->vframe)))
- vframe_process_count = 2;
-
- if (ready_count >= vframe_process_count) {
- struct di_buf_s *di_buf_i;
-
- di_lock_irqfiq_save(irq_flag2);
- /*get post free*/
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 19, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= vframe_process_count) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- di_buf->c.di_buf_dup_p[i + 1] = NULL;
- break;
- }
- }
- if (i < vframe_process_count) {
- PR_ERR("%s:6\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 22;
-
- recovery_flag++;
- return 0;
- }
-
- di_buf_i = di_buf->c.di_buf_dup_p[0];
- if (!is_progressive(ready_di_buf->vframe) &&
- ((dimp_get(eDI_MP_skip_top_bot) == 1) ||
- (dimp_get(eDI_MP_skip_top_bot) == 2))) {
- /*ready is not p?*/
- unsigned int frame_type =
- di_buf->c.di_buf_dup_p[1]->
- vframe->type &
- VIDTYPE_TYPEMASK;
- if (dimp_get(eDI_MP_skip_top_bot) == 1) {
- di_buf_i = (frame_type ==
- VIDTYPE_INTERLACE_TOP)
- ? di_buf->c.di_buf_dup_p[1]
- : di_buf->c.di_buf_dup_p[0];
-
- } else if (
- dimp_get(eDI_MP_skip_top_bot)
- == 2) {
- di_buf_i = (frame_type ==
- VIDTYPE_INTERLACE_BOTTOM)
- ? di_buf->c.di_buf_dup_p[1]
- : di_buf->c.di_buf_dup_p[0];
- }
- }
-
- memcpy(di_buf->vframe, di_buf_i->vframe,
- sizeof(vframe_t));
-
- di_buf->vframe->width = di_buf_i->c.width_bk;
- di_buf->vframe->private_data = di_buf;
-
- di_buf->vframe->early_process_fun = do_pre_only_fun;
-
- dimv3_print("%s:2\n", __func__);
- if (ready_di_buf->c.post_proc_flag == -2) {
- di_buf->vframe->type
- |= VIDTYPE_VIU_FIELD;
- di_buf->vframe->type
- &= ~(VIDTYPE_TYPEMASK);
- di_buf->vframe->process_fun
- = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- di_buf->c.pd_config.global_mode = PULL_DOWN_EI;
- } else {
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- di_buf->c.pd_config.global_mode =
- PULL_DOWN_NORMAL;
- }
- di_buf->c.di_buf[0] = ready_di_buf;
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, ready_di_buf);
-
- drop_frame(check_drop,
- di_buf->c.di_buf[0]->c.throw_flag,
- di_buf, channel);
-
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <prog by frame>: ", __func__);
-#endif
- ret = 1;
- #if 0
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
- #endif
- }
- } else if (ready_count >= 2) {
- /*for progressive input,
- * type 1: separate two fields,
- * type 2: bypass post as frame
- */
- unsigned char prog_tb_field_proc_type =
- (dimp_get(eDI_MP_prog_proc_config) >> 1) & 0x3;
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 20, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= 2) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- break;
- }
- }
- if (i < 2) {
- PR_ERR("%s:Error6\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 21;
-
- recovery_flag++;
- return 0;
- }
-
- memcpy(di_buf->vframe,
- di_buf->c.di_buf_dup_p[0]->vframe,
- sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
-
- /*separate one progressive frame
- * as two interlace fields
- */
- if (prog_tb_field_proc_type == 1) {
- /* do weave by di post */
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- if (di_buf->c.di_buf_dup_p[0]->c.new_format_flag)
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
-
- di_buf->c.pd_config.global_mode = PULL_DOWN_BUF1;
- di_buf->vframe->process_fun =
- (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- } else if (prog_tb_field_proc_type == 0) {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- /* do weave by vpp */
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE;
- if ((di_buf->c.di_buf_dup_p[0]->c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- } else {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
-
- di_buf->vframe->width
- = di_buf->c.di_buf_dup_p[0]->c.width_bk;
- if ((di_buf->c.di_buf_dup_p[0]->c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
- if (prog_tb_field_proc_type == 2) {
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- /* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- } else {
- /* top */
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- }
- }
-
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- queuev3_out(channel, di_buf->c.di_buf[0]);
- /*check if the field is error,then drop*/
- if ((di_buf->c.di_buf_dup_p[0]->vframe->type &
- VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_BOTTOM) {
- di_buf->c.di_buf[1] = di_buf->c.di_buf_dup_p[1] = NULL;
- queuev3_in(channel, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, channel);
- pr_dbg("%s drop field %d.\n", __func__,
- di_buf->c.di_buf_dup_p[0]->c.seq);
- } else {
- di_buf->c.di_buf[1] = di_buf->c.di_buf_dup_p[1];
- queuev3_out(channel, di_buf->c.di_buf[1]);
-
- drop_frame(dimp_get(eDI_MP_check_start_drop_prog),
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag),
- di_buf, channel);
- }
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <prog by field>: ", __func__);
-#endif
- ret = 1;
-#if 0
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
-#endif
- }
- #endif
- return ret;
-}
-/***********************************************
- * from dim_process_post_vframe_b
- **********************************************/
-static int dim_pst_vframe_p_used2ibuf(unsigned int channel,
- struct di_buf_s *ready_di_buf)
-{
- ulong irq_flag2 = 0;
- int i = 0;
- int ret = 0;
-// int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- //struct di_buf_s *ready_di_buf;
- struct di_buf_s *p = NULL;
- int itmp;
- int ready_count = div3_que_list_count(channel, QUE_PRE_READY);
- bool check_drop = false;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
- struct di_buf_s *di_buf_i;
-
- /*p */
- /*bypass_all mode */
- /*?? */
- /*bypass post mode ? */
-
- int vframe_process_count = 1;
-
- if (ready_count < vframe_process_count)
- return 0;
-
- di_lock_irqfiq_save(irq_flag2);
- /*get post free*/
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 19, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
- itmp = 0;
- dimv3_print("%s\n", __func__);
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
- /*set post buf c.di_buf_dup_p[0] = ready*/
- #ifdef HIS_V3
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= vframe_process_count) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- di_buf->c.di_buf_dup_p[i + 1] = NULL;
- break;
- }
- }
- #else
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= vframe_process_count) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- di_buf->c.di_buf_dup_p[i + 1] = NULL;
- //break;
- }
- #endif
- if (i < vframe_process_count) {
- PR_ERR("%s:6\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 22;
-
- recovery_flag++;
- return 0;
- }
-
- /*di_buf_i is pre_ready*/
- di_buf_i = di_buf->c.di_buf_dup_p[0];
-
- #if 0 /*remove vframe 12-03*/
- /*pre_ready to post*/
- memcpy(di_buf->vframe, di_buf_i->vframe,
- sizeof(vframe_t));
-
- di_buf->vframe->width = di_buf_i->c.width_bk;
- di_buf->vframe->private_data = di_buf;
- di_buf->vframe->early_process_fun = do_pre_only_fun;
- #endif
- dimv3_print("%s:2\n", __func__);
- if (ready_di_buf->c.post_proc_flag == -2) { /*?*/
- #if 0 /*remove vframe 12-03*/
- di_buf->vframe->type |= VIDTYPE_VIU_FIELD;
- di_buf->vframe->type &= ~(VIDTYPE_TYPEMASK);
- di_buf->vframe->process_fun
- = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- #endif
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- di_buf->c.pd_config.global_mode = PULL_DOWN_EI;
- } else {
- //di_buf->vframe->process_fun = NULL;/*remove vframe 12-03*/
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- di_buf->c.pd_config.global_mode = PULL_DOWN_NORMAL;
- }
- di_buf->c.di_buf[0] = ready_di_buf;
- di_buf->c.di_buf[1] = NULL;
- di_buf->c.wmode = ready_di_buf->c.wmode;
- di_buf->c.vmode = ready_di_buf->c.vmode;
- di_buf->c.pdvfm = ready_di_buf->c.pdvfm; /*2019-12-03*/
- queuev3_out(channel, ready_di_buf);
- ready_di_buf->c.sts |= EDI_ST_VFM_P_U2I;
- if (ready_di_buf->c.di_wr_linked_buf)
- ready_di_buf->c.di_wr_linked_buf->c.sts |= EDI_ST_VFM_P_U2I;
-
- drop_frame(check_drop, /*false*/
- di_buf->c.di_buf[0]->c.throw_flag,
- di_buf, channel);
-
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <prog by frame>: ", __func__);
-#endif
- ret = 1;
-
- return ret;
-}
-
-/***********************************************
- * from dim_process_post_vframe_b
- **********************************************/
-static int dim_pst_vframe_p_as_i(unsigned int channel,
- struct di_buf_s *ready_di_buf)
-{
- ulong irq_flag2 = 0;
- int i = 0;
- int ret = 0;
-// int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- //struct di_buf_s *ready_di_buf;
- struct di_buf_s *p = NULL;
- int itmp;
- int ready_count = div3_que_list_count(channel, QUE_PRE_READY);
- bool check_drop = false;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
- unsigned char prog_tb_field_proc_type =
- (dimp_get(eDI_MP_prog_proc_config) >> 1) & 0x3;
-
-
- if (ready_count < 2)
- return 0;
-
- /*for progressive input,
- * type 1: separate two fields,
- * type 2: bypass post as frame
- */
-
- di_lock_irqfiq_save(irq_flag2);
-
- /*di_buf: post free*/
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 20, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- dimv3_print("%s\n", __func__);
- i = 0;
- /*set post di_buf->c.di_buf_dup_p[0],[1] as pre ready*/
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= 2) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- break;
- }
- }
- if (i < 2) {
- PR_ERR("%s:Error6\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 21;
-
- recovery_flag++;
- return 0;
- }
-
- #if 0 /*remove vframe 12-03*/
- /*set post buf as top */
- memcpy(di_buf->vframe,
- di_buf->c.di_buf_dup_p[0]->vframe,
- sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- #endif
- /*separate one progressive frame
- * as two interlace fields
- */
- if (prog_tb_field_proc_type == 1) {
- /* do weave by di post */
- #if 0 /*remove vframe 12-03*/
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- if (di_buf->c.di_buf_dup_p[0]->c.new_format_flag)
- di_buf->vframe->early_process_fun = de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun = do_nothing_fun;
- #endif
- di_buf->c.pd_config.global_mode = PULL_DOWN_BUF1;
- #if 0 /*remove vframe 12-03*/
- di_buf->vframe->process_fun =
- (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- #endif
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- /*2019-12-03*/
- di_buf->c.pdvfm = di_buf->c.di_buf_dup_p[0]->c.pdvfm;
- } else if (prog_tb_field_proc_type == 0) {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- /* do weave by vpp */
- PR_ERR("%s:type?\n", __func__);
- #if 0
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE;
- if ((di_buf->c.di_buf_dup_p[0]->c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- #endif
- } else {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- PR_ERR("%s:type2\n", __func__);
- #if 0
- di_buf->vframe->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
-
- di_buf->vframe->width
- = di_buf->c.di_buf_dup_p[0]->c.width_bk;
- if ((di_buf->c.di_buf_dup_p[0]->c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
- if (prog_tb_field_proc_type == 2) {
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
-/* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]->nr_canvas_idx;
- } else {
- /* top */
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]->nr_canvas_idx;
- }
- #endif
- }
-
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.wmode = ready_di_buf->c.wmode;
- di_buf->c.vmode = di_buf->c.di_buf_dup_p[0]->c.vmode;
- queuev3_out(channel, di_buf->c.di_buf[0]);
- di_buf->c.di_buf[0]->c.sts |= EDI_ST_VFM_P_ASI_T;
- /*check if the field is error,then drop*/
- if (!(di_buf->c.di_buf_dup_p[0]->c.wmode.is_top)) {
- di_buf->c.di_buf[1] = di_buf->c.di_buf_dup_p[1] = NULL;
- queuev3_in(channel, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, channel);
- PR_INF("%s drop field %d.\n", __func__,
- di_buf->c.di_buf_dup_p[0]->c.seq);
- } else {
- di_buf->c.di_buf[1] = di_buf->c.di_buf_dup_p[1];
- queuev3_out(channel, di_buf->c.di_buf[1]);
- di_buf->c.di_buf[1]->c.sts |= EDI_ST_VFM_P_ASI_B;
- drop_frame(check_drop/*dimp_get(eDI_MP_check_start_drop_prog)*/,
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag),
- di_buf, channel);
- }
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <prog by field>: ", __func__);
-#endif
- ret = 1;
-
- return ret;
-}
-
-static int dim_pst_vframe_c_bypass_all(unsigned int ch,
- struct di_buf_s *ready_di_buf)
-{
- struct di_buf_s *di_buf = NULL;
- struct di_ch_s *pch;
- struct dim_inter_s *pintf;
-
- pch = get_chdata(ch);
- if (!pch) {
- PR_ERR("%s:no pch\n", __func__);
- return 0;
- }
-
- pintf = &pch->interf;
-
- /*post free*/
- di_buf = div3_que_out_to_di_buf(ch, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 19, ch))
- return 0;
-
- di_buf->c.di_buf_dup_p[0] = ready_di_buf;
- //di_buf_i = di_buf->di_buf_dup_p[0];
- #if 0
- memcpy(di_buf->vframe, ready_di_buf->vframe,
- sizeof(vframe_t));
-
- //di_buf->vframe->width = ready_di_buf->c.width_bk;
- di_buf->vframe->private_data = di_buf;
-
- if (ready_di_buf->c.new_format_flag) {
- pr_info("DI:ch[%d],%d disable post.\n",
- ch,
- __LINE__);
- di_buf->vframe->early_process_fun = de_post_disable_fun;
- } else {
- di_buf->vframe->early_process_fun = do_nothing_fun;
- }
- #endif
- dimv3_print("%s %p,%d,t[%d]\n", __func__, di_buf,
- di_buf->index, di_buf->type);
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL; /*need*/
- di_buf->c.pd_config.global_mode = PULL_DOWN_NORMAL;/*no use*/
- di_buf->c.di_buf[0] = ready_di_buf;
- di_buf->c.di_buf[1] = NULL;
- di_buf->c.wmode = ready_di_buf->c.wmode;
- di_buf->c.pdvfm = ready_di_buf->c.pdvfm;
- /*input buf from pre_ready out*/
- queuev3_out(ch, ready_di_buf);
-
-
- /*post buf to doing*/
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) {
- //PR_INF("%s:\n", __func__);
- //queue_in(ch, di_buf, QUEUE_POST_DOING);
- //di_que_in(ch, QUE_POST_DOING, di_buf);
-
- if (dimv3_tmode_is_localpost(ch))
- div3_que_in(ch, QUE_POST_DOING, di_buf);
- else
- div3_que_in(ch, QUE_POST_NOBUF, di_buf);
-
- }
-
- if (pintf->op_ins_2_doing)
- pintf->op_ins_2_doing(pch, 1, di_buf);
- dimv3_tr_ops.post_do(di_buf->c.vmode.omx_index);
-
- return 1;
-}
-
-/* */
-int dimv3_pst_vframe_top(unsigned int ch)
-{
- int ready_count = div3_que_list_count(ch, QUE_PRE_READY);
- struct di_buf_s *ready_di_buf;
- int buffer_keep_count = 3;
- struct di_buf_s *p[3] = {NULL};
- int itmp;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
-// int i = 0;
- int ret = 0;
- struct di_ch_s *pch;
- struct di_buffer *ins_buf;
-
- pch = get_chdata(ch);
- if (!pch)
- return 0;
-
- if (div3_que_is_empty(ch, QUE_POST_FREE))
- return 0;
- /*add : for now post buf only 3.*/
- //if (list_count(ch, QUEUE_POST_DOING) > 2)
-
- if (div3_que_list_count(ch, QUE_POST_DOING) > 2)
- return 0;
-
- if (ready_count == 0)
- return 0;
-
- ready_di_buf = div3_que_peek(ch, QUE_PRE_READY);
- if (!ready_di_buf) {
- pr_dbg("%s:Error1\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 16;
-
- recovery_flag++;
- return 0;
- }
- /*******************************************/
- if (ready_count >= buffer_keep_count &&
- ready_di_buf->c.wmode.is_i &&
- !ready_di_buf->c.wmode.is_bypass &&
- !ready_di_buf->c.wmode.need_bypass) {
-
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < buffer_keep_count; itmp++)
- p[itmp] = pwv3_qindex_2_buf(ch, tmpa[itmp]);
-
- if (p[2]->c.wmode.is_bypass ||
- p[1]->c.wmode.is_bypass ||
- !p[1]->c.wmode.is_i) {
- /**/
- p[1]->c.wmode.is_bypass = 1;
-
- /*********************/
- if (p[1]->c.pdvfm && p[1]->c.pdvfm->vfm_in) {
- ins_buf =
- (struct di_buffer *)p[1]->c.pdvfm->vfm_in;
- ins_buf->flag |= DI_FLAG_BUF_BY_PASS;
- #if 0
- /*dec vf keep*/
- if (p[1]->c.in_buf) {
- queuev3_in(ch, p[1]->c.in_buf,
- QUEUE_RECYCLE);
- p[1]->c.in_buf = NULL;
- dimv3_print("%s:recy dec vf;%d,t[%d]\n",
- __func__,
- p[1]->index, p[1]->type);
- } else {
- PR_INF("%s:p:%d,t[%d]\n", __func__,
- p[1]->index, p[1]->type);
- }
- #endif
- PR_INF("%s:%d, to bypass\n", __func__,
- ins_buf->mng.index);
- } else {
- PR_ERR("%s bypass no input?\n", __func__);
- }
- //p[0]->c.wmode.is_bypass = 1;
- /*drop p[0] dummy*/
- queuev3_out(ch, p[0]);
-
- /*dec vf keep*/
- if (p[0]->c.in_buf) {
- queuev3_in(ch, p[0]->c.in_buf, QUEUE_RECYCLE);
- p[0]->c.in_buf = NULL;
- dimv3_print("%s:recydecvf;%d,t[%d]\n", __func__,
- p[0]->index, p[0]->type);
- } else {
- PR_INF("%s:p:%d,t[%d]\n", __func__,
- p[0]->index, p[0]->type);
- }
- queuev3_in(ch, p[0], QUEUE_RECYCLE);
- /*p1 to bypass*/
- return 1;
- }
- }
- #if 0
- /*******************************************/
- if ((ready_di_buf->c.post_proc_flag) &&
- (ready_count >= buffer_keep_count)) {
- i = 0;
-
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) { /*ary:for what?*/
- p[0] = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- /* if(p->post_proc_flag == 0){ */
- if (p[0]->type == VFRAME_TYPE_IN) {
- ready_di_buf->c.post_proc_flag = -1;
- ready_di_buf->c.new_format_flag = 1;
- }
- i++;
- if (i > 2)
- break;
- }
- }
- #endif
- if (ready_di_buf->c.wmode.is_bypass) {
- dbg_dbg("%s:i[%d],%d\n", __func__,
- ready_di_buf->c.pdvfm->index,
- ready_di_buf->c.wmode.is_bypass);
- ret = dim_pst_vframe_c_bypass_all(ch, ready_di_buf);
- } else if (ready_di_buf->c.wmode.p_use_2i) {
- ret = dim_pst_vframe_p_used2ibuf(ch, ready_di_buf);
- } else if (ready_di_buf->c.wmode.p_as_i) {
- ret = dim_pst_vframe_p_as_i(ch, ready_di_buf);
- } else if (ready_di_buf->c.post_proc_flag > 0) {
- if (ready_count >= buffer_keep_count) {
- if (ready_di_buf->c.wmode.is_i)
- ret = dim_pst_vframe_i(ch, ready_di_buf);
- else
- ret = dim_pst_vframe_a(ch, ready_di_buf);
- }
-
- } else if (!ready_di_buf->c.post_proc_flag &&
- ready_di_buf->type == VFRAME_TYPE_IN) {
- /*bypass mode*/
- ret = dim_pst_vframe_c_bypass_all(ch, ready_di_buf);
- } else {
- dimv3_print("vfm_top other\n");
- ret = dim_pst_vframe_b(ch, ready_di_buf);
- }
-
- return ret;
-}
-
-int dimv3_process_post_vframe(unsigned int channel)
-{
-
- #if 0
-/*
- * 1) get buf from post_free_list, config it according to buf
- * in pre_ready_list, send it to post_ready_list
- * (it will be send to post_free_list in di_vf_put())
- * 2) get buf from pre_ready_list, attach it to buf from post_free_list
- * (it will be send to recycle_list in di_vf_put() )
- */
- ulong irq_flag2 = 0;
- int i = 0;
- int ret = 0;
- int buffer_keep_count = 3;
- struct di_buf_s *di_buf = NULL;
- struct di_buf_s *ready_di_buf;
- struct di_buf_s *p = NULL;/* , *ptmp; */
- int itmp;
- /* new que int ready_count = list_count(channel, QUEUE_PRE_READY);*/
- int ready_count = div3_que_list_count(channel, QUE_PRE_READY);
- bool check_drop = false;
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
-
-#if 1
- if (div3_que_is_empty(channel, QUE_POST_FREE))
- return 0;
- /*add : for now post buf only 3.*/
- //if (list_count(channel, QUEUE_POST_DOING) > 2)
- if (div3_que_list_count(channel, QUE_POST_DOING) > 2)
- return 0;
-#else
- /*for post write mode ,need reserved a post free buf;*/
- if (div3_que_list_count(channel, QUE_POST_FREE) < 2)
- return 0;
-#endif
- if (ready_count == 0)
- return 0;
-
- ready_di_buf = div3_que_peek(channel, QUE_PRE_READY);
- if (!ready_di_buf || !ready_di_buf->vframe) {
- pr_dbg("%s:Error1\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 16;
-
- recovery_flag++;
- return 0;
- }
- dimv3_print("%s:1 ready_count[%d]:post_proc_flag[%d]\n", __func__,
- ready_count, ready_di_buf->c.post_proc_flag);
- if ((ready_di_buf->c.post_proc_flag) &&
- (ready_count >= buffer_keep_count)) {
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- /* if(p->post_proc_flag == 0){ */
- if (p->type == VFRAME_TYPE_IN) {
- ready_di_buf->c.post_proc_flag = -1;
- ready_di_buf->c.new_format_flag = 1;
- }
- i++;
- if (i > 2)
- break;
- }
- }
- if (ready_di_buf->c.post_proc_flag > 0) {
- if (ready_count >= buffer_keep_count) {
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 17, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- dimv3_print("di:keep[%d]:t[%d]:idx[%d]\n",
- i, tmpa[itmp], p->index);
- di_buf->c.di_buf_dup_p[i++] = p;
-
- if (i >= buffer_keep_count)
- break;
- }
- if (i < buffer_keep_count) {
- PR_ERR("%s:3\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 18;
- recovery_flag++;
- return 0;
- }
-
- memcpy(di_buf->vframe,
- di_buf->c.di_buf_dup_p[1]->vframe,
- sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
- if (di_buf->c.di_buf_dup_p[1]->c.post_proc_flag == 3) {
- /* dummy, not for display */
- inc_post_ref_count(di_buf);
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, di_buf->c.di_buf[0]);
- di_lock_irqfiq_save(irq_flag2);
- queuev3_in(channel, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
- dimv3_print("%s <dummy>: ", __func__);
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <dummy>: ", __func__);
-#endif
- } else {
- if (di_buf->c.di_buf_dup_p[1]->c.post_proc_flag
- == 2) {
- di_buf->c.pd_config.global_mode
- = PULL_DOWN_BLEND_2;
- /* blend with di_buf->di_buf_dup_p[2] */
- } else {
- set_pulldown_mode(di_buf, channel);
- }
- di_buf->vframe->type =
- VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
-
- di_buf->vframe->width
- = di_buf->c.di_buf_dup_p[1]->c.width_bk;
-
- if (di_buf->c.di_buf_dup_p[1]->c.new_format_flag) {
- /* if (di_buf->di_buf_dup_p[1]
- * ->post_proc_flag == 2) {
- */
- di_buf->vframe->early_process_fun =
- de_post_disable_fun;
- } else {
- di_buf->vframe->early_process_fun =
- do_nothing_fun;
- }
-
- if (di_buf->c.di_buf_dup_p[1]->type == VFRAME_TYPE_IN) {
- /* next will be bypass */
- di_buf->vframe->type
- = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx; /* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx;
- di_buf->vframe->process_fun =
- NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- } else {
- /*for debug*/
- if (dimp_get(eDI_MP_debug_blend_mode) != -1)
- di_buf->c.pd_config.global_mode
- = dimp_get(eDI_MP_debug_blend_mode);
-
- di_buf->vframe->process_fun =
-((dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) ?
- NULL : dimv3_post_process);
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- inc_post_ref_count(di_buf);
- }
- di_buf->c.di_buf[0] /*ary:di_buf_di_buf*/
- = di_buf->c.di_buf_dup_p[0];
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, di_buf->c.di_buf[0]);
-
- drop_frame(true,
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[2]->c.throw_flag),
- di_buf, channel);
-
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <interlace>: ", __func__);
-#endif
- if (!(dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)))
- pwv3_vf_notify_receiver(channel,
-VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
- }
- ret = 1;
- }
- } else {
- if (is_progressive(ready_di_buf->vframe) ||
- ready_di_buf->type == VFRAME_TYPE_IN ||
- ready_di_buf->c.post_proc_flag < 0 ||
- dimp_get(eDI_MP_bypass_post_state)
- ){
- int vframe_process_count = 1;
-#ifdef DET3D
- int dual_vframe_flag = 0;
-
- if ((ppre->vframe_interleave_flag &&
- ready_di_buf->c.left_right) ||
- (dimp_get(eDI_MP_bypass_post) & 0x100)) {
- dual_vframe_flag = 1;
- vframe_process_count = 2;
- }
-#endif
- if (dimp_get(eDI_MP_skip_top_bot) &&
- (!is_progressive(ready_di_buf->vframe)))
- vframe_process_count = 2;
-
- if (ready_count >= vframe_process_count) {
- struct di_buf_s *di_buf_i;
-
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 19, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel,
- tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= vframe_process_count) {
- di_buf->c.di_buf_dup_p[i]
- = NULL;
- di_buf->c.di_buf_dup_p[i + 1]
- = NULL;
- break;
- }
- }
- if (i < vframe_process_count) {
- PR_ERR("%s:6\n", __func__);
- if (recovery_flag == 0)
- recovery_log_reason = 22;
-
- recovery_flag++;
- return 0;
- }
-
- di_buf_i = di_buf->c.di_buf_dup_p[0];
- if (!is_progressive(ready_di_buf->vframe) &&
- ((dimp_get(eDI_MP_skip_top_bot) == 1) ||
- (dimp_get(eDI_MP_skip_top_bot) == 2))) {
- unsigned int frame_type =
- di_buf->c.di_buf_dup_p[1]->
- vframe->type &
- VIDTYPE_TYPEMASK;
- if (dimp_get(eDI_MP_skip_top_bot)
- == 1) {
- di_buf_i = (frame_type ==
- VIDTYPE_INTERLACE_TOP)
- ? di_buf->c.di_buf_dup_p[1]
- : di_buf->c.di_buf_dup_p[0];
- } else if (
- dimp_get(eDI_MP_skip_top_bot)
- == 2) {
- di_buf_i = (frame_type ==
- VIDTYPE_INTERLACE_BOTTOM)
- ? di_buf->c.di_buf_dup_p[1]
- : di_buf->c.di_buf_dup_p[0];
- }
- }
-
- memcpy(di_buf->vframe, di_buf_i->vframe,
- sizeof(vframe_t));
-
- di_buf->vframe->width = di_buf_i->c.width_bk;
- di_buf->vframe->private_data = di_buf;
-
- if (ready_di_buf->c.new_format_flag &&
- (ready_di_buf->type == VFRAME_TYPE_IN)) {
- PR_INF("ch[%d],%d disable post.\n",
- channel,
- __LINE__);
- di_buf->vframe->early_process_fun
- = de_post_disable_fun;
- } else {
- if (ready_di_buf->type ==
- VFRAME_TYPE_IN)
- di_buf->vframe->
- early_process_fun
- = do_nothing_fun;
-
- else
- di_buf->vframe->
- early_process_fun
- = do_pre_only_fun;
- }
- dimv3_print("%s:2\n", __func__);
- if (ready_di_buf->c.post_proc_flag == -2) {
- di_buf->vframe->type
- |= VIDTYPE_VIU_FIELD;
- di_buf->vframe->type
- &= ~(VIDTYPE_TYPEMASK);
- di_buf->vframe->process_fun
-= (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- di_buf->c.process_fun_index =
- PROCESS_FUN_DI;
- di_buf->c.pd_config.global_mode
- = PULL_DOWN_EI;
- } else {
- di_buf->vframe->process_fun =
- NULL;
- di_buf->c.process_fun_index =
- PROCESS_FUN_NULL;
- di_buf->c.pd_config.global_mode =
- PULL_DOWN_NORMAL;
- }
- di_buf->c.di_buf[0] = ready_di_buf;
- di_buf->c.di_buf[1] = NULL;
- queuev3_out(channel, ready_di_buf);
-
-#ifdef DET3D
- if (dual_vframe_flag) {
- di_buf->c.di_buf[1] =
- di_buf->c.di_buf_dup_p[1];
- queuev3_out(channel,
- di_buf->c.di_buf[1]);
- }
-#endif
- drop_frame(check_drop,
- di_buf->c.di_buf[0]->c.throw_flag,
- di_buf, channel);
-
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print(
- "%s <prog by frame>: ",
- __func__);
-#endif
- ret = 1;
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
- }
- } else if (ready_count >= 2) {
- /*for progressive input,type
- * 1:separate tow fields,type
- * 2:bypass post as frame
- */
- unsigned char prog_tb_field_proc_type =
- (dimp_get(eDI_MP_prog_proc_config) >> 1) & 0x3;
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = div3_que_out_to_di_buf(channel, QUE_POST_FREE);
- if (dimv3_check_di_buf(di_buf, 20, channel)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return 0;
- }
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- i = 0;
-
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- di_buf->c.di_buf_dup_p[i++] = p;
- if (i >= 2) {
- di_buf->c.di_buf_dup_p[i] = NULL;
- break;
- }
- }
- if (i < 2) {
- PR_ERR("%s:Error6\n", __func__);
-
- if (recovery_flag == 0)
- recovery_log_reason = 21;
-
- recovery_flag++;
- return 0;
- }
-
- memcpy(di_buf->vframe,
- di_buf->c.di_buf_dup_p[0]->vframe,
- sizeof(vframe_t));
- di_buf->vframe->private_data = di_buf;
-
- /*separate one progressive frame
- * as two interlace fields
- */
- if (prog_tb_field_proc_type == 1) {
- /* do weave by di post */
- di_buf->vframe->type =
- VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- if (
- di_buf->c.di_buf_dup_p[0]->
- c.new_format_flag)
- di_buf->vframe->
- early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->
- early_process_fun =
- do_nothing_fun;
-
- di_buf->c.pd_config.global_mode =
- PULL_DOWN_BUF1;
- di_buf->vframe->process_fun =
-(dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) ? NULL :
- dimv3_post_process;
- di_buf->c.process_fun_index = PROCESS_FUN_DI;
- } else if (prog_tb_field_proc_type == 0) {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- /* do weave by vpp */
- di_buf->vframe->type =
- VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE;
- if (
- (di_buf->c.di_buf_dup_p[0]->
- c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->
- early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->
- early_process_fun =
- do_nothing_fun;
- di_buf->vframe->process_fun = NULL;
- di_buf->c.process_fun_index = PROCESS_FUN_NULL;
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]->
- nr_canvas_idx;
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]->
- nr_canvas_idx;
- } else {
- /* to do: need change for
- * DI_USE_FIXED_CANVAS_IDX
- */
- di_buf->vframe->type =
- VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD |
- VIDTYPE_PRE_INTERLACE;
- di_buf->vframe->height >>= 1;
-
- di_buf->vframe->width
- = di_buf->c.di_buf_dup_p[0]->c.width_bk;
- if (
- (di_buf->c.di_buf_dup_p[0]->
- c.new_format_flag) ||
- (Rd(DI_IF1_GEN_REG) & 1))
- di_buf->vframe->
- early_process_fun =
- de_post_disable_fun;
- else
- di_buf->vframe->
- early_process_fun =
- do_nothing_fun;
- if (prog_tb_field_proc_type == 2) {
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx;
-/* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[0]
- ->nr_canvas_idx;
- } else {
- di_buf->vframe->canvas0Addr =
- di_buf->c.di_buf_dup_p[1]
- ->nr_canvas_idx; /* top */
- di_buf->vframe->canvas1Addr =
- di_buf->c.di_buf_dup_p[1]
- ->nr_canvas_idx;
- }
- }
-
- di_buf->c.di_buf[0] = di_buf->c.di_buf_dup_p[0];
- queuev3_out(channel, di_buf->c.di_buf[0]);
- /*check if the field is error,then drop*/
- if (
- (di_buf->c.di_buf_dup_p[0]->vframe->type &
- VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_BOTTOM) {
- di_buf->c.di_buf[1] =
- di_buf->c.di_buf_dup_p[1] = NULL;
- queuev3_in(channel, di_buf, QUEUE_TMP);
- recycle_vframe_type_post(di_buf, channel);
- pr_dbg("%s drop field %d.\n", __func__,
- di_buf->c.di_buf_dup_p[0]->c.seq);
- } else {
- di_buf->c.di_buf[1] =
- di_buf->c.di_buf_dup_p[1];
- queuev3_out(channel, di_buf->c.di_buf[1]);
-
- drop_frame(
- dimp_get(eDI_MP_check_start_drop_prog),
- (di_buf->c.di_buf_dup_p[0]->c.throw_flag) ||
- (di_buf->c.di_buf_dup_p[1]->c.throw_flag),
- di_buf, channel);
- }
- frame_count++;
-#ifdef DI_BUFFER_DEBUG
- dimv3_print("%s <prog by field>: ", __func__);
-#endif
- ret = 1;
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
- }
- }
-
-#ifdef DI_BUFFER_DEBUG
- if (di_buf) {
- dimv3_print("%s[%d](",
- vframe_type_name[di_buf->type], di_buf->index);
- for (i = 0; i < 2; i++) {
- if (di_buf->c.di_buf[i])
- dimv3_print("%s[%d],",
- vframe_type_name[di_buf->c.di_buf[i]->type],
- di_buf->c.di_buf[i]->index);
- }
- dimv3_print(")(vframe type %x dur %d)",
- di_buf->vframe->type, di_buf->vframe->duration);
- if (di_buf->c.di_buf_dup_p[1] &&
- (di_buf->c.di_buf_dup_p[1]->c.post_proc_flag == 3))
- dimv3_print("=> recycle_list\n");
- else
- dimv3_print("=> post_ready_list\n");
- }
-#endif
- return ret;
- #endif
- return 0;
-}
-#if 0
-/*
- * di task
- */
-void dim_unreg_process(unsigned int channel) /*ary no use*/
-{
- unsigned long start_jiffes = 0;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- PR_INF("%s unreg start %d.\n", __func__, get_reg_flag(channel));
- if (get_reg_flag(channel)) {
- start_jiffes = jiffies_64;
- di_vframe_unreg(channel);
- pr_dbg("%s vf unreg cost %u ms.\n", __func__,
- jiffies_to_msecs(jiffies_64 - start_jiffes));
- unreg_cnt++;
- if (unreg_cnt > 0x3fffffff)
- unreg_cnt = 0;
- pr_dbg("%s unreg stop %d.\n", __func__, get_reg_flag(channel));
-
- } else {
- ppre->force_unreg_req_flag = 0;
- ppre->disable_req_flag = 0;
- recovery_flag = 0;
- }
-}
-#endif
-void div3_unreg_setting(void)
-{
- unsigned int mirror_disable = get_blackout_policy();
-
- if (!get_hw_reg_flg()) {
- PR_ERR("%s:have setting?do nothing\n", __func__);
- return;
- }
-
- PR_INF("%s\n", __func__);
- /*set flg*/
- set_hw_reg_flg(false);
-
- dimhv3_enable_di_pre_mif(false, dimp_get(eDI_MP_mcpre_en));
- postv3_close_new(); /*2018-11-29*/
- dimhv3_afbc_reg_sw(false);
- dimhv3_hw_uninit();
- if (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) {
- dimv3_pre_gate_control(false, dimp_get(eDI_MP_mcpre_en));
- get_ops_nr()->nr_gate_control(false);
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) {
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x80f60000);
- dimv3_DI_Wr(DI_PRE_CTRL, 0);
- } else {
- dimv3_DI_Wr(DI_CLKG_CTRL, 0xf60000);
- }
- /*ary add for switch to post wr, can't display*/
- //PR_INF("patch dimh_disable_post_deinterlace_2\n");
- dimhv3_disable_post_deinterlace_2();
- /* nr/blend0/ei0/mtn0 clock gate */
-
- dimv3_hw_disable(dimp_get(eDI_MP_mcpre_en));
-
- if (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) {
- #ifdef DIM_HIS
- dimhv3_enable_di_post_mif(GATE_OFF);
- dimv3_post_gate_control(false);
- #else
- hpstv3_power_ctr(false);
- #endif
- dimv3_top_gate_control(false, false);
- } else {
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x80000000);
- }
- if (!is_meson_gxl_cpu() &&
- !is_meson_gxm_cpu() &&
- !is_meson_gxbb_cpu() &&
- !is_meson_txlx_cpu())
- diextv3_clk_b_sw(false);
- PR_INF("%s disable di mirror image.\n", __func__);
-
-#if 0
- if (mirror_disable) {
- /*no mirror:*/
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support))
- dimv3_set_power_control(0);
-
- } else {
- /*have mirror:*/
- }
-#else /*0624?*/
- if ((dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support)) ||
- mirror_disable) {
- /*diwr_set_power_control(0);*/
- hpstv3_mem_pd_sw(0);
- }
- if (mirror_disable)
- hpstv3_vd1_sw(0);
-#endif
-
- #if 0 /*tmp*/
- if (post_wr_en && post_wr_support)
- dimv3_set_power_control(0);
- #endif
-
- disp_frame_count = 0;/* debug only*/
-}
-
-void div3_unreg_variable(unsigned int channel)
-{
- ulong irq_flag2 = 0;
- unsigned int mirror_disable = 0;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- //struct di_dev_s *de_devp = get_dim_de_devp();
-
-#if (defined ENABLE_SPIN_LOCK_ALWAYS)
- ulong flags = 0;
-
- spin_lock_irqsave(&plistv3_lock, flags);
-#endif
- PR_INF("%s:ch[%d]\n", __func__, channel);
- set_init_flag(channel, false); /*init_flag = 0;*/
- dimv3_sumx_clear(channel);
-
- mirror_disable = get_blackout_policy();
- di_lock_irqfiq_save(irq_flag2);
- dimv3_print("%s: dimv3_uninit_buf\n", __func__);
- dimv3_uninit_buf(mirror_disable, channel);
-
- get_ops_mtn()->adpative_combing_exit();
-
- di_unlock_irqfiq_restore(irq_flag2);
-
-#if (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plistv3_lock, flags);
-#endif
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_REG, false);
-
- ppre->force_unreg_req_flag = 0;
- ppre->disable_req_flag = 0;
- recovery_flag = 0;
- ppre->cur_prog_flag = 0;
-
- if (cfgeq(mem_flg, eDI_MEM_M_cma) ||
- cfgeq(mem_flg, eDI_MEM_M_codec_a) ||
- cfgeq(mem_flg, eDI_MEM_M_codec_b))
- dipv3_wq_cma_run(channel, false);
-
- sum_g_clear(channel);
- sum_p_clear(channel);
- get_chdata(channel)->sum_pst_done = 0;
- di_bypass_state_set(channel, true); /*from unreg any use ?*/
- dbg_reg("%s:end\n", __func__);
-}
-
-void diextv3_clk_b_sw(bool on)
-{
- if (on)
- extv3_ops.switch_vpu_clk_gate_vmod(VPU_VPU_CLKB,
- VPU_CLK_GATE_ON);
- else
- extv3_ops.switch_vpu_clk_gate_vmod(VPU_VPU_CLKB,
- VPU_CLK_GATE_OFF);
-}
-
-#if 0 /*no use*/
-void dim_reg_process(unsigned int channel)
-{
- /*get vout information first time*/
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (get_reg_flag(channel))
- return;
- di_vframe_reg(channel);
-
- ppre->bypass_flag = false;
- reg_cnt++;
- if (reg_cnt > 0x3fffffff)
- reg_cnt = 0;
- dimv3_print("########%s\n", __func__);
-}
-#endif
-
-
-void dimv3_rdma_init(void)
-{
-
-}
-
-void dimv3_rdma_exit(void)
-{
-#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- /* rdma handle */
- if (de_devp->rdma_handle > 0)
- rdma_unregister(de_devp->rdma_handle);
-#endif
-}
-
-static void di_load_pq_table(void)
-{
- struct di_pq_parm_s *pos = NULL, *tmp = NULL;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (atomic_read(&de_devp->pq_flag) == 0 &&
- (de_devp->flags & DI_LOAD_REG_FLAG)) {
- atomic_set(&de_devp->pq_flag, 1);
- list_for_each_entry_safe(pos, tmp,
- &de_devp->pq_table_list, list) {
- dimhv3_load_regs(pos);
- list_del(&pos->list);
- di_pq_parm_destroy(pos);
- }
- de_devp->flags &= ~DI_LOAD_REG_FLAG;
- atomic_set(&de_devp->pq_flag, 0);
- }
-}
-
-static void di_pre_size_change(unsigned short width,
- unsigned short height,
- unsigned short vf_type,
- unsigned int channel)
-{
- unsigned int blkhsize = 0;
- int pps_w = 0, pps_h = 0;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- /*pr_info("%s:\n", __func__);*/
- /*debug only:*/
- /*di_pause(channel, true);*/
- get_ops_nr()->nr_all_config(width, height, vf_type);
- #ifdef DET3D
- /*det3d_config*/
- get_ops_3d()->det3d_config(dimp_get(eDI_MP_det3d_en) ? 1 : 0);
- #endif
- if (dimp_get(eDI_MP_pulldown_enable)) {
- /*pulldown_init(width, height);*/
- get_ops_pd()->init(width, height);
- dimhv3_init_field_mode(height);
-
- if (is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_gxlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu())
- dimv3_film_mode_win_config(width, height);
- }
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimhv3_combing_pd22_window_config(width, height);
- dimv3_RDMA_WR(DI_PRE_SIZE, (width - 1) |
- ((height - 1) << 16));
-
- if (dimp_get(eDI_MP_mcpre_en)) {
- blkhsize = (width + 4) / 5;
- dimv3_RDMA_WR(MCDI_HV_SIZEIN, height
- | (width << 16));
- dimv3_RDMA_WR(MCDI_HV_BLKSIZEIN, (overturn ? 3 : 0) << 30
- | blkhsize << 16 | height);
- dimv3_RDMA_WR(MCDI_BLKTOTAL, blkhsize * height);
- if (is_meson_gxlx_cpu()) {
- dimv3_RDMA_WR(MCDI_PD_22_CHK_FLG_CNT, 0);
- dimv3_RDMA_WR(MCDI_FIELD_MV, 0);
- }
- }
- if (channel == 0 ||
- (channel == 1 && !get_reg_flag(0)))
- di_load_pq_table();
- #ifdef OLD_PRE_GL
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimv3_RDMA_WR(DI_PRE_GL_CTRL, 0x80000005);
- #endif
- if (de_devp->nrds_enable)
- dimv3_nr_ds_init(width, height);
- if (de_devp->pps_enable && dimp_get(eDI_MP_pps_position)) {
- pps_w = ppre->cur_width;
- pps_h = ppre->cur_height >> 1;
- dimv3_pps_config(1, pps_w, pps_h,
- dimp_get(eDI_MP_pps_dstw),
- (dimp_get(eDI_MP_pps_dsth) >> 1));
- }
-
- if (is_meson_sm1_cpu() || is_meson_tm2_cpu()) {
- if (de_devp->h_sc_down_en) {
- pps_w = ppre->cur_width;
- dimv3_inp_hsc_setting(pps_w,
- dimp_get(eDI_MP_pre_hsc_down_width));
- } else {
- dimv3_inp_hsc_setting(ppre->cur_width,
- ppre->cur_width);
- }
- }
-
- #if 0
- dimhv3_interrupt_ctrl(ppre->madi_enable,
- det3d_en ? 1 : 0,
- de_devp->nrds_enable,
- post_wr_en,
- ppre->mcdi_enable);
- #else
- /*dimh_int_ctr(0, 0, 0, 0, 0, 0);*/
- dimhv3_int_ctr(1, ppre->madi_enable,
- dimp_get(eDI_MP_det3d_en) ? 1 : 0,
- de_devp->nrds_enable,
- dimp_get(eDI_MP_post_wr_en),
- ppre->mcdi_enable);
- #endif
-}
-#if 0
-static bool need_bypass(struct vframe_s *vf)
-{
- if (vf->type & VIDTYPE_MVC)
- return true;
-
- if (vf->source_type == VFRAME_SOURCE_TYPE_PPMGR)
- return true;
-
- if (vf->type & VIDTYPE_VIU_444)
- return true;
-
- if (vf->type & VIDTYPE_PIC)
- return true;
-#if 0
- if (vf->type & VIDTYPE_COMPRESS)
- return true;
-#else
- /*support G12A and TXLX platform*/
- if (vf->type & VIDTYPE_COMPRESS) {
- if (!dimhv3_afbc_is_supported())
- return true;
- if ((vf->compHeight > (default_height + 8)) ||
- (vf->compWidth > default_width))
- return true;
- }
-#endif
- if ((vf->width > default_width) ||
- (vf->height > (default_height + 8)))
- return true;
-#if 0
- if (vfv3_type_is_prog(vf->type)) {/*temp bypass p*/
- return true;
- }
-#endif
- /*true bypass for 720p above*/
- if ((vf->flag & VFRAME_FLAG_GAME_MODE) &&
- (vf->width > 720))
- return true;
-
- return false;
-}
-#endif
-/*********************************
- *
- * setting register only call when
- * from di_reg_process_irq
- *********************************/
-void div3_reg_setting(unsigned int channel, struct vframe_s *vframe,
- struct dim_wmode_s *pwmode)
-{
- unsigned short nr_height = 0, first_field_type;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- PR_INF("%s:ch[%d]:for first ch reg:\n", __func__, channel);
-
- if (get_hw_reg_flg()) {
- PR_ERR("%s:have setting?do nothing\n", __func__);
- return;
- }
- /*set flg*/
- set_hw_reg_flg(true);
-
- diextv3_clk_b_sw(true);
-
- dimv3_ddbg_mod_save(eDI_DBG_MOD_REGB, channel, 0);
-
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support))
- dimv3_set_power_control(1);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
- /*if (!use_2_interlace_buff) {*/
- if (1) {
- dimv3_top_gate_control(true, true);
- /* dim_post_gate_control(true);*/
- /* freerun for reg configuration */
- /* dimh_enable_di_post_mif(GATE_AUTO);*/
- hpstv3_power_ctr(true);
- } else {
- dimv3_top_gate_control(true, false);
- }
- de_devp->flags |= DI_VPU_CLKB_SET;
- #if 1 /*set clkb to max */
- if (is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()
- ) {
- #ifdef CLK_TREE_SUPPORT
- clk_set_rate(de_devp->vpu_clkb,
- de_devp->clkb_max_rate);
- #endif
- }
- #endif
- dimhv3_enable_di_pre_mif(false, dimp_get(eDI_MP_mcpre_en));
- dimv3_pre_gate_control(true, dimp_get(eDI_MP_mcpre_en));
- dimv3_rst_protect(true);/*2019-01-22 by VLSI feng.wang*/
- dimv3_pre_nr_wr_done_sel(true);
- get_ops_nr()->nr_gate_control(true);
- } else {
- /* if mcdi enable DI_CLKG_CTRL should be 0xfef60000 */
- dimv3_DI_Wr(DI_CLKG_CTRL, 0xfef60001);
- /* nr/blend0/ei0/mtn0 clock gate */
- }
- /*--------------------------*/
- dimv3_init_setting_once();
- /*--------------------------*/
- /*div3_post_reset();*/ /*add by feijun 2018-11-19 */
- postv3_mif_sw(false);
- postv3_dbg_contr();
- /*--------------------------*/
-
- //nr_height = (vframe->height >> 1);/*temp*/
- nr_height = pwmode->src_h >> 1;
- /*--------------------------*/
- dimhv3_calc_lmv_init();
- first_field_type = (vframe->type & VIDTYPE_TYPEMASK);
- //di_pre_size_change(vframe->width, nr_height,
- // first_field_type, channel);
- di_pre_size_change(pwmode->src_w, nr_height,
- first_field_type, channel);
- get_ops_nr()->cue_int(vframe);
- dimv3_ddbg_mod_save(eDI_DBG_MOD_REGE, channel, 0);
-
- /*--------------------------*/
- /*test*/
- dimhv3_int_ctr(0, 0, 0, 0, 0, 0);
-}
-
-/*********************************
- *
- * setting variable
- * from di_reg_process_irq
- *
- *********************************/
-#if 0
-void di_reg_variable(unsigned int channel,
- struct dim_dvfm_s *pdvfm)
-{
- ulong irq_flag2 = 0;
- #ifndef RUN_DI_PROCESS_IN_IRQ
- ulong flags = 0;
- #endif
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if ((prev3_run_flag != DI_RUN_FLAG_RUN) &&
- (prev3_run_flag != DI_RUN_FLAG_STEP))
- return;
- if (prev3_run_flag == DI_RUN_FLAG_STEP)
- prev3_run_flag = DI_RUN_FLAG_STEP_DONE;
-
- dbg_reg("%s:\n", __func__);
-
- dimv3_print("%s:0x%p\n", __func__, pdvfm->vfm_in);
- if (!pdvfm) {
- PR_ERR("%s: nothing\n", __func__);
- return;
- }
- dimv3_tst_4k_reg_val();
- //dip_init_value_reg(channel);/*add 0404 for post*/
-#ifdef DIM_DEBUG_QUE_ERR
- dim_dbg_que_int();
-#endif
- dimv3_ddbg_mod_save(eDI_DBG_MOD_RVB, channel, 0);
- #if 0
- if (need_bypass(vframe) ||
- ((dimp_get(eDI_MP_di_debug_flag) >> 20) & 0x1)) {
- if (!ppre->bypass_flag) {
- PR_INF("%ux%u-0x%x.\n",
- vframe->width,
- vframe->height,
- vframe->type);
- }
- ppre->bypass_flag = true;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- return;
-
- ppre->bypass_flag = false;
- }
- #else
- if (pdvfm->wmode.need_bypass) {
- if (!ppre->bypass_flag) {
- PR_INF("%ux%u-0x%x.\n",
- pdvfm->in_inf.w,
- pdvfm->in_inf.h,
- pdvfm->in_inf.vtype);
- }
- ppre->bypass_flag = true;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- return;
-
- ppre->bypass_flag = false;
- }
- #endif
- /* patch for vdin progressive input */
- #if 0
- if ((is_from_vdin(vframe) &&
- is_progressive(vframe))
- #else
- if ((pdvfm->wmode.is_vdin &&
- !pdvfm->wmode.is_i)
- #endif
- #ifdef DET3D
- || dimp_get(eDI_MP_det3d_en)
- #endif
- || (dimp_get(eDI_MP_use_2_interlace_buff) & 0x2)
- ) {
- dimp_set(eDI_MP_use_2_interlace_buff, 1);
- } else {
- dimp_set(eDI_MP_use_2_interlace_buff, 0);
- }
- de_devp->nrds_enable = dimp_get(eDI_MP_nrds_en);
- de_devp->pps_enable = dimp_get(eDI_MP_pps_en);
- /*di pre h scaling down: sm1 tm2*/
- de_devp->h_sc_down_en = di_mp_uit_get(eDI_MP_pre_hsc_down_en);
-
- if (dimp_get(eDI_MP_di_printk_flag) & 2)
- dimp_set(eDI_MP_di_printk_flag, 1);
-
- dimv3_print("%s: vframe come => di_init_buf\n", __func__);
-
- if (cfgeq(mem_flg, eDI_MEM_M_rev) && !de_devp->mem_flg)
- dimv3_rev_mem_check();
-
- /*(is_progressive(vframe) && (prog_proc_config & 0x10)) {*/
- if (0) {
-#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_lock_irqsave(&plistv3_lock, flags);
-#endif
- di_lock_irqfiq_save(irq_flag2);
- /*
- * 10 bit mode need 1.5 times buffer size of
- * 8 bit mode, init the buffer size as 10 bit
- * mode size, to make sure can switch bit mode
- * smoothly.
- */
- di_init_buf(default_width, default_height, 1, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
-#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plistv3_lock, flags);
-#endif
- } else {
-#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_lock_irqsave(&plistv3_lock, flags);
-#endif
- di_lock_irqfiq_save(irq_flag2);
- /*
- * 10 bit mode need 1.5 times buffer size of
- * 8 bit mode, init the buffer size as 10 bit
- * mode size, to make sure can switch bit mode
- * smoothly.
- */
- di_init_buf(default_width, default_height, 0, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
-#if (!(defined RUN_DI_PROCESS_IN_IRQ)) || (defined ENABLE_SPIN_LOCK_ALWAYS)
- spin_unlock_irqrestore(&plistv3_lock, flags);
-#endif
- }
-
- ppre->mtn_status =
- #if 0
- get_ops_mtn()->adpative_combing_config(vframe->width,
- (vframe->height >> 1),
- (vframe->source_type),
- is_progressive(vframe),
- vframe->sig_fmt);
- #else
- get_ops_mtn()->adpative_combing_config(pdvfm->in_inf.w,
- (pdvfm->in_inf.h >> 1),
- (pdvfm->in_inf.src_type),
- !pdvfm->wmode.is_i,
- pdvfm->in_inf.sig_fmt);
- #endif
-
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_REG, true);
- div3_sum_reg_init(channel);
-
- set_init_flag(channel, true);/*init_flag = 1;*/
-
- dimv3_ddbg_mod_save(eDI_DBG_MOD_RVE, channel, 0);
-
-}
-#else
-
-void di_reg_variable_needbypass(unsigned int channel,
- struct dim_dvfm_s *pdvfm)
-{
-// ulong irq_flag2 = 0;
- //#ifndef RUN_DI_PROCESS_IN_IRQ
-// ulong flags = 0;
- //#endif
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-// struct di_dev_s *de_devp = get_dim_de_devp();
-
- dbg_reg("%s:\n", __func__);
-
- if (!pdvfm) {
- PR_ERR("%s: nothing\n", __func__);
- return;
- }
- dimv3_print("%s:0x%p\n", __func__, pdvfm->vfm_in);
-
- dimv3_tst_4k_reg_val();
- //dip_init_value_reg(channel);/*add 0404 for post*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_RVB, channel, 0);
-
- if (pdvfm->wmode.need_bypass) {
- if (!ppre->bypass_flag) {
- PR_INF("%ux%u-0x%x.\n",
- pdvfm->in_inf.w,
- pdvfm->in_inf.h,
- pdvfm->wmode.vtype);
- }
- ppre->bypass_flag = true;
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_OTHER, false);
- return;
- }
-
-}
-
-void di_reg_variable_normal(unsigned int channel,
- struct dim_dvfm_s *pdvfm)
-{
- ulong irq_flag2 = 0;
- #ifndef RUN_DI_PROCESS_IN_IRQ
- ulong flags = 0;
- #endif
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- dbg_reg("%s:\n", __func__);
-
- dim_dbg_delay_mask_set(0);
-
- if (!pdvfm) {
- PR_ERR("%s: nothing\n", __func__);
- return;
- }
- dimv3_print("%s:0x%p\n", __func__, pdvfm->vfm_in);
-
- dimv3_tst_4k_reg_val();
- //dip_init_value_reg(channel);/*add 0404 for post*/
- dimv3_ddbg_mod_save(eDI_DBG_MOD_RVB, channel, 0);
-
- ppre->bypass_flag = false;
- /* patch for vdin progressive input */
-
- #if 0
- if ((pdvfm->wmode.is_vdin &&
- !pdvfm->wmode.is_i)
- || (dimp_get(eDI_MP_use_2_interlace_buff) & 0x2)
- ) {
- dimp_set(eDI_MP_use_2_interlace_buff, 1);
- } else {
- dimp_set(eDI_MP_use_2_interlace_buff, 0);
- }
- #else
- if ((pdvfm->wmode.is_vdin && !pdvfm->wmode.is_i) ||
- (cfgg(PMODE) == 2)) {
- dimp_set(eDI_MP_use_2_interlace_buff, 1);
- } else {
- dimp_set(eDI_MP_use_2_interlace_buff, 0);
- }
- #endif
- de_devp->nrds_enable = dimp_get(eDI_MP_nrds_en);
- de_devp->pps_enable = dimp_get(eDI_MP_pps_en);
- dbg_reg("pps_enable[%d]\n", de_devp->pps_enable);
- /*di pre h scaling down: sm1 tm2*/
- //de_devp->h_sc_down_en = dimp_get(eDI_MP_pre_hsc_down_en);
- //PR_INF("pps2[%d]\n",de_devp->h_sc_down_en);
-
- if (dimp_get(eDI_MP_di_printk_flag) & 2)
- dimp_set(eDI_MP_di_printk_flag, 1);
-
- dimv3_print("%s: vframe come => di_init_buf\n", __func__);
-
- if (cfgeq(mem_flg, eDI_MEM_M_rev) && !de_devp->mem_flg)
- dimv3_rev_mem_check();
-
- /*(is_progressive(vframe) && (prog_proc_config & 0x10)) {*/
- if (0) {
-
- spin_lock_irqsave(&plistv3_lock, flags);
-
- di_lock_irqfiq_save(irq_flag2);
- /*
- * 10 bit mode need 1.5 times buffer size of
- * 8 bit mode, init the buffer size as 10 bit
- * mode size, to make sure can switch bit mode
- * smoothly.
- */
- di_init_buf(default_width, default_height, 1, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
-
- spin_unlock_irqrestore(&plistv3_lock, flags);
-
- } else {
-
- spin_lock_irqsave(&plistv3_lock, flags);
-
- di_lock_irqfiq_save(irq_flag2);
- /*
- * 10 bit mode need 1.5 times buffer size of
- * 8 bit mode, init the buffer size as 10 bit
- * mode size, to make sure can switch bit mode
- * smoothly.
- */
- di_init_buf(default_width, default_height, 0, channel);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
-
- spin_unlock_irqrestore(&plistv3_lock, flags);
-
- }
-
- ppre->mtn_status =
- #if 0
- get_ops_mtn()->adpative_combing_config(vframe->width,
- (vframe->height >> 1),
- (vframe->source_type),
- is_progressive(vframe),
- vframe->sig_fmt);
- #else
- get_ops_mtn()->adpative_combing_config(pdvfm->in_inf.w,
- (pdvfm->in_inf.h >> 1),
- (pdvfm->in_inf.src_type),
- !pdvfm->wmode.is_i,
- pdvfm->in_inf.sig_fmt);
- #endif
-
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_REG, true);
- div3_sum_reg_init(channel);
-
- set_init_flag(channel, true);/*init_flag = 1;*/
-
- dimv3_ddbg_mod_save(eDI_DBG_MOD_RVE, channel, 0);
-
-}
-
-#endif
-/*para 1 not use*/
-
-/*
- * provider/receiver interface
- */
-
-/*************************/
-#if 0
-int di_ori_event_unreg(unsigned int channel)
-{
- //struct di_pre_stru_s *ppre = get_pre_stru(channel);
- #if 0
- pr_dbg("%s , is_bypass() %d bypass_all %d\n",
- __func__,
- dim_is_bypass(NULL, channel),
- /*trick_mode,*/
- div3_cfgx_get(channel, eDI_CFGX_BYPASS_ALL));
- #endif
-
- /*dbg_ev("%s:unreg\n", __func__);*/
- dipv3_even_unreg_val(channel); /*new*/
-
- /*ppre->vdin_source = false; no use*/
-
- dipv3_event_unreg_chst(channel);
-
- //move to unreg di_bypass_state_set(channel, true);
-
- dbg_ev("ch[%d]unreg end\n", channel);
- return 0;
-}
-#endif
-#if 0
-int di_ori_event_reg(void *data, unsigned int channel)
-{
- //struct di_pre_stru_s *ppre = get_pre_stru(channel);
- //struct di_post_stru_s *ppost = get_post_stru(channel);
- //struct di_dev_s *de_devp = get_dim_de_devp();
-
- dipv3_even_reg_init_val(channel);
-
- #if 0 /*no use*/
- if (de_devp->flags & DI_SUSPEND_FLAG) {
- PR_ERR("reg event device hasn't resumed\n");
- return -1;
- }
- #endif
- if (get_reg_flag(channel)) {
- PR_ERR("no muti instance.\n");
- return -1;
- }
- //dbg_ev("reg:%s\n", provider_name);
- //move to variable set di_bypass_state_set(channel, false);
-
- dipv3_event_reg_chst(channel);
-
- #if 0 /*no use*/
- if (strncmp(provider_name, "vdin0", 4) == 0)
- ppre->vdin_source = true;
- else
- ppre->vdin_source = false;
- #endif
- /*ary: need use interface api*/
- /*receiver_name = vf_get_receiver_name(VFM_NAME);*/
- #if 0
- preceiver = vf_get_receiver(div3_rev_name[channel]);
- receiver_name = preceiver->name;
- #endif
- #if 0 /*ary clear run_early_proc_fun_flag*/
- if (receiver_name) {
- if (!strcmp(receiver_name, "amvideo")) {
- ppost->run_early_proc_fun_flag = 0;
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support))
- ppost->run_early_proc_fun_flag = 1;
- } else {
- ppost->run_early_proc_fun_flag = 1;
- PR_INF("set run_early_proc_fun_flag to 1\n");
- }
- } else {
- PR_INF("%s error receiver is null.\n", __func__);
- }
- #endif
- dbg_ev("ch[%d]:reg end\n", channel);
- return 0;
-}
-#endif
-
-int div3_ori_event_qurey_vdin2nr(unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- return ppre->vdin2nr;
-}
-
-int div3_ori_event_reset(unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- void **pvframe_in = getv3_vframe_in(channel);
- int i;
- ulong flags;
-
- /*block*/
- di_blocking = 1;
-
- /*dbg_ev("%s: VFRAME_EVENT_PROVIDER_RESET\n", __func__);*/
- if (//dim_is_bypass(NULL, channel) ||
- di_bypass_state_get(channel) ||
- ppre->bypass_flag) {
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_RESET,
- NULL);
- }
-
- spin_lock_irqsave(&plistv3_lock, flags);
- for (i = 0; i < MAX_IN_BUF_NUM; i++) {
- if (pvframe_in[i])
- pr_dbg("DI:clear vframe_in[%d]\n", i);
-
- pvframe_in[i] = NULL;
- }
- spin_unlock_irqrestore(&plistv3_lock, flags);
- di_blocking = 0;
-
- return 0;
-}
-
-int div3_ori_event_light_unreg(unsigned int channel)
-{
- void **pvframe_in = getv3_vframe_in(channel);
- int i;
- ulong flags;
-
- di_blocking = 1;
-
- pr_dbg("%s: vf_notify_receiver ligth unreg\n", __func__);
-
- spin_lock_irqsave(&plistv3_lock, flags);
- for (i = 0; i < MAX_IN_BUF_NUM; i++) {
- if (pvframe_in[i])
- pr_dbg("DI:clear vframe_in[%d]\n", i);
-
- pvframe_in[i] = NULL;
- }
- spin_unlock_irqrestore(&plistv3_lock, flags);
- di_blocking = 0;
-
- return 0;
-}
-
-int div3_ori_event_light_unreg_revframe(unsigned int channel)
-{
- void **pvframe_in = getv3_vframe_in(channel);
- int i;
- ulong flags;
- struct dim_itf_ops_s *pvfmops;
- struct di_ch_s *pch;
- unsigned char vf_put_flag = 0;
-
- PR_INF("%s:ch[%d]\n", __func__, channel);
-/*
- * do not display garbage when 2d->3d or 3d->2d
- */
- pch = get_chdata(channel);
- pvfmops = &pch->interf.opsi;
-
- spin_lock_irqsave(&plistv3_lock, flags);
- for (i = 0; i < MAX_IN_BUF_NUM; i++) {
- if (pvframe_in[i]) {
- //pw_vf_put(pvframe_in[i], channel);
- pvfmops->put(pvframe_in[i], pch);
- pr_dbg("DI:clear vframe_in[%d]\n", i);
- vf_put_flag = 1;
- }
- pvframe_in[i] = NULL;
- }
- //if (vf_put_flag)
- // pw_vf_notify_provider(channel,
- // VFRAME_EVENT_RECEIVER_PUT, NULL);
-
- spin_unlock_irqrestore(&plistv3_lock, flags);
-
- return 0;
-}
-
-int div3_irq_ori_event_ready(unsigned int channel)
-{
- return 0;
-}
-
-#if 0
-int di_ori_event_ready(unsigned int channel)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (ppre->bypass_flag)
- pwv3_vf_notify_receiver(channel,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
- #if 0 /*hw timer*/
- if (dipv3_chst_get(channel) == eDI_TOP_STATE_REG_STEP1)
- taskv3_send_cmd(LCMD1(eCMD_READY, channel));
- else
- taskv3_send_ready();
-
- div3_irq_ori_event_ready(channel);
- #endif
- return 0;
-}
-#endif
-#if 0 /*move to di_vframe.c*/
-int div3_ori_event_qurey_state(unsigned int channel)
-{
- /*int in_buf_num = 0;*/
- struct vframe_states states;
-
- if (recovery_flag)
- return RECEIVER_INACTIVE;
-
- /*fix for ucode reset method be break by di.20151230*/
- di_vf_l_states(&states, channel);
- if (states.buf_avail_num > 0)
- return RECEIVER_ACTIVE;
-
- if (pwv3_vf_notify_receiver(
- channel,
- VFRAME_EVENT_PROVIDER_QUREY_STATE,
- NULL) == RECEIVER_ACTIVE)
- return RECEIVER_ACTIVE;
-
- return RECEIVER_INACTIVE;
-}
-#endif
-void div3_ori_event_set_3D(int type, void *data, unsigned int channel)
-{
-#ifdef DET3D
-
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (type == VFRAME_EVENT_PROVIDER_SET_3D_VFRAME_INTERLEAVE) {
- int flag = (long)data;
-
- ppre->vframe_interleave_flag = flag;
- }
-
-#endif
-}
-
-/*************************/
-
-/*recycle the buffer for keeping buffer*/
-static void recycle_keep_buffer(unsigned int channel)
-{
- ulong irq_flag2 = 0;
- int i = 0;
- struct di_buf_s *keep_buf;
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- keep_buf = ppost->keep_buf;
- if (!IS_ERR_OR_NULL(keep_buf)) {
- PR_ERR("%s:\n", __func__);
- if (keep_buf->type == VFRAME_TYPE_POST) {
- pr_dbg("%s recycle keep cur di_buf %d (",
- __func__, keep_buf->index);
- di_lock_irqfiq_save(irq_flag2);
- for (i = 0; i < USED_LOCAL_BUF_MAX; i++) {
- if (keep_buf->c.di_buf_dup_p[i]) {
- queuev3_in(channel,
- keep_buf->c.di_buf_dup_p[i],
- QUEUE_RECYCLE);
- pr_dbg(" %d ",
- keep_buf->c.di_buf_dup_p[i]->index);
- }
- }
- div3_que_in(channel, QUE_POST_FREE, keep_buf);
- di_unlock_irqfiq_restore(irq_flag2);
- pr_dbg(")\n");
- }
- ppost->keep_buf = NULL;
- }
-}
-
-/************************************/
-/************************************/
-struct vframe_s *div3_vf_l_get(struct di_ch_s *pch)
-{
- vframe_t *vframe_ret = NULL;
- struct di_buf_s *di_buf = NULL;
-#ifdef DI_DEBUG_POST_BUF_FLOW
- struct di_buf_s *nr_buf = NULL;
-#endif
- unsigned int ch = pch->ch_id;
-
- ulong irq_flag2 = 0;
- //struct di_post_stru_s *ppost = get_post_stru(channel);
-
- if (!get_init_flag(ch) ||
- recovery_flag ||
- di_blocking ||
- !get_reg_flag(ch) ||
- dump_state_flag) {
- dimv3_tr_ops.post_get2(1);
- return NULL;
- }
-
- /**************************/
- if (listv3_count(ch, QUEUE_DISPLAY) > DI_POST_GET_LIMIT) {
- dimv3_tr_ops.post_get2(2);
- return NULL;
- }
- /**************************/
- if (!div3_que_is_empty(ch, QUE_POST_READY)) {
-
- dimv3_log_buffer_state("ge_", ch);
- di_lock_irqfiq_save(irq_flag2);
-
- di_buf = div3_que_out_to_di_buf(ch, QUE_POST_READY);
- if (dimv3_check_di_buf(di_buf, 21, ch)) {
- di_unlock_irqfiq_restore(irq_flag2);
- return NULL;
- }
- /* add it into display_list */
- queuev3_in(ch, di_buf, QUEUE_DISPLAY);
-
- di_unlock_irqfiq_restore(irq_flag2);
-
- if (di_buf) {
- vframe_ret = di_buf->vframe;
-#ifdef DI_DEBUG_POST_BUF_FLOW
- /*move to post_ready_buf_set*/
- nr_buf = di_buf->c.di_buf_dup_p[1];
- if (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support) &&
- (di_buf->c.process_fun_index != PROCESS_FUN_NULL)) {
- #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vframe_ret->canvas0_config[0].phy_addr =
- di_buf->nr_adr;
- vframe_ret->canvas0_config[0].width =
- di_buf->canvas_width[NR_CANVAS],
- vframe_ret->canvas0_config[0].height =
- di_buf->canvas_height;
- vframe_ret->canvas0_config[0].block_mode = 0;
- vframe_ret->plane_num = 1;
- vframe_ret->canvas0Addr = -1;
- vframe_ret->canvas1Addr = -1;
- if (dimp_get(eDI_MP_show_nrwr)) {
- vframe_ret->canvas0_config[0].phy_addr =
- nr_buf->nr_adr;
- vframe_ret->canvas0_config[0].width =
- nr_buf->canvas_width[NR_CANVAS];
- vframe_ret->canvas0_config[0].height =
- nr_buf->canvas_height;
- }
- #else
- config_canvas_idx(di_buf, di_wr_idx, -1);
- vframe_ret->canvas0Addr = di_buf->nr_canvas_idx;
- vframe_ret->canvas1Addr = di_buf->nr_canvas_idx;
- if (dimp_get(eDI_MP_show_nrwr)) {
- config_canvas_idx(nr_buf,
- di_wr_idx, -1);
- vframe_ret->canvas0Addr = di_wr_idx;
- vframe_ret->canvas1Addr = di_wr_idx;
- }
- #endif
- vframe_ret->early_process_fun = dimv3_do_post_wr_fun;
- vframe_ret->process_fun = NULL;
- }
-#endif
- di_buf->c.seq = disp_frame_count;
- atomic_set(&di_buf->c.di_cnt, 1);
- }
- disp_frame_count++;
-
- dimv3_log_buffer_state("get", ch);
- }
- if (vframe_ret) {
- dimv3_print("%s:ch[%d];typ:%s;id[%d];omx[%d] %u ms\n", __func__,
- ch,
- vframe_type_name[di_buf->type],
- di_buf->index,
- vframe_ret->omx_index,
- dim_get_timerms(vframe_ret->ready_jiffies64));
- didbgv3_vframe_out_save(vframe_ret);
-
- dimv3_tr_ops.post_get(vframe_ret->omx_index);
- } else {
- dimv3_tr_ops.post_get2(3);
- }
-
- #if 0 /*clear run_early_proc_fun_flag*/
- if (!dimp_get(eDI_MP_post_wr_en) &&
- ppost->run_early_proc_fun_flag &&
- vframe_ret) {
- if (vframe_ret->early_process_fun == do_pre_only_fun)
- vframe_ret->early_process_fun(vframe_ret->private_data,
- vframe_ret);
- }
- #endif
- return vframe_ret;
-}
-
-void div3_vf_l_put(struct vframe_s *vf, struct di_ch_s *pch)
-{
- struct di_buf_s *di_buf = NULL;
- ulong irq_flag2 = 0;
- unsigned int ch = pch->ch_id;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_post_stru_s *ppost = get_post_stru(ch);
-
- if (ppre->bypass_flag) {
- //pw_vf_put(vf, channel);
- //pw_vf_notify_provider(channel,
- // VFRAME_EVENT_RECEIVER_PUT, NULL);
- if (!IS_ERR_OR_NULL(ppost->keep_buf))
- recycle_keep_buffer(ch);
- return;
- }
-/* struct di_buf_s *p = NULL; */
-/* int itmp = 0; */
- if (!get_init_flag(ch) ||
- recovery_flag ||
- IS_ERR_OR_NULL(vf)) {
- PR_ERR("%s: 0x%p\n", __func__, vf);
- return;
- }
- if (di_blocking)
- return;
- dimv3_log_buffer_state("pu_", ch);
- di_buf = (struct di_buf_s *)vf->private_data;
- if (IS_ERR_OR_NULL(di_buf)) {
- //pw_vf_put(vf, channel);
- //pw_vf_notify_provider(channel,
- // VFRAME_EVENT_RECEIVER_PUT, NULL);
- pch->interf.opsi.put(vf, pch);
- PR_ERR("%s: get vframe %p without di buf\n",
- __func__, vf);
- return;
- }
-
- di_lock_irqfiq_save(irq_flag2);
- if (di_buf->type == VFRAME_TYPE_POST) {
- //di_lock_irqfiq_save(irq_flag2);
-
- /*check if in QUE_POST_DISPLAY*/
- /*di_buf->queue_index = QUEUE_DISPLAY;*/
- if (isv3_in_queue(ch, di_buf, QUEUE_DISPLAY)) {
- di_buf->queue_index = -1;
- div3_que_in(ch, QUE_POST_BACK, di_buf);
- //di_unlock_irqfiq_restore(irq_flag2);
- } else {
- //di_unlock_irqfiq_restore(irq_flag2);
- PR_ERR("%s:not in display %d\n", __func__,
- di_buf->index);
- }
-
- } else {
- //di_lock_irqfiq_save(irq_flag2);
- queuev3_in(ch, di_buf, QUEUE_RECYCLE);
- //di_unlock_irqfiq_restore(irq_flag2);
- }
- di_unlock_irqfiq_restore(irq_flag2);
-
- dimv3_print("%s: ch[%d];typ[%s];id[%d];omxp[%d]\n", __func__,
- ch,
- vframe_type_name[di_buf->type], di_buf->index,
- di_buf->vframe->omx_index);
-
- //task_send_ready(); /*hw timer*/
-}
-
-#ifdef DBG2
-void dimv3_recycle_post_back(unsigned int channel)
-{
- struct di_buf_s *di_buf = NULL;
- unsigned int post_buf_index;
- struct di_buf_s *pbuf_post = get_buf_post(channel);
- ulong irq_flag2 = 0;
-
- struct di_post_stru_s *ppost = get_post_stru(channel);
-
- if (pwv3_queue_empty(channel, QUE_POST_BACK))
- return;
-
- while (pwv3_queue_out(channel, QUE_POST_BACK, &post_buf_index)) {
- /*pr_info("dp2:%d\n", post_buf_index);*/
- if (post_buf_index >= MAX_POST_BUF_NUM) {
- PR_ERR("%s:index is overlfow[%d]\n",
- __func__, post_buf_index);
- break;
- }
- dimv3_print("di_back:%d\n", post_buf_index);
- di_lock_irqfiq_save(irq_flag2); /**/
-
- di_buf = &pbuf_post[post_buf_index];
- if (!atomic_dec_and_test(&di_buf->c.di_cnt))
- PR_ERR("%s,di_cnt > 0\n", __func__);
- recycle_vframe_type_post(di_buf, channel);
- di_unlock_irqfiq_restore(irq_flag2);
- }
- /*back keep_buf:*/
- if (ppost->keep_buf_post) {
- PR_INF("ch[%d]:%s:%d\n",
- channel,
- __func__,
- ppost->keep_buf_post->index);
- di_lock_irqfiq_save(irq_flag2); /**/
- div3_que_in(channel, QUE_POST_FREE, ppost->keep_buf_post);
- di_unlock_irqfiq_restore(irq_flag2);
- ppost->keep_buf_post = NULL;
- }
-}
-#else
-void dimv3_recycle_post_back(unsigned int channel)
-{
- struct di_buf_s *di_buf = NULL;
- ulong irq_flag2 = 0;
- unsigned int i = 0;
-
- if (div3_que_is_empty(channel, QUE_POST_BACK))
- return;
-
-
- while (i < MAX_FIFO_SIZE) {
- i++;
-
- di_buf = div3_que_peek(channel, QUE_POST_BACK);
- /*pr_info("dp2:%d\n", post_buf_index);*/
- if (!di_buf)
- break;
-
- if (di_buf->type != VFRAME_TYPE_POST) {
- queuev3_out(channel, di_buf);
- PR_ERR("%s:type is not post\n", __func__);
- continue;
- }
-
- dimv3_print("di_back:%d\n", di_buf->index);
- di_lock_irqfiq_save(irq_flag2); /**/
- div3_que_out(channel, QUE_POST_BACK, di_buf);
- di_buf->queue_index = QUEUE_DISPLAY;
- /*queue_out(channel, di_buf);*/
-
- if (!atomic_dec_and_test(&di_buf->c.di_cnt))
- PR_ERR("%s,di_cnt > 0\n", __func__);
-
- recycle_vframe_type_post(di_buf, channel);
- //di_buf->c.invert_top_bot_flag = 0;
- //di_que_in(channel, QUE_POST_FREE, di_buf);
-
- di_unlock_irqfiq_restore(irq_flag2);
- }
-
- if (div3_cfg_top_get(EDI_CFG_KEEP_CLEAR_AUTO))
- taskv3_send_cmd(LCMD1(ECMD_RL_KEEP_ALL, channel));
- //dim_post_keep_release_all_2free(channel);
-
-}
-
-#endif
-struct vframe_s *div3_vf_l_peek(struct di_ch_s *pch)
-{
- struct vframe_s *vframe_ret = NULL;
- struct di_buf_s *di_buf = NULL;
-// struct di_pre_stru_s *ppre = get_pre_stru(channel);
- unsigned int ch;
-
- ch = pch->ch_id;
- /*dim_print("%s:ch[%d]\n",__func__, channel);*/
-
- div3_sum_inc(ch, eDI_SUM_O_PEEK_CNT);
- #if 0
- if (ppre->bypass_flag) {
- dimv3_tr_ops.post_peek(0);
- return pw_vf_peek(channel);
- }
- #endif
- if (!get_init_flag(ch) ||
- recovery_flag ||
- di_blocking ||
- !get_reg_flag(ch) ||
- dump_state_flag) {
- dimv3_tr_ops.post_peek(1);
- return NULL;
- }
-
- /**************************/
- if (listv3_count(ch, QUEUE_DISPLAY) > DI_POST_GET_LIMIT) {
- dimv3_tr_ops.post_peek(2);
- return NULL;
- }
- /**************************/
- dimv3_log_buffer_state("pek", ch);
-
- {
- if (!div3_que_is_empty(ch, QUE_POST_READY)) {
- di_buf = div3_que_peek(ch, QUE_POST_READY);
- if (di_buf)
- vframe_ret = di_buf->vframe;
- }
- }
-#ifdef DI_BUFFER_DEBUG
- if (vframe_ret)
- dimv3_print("%s: %s[%d]:%x\n", __func__,
- vframe_type_name[di_buf->type],
- di_buf->index, vframe_ret);
-#endif
- if (vframe_ret)
- dimv3_tr_ops.post_peek(9);
- else
- dimv3_tr_ops.post_peek(4);
- return vframe_ret;
-}
-
-#if 0 /*move to di_vframe.c*/
-int di_vf_l_states(struct vframe_states *states, unsigned int channel)
-{
- struct di_mm_s *mm = dim_mm_get(channel);
-
- /*pr_info("%s: ch[%d]\n", __func__, channel);*/
- if (!states)
- return -1;
- states->vf_pool_size = mm->sts.num_local;
- states->buf_free_num = listv3_count(channel, QUEUE_LOCAL_FREE);
-
- states->buf_avail_num = div3_que_list_count(channel, QUE_POST_READY);
- states->buf_recycle_num = listv3_count(channel, QUEUE_RECYCLE);
- if (dimp_get(eDI_MP_di_dbg_mask) & 0x1) {
- di_pr_info("di-pre-ready-num:%d\n",
- /*new que list_count(channel, QUEUE_PRE_READY));*/
- div3_que_list_count(channel, QUE_PRE_READY));
- di_pr_info("di-display-num:%d\n",
- listv3_count(channel, QUEUE_DISPLAY));
- }
- return 0;
-}
-#endif
-/**********************************************/
-
-/*****************************
- * di driver file_operations
- *
- ******************************/
-#if 0 /*move to di_sys.c*/
-static int di_open(struct inode *node, struct file *file)
-{
- di_dev_t *di_in_devp;
-
-/* Get the per-device structure that contains this cdev */
- di_in_devp = container_of(node->i_cdev, di_dev_t, cdev);
- file->private_data = di_in_devp;
-
- return 0;
-}
-
-static int di_release(struct inode *node, struct file *file)
-{
-/* di_dev_t *di_in_devp = file->private_data; */
-
-/* Reset file pointer */
-
-/* Release some other fields */
- file->private_data = NULL;
- return 0;
-}
-
-#endif /*move to di_sys.c*/
-
-static struct di_pq_parm_s *di_pq_parm_create(struct am_pq_parm_s *pq_parm_p)
-{
- struct di_pq_parm_s *pq_ptr = NULL;
- struct am_reg_s *am_reg_p = NULL;
- size_t mem_size = 0;
-
- pq_ptr = vzalloc(sizeof(*pq_ptr));
- mem_size = sizeof(struct am_pq_parm_s);
- memcpy(&pq_ptr->pq_parm, pq_parm_p, mem_size);
- mem_size = sizeof(struct am_reg_s) * pq_parm_p->table_len;
- am_reg_p = vzalloc(mem_size);
- if (!am_reg_p) {
- vfree(pq_ptr);
- PR_ERR("alloc pq table memory errors\n");
- return NULL;
- }
- pq_ptr->regs = am_reg_p;
-
- return pq_ptr;
-}
-
-static void di_pq_parm_destroy(struct di_pq_parm_s *pq_ptr)
-{
- if (!pq_ptr) {
- PR_ERR("%s pq parm pointer null.\n", __func__);
- return;
- }
- vfree(pq_ptr->regs);
- vfree(pq_ptr);
-}
-
-/*move from ioctrl*/
-long dimv3_pq_load_io(unsigned long arg)
-{
- long ret = 0, tab_flag = 0;
- di_dev_t *di_devp;
- void __user *argp = (void __user *)arg;
- size_t mm_size = 0;
- struct am_pq_parm_s tmp_pq_s = {0};
- struct di_pq_parm_s *di_pq_ptr = NULL;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-// unsigned int channel = 0; /*fix to channel 0*/
-
- di_devp = de_devp;
-
- mm_size = sizeof(struct am_pq_parm_s);
- if (copy_from_user(&tmp_pq_s, argp, mm_size)) {
- PR_ERR("set pq parm errors\n");
- return -EFAULT;
- }
- if (tmp_pq_s.table_len >= TABLE_LEN_MAX) {
- PR_ERR("load 0x%x wrong pq table_len.\n",
- tmp_pq_s.table_len);
- return -EFAULT;
- }
- tab_flag = TABLE_NAME_DI | TABLE_NAME_NR | TABLE_NAME_MCDI |
- TABLE_NAME_DEBLOCK | TABLE_NAME_DEMOSQUITO;
- if (tmp_pq_s.table_name & tab_flag) {
- PR_INF("load 0x%x pq table len %u %s.\n",
- tmp_pq_s.table_name, tmp_pq_s.table_len,
- get_reg_flag_all() ? "directly" : "later");
- } else {
- PR_ERR("load 0x%x wrong pq table.\n",
- tmp_pq_s.table_name);
- return -EFAULT;
- }
- di_pq_ptr = di_pq_parm_create(&tmp_pq_s);
- if (!di_pq_ptr) {
- PR_ERR("allocat pq parm struct error.\n");
- return -EFAULT;
- }
- argp = (void __user *)tmp_pq_s.table_ptr;
- mm_size = tmp_pq_s.table_len * sizeof(struct am_reg_s);
- if (copy_from_user(di_pq_ptr->regs, argp, mm_size)) {
- PR_ERR("user copy pq table errors\n");
- return -EFAULT;
- }
- if (get_reg_flag_all()) {
- dimhv3_load_regs(di_pq_ptr);
- di_pq_parm_destroy(di_pq_ptr);
-
- return ret;
- }
- if (atomic_read(&de_devp->pq_flag) == 0) {
- atomic_set(&de_devp->pq_flag, 1);
- if (di_devp->flags & DI_LOAD_REG_FLAG) {
- struct di_pq_parm_s *pos = NULL, *tmp = NULL;
-
- list_for_each_entry_safe(pos, tmp,
- &di_devp->pq_table_list, list) {
- if (di_pq_ptr->pq_parm.table_name ==
- pos->pq_parm.table_name) {
- PR_INF("remove 0x%x table.\n",
- pos->pq_parm.table_name);
- list_del(&pos->list);
- di_pq_parm_destroy(pos);
- }
- }
- }
- list_add_tail(&di_pq_ptr->list,
- &di_devp->pq_table_list);
- di_devp->flags |= DI_LOAD_REG_FLAG;
- atomic_set(&de_devp->pq_flag, 0);
- } else {
- PR_ERR("please retry table name 0x%x.\n",
- di_pq_ptr->pq_parm.table_name);
- di_pq_parm_destroy(di_pq_ptr);
- ret = -EFAULT;
- }
-
- return ret;
-}
-
-#if 0 /*#ifdef CONFIG_AMLOGIC_MEDIA_RDMA*/
-unsigned int dimv3_RDMA_RD_BITS(unsigned int adr, unsigned int start,
- unsigned int len)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (de_devp->rdma_handle && di_pre_rdma_enable)
- return rdma_read_reg(de_devp->rdma_handle, adr) &
- (((1 << len) - 1) << start);
- else
- return Rd_reg_bits(adr, start, len);
-}
-
-unsigned int dimv3_RDMA_WR(unsigned int adr, unsigned int val)
-{
- unsigned int channel = get_current_channel();
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (is_need_stop_reg(adr))
- return 0;
-
- if (de_devp->rdma_handle > 0 && di_pre_rdma_enable) {
- if (ppre->field_count_for_cont < 1)
- dimv3_DI_Wr(adr, val);
- else
- rdma_write_reg(de_devp->rdma_handle, adr, val);
- return 0;
- }
-
- dimv3_DI_Wr(adr, val);
- return 1;
-}
-
-unsigned int dimv3_RDMA_RD(unsigned int adr)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (de_devp->rdma_handle > 0 && di_pre_rdma_enable)
- return rdma_read_reg(de_devp->rdma_handle, adr);
- else
- return Rd(adr);
-}
-
-unsigned int dimv3_RDMA_WR_BITS(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len)
-{
- unsigned int channel = get_current_channel();
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (is_need_stop_reg(adr))
- return 0;
-
- if (de_devp->rdma_handle > 0 && di_pre_rdma_enable) {
- if (ppre->field_count_for_cont < 1)
- dimv3_DI_Wr_reg_bits(adr, val, start, len);
- else
- rdma_write_reg_bits(de_devp->rdma_handle,
- adr, val, start, len);
- return 0;
- }
- dimv3_DI_Wr_reg_bits(adr, val, start, len);
- return 1;
-}
-#else
-unsigned int dimv3_RDMA_RD_BITS(unsigned int adr, unsigned int start,
- unsigned int len)
-{
- return Rd_reg_bits(adr, start, len);
-}
-
-unsigned int dimv3_RDMA_WR(unsigned int adr, unsigned int val)
-{
- dimv3_DI_Wr(adr, val);
- if (get_dbg_data()->delay_cnt)
- udelay(get_dbg_data()->delay_cnt);
- return 1;
-}
-
-unsigned int dimv3_RDMA_RD(unsigned int adr)
-{
- return Rd(adr);
-}
-
-unsigned int dimv3_RDMA_WR_BITS(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len)
-{
- dimv3_DI_Wr_reg_bits(adr, val, start, len);
- if (get_dbg_data()->delay_cnt)
- udelay(get_dbg_data()->delay_cnt);
- return 1;
-}
-#endif
-
-void dimv3_set_di_flag(void)
-{
- if (is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_gxlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) {
- dimp_set(eDI_MP_mcpre_en, 1);
- mc_mem_alloc = true;
- dimp_set(eDI_MP_pulldown_enable, 0);
- //di_pre_rdma_enable = false;
- /*
- * txlx atsc 1080i ei only will cause flicker
- * when full to small win in home screen
- */
-
- dimp_set(eDI_MP_di_vscale_skip_enable,
- (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu()) ? 12 : 4);
- /*use_2_interlace_buff = is_meson_gxlx_cpu()?0:1;*/
- dimp_set(eDI_MP_use_2_interlace_buff,
- is_meson_gxlx_cpu() ? 0 : 1);
- if (is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_gxlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) {
- dimp_set(eDI_MP_full_422_pack, 1);
- }
-
- if (dimp_get(eDI_MP_nr10bit_support)) {
- dimp_set(eDI_MP_di_force_bit_mode, 10);
- } else {
- dimp_set(eDI_MP_di_force_bit_mode, 8);
- dimp_set(eDI_MP_full_422_pack, 0);
- }
-
- dimp_set(eDI_MP_post_hold_line,
- (is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu() ||
- is_meson_sm1_cpu()) ? 10 : 17);
- } else {
- /*post_hold_line = 8;*/ /*2019-01-10: from VLSI feijun*/
- dimp_set(eDI_MP_post_hold_line, 8);
- dimp_set(eDI_MP_mcpre_en, 0);
- dimp_set(eDI_MP_pulldown_enable, 0);
- //di_pre_rdma_enable = false;
- dimp_set(eDI_MP_di_vscale_skip_enable, 4);
- dimp_set(eDI_MP_use_2_interlace_buff, 0);
- dimp_set(eDI_MP_di_force_bit_mode, 8);
- }
- /*if (is_meson_tl1_cpu() || is_meson_tm2_cpu())*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimp_set(eDI_MP_pulldown_enable, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- intr_mode = 3;
-
- pldn_dly = 2;
- pldn_dly1 = 2;
-
-
- get_ops_mtn()->mtn_int_combing_glbmot();
-}
-
-#if 0 /*move to di_sys.c*/
-static const struct reserved_mem_ops rmem_di_ops = {
- .device_init = rmem_di_device_init,
- .device_release = rmem_di_device_release,
-};
-
-static int __init rmem_di_setup(struct reserved_mem *rmem)
-{
- rmem->ops = &rmem_di_ops;
-/* rmem->priv = cma; */
-
- di_pr_info(
- "DI reserved memory: created CMA memory pool at %pa, size %ld MiB\n",
- &rmem->base, (unsigned long)rmem->size / SZ_1M);
-
- return 0;
-}
-
-RESERVEDMEM_OF_DECLARE(di, "amlogic, di-mem", rmem_di_setup);
-#endif
-
-void dimv3_get_vpu_clkb(struct device *dev, struct di_dev_s *pdev)
-{
- int ret = 0;
- unsigned int tmp_clk[2] = {0, 0};
- struct clk *vpu_clk = NULL;
- struct clk *clkb_tmp_comp = NULL;
-
- vpu_clk = clk_get(dev, "vpu_mux");
- if (IS_ERR(vpu_clk))
- PR_ERR("%s: get clk vpu error.\n", __func__);
- else
- clk_prepare_enable(vpu_clk);
-
- ret = of_property_read_u32_array(dev->of_node, "clock-range",
- tmp_clk, 2);
- if (ret) {
- pdev->clkb_min_rate = 250000000;
- pdev->clkb_max_rate = 500000000;
- } else {
- pdev->clkb_min_rate = tmp_clk[0] * 1000000;
- pdev->clkb_max_rate = tmp_clk[1] * 1000000;
- }
- PR_INF("vpu clkb <%lu, %lu>\n", pdev->clkb_min_rate,
- pdev->clkb_max_rate);
- #ifdef CLK_TREE_SUPPORT
- pdev->vpu_clkb = clk_get(dev, "vpu_clkb_composite");
- if (is_meson_tl1_cpu()) {
- clkb_tmp_comp = clk_get(dev, "vpu_clkb_tmp_composite");
- if (IS_ERR(clkb_tmp_comp)) {
- PR_ERR("clkb_tmp_comp error\n");
- } else {
- /*ary: this make clk from 500 to 666?*/
- if (!IS_ERR(vpu_clk))
- clk_set_parent(clkb_tmp_comp, vpu_clk);
- }
- }
-
- if (IS_ERR(pdev->vpu_clkb)) {
- PR_ERR("%s: get vpu clkb gate error.\n", __func__);
- } else {
- clk_set_rate(pdev->vpu_clkb, pdev->clkb_min_rate);
- PR_INF("get clkb rate:%ld\n", clk_get_rate(pdev->vpu_clkb));
- }
-
- #endif
-}
-
-module_param_named(invert_top_bot, invert_top_bot, int, 0664);
-
-#ifdef SUPPORT_START_FRAME_HOLD
-module_param_named(start_frame_hold_count, start_frame_hold_count, int, 0664);
-#endif
-
-#ifdef DET3D
-
-MODULE_PARM_DESC(det3d_mode, "\n det3d_mode\n");
-module_param(det3d_mode, uint, 0664);
-#endif
-
-module_param_array(di_stop_reg_addr, uint, &num_di_stop_reg_addr,
- 0664);
-
-module_param_named(overturn, overturn, bool, 0664);
-
-#ifdef DEBUG_SUPPORT
-#ifdef RUN_DI_PROCESS_IN_IRQ
-module_param_named(input2pre, input2pre, uint, 0664);
-module_param_named(input2pre_buf_miss_count, input2pre_buf_miss_count,
- uint, 0664);
-module_param_named(input2pre_proc_miss_count, input2pre_proc_miss_count,
- uint, 0664);
-module_param_named(input2pre_miss_policy, input2pre_miss_policy, uint, 0664);
-module_param_named(input2pre_throw_count, input2pre_throw_count, uint, 0664);
-#endif
-#ifdef SUPPORT_MPEG_TO_VDIN
-module_param_named(mpeg2vdin_en, mpeg2vdin_en, int, 0664);
-module_param_named(mpeg2vdin_flag, mpeg2vdin_flag, int, 0664);
-#endif
-//module_param_named(di_pre_rdma_enable, di_pre_rdma_enable, uint, 0664);
-module_param_named(pldn_dly, pldn_dly, uint, 0644);
-module_param_named(pldn_dly1, pldn_dly1, uint, 0644);
-module_param_named(di_reg_unreg_cnt, di_reg_unreg_cnt, int, 0664);
-module_param_named(bypass_pre, bypass_pre, int, 0664);
-module_param_named(frame_count, frame_count, int, 0664);
-#endif
-
-int dimv3_seq_file_module_para_di(struct seq_file *seq)
-{
- seq_puts(seq, "di---------------\n");
-
-#ifdef DET3D
- seq_printf(seq, "%-15s:%d\n", "det3d_frame_cnt", det3d_frame_cnt);
-#endif
-
-#ifdef SUPPORT_START_FRAME_HOLD
- seq_printf(seq, "%-15s:%d\n", "start_frame_hold_count",
- start_frame_hold_count);
-#endif
- seq_printf(seq, "%-15s:%ld\n", "same_field_top_count",
- same_field_top_count);
- seq_printf(seq, "%-15s:%ld\n", "same_field_bot_count",
- same_field_bot_count);
-
- seq_printf(seq, "%-15s:%d\n", "overturn", overturn);
-
-#ifdef DEBUG_SUPPORT
-#ifdef RUN_DI_PROCESS_IN_IRQ
- seq_printf(seq, "%-15s:%d\n", "input2pre", input2pre);
- seq_printf(seq, "%-15s:%d\n", "input2pre_buf_miss_count",
- input2pre_buf_miss_count);
- seq_printf(seq, "%-15s:%d\n", "input2pre_proc_miss_count",
- input2pre_proc_miss_count);
- seq_printf(seq, "%-15s:%d\n", "input2pre_miss_policy",
- input2pre_miss_policy);
- seq_printf(seq, "%-15s:%d\n", "input2pre_throw_count",
- input2pre_throw_count);
-#endif
-#ifdef SUPPORT_MPEG_TO_VDIN
-
- seq_printf(seq, "%-15s:%d\n", "mpeg2vdin_en", mpeg2vdin_en);
- seq_printf(seq, "%-15s:%d\n", "mpeg2vdin_flag", mpeg2vdin_flag);
-#endif
-// seq_printf(seq, "%-15s:%d\n", "di_pre_rdma_enable",
-// di_pre_rdma_enable);
- seq_printf(seq, "%-15s:%d\n", "pldn_dly", pldn_dly);
- seq_printf(seq, "%-15s:%d\n", "pldn_dly1", pldn_dly1);
- seq_printf(seq, "%-15s:%d\n", "di_reg_unreg_cnt", di_reg_unreg_cnt);
- seq_printf(seq, "%-15s:%d\n", "bypass_pre", bypass_pre);
- seq_printf(seq, "%-15s:%d\n", "frame_count", frame_count);
-#endif
-/******************************/
-
-#ifdef DET3D
- seq_printf(seq, "%-15s:%d\n", "det3d_mode", det3d_mode);
-#endif
- return 0;
-}
-
-#if 0 /*move to di_sys.c*/
-MODULE_DESCRIPTION("AMLOGIC DEINTERLACE driver");
-MODULE_LICENSE("GPL");
-MODULE_VERSION("4.0.0");
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _DI_H
-#define _DI_H
-#include <linux/cdev.h>
-#include <linux/types.h>
-#include <linux/amlogic/media/di/di_interface.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-
-#include "../di_local/di_local.h"
-#include <linux/clk.h>
-#include <linux/atomic.h>
-#include "deinterlace_hw.h"
-#include "../deinterlace/di_pqa.h"
-/************************************************
- * config define
- ***********************************************/
-#define DIM_OUT_NV21 (1)
-
-/*trigger_pre_di_process param*/
-#define TRIGGER_PRE_BY_PUT 'p'
-#define TRIGGER_PRE_BY_DE_IRQ 'i'
-#define TRIGGER_PRE_BY_UNREG 'u'
-/*di_timer_handle*/
-#define TRIGGER_PRE_BY_TIMER 't'
-#define TRIGGER_PRE_BY_FORCE_UNREG 'f'
-#define TRIGGER_PRE_BY_VFRAME_READY 'r'
-#define TRIGGER_PRE_BY_PROVERDER_UNREG 'n'
-#define TRIGGER_PRE_BY_DEBUG_DISABLE 'd'
-#define TRIGGER_PRE_BY_PROVERDER_REG 'R'
-
-#define DI_RUN_FLAG_RUN 0
-#define DI_RUN_FLAG_PAUSE 1
-#define DI_RUN_FLAG_STEP 2
-#define DI_RUN_FLAG_STEP_DONE 3
-
-#define USED_LOCAL_BUF_MAX 3
-#define BYPASS_GET_MAX_BUF_NUM 4
-
-/* buffer management related */
-#define MAX_IN_BUF_NUM (4)
-#define MAX_LOCAL_BUF_NUM (7)
-#define MAX_POST_BUF_NUM (7) /*(5)*/ /* 16 */
-/****************************************************
- * one post buf: 0x4fb000
- ***************************************************/
-#define VFRAME_TYPE_IN 1
-#define VFRAME_TYPE_LOCAL 2
-#define VFRAME_TYPE_POST 3
-#define VFRAME_TYPE_NUM 3
-
-#define DI_POST_GET_LIMIT 4
-#define DI_PRE_READY_LIMIT 4
-/*vframe define*/
-#define vframe_t struct vframe_s
-
-//no use#define is_from_vdin(vframe) ((vframe)->type & VIDTYPE_VIU_422)
-/***********************************/
-/*replace vframe_s:*/
-struct dim_itf_u {
- struct vframe_s vfm;
- struct di_buffer dbuf; /*option for ins*/
-};
-/**********************************/
-
-/* canvas defination */
-#define DI_USE_FIXED_CANVAS_IDX
-/*#define DET3D */
-#undef SUPPORT_MPEG_TO_VDIN
-#define CLK_TREE_SUPPORT
-#ifndef CONFIG_AMLOGIC_MEDIA_RDMA
-#ifndef VSYNC_WR_MPEG_REG
-#define VSYNC_WR_MPEG_REG(adr, val) aml_write_vcbus(adr, val)
-#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
- aml_vcbus_update_bits((adr), \
- ((1 << (len)) - 1) << (start), (val) << (start))
-
-#define VSYNC_RD_MPEG_REG(adr) aml_read_vcbus(adr)
-#endif
-#endif
-
-#define IS_VDIN_SRC(src) ( \
- ((src) == VFRAME_SOURCE_TYPE_TUNER) || \
- ((src) == VFRAME_SOURCE_TYPE_CVBS) || \
- ((src) == VFRAME_SOURCE_TYPE_COMP) || \
- ((src) == VFRAME_SOURCE_TYPE_HDMI))
-
-#define VFMT_IS_I(vftype) ((vftype) & VIDTYPE_INTERLACE_BOTTOM)
-
-#define IS_COMP_MODE(vftype) ((vftype) & VIDTYPE_COMPRESS)
-
-#define VFMT_SET_TOP(vftype) (((vftype) & (~VIDTYPE_TYPEMASK)) | \
- VIDTYPE_INTERLACE_TOP)
-
-#define VFMT_SET_BOTTOM(vftype) (((vftype) & (~VIDTYPE_TYPEMASK)) | \
- VIDTYPE_INTERLACE_BOTTOM)
-
-#define VFMT_IS_TOP(vfm) (((vfm) & VIDTYPE_TYPEMASK) == \
- VIDTYPE_INTERLACE_TOP)
-
-enum process_fun_index_e {
- PROCESS_FUN_NULL = 0,
- PROCESS_FUN_DI,
- PROCESS_FUN_PD,
- PROCESS_FUN_PROG,
- PROCESS_FUN_BOB
-};
-
-#define process_fun_index_t enum process_fun_index_e
-
-enum canvas_idx_e {
- NR_CANVAS,
- MTN_CANVAS,
- MV_CANVAS,
-};
-
-#define pulldown_mode_t enum pulldown_mode_e
-
-struct mcinfo_pre_s {
- unsigned int highvertfrqflg;
- unsigned int motionparadoxflg;
- unsigned int regs[26];/* reg 0x2fb0~0x2fc9 */
-};
-/**********************************************************
- *
- *********************************************************/
-enum EDIM_TMODE {
- EDIM_TMODE_NONE,
- EDIM_TMODE_1_PW_VFM,
- /* EDIM_TMODE_1_PW_LOCAL ******
- * pre + post write
- * all buf alloc by di
- * use vframe event
- ******************************/
- EDIM_TMODE_2_PW_OUT,
- /* EDIM_TMODE_2_PRE_OUT ******
- * pre + post write
- * post buf alloc by other module
- * not use vframe path
- * add 2019-11-26 for zhouzhi
- ******************************/
- EDIM_TMODE_3_PW_LOCAL,
- /* EDIM_TMODE_2_PRE_OUT ******
- * pre + post write
- * post buf alloc by self
- * not use vframe path
- * add 2019-12-04 for test
- ******************************/
-};
-
-struct dim_wmode_s {
- enum EDIM_TMODE tmode;
- unsigned int buf_type; /*add this to split kinds */
- unsigned int is_afbc :1,
- is_vdin :1,
- is_i :1,
- need_bypass :1,
- is_bypass :1,
- pre_bypass :1,
- post_bypass :1,
- flg_keep :1, /*keep buf*/
-
- trick_mode :1,
- prog_proc_config :1, /*debug only: proc*/
- /**************************************
- *prog_proc_config: same as p_as_i?
- *1: process p from decoder as field
- *0: process p from decoder as frame
- ***************************************/
- is_invert_tp :1,
- p_as_i :1,
- p_use_2i :1,
- is_angle :1,
- is_top :1, /*include */
- is_eos :1,
-
- reserved :16;
- unsigned int vtype; /*vfm->type*/
- //unsigned int h; /*taget h*/
- //unsigned int w; /*taget w*/
- unsigned int src_h;
- unsigned int src_w;
- unsigned int tgt_h;
- unsigned int tgt_w;
- unsigned int o_h;
- unsigned int o_w;
- unsigned int seq;
- unsigned int seq_pre;
-};
-
-#define DIM_VFM_PROGRESSIVE 0x000000
-#define DIM_VFM_INTERLACE_TOP 0x000001
-#define DIM_VFM_INTERLACE_BOTTOM 0x000003
-#define DIM_VFM_TYPEMASK 0x000007
-#define DIM_VFM_INTERLACE 0x000001
-#define DIM_VFM_VIU_NV12 0x80
-#define DIM_VFM_VIU_422 0x000800
-#define DIM_VFM_VIU_444 0x004000
-#define DIM_VFM_VIU_NV21 0x008000
-#define DIM_VFM_COMPRESS 0x100000
-
-/*apply:*/
-#define DIM_VFM_MASK_ALL 0x10c887
-#define DIM_VFM_LOCAL_T (DIM_VFM_INTERLACE_TOP | \
- DIM_VFM_VIU_422)
-#define DIM_VFM_LOCAL_B (DIM_VFM_INTERLACE_BOTTOM | \
- DIM_VFM_VIU_422)
-
-#define DIM_VFMT_IS_I(vftype) ((vftype) & DIM_VFM_INTERLACE_BOTTOM)
-#define DIM_VFMT_IS_TOP(vfm) (((vfm) & DIM_VFM_TYPEMASK) == \
- DIM_VFM_INTERLACE_TOP)
-#define DIM_VFMT_IS_P(vftype) (((vftype) & DIM_VFM_TYPEMASK) == 0)
-
-
-/*use this replace vframe data in di work*/
-struct dim_vmode_s {
- unsigned int vtype;
- unsigned int h;
- unsigned int w;
- unsigned int canvas0Addr;
- unsigned int canvas1Addr;
- unsigned int bitdepth; /*copy*/
- unsigned int bit_mode; /*count*/
- unsigned int omx_index;
- u64 ready_jiffies64; /*copy from vframe u64 ready_jiffies64;*/
-};
-
-struct di_in_inf_s {
- /*use this for judge type change or not */
- unsigned int ch;
- unsigned int vtype_ori; /*only debug*/
- unsigned int src_type;
- unsigned int trans_fmt;
- unsigned int sig_fmt;/*use for mtn*/
- unsigned int h;
- unsigned int w;
-};
-
-enum EDIM_DISP_TYPE {
- EDIM_DISP_T_NONE,
- EDIM_DISP_T_IN, /*need bypass*/
- EDIM_DISP_T_PRE,
- EDIM_DISP_T_NR,
- EDIM_DISP_T_PST,
-};
-
-struct dim_dvfm_s {
-// unsigned int code_name;/*0x12345678*/
- unsigned int index;
-
- enum EDIM_DISP_TYPE etype;
- struct di_in_inf_s in_inf;
- struct dim_wmode_s wmode;
- struct dim_vmode_s vmode;
- //struct vframe_s vframe;/*input cp*/
- struct dim_itf_u vframe;
- void *vfm_in;
- void *vfm_out; /*only for ins*/
- void *di_buf;/*vfm out is in di_buf*/
-};
-
-struct di_buf_c_s {
- struct dim_wmode_s wmode;
- struct dim_vmode_s vmode;
- struct dim_dvfm_s *pdvfm;
- int post_proc_flag;
- /* post_proc_flag:
- * 0: no post di;
- * 1: normal post di;
- * 2, edge only; 3, dummy
- ***********************/
- int new_format_flag;
- int throw_flag;
- int invert_top_bot_flag;
- int seq;
- int pre_ref_count;
- /* pre_ref_count:none zero, is used by mem_mif,
- * chan2_mif, or wr_buf
- */
- int post_ref_count;
- /* post_ref_count: none zero, is used by post process */
- struct mcinfo_pre_s curr_field_mcinfo;
- /*curr_field_mcinfo for type of VFRAME_TYPE_LOCAL */
- struct pulldown_detected_s pd_config;
- /* pd_config: blend window */
- unsigned int privated; /*?*/
- /* privated:tff bff check result bit[1:0]*/
- unsigned int canvas_config_flag;
- /**canvas_config_flag************
- * 0,configed; 1,config type 1 (prog);
- * 2, config type 2 (interlace)
- ********************************/
- enum process_fun_index_e process_fun_index;
- int early_process_fun_index;
- int left_right;
- /* left_right:1,left eye; 0,right eye in field alternative*/
- struct di_buf_s *di_buf[2];
- /* di_buf:**********************
- * di_buf[0]:pre_ready
- * for type of VFRAME_TYPE_POST?
- *******************************/
- struct di_buf_s *di_buf_dup_p[5];
- /* di_buf_dup_p *****************
- *0~4: n-2, n-1, n, n+1, n+2; n is the field to display
- *0: n-2
- *1: n-1
- *2: n
- *3: n+1
- *4: n+2*************************/
- struct di_buf_s *di_wr_linked_buf;
- atomic_t di_cnt;
- /* di_cnt************************
- * debug for di-vf-get/put
- * 1: after get
- * 0: after put
- ********************************/
- unsigned int width_bk;
- unsigned int blend_mode; /*ary add for debug*/
-
- unsigned int sts;
-
- struct di_buf_s *in_buf; /*keep dec vf: link in buf*/
- unsigned int dec_vf_state; /*keep dec vf:*/
-};
-
-struct di_buf_s {
- /********************************/
- unsigned int code_name;/*0x87654321*/
- unsigned int channel;
- int index;
-
- int type;
-
- /*******
- * index in vframe_in_dup[] or vframe_in[],
- * only for type of VFRAME_TYPE_IN
- */
- int queue_index;
- struct vframe_s *vframe;
-
- struct page *pages;
- unsigned long nr_adr;
- int nr_canvas_idx;
- unsigned long mtn_adr;
- int mtn_canvas_idx;
- unsigned long cnt_adr;
- int cnt_canvas_idx;
- unsigned long mcinfo_adr;
- unsigned short *mcinfo_adr_v;/**/
- bool mcinfo_alloc_flg; /**/
- int mcinfo_canvas_idx;
- unsigned long mcvec_adr;
- int mcvec_canvas_idx;
- unsigned int canvas_height;
- unsigned int canvas_height_mc; /*ary add for mc h is diff*/
- unsigned int canvas_width[3];/* nr/mtn/mv */
- struct di_buffer *ins; /*for EDIM_TMODE_3_PW_LOCAL*/
- /********************************/
- struct di_buf_c_s c;
-};
-
-#define RDMA_DET3D_IRQ 0x20
-/* vdin0 rdma irq */
-#define RDMA_DEINT_IRQ 0x2
-#define RDMA_TABLE_SIZE ((PAGE_SIZE) << 1)
-
-#define MAX_CANVAS_WIDTH 1920
-#define MAX_CANVAS_HEIGHT 1088
-
-/* #define DI_BUFFER_DEBUG */
-
-#define DI_LOG_MTNINFO 0x02
-#define DI_LOG_PULLDOWN 0x10
-#define DI_LOG_BUFFER_STATE 0x20
-#define DI_LOG_TIMESTAMP 0x100
-#define DI_LOG_PRECISE_TIMESTAMP 0x200
-#define DI_LOG_QUEUE 0x40
-#define DI_LOG_VFRAME 0x80
-
-#if 0
-#define QUEUE_LOCAL_FREE 0
-#define QUEUE_IN_FREE 1
-#define QUEUE_PRE_READY 2
-#define QUEUE_POST_FREE 3
-#define QUEUE_POST_READY 4
-#define QUEUE_RECYCLE 5
-#define QUEUE_DISPLAY 6
-#define QUEUE_TMP 7
-#define QUEUE_POST_DOING 8
-#define QUEUE_NUM 9
-#else
-#define QUEUE_LOCAL_FREE 0
-#define QUEUE_RECYCLE 1 /* 5 */
-#define QUEUE_DISPLAY 2 /* 6 */
-#define QUEUE_TMP 3 /* 7 */
-#define QUEUE_POST_DOING 4 /* 8 */
-
-#define QUEUE_IN_FREE 5 /* 1 */
-#define QUEUE_PRE_READY 6 /* 2 */
-#define QUEUE_POST_FREE 7 /* 3 */
-#define QUEUE_POST_READY 8 /* 4 QUE_POST_READY */
-
-/*new use this for put back control*/
-#define QUEUE_POST_PUT_BACK (9)
-#define QUEUE_POST_DOING2 (10)
-#define QUEUE_POST_NOBUF (11)
-#define QUEUE_POST_KEEP (12)/*below use pw_queue_in*/
-#define QUEUE_POST_KEEP_BACK (13)
-
-#define QUEUE_NUM 5 /* 9 */
-#define QUEUE_NEW_THD_MIN (QUEUE_IN_FREE - 1)
-#define QUEUE_NEW_THD_MAX (QUEUE_POST_KEEP_BACK + 1)
-
-#endif
-
-#define queue_t struct queue_s
-
-#define VFM_NAME "deinterlace"
-
-#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
-void enable_rdma(int enable_flag);
-int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
-int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
-u32 VSYNC_RD_MPEG_REG(u32 adr);
-bool is_vsync_rdma_enable(void);
-#else
-#ifndef VSYNC_WR_MPEG_REG
-#define VSYNC_WR_MPEG_REG(adr, val) aml_write_vcbus(adr, val)
-#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
- aml_vcbus_update_bits((adr), \
- ((1 << (len)) - 1) << (start), (val) << (start))
-
-#define VSYNC_RD_MPEG_REG(adr) aml_read_vcbus(adr)
-#endif
-#endif
-
-#define DI_COUNT 1
-#define DI_MAP_FLAG 0x1
-#define DI_SUSPEND_FLAG 0x2
-#define DI_LOAD_REG_FLAG 0x4
-#define DI_VPU_CLKB_SET 0x8
-
-struct dim_dvfm_s;
-
-struct di_dev_s {
- dev_t devt;
- struct cdev cdev; /* The cdev structure */
- struct device *dev;
- struct platform_device *pdev;
- dev_t devno;
- struct class *pclss;
-
- bool sema_flg; /*di_sema_init_flag*/
-
- struct task_struct *task;
- struct clk *vpu_clkb;
- unsigned long clkb_max_rate;
- unsigned long clkb_min_rate;
- struct list_head pq_table_list;
- atomic_t pq_flag;
- unsigned char di_event;
- unsigned int pre_irq;
- unsigned int post_irq;
- unsigned int flags;
- unsigned long jiffy;
-
- bool mem_flg; /*ary add for make sure mem is ok*/
- unsigned int buf_num_avail;
- int rdma_handle;
- /* is support nr10bit */
- unsigned int nr10bit_support;
- /* is DI support post wr to mem for OMX */
- unsigned int post_wr_support;
- unsigned int nrds_enable;
- unsigned int pps_enable;
- unsigned int h_sc_down_en;/*sm1, tm2 ...*/
- /*struct mutex cma_mutex;*/
-
- struct dentry *dbg_root; /*dbg_fs*/
- /***************************/
- /*struct di_data_l_s data_l;*/
- void *data_l;
-
-};
-#if 1
-struct di_pre_stru_s {
-/* pre input */
- struct DI_MIF_s di_inp_mif;
- struct DI_MIF_s di_mem_mif;
- struct DI_MIF_s di_chan2_mif;
- struct di_buf_s *di_inp_buf;
- struct di_buf_s *di_post_inp_buf;
- struct di_buf_s *di_inp_buf_next;
- /* p_asi_next: ary:add for p */
- struct di_buf_s *p_asi_next;
- struct di_buf_s *di_mem_buf_dup_p;
- struct di_buf_s *di_chan2_buf_dup_p;
-/* pre output */
- struct DI_SIM_MIF_s di_nrwr_mif;
- struct DI_SIM_MIF_s di_mtnwr_mif;
- struct di_buf_s *di_wr_buf; /**/
- struct di_buf_s *di_post_wr_buf;
- struct DI_SIM_MIF_s di_contp2rd_mif;
- struct DI_SIM_MIF_s di_contprd_mif;
- struct DI_SIM_MIF_s di_contwr_mif;
- unsigned int field_count;
- /* field_count
- * old name: field_count_for_cont
- *ary: one type play cnt
- ******************************/
-/*
- * 0 (f0,null,f0)->nr0,
- * 1 (f1,nr0,f1)->nr1_cnt,
- * 2 (f2,nr1_cnt,nr0)->nr2_cnt
- * 3 (f3,nr2_cnt,nr1_cnt)->nr3_cnt
- */
- struct DI_MC_MIF_s di_mcinford_mif;
- struct DI_MC_MIF_s di_mcvecwr_mif;
- struct DI_MC_MIF_s di_mcinfowr_mif;
-/* pre state */
- int in_seq;
- int recycle_seq;
- int pre_ready_seq;
-
- int pre_de_busy; /* 1 if pre_de is not done */
- int pre_de_process_flag; /* flag when dim_pre_de_process done */
- int pre_de_clear_flag;
- /* flag is set when VFRAME_EVENT_PROVIDER_UNREG*/
- int unreg_req_flag_cnt;
-
- int reg_req_flag_cnt;
- int force_unreg_req_flag;
- int disable_req_flag;
- /* current source info */
- int cur_width;
- int cur_height;
- int cur_inp_type;
- int cur_source_type;
- int cur_sig_fmt;
- unsigned int orientation;
- int cur_prog_flag;
- /* 1 for progressive source */
- /* valid only when prog_proc_type is 0, for
- * progressive source: top field 1, bot field 0
- */
- int source_change_flag;
-
- bool input_size_change_flag;
- /* input_size_change_flag,
- * 1: need reconfig pre/nr/dnr size
- * 0: not need config pre/nr/dnr size
- ******************************************/
-
-/* true: bypass di all logic, false: not bypass */
- bool bypass_flag;
- unsigned char prog_proc_type;
-/* set by prog_proc_config when source is vdin,
- * 0: i mode or p as i mode
- * 1: use 1 p buffer;
- * 2: p use 2 i buffer;
- * 3:use 2 i paralleling buffer ary:x
- */
-
- unsigned char madi_enable;
- unsigned char mcdi_enable;
- unsigned int pps_dstw; /*no use ?*/
- unsigned int pps_dsth; /*no use ?*/
- int left_right;/*1,left eye; 0,right eye in field alternative*/
-/*input2pre*/
- int bypass_start_count;
-/* need discard some vframe when input2pre => bypass */
- unsigned char vdin2nr;
- enum tvin_trans_fmt source_trans_fmt;
- enum tvin_trans_fmt det3d_trans_fmt;
-
- unsigned int width_bk;
-#ifdef DET3D
- unsigned int det_lr; /*ary DET3D*/
- unsigned int det_tp; /*ary DET3D*/
- unsigned int det_la; /*ary DET3D*/
- unsigned int det_null; /*ary DET3D*/
- int vframe_interleave_flag;
-#endif
-/**/
- int pre_de_irq_timeout_count;
- int pre_throw_flag; /*ary: for what?*/
- int bad_frame_throw_count;
-/*for static pic*/
- int static_frame_count;/*ary: no use*/
- bool force_interlace;
- bool bypass_pre;
- bool invert_flag;
- //bool vdin_source; /*ary no use*/
-
- int cma_release_req;
- /* for performance debug */
- unsigned long irq_time[2];
- /* combing adaptive */
- struct combing_status_s *mtn_status;
- bool combing_fix_en;
- unsigned int comb_mode;
- //struct dim_dvfm_s lst_dvfm;
- struct dim_dvfm_s *dvfm;
- unsigned int cnt_put;
- unsigned int cnt_get;
-
-};
-#endif
-struct di_post_stru_s {
- struct DI_MIF_s di_buf0_mif;
- struct DI_MIF_s di_buf1_mif;
- struct DI_MIF_s di_buf2_mif;
- struct DI_SIM_MIF_s di_diwr_mif;
- struct DI_SIM_MIF_s di_mtnprd_mif;
- struct DI_MC_MIF_s di_mcvecrd_mif;
- /*post doing buf and write buf to post ready*/
- struct di_buf_s *cur_post_buf;
- struct di_buf_s *keep_buf;
- struct di_buf_s *keep_buf_post; /*ary add for keep post buf*/
- int update_post_reg_flag;
- int run_early_proc_fun_flag; /*ary ?*/
- int cur_disp_index;
- int canvas_id;
- int next_canvas_id;
- bool toggle_flag;
- bool vscale_skip_flag;
-// uint start_pts;
- int buf_type;
- int de_post_process_done;
- int post_de_busy;
- int di_post_num;
- unsigned int post_peek_underflow;
- unsigned int di_post_process_cnt;
- unsigned int check_recycle_buf_cnt;/*cp to di_hpre_s*/
- /* performance debug */
- unsigned int post_wr_cnt;
- unsigned long irq_time;
-
- /*frame cnt*/
- unsigned int frame_cnt; /*cnt for post process*/
-};
-
-#define MAX_QUEUE_POOL_SIZE 256
-struct queue_s {
- unsigned int num;
- unsigned int in_idx;
- unsigned int out_idx;
- unsigned int type;
-/* 0, first in first out;
- * 1, general;2, fix position for di buf
- */
- unsigned int pool[MAX_QUEUE_POOL_SIZE];
-};
-
-struct di_buf_pool_s {
- struct di_buf_s *di_buf_ptr;
- unsigned int size;
-};
-
-//unsigned char dim_is_bypass(vframe_t *vf_in, unsigned int channel);
-bool dimv3_bypass_first_frame(unsigned int ch);
-
-int div3_cnt_buf(int width, int height, int prog_flag, int mc_mm,
- int bit10_support, int pack422);
-int dim_ins_cnt_post_cvs_size(struct di_buf_s *di_buf,
- struct di_buffer *ins_buf);
-int dim_ins_cnt_post_cvs_size2(struct di_buf_s *di_buf,
- struct di_buffer *ins_buf,
- unsigned int ch);
-
-unsigned int dim_ins_cnt_post_size(unsigned int w, unsigned int h);
-
-/*---get di state parameter---*/
-struct di_dev_s *getv3_dim_de_devp(void);
-
-const char *dimv3_get_version_s(void);
-int dimv3_get_dump_state_flag(void);
-
-int dimv3_get_blocking(void);
-
-struct di_buf_s *dimv3_get_recovery_log_di_buf(void);
-
-unsigned long dimv3_get_reg_unreg_timeout_cnt(void);
-//struct vframe_s **dim_get_vframe_in(unsigned int ch);
-int dimv3_check_recycle_buf(unsigned int ch);
-
-int dimv3_seq_file_module_para_di(struct seq_file *seq);
-int dimv3_seq_file_module_para_hw(struct seq_file *seq);
-
-int dim_seq_file_module_para_film_fw1(struct seq_file *seq);
-int dim_seq_file_module_para_mtn(struct seq_file *seq);
-
-int dimv3_seq_file_module_para_pps(struct seq_file *seq);
-
-int dim_seq_file_module_para_(struct seq_file *seq);
-
-/***********************/
-#ifdef HIS_V3
-void dim_lock_irqfiq_save(ulong flg);
-void dim_unlock_irqfiq_restore(ulong flg);
-#endif
-
-unsigned int div3_get_dts_nrds_en(void);
-int div3_get_disp_cnt(void);
-void dbg_vfmv3(struct vframe_s *vf, unsigned int cnt);
-
-/*---------------------*/
-long dimv3_pq_load_io(unsigned long arg);
-int dimv3_get_canvas(void);
-/*unsigned int dim_cma_alloc_total(struct di_dev_s *de_devp);*/
-irqreturn_t dimv3_irq(int irq, void *dev_instance);
-irqreturn_t dimv3_post_irq(int irq, void *dev_instance);
-
-void dimv3_rdma_init(void);
-void dimv3_rdma_exit(void);
-
-void dimv3_set_di_flag(void);
-void dimv3_get_vpu_clkb(struct device *dev, struct di_dev_s *pdev);
-
-void dimv3_log_buffer_state(unsigned char *tag, unsigned int channel);
-
-unsigned char dimv3_pre_de_buf_config(unsigned int ch);
-unsigned char dim_pre_de_buf_config_bypass(unsigned int ch);
-unsigned char dim_pre_de_buf_config_p_asi_t(unsigned int ch);
-unsigned char dim_pre_de_buf_config_p_asi_b(unsigned int ch);
-unsigned char dim_pre_de_buf_config_top(unsigned int ch);
-
-void dimv3_pre_de_process(unsigned int channel);
-//void dim_pre_de_done_buf_config(struct di_ch_s *pch, bool flg_timeout);
-void dimv3_pre_de_done_buf_clear(unsigned int channel);
-
-void div3_reg_setting(unsigned int channel, struct vframe_s *vframe,
- struct dim_wmode_s *pwmode);
-//void di_reg_variable(unsigned int channel, struct dim_dvfm_s *pdvfm);
-void di_reg_variable_needbypass(unsigned int channel,
- struct dim_dvfm_s *pdvfm);
-void di_reg_variable_normal(unsigned int channel,
- struct dim_dvfm_s *pdvfm);
-
-
-/*void dim_unreg_process_irq(unsigned int channel);*/
-void div3_unreg_variable(unsigned int channel);
-void div3_unreg_setting(void);
-
-void dimv3_uninit_buf(unsigned int disable_mirror, unsigned int channel);
-//void dim_unreg_process(unsigned int channel);
-
-int dimv3_process_post_vframe(unsigned int channel);
-int dimv3_pst_vframe_top(unsigned int ch);
-
-unsigned char dimv3_check_di_buf(struct di_buf_s *di_buf, int reason,
- unsigned int channel);
-int dimv3_do_post_wr_fun(void *arg, vframe_t *disp_vf);
-int dimv3_post_process(void *arg, unsigned int zoom_start_x_lines,
- unsigned int zoom_end_x_lines,
- unsigned int zoom_start_y_lines,
- unsigned int zoom_end_y_lines, vframe_t *disp_vf);
-void dimv3_post_de_done_buf_config(unsigned int channel);
-void dimv3_recycle_post_back(unsigned int channel);
-void recyclev3_post_ready_local(struct di_buf_s *di_buf,
- unsigned int channel);
-
-/*--------------------------*/
-unsigned char dimv3_vcry_get_flg(void);
-void dimv3_vcry_flg_inc(void);
-void dimv3_vcry_set_flg(unsigned char val);
-/*--------------------------*/
-unsigned int dimv3_vcry_get_log_reason(void);
-void dimv3_vcry_set_log_reason(unsigned int val);
-/*--------------------------*/
-unsigned char dimv3_vcry_get_log_q_idx(void);
-void dimv3_vcry_set_log_q_idx(unsigned int val);
-/*--------------------------*/
-struct di_buf_s **dimv3_vcry_get_log_di_buf(void);
-void dimv3_vcry_set_log_di_buf(struct di_buf_s *di_bufp);
-void dimv3_vcry_set(unsigned int reason, unsigned int idx,
- struct di_buf_s *di_bufp);
-
-const char *dimv3_get_vfm_type_name(unsigned int nub);
-
-bool dimv3_get_mcmem_alloc(void);
-bool dimv3_get_overturn(void);
-
-int dimv3_get_reg_unreg_cnt(void);
-void dimv3_reg_timeout_inc(void);
-
-//no use void dim_reg_process(unsigned int channel);
-//bool is_bypass2(struct vframe_s *vf_in, unsigned int ch);
-void dimv3_post_keep_cmd_proc(unsigned int ch, unsigned int index);
-void dimv3_dbg_release_keep_all(unsigned int ch);
-/*--------------------------*/
-//int di_ori_event_unreg(unsigned int channel);
-//int di_ori_event_reg(void *data, unsigned int channel);
-int div3_ori_event_qurey_vdin2nr(unsigned int channel);
-int div3_ori_event_reset(unsigned int channel);
-int div3_ori_event_light_unreg(unsigned int channel);
-int div3_ori_event_light_unreg_revframe(unsigned int channel);
-//int di_ori_event_ready(unsigned int channel);
-//int div3_ori_event_qurey_state(unsigned int channel);
-void div3_ori_event_set_3D(int type, void *data, unsigned int channel);
-
-/*--------------------------*/
-extern int prev3_run_flag;
-extern unsigned int dbgv3_first_cnt_pre;
-extern spinlock_t plistv3_lock;
-
-void dimv3_dbg_pre_cnt(unsigned int channel, char *item);
-
-void diextv3_clk_b_sw(bool on);
-
-//int di_vf_l_states(struct vframe_states *states, unsigned int channel);
-
-
-unsigned char dimv3_pre_de_buf_config_p_asi(unsigned int ch);
-void dimv3_post_keep_back_recycle(unsigned int ch);
-void dbgv3_mode(unsigned int position);
-bool dimv3_post_keep_release_all_2free(unsigned int ch);
-
-
-/*---------------------*/
-
-ssize_t
-storev3_config(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count);
-ssize_t
-storev3_dbg(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count);
-ssize_t
-storev3_dump_mem(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len);
-ssize_t
-storev3_log(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count);
-ssize_t
-showv3_vframe_status(struct device *dev,
- struct device_attribute *attr,
- char *buf);
-
-ssize_t dimv3_read_log(char *buf);
-int dimv3_get_invert_tb(void);
-enum EDPST_MODE;
-struct di_win_s;
-
-void div3_cnt_cvs(enum EDPST_MODE mode,
- struct di_win_s *in,
- struct di_win_s *out);
-
-/*---------------------*/
-
-struct di_buf_s *dimv3_get_buf(unsigned int channel,
- int queue_idx, int *start_pos);
-
-#define queue_for_each_entry(di_buf, channel, queue_idx, list) \
- for (itmp = 0; \
- ((di_buf = dimv3_get_buf(channel, queue_idx, &itmp)) != NULL);)
-
-#define di_dev_t struct di_dev_s
-
-#define di_pr_info(fmt, args ...) pr_info("DIV3: " fmt, ## args)
-
-#define pr_dbg(fmt, args ...) pr_debug("DIV3: " fmt, ## args)
-
-#define pr_error(fmt, args ...) pr_err("DIV3: " fmt, ## args)
-
-/*this is debug for buf*/
-/*#define DI_DEBUG_POST_BUF_FLOW (1)*/
-#define DIM_DEBUG_QUE_ERR (1)
-//#define TST_NEW_INS_INTERFACE (1)
-//#define TST_NEW_INS_RUN_Q (1)
-#define TST_OVFM_BY_DI (1)
-/* DI_MOVE_POST 2019-09-23 move post function*/
-/********************************************************************
- *history:
- * 2019-09-20: test input 4k mode
- * 2019-09-24:
- * add dpst_cma_alloc|dpst_cma_release
- * add bset | bclr | bget
- * 2019-10-11: begin to split hw layer
- * add di_pre_hw.c|.h
- * add dim_mcinfo_v_alloc / release for mcinfo buf phy to v
- * 2019-11-14: add dim_hpre_ops (function is null now)
- * move pre_vinfo_set from di_pre.c to di_pre_hw.c
- * 2019-11-15: add qued
- * 2019-12-10: v need %4 issue
- * add V_DIV4
- *******************************************************************/
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace_dbg.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/printk.h>
-#include <linux/semaphore.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/list.h>
-#include <linux/of_irq.h>
-#include <linux/uaccess.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include "register.h"
-#include "deinterlace_dbg.h"
-#include "di_pps.h"
-#include "nr_downscale.h"
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include "deinterlace.h"
-
-#include "di_data_l.h"
-#include "di_que.h"
-#include "di_prc.h"
-#include "di_pre.h"
-#include "di_post.h"
-
-#include "di_vframe.h"
-
-/*2018-07-18 add debugfs*/
-#include <linux/seq_file.h>
-#include <linux/debugfs.h>
-/*2018-07-18 -----------*/
-
-void dimv3_parse_cmd_params(char *buf_orig, char **parm)
-{
- char *ps, *token;
- char delim1[3] = " ";
- char delim2[2] = "\n";
- unsigned int n = 0;
-
- strcat(delim1, delim2);
- ps = buf_orig;
- while (1) {
- token = strsep(&ps, delim1);
- if (!token)
- break;
- if (*token == '\0')
- continue;
- parm[n++] = token;
- }
-}
-
-static const unsigned int size_reg_addr1[] = {
- 0x1702, 0x1703, 0x2d01,
- 0x2d01, 0x2d8f, 0x2d08,
- 0x2d09, 0x2f00, 0x2f01,
- 0x17d0, 0x17d1, 0x17d2,
- 0x17d3, 0x17dd, 0x17de,
- 0x17df, 0x17e0, 0x17f7,
- 0x17f8, 0x17f9, 0x17fa,
- 0x17c0, 0x17c1, 0x17a0,
- 0x17a1, 0x17c3, 0x17c4,
- 0x17cb, 0x17cc, 0x17a3,
- 0x17a4, 0x17a5, 0x17a6,
- 0x2f92, 0x2f93, 0x2f95,
- 0x2f96, 0x2f98, 0x2f99,
- 0x2f9b, 0x2f9c, 0x2f65,
- 0x2f66, 0x2f67, 0x2f68,
- 0x1a53, 0x1a54, 0x1a55,
- 0x1a56, 0x17ea, 0x17eb,
- 0x17ec, 0x17ed, 0x2012,
- 0x2013, 0x2014, 0x2015,
- 0xffff
-};
-
-/*g12 new added*/
-static const unsigned int size_reg_addr2[] = {
- 0x37d2, 0x37d3, 0x37d7,
- 0x37d8, 0x37dc, 0x37dd,
- 0x37e1, 0x37e2, 0x37e6,
- 0x37e7, 0x37e9, 0x37ea,
- 0x37ed, 0x37ee, 0x37f1,
- 0x37f2, 0x37f4, 0x37f5,
- 0x37f6, 0x37f8, 0x3751,
- 0x3752, 0x376e, 0x376f,
- 0x37f9, 0x37fa, 0x37fc,
- 0x3740, 0x3757, 0x3762,
- 0xffff
-};
-
-/*2018-08-17 add debugfs*/
-static int seq_file_dump_di_reg_show(struct seq_file *seq, void *v)
-{
- unsigned int i = 0, base_addr = 0;
-
- if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
- base_addr = 0xff900000;
- else
- base_addr = 0xd0100000;
-
- seq_puts(seq, "----dump di reg----\n");
- seq_puts(seq, "----dump size reg---\n");
- /*txl crash when dump 0x37d2~0x3762 of size_reg_addr*/
- for (i = 0; size_reg_addr1[i] != 0xffff; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((size_reg_addr1[i]) << 2),
- size_reg_addr1[i], dimv3_RDMA_RD(size_reg_addr1[i]));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- for (i = 0; size_reg_addr2[i] != 0xffff; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((size_reg_addr2[i]) << 2),
- size_reg_addr2[i],
- dimv3_RDMA_RD(size_reg_addr2[i]));
- }
- for (i = 0; i < 255; i++) {
- if (i == 0x45)
- seq_puts(seq, "----nr reg----");
- if (i == 0x80)
- seq_puts(seq, "----3d reg----");
- if (i == 0x9e)
- seq_puts(seq, "---nr reg done---");
- if (i == 0x9c)
- seq_puts(seq, "---3d reg done---");
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x1700 + i) << 2),
- 0x1700 + i, dimv3_RDMA_RD(0x1700 + i));
- }
- for (i = 0; i < 4; i++) {
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x20ab + i) << 2),
- 0x20ab + i, dimv3_RDMA_RD(0x20ab + i));
- }
- seq_puts(seq, "----dump mcdi reg----\n");
- for (i = 0; i < 201; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2f00 + i) << 2),
- 0x2f00 + i, dimv3_RDMA_RD(0x2f00 + i));
- seq_puts(seq, "----dump pulldown reg----\n");
- for (i = 0; i < 26; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2fd0 + i) << 2),
- 0x2fd0 + i, dimv3_RDMA_RD(0x2fd0 + i));
- seq_puts(seq, "----dump bit mode reg----\n");
- for (i = 0; i < 4; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x20a7 + i) << 2),
- 0x20a7 + i, dimv3_RDMA_RD(0x20a7 + i));
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (0x2022 << 2),
- 0x2022, dimv3_RDMA_RD(0x2022));
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (0x17c1 << 2),
- 0x17c1, dimv3_RDMA_RD(0x17c1));
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (0x17c2 << 2),
- 0x17c2, dimv3_RDMA_RD(0x17c2));
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (0x1aa7 << 2),
- 0x1aa7, dimv3_RDMA_RD(0x1aa7));
- seq_puts(seq, "----dump dnr reg----\n");
- for (i = 0; i < 29; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2d00 + i) << 2),
- 0x2d00 + i, dimv3_RDMA_RD(0x2d00 + i));
- seq_puts(seq, "----dump if0 reg----\n");
- for (i = 0; i < 26; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x1a60 + i) << 2),
- 0x1a50 + i, dimv3_RDMA_RD(0x1a50 + i));
- seq_puts(seq, "----dump gate reg----\n");
- seq_printf(seq, "[0x%x][0x1718]=0x%x\n",
- base_addr + ((0x1718) << 2),
- dimv3_RDMA_RD(0x1718));
- for (i = 0; i < 5; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2006 + i) << 2),
- 0x2006 + i, dimv3_RDMA_RD(0x2006 + i));
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2dff) << 2),
- 0x2dff, dimv3_RDMA_RD(0x2dff));
- seq_puts(seq, "----dump if2 reg----\n");
- for (i = 0; i < 29; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + ((0x2010 + i) << 2),
- 0x2010 + i, dimv3_RDMA_RD(0x2010 + i));
- if (!is_meson_txl_cpu()) {
- seq_puts(seq, "----dump nr4 reg----\n");
- for (i = 0x2da4; i < 0x2df6; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2),
- i, dimv3_RDMA_RD(i));
- for (i = 0x3700; i < 0x373f; i++)
- seq_printf(seq, "[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2),
- i, dimv3_RDMA_RD(i));
- }
- seq_puts(seq, "----dump reg done----\n");
- return 0;
-}
-
-static void dump_mif_state(struct DI_MIF_s *mif)
-{
- pr_info("luma <%u, %u> <%u %u>.\n",
- mif->luma_x_start0, mif->luma_x_end0,
- mif->luma_y_start0, mif->luma_y_end0);
- pr_info("chroma <%u, %u> <%u %u>.\n",
- mif->chroma_x_start0, mif->chroma_x_end0,
- mif->chroma_y_start0, mif->chroma_y_end0);
- pr_info("canvas id <%u %u %u>.\n",
- mif->canvas0_addr0,
- mif->canvas0_addr1,
- mif->canvas0_addr2);
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dump_mif_state*/
-static void dump_mif_state_seq(struct DI_MIF_s *mif,
- struct seq_file *seq)
-{
- seq_printf(seq, "luma <%u, %u> <%u %u>.\n",
- mif->luma_x_start0, mif->luma_x_end0,
- mif->luma_y_start0, mif->luma_y_end0);
- seq_printf(seq, "chroma <%u, %u> <%u %u>.\n",
- mif->chroma_x_start0, mif->chroma_x_end0,
- mif->chroma_y_start0, mif->chroma_y_end0);
- seq_printf(seq, "canvas id <%u %u %u>.\n",
- mif->canvas0_addr0,
- mif->canvas0_addr1,
- mif->canvas0_addr2);
-}
-
-static void dump_simple_mif_state(struct DI_SIM_MIF_s *simp_mif)
-{
- pr_info("<%u %u> <%u %u>.\n",
- simp_mif->start_x, simp_mif->end_x,
- simp_mif->start_y, simp_mif->end_y);
- pr_info("canvas num <%u>.\n",
- simp_mif->canvas_num);
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dump_simple_mif_state*/
-static void dump_simple_mif_state_seq(struct DI_SIM_MIF_s *simp_mif,
- struct seq_file *seq)
-{
- seq_printf(seq, "<%u %u> <%u %u>.\n",
- simp_mif->start_x, simp_mif->end_x,
- simp_mif->start_y, simp_mif->end_y);
- seq_printf(seq, "canvas num <%u>.\n",
- simp_mif->canvas_num);
-}
-
-static void dump_mc_mif_state(struct DI_MC_MIF_s *mc_mif)
-{
- pr_info("startx %u,<%u %u>, size <%u %u>.\n",
- mc_mif->start_x, mc_mif->start_y,
- mc_mif->end_y, mc_mif->size_x,
- mc_mif->size_y);
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dump_mc_mif_state*/
-static void dump_mc_mif_state_seq(struct DI_MC_MIF_s *mc_mif,
- struct seq_file *seq)
-{
- seq_printf(seq, "startx %u,<%u %u>, size <%u %u>.\n",
- mc_mif->start_x, mc_mif->start_y,
- mc_mif->end_y, mc_mif->size_x,
- mc_mif->size_y);
-}
-
-void dimv3_dump_pre_stru(struct di_pre_stru_s *ppre)
-{
- pr_info("di_pre_stru:\n");
- pr_info("di_mem_buf_dup_p = 0x%p\n",
- ppre->di_mem_buf_dup_p);
- pr_info("di_chan2_buf_dup_p = 0x%p\n",
- ppre->di_chan2_buf_dup_p);
- pr_info("in_seq = %d\n",
- ppre->in_seq);
- pr_info("recycle_seq = %d\n",
- ppre->recycle_seq);
- pr_info("pre_ready_seq = %d\n",
- ppre->pre_ready_seq);
- pr_info("pre_de_busy = %d\n",
- ppre->pre_de_busy);
-
- pr_info("pre_de_process_flag = %d\n",
- ppre->pre_de_process_flag);
- pr_info("pre_de_irq_timeout_count=%d\n",
- ppre->pre_de_irq_timeout_count);
-
- pr_info("cur_width = %d\n",
- ppre->cur_width);
- pr_info("cur_height = %d\n",
- ppre->cur_height);
- pr_info("cur_inp_type = 0x%x\n",
- ppre->cur_inp_type);
- pr_info("cur_source_type = %d\n",
- ppre->cur_source_type);
- pr_info("cur_prog_flag = %d\n",
- ppre->cur_prog_flag);
- pr_info("source_change_flag = %d\n",
- ppre->source_change_flag);
- pr_info("bypass_flag = %s\n",
- ppre->bypass_flag ? "true" : "false");
- pr_info("prog_proc_type = %d\n",
- ppre->prog_proc_type);
- pr_info("madi_enable = %u\n",
- ppre->madi_enable);
- pr_info("mcdi_enable = %u\n",
- ppre->mcdi_enable);
-#ifdef DET3D
- pr_info("vframe_interleave_flag = %d\n",
- ppre->vframe_interleave_flag);
-#endif
- pr_info("left_right = %d\n",
- ppre->left_right);
- pr_info("force_interlace = %s\n",
- ppre->force_interlace ? "true" : "false");
- pr_info("vdin2nr = %d\n",
- ppre->vdin2nr);
- pr_info("bypass_pre = %s\n",
- ppre->bypass_pre ? "true" : "false");
- pr_info("invert_flag = %s\n",
- ppre->invert_flag ? "true" : "false");
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dim_dump_pre_stru*/
-static int dump_di_pre_stru_seq(struct seq_file *seq, void *v,
- unsigned int channel)
-
-{
- struct di_pre_stru_s *di_pre_stru_p = get_pre_stru(channel);
-
- seq_printf(seq, "di_pre_stru[%d]:\n", channel);
- seq_printf(seq, "%-25s = 0x%p\n", "di_mem_buf_dup_p",
- di_pre_stru_p->di_mem_buf_dup_p);
- seq_printf(seq, "%-25s = 0x%p\n", "di_chan2_buf_dup_p",
- di_pre_stru_p->di_chan2_buf_dup_p);
- seq_printf(seq, "%-25s = %d\n", "in_seq",
- di_pre_stru_p->in_seq);
- seq_printf(seq, "%-25s = %d\n", "recycle_seq",
- di_pre_stru_p->recycle_seq);
- seq_printf(seq, "%-25s = %d\n", "pre_ready_seq",
- di_pre_stru_p->pre_ready_seq);
- seq_printf(seq, "%-25s = %d\n", "pre_de_busy",
- di_pre_stru_p->pre_de_busy);
- seq_printf(seq, "%-25s = %d\n", "pre_de_process_flag",
- di_pre_stru_p->pre_de_process_flag);
- seq_printf(seq, "%-25s =%d\n", "pre_de_irq_timeout_count",
- di_pre_stru_p->pre_de_irq_timeout_count);
- seq_printf(seq, "%-25s = %d\n", "cur_width",
- di_pre_stru_p->cur_width);
- seq_printf(seq, "%-25s = %d\n", "cur_height",
- di_pre_stru_p->cur_height);
- seq_printf(seq, "%-25s = 0x%x\n", "cur_inp_type",
- di_pre_stru_p->cur_inp_type);
- seq_printf(seq, "%-25s = %d\n", "cur_source_type",
- di_pre_stru_p->cur_source_type);
- seq_printf(seq, "%-25s = %d\n", "cur_prog_flag",
- di_pre_stru_p->cur_prog_flag);
- seq_printf(seq, "%-25s = %d\n", "source_change_flag",
- di_pre_stru_p->source_change_flag);
- seq_printf(seq, "%-25s = %s\n", "bypass_flag",
- di_pre_stru_p->bypass_flag ? "true" : "false");
- seq_printf(seq, "%-25s = %d\n", "prog_proc_type",
- di_pre_stru_p->prog_proc_type);
- seq_printf(seq, "%-25s = %d\n", "madi_enable",
- di_pre_stru_p->madi_enable);
- seq_printf(seq, "%-25s = %d\n", "mcdi_enable",
- di_pre_stru_p->mcdi_enable);
-#ifdef DET3D
- seq_printf(seq, "%-25s = %d\n", "vframe_interleave_flag",
- di_pre_stru_p->vframe_interleave_flag);
-#endif
- seq_printf(seq, "%-25s = %d\n", "left_right",
- di_pre_stru_p->left_right);
- seq_printf(seq, "%-25s = %s\n", "force_interlace",
- di_pre_stru_p->force_interlace ? "true" : "false");
- seq_printf(seq, "%-25s = %d\n", "vdin2nr",
- di_pre_stru_p->vdin2nr);
- seq_printf(seq, "%-25s = %s\n", "bypass_pre",
- di_pre_stru_p->bypass_pre ? "true" : "false");
- seq_printf(seq, "%-25s = %s\n", "invert_flag",
- di_pre_stru_p->invert_flag ? "true" : "false");
-
- return 0;
-}
-
-void dimv3_dump_post_stru(struct di_post_stru_s *di_post_stru_p)
-{
- pr_info("\ndi_post_stru:\n");
- pr_info("run_early_proc_fun_flag = %d\n",
- di_post_stru_p->run_early_proc_fun_flag);
- pr_info("cur_disp_index = %d\n",
- di_post_stru_p->cur_disp_index);
- pr_info("post_de_busy = %d\n",
- di_post_stru_p->post_de_busy);
- pr_info("de_post_process_done = %d\n",
- di_post_stru_p->de_post_process_done);
- pr_info("cur_post_buf = 0x%p\n",
- di_post_stru_p->cur_post_buf);
- pr_info("post_peek_underflow = %u\n",
- di_post_stru_p->post_peek_underflow);
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dim_dump_post_stru*/
-static int dump_di_post_stru_seq(struct seq_file *seq, void *v,
- unsigned int channel)
-{
- struct di_post_stru_s *di_post_stru_p = get_post_stru(channel);
-
- seq_printf(seq, "di_post_stru[%d]:\n", channel);
- seq_printf(seq, "run_early_proc_fun_flag = %d\n",
- di_post_stru_p->run_early_proc_fun_flag);
- seq_printf(seq, "cur_disp_index = %d\n",
- di_post_stru_p->cur_disp_index);
- seq_printf(seq, "post_de_busy = %d\n",
- di_post_stru_p->post_de_busy);
- seq_printf(seq, "de_post_process_done = %d\n",
- di_post_stru_p->de_post_process_done);
- seq_printf(seq, "cur_post_buf = 0x%p\n",
- di_post_stru_p->cur_post_buf);
- seq_printf(seq, "post_peek_underflow = %u\n",
- di_post_stru_p->post_peek_underflow);
- seq_printf(seq, "frame_cnt = %u\n",
- di_post_stru_p->frame_cnt);
-
- return 0;
-}
-
-void dimv3_dump_mif_size_state(struct di_pre_stru_s *pre_stru_p,
- struct di_post_stru_s *post_stru_p)
-{
- pr_info("======pre mif status======\n");
- pr_info("DI_PRE_CTRL=0x%x\n", Rd(DI_PRE_CTRL));
- pr_info("DI_PRE_SIZE H=%d, V=%d\n",
- (Rd(DI_PRE_SIZE) >> 16) & 0xffff,
- Rd(DI_PRE_SIZE) & 0xffff);
- pr_info("DNR_HVSIZE=0x%x\n", Rd(DNR_HVSIZE));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- pr_info("CONTWR_CAN_SIZE=0x%x\n", Rd(0x37ec));
- pr_info("MTNWR_CAN_SIZE=0x%x\n", Rd(0x37f0));
- }
- pr_info("DNR_STAT_X_START_END=0x%x\n", Rd(0x2d08));
- pr_info("DNR_STAT_Y_START_END=0x%x\n", Rd(0x2d09));
- pr_info("MCDI_HV_SIZEIN=0x%x\n", Rd(0x2f00));
- pr_info("MCDI_HV_BLKSIZEIN=0x%x\n", Rd(0x2f01));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- pr_info("MCVECWR_CAN_SIZE=0x%x\n", Rd(0x37f4));
- pr_info("MCINFWR_CAN_SIZE=0x%x\n", Rd(0x37f8));
- pr_info("NRDSWR_CAN_SIZE=0x%x\n", Rd(0x37fc));
- pr_info("NR_DS_BUF_SIZE=0x%x\n", Rd(0x3740));
- }
-
- pr_info("=====inp mif:\n");
-#if 0
- Wr(DI_DBG_CTRL, 0x1b);
- Wr(DI_DBG_CTRL1, 0x640064);
- Wr_reg_bits(DI_PRE_GL_CTRL, 0, 31, 1);
- Wr_reg_bits(DI_PRE_CTRL, 0, 11, 1);
- Wr_reg_bits(DI_PRE_CTRL, 1, 31, 1);
- Wr_reg_bits(DI_PRE_GL_CTRL, 1, 31, 1);
- pr_info("DI_DBG_SRDY_INF=0x%x\n", Rd(DI_DBG_SRDY_INF));
- pr_info("DI_DBG_RRDY_INF=0x%x\n", Rd(DI_DBG_RRDY_INF));
-#endif
- pr_info("DI_INP_GEN_REG=0x%x\n", Rd(DI_INP_GEN_REG));
- dump_mif_state(&pre_stru_p->di_inp_mif);
- pr_info("=====mem mif:\n");
- pr_info("DI_MEM_GEN_REG=0x%x\n", Rd(DI_MEM_GEN_REG));
- dump_mif_state(&pre_stru_p->di_mem_mif);
- pr_info("=====chan2 mif:\n");
- pr_info("DI_CHAN2_GEN_REG=0x%x\n", Rd(DI_CHAN2_GEN_REG));
- dump_mif_state(&pre_stru_p->di_chan2_mif);
- pr_info("=====nrwr mif:\n");
- pr_info("DI_NRWR_CTRL=0x%x\n", Rd(DI_NRWR_CTRL));
- dump_simple_mif_state(&pre_stru_p->di_nrwr_mif);
- pr_info("=====mtnwr mif:\n");
- dump_simple_mif_state(&pre_stru_p->di_mtnwr_mif);
- pr_info("=====contp2rd mif:\n");
- dump_simple_mif_state(&pre_stru_p->di_contp2rd_mif);
- pr_info("=====contprd mif:\n");
- dump_simple_mif_state(&pre_stru_p->di_contprd_mif);
- pr_info("=====contwr mif:\n");
- dump_simple_mif_state(&pre_stru_p->di_contwr_mif);
- pr_info("=====mcinford mif:\n");
- dump_mc_mif_state(&pre_stru_p->di_mcinford_mif);
- pr_info("=====mcinfowr mif:\n");
- dump_mc_mif_state(&pre_stru_p->di_mcinfowr_mif);
- pr_info("=====mcvecwr mif:\n");
- dump_mc_mif_state(&pre_stru_p->di_mcvecwr_mif);
- pr_info("======post mif status======\n");
- pr_info("DI_POST_SIZE=0x%x\n", Rd(DI_POST_SIZE));
- pr_info("DECOMB_FRM_SIZE=0x%x\n", Rd(0x2d8f));
- pr_info("=====if0 mif:\n");
- pr_info("DI_IF0_GEN_REG=0x%x\n", Rd(0x2030));
- dump_mif_state(&post_stru_p->di_buf0_mif);
- pr_info("=====if1 mif:\n");
- pr_info("DI_IF1_GEN_REG=0x%x\n", Rd(0x17e8));
- dump_mif_state(&post_stru_p->di_buf1_mif);
- pr_info("=====if2 mif:\n");
- pr_info("DI_IF2_GEN_REG=0x%x\n", Rd(0x2010));
- dump_mif_state(&post_stru_p->di_buf2_mif);
- pr_info("=====diwr mif:\n");
- dump_simple_mif_state(&post_stru_p->di_diwr_mif);
- pr_info("=====mtnprd mif:\n");
- dump_simple_mif_state(&post_stru_p->di_mtnprd_mif);
- pr_info("=====mcvecrd mif:\n");
- dump_mc_mif_state(&post_stru_p->di_mcvecrd_mif);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- pr_info("======pps size status======\n");
- pr_info("DI_SC_LINE_IN_LENGTH=0x%x\n", Rd(0x3751));
- pr_info("DI_SC_PIC_IN_HEIGHT=0x%x\n", Rd(0x3752));
- pr_info("DI_HDR_IN_HSIZE=0x%x\n", Rd(0x376e));
- pr_info("DI_HDR_IN_VSIZE=0x%x\n", Rd(0x376f));
- }
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dump_mif_size_state*/
-int dimv3_dump_mif_size_state_show(struct seq_file *seq,
- void *v, unsigned int channel)
-{
- struct di_pre_stru_s *di_pre_stru_p;
- struct di_post_stru_s *di_post_stru_p;
-
- di_pre_stru_p = get_pre_stru(channel);
- di_post_stru_p = get_post_stru(channel);
-
- seq_puts(seq, "======pre mif status======\n");
- seq_printf(seq, "DI_PRE_CTRL=0x%x\n", Rd(DI_PRE_CTRL));
- seq_printf(seq, "DI_PRE_SIZE=0x%x\n", Rd(DI_PRE_SIZE));
- seq_printf(seq, "DNR_HVSIZE=0x%x\n", Rd(DNR_HVSIZE));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- seq_printf(seq, "CONTWR_CAN_SIZE=0x%x\n", Rd(0x37ec));
- seq_printf(seq, "MTNWR_CAN_SIZE=0x%x\n", Rd(0x37f0));
- }
- seq_printf(seq, "DNR_STAT_X_START_END=0x%x\n", Rd(0x2d08));
- seq_printf(seq, "DNR_STAT_Y_START_END=0x%x\n", Rd(0x2d09));
- seq_printf(seq, "MCDI_HV_SIZEIN=0x%x\n", Rd(0x2f00));
- seq_printf(seq, "MCDI_HV_BLKSIZEIN=0x%x\n", Rd(0x2f01));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- seq_printf(seq, "MCVECWR_CAN_SIZE=0x%x\n", Rd(0x37f4));
- seq_printf(seq, "MCINFWR_CAN_SIZE=0x%x\n", Rd(0x37f8));
- seq_printf(seq, "NRDSWR_CAN_SIZE=0x%x\n", Rd(0x37fc));
- seq_printf(seq, "NR_DS_BUF_SIZE=0x%x\n", Rd(0x3740));
- }
-
- seq_puts(seq, "=====inp mif:\n");
-
- seq_printf(seq, "DI_INP_GEN_REG=0x%x\n", Rd(DI_INP_GEN_REG));
- dump_mif_state_seq(&di_pre_stru_p->di_inp_mif, seq);/*dump_mif_state*/
- seq_puts(seq, "=====mem mif:\n");
- seq_printf(seq, "DI_MEM_GEN_REG=0x%x\n", Rd(DI_MEM_GEN_REG));
- dump_mif_state_seq(&di_pre_stru_p->di_mem_mif, seq);
- seq_puts(seq, "=====chan2 mif:\n");
- seq_printf(seq, "DI_CHAN2_GEN_REG=0x%x\n", Rd(DI_CHAN2_GEN_REG));
- dump_mif_state_seq(&di_pre_stru_p->di_chan2_mif, seq);
- seq_puts(seq, "=====nrwr mif:\n");
- seq_printf(seq, "DI_NRWR_CTRL=0x%x\n", Rd(DI_NRWR_CTRL));
- /*dump_simple_mif_state*/
- dump_simple_mif_state_seq(&di_pre_stru_p->di_nrwr_mif, seq);
- seq_puts(seq, "=====mtnwr mif:\n");
- dump_simple_mif_state_seq(&di_pre_stru_p->di_mtnwr_mif, seq);
- seq_puts(seq, "=====contp2rd mif:\n");
- dump_simple_mif_state_seq(&di_pre_stru_p->di_contp2rd_mif, seq);
- seq_puts(seq, "=====contprd mif:\n");
- dump_simple_mif_state_seq(&di_pre_stru_p->di_contprd_mif, seq);
- seq_puts(seq, "=====contwr mif:\n");
- dump_simple_mif_state_seq(&di_pre_stru_p->di_contwr_mif, seq);
- seq_puts(seq, "=====mcinford mif:\n");
- /*dump_mc_mif_state*/
- dump_mc_mif_state_seq(&di_pre_stru_p->di_mcinford_mif, seq);
- seq_puts(seq, "=====mcinfowr mif:\n");
- dump_mc_mif_state_seq(&di_pre_stru_p->di_mcinfowr_mif, seq);
- seq_puts(seq, "=====mcvecwr mif:\n");
- dump_mc_mif_state_seq(&di_pre_stru_p->di_mcvecwr_mif, seq);
- seq_puts(seq, "======post mif status======\n");
- seq_printf(seq, "DI_POST_SIZE=0x%x\n", Rd(DI_POST_SIZE));
- seq_printf(seq, "DECOMB_FRM_SIZE=0x%x\n", Rd(0x2d8f));
- seq_puts(seq, "=====if0 mif:\n");
- seq_printf(seq, "DI_IF0_GEN_REG=0x%x\n", Rd(0x2030));
- dump_mif_state_seq(&di_post_stru_p->di_buf0_mif, seq);
- seq_puts(seq, "=====if1 mif:\n");
- seq_printf(seq, "DI_IF1_GEN_REG=0x%x\n", Rd(0x17e8));
- dump_mif_state_seq(&di_post_stru_p->di_buf1_mif, seq);
- seq_puts(seq, "=====if2 mif:\n");
- seq_printf(seq, "DI_IF2_GEN_REG=0x%x\n", Rd(0x2010));
- dump_mif_state_seq(&di_post_stru_p->di_buf2_mif, seq);
- seq_puts(seq, "=====diwr mif:\n");
- dump_simple_mif_state_seq(&di_post_stru_p->di_diwr_mif, seq);
- seq_puts(seq, "=====mtnprd mif:\n");
- dump_simple_mif_state_seq(&di_post_stru_p->di_mtnprd_mif, seq);
- seq_puts(seq, "=====mcvecrd mif:\n");
- dump_mc_mif_state_seq(&di_post_stru_p->di_mcvecrd_mif, seq);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- seq_puts(seq, "======pps size status======\n");
- seq_printf(seq, "DI_SC_LINE_IN_LENGTH=0x%x\n", Rd(0x3751));
- seq_printf(seq, "DI_SC_PIC_IN_HEIGHT=0x%x\n", Rd(0x3752));
- seq_printf(seq, "DI_HDR_IN_HSIZE=0x%x\n", Rd(0x376e));
- seq_printf(seq, "DI_HDR_IN_VSIZE=0x%x\n", Rd(0x376f));
- }
- return 0;
-}
-
-void dimv3_dump_di_buf(struct di_buf_s *di_buf)
-{
- pr_info("di_buf %p vframe %p:\n", di_buf, di_buf->vframe);
- pr_info("index %d, post_proc_flag %d, new_format_flag %d, type %d,",
- di_buf->index, di_buf->c.post_proc_flag,
- di_buf->c.new_format_flag, di_buf->type);
- pr_info("seq %d, pre_ref_count %d,post_ref_count %d, queue_index %d,",
- di_buf->c.seq, di_buf->c.pre_ref_count,
- di_buf->c.post_ref_count,
- di_buf->queue_index);
- pr_info("pulldown_mode %d process_fun_index %d\n",
- di_buf->c.pd_config.global_mode, di_buf->c.process_fun_index);
- pr_info("di_buf: %p, %p, di_buf_dup_p: %p, %p, %p, %p, %p\n",
- di_buf->c.di_buf[0], di_buf->c.di_buf[1],
- di_buf->c.di_buf_dup_p[0],
- di_buf->c.di_buf_dup_p[1], di_buf->c.di_buf_dup_p[2],
- di_buf->c.di_buf_dup_p[3], di_buf->c.di_buf_dup_p[4]);
- pr_info(
- "nr_adr 0x%lx, nr_canvas_idx 0x%x, mtn_adr 0x%lx, mtn_canvas_idx 0x%x",
- di_buf->nr_adr, di_buf->nr_canvas_idx, di_buf->mtn_adr,
- di_buf->mtn_canvas_idx);
- pr_info("cnt_adr 0x%lx, cnt_canvas_idx 0x%x\n",
- di_buf->cnt_adr, di_buf->cnt_canvas_idx);
- pr_info("di_cnt %d, priveated %u.\n",
- atomic_read(&di_buf->c.di_cnt), di_buf->c.privated);
-}
-
-void dimv3_dump_pool(struct queue_s *q)
-{
- int j;
-
- pr_info("queue: in_idx %d, out_idx %d, num %d, type %d\n",
- q->in_idx, q->out_idx, q->num, q->type);
- for (j = 0; j < MAX_QUEUE_POOL_SIZE; j++) {
- pr_info("0x%x ", q->pool[j]);
- if (((j + 1) % 16) == 0)
- pr_debug("\n");
- }
- pr_info("\n");
-}
-
-void dimv3_dump_vframe(struct vframe_s *vf)
-{
- pr_info("vframe %p:\n", vf);
- pr_info("index %d, type 0x%x, type_backup 0x%x, blend_mode %d bitdepth %d\n",
- vf->index, vf->type, vf->type_backup,
- vf->blend_mode, (vf->bitdepth & BITDEPTH_Y10) ? 10 : 8);
- pr_info("duration %d, duration_pulldown %d, pts %d, flag 0x%x\n",
- vf->duration, vf->duration_pulldown, vf->pts, vf->flag);
- pr_info("canvas0Addr 0x%x, canvas1Addr 0x%x, bufWidth %d\n",
- vf->canvas0Addr, vf->canvas1Addr, vf->bufWidth);
- pr_info("width %d, height %d, ratio_control 0x%x, orientation 0x%x\n",
- vf->width, vf->height, vf->ratio_control, vf->orientation);
- pr_info("source_type %d, phase %d, soruce_mode %d, sig_fmt %d\n",
- vf->source_type, vf->phase, vf->source_mode, vf->sig_fmt);
- pr_info(
- "trans_fmt 0x%x, lefteye(%d %d %d %d), righteye(%d %d %d %d)\n",
- vf->trans_fmt, vf->left_eye.start_x, vf->left_eye.start_y,
- vf->left_eye.width, vf->left_eye.height,
- vf->right_eye.start_x, vf->right_eye.start_y,
- vf->right_eye.width, vf->right_eye.height);
- pr_info("mode_3d_enable %d, use_cnt %d,",
- vf->mode_3d_enable, atomic_read(&vf->use_cnt));
- pr_info("early_process_fun 0x%p, process_fun 0x%p, private_data %p\n",
- vf->early_process_fun,
- vf->process_fun, vf->private_data);
- pr_info("pixel_ratio %d list %p\n",
- vf->pixel_ratio, &vf->list);
-}
-
-void dimv3_print_di_buf(struct di_buf_s *di_buf, int format)
-{
- if (!di_buf)
- return;
- if (format == 1) {
- pr_info(
- "\t+index %d, 0x%p, type %d, vframetype 0x%x, trans_fmt %u,bitdepath %d\n",
- di_buf->index,
- di_buf,
- di_buf->type,
- di_buf->vframe->type,
- di_buf->vframe->trans_fmt,
- di_buf->vframe->bitdepth);
- if (di_buf->c.di_wr_linked_buf) {
- pr_info("\tlinked +index %d, 0x%p, type %d\n",
- di_buf->c.di_wr_linked_buf->index,
- di_buf->c.di_wr_linked_buf,
- di_buf->c.di_wr_linked_buf->type);
- }
- } else if (format == 2) {
- pr_info("index %d, 0x%p(vframe 0x%p), type %d\n",
- di_buf->index, di_buf,
- di_buf->vframe, di_buf->type);
- pr_info("vframetype 0x%x, trans_fmt %u,duration %d pts %d,bitdepth %d\n",
- di_buf->vframe->type,
- di_buf->vframe->trans_fmt,
- di_buf->vframe->duration,
- di_buf->vframe->pts,
- di_buf->vframe->bitdepth);
- if (di_buf->c.di_wr_linked_buf) {
- pr_info("linked index %d, 0x%p, type %d\n",
- di_buf->c.di_wr_linked_buf->index,
- di_buf->c.di_wr_linked_buf,
- di_buf->c.di_wr_linked_buf->type);
- }
- }
-}
-
-/*2018-08-17 add debugfs*/
-/*same as print_di_buf*/
-static void print_di_buf_seq(struct di_buf_s *di_buf, int format,
- struct seq_file *seq)
-{
- if (!di_buf)
- return;
- if (format == 1) {
- seq_printf(seq, "\t+index %d, 0x%p, type %d, omx%d\n",
- di_buf->index,
- di_buf,
- di_buf->type,
- di_buf->vframe->omx_index);
- seq_printf(seq, "vframetype 0x%x, trans_fmt %u,bitdepath %d\n",
- di_buf->vframe->type,
- di_buf->vframe->trans_fmt,
- di_buf->vframe->bitdepth);
- seq_printf(seq, "\t\tsts 0x%x,seq:%d\n",
- di_buf->c.sts, di_buf->c.seq);
- if (di_buf->c.di_wr_linked_buf) {
- seq_printf(seq, "\tlinked +index %d, 0x%p, type %d\n",
- di_buf->c.di_wr_linked_buf->index,
- di_buf->c.di_wr_linked_buf,
- di_buf->c.di_wr_linked_buf->type);
- }
- } else if (format == 2) {
- seq_printf(seq, "index %d, 0x%p(vframe 0x%p), type %d, omx%d, sts 0x%x\n",
- di_buf->index, di_buf,
- di_buf->vframe, di_buf->type,
- di_buf->vframe->omx_index,
- di_buf->c.sts);
- seq_printf(seq, "vfmtype 0x%x, trans_fmt %u\n",
- di_buf->vframe->type,
- di_buf->vframe->trans_fmt);
- seq_printf(seq, ",duration %d pts %d,bitdepth %d\n",
- di_buf->vframe->duration,
- di_buf->vframe->pts,
- di_buf->vframe->bitdepth);
- if (di_buf->c.di_wr_linked_buf) {
- seq_printf(seq, "linked index %d, 0x%p, type %d\n",
- di_buf->c.di_wr_linked_buf->index,
- di_buf->c.di_wr_linked_buf,
- di_buf->c.di_wr_linked_buf->type);
- }
- }
-}
-
-void dimv3_dump_pre_mif_state(void)
-{
- unsigned int i = 0;
-
- Wr_reg_bits(DI_INP_GEN_REG3, 3, 10, 2);
- Wr_reg_bits(DI_MEM_GEN_REG3, 3, 10, 2);
- Wr_reg_bits(DI_CHAN2_GEN_REG3, 3, 10, 2);
- pr_info("DI_INP_GEN_REG2=0x%x.\n", Rd(DI_INP_GEN_REG2));
- pr_info("DI_INP_GEN_REG3=0x%x.\n", Rd(DI_INP_GEN_REG3));
- for (i = 0; i < 10; i++)
- pr_info("0x%x=0x%x.\n", 0x17ce + i, Rd(0x17ce + i));
- pr_info("DI_MEM_GEN_REG2=0x%x.\n", Rd(DI_MEM_GEN_REG2));
- pr_info("DI_MEM_GEN_REG3=0x%x.\n", Rd(DI_MEM_GEN_REG3));
- pr_info("DI_MEM_LUMA_FIFO_SIZE=0x%x.\n", Rd(DI_MEM_LUMA_FIFO_SIZE));
- for (i = 0; i < 10; i++)
- pr_info("0x%x=0x%x.\n", 0x17db + i, Rd(0x17db + i));
- pr_info("DI_CHAN2_GEN_REG2=0x%x.\n", Rd(DI_CHAN2_GEN_REG2));
- pr_info("DI_CHAN2_GEN_REG3=0x%x.\n", Rd(DI_CHAN2_GEN_REG3));
- pr_info("DI_CHAN2_LUMA_FIFO_SIZE=0x%x.\n", Rd(DI_CHAN2_LUMA_FIFO_SIZE));
- for (i = 0; i < 10; i++)
- pr_info("0x%x=0x%x.\n", 0x17f5 + i, Rd(0x17f5 + i));
-}
-
-void dimv3_dump_post_mif_reg(void)
-{
- pr_info("VIU_MISC_CTRL0=0x%x\n", Rd(VIU_MISC_CTRL0));
-
- pr_info("VD1_IF0_GEN_REG=0x%x\n", Rd(VD1_IF0_GEN_REG));
- pr_info("VD1_IF0_GEN_REG2=0x%x\n", Rd(VD1_IF0_GEN_REG2));
- pr_info("VD1_IF0_GEN_REG3=0x%x\n", Rd(VD1_IF0_GEN_REG3));
- pr_info("VD1_IF0_LUMA_X0=0x%x\n", Rd(VD1_IF0_LUMA_X0));
- pr_info("VD1_IF0_LUMA_Y0=0x%x\n", Rd(VD1_IF0_LUMA_Y0));
- pr_info("VD1_IF0_CHROMA_X0=0x%x\n", Rd(VD1_IF0_CHROMA_X0));
- pr_info("VD1_IF0_CHROMA_Y0=0x%x\n", Rd(VD1_IF0_CHROMA_Y0));
- pr_info("VD1_IF0_LUMA_X1=0x%x\n", Rd(VD1_IF0_LUMA_X1));
- pr_info("VD1_IF0_LUMA_Y1=0x%x\n", Rd(VD1_IF0_LUMA_Y1));
- pr_info("VD1_IF0_CHROMA_X1=0x%x\n", Rd(VD1_IF0_CHROMA_X1));
- pr_info("VD1_IF0_CHROMA_Y1=0x%x\n", Rd(VD1_IF0_CHROMA_Y1));
- pr_info("VD1_IF0_REPEAT_LOOP=0x%x\n", Rd(VD1_IF0_RPT_LOOP));
- pr_info("VD1_IF0_LUMA0_RPT_PAT=0x%x\n", Rd(VD1_IF0_LUMA0_RPT_PAT));
- pr_info("VD1_IF0_CHROMA0_RPT_PAT=0x%x\n", Rd(VD1_IF0_CHROMA0_RPT_PAT));
- pr_info("VD1_IF0_LUMA_PSEL=0x%x\n", Rd(VD1_IF0_LUMA_PSEL));
- pr_info("VD1_IF0_CHROMA_PSEL=0x%x\n", Rd(VD1_IF0_CHROMA_PSEL));
- pr_info("VIU_VD1_FMT_CTRL=0x%x\n", Rd(VIU_VD1_FMT_CTRL));
- pr_info("VIU_VD1_FMT_W=0x%x\n", Rd(VIU_VD1_FMT_W));
-
- pr_info("DI_IF1_GEN_REG=0x%x\n", Rd(DI_IF1_GEN_REG));
- pr_info("DI_IF1_GEN_REG2=0x%x\n", Rd(DI_IF1_GEN_REG2));
- pr_info("DI_IF1_GEN_REG3=0x%x\n", Rd(DI_IF1_GEN_REG3));
- pr_info("DI_IF1_CANVAS0=0x%x\n", Rd(DI_IF1_CANVAS0));
- pr_info("DI_IF1_LUMA_X0=0x%x\n", Rd(DI_IF1_LUMA_X0));
- pr_info("DI_IF1_LUMA_Y0=0x%x\n", Rd(DI_IF1_LUMA_Y0));
- pr_info("DI_IF1_CHROMA_X0=0x%x\n", Rd(DI_IF1_CHROMA_X0));
- pr_info("DI_IF1_CHROMA_Y0=0x%x\n", Rd(DI_IF1_CHROMA_Y0));
- pr_info("DI_IF1_LUMA0_RPT_PAT=0x%x\n", Rd(DI_IF1_LUMA0_RPT_PAT));
- pr_info("DI_IF1_CHROMA0_RPT_PAT=0x%x\n", Rd(DI_IF1_LUMA0_RPT_PAT));
- pr_info("DI_IF1_FMT_CTRL=0x%x\n", Rd(DI_IF1_FMT_CTRL));
- pr_info("DI_IF1_FMT_W=0x%x\n", Rd(DI_IF1_FMT_W));
-
- pr_info("DI_IF2_GEN_REG=0x%x\n", Rd(DI_IF2_GEN_REG));
- pr_info("DI_IF2_GEN_REG2=0x%x\n", Rd(DI_IF2_GEN_REG2));
- pr_info("DI_IF2_GEN_REG3=0x%x\n", Rd(DI_IF2_GEN_REG3));
- pr_info("DI_IF2_CANVAS0=0x%x\n", Rd(DI_IF2_CANVAS0));
- pr_info("DI_IF2_LUMA_X0=0x%x\n", Rd(DI_IF2_LUMA_X0));
- pr_info("DI_IF2_LUMA_Y0=0x%x\n", Rd(DI_IF2_LUMA_Y0));
- pr_info("DI_IF2_CHROMA_X0=0x%x\n", Rd(DI_IF2_CHROMA_X0));
- pr_info("DI_IF2_CHROMA_Y0=0x%x\n", Rd(DI_IF2_CHROMA_Y0));
- pr_info("DI_IF2_LUMA0_RPT_PAT=0x%x\n", Rd(DI_IF2_LUMA0_RPT_PAT));
- pr_info("DI_IF2_CHROMA0_RPT_PAT=0x%x\n", Rd(DI_IF2_LUMA0_RPT_PAT));
- pr_info("DI_IF2_FMT_CTRL=0x%x\n", Rd(DI_IF2_FMT_CTRL));
- pr_info("DI_IF2_FMT_W=0x%x\n", Rd(DI_IF2_FMT_W));
-
- pr_info("DI_DIWR_Y=0x%x\n", Rd(DI_DIWR_Y));
- pr_info("DI_DIWR_CTRL=0x%x", Rd(DI_DIWR_CTRL));
- pr_info("DI_DIWR_X=0x%x.\n", Rd(DI_DIWR_X));
-}
-
-void dimv3_dump_buf_addr(struct di_buf_s *di_buf, unsigned int num)
-{
- unsigned int i = 0;
- struct di_buf_s *di_buf_p = NULL;
-
- for (i = 0; i < num; i++) {
- di_buf_p = (di_buf + i);
- pr_info("di_buf[%d] nr_addr 0x%lx,",
- di_buf_p->index, di_buf_p->nr_adr);
- pr_info("mtn_addr 0x%lx, cnt_adr 0x%lx,",
- di_buf_p->mtn_adr, di_buf_p->cnt_adr);
- pr_info("mv_adr 0x%lx, mcinfo_adr 0x%lx.\n",
- di_buf_p->mcvec_adr, di_buf_p->mcinfo_adr);
- }
-}
-
-static int seq_file_module_para_show(struct seq_file *seq, void *v)
-{
- dimv3_seq_file_module_para_di(seq);
- dimv3_seq_file_module_para_hw(seq);
- dimv3_seq_file_module_para_pps(seq);
- get_ops_mtn()->module_para(seq);
- get_ops_nr()->module_para(seq);
- get_ops_pd()->module_para(seq);
-
- return 0;
-}
-
-/*2018-08-17 add debugfs*/
-/*same as dump_state*/
-int dimv3_state_show(struct seq_file *seq, void *v, unsigned int channel)
-{
- int itmp, i;
- struct di_buf_s *p = NULL, *keep_buf;/* ptmp; */
- struct di_pre_stru_s *di_pre_stru_p;
- struct di_post_stru_s *di_post_stru_p;
- /*struct di_dev_s *de_devp = get_dim_de_devp();*/
- const char *version_s = dimv3_get_version_s();
- int dump_state_flag = dimv3_get_dump_state_flag();
- unsigned char recovery_flag = dimv3_vcry_get_flg();
- unsigned int recovery_log_reason = dimv3_vcry_get_log_reason();
- int di_blocking = dimv3_get_blocking();
- unsigned int recovery_log_queue_idx = dimv3_vcry_get_log_q_idx();
- struct di_buf_s *recovery_log_di_buf = dimv3_get_recovery_log_di_buf();
- unsigned long reg_unreg_timeout_cnt = dimv3_get_reg_unreg_timeout_cnt();
- void **vframe_in = getv3_vframe_in(channel);
- unsigned int tmpa[MAX_FIFO_SIZE]; /*new que*/
- unsigned int psize; /*new que*/
- struct di_hpre_s *pre = get_hw_pre();
- struct di_hpst_s *post = get_hw_pst();
- char *splt = "---------------------------";
- struct di_mm_s *mm = dim_mm_get(channel); /*mm-0705*/
- struct di_ch_s *pch;
- struct di_buf_s *pbuf_local = get_buf_local(channel);
-
- di_pre_stru_p = get_pre_stru(channel);
- di_post_stru_p = get_post_stru(channel);
- pch = get_chdata(channel);
-
- PR_INF("%s:1\n", __func__);/*debug*/
- dump_state_flag = 1;
- seq_printf(seq, "%s:ch[%d]\n", __func__, channel);
- seq_printf(seq, "version %s, init_flag %d\n",
- version_s,
- get_init_flag(channel));
- seq_printf(seq, "recovery_flag = %d, reason=%d, di_blocking=%d",
- recovery_flag, recovery_log_reason, di_blocking);
- seq_printf(seq, "recovery_log_q_idx=%d, recovery_log_di_buf=0x%p\n",
- recovery_log_queue_idx, recovery_log_di_buf);
- seq_printf(seq, "buffer_size=%d, mem_flag=%s, cma_flag=%d\n",
- mm->cfg.size_local,
- div3_cma_dbg_get_st_name(channel),
- cfgg(mem_flg));
- keep_buf = di_post_stru_p->keep_buf;
- seq_printf(seq, "used_post_buf_index %d(0x%p),",
- IS_ERR_OR_NULL(keep_buf) ?
- -1 : keep_buf->index, keep_buf);
- if (!IS_ERR_OR_NULL(keep_buf)) {
- seq_puts(seq, "used_local_buf_index:\n");
- for (i = 0; i < USED_LOCAL_BUF_MAX; i++) {
- p = keep_buf->c.di_buf_dup_p[i];
- seq_printf(seq, "%d(0x%p) ",
- IS_ERR_OR_NULL(p) ? -1 : p->index, p);
- }
- }
- PR_INF("%s:2\n", __func__);/*debug*/
- /********************************/
- /* in_free_list */
- /********************************/
- div3_que_list(channel, QUE_IN_FREE, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "\nin_free_list max(%d) curr(%d):\n",
- MAX_IN_BUF_NUM, psize);
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
-
- seq_printf(seq, "index %2d, 0x%p, type %d\n",
- p->index, p, p->type);
- }
- seq_printf(seq, "%s\n", splt);
- /********************************/
- /* local_free_list */
- /********************************/
- itmp = listv3_count(channel, QUEUE_LOCAL_FREE);
- seq_printf(seq, "local_free_list (max %d):(curr %d)\n",
- mm->cfg.num_local, itmp);
- queue_for_each_entry(p, channel, QUEUE_LOCAL_FREE, list) {
- seq_printf(seq, "index %2d, 0x%p, type %d\n",
- p->index, p, p->type);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:3\n", __func__);/*debug*/
- /********************************/
- /* post_doing_list */
- /********************************/
- seq_puts(seq, "post_doing_list:\n");
- //queue_for_each_entry(p, channel, QUEUE_POST_DOING, list) {
- div3_que_list(channel, QUE_POST_DOING, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- print_di_buf_seq(p, 2, seq);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* pre_ready_list */
- /********************************/
- seq_puts(seq, "pre_ready_list:\n");
- div3_que_list(channel, QUE_PRE_READY, &tmpa[0], &psize); /*new que*/
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
-
- print_di_buf_seq(p, 2, seq);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:4\n", __func__);/*debug*/
-
- /********************************/
- /* post_free_list */
- /********************************/
- div3_que_list(channel, QUE_POST_FREE, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_free_list (max %d) (crr %d):\n",
- mm->cfg.num_post, psize);
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
-
- seq_printf(seq, "index %2d, 0x%p, type %d, vframetype 0x%x\n",
- p->index, p, p->type, p->vframe->type);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:5\n", __func__);/*debug*/
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(channel, QUE_POST_READY, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]); /*new que*/
-
- print_di_buf_seq(p, 2, seq);
- print_di_buf_seq(p->c.di_buf[0], 1, seq);
- print_di_buf_seq(p->c.di_buf[1], 1, seq);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* display_list */
- /********************************/
- seq_puts(seq, "display_list:\n");
- queue_for_each_entry(p, channel, QUEUE_DISPLAY, list) {
- print_di_buf_seq(p, 2, seq);
- print_di_buf_seq(p->c.di_buf[0], 1, seq);
- print_di_buf_seq(p->c.di_buf[1], 1, seq);
- seq_printf(seq, "\tblend:%d\n", p->c.pd_config.global_mode);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:6\n", __func__);/*debug*/
-
- /********************************/
- /* recycle_list */
- /********************************/
- seq_puts(seq, "recycle_list:\n");
- queue_for_each_entry(p, channel, QUEUE_RECYCLE, list) {
- seq_printf(seq,
- "index %d, 0x%p, type %d, vfm 0x%x pre %d postt %d\n",
- p->index, p, p->type,
- p->vframe->type,
- p->c.pre_ref_count,
- p->c.post_ref_count);
- if (p->c.di_wr_linked_buf) {
- seq_printf(seq,
- "ld index %2d, 0x%p, type %d pret %d pst %d\n",
- p->c.di_wr_linked_buf->index,
- p->c.di_wr_linked_buf,
- p->c.di_wr_linked_buf->type,
- p->c.di_wr_linked_buf->c.pre_ref_count,
- p->c.di_wr_linked_buf->c.post_ref_count);
- }
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:7\n", __func__);/*debug*/
- /********************************/
- /* tmp_list */
- /********************************/
- seq_printf(seq, "tmp_list:%d\n", listv3_count(channel, QUEUE_TMP));
- queue_for_each_entry(p, channel, QUEUE_TMP, list) {
- print_di_buf_seq(p, 2, seq);
- print_di_buf_seq(p->c.di_buf[0], 1, seq);
- print_di_buf_seq(p->c.di_buf[1], 1, seq);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:8\n", __func__);/*debug*/
- /********************************/
- /* local_list */
- /********************************/
- seq_puts(seq, "local list\n");
- for (i = 0; i < MAX_LOCAL_BUF_NUM * 2; i++) {
- p = &pbuf_local[i];
- if (!p->pages)
- continue;
- print_di_buf_seq(p, 2, seq);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:9\n", __func__);/*debug*/
-
- /********************************/
- /* post back */
- /********************************/
- div3_que_list(channel, QUE_POST_BACK, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_back: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- seq_printf(seq, "\ttype[%d],index[%d]\n", p->type, p->index);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* post keep */
- /********************************/
- div3_que_list(channel, QUE_POST_KEEP, &tmpa[0], &psize);
- seq_printf(seq, "post_keep: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- seq_printf(seq, "\ttype[%d],index[%d]\n", p->type, p->index);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:10\n", __func__);/*debug*/
-
- /********************************
- * post keep back
- ********************************/
- div3_que_list(channel, QUE_POST_KEEP_BACK, &tmpa[0], &psize);
- seq_printf(seq, "post_keep_back: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
- seq_printf(seq, "\ttype[%d],index[%d]\n", p->type, p->index);
- }
- seq_printf(seq, "%s\n", splt);
- PR_INF("%s:11\n", __func__);/*debug*/
-
- /********************************/
-
- if (di_pre_stru_p->di_inp_buf) {
- seq_printf(seq, "di_inp_buf:index %d, 0x%p, type %d\n",
- di_pre_stru_p->di_inp_buf->index,
- &di_pre_stru_p->di_inp_buf,
- di_pre_stru_p->di_inp_buf->type);
- } else {
- seq_puts(seq, "di_inp_buf: NULL\n");
- }
- if (di_pre_stru_p->di_wr_buf) {
- seq_printf(seq, "di_wr_buf:index %d, 0x%p, type %d\n",
- di_pre_stru_p->di_wr_buf->index,
- &di_pre_stru_p->di_wr_buf,
- di_pre_stru_p->di_wr_buf->type);
- } else {
- seq_puts(seq, "di_wr_buf: NULL\n");
- }
- PR_INF("%s:12\n", __func__);/*debug*/
- dump_di_pre_stru_seq(seq, v, channel);
- dump_di_post_stru_seq(seq, v, channel);
- seq_puts(seq, "vframe_in[]:");
-
- for (i = 0; i < MAX_IN_BUF_NUM; i++) {
- seq_printf(seq, "0x%p\n", *vframe_in);
- vframe_in++;
- }
- PR_INF("%s:13\n", __func__);/*debug*/
-
- seq_puts(seq, "\n");
-
- if (pch->interf.reg)
- seq_printf(seq, "vf_peek()=>0x%p, video_peek_cnt = %d\n",
- pch->interf.opsi.peek(pch),/*pw_vf_peek(channel),*/
- div3_sum_get(channel, eDI_SUM_O_PEEK_CNT));
-// seq_printf(seq, "pause = 0x%x\n", pch->pause);
- seq_printf(seq, "reg_unreg_timerout = %lu\n",
- reg_unreg_timeout_cnt);
- seq_printf(seq, "%-15s=%s\n", "top_state",
- dipv3_chst_get_name_curr(channel));
- seq_printf(seq, "%-15s=%d\n", "trig_unreg",
- get_flag_trig_unreg(channel));
- seq_printf(seq, "%-15s=%s\n", "cma_state",
- div3_cma_dbg_get_st_name(channel));
- seq_printf(seq, "%-15s=%d\n", "bypass_compelet",
- isv3_bypss2_complete(channel));
- seq_printf(seq, "%-15s=%d\n", "reg_flag",
- get_reg_flag(channel));
- seq_printf(seq, "%-15s=%s\n", "pre_state",
- dprev3_state4_name_get(pre->pre_st));
- seq_printf(seq, "%-15s=%s\n", "post_state",
- dpstv3_state_name_get(post->state));
-
- seq_printf(seq, "%-15s=%d\n", "pre_get_sum",
- get_sum_g(channel));
- seq_printf(seq, "%-15s=%d\n", "pre_put_sum",
- get_sum_p(channel));
- seq_printf(seq, "%-15s=%d\n", "pst_done_sum",
- pch->sum_pst_done);
- PR_INF("%s:14\n", __func__);/*debug*/
- dump_state_flag = 0;
- return 0;
-}
-
-static int seq_file_afbc_show(struct seq_file *seq, void *v)
-{
- seq_puts(seq, "******dump VD2 AFBC********\n");
- seq_printf(seq, "VD2_AFBC_ENABLE 0x%x.\n",
- dimv3_RDMA_RD(VD2_AFBC_ENABLE));
- seq_printf(seq, "VD2_AFBC_STAT 0x%x.\n", dimv3_RDMA_RD(VD2_AFBC_STAT));
- seq_printf(seq, "VD2_AFBCD1_MISC_CTRL 0x%x.\n",
- dimv3_RDMA_RD(VD2_AFBCD1_MISC_CTRL));
-
- seq_puts(seq, "******dump VD1 AFBC********\n");
- seq_printf(seq, "AFBC_ENABLE 0x%x.\n", dimv3_RDMA_RD(AFBC_ENABLE));
- seq_printf(seq, "AFBC_STAT 0x%x.\n", dimv3_RDMA_RD(AFBC_STAT));
- seq_printf(seq, "VD1_AFBCD0_MISC_CTRL 0x%x.\n",
- dimv3_RDMA_RD(VD1_AFBCD0_MISC_CTRL));
- seq_puts(seq, "***************************\n");
-
- seq_printf(seq, "VIUMISC_CTRL0 0x%x.\n", dimv3_RDMA_RD(VIU_MISC_CTRL0));
- seq_printf(seq, "VIUMISC_CTRL1 0x%x.\n", dimv3_RDMA_RD(VIU_MISC_CTRL1));
- seq_printf(seq, "VIUBMISC_CTRL0 0x%x.\n",
- dimv3_RDMA_RD(VIUB_MISC_CTRL0));
-
- seq_printf(seq, "DI_PRE_CTRL bit8=%d,bit 28 =%d.\n",
- dimv3_RDMA_RD_BITS(DI_PRE_CTRL, 8, 1),
- dimv3_RDMA_RD_BITS(DI_PRE_CTRL, 28, 1));
-
- return 0;
-}
-
-/*2018-08-17 add debugfs*/
-#define DEFINE_SHOW_DI(__name) \
-static int __name ## _open(struct inode *inode, struct file *file) \
-{ \
- return single_open(file, __name ## _show, inode->i_private); \
-} \
- \
-static const struct file_operations __name ## _fops = { \
- .owner = THIS_MODULE, \
- .open = __name ## _open, \
- .read = seq_read, \
- .llseek = seq_lseek, \
- .release = single_release, \
-}
-
-DEFINE_SHOW_DI(seq_file_module_para);
-/*DEFINE_SHOW_DI(seq_file_di_state);*/
-DEFINE_SHOW_DI(seq_file_dump_di_reg);
-/*DEFINE_SHOW_DI(seq_file_dump_mif_size_state);*/
-DEFINE_SHOW_DI(seq_file_afbc);
-
-struct di_debugfs_files_t {
- const char *name;
- const umode_t mode;
- const struct file_operations *fops;
-};
-
-static struct di_debugfs_files_t di_debugfs_files[] = {
-/* {"state", S_IFREG | 0644, &seq_file_di_state_fops},*/
- {"dumpreg", S_IFREG | 0644, &seq_file_dump_di_reg_fops},
-/* {"dumpmif", S_IFREG | 0644, &seq_file_dump_mif_size_state_fops},*/
- {"dumpafbc", S_IFREG | 0644, &seq_file_afbc_fops},
- {"dumppara", S_IFREG | 0644, &seq_file_module_para_fops}
-};
-
-void dimv3_debugfs_init(void)
-{
- int i;
- struct dentry *ent;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (de_devp->dbg_root)
- return;
-
- de_devp->dbg_root = debugfs_create_dir("di", NULL);
- if (!de_devp->dbg_root) {
- PR_ERR("can't create debugfs dir di\n");
- return;
- }
-
- for (i = 0; i < ARRAY_SIZE(di_debugfs_files); i++) {
- ent = debugfs_create_file(di_debugfs_files[i].name,
- di_debugfs_files[i].mode,
- de_devp->dbg_root, NULL,
- di_debugfs_files[i].fops);
- if (!ent)
- PR_ERR("debugfs create failed\n");
- }
-}
-
-void dimv3_debugfs_exit(void)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
- if (de_devp && de_devp->dbg_root)
- debugfs_remove_recursive(de_devp->dbg_root);
-}
-
-/*-----------------------*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace_dbg.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _DI_DBG_H
-#define _DI_DBG_H
-#include "deinterlace.h"
-
-void dimv3_parse_cmd_params(char *buf_orig, char **parm);
-void dimv3_dump_pre_stru(struct di_pre_stru_s *ppre);
-void dimv3_dump_post_stru(struct di_post_stru_s *di_post_stru_p);
-void dimv3_dump_di_buf(struct di_buf_s *di_buf);
-void dimv3_dump_pool(struct queue_s *q);
-void dimv3_dump_vframe(vframe_t *vf);
-void dimv3_print_di_buf(struct di_buf_s *di_buf, int format);
-void dimv3_dump_pre_mif_state(void);
-void dimv3_dump_post_mif_reg(void);
-void dimv3_dump_buf_addr(struct di_buf_s *di_buf, unsigned int num);
-void dimv3_dump_mif_size_state(struct di_pre_stru_s *pre,
- struct di_post_stru_s *post);
-void debugv3_device_files_add(struct device *dev);
-void debugv3_device_files_del(struct device *dev);
-void dimv3_debugfs_init(void);
-void dimv3_debugfs_exit(void);
-int dimv3_state_show(struct seq_file *seq, void *v,
- unsigned int channel);
-int dimv3_dump_mif_size_state_show(struct seq_file *seq, void *v,
- unsigned int channel);
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace_hw.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/atomic.h>
-
-#include <linux/amlogic/media/vpu/vpu.h>
-#include <linux/amlogic/cpu_version.h>
-#include <linux/amlogic/media/canvas/canvas.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/video_sink/video.h>
-#include "deinterlace.h"
-#include "di_data_l.h"
-
-#include "deinterlace_hw.h"
-#include "register.h"
-#include "register_nr4.h"
-#ifdef DET3D
-#include "detect3d.h"
-#endif
-#include "di_api.h"
-#include "di_reg_tab.h"
-#include "di_prc.h"
-
-#include <linux/seq_file.h>
-
-static unsigned int ctrl_regs[SKIP_CTRE_NUM];
-
-static void set_di_inp_fmt_more(
- unsigned int repeat_l0_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- );
-
-static void set_di_inp_mif(struct DI_MIF_s *mif, int urgent, int hold_line);
-
-static void set_di_mem_fmt_more(
- int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- );
-
-static void set_di_mem_mif(struct DI_MIF_s *mif, int urgent, int hold_line);
-
-static void set_di_if0_fmt_more(
- int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- );
-
-static void set_di_if1_fmt_more(
- int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- );
-
-static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
- int hold_line, int vskip_cnt);
-
-static void set_di_chan2_mif(struct DI_MIF_s *mif, int urgent, int hold_line);
-
-static void set_di_if0_mif(struct DI_MIF_s *mif, int urgent,
- int hold_line, int vskip_cnt, int wr_en);
-
-static void set_di_if0_mif_g12(struct DI_MIF_s *mif, int urgent,
- int hold_line, int vskip_cnt, int wr_en);
-
-static void ma_di_init(void)
-{
- /* 420->422 chrome difference is large motion is large,flick */
- dimv3_DI_Wr(DI_MTN_1_CTRL4, 0x01800880);
- dimv3_DI_Wr(DI_MTN_1_CTRL7, 0x0a800480);
- /* mtn setting */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
- dimv3_DI_Wr_reg_bits(DI_MTN_CTRL, 1, 0, 1);
- dimv3_DI_Wr(DI_MTN_1_CTRL1, 0x202015);
- } else {
- dimv3_DI_Wr(DI_MTN_1_CTRL1, 0xa0202015);
- }
- /* invert chan2 field num */
- dimv3_DI_Wr(DI_MTN_CTRL1, (1 << 17) | 2);
- /* no invert chan2 field num from gxlx*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- dimv3_DI_Wr(DI_MTN_CTRL1, 2);
-}
-
-static void ei_hw_init(void)
-{
- /* ei setting */
- dimv3_DI_Wr(DI_EI_CTRL0, 0x00ff0100);
- dimv3_DI_Wr(DI_EI_CTRL1, 0x5a0a0f2d);
- dimv3_DI_Wr(DI_EI_CTRL2, 0x050a0a5d);
- dimv3_DI_Wr(DI_EI_CTRL3, 0x80000013);
- if (is_meson_txlx_cpu()) {
- dimv3_DI_Wr_reg_bits(DI_EI_DRT_CTRL, 1, 30, 1);
- dimv3_DI_Wr_reg_bits(DI_EI_DRT_CTRL, 1, 31, 1);
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) {
- dimv3_DI_Wr_reg_bits(DI_EI_DRT_CTRL_GXLX, 1, 30, 1);
- dimv3_DI_Wr_reg_bits(DI_EI_DRT_CTRL_GXLX, 1, 31, 1);
- }
-}
-
-static void mc_di_param_init(void)
-{
- dimv3_DI_Wr(MCDI_CHK_EDGE_GAIN_OFFST, 0x4f6124);
- dimv3_DI_Wr(MCDI_LMV_RT, 0x7455);
- dimv3_DI_Wr(MCDI_LMV_GAINTHD, 0x6014d409);
- dimv3_DI_Wr(MCDI_REL_DET_LPF_MSK_22_30, 0x0a010001);
- dimv3_DI_Wr(MCDI_REL_DET_LPF_MSK_31_34, 0x01010101);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_DI_Wr_reg_bits(MCDI_REF_MV_NUM, 2, 0, 2);
-}
-
-void dimhv3_init_field_mode(unsigned short height)
-{
- dimv3_DI_Wr(DIPD_COMB_CTRL0, 0x02400210);
- dimv3_DI_Wr(DIPD_COMB_CTRL1, 0x88080808);
- dimv3_DI_Wr(DIPD_COMB_CTRL2, 0x41041008);
- dimv3_DI_Wr(DIPD_COMB_CTRL3, 0x00008053);
- dimv3_DI_Wr(DIPD_COMB_CTRL4, 0x20070002);
- if (height > 288)
- dimv3_DI_Wr(DIPD_COMB_CTRL5, 0x04041020);
- else
- dimv3_DI_Wr(DIPD_COMB_CTRL5, 0x04040804);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- dimv3_DI_Wr(DIPD_COMB_CTRL6, 0x00107064);
- dimv3_DI_Wr_reg_bits(DI_MC_32LVL0, 16, 0, 8);
- dimv3_DI_Wr_reg_bits(DI_MC_22LVL0, 256, 0, 16);
-}
-
-static void mc_pd22_check_irq(void)
-{
- int cls_2_stl_thd = 1, cls_2_stl = 0;
- int is_zmv = 0, no_gmv = 0;
- int i, last_gmv, last_22_flg;
- int cur_gmv, cur_22_flg;
- unsigned int reg_val = 0;
-
- if (!dimp_get(eDI_MP_pd22_flg_calc_en))
- return;
-
- is_zmv = dimv3_RDMA_RD_BITS(MCDI_RO_GMV_LOCK_FLG, 1, 1);
- last_gmv = dimv3_RDMA_RD_BITS(MCDI_FIELD_MV, 0, 6);
- last_gmv = last_gmv > 32 ? (32 - last_gmv) : last_gmv;
- cur_gmv = dimv3_RDMA_RD_BITS(MCDI_RO_GMV_LOCK_FLG, 2, 6);
- cur_gmv = cur_gmv > 32 ? (32 - cur_gmv) : cur_gmv;
-
- cls_2_stl = abs(cur_gmv) <= cls_2_stl_thd;
- no_gmv = (abs(cur_gmv) == 32 && (abs(last_gmv) <= cls_2_stl_thd));
- for (i = 0; i < 3; i++) {
- last_22_flg =
- dimv3_RDMA_RD_BITS(MCDI_PD_22_CHK_FLG_CNT, (24 + i), 1);
- cur_22_flg = dimv3_RDMA_RD_BITS(MCDI_RO_PD_22_FLG, (24 + i), 1);
- if ((is_zmv == 1 || cls_2_stl == 1 || no_gmv == 1) &&
- last_22_flg == 1 && cur_22_flg == 0) {
- dimv3_RDMA_WR_BITS(MCDI_PD_22_CHK_FLG_CNT,
- last_22_flg, (24 + i), 1);
- reg_val = dimv3_RDMA_RD_BITS(MCDI_PD22_CHK_THD_RT,
- 0, 5) - 1;
- dimv3_RDMA_WR_BITS(MCDI_PD_22_CHK_FLG_CNT,
- reg_val, i * 8, 8);
- } else {
- dimv3_RDMA_WR_BITS(MCDI_PD_22_CHK_FLG_CNT,
- cur_22_flg, (24 + i), 1);
- reg_val =
- dimv3_RDMA_RD_BITS(MCDI_RO_PD_22_FLG, i * 8, 8);
- dimv3_RDMA_WR_BITS(MCDI_PD_22_CHK_FLG_CNT,
- reg_val, i * 8, 8);
- }
- }
-}
-
-void dimhv3_mc_pre_mv_irq(void)
-{
- unsigned int val1;
-
- if (dimp_get(eDI_MP_pd22_flg_calc_en) && is_meson_gxlx_cpu()) {
- mc_pd22_check_irq();
- } else {
- val1 = dimv3_RDMA_RD(MCDI_RO_PD_22_FLG);
- dimv3_RDMA_WR(MCDI_PD_22_CHK_FLG_CNT, val1);
- }
-
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_HIGH_VERT_FRQ_FLG, 0, 1);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_HVF_PRDX_CNT, val1, 0, 1);
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_HIGH_VERT_FRQ_FLG, 1, 2);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_HVF_PRDX_CNT, val1, 2, 2);
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_HIGH_VERT_FRQ_FLG, 8, 8);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_HVF_PRDX_CNT, val1, 8, 8);
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_MOTION_PARADOX_FLG, 0, 16);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_HVF_PRDX_CNT, val1, 16, 16);
-
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_RPT_MV, 0, 6);
- if (val1 == 32) {
- val1 = 0;
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 0, 15, 1);
- } else {
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 1, 15, 1);
- }
-
- dimv3_RDMA_WR_BITS(MCDI_FIELD_MV, val1, 8, 6);
-
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_GMV_LOCK_FLG, 0, 1);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_MV, val1, 14, 1);
-
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_GMV_LOCK_FLG, 8, 8);
- dimv3_RDMA_WR_BITS(MCDI_FIELD_MV, val1, 16, 8);
-
- val1 = dimv3_RDMA_RD_BITS(MCDI_RO_GMV_LOCK_FLG, 2, 6);
- if (val1 == 32) {
- val1 = 0;
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 0, 14, 1);
- } else {
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 1, 14, 1);
- }
- dimv3_RDMA_WR_BITS(MCDI_FIELD_MV, val1, 0, 6);
-
- val1 = dimv3_RDMA_RD(MCDI_FIELD_LUMA_AVG_SUM_1);
- dimv3_RDMA_WR(MCDI_FIELD_LUMA_AVG_SUM_0, val1);
-
- val1 = dimv3_RDMA_RD(MCDI_RO_FLD_LUMA_AVG_SUM);
- dimv3_RDMA_WR(MCDI_FIELD_LUMA_AVG_SUM_1, val1);
-}
-
-static void lmvs_init(struct mcinfo_lmv_s *lmvs, unsigned short lmv)
-{
- lmvs->lock_flag = (lmv >> 14) & 3;
- lmvs->lmv = (lmv >> 8) & 63;
- lmvs->lmv = lmvs->lmv > 32 ? (32 - lmvs->lmv) : lmvs->lmv;
- lmvs->lock_cnt = (lmv & 255);
-}
-
-void dimhv3_calc_lmv_init(void)
-{
- if (dimp_get(eDI_MP_lmv_lock_win_en)) {
- dimv3_RDMA_WR_BITS(MCDI_REL_DET_LMV_DIF_CHK, 3, 12, 2);
- dimv3_RDMA_WR_BITS(MCDI_LMVLCKSTEXT_1, 3, 30, 2);
- } else {
- dimv3_RDMA_WR_BITS(MCDI_REL_DET_LMV_DIF_CHK, 0, 12, 2);
- dimv3_RDMA_WR_BITS(MCDI_LMVLCKSTEXT_1, 0, 30, 2);
- }
-}
-
-static struct mcinfo_lmv_s lines_mv[540];
-
-void dimhv3_calc_lmv_base_mcinfo(unsigned int vf_height,
- unsigned short *mcinfo_adr_v,
- unsigned int mcinfo_size)
-{
- unsigned short i, top_str, bot_str, top_end, bot_end, j = 0;
- unsigned short *mcinfo_vadr = NULL, lck_num;
- unsigned short flg_m1 = 0, flg_i = 0, nLmvLckSt = 0;
- unsigned short lmv_lckstext[3] = {0, 0, 0}, nLmvLckEd;
- unsigned short lmv_lckedext[3] = {0, 0, 0}, nLmvLckNum;
- #if 0
- bool bflg_vmap = false;
- u8 *tmp;
- #endif
- /*mcinfo_vadr = (unsigned short *)phys_to_virt(mcinfo_adr);*/
-
- if (!dimp_get(eDI_MP_lmv_lock_win_en))
- return;
-
- #if 0
- tmp = dimv3_vmap(mcinfo_adr, mcinfo_size, &bflg_vmap);
- if (!tmp) {
- dimv3_print("err:dimv3_vmap failed\n");
- return;
- }
- mcinfo_vadr = (unsigned short *)tmp;
- #else
- mcinfo_vadr = mcinfo_adr_v;
- #endif
-
- for (i = 0; i < (vf_height >> 1); i++) {
- lmvs_init(&lines_mv[i], *(mcinfo_vadr + i));
- j = i + (vf_height >> 1);
- lmvs_init(&lines_mv[j], *(mcinfo_vadr + i + 272));
- if (dimp_get(eDI_MP_pr_mcinfo_cnt) && j < (vf_height - 10) &&
- j > (vf_height - dimp_get(eDI_MP_offset_lmv))) {
- pr_info("MCINFO[%u]=0x%x\t", j,
- *(mcinfo_vadr + i + 272));
- if (i % 16 == 0)
- pr_info("\n");
- }
- }
- #if 0
- if (bflg_vmap)
- dimv3_unmap_phyaddr(tmp);
- #endif
-
- /*pr_mcinfo_cnt ? pr_mcinfo_cnt-- : (pr_mcinfo_cnt = 0);*/
- dimp_get(eDI_MP_pr_mcinfo_cnt) ?
- dimp_dec(eDI_MP_pr_mcinfo_cnt) :
- dimp_set(eDI_MP_pr_mcinfo_cnt, 0);
-
- top_str = 0;
- top_end = dimp_get(eDI_MP_offset_lmv);
- i = top_str;
- j = 0;
- lck_num = Rd_reg_bits(MCDI_LMVLCKSTEXT_1, 16, 12);
-
- while (i < top_end) {
- flg_m1 = (i == top_str) ? 0 :
- (lines_mv[i - 1].lock_flag > 0);
- flg_i = (i == top_end - 1) ? 0 :
- lines_mv[i].lock_flag > 0;
- if (!flg_m1 && flg_i) {
- #if 0
- nLmvLckSt = (j == 0) ? i : ((i < (lmv_lckedext[j - 1] +
- dimp_get(eDI_MP_lmv_dist))) ?
- lmv_lckstext[j - 1] : i);
- #else
- if (j == 0) {
- nLmvLckSt = i;
- } else {
- if (i < (lmv_lckedext[j - 1] +
- dimp_get(eDI_MP_lmv_dist)))
- nLmvLckSt = lmv_lckstext[j - 1];
- else
- nLmvLckSt = i;
- }
- #endif
- j = (nLmvLckSt != i) ? (j - 1) : j;
- } else if (flg_m1 && !flg_i) {
- nLmvLckEd = i;
- nLmvLckNum = (nLmvLckEd - nLmvLckSt + 1);
- if (nLmvLckNum >= lck_num) {
- lmv_lckstext[j] = nLmvLckSt;
- lmv_lckedext[j] = nLmvLckEd;
- j++;
- }
- }
- i++;
- if (j > 2)
- break;
- }
-
- bot_str = vf_height - dimp_get(eDI_MP_offset_lmv) - 1;
- bot_end = vf_height;
- i = bot_str;
- while (i < bot_end && j < 3) {
- flg_m1 = (i == bot_str) ? 0 :
- (lines_mv[i - 1].lock_flag > 0);
- flg_i = (i == bot_end - 1) ? 0 :
- lines_mv[i].lock_flag > 0;
- if (!flg_m1 && flg_i) {
- nLmvLckSt = (j == 0) ? i : ((i < (lmv_lckedext[j - 1] +
- dimp_get(eDI_MP_lmv_dist))) ?
- lmv_lckstext[j - 1] : i);
- j = (nLmvLckSt != i) ? (j - 1) : j;
- } else if (flg_m1 && !flg_i) {
- nLmvLckEd = i;
- nLmvLckNum = (nLmvLckEd - nLmvLckSt + 1);
- if (nLmvLckNum >= lck_num) {
- lmv_lckstext[j] = nLmvLckSt;
- lmv_lckedext[j] = nLmvLckEd;
- j++;
- }
- }
- i++;
- if (j > 2)
- break;
- }
-
- Wr(MCDI_LMVLCKSTEXT_0, lmv_lckstext[1] << 16 | lmv_lckstext[0]);
- Wr_reg_bits(MCDI_LMVLCKSTEXT_1, lmv_lckstext[2], 0, 12);
- Wr(MCDI_LMVLCKEDEXT_0, lmv_lckedext[1] << 16 | lmv_lckedext[0]);
- Wr(MCDI_LMVLCKEDEXT_1, lmv_lckedext[2]);
-}
-
-/*
- * config pre hold ratio & mif request block len
- * pass_ratio = (pass_cnt + 1)/(pass_cnt + 1 + hold_cnt + 1)
- */
-static void pre_hold_block_mode_config(void)
-{
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_DI_Wr(DI_PRE_HOLD, 0);
- /* go field after 2 lines */
- #ifdef OLD_PRE_GL
- dimv3_DI_Wr(DI_PRE_GL_CTRL,
- (0x80000000 | dimp_get(eDI_MP_line_num_pre_frst)));
- #else
- hprev3_gl_sw(false);
- #endif
- } else if (is_meson_txlx_cpu()) {
- /* setup pre process ratio to 66.6%*/
- dimv3_DI_Wr(DI_PRE_HOLD, (1 << 31) | (1 << 16) | 3);
- /* block len, after block insert null req to balance reqs */
- dimv3_DI_Wr_reg_bits(DI_INP_GEN_REG3, 0, 4, 3);
- dimv3_DI_Wr_reg_bits(DI_MEM_GEN_REG3, 0, 4, 3);
- dimv3_DI_Wr_reg_bits(DI_CHAN2_GEN_REG3, 0, 4, 3);
- dimv3_DI_Wr_reg_bits(DI_IF1_GEN_REG3, 0, 4, 3);
- dimv3_DI_Wr_reg_bits(DI_IF2_GEN_REG3, 0, 4, 3);
- dimv3_DI_Wr_reg_bits(VD1_IF0_GEN_REG3, 0, 4, 3);
- } else {
- dimv3_DI_Wr(DI_PRE_HOLD, (1 << 31) | (31 << 16) | 31);
- }
-}
-
-/*
- * ctrl or size related regs configured
- * in software base on real size and condition
- */
-static void set_skip_ctrl_size_regs(void)
-{
- ctrl_regs[0] = DI_CLKG_CTRL;
- ctrl_regs[1] = DI_MTN_1_CTRL1;
- ctrl_regs[2] = MCDI_MOTINEN;
- ctrl_regs[3] = MCDI_CTRL_MODE;
- ctrl_regs[4] = MCDI_MC_CRTL;
- ctrl_regs[5] = MCDI_PD_22_CHK_WND0_X;
- ctrl_regs[6] = MCDI_PD_22_CHK_WND0_Y;
- ctrl_regs[7] = MCDI_PD_22_CHK_WND1_X;
- ctrl_regs[8] = MCDI_PD_22_CHK_WND1_Y;
- ctrl_regs[9] = NR4_MCNR_LUMA_STAT_LIMTX;
- ctrl_regs[10] = NR4_MCNR_LUMA_STAT_LIMTY;
- ctrl_regs[11] = NR4_NM_X_CFG;
- ctrl_regs[12] = NR4_NM_Y_CFG;
-}
-
-void dimv3_hw_init_reg(void)
-{
- unsigned short fifo_size_post = 0x120;/*feijun 08-02*/
-
- if (is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_sm1_cpu()) {
- dimv3_DI_Wr(DI_IF1_LUMA_FIFO_SIZE, fifo_size_post);
- /* 17f2 is DI_IF1_luma_fifo_size */
- dimv3_DI_Wr(DI_IF2_LUMA_FIFO_SIZE, fifo_size_post);
- dimv3_DI_Wr(DI_IF0_LUMA_FIFO_SIZE, fifo_size_post);
- }
-
- //PR_INF("%s, 0x%x\n", __func__, dim_RDMA_RD(DI_IF0_LUMA_FIFO_SIZE));
-}
-
-void dimhv3_hw_init(bool pd_enable, bool mc_enable)
-{
- unsigned short fifo_size_vpp = 0xc0;
- unsigned short fifo_size_di = 0xc0;
-
- diextv3_clk_b_sw(true);
- if (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_sm1_cpu() ||
- is_meson_tm2_cpu())
- dimv3_top_gate_control(true, true);
- else if (is_meson_gxl_cpu() ||
- is_meson_gxm_cpu() ||
- is_meson_gxlx_cpu())
- dimv3_DI_Wr(DI_CLKG_CTRL, 0xffff0001);
- else
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x1); /* di no clock gate */
-
- if (is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_gxlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_sm1_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu()) {
- /* vpp fifo max size on txl :128*3=384[0x180] */
- /* di fifo max size on txl :96*3=288[0x120] */
- fifo_size_vpp = 0x180;
- fifo_size_di = 0x120;
- }
-
- /*enable lock win, suggestion from vlsi zheng.bao*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimp_set(eDI_MP_lmv_lock_win_en, 0);/*lmv_lock_win_en = 0;*/
-
- dimv3_DI_Wr(VD1_IF0_LUMA_FIFO_SIZE, fifo_size_vpp);
- dimv3_DI_Wr(VD2_IF0_LUMA_FIFO_SIZE, fifo_size_vpp);
- /* 1a83 is vd2_if0_luma_fifo_size */
- dimv3_DI_Wr(DI_INP_LUMA_FIFO_SIZE, fifo_size_di);
- /* 17d8 is DI_INP_luma_fifo_size */
- dimv3_DI_Wr(DI_MEM_LUMA_FIFO_SIZE, fifo_size_di);
- /* 17e5 is DI_MEM_luma_fifo_size */
- dimv3_DI_Wr(DI_IF1_LUMA_FIFO_SIZE, fifo_size_di);
- /* 17f2 is DI_IF1_luma_fifo_size */
- dimv3_DI_Wr(DI_IF2_LUMA_FIFO_SIZE, fifo_size_di);
- /* 201a is if2 fifo size */
- dimv3_DI_Wr(DI_CHAN2_LUMA_FIFO_SIZE, fifo_size_di);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_DI_Wr(DI_IF0_LUMA_FIFO_SIZE, fifo_size_di);
- dimv3_DI_Wr(DI_ARB_CTRL, 0);
- } else {
- /* enable di all arb */
- dimv3_DI_Wr_reg_bits(DI_ARB_CTRL, 0xf0f, 0, 16);
- }
- /* 17b3 is DI_chan2_luma_fifo_size */
- if (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_sm1_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu()) {
- dimv3_pre_gate_control(true, true);
- dimv3_post_gate_control(true);
- }
-
- pre_hold_block_mode_config();
- set_skip_ctrl_size_regs();
- ma_di_init();
- ei_hw_init();
- get_ops_nr()->nr_hw_init();
- if (pd_enable)
- dimhv3_init_field_mode(288);
-
- if (mc_enable)
- mc_di_param_init();
- if (is_meson_txlx_cpu() ||
- is_meson_txhd_cpu() ||
- is_meson_g12a_cpu() ||
- is_meson_sm1_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_tl1_cpu() ||
- is_meson_tm2_cpu()) {
- dimv3_pre_gate_control(false, true);
- dimv3_post_gate_control(false);
- dimv3_top_gate_control(false, false);
- } else if (is_meson_txl_cpu() || is_meson_gxlx_cpu()) {
- /* di clock div enable for pq load */
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x80000000);
- } else {
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x2); /* di clock gate all */
- }
-
- diextv3_clk_b_sw(false);
-
- /*move from prob*/
- dimv3_DI_Wr_reg_bits(MCDI_MC_CRTL, 0, 0, 1);
-}
-
-void dimhv3_hw_uninit(void)
-{
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
- get_ops_nr()->nr_gate_control(false);
-}
-
-/*
- * mtn wr mif, contprd mif, contp2rd mif,
- * contwr mif config
- */
-static void set_ma_pre_mif(struct DI_SIM_MIF_s *mtnwr_mif,
- struct DI_SIM_MIF_s *contprd_mif,
- struct DI_SIM_MIF_s *contp2rd_mif,
- struct DI_SIM_MIF_s *contwr_mif,
- unsigned short urgent)
-{
- /* current field mtn canvas index. */
- dimv3_RDMA_WR(DI_MTNWR_X,
- (mtnwr_mif->start_x << 16) |
- (mtnwr_mif->end_x));
- dimv3_RDMA_WR(DI_MTNWR_Y,
- (mtnwr_mif->start_y << 16) |
- (mtnwr_mif->end_y));
- dimv3_RDMA_WR(DI_MTNWR_CTRL,
- mtnwr_mif->canvas_num |
- (urgent << 8)); /* urgent. */
-
- dimv3_RDMA_WR(DI_CONTPRD_X,
- (contprd_mif->start_x << 16) |
- (contprd_mif->end_x));
- dimv3_RDMA_WR(DI_CONTPRD_Y,
- (contprd_mif->start_y << 16) |
- (contprd_mif->end_y));
- dimv3_RDMA_WR(DI_CONTP2RD_X,
- (contp2rd_mif->start_x << 16) |
- (contp2rd_mif->end_x));
- dimv3_RDMA_WR(DI_CONTP2RD_Y,
- (contp2rd_mif->start_y << 16) |
- (contp2rd_mif->end_y));
- dimv3_RDMA_WR(DI_CONTRD_CTRL,
- (contprd_mif->canvas_num << 8) |
- (urgent << 16) | /* urgent */
- contp2rd_mif->canvas_num);
-
- dimv3_RDMA_WR(DI_CONTWR_X,
- (contwr_mif->start_x << 16) |
- (contwr_mif->end_x));
- dimv3_RDMA_WR(DI_CONTWR_Y,
- (contwr_mif->start_y << 16) |
- (contwr_mif->end_y));
- dimv3_RDMA_WR(DI_CONTWR_CTRL,
- contwr_mif->canvas_num |
- (urgent << 8));/* urgent. */
-}
-
-static void set_ma_pre_mif_g12(struct DI_SIM_MIF_s *mtnwr_mif,
- struct DI_SIM_MIF_s *contprd_mif,
- struct DI_SIM_MIF_s *contp2rd_mif,
- struct DI_SIM_MIF_s *contwr_mif,
- unsigned short urgent)
-{
- dimv3_RDMA_WR_BITS(CONTRD_SCOPE_X, contprd_mif->start_x, 0, 13);
- dimv3_RDMA_WR_BITS(CONTRD_SCOPE_X, contprd_mif->end_x, 16, 13);
- dimv3_RDMA_WR_BITS(CONTRD_SCOPE_Y, contprd_mif->start_y, 0, 13);
- dimv3_RDMA_WR_BITS(CONTRD_SCOPE_Y, contprd_mif->end_y, 16, 13);
- dimv3_RDMA_WR_BITS(CONTRD_CTRL1, contprd_mif->canvas_num, 16, 8);
- dimv3_RDMA_WR_BITS(CONTRD_CTRL1, 2, 8, 2);
- dimv3_RDMA_WR_BITS(CONTRD_CTRL1, 0, 0, 3);
-
- dimv3_RDMA_WR_BITS(CONT2RD_SCOPE_X, contp2rd_mif->start_x, 0, 13);
- dimv3_RDMA_WR_BITS(CONT2RD_SCOPE_X, contp2rd_mif->end_x, 16, 13);
- dimv3_RDMA_WR_BITS(CONT2RD_SCOPE_Y, contp2rd_mif->start_y, 0, 13);
- dimv3_RDMA_WR_BITS(CONT2RD_SCOPE_Y, contp2rd_mif->end_y, 16, 13);
- dimv3_RDMA_WR_BITS(CONT2RD_CTRL1, contp2rd_mif->canvas_num, 16, 8);
- dimv3_RDMA_WR_BITS(CONT2RD_CTRL1, 2, 8, 2);
- dimv3_RDMA_WR_BITS(CONT2RD_CTRL1, 0, 0, 3);
-
- /* current field mtn canvas index. */
- dimv3_RDMA_WR_BITS(MTNWR_X, mtnwr_mif->start_x, 16, 13);
- dimv3_RDMA_WR_BITS(MTNWR_X, mtnwr_mif->end_x, 0, 13);
- dimv3_RDMA_WR_BITS(MTNWR_X, 2, 30, 2);
- dimv3_RDMA_WR_BITS(MTNWR_Y, mtnwr_mif->start_y, 16, 13);
- dimv3_RDMA_WR_BITS(MTNWR_Y, mtnwr_mif->end_y, 0, 13);
- dimv3_RDMA_WR_BITS(MTNWR_CTRL, mtnwr_mif->canvas_num, 0, 8);
- dimv3_RDMA_WR_BITS(MTNWR_CAN_SIZE,
- (mtnwr_mif->end_y - mtnwr_mif->start_y), 0, 13);
- dimv3_RDMA_WR_BITS(MTNWR_CAN_SIZE,
- (mtnwr_mif->end_x - mtnwr_mif->start_x), 16, 13);
-
- dimv3_RDMA_WR_BITS(CONTWR_X, contwr_mif->start_x, 16, 13);
- dimv3_RDMA_WR_BITS(CONTWR_X, contwr_mif->end_x, 0, 13);
- dimv3_RDMA_WR_BITS(CONTWR_X, 2, 30, 2);
- dimv3_RDMA_WR_BITS(CONTWR_Y, contwr_mif->start_y, 16, 13);
- dimv3_RDMA_WR_BITS(CONTWR_Y, contwr_mif->end_y, 0, 13);
- dimv3_RDMA_WR_BITS(CONTWR_CTRL, contwr_mif->canvas_num, 0, 8);
- dimv3_RDMA_WR_BITS(CONTWR_CAN_SIZE,
- (contwr_mif->end_y - contwr_mif->start_y), 0, 13);
- dimv3_RDMA_WR_BITS(CONTWR_CAN_SIZE,
- (contwr_mif->end_x - contwr_mif->start_x), 16, 13);
-}
-
-static void set_di_nrwr_mif(struct DI_SIM_MIF_s *nrwr_mif,
- unsigned short urgent)
-{
- dimv3_RDMA_WR_BITS(DI_NRWR_X, nrwr_mif->end_x, 0, 14);
- dimv3_RDMA_WR_BITS(DI_NRWR_X, nrwr_mif->start_x, 16, 14);
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->start_y, 16, 13);
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->end_y, 0, 13);
- /* wr ext en from gxtvbb */
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, 1, 15, 1);
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, 3, 30, 2);
-
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->bit_mode & 0x1, 14, 1);
-
- /*fix 1080i crash when di work on low speed*/
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) &&
- ((nrwr_mif->bit_mode & 0x3) == 0x3)) {
- dimv3_RDMA_WR(DI_NRWR_CTRL,
- nrwr_mif->canvas_num |
- (urgent << 16) |
- 3 << 22 |
- 1 << 24 |
- 2 << 26 | /*burst_lim 1->2 2->4*/
- 1 << 30); /* urgent bit 16 */
- } else {
- dimv3_RDMA_WR(DI_NRWR_CTRL,
- nrwr_mif->canvas_num |
- (urgent << 16) |
- 1 << 24 |
- 2 << 26 | /*burst_lim 1->2 2->4*/
- 1 << 30); /* urgent bit 16 */
- }
-}
-
-void dimhv3_interrupt_ctrl(unsigned char ma_en,
- unsigned char det3d_en, unsigned char nrds_en,
- unsigned char post_wr, unsigned char mc_en)
-{
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, ma_en ? 0 : 1, 17, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, ma_en ? 0 : 1, 20, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, mc_en ? 0 : 3, 22, 2);
- /* enable nr wr int */
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 0, 16, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, post_wr ? 0 : 1, 18, 1);
- /* mask me interrupt hit abnormal */
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 1, 21, 1);
- /* mask hist interrupt */
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 1, 19, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, det3d_en ? 0 : 1, 24, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, nrds_en ? 0 : 1, 25, 1);
- /* clean all pending interrupt bits */
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 0xffff, 0, 16);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 3, 30, 2);
- else
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, 0, 30, 2);
-}
-
-void dimhv3_int_ctr(unsigned int set_mod, unsigned char ma_en,
- unsigned char det3d_en, unsigned char nrds_en,
- unsigned char post_wr, unsigned char mc_en)
-{
- static unsigned char lst_ma, lst_det3d, lst_nrds, lst_pw, lst_mc;
-
- if (set_mod == 0) {
- /*int:*/
- lst_ma = 1;
- lst_det3d = 0;
- lst_nrds = 1;
- lst_pw = 1;
- lst_mc = 1;
- dimhv3_interrupt_ctrl(lst_ma,
- lst_det3d,
- lst_nrds,
- lst_pw,
- lst_mc);
- return;
- }
-
- if (ma_en != lst_ma) {
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, ma_en ? 0 : 1, 17, 1);
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, ma_en ? 0 : 1, 20, 1);
- lst_ma = ma_en;
- }
- if (mc_en != lst_mc) {
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, mc_en ? 0 : 3, 22, 2);
- lst_mc = mc_en;
- }
-
- if (post_wr != lst_pw) {
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, post_wr ? 0 : 1, 18, 1);
- lst_pw = post_wr;
- }
-
- if (det3d_en != lst_det3d) {
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, det3d_en ? 0 : 1, 24, 1);
- lst_det3d = det3d_en;
- }
-
- if (nrds_en != lst_nrds) {
- dimv3_RDMA_WR_BITS(DI_INTR_CTRL, nrds_en ? 0 : 1, 25, 1);
- lst_nrds = nrds_en;
- }
-}
-
-void dimhv3_enable_di_pre_aml(
- struct DI_MIF_s *di_inp_mif,
- struct DI_MIF_s *di_mem_mif,
- struct DI_MIF_s *di_chan2_mif,
- struct DI_SIM_MIF_s *di_nrwr_mif,
- struct DI_SIM_MIF_s *di_mtnwr_mif,
- struct DI_SIM_MIF_s *di_contp2rd_mif,
- struct DI_SIM_MIF_s *di_contprd_mif,
- struct DI_SIM_MIF_s *di_contwr_mif,
- unsigned char madi_en, unsigned char pre_field_num,
- unsigned char pre_vdin_link)
-{
- bool mem_bypass = false, chan2_disable = false;
- unsigned short nrwr_hsize = 0, nrwr_vsize = 0;
- unsigned short chan2_hsize = 0, chan2_vsize = 0;
- unsigned short mem_hsize = 0, mem_vsize = 0;
-
- set_di_inp_mif(di_inp_mif,
- dimp_get(eDI_MP_pre_urgent),
- dimp_get(eDI_MP_pre_hold_line));
- set_di_nrwr_mif(di_nrwr_mif,
- dimp_get(eDI_MP_pre_urgent));
- set_di_mem_mif(di_mem_mif,
- dimp_get(eDI_MP_pre_urgent),
- dimp_get(eDI_MP_pre_hold_line));
- set_di_chan2_mif(di_chan2_mif,
- dimp_get(eDI_MP_pre_urgent),
- dimp_get(eDI_MP_pre_hold_line));
-
- nrwr_hsize = di_nrwr_mif->end_x -
- di_nrwr_mif->start_x + 1;
- nrwr_vsize = di_nrwr_mif->end_y -
- di_nrwr_mif->start_y + 1;
- chan2_hsize = di_chan2_mif->luma_x_end0 -
- di_chan2_mif->luma_x_start0 + 1;
- chan2_vsize = di_chan2_mif->luma_y_end0 -
- di_chan2_mif->luma_y_start0 + 1;
- mem_hsize = di_mem_mif->luma_x_end0 -
- di_mem_mif->luma_x_start0 + 1;
- mem_vsize = di_mem_mif->luma_y_end0 -
- di_mem_mif->luma_y_start0 + 1;
- if ((chan2_hsize != nrwr_hsize) || (chan2_vsize != nrwr_vsize))
- chan2_disable = true;
- if ((mem_hsize != nrwr_hsize) || (mem_vsize != nrwr_vsize))
- mem_bypass = true;
- /*
- * enable&disable contwr txt
- */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B))
- dimv3_RDMA_WR_BITS(DI_MTN_CTRL, madi_en ? 5 : 0, 29, 3);
- else
- dimv3_RDMA_WR_BITS(DI_MTN_1_CTRL1, madi_en ? 5 : 0, 29, 3);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (madi_en) {
- set_ma_pre_mif_g12(di_mtnwr_mif,
- di_contprd_mif,
- di_contp2rd_mif,
- di_contwr_mif,
- dimp_get(eDI_MP_pre_urgent));
- } else {
- chan2_disable = true;
- }
- dimv3_RDMA_WR_BITS(DI_PRE_GL_THD,
- dimp_get(eDI_MP_pre_hold_line), 16, 6);
- if (dimp_get(eDI_MP_pre_ctrl))
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL,
- dimp_get(eDI_MP_pre_ctrl), 0, 29);
- else
- dimv3_RDMA_WR(DI_PRE_CTRL,
- 1 | /* nr wr en */
- (madi_en << 1) | /* mtn en */
- (madi_en << 2) | /* check3:2pulldown*/
- (madi_en << 3) | /* check2:2pulldown*/
- (1 << 4) |
- (madi_en << 5) | /*hist check enable*/
- /* hist check use chan2. */
- (madi_en << 6) |
- /*hist check use data before noise reduction.*/
- ((chan2_disable ? 0 : 1) << 8) |
- /* chan 2 enable for 2:2 pull down check.*/
- /* line buffer 2 enable */
- ((chan2_disable ? 0 : 1) << 9) |
- (0 << 10) | /* pre drop first. */
- (1 << 11) | /* nrds mif enable */
- (0 << 12) | /* pre viu link */
- (pre_vdin_link << 13) |
- /* pre go line link */
- (pre_vdin_link << 14) |
- (1 << 21) | /*invertNRfield num*/
- (1 << 22) | /* MTN after NR. */
- (0 << 25) | /* contrd en */
- ((mem_bypass ? 1 : 0) << 28) |
- pre_field_num << 29);
- } else {
- if (madi_en) {
- set_ma_pre_mif(di_mtnwr_mif,
- di_contprd_mif,
- di_contp2rd_mif,
- di_contwr_mif,
- dimp_get(eDI_MP_pre_urgent));
- }
- dimv3_RDMA_WR(DI_PRE_CTRL,
- 1 /* nr enable */
- | (madi_en << 1) /* mtn_en */
- | (madi_en << 2) /* check 3:2 pulldown */
- | (madi_en << 3) /* check 2:2 pulldown */
- | (1 << 4)
- | (madi_en << 5) /* hist check enable */
- | (1 << 6) /* hist check use chan2. */
- | (0 << 7)
- /* hist check use data before noise reduction. */
- | (madi_en << 8)
- /* chan 2 enable for 2:2 pull down check.*/
- | (madi_en << 9) /* line buffer 2 enable */
- | (0 << 10) /* pre drop first. */
- | (0 << 11) /* di pre repeat */
- | (0 << 12) /* pre viu link */
- | (pre_vdin_link << 13)
- | (pre_vdin_link << 14) /* pre go line link */
- | (dimp_get(eDI_MP_pre_hold_line) << 16)
- /* pre hold line number */
- | (1 << 22) /* MTN after NR. */
- | (madi_en << 25) /* contrd en */
- | (pre_field_num << 29) /* pre field number.*/
- );
- }
-}
-
-/*
- * after g12a, framereset will not reset simple
- * wr mif of pre such as mtn&cont&mv&mcinfo wr
- */
-static const unsigned int reg_AFBC[AFBC_DEC_NUB][AFBC_REG_INDEX_NUB] = {
- {
- AFBC_ENABLE,
- AFBC_MODE,
- AFBC_SIZE_IN,
- AFBC_DEC_DEF_COLOR,
- AFBC_CONV_CTRL,
- AFBC_LBUF_DEPTH,
- AFBC_HEAD_BADDR,
- AFBC_BODY_BADDR,
- AFBC_SIZE_OUT,
- AFBC_OUT_YSCOPE,
- AFBC_STAT,
- AFBC_VD_CFMT_CTRL,
- AFBC_VD_CFMT_W,
- AFBC_MIF_HOR_SCOPE,
- AFBC_MIF_VER_SCOPE,
- AFBC_PIXEL_HOR_SCOPE,
- AFBC_PIXEL_VER_SCOPE,
- AFBC_VD_CFMT_H,
- },
- {
- VD2_AFBC_ENABLE,
- VD2_AFBC_MODE,
- VD2_AFBC_SIZE_IN,
- VD2_AFBC_DEC_DEF_COLOR,
- VD2_AFBC_CONV_CTRL,
- VD2_AFBC_LBUF_DEPTH,
- VD2_AFBC_HEAD_BADDR,
- VD2_AFBC_BODY_BADDR,
- VD2_AFBC_OUT_XSCOPE,
- VD2_AFBC_OUT_YSCOPE,
- VD2_AFBC_STAT,
- VD2_AFBC_VD_CFMT_CTRL,
- VD2_AFBC_VD_CFMT_W,
- VD2_AFBC_MIF_HOR_SCOPE,
- VD2_AFBC_MIF_VER_SCOPE,
- VD2_AFBC_PIXEL_HOR_SCOPE,
- VD2_AFBC_PIXEL_VER_SCOPE,
- VD2_AFBC_VD_CFMT_H,
-
- },
-
-};
-
-#define AFBC_DEC_SEL (eAFBC_DEC1)
-
-static enum eAFBC_DEC afbc_get_decnub(void)
-{
- enum eAFBC_DEC sel_dec = eAFBC_DEC0;
-
- if (is_meson_gxl_cpu())
- sel_dec = eAFBC_DEC0;
- else if (is_meson_txlx_cpu())
- sel_dec = eAFBC_DEC1;
- else if (is_meson_g12a_cpu())
- sel_dec = AFBC_DEC_SEL;
- /* TL1 only have AFBC0 */
- else if (is_meson_tl1_cpu())
- sel_dec = eAFBC_DEC0;
- return sel_dec;
-}
-
-static const unsigned int *afbc_get_regbase(void)
-{
- return ®_AFBC[afbc_get_decnub()][0];
-}
-
-bool dimhv3_afbc_is_supported(void)
-{
- bool ret = false;
-
- /*currently support txlx and g12a*/
- if (is_meson_txlx_cpu() ||
- is_meson_g12a_cpu()
- /*|| is_meson_tl1_cpu()*/)
- ret = false;
- return ret;
-}
-
-static void afbc_sw_trig(bool on);
-
-void dimhv3_enable_afbc_input(struct vframe_s *vf)
-{
- unsigned int r, u, v, w_aligned, h_aligned;
- unsigned int out_height = 0;
- unsigned int vfmt_rpt_first = 1, vt_ini_phase = 0;
- const unsigned int *reg = afbc_get_regbase();
-
- if (!dimhv3_afbc_is_supported())
- return;
-
- if ((vf->type & VIDTYPE_COMPRESS)) {
- /* only reg for the first time*/
- dimhv3_afbc_reg_sw(true);
- afbc_sw_trig(true);
- } else {
- afbc_sw_trig(false);
- return;
- }
- w_aligned = round_up((vf->width - 1), 32);
- h_aligned = round_up((vf->height - 1), 4);
- r = (3 << 24) |
- (10 << 16) |
- (1 << 14) | /*burst1 1*/
- (vf->bitdepth & BITDEPTH_MASK);
- if (vf->bitdepth & BITDEPTH_SAVING_MODE)
- r |= (1 << 28); /* mem_saving_mode */
- if (vf->type & VIDTYPE_SCATTER)
- r |= (1 << 29);
- out_height = h_aligned;
- if ((vf->type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP) {
- r |= 0x40;
- vt_ini_phase = 0xc;
- out_height = h_aligned >> 1;
- } else if ((vf->type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_BOTTOM) {
- r |= 0x80;
- vt_ini_phase = 0x4;
- vfmt_rpt_first = 0;
- out_height = h_aligned >> 1;
- }
- dimv3_RDMA_WR(reg[eAFBC_MODE], r);
- r = 0x100;
- /* TL1 add bit[13:12]: fmt_mode; 0:yuv444; 1:yuv422; 2:yuv420
- * di does not support yuv444, so for fmt yuv444 di will bypass+
- */
- if (is_meson_tl1_cpu()) {
- if (vf->type & VIDTYPE_VIU_444)
- r |= (0 << 12);
- else if (vf->type & VIDTYPE_VIU_422)
- r |= (1 << 12);
- else
- r |= (2 << 12);
- }
- dimv3_RDMA_WR(reg[eAFBC_CONV_CTRL], r);
- u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
- v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
- dimv3_RDMA_WR(reg[eAFBC_DEC_DEF_COLOR],
- 0x3FF00000 | /*Y,bit20+*/
- 0x80 << (u + 10) |
- 0x80 << v);
- /* chroma formatter */
- dimv3_RDMA_WR(reg[eAFBC_VD_CFMT_CTRL],
- (1 << 21) | /* HFORMATTER_YC_RATIO_2_1 */
- (1 << 20) | /* HFORMATTER_EN */
- (vfmt_rpt_first << 16) | /* VFORMATTER_RPTLINE0_EN */
- (vt_ini_phase << 8) |
- (16 << 1) | /* VFORMATTER_PHASE_BIT */
- 0); /* different with inp */
-
- dimv3_RDMA_WR(reg[eAFBC_VD_CFMT_W],
- (w_aligned << 16) | (w_aligned / 2));
- dimv3_RDMA_WR(reg[eAFBC_MIF_HOR_SCOPE],
- (0 << 16) | ((w_aligned >> 5) - 1));
- dimv3_RDMA_WR(reg[eAFBC_MIF_VER_SCOPE],
- (0 << 16) | ((h_aligned >> 2) - 1));
-
- dimv3_RDMA_WR(reg[eAFBC_PIXEL_HOR_SCOPE],
- (0 << 16) | (vf->width - 1));
- dimv3_RDMA_WR(reg[eAFBC_VD_CFMT_H], out_height);
-
- dimv3_RDMA_WR(reg[eAFBC_PIXEL_VER_SCOPE],
- 0 << 16 | (vf->height - 1));
- dimv3_RDMA_WR(reg[eAFBC_SIZE_IN], h_aligned | w_aligned << 16);
- dimv3_RDMA_WR(reg[eAFBC_SIZE_OUT], out_height | w_aligned << 16);
- dimv3_RDMA_WR(reg[eAFBC_HEAD_BADDR], vf->compHeadAddr >> 4);
- dimv3_RDMA_WR(reg[eAFBC_BODY_BADDR], vf->compBodyAddr >> 4);
-}
-
-static void afbcx_power_sw(enum eAFBC_DEC decsel, bool on) /*g12a*/
-{
- unsigned int reg_ctrl;
-
- if (decsel == eAFBC_DEC0)
- reg_ctrl = VD1_AFBCD0_MISC_CTRL;
- else
- reg_ctrl = VD2_AFBCD1_MISC_CTRL;
- if (on)
- dimv3_RDMA_WR_BITS(reg_ctrl, 0, 0, 8);
- else
- dimv3_RDMA_WR_BITS(reg_ctrl, 0x55, 0, 8);
-}
-
-static void afbcx_sw(bool on) /*g12a*/
-{
- unsigned int tmp;
- unsigned int mask;
- unsigned int reg_ctrl, reg_en;
- enum eAFBC_DEC dec_sel;
-
- dec_sel = afbc_get_decnub();
-
- if (dec_sel == eAFBC_DEC0) {
- reg_ctrl = VD1_AFBCD0_MISC_CTRL;
- reg_en = AFBC_ENABLE;
- } else {
- reg_ctrl = VD2_AFBCD1_MISC_CTRL;
- reg_en = VD2_AFBC_ENABLE;
- }
-
- mask = (3 << 20) | (1 << 12) | (1 << 9);
- /*clear*/
- tmp = dimv3_RDMA_RD(reg_ctrl) & (~mask);
-
- if (on) {
- tmp = tmp |
- (2 << 20) |
- (1 << 12) |
- (1 << 9);
- dimv3_RDMA_WR(reg_ctrl, tmp);
- dimv3_RDMA_WR_BITS(VD2_AFBCD1_MISC_CTRL,
- (reg_ctrl == VD1_AFBCD0_MISC_CTRL) ? 0 : 1,
- 8, 1);
- dimv3_RDMA_WR(reg_en, 0x1600);
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
- /*TL1 add mem control bit */
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- dimv3_RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 1, 22, 1);
- } else {
- dimv3_RDMA_WR(reg_ctrl, tmp);
- dimv3_RDMA_WR(reg_en, 0x1600);
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- if (is_meson_tl1_cpu() || is_meson_tm2_cpu())
- dimv3_RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 0, 22, 1);
- }
-#if 0
- PR_INF("%s,on[%d],CTRL[0x%x],en[0x%x]\n", __func__, on,
- dimv3_RDMA_RD(VD1_AFBCD0_MISC_CTRL),
- dimv3_RDMA_RD(VD1_AFBCD0_MISC_CTRL));
-#endif
-}
-
-static void afbc_sw_old(bool on)/*txlx*/
-{
- enum eAFBC_DEC dec_sel;
- unsigned int reg_en;
-
- dec_sel = afbc_get_decnub();
-
- if (dec_sel == eAFBC_DEC0) {
- /*reg_ctrl = VD1_AFBCD0_MISC_CTRL;*/
- reg_en = AFBC_ENABLE;
- } else {
- /*reg_ctrl = VD2_AFBCD1_MISC_CTRL;*/
- reg_en = VD2_AFBC_ENABLE;
- }
-
- if (on) {
- /* DI inp(current data) switch to AFBC */
- if (dimv3_RDMA_RD_BITS(VIU_MISC_CTRL0, 29, 1) != 1)
- dimv3_RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 29, 1);
- if (dimv3_RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 1)
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
- if (dimv3_RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 1)
- dimv3_RDMA_WR_BITS(VIU_MISC_CTRL1, 1, 0, 1);
- if (dec_sel == eAFBC_DEC0) {
- /*gxl only?*/
- if (dimv3_RDMA_RD_BITS(VIU_MISC_CTRL0, 19, 1) != 1)
- dimv3_RDMA_WR_BITS(VIU_MISC_CTRL0, 1, 19, 1);
- }
- if (dimv3_RDMA_RD(reg_en) != 0x1600)
- dimv3_RDMA_WR(reg_en, 0x1600);
-
- } else {
- dimv3_RDMA_WR(reg_en, 0);
- /* afbc to vpp(replace vd1) enable */
-
- if (dimv3_RDMA_RD_BITS(VIU_MISC_CTRL1, 0, 1) != 0 ||
- dimv3_RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) != 0) {
- dimv3_RDMA_WR_BITS(VIU_MISC_CTRL1, 0, 0, 1);
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- }
- }
-}
-
-static bool afbc_is_used(void)
-{
- bool ret = false;
-
- if (dimv3_RDMA_RD_BITS(VIUB_MISC_CTRL0, 16, 1) == 1)
- ret = true;
-
- /*dim_print("%s:%d\n",__func__,ret);*/
-
- return ret;
-}
-
-static void afbc_power_sw(bool on)
-{
- /*afbc*/
- enum eAFBC_DEC dec_sel;
- unsigned int vpu_sel;
-
- dec_sel = afbc_get_decnub();
- if (dec_sel == eAFBC_DEC0)
- vpu_sel = VPU_AFBC_DEC;
- else
- vpu_sel = VPU_AFBC_DEC1;
-
- extv3_ops.switch_vpu_mem_pd_vmod(vpu_sel, on);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- afbcx_power_sw(dec_sel, on);
-}
-
-static int afbc_reg_unreg_flag;
-void dimhv3_afbc_reg_sw(bool on)
-{
- if (!dimhv3_afbc_is_supported())
- return;
-
- if (on && (!afbc_reg_unreg_flag)) {
- afbc_power_sw(true);
- afbc_reg_unreg_flag = 1;
- }
- if ((!on) && afbc_reg_unreg_flag) {
- afbc_sw_trig(false);
- afbc_power_sw(false);
- afbc_reg_unreg_flag = 0;
- }
-}
-
-static void afbc_sw(bool on)
-{
- if (is_meson_gxl_cpu() || is_meson_txlx_cpu())
- afbc_sw_old(on);
- else
- afbcx_sw(on);
-}
-
-static void afbc_sw_trig(bool on)
-{
- afbc_sw(on);
-}
-
-static void afbc_input_sw(bool on)
-{
- const unsigned int *reg = afbc_get_regbase();
- unsigned int reg_AFBC_ENABLE;
-
- if (!dimhv3_afbc_is_supported())
- return;
-
- reg_AFBC_ENABLE = reg[eAFBC_ENABLE];
-
- /*dim_print("%s:0x%x\n", __func__,reg_AFBC_ENABLE);*/
- if (on)
- dimv3_RDMA_WR_BITS(reg_AFBC_ENABLE, 1, 8, 1);
- else
- dimv3_RDMA_WR_BITS(reg_AFBC_ENABLE, 0, 8, 1);
-}
-
-void dimhv3_enable_mc_di_pre_g12(struct DI_MC_MIF_s *mcinford_mif,
- struct DI_MC_MIF_s *mcinfowr_mif,
- struct DI_MC_MIF_s *mcvecwr_mif,
- unsigned char mcdi_en)
-{
- dimv3_RDMA_WR_BITS(MCDI_MOTINEN, (mcdi_en ? 3 : 0), 0, 2);
- if (is_meson_g12a_cpu() ||
- is_meson_g12b_cpu() ||
- is_meson_sm1_cpu())
- dimv3_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfef7ff : 0));
- else
- dimv3_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfff7ff : 0));
-
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, (mcdi_en ? 3 : 0), 16, 2);
-
- dimv3_RDMA_WR_BITS(MCINFRD_SCOPE_X, mcinford_mif->size_x, 16, 13);
- dimv3_RDMA_WR_BITS(MCINFRD_SCOPE_Y, mcinford_mif->size_y, 16, 13);
- dimv3_RDMA_WR_BITS(MCINFRD_CTRL1, mcinford_mif->canvas_num, 16, 8);
- dimv3_RDMA_WR_BITS(MCINFRD_CTRL1, 2, 0, 3);
-
- dimv3_RDMA_WR_BITS(MCVECWR_X, mcvecwr_mif->size_x, 0, 13);
- dimv3_RDMA_WR_BITS(MCVECWR_Y, mcvecwr_mif->size_y, 0, 13);
- dimv3_RDMA_WR_BITS(MCVECWR_CTRL, mcvecwr_mif->canvas_num, 0, 8);
- dimv3_RDMA_WR_BITS(MCVECWR_CAN_SIZE, mcvecwr_mif->size_y, 0, 13);
- dimv3_RDMA_WR_BITS(MCVECWR_CAN_SIZE, mcvecwr_mif->size_x, 16, 13);
-
- dimv3_RDMA_WR_BITS(MCINFWR_X, mcinfowr_mif->size_x, 0, 13);
- dimv3_RDMA_WR_BITS(MCINFWR_Y, mcinfowr_mif->size_y, 0, 13);
- dimv3_RDMA_WR_BITS(MCINFWR_CTRL, mcinfowr_mif->canvas_num, 0, 8);
- dimv3_RDMA_WR_BITS(MCINFWR_CAN_SIZE, mcinfowr_mif->size_y, 0, 13);
- dimv3_RDMA_WR_BITS(MCINFWR_CAN_SIZE, mcinfowr_mif->size_x, 16, 13);
-}
-
-void dimhv3_enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
- struct DI_MC_MIF_s *di_mcinfowr_mif,
- struct DI_MC_MIF_s *di_mcvecwr_mif,
- unsigned char mcdi_en)
-{
- bool me_auto_en = true;
- unsigned int ctrl_mode = 0;
-
- dimv3_RDMA_WR_BITS(DI_MTN_CTRL1, (mcdi_en ? 3 : 0), 12, 2);
- if (is_meson_gxlx_cpu() || is_meson_txhd_cpu())
- me_auto_en = false;
-
- ctrl_mode = (me_auto_en ? 0x1bfff7ff : 0x1bfe37ff);
- dimv3_RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? ctrl_mode : 0));
- dimv3_RDMA_WR_BITS(MCDI_MOTINEN, (mcdi_en ? 3 : 0), 0, 2);
-
- dimv3_RDMA_WR(MCDI_MCVECWR_X, di_mcvecwr_mif->size_x);
- dimv3_RDMA_WR(MCDI_MCVECWR_Y, di_mcvecwr_mif->size_y);
- dimv3_RDMA_WR(MCDI_MCINFOWR_X, di_mcinfowr_mif->size_x);
- dimv3_RDMA_WR(MCDI_MCINFOWR_Y, di_mcinfowr_mif->size_y);
-
- dimv3_RDMA_WR(MCDI_MCINFORD_X, di_mcinford_mif->size_x);
- dimv3_RDMA_WR(MCDI_MCINFORD_Y, di_mcinford_mif->size_y);
- dimv3_RDMA_WR(MCDI_MCVECWR_CANVAS_SIZE,
- (di_mcvecwr_mif->size_x << 16) + di_mcvecwr_mif->size_y);
- dimv3_RDMA_WR(MCDI_MCINFOWR_CANVAS_SIZE,
- (di_mcinfowr_mif->size_x << 16) + di_mcinfowr_mif->size_y);
- dimv3_RDMA_WR(MCDI_MCINFORD_CANVAS_SIZE,
- (di_mcinford_mif->size_x << 16) + di_mcinford_mif->size_y);
-
- dimv3_RDMA_WR(MCDI_MCVECWR_CTRL,
- di_mcvecwr_mif->canvas_num |
- (0 << 14) | /* sync latch en */
- (dimp_get(eDI_MP_pre_urgent) << 8) | /* urgent */
- (1 << 12) | /*enable reset by frame rst*/
- (0x4031 << 16));
- dimv3_RDMA_WR(MCDI_MCINFOWR_CTRL,
- di_mcinfowr_mif->canvas_num |
- (0 << 14) | /* sync latch en */
- (dimp_get(eDI_MP_pre_urgent) << 8) | /* urgent */
- (1 << 12) | /*enable reset by frame rst*/
- (0x4042 << 16));
- dimv3_RDMA_WR(MCDI_MCINFORD_CTRL,
- di_mcinford_mif->canvas_num |
- (0 << 10) | /* sync latch en */
- (dimp_get(eDI_MP_pre_urgent) << 8) | /* urgent */
- (1 << 9) | /*enable reset by frame rst*/
- (0x42 << 16));
-}
-
-void dimhv3_enable_mc_di_post_g12(struct DI_MC_MIF_s *mcvecrd_mif,
- int urgent, bool reverse, int invert_mv)
-{
- unsigned int end_x;
-
- dimv3_VSYNC_WR_MPEG_REG(MCVECRD_CTRL1,
- mcvecrd_mif->canvas_num << 16 |
- 2 << 8 |
- (reverse ? 3 : 0) << 4 |
- 2);
- end_x = mcvecrd_mif->size_x + mcvecrd_mif->start_x;
- dimv3_VSYNC_WR_MPEG_REG(MCVECRD_SCOPE_X,
- mcvecrd_mif->start_x |
- end_x << 16);
- dimv3_VSYNC_WR_MPEG_REG(MCVECRD_SCOPE_Y,
- (reverse ? 1 : 0) << 30 |
- mcvecrd_mif->start_y |
- mcvecrd_mif->end_y << 16);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCVECRD_CTRL2, urgent, 16, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, mcvecrd_mif->vecrd_offset,
- 12, 3);
- if (mcvecrd_mif->blend_en) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcen_mode), 0, 2);
- if (!div3_cfg_top_get(EDI_CFG_ref_2)) {
- /*(!dimp_get(eDI_MP_post_wr_en)) {*/
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 1, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 3, 18, 2);
- } else {/*OTT-3210*/
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 2, 18, 2);
- }
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 2, 18, 2);
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcuv_en), 10, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- invert_mv, 17, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcdebug_mode), 2, 3);
-}
-
-void dimhv3_enable_mc_di_post(struct DI_MC_MIF_s *di_mcvecrd_mif,
- int urgent, bool reverse, int invert_mv)
-{
- di_mcvecrd_mif->size_y =
- (di_mcvecrd_mif->end_y - di_mcvecrd_mif->start_y + 1);
- dimv3_VSYNC_WR_MPEG_REG(MCDI_MCVECRD_X,
- (reverse ? 1 : 0) << 30 |
- di_mcvecrd_mif->start_x << 16 |
- (di_mcvecrd_mif->size_x +
- di_mcvecrd_mif->start_x));
- dimv3_VSYNC_WR_MPEG_REG(MCDI_MCVECRD_Y,
- (reverse ? 1 : 0) << 30 |
- di_mcvecrd_mif->start_y << 16 |
- di_mcvecrd_mif->end_y);
- dimv3_VSYNC_WR_MPEG_REG(MCDI_MCVECRD_CANVAS_SIZE,
- (di_mcvecrd_mif->size_x << 16) |
- di_mcvecrd_mif->size_y);
- dimv3_VSYNC_WR_MPEG_REG(MCDI_MCVECRD_CTRL,
- di_mcvecrd_mif->canvas_num |
- (urgent << 8) | /* urgent */
- (1 << 9) | /* canvas enable */
- (0 << 10) |
- (0x31 << 16));
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, di_mcvecrd_mif->vecrd_offset,
- 12, 3);
- if (di_mcvecrd_mif->blend_en)
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcen_mode), 0, 2);
- else
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcuv_en), 10, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 1, 11, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- invert_mv, 17, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- 3, 18, 2);
- }
- } else
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcuv_en), 9, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcdebug_mode), 2, 3);
-}
-
-static void set_di_inp_fmt_more(unsigned int repeat_l0_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int hfmt_en = 1, nrpt_phase0_en = 0;
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_RDMA_WR(DI_INP_FMT_CTRL,
- (hz_rpt << 28) | /* hz rpt pixel */
- (hz_ini_phase << 24) | /* hz ini phase */
- (0 << 23) | /* repeat p0 enable */
- (hz_yc_ratio << 21) | /* hz yc ratio */
- (hfmt_en << 20) | /* hz enable */
- (nrpt_phase0_en << 17) | /* nrpt_phase0 enable */
- (repeat_l0_en << 16) | /* repeat l0 enable */
- (0 << 12) | /* skip line num */
- (vt_ini_phase << 8) | /* vt ini phase */
- (vt_phase_step << 1) | /* vt phase step (3.4) */
- (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_RDMA_WR(DI_INP_FMT_W,
- (y_length << 16) | /* hz format width */
- (c_length << 0) /* vt format width */
- );
-}
-
-static void set_di_inp_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
-{
- unsigned int bytes_per_pixel;
- unsigned int demux_mode;
- unsigned int chro_rpt_lastl_ctrl, vfmt_rpt_first = 0;
- unsigned int luma0_rpt_loop_start;
- unsigned int luma0_rpt_loop_end;
- unsigned int luma0_rpt_loop_pat;
- unsigned int chroma0_rpt_loop_start;
- unsigned int chroma0_rpt_loop_end;
- unsigned int chroma0_rpt_loop_pat;
- unsigned int vt_ini_phase = 0;
- unsigned int reset_on_gofield;
- unsigned int little_endian = 0;
-
- if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = mif->src_prog ? 0 : 1;
- chroma0_rpt_loop_end = mif->src_prog ? 0 : 1;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = mif->src_prog ? 0 : 0x80;
-
- vfmt_rpt_first = 1;
- if (mif->output_field_num == 0)
- vt_ini_phase = 0xe;
- else
- vt_ini_phase = 0xa;
-
- if (mif->src_prog) {
- if (mif->output_field_num == 0) {
- vt_ini_phase = 0xc;
- } else {
- vt_ini_phase = 0x4;
- vfmt_rpt_first = 0;
- }
- }
-
- } else if (mif->set_separate_en != 0 && mif->src_field_mode == 0) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x0;
- chroma0_rpt_loop_pat = 0x0;
- } else if (mif->set_separate_en == 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = 1;
- chroma0_rpt_loop_end = 1;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = 0x80;
- } else {
- chro_rpt_lastl_ctrl = 0;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x00;
- chroma0_rpt_loop_pat = 0x00;
- }
-
- bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- demux_mode = mif->video_mode;
-
- if (mif->set_separate_en == 3)
- little_endian = 1;
- /* ---------------------- */
- /* General register */
- /* ---------------------- */
- reset_on_gofield = 1;/* default enable according to vlsi */
- dimv3_RDMA_WR(DI_INP_GEN_REG,
- (reset_on_gofield << 29) |
- (urgent << 28) | /* chroma urgent bit */
- (urgent << 27) | /* luma urgent bit. */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) | /*burst_size_cr*/
- (1 << 10) | /*burst_size_cb*/
- (3 << 8) | /*burst_size_y*/
- (little_endian << 4) |
- (chro_rpt_lastl_ctrl << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (0 << 0)/* cntl_enable */
- );
- if (mif->set_separate_en == 3) {
- /* Enable NV21 Display */
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG2, 2, 0, 2);
- } else if (mif->set_separate_en == 2) {
- /* Enable NV12 Display */
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG2, 1, 0, 2);
- } else {
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG2, 0, 0, 2);
- }
-
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG3, mif->bit_mode & 0x3, 8, 2);
- if (mif->set_separate_en == 3)
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG3, 0, 0, 1);
- else
- dimv3_RDMA_WR_BITS(DI_INP_GEN_REG3, 1, 0, 1);
- dimv3_RDMA_WR(DI_INP_CANVAS0,
- (mif->canvas0_addr2 << 16) | /* cntl_canvas0_addr2 */
- (mif->canvas0_addr1 << 8) | /* cntl_canvas0_addr1 */
- (mif->canvas0_addr0 << 0) /* cntl_canvas0_addr0 */
- );
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_INP_LUMA_X0, (mif->luma_x_end0 << 16) |
- /* cntl_luma_x_end0 */
- (mif->luma_x_start0 << 0)/* cntl_luma_x_start0 */
- );
- dimv3_RDMA_WR(DI_INP_LUMA_Y0, (mif->luma_y_end0 << 16) |
- /* cntl_luma_y_end0 */
- (mif->luma_y_start0 << 0) /* cntl_luma_y_start0 */
- );
- dimv3_RDMA_WR(DI_INP_CHROMA_X0, (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_RDMA_WR(DI_INP_CHROMA_Y0, (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_INP_RPT_LOOP,
- (0 << 28) |
- (0 << 24) |
- (0 << 20) |
- (0 << 16) |
- (chroma0_rpt_loop_start << 12) |
- (chroma0_rpt_loop_end << 8) |
- (luma0_rpt_loop_start << 4) |
- (luma0_rpt_loop_end << 0)
- );
-
- dimv3_RDMA_WR(DI_INP_LUMA0_RPT_PAT, luma0_rpt_loop_pat);
- dimv3_RDMA_WR(DI_INP_CHROMA0_RPT_PAT, chroma0_rpt_loop_pat);
-
- /* Dummy pixel value */
- dimv3_RDMA_WR(DI_INP_DUMMY_PIXEL, 0x00808000);
- if ((mif->set_separate_en != 0)) {/* 4:2:0 block mode.*/
- set_di_inp_fmt_more(vfmt_rpt_first,/* hfmt_en */
- 1,/* hz_yc_ratio */
- 0,/* hz_ini_phase */
- 1,/* vfmt_en */
- mif->src_prog ? 0 : 1,/* vt_yc_ratio */
- vt_ini_phase,/* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- /* y_length */
- mif->chroma_x_end0 - mif->chroma_x_start0 + 1,
- /* c length */
- 0); /* hz repeat. */
- } else {
- set_di_inp_fmt_more(vfmt_rpt_first, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- ((mif->luma_x_end0 >> 1) -
- (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat. */
- }
-}
-
-static void set_di_mem_fmt_more(int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_RDMA_WR(DI_MEM_FMT_CTRL,
- (hz_rpt << 28) | /* hz rpt pixel */
- (hz_ini_phase << 24) | /* hz ini phase */
- (0 << 23) | /* repeat p0 enable */
- (hz_yc_ratio << 21) | /* hz yc ratio */
- (hfmt_en << 20) | /* hz enable */
- (1 << 17) | /* nrpt_phase0 enable */
- (0 << 16) | /* repeat l0 enable */
- (0 << 12) | /* skip line num */
- (vt_ini_phase << 8) | /* vt ini phase */
- (vt_phase_step << 1) | /* vt phase step (3.4) */
- (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_RDMA_WR(DI_MEM_FMT_W,
- (y_length << 16) | /* hz format width */
- (c_length << 0) /* vt format width */
- );
-}
-
-static void set_di_chan2_fmt_more(int hfmt_en,
- int hz_yc_ratio,/* 2bit */
- int hz_ini_phase,/* 4bit */
- int vfmt_en,
- int vt_yc_ratio,/* 2bit */
- int vt_ini_phase,/* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_RDMA_WR(DI_CHAN2_FMT_CTRL,
- (hz_rpt << 28) | /* hz rpt pixel */
- (hz_ini_phase << 24) | /* hz ini phase */
- (0 << 23) | /* repeat p0 enable */
- (hz_yc_ratio << 21) | /* hz yc ratio */
- (hfmt_en << 20) | /* hz enable */
- (1 << 17) | /* nrpt_phase0 enable */
- (0 << 16) | /* repeat l0 enable */
- (0 << 12) | /* skip line num */
- (vt_ini_phase << 8) | /* vt ini phase */
- (vt_phase_step << 1) | /* vt phase step (3.4) */
- (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_RDMA_WR(DI_CHAN2_FMT_W, (y_length << 16) | /* hz format width */
- (c_length << 0) /* vt format width */
- );
-}
-
-static void set_di_mem_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
-{
- unsigned int bytes_per_pixel;
- unsigned int demux_mode;
- unsigned int chro_rpt_lastl_ctrl;
- unsigned int luma0_rpt_loop_start;
- unsigned int luma0_rpt_loop_end;
- unsigned int luma0_rpt_loop_pat;
- unsigned int chroma0_rpt_loop_start;
- unsigned int chroma0_rpt_loop_end;
- unsigned int chroma0_rpt_loop_pat;
- unsigned int reset_on_gofield;
-
- if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = 1;
- chroma0_rpt_loop_end = 1;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = 0x80;
- } else if (mif->set_separate_en != 0 && mif->src_field_mode == 0) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x0;
- chroma0_rpt_loop_pat = 0x0;
- } else if (mif->set_separate_en == 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = 0x00;
- } else {
- chro_rpt_lastl_ctrl = 0;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x00;
- chroma0_rpt_loop_pat = 0x00;
- }
-
- bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- demux_mode = mif->video_mode;
-
- /* ---------------------- */
- /* General register */
- /* ---------------------- */
- reset_on_gofield = 1;/* default enable according to vlsi */
- dimv3_RDMA_WR(DI_MEM_GEN_REG,
- (reset_on_gofield << 29) | /* reset on go field */
- (urgent << 28) | /* urgent bit. */
- (urgent << 27) | /* urgent bit. */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) | /*burst_size_cr*/
- (1 << 10) | /*burst_size_cb*/
- (3 << 8) | /*burst_size_y*/
- (chro_rpt_lastl_ctrl << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (0 << 0) /* cntl_enable */
- );
- if (mif->set_separate_en == 2) {
- /* Enable NV12 Display */
- dimv3_RDMA_WR_BITS(DI_MEM_GEN_REG2, 1, 0, 1);
- } else {
- dimv3_RDMA_WR_BITS(DI_MEM_GEN_REG2, 0, 0, 1);
- }
- dimv3_RDMA_WR_BITS(DI_MEM_GEN_REG3, mif->bit_mode & 0x3, 8, 2);
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_MEM_CANVAS0,
- (mif->canvas0_addr2 << 16) |
- /* cntl_canvas0_addr2 */
- (mif->canvas0_addr1 << 8) |
- (mif->canvas0_addr0 << 0));
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_MEM_LUMA_X0,
- (mif->luma_x_end0 << 16) |
- (mif->luma_x_start0 << 0) /* cntl_luma_x_start0 */
- );
- dimv3_RDMA_WR(DI_MEM_LUMA_Y0,
- (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0) /* cntl_luma_y_start0 */
- );
- dimv3_RDMA_WR(DI_MEM_CHROMA_X0,
- (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0)
- );
- dimv3_RDMA_WR(DI_MEM_CHROMA_Y0,
- (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0)
- );
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_MEM_RPT_LOOP, (0 << 28) |
- (0 << 24) |
- (0 << 20) |
- (0 << 16) |
- (chroma0_rpt_loop_start << 12) |
- (chroma0_rpt_loop_end << 8) |
- (luma0_rpt_loop_start << 4) |
- (luma0_rpt_loop_end << 0)
- );
-
- dimv3_RDMA_WR(DI_MEM_LUMA0_RPT_PAT, luma0_rpt_loop_pat);
- dimv3_RDMA_WR(DI_MEM_CHROMA0_RPT_PAT, chroma0_rpt_loop_pat);
-
- /* Dummy pixel value */
- dimv3_RDMA_WR(DI_MEM_DUMMY_PIXEL, 0x00808000);
- if ((mif->set_separate_en != 0)) {/* 4:2:0 block mode.*/
- set_di_mem_fmt_more(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- /* y_length */
- mif->chroma_x_end0 - mif->chroma_x_start0 + 1,
- /* c length */
- 0); /* hz repeat. */
- } else {
- set_di_mem_fmt_more(1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- ((mif->luma_x_end0 >> 1)
- - (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat. */
- }
-}
-
-static void set_di_if0_fmt_more(int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_VSYNC_WR_MPEG_REG(VIU_VD1_FMT_CTRL,
- (hz_rpt << 28) | /* hz rpt pixel */
- (hz_ini_phase << 24) | /* hz ini phase */
- (0 << 23) | /* repeat p0 enable*/
- (hz_yc_ratio << 21) | /* hz yc ratio */
- (hfmt_en << 20) | /* hz enable */
- (1 << 17) | /* nrpt_phase0 en*/
- (0 << 16) | /* repeat l0 en*/
- (0 << 12) | /* skip line num */
- (vt_ini_phase << 8) | /* vt ini phase */
- (vt_phase_step << 1) | /*vt phase step(3.4*/
- (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_VSYNC_WR_MPEG_REG(VIU_VD1_FMT_W,
- (y_length << 16) | /* hz format width */
- (c_length << 0) /* vt format width */
- );
-}
-
-static void set_di_if1_fmt_more(int hfmt_en,
- int hz_yc_ratio,/* 2bit */
- int hz_ini_phase,/* 4bit */
- int vfmt_en,
- int vt_yc_ratio,/* 2bit */
- int vt_ini_phase,/* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_FMT_CTRL,
- (hz_rpt << 28) /* hz rpt pixel */
- | (hz_ini_phase << 24) /* hz ini phase */
- | (0 << 23) /* repeat p0 enable */
- | (hz_yc_ratio << 21) /* hz yc ratio */
- | (hfmt_en << 20) /* hz enable */
- | (1 << 17) /* nrpt_phase0 enable*/
- | (0 << 16) /* repeat l0 enable */
- | (0 << 12) /* skip line num */
- | (vt_ini_phase << 8) /* vt ini phase */
- | (vt_phase_step << 1) /* vt phase step_3.4*/
- | (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_FMT_W,
- (y_length << 16) | (c_length << 0));
-}
-
-static void set_di_if2_fmt_more(int hfmt_en,
- int hz_yc_ratio,/* 2bit */
- int hz_ini_phase,/* 4bit */
- int vfmt_en,
- int vt_yc_ratio,/* 2bit */
- int vt_ini_phase,/* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_FMT_CTRL,
- (hz_rpt << 28) /* hz rpt pixel */
- | (hz_ini_phase << 24) /* hz ini phase */
- | (0 << 23) /* repeat p0 enable */
- | (hz_yc_ratio << 21) /* hz yc ratio */
- | (hfmt_en << 20) /* hz enable */
- | (1 << 17) /* nrpt_phase0 enable*/
- | (0 << 16) /* repeat l0 enable */
- | (0 << 12) /* skip line num */
- | (vt_ini_phase << 8) /* vt ini phase */
- | (vt_phase_step << 1) /* vt phase step(3.4)*/
- | (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_FMT_W,
- (y_length << 16) | (c_length << 0));
-}
-
-static const u32 vpat[] = {0, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
-
-static void set_di_if2_mif(struct DI_MIF_s *mif, int urgent,
- int hold_line, int vskip_cnt)
-{
- unsigned int bytes_per_pixel, demux_mode;
- unsigned int pat, loop = 0, chro_rpt_lastl_ctrl = 0;
-
- if (mif->set_separate_en == 1) {
- pat = vpat[(vskip_cnt << 1) + 1];
- /*top*/
- if (mif->src_field_mode == 0) {
- chro_rpt_lastl_ctrl = 1;
- loop = 0x11;
- pat <<= 4;
- }
- } else {
- loop = 0;
- pat = vpat[vskip_cnt];
- }
- #if 0
- bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- #else
- if (mif->set_separate_en) {
- bytes_per_pixel = 0;
- } else {
- if (mif->video_mode)
- bytes_per_pixel = 2;
- else
- bytes_per_pixel = 1;
- }
- #endif
- demux_mode = mif->video_mode;
-
- /* ---------------------- */
- /* General register */
- /* ---------------------- */
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_GEN_REG,
- (1 << 29) | /* reset on go field */
- (urgent << 28) | /* urgent */
- (urgent << 27) | /* luma urgent */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) | /*burst_size_cr*/
- (1 << 10) | /*burst_size_cb*/
- (3 << 8) | /*burst_size_y*/
- (chro_rpt_lastl_ctrl << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (1 << 0)/* cntl_enable */
- );
- /* post bit mode config, if0 config in video.c
- * dim_VSYNC_WR_MPEG_REG_BITS(DI_IF2_GEN_REG3, mif->bit_mode, 8, 2);
- */
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_CANVAS0, (mif->canvas0_addr2 << 16) |
- (mif->canvas0_addr1 << 8) | (mif->canvas0_addr0 << 0));
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_LUMA_X0, (mif->luma_x_end0 << 16) |
- (mif->luma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_LUMA_Y0, (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_CHROMA_X0, (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_CHROMA_Y0, (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_RPT_LOOP,
- (loop << 24) |
- (loop << 16) |
- (loop << 8) |
- (loop << 0)
- );
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_LUMA0_RPT_PAT, pat);
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_CHROMA0_RPT_PAT, pat);
-
- /* Dummy pixel value */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_DUMMY_PIXEL, 0x00808000);
- if (mif->set_separate_en != 0) { /* 4:2:0 block mode. */
- set_di_if2_fmt_more(1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- mif->chroma_x_end0 -
- mif->chroma_x_start0 + 1,
- 0); /* hz repeat. */
- } else {
- set_di_if2_fmt_more(1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- ((mif->luma_x_end0 >> 1) -
- (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat */
- }
-}
-
-static void set_di_if1_mif(struct DI_MIF_s *mif, int urgent,
- int hold_line, int vskip_cnt)
-{
- unsigned int bytes_per_pixel, demux_mode;
- unsigned int pat, loop = 0, chro_rpt_lastl_ctrl = 0;
-
- if (mif->set_separate_en == 1) {
- pat = vpat[(vskip_cnt << 1) + 1];
- /*top*/
- if (mif->src_field_mode == 0) {
- chro_rpt_lastl_ctrl = 1;
- loop = 0x11;
- pat <<= 4;
- }
- } else {
- loop = 0;
- pat = vpat[vskip_cnt];
- }
- #if 0
- bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- #else
- if (mif->set_separate_en) {
- bytes_per_pixel = 0;
- } else {
- if (mif->video_mode)
- bytes_per_pixel = 2;
- else
- bytes_per_pixel = 1;
- }
- #endif
- demux_mode = mif->video_mode;
-
- /* ---------------------- */
- /* General register */
- /* ---------------------- */
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG,
- (1 << 29) | /* reset on go field */
- (urgent << 28) | /* urgent */
- (urgent << 27) | /* luma urgent */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) | /*burst_size_cr*/
- (1 << 10) | /*burst_size_cb*/
- (3 << 8) | /*burst_size_y*/
- (chro_rpt_lastl_ctrl << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (1 << 0) /* cntl_enable */
- );
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_CANVAS0,
- (mif->canvas0_addr2 << 16) |
- (mif->canvas0_addr1 << 8) |
- (mif->canvas0_addr0 << 0));
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_LUMA_X0,
- (mif->luma_x_end0 << 16) |
- (mif->luma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_LUMA_Y0,
- (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_CHROMA_X0,
- (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_CHROMA_Y0,
- (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_RPT_LOOP,
- (loop << 24) |
- (loop << 16) |
- (loop << 8) |
- (loop << 0)
- );
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_LUMA0_RPT_PAT, pat);
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_CHROMA0_RPT_PAT, pat);
-
- /* Dummy pixel value */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_DUMMY_PIXEL, 0x00808000);
- if (mif->set_separate_en != 0) { /* 4:2:0 block mode. */
- set_di_if1_fmt_more(1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- mif->chroma_x_end0 -
- mif->chroma_x_start0 + 1,
- 0); /* hz repeat. */
- } else {
- set_di_if1_fmt_more(1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- ((mif->luma_x_end0 >> 1) -
- (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat */
- }
-}
-
-static void set_di_chan2_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
-{
- unsigned int bytes_per_pixel;
- unsigned int demux_mode;
- unsigned int chro_rpt_lastl_ctrl;
- unsigned int luma0_rpt_loop_start;
- unsigned int luma0_rpt_loop_end;
- unsigned int luma0_rpt_loop_pat;
- unsigned int chroma0_rpt_loop_start;
- unsigned int chroma0_rpt_loop_end;
- unsigned int chroma0_rpt_loop_pat;
- unsigned int reset_on_gofield;
-
- if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = 1;
- chroma0_rpt_loop_end = 1;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = 0x80;
- } else if (mif->set_separate_en != 0 && mif->src_field_mode == 0) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x0;
- chroma0_rpt_loop_pat = 0x0;
- } else if (mif->set_separate_en == 0 && mif->src_field_mode == 1) {
- chro_rpt_lastl_ctrl = 1;
- luma0_rpt_loop_start = 1;
- luma0_rpt_loop_end = 1;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x80;
- chroma0_rpt_loop_pat = 0x00;
- } else {
- chro_rpt_lastl_ctrl = 0;
- luma0_rpt_loop_start = 0;
- luma0_rpt_loop_end = 0;
- chroma0_rpt_loop_start = 0;
- chroma0_rpt_loop_end = 0;
- luma0_rpt_loop_pat = 0x00;
- chroma0_rpt_loop_pat = 0x00;
- }
- #if 0
- bytes_per_pixel = mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- #else
- if (mif->set_separate_en) {
- bytes_per_pixel = 0;
- } else {
- if (mif->video_mode)
- bytes_per_pixel = 2;
- else
- bytes_per_pixel = 1;
- }
- #endif
- demux_mode = mif->video_mode;
-
- /* ---------------------- */
- /* General register */
- /* ---------------------- */
- reset_on_gofield = 1;/* default enable according to vlsi */
- dimv3_RDMA_WR(DI_CHAN2_GEN_REG,
- (reset_on_gofield << 29) |
- (urgent << 28) | /* urgent */
- (urgent << 27) | /* luma urgent */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) |
- (bytes_per_pixel << 14) |
- (1 << 12) | /*burst_size_cr*/
- (1 << 10) | /*burst_size_cb*/
- (3 << 8) | /*burst_size_y*/
- (chro_rpt_lastl_ctrl << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (0 << 0) /* cntl_enable */
- );
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- if (mif->set_separate_en == 2) {
- /* Enable NV12 Display */
- dimv3_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 1, 0, 1);
- } else {
- dimv3_RDMA_WR_BITS(DI_CHAN2_GEN_REG2, 0, 0, 1);
- }
- dimv3_RDMA_WR_BITS(DI_CHAN2_GEN_REG3, mif->bit_mode & 0x3, 8, 2);
- dimv3_RDMA_WR(DI_CHAN2_CANVAS0, (mif->canvas0_addr2 << 16) |
- (mif->canvas0_addr1 << 8) |
- (mif->canvas0_addr0 << 0));
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_CHAN2_LUMA_X0, (mif->luma_x_end0 << 16) |
- /* cntl_luma_x_end0 */
- (mif->luma_x_start0 << 0));
- dimv3_RDMA_WR(DI_CHAN2_LUMA_Y0, (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0));
- dimv3_RDMA_WR(DI_CHAN2_CHROMA_X0, (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_RDMA_WR(DI_CHAN2_CHROMA_Y0, (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_RDMA_WR(DI_CHAN2_RPT_LOOP,
- (0 << 28) |
- (0 << 24) |
- (0 << 20) |
- (0 << 16) |
- (0 << 12) |
- (0 << 8) |
- (luma0_rpt_loop_start << 4) |
- (luma0_rpt_loop_end << 0)
- );
-
- dimv3_RDMA_WR(DI_CHAN2_LUMA0_RPT_PAT, luma0_rpt_loop_pat);
-
- /* Dummy pixel value */
- dimv3_RDMA_WR(DI_CHAN2_DUMMY_PIXEL, 0x00808000);
-
- if ((mif->set_separate_en != 0)) { /* 4:2:0 block mode. */
- set_di_chan2_fmt_more(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 -
- mif->luma_x_start0 + 1, /* y_length */
- mif->chroma_x_end0 -
- mif->chroma_x_start0 + 1,/* c length */
- 0); /* hz repeat. */
- } else {
- set_di_chan2_fmt_more(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- mif->luma_x_end0 -
- mif->luma_x_start0 + 1, /* y_length */
- ((mif->luma_x_end0 >> 1) -
- (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat. */
- }
-}
-
-static void set_di_if0_mif(struct DI_MIF_s *mif, int urgent, int hold_line,
- int vskip_cnt, int post_write_en)
-{
- unsigned int pat, loop = 0;
- unsigned int bytes_per_pixel, demux_mode;
-
- if (mif->set_separate_en == 1) {
- pat = vpat[(vskip_cnt << 1) + 1];
- if (mif->src_field_mode == 0) {/* top */
- loop = 0x11;
- pat <<= 4;
- }
- } else {
- loop = 0;
- pat = vpat[vskip_cnt];
-
- if (post_write_en) {
- bytes_per_pixel =
- mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- demux_mode = mif->video_mode;
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_GEN_REG,
- (1 << 29) | /* reset on go field */
- (urgent << 28) | /* urgent */
- (urgent << 27) | /* luma urgent */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) |
- (1 << 10) |
- (3 << 8) |
- (0 << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (1 << 0) /* cntl_enable */
- );
- }
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_CANVAS0,
- (mif->canvas0_addr2 << 16) |
- (mif->canvas0_addr1 << 8) |
- (mif->canvas0_addr0 << 0));
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_LUMA_X0, (mif->luma_x_end0 << 16) |
- (mif->luma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_LUMA_Y0, (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_CHROMA_X0, (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_CHROMA_Y0, (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
- }
-
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_RPT_LOOP,
- (loop << 24) |
- (loop << 16) |
- (loop << 8) |
- (loop << 0));
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_LUMA0_RPT_PAT, pat);
- dimv3_VSYNC_WR_MPEG_REG(VD1_IF0_CHROMA0_RPT_PAT, pat);
-
- if (post_write_en) {
- /* 4:2:0 block mode. */
- if (mif->set_separate_en != 0) {
- set_di_if0_fmt_more(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- /* y_length */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- /* c length */
- mif->chroma_x_end0 - mif->chroma_x_start0 + 1,
- 0); /* hz repeat. */
- } else {
- set_di_if0_fmt_more(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- /* y_length */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- /* c length */
- ((mif->luma_x_end0 >> 1) - (
- mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat */
- }
- }
-}
-
-static void set_di_if0_fmt_more_g12(int hfmt_en,
- int hz_yc_ratio, /* 2bit */
- int hz_ini_phase, /* 4bit */
- int vfmt_en,
- int vt_yc_ratio, /* 2bit */
- int vt_ini_phase, /* 4bit */
- int y_length,
- int c_length,
- int hz_rpt /* 1bit */
- )
-{
- int vt_phase_step = (16 >> vt_yc_ratio);
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_FMT_CTRL,
- (hz_rpt << 28) | /* hz rpt pixel */
- (hz_ini_phase << 24) | /* hz ini phase */
- (0 << 23) | /* repeat p0 enable */
- (hz_yc_ratio << 21) | /* hz yc ratio */
- (hfmt_en << 20) | /* hz enable */
- (1 << 17) | /* nrpt_phase0 enable */
- (0 << 16) | /* repeat l0 enable */
- (0 << 12) | /* skip line num */
- (vt_ini_phase << 8) | /* vt ini phase */
- (vt_phase_step << 1) | /* vt phase step (3.4) */
- (vfmt_en << 0) /* vt enable */
- );
-
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_FMT_W,
- (y_length << 16) | /* hz format width */
- (c_length << 0) /* vt format width */
- );
-}
-
-static void set_di_if0_mif_g12(struct DI_MIF_s *mif, int urgent, int hold_line,
- int vskip_cnt, int post_write_en)
-{
- unsigned int pat, loop = 0;
- unsigned int bytes_per_pixel, demux_mode;
-
- if (mif->set_separate_en == 1) {
- pat = vpat[(vskip_cnt << 1) + 1];
- if (mif->src_field_mode == 0) {/* top */
- loop = 0x11;
- pat <<= 4;
- }
- } else {
- loop = 0;
- pat = vpat[vskip_cnt];
-
- bytes_per_pixel =
- mif->set_separate_en ? 0 : (mif->video_mode ? 2 : 1);
- demux_mode = mif->video_mode;
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_GEN_REG,
- (1 << 29) | /* reset on go field */
- (urgent << 28) | /* urgent */
- (urgent << 27) | /* luma urgent */
- (1 << 25) | /* no dummy data. */
- (hold_line << 19) | /* hold lines */
- (1 << 18) | /* push dummy pixel */
- (demux_mode << 16) | /* demux_mode */
- (bytes_per_pixel << 14) |
- (1 << 12) |
- (1 << 10) |
- (3 << 8) |
- (0 << 6) |
- ((mif->set_separate_en != 0) << 1) |
- (1 << 0) /* cntl_enable */
- );
- /* ---------------------- */
- /* Canvas */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_CANVAS0,
- (mif->canvas0_addr2 << 16) |
- (mif->canvas0_addr1 << 8) |
- (mif->canvas0_addr0 << 0));
- if (mif->set_separate_en == 2) {
- /* Enable NV12 Display */
- dimv3_RDMA_WR_BITS(DI_IF0_GEN_REG2, 1, 0, 1);
- } else {
- dimv3_RDMA_WR_BITS(DI_IF0_GEN_REG2, 0, 0, 1);
- }
-
- /* ---------------------- */
- /* Picture 0 X/Y start,end */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_LUMA_X0,
- (mif->luma_x_end0 << 16) |
- (mif->luma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_LUMA_Y0,
- (mif->luma_y_end0 << 16) |
- (mif->luma_y_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_CHROMA_X0,
- (mif->chroma_x_end0 << 16) |
- (mif->chroma_x_start0 << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_CHROMA_Y0,
- (mif->chroma_y_end0 << 16) |
- (mif->chroma_y_start0 << 0));
- }
- /* ---------------------- */
- /* Repeat or skip */
- /* ---------------------- */
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_REPEAT_LOOP,
- (loop << 24) |
- (loop << 16) |
- (loop << 8) |
- (loop << 0));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_LUMA0_RPT_PAT, pat);
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_CHROMA0_RPT_PAT, pat);
-
- /* 4:2:0 block mode. */
- if (mif->set_separate_en != 0) {
- set_di_if0_fmt_more_g12(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 1, /* vfmt_en */
- 1, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- /* y_length */
- mif->luma_x_end0 - mif->luma_x_start0 + 1,
- /* c length */
- mif->chroma_x_end0 - mif->chroma_x_start0 + 1,
- 0); /* hz repeat. */
- } else {
- set_di_if0_fmt_more_g12(
- 1, /* hfmt_en */
- 1, /* hz_yc_ratio */
- 0, /* hz_ini_phase */
- 0, /* vfmt_en */
- 0, /* vt_yc_ratio */
- 0, /* vt_ini_phase */
- /* y_length */
- mif->luma_x_end0 -
- mif->luma_x_start0 + 1,
- /* c length */
- ((mif->luma_x_end0 >> 1) -
- (mif->luma_x_start0 >> 1) + 1),
- 0); /* hz repeat */
- }
-}
-
-static unsigned int di_mc_update;
-void dimhv3_patch_post_update_mc(void)
-{
- if (di_mc_update == DI_MC_SW_ON_MASK)
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_CTRL, 1, 9, 1);
-}
-
-void dimhv3_patch_post_update_mc_sw(unsigned int cmd, bool on)
-{
- unsigned int l_flg = di_mc_update;
-
- switch (cmd) {
- case DI_MC_SW_IC:
- if (is_meson_gxtvbb_cpu() ||
- is_meson_txl_cpu() ||
- is_meson_txlx_cpu() ||
- is_meson_txhd_cpu()) {
- di_mc_update |= DI_MC_SW_IC;
- }
- break;
- case DI_MC_SW_REG:
- if (on) {
- di_mc_update |= cmd;
- di_mc_update &= ~DI_MC_SW_OTHER;
- } else {
- di_mc_update &= ~(cmd | DI_MC_SW_OTHER);
- }
- break;
- case DI_MC_SW_OTHER:
-
-/* case DI_MC_SW_POST:*/
- if (on)
- di_mc_update |= cmd;
- else
- di_mc_update &= ~cmd;
-
- break;
- }
-
- if (l_flg != di_mc_update)
- pr_debug("%s:0x%x->0x%x\n", __func__, l_flg, di_mc_update);
-}
-
-void dimhv3_post_ctrl(enum DI_HW_POST_CTRL contr, unsigned int post_write_en)
-{
- unsigned int reg_val;
-
- if (!post_write_en || !cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- return;
-
- switch (contr) {
- case DI_HW_POST_CTRL_INIT:
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL,
- 0x80000000 |
- dimp_get(eDI_MP_line_num_post_frst));
- break;
- case DI_HW_POST_CTRL_RESET: /*replace post_frame_reset_g12a*/
- reg_val = (0xc3200000 | dimp_get(eDI_MP_line_num_post_frst));
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, reg_val);
- reg_val = (0x83200000 | dimp_get(eDI_MP_line_num_post_frst));
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, reg_val);
-
- break;
- }
-}
-
-void dimhv3_initial_di_post_2(int hsize_post, int vsize_post,
- int hold_line, bool post_write_en)
-{
- div3_post_set_flow(post_write_en, eDI_POST_FLOW_STEP1_STOP);/*dbg a*/
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_SIZE,
- (hsize_post - 1) | ((vsize_post - 1) << 16));
-
- /* if post size < MIN_POST_WIDTH, force old ei */
- if (hsize_post < MIN_POST_WIDTH)
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_EI_CTRL3, 0, 31, 1);
- else
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_EI_CTRL3, 1, 31, 1);
-
- /* DI_VSYNC_WR_MPEG_REG(DI_BLEND_REG0_Y, (vsize_post >> 2) - 1); */
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG0_Y, (vsize_post - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG1_Y,
- ((vsize_post >> 2) << 16) |
- (2 * (vsize_post >> 2) - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG2_Y,
- ((2 * (vsize_post >> 2)) << 16) |
- (3 * (vsize_post >> 2) - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG3_Y,
- ((3 * (vsize_post >> 2)) << 16) |
- (vsize_post - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG0_X, (hsize_post - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG1_X, (hsize_post - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG2_X, (hsize_post - 1));
- dimv3_VSYNC_WR_MPEG_REG(DI_BLEND_REG3_X, (hsize_post - 1));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (post_write_en) {
- #if 0
- dimv3_print("%s:VD1_AFBCD0_MISC_CTRL\n", __func__);
- #endif
- /*di if0 mif to di post*/
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIUB_MISC_CTRL0, 0, 4, 1);
- /*di_mif0_en:select mif to di*/
- #if 0
- DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
- 1, 8, 1);
- #endif
- #ifdef DIM_HIS
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
- 0, 8, 1);
- #endif
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
- 1, 8, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIUB_MISC_CTRL0, 0, 4, 1);
- }
-
- } else {
- /* enable ma,disable if0 to vpp */
- if ((VSYNC_RD_MPEG_REG(VIU_MISC_CTRL0) & 0x50000) != 0x50000) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL0, 5, 16, 3);
- if (post_write_en)
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL0,
- 1, 28, 1);
- }
- }
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_CTRL,
- (0 << 0) |
- (0 << 1) |
- (0 << 2) |
- (0 << 3) |
- (0 << 4) |
- (0 << 5) |
- (0 << 6) |
- ((post_write_en ? 1 : 0) << 7) |
- ((post_write_en ? 0 : 1) << 8) |
- (0 << 9) |
- (0 << 10) |
- (0 << 11) |
- (0 << 12) |
- (hold_line << 16) |
- (0 << 29) |
- (0x3 << 30)
- );
-}
-
-static void post_bit_mode_config(unsigned char if0,
- unsigned char if1,
- unsigned char if2,
- unsigned char post_wr)
-{
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB))
- return;
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimv3_DI_Wr_reg_bits(DI_IF0_GEN_REG3, if0 & 0x3, 8, 2);
- else
- dimv3_DI_Wr_reg_bits(VD1_IF0_GEN_REG3, if0 & 0x3, 8, 2);
- dimv3_DI_Wr_reg_bits(DI_IF1_GEN_REG3, if1 & 0x3, 8, 2);
- dimv3_DI_Wr_reg_bits(DI_IF2_GEN_REG3, if2 & 0x3, 8, 2);
- #ifndef DIM_OUT_NV21 /* NO_NV21 */
- dimv3_DI_Wr_reg_bits(DI_DIWR_Y, post_wr & 0x1, 14, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) && ((post_wr & 0x3) == 0x3))
- dimv3_DI_Wr_reg_bits(DI_DIWR_CTRL, 0x3, 22, 2);
- #endif
-}
-
-void dimhv3_post_switch_buffer(
- struct DI_MIF_s *di_buf0_mif,
- struct DI_MIF_s *di_buf1_mif,
- struct DI_MIF_s *di_buf2_mif,
- struct DI_SIM_MIF_s *di_diwr_mif,
- struct DI_SIM_MIF_s *di_mtnprd_mif,
- struct DI_MC_MIF_s *di_mcvecrd_mif,
- int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
- int di_vpp_en, int di_ddr_en,
- int post_field_num, int hold_line, int urgent,
- int invert_mv, bool pd_enable, bool mc_enable,
- int vskip_cnt
-)
-{
- int ei_only, buf1_en;
-
- ei_only = ei_en && !blend_en && (di_vpp_en || di_ddr_en);
- buf1_en = (!ei_only && (di_ddr_en || di_vpp_en));
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_VSYNC_WR_MPEG_REG(DI_IF0_CANVAS0,
- (di_buf0_mif->canvas0_addr2 << 16) |
- (di_buf0_mif->canvas0_addr1 << 8) |
- (di_buf0_mif->canvas0_addr0 << 0));
- if (!di_ddr_en) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG,
- 0, 0, 1);
- }
- if (mc_enable) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCVECRD_CTRL1,
- di_mcvecrd_mif->canvas_num,
- 16, 8);
- }
- /*motion for current display field.*/
- if (blend_mtn_en) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MTNRD_CTRL1,
- di_mtnprd_mif->canvas_num,
- 16, 8);
- /* current field mtn canvas index.*/
- }
- } else {
- if ((VSYNC_RD_MPEG_REG(VIU_MISC_CTRL0) & 0x50000) != 0x50000)
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL0, 5, 16, 3);
- if (di_ddr_en)
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL0, 1, 28, 1);
- if (ei_en || di_vpp_en || di_ddr_en)
- set_di_if0_mif(di_buf0_mif, urgent,
- hold_line, vskip_cnt, di_ddr_en);
- if (mc_enable) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_CTRL,
- /* canvas enable */
- (1 << 9) |
- (urgent << 8) |
- di_mcvecrd_mif->canvas_num,
- 0, 10);
- }
- /*motion for current display field.*/
- if (blend_mtn_en) {
- dimv3_VSYNC_WR_MPEG_REG(DI_MTNRD_CTRL,
- (di_mtnprd_mif->canvas_num << 8) |
- (urgent << 16));
- /*current field mtn canvas index.*/
- }
- }
-
- if (!ei_only && (di_ddr_en || di_vpp_en)) {
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_CANVAS0,
- (di_buf1_mif->canvas0_addr2 << 16) |
- (di_buf1_mif->canvas0_addr1 << 8) |
- (di_buf1_mif->canvas0_addr0 << 0));
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_CANVAS0,
- (di_buf2_mif->canvas0_addr2 << 16) |
- (di_buf2_mif->canvas0_addr1 << 8) |
- (di_buf2_mif->canvas0_addr0 << 0));
- }
-
- if (di_ddr_en) {
- #ifndef DIM_OUT_NV21 /* NO_NV21 */
- dimv3_VSYNC_WR_MPEG_REG(DI_DIWR_CTRL,
- di_diwr_mif->canvas_num |
- (urgent << 16) |
- (2 << 26) |
- (di_ddr_en << 30));
- post_bit_mode_config(di_buf0_mif->bit_mode,
- di_buf1_mif->bit_mode,
- di_buf2_mif->bit_mode,
- di_diwr_mif->bit_mode);
- #endif
- }
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, blend_en, 31, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, blend_mode, 20, 2);
- if ((dimp_get(eDI_MP_pldn_ctrl_rflsh) == 1) && pd_enable)
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, 7, 22, 3);
-
- if (mc_enable) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- invert_mv,
- 17, 1);/* invert mv */
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- di_mcvecrd_mif->vecrd_offset, 12, 3);
- if (di_mcvecrd_mif->blend_en) {
- if (blend_mode == 1) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcen_mode), 0, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- 2, 18, 2);
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- dimp_get(eDI_MP_mcen_mode), 0, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- 1, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- 3, 18, 2);
- }
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 0, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL, 2, 18, 2);
- }
- }
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_POST_GL_THD,
- hold_line, 16, 5);
- hold_line = 0;
- }
-
- if (!is_meson_txlx_cpu())
- invert_mv = 0;
- if (dimp_get(eDI_MP_post_ctrl) != 0)
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_CTRL,
- dimp_get(eDI_MP_post_ctrl) |
- (0x3 << 30));
- else {
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_CTRL,
- ((ei_en | blend_en) << 0) | /* line buf 0 enable */
- ((blend_mode == 1 ? 1 : 0) << 1) |
- (ei_en << 2) | /* ei enable */
- (blend_mtn_en << 3) | /* mtn line buffer enable */
- (blend_mtn_en << 4) | /* mtnp read mif enable */
- (blend_en << 5) |
- (1 << 6) | /* di mux output enable */
- (di_ddr_en << 7) | /* di wr to SDRAM enable.*/
- (di_vpp_en << 8) | /* di to VPP enable. */
- (0 << 9) | /* mif0 to VPP enable. */
- (0 << 10) | /* post drop first. */
- (0 << 11) |
- (di_vpp_en << 12) | /* post viu link */
- (invert_mv << 14) |
- (hold_line << 16) | /* post hold line number */
- (post_field_num << 29) | /* post field number. */
- (0x3 << 30) /* post soft rst post frame rst. */
- );
- }
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A) && di_ddr_en) {
-#if 0
- postv3_frame_reset_g12a();
-#endif
- } else if (di_ddr_en && mc_enable) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_CTRL, 1, 9, 1);
- }
-}
-
-static void set_post_mtnrd_mif(struct DI_SIM_MIF_s *mtnprd_mif,
- unsigned char urgent)
-{
- dimv3_VSYNC_WR_MPEG_REG(DI_MTNPRD_X,
- (mtnprd_mif->start_x << 16) |
- (mtnprd_mif->end_x));
- dimv3_VSYNC_WR_MPEG_REG(DI_MTNPRD_Y,
- (mtnprd_mif->start_y << 16) |
- (mtnprd_mif->end_y));
- dimv3_VSYNC_WR_MPEG_REG(DI_MTNRD_CTRL,
- (mtnprd_mif->canvas_num << 8) |
- (urgent << 16)
- );
-}
-
-static void set_post_mtnrd_mif_g12(struct DI_SIM_MIF_s *mtnprd_mif)
-{
- dimv3_VSYNC_WR_MPEG_REG(MTNRD_SCOPE_X,
- (mtnprd_mif->end_x << 16) |
- (mtnprd_mif->start_x));
- dimv3_VSYNC_WR_MPEG_REG(MTNRD_SCOPE_Y,
- (mtnprd_mif->end_y << 16) |
- (mtnprd_mif->start_y));
- dimv3_VSYNC_WR_MPEG_REG_BITS(MTNRD_CTRL1,
- mtnprd_mif->canvas_num, 16, 8);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MTNRD_CTRL1, 0, 0, 3);
-}
-
-#ifdef DIM_OUT_NV21
-static void dimh_pst_mif_set(struct DI_SIM_MIF_s *cfg_mif,
- unsigned int urgent,
- unsigned int ddr_en);
-#endif
-
-void dimhv3_enable_di_post_2(
- struct DI_MIF_s *di_buf0_mif,
- struct DI_MIF_s *di_buf1_mif,
- struct DI_MIF_s *di_buf2_mif,
- struct DI_SIM_MIF_s *di_diwr_mif,
- struct DI_SIM_MIF_s *di_mtnprd_mif,
- int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
- int di_vpp_en, int di_ddr_en, int post_field_num,
- int hold_line, int urgent, int invert_mv,
- int vskip_cnt
-)
-{
- int ei_only;
- int buf1_en;
-
- ei_only = ei_en && !blend_en && (di_vpp_en || di_ddr_en);
- buf1_en = (!ei_only && (di_ddr_en || di_vpp_en));
-
- if (ei_en || di_vpp_en || di_ddr_en) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- set_di_if0_mif_g12(di_buf0_mif, di_vpp_en,
- hold_line, vskip_cnt, di_ddr_en);
- /* if di post vpp link disable vd1 for new if0 */
- if (!di_ddr_en) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG,
- 0, 0, 1);
- }
- } else
- set_di_if0_mif(di_buf0_mif, di_vpp_en,
- hold_line, vskip_cnt, di_ddr_en);
- }
-
- set_di_if1_mif(di_buf1_mif, di_vpp_en, hold_line, vskip_cnt);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- set_di_if2_mif(di_buf2_mif,
- di_vpp_en, hold_line, vskip_cnt);
- /* motion for current display field. */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- set_post_mtnrd_mif_g12(di_mtnprd_mif);
- else
- set_post_mtnrd_mif(di_mtnprd_mif, urgent);
- if (di_ddr_en) {
- #ifdef DIM_OUT_NV21 /* NO_NV21 */
- dimh_pst_mif_set(di_diwr_mif, urgent, di_ddr_en);
- post_bit_mode_config(di_buf0_mif->bit_mode,
- di_buf1_mif->bit_mode,
- di_buf2_mif->bit_mode,
- di_diwr_mif->bit_mode);
- #else
- dimv3_VSYNC_WR_MPEG_REG(DI_DIWR_X,
- (di_diwr_mif->start_x << 16) |
- (di_diwr_mif->end_x));
- dimv3_VSYNC_WR_MPEG_REG(DI_DIWR_Y,
- (3 << 30) |
- (di_diwr_mif->start_y << 16) |
- /* wr ext en from gxtvbb */
- (1 << 15) |
- (di_diwr_mif->end_y));
- dimv3_VSYNC_WR_MPEG_REG(DI_DIWR_CTRL,
- di_diwr_mif->canvas_num |
- (urgent << 16) |
- (2 << 26) |
- (di_ddr_en << 30));
- post_bit_mode_config(di_buf0_mif->bit_mode,
- di_buf1_mif->bit_mode,
- di_buf2_mif->bit_mode,
- di_diwr_mif->bit_mode);
- #endif
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, 7, 22, 3);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- blend_en & 0x1, 31, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- blend_mode & 0x3, 20, 2);
- if (!is_meson_txlx_cpu())
- invert_mv = 0;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_POST_GL_THD,
- hold_line, 16, 5);
- hold_line = 0;
- }
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_CTRL,
- ((ei_en | blend_en) << 0) | /* line buffer 0 enable */
- ((blend_mode == 1 ? 1 : 0) << 1) |
- (ei_en << 2) | /* ei enable */
- (blend_mtn_en << 3) | /* mtn line buffer enable */
- (blend_mtn_en << 4) | /* mtnp read mif enable */
- (blend_en << 5) |
- (1 << 6) | /* di mux output enable */
- /* di write to SDRAM enable. */
- (di_ddr_en << 7) |
- (di_vpp_en << 8) | /* di to VPP enable. */
- (0 << 9) | /* mif0 to VPP enable. */
- (0 << 10) | /* post drop first. */
- (0 << 11) |
- (di_vpp_en << 12) | /* post viu link */
- (invert_mv << 14) | /* invert mv */
- (hold_line << 16) | /* post hold line number */
- (post_field_num << 29) | /* post field number. */
- (0x3 << 30) /* post soft rst post frame rst. */
- );
-}
-
-void dimhv3_pst_trig_resize(void)
-{
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_SIZE, (32 - 1) | ((128 - 1) << 16));
-}
-
-void dimhv3_disable_post_deinterlace_2(void)
-{
- PR_INF("%s\n", __func__);
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_CTRL, 0x3 << 30);
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_SIZE, (32 - 1) | ((128 - 1) << 16));
- dimv3_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG, 0x3 << 30);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_VSYNC_WR_MPEG_REG(DI_IF2_GEN_REG, 0x3 << 30);
- /* disable ma,enable if0 to vpp,enable afbc to vpp */
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if ((VSYNC_RD_MPEG_REG(VIU_MISC_CTRL0) & 0x50000) != 0)
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL0, 0, 16, 4);
- /* DI inp(current data) switch to memory */
- dimv3_VSYNC_WR_MPEG_REG_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
- }
- /* dim_VSYNC_WR_MPEG_REG(DI_IF1_GEN_REG,
- * Rd(DI_IF1_GEN_REG) & 0xfffffffe);
- */
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- /*dbg a dim_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0);*/
- div3_post_set_flow(1, eDI_POST_FLOW_STEP1_STOP);
- #ifdef DIM_HIS
- dimv3_print("%s:VD1_AFBCD0_MISC_CTRL 0", __func__);
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 8, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 20, 2);
- #endif
- }
-}
-
-void dimhv3_enable_di_post_mif(enum gate_mode_e mode)
-{
- unsigned char gate = 0;
-
- switch (mode) {
- case GATE_OFF:
- gate = 1;
- break;
- case GATE_ON:
- gate = 2;
- break;
- case GATE_AUTO:
- gate = 2;
- break;
- default:
- gate = 0;
- }
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- /* enable if0 external gate freerun hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 2, 2);
- /* enable if1 external gate freerun hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 4, 2);
- /* enable if1 external gate freerun hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 6, 2);
- /* enable di wr external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 8, 2);
- /* enable mtn rd external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 10, 2);
- /* enable mv rd external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 12, 2);
- } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
- /* enable if1 external gate freerun hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1,
- ((gate == 0) ? 2 : gate), 2, 2);
- /* enable if2 external gate freerun hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1,
- ((gate == 0) ? 2 : gate), 4, 2);
- /* enable di wr external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 6, 2);
- /* enable mtn rd external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 8, 2);
- /* enable mv rd external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 10, 2);
- }
-}
-
-void dimv3_hw_disable(bool mc_enable)
-{
- dimhv3_enable_di_pre_mif(false, mc_enable);
- dimv3_DI_Wr(DI_POST_SIZE, (32 - 1) | ((128 - 1) << 16));
- dimv3_DI_Wr_reg_bits(DI_IF1_GEN_REG, 0, 0, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_DI_Wr_reg_bits(DI_IF2_GEN_REG, 0, 0, 1);
- /* disable ma,enable if0 to vpp,enable afbc to vpp */
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (Rd_reg_bits(VIU_MISC_CTRL0, 16, 4) != 0)
- dimv3_DI_Wr_reg_bits(VIU_MISC_CTRL0, 0, 16, 4);
- /* DI inp(current data) switch to memory */
- dimv3_DI_Wr_reg_bits(VIUB_MISC_CTRL0, 0, 16, 1);
- }
- dimv3_DI_Wr(DI_POST_CTRL, 0);
-}
-
-/*
- * old pulldown windows share below ctrl
- * registers
- * with new pulldown windows
- */
-void dimv3_film_mode_win_config(unsigned int width, unsigned int height)
-{
- unsigned int win0_start_x, win0_end_x, win0_start_y, win0_end_y;
- unsigned int win1_start_x, win1_end_x, win1_start_y, win1_end_y;
- unsigned int win2_start_x, win2_end_x, win2_start_y, win2_end_y;
- unsigned int win3_start_x, win3_end_x, win3_start_y, win3_end_y;
- unsigned int win4_start_x, win4_end_x, win4_start_y, win4_end_y;
-
- win0_start_x = 0;
- win1_start_x = 0;
- win2_start_x = 0;
- win3_start_x = 0;
- win4_start_x = 0;
- win0_end_x = width - 1;
- win1_end_x = width - 1;
- win2_end_x = width - 1;
- win3_end_x = width - 1;
- win4_end_x = width - 1;
- win0_start_y = 0;
- win1_start_y = (height >> 3); /* 1/8 */
- win0_end_y = win1_start_y - 1;
- win2_start_y = win1_start_y + (height >> 2); /* 1/4 */
- win1_end_y = win2_start_y - 1;
- win3_start_y = win2_start_y + (height >> 2); /* 1/4 */
- win2_end_y = win3_start_y - 1;
- win4_start_y = win3_start_y + (height >> 2); /* 1/4 */
- win3_end_y = win4_start_y - 1;
- win4_end_y = win4_start_y + (height >> 3) - 1; /* 1/8 */
-
- dimv3_RDMA_WR(DI_MC_REG0_X, (win0_start_x << 16) | win0_end_x);
- dimv3_RDMA_WR(DI_MC_REG0_Y, (win0_start_y << 16) | win0_end_y);
- dimv3_RDMA_WR(DI_MC_REG1_X, (win1_start_x << 16) | win1_end_x);
- dimv3_RDMA_WR(DI_MC_REG1_Y, (win1_start_y << 16) | win1_end_y);
- dimv3_RDMA_WR(DI_MC_REG2_X, (win2_start_x << 16) | win2_end_x);
- dimv3_RDMA_WR(DI_MC_REG2_Y, (win2_start_y << 16) | win2_end_y);
- dimv3_RDMA_WR(DI_MC_REG3_X, (win3_start_x << 16) | win3_end_x);
- dimv3_RDMA_WR(DI_MC_REG3_Y, (win3_start_y << 16) | win3_end_y);
- dimv3_RDMA_WR(DI_MC_REG4_X, (win4_start_x << 16) | win4_end_x);
- dimv3_RDMA_WR(DI_MC_REG4_Y, (win4_start_y << 16) | win4_end_y);
-}
-
-/*
- * old pulldown detction module, global field diff/num & frame
- * diff/numm and 5 window included
- */
-void dimv3_read_pulldown_info(unsigned int *glb_frm_mot_num,
- unsigned int *glb_fid_mot_num)
-{
- /*
- * addr will increase by 1 automatically
- */
- dimv3_DI_Wr(DI_INFO_ADDR, 1);
- *glb_frm_mot_num = (Rd(DI_INFO_DATA) & 0xffffff);
- dimv3_DI_Wr(DI_INFO_ADDR, 4);
- *glb_fid_mot_num = (Rd(DI_INFO_DATA) & 0xffffff);
-}
-
-#if 0 /*move from deinterlace_hw.c to pulldown_drv.c*/
-
-void read_new_pulldown_info(struct FlmModReg_t *pFMReg)
-{
- int i = 0;
-
- for (i = 0; i < 6; i++) {
- pFMReg->rROFrmDif02[i] = Rd(DIPD_RO_COMB_0 + i);
- pFMReg->rROFldDif01[i] = Rd(DIPD_RO_COMB_6 + i);
- }
-
- /* pFMReg->rROFrmDif02[0] = Rd(DIPD_RO_COMB_0); */
- /* pFMReg->rROFldDif01[0] = Rd(DIPD_RO_COMB_6); */
-
- for (i = 0; i < 9; i++)
- pFMReg->rROCmbInf[i] = Rd(DIPD_RO_COMB_12 + i);
-}
-
-#endif
-/*
- * DIPD_RO_COMB_0~DIPD_RO_COMB11 and DI_INFO_DATA
- * will be reset, so call this function after all
- * data have be fetched
- */
-void dimv3_pulldown_info_clear_g12a(void)
-{
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 1, 30, 1);
-}
-
-/*
- * manual reset contrd, cont2rd, mcinford mif
- * which fix after g12a
- */
-static void reset_pre_simple_rd_mif_g12(unsigned char madi_en,
- unsigned char mcdi_en)
-{
- unsigned int reg_val = 0;
-
- if (madi_en || mcdi_en) {
- dimv3_RDMA_WR_BITS(CONTRD_CTRL2, 1, 31, 1);
- dimv3_RDMA_WR_BITS(CONT2RD_CTRL2, 1, 31, 1);
- dimv3_RDMA_WR_BITS(MCINFRD_CTRL2, 1, 31, 1);
- reg_val = dimv3_RDMA_RD(DI_PRE_CTRL);
- if (madi_en)
- reg_val |= (1 << 25);
- if (mcdi_en)
- reg_val |= (1 << 10);
- /* enable cont rd&mcinfo rd, manual start */
- dimv3_RDMA_WR(DI_PRE_CTRL, reg_val);
- dimv3_RDMA_WR_BITS(CONTRD_CTRL2, 0, 31, 1);
- dimv3_RDMA_WR_BITS(CONT2RD_CTRL2, 0, 31, 1);
- dimv3_RDMA_WR_BITS(MCINFRD_CTRL2, 0, 31, 1);
- }
-}
-
-/*
- * frame reset for pre which have nothing with encoder
- * go field
- */
-void dimv3_pre_frame_reset_g12(unsigned char madi_en,
- unsigned char mcdi_en)
-{
- unsigned int reg_val = 0;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
- reset_pre_simple_rd_mif_g12(madi_en, mcdi_en);
- } else {
- reg_val = dimv3_RDMA_RD(DI_PRE_CTRL);
- if (madi_en)
- reg_val |= (1 << 25);
- if (mcdi_en)
- reg_val |= (1 << 10);
- dimv3_RDMA_WR(DI_PRE_CTRL, reg_val);
- }
- /* reset simple mif which framereset not cover */
- dimv3_RDMA_WR_BITS(CONTWR_CAN_SIZE, 1, 14, 1);
- dimv3_RDMA_WR_BITS(MTNWR_CAN_SIZE, 1, 14, 1);
- dimv3_RDMA_WR_BITS(MCVECWR_CAN_SIZE, 1, 14, 1);
- dimv3_RDMA_WR_BITS(MCINFWR_CAN_SIZE, 1, 14, 1);
-
- dimv3_RDMA_WR_BITS(CONTWR_CAN_SIZE, 0, 14, 1);
- dimv3_RDMA_WR_BITS(MTNWR_CAN_SIZE, 0, 14, 1);
- dimv3_RDMA_WR_BITS(MCVECWR_CAN_SIZE, 0, 14, 1);
- dimv3_RDMA_WR_BITS(MCINFWR_CAN_SIZE, 0, 14, 1);
-
- #ifdef OLD_PRE_GL
- reg_val = 0xc3200000 | dimp_get(eDI_MP_line_num_pre_frst);
- dimv3_RDMA_WR(DI_PRE_GL_CTRL, reg_val);
- reg_val = 0x83200000 | dimp_get(eDI_MP_line_num_pre_frst);
- dimv3_RDMA_WR(DI_PRE_GL_CTRL, reg_val);
- #else
- hprev3_gl_sw(true);
- #endif
-}
-
-/*2019-12-25 by feijun*/
-void hprev3_gl_sw(bool on)
-{
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
- return;
- if (on)
- dimv3_RDMA_WR(DI_PRE_GL_CTRL,
- 0x80200000 | dimp_get(eDI_MP_line_num_pre_frst));
- // 0x83200000 | dimp_get(eDI_MP_line_num_pre_frst));
- else
- dimv3_RDMA_WR(DI_PRE_GL_CTRL, 0xc0000000);
-
-}
-/*
- * frame + soft reset for the pre modules
- */
-void dimv3_pre_frame_reset(void)
-{
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 3, 30, 2);
-}
-
-/*
- * frame reset for post which have nothing with encoder
- * go field
- */
-void postv3_frame_reset_g12a(void)
-{
- unsigned int reg_val = 0;
-
- reg_val = (0xc0200000 | dimp_get(eDI_MP_line_num_post_frst));
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, reg_val);
- reg_val = (0x80200000 | dimp_get(eDI_MP_line_num_post_frst));
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, reg_val);
-}
-
-void dimv3_post_read_reverse_irq(bool reverse,
- unsigned char mc_pre_flag, bool mc_enable)
-{
- unsigned short flag_val = 1;
-
- mc_pre_flag = dimp_get(eDI_MP_if2_disable) ? 1 : mc_pre_flag;
- if (reverse) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF0_GEN_REG2, 3, 2, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MTNRD_CTRL1, 3, 4, 2);
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG2,
- 0xf, 2, 4);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_MTNRD_CTRL, 0xf, 17, 4);
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF1_GEN_REG2, 3, 2, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD2_IF0_GEN_REG2, 0xf, 2, 4);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF2_GEN_REG2, 3, 2, 2);
- if (mc_enable) {
- /* motion vector read reverse*/
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_X, 1, 30, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_Y, 1, 30, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- if (is_meson_txlx_cpu()) {
- dimv3_VSYNC_WR_MPEG_REG_BITS
- (MCDI_MC_CRTL,
- dimp_get(eDI_MP_pre_flag),
- 8, 2);
- flag_val =
- (dimp_get(eDI_MP_pre_flag) != 2) ?
- 0 : 1;
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS
- (MCDI_MC_CRTL,
- mc_pre_flag, 8, 2);
- flag_val = (mc_pre_flag != 2) ? 0 : 1;
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, flag_val, 11, 1);
- /* disable if2 for wave if1 case,
- *disable mc for pq issue
- */
- if (dimp_get(eDI_MP_if2_disable)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- DI_IF2_GEN_REG, 0, 0, 1);
- if (cpu_after_eq(
- MESON_CPU_MAJOR_ID_GXLX))
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, 0, 18, 1);
- }
- } else
- dimv3_VSYNC_WR_MPEG_REG_BITS
- (MCDI_MC_CRTL,
- mc_pre_flag, 8, 1);
- }
- } else {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF0_GEN_REG2, 0, 2, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MTNRD_CTRL1, 0, 4, 2);
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG2, 0, 2, 4);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_MTNRD_CTRL, 0, 17, 4);
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF1_GEN_REG2, 0, 2, 2);
- dimv3_VSYNC_WR_MPEG_REG_BITS(VD2_IF0_GEN_REG2, 0, 2, 4);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_IF2_GEN_REG2, 0, 2, 2);
- if (mc_enable) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_X, 0, 30, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_Y, 0, 30, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- if (is_meson_txlx_cpu()) {
- dimv3_VSYNC_WR_MPEG_REG_BITS
- (MCDI_MC_CRTL,
- dimp_get(eDI_MP_pre_flag),
- 8, 2);
- flag_val =
- (dimp_get(eDI_MP_pre_flag) != 2) ?
- 0 : 1;
- } else {
- dimv3_VSYNC_WR_MPEG_REG_BITS
- (MCDI_MC_CRTL,
- mc_pre_flag, 8, 2);
- flag_val = (mc_pre_flag != 2) ? 0 : 1;
- }
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, flag_val, 11, 1);
- /* disable if2 for wave if1 case */
- if (dimp_get(eDI_MP_if2_disable)) {
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, 0, 11, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- DI_IF2_GEN_REG, 0, 0, 1);
- if (cpu_after_eq(
- MESON_CPU_MAJOR_ID_GXLX))
- dimv3_VSYNC_WR_MPEG_REG_BITS(
- MCDI_MC_CRTL, 0, 18, 1);
- }
- } else
- dimv3_VSYNC_WR_MPEG_REG_BITS(MCDI_MC_CRTL,
- mc_pre_flag, 8, 1);
- }
- }
-}
-
-void dimv3_set_power_control(unsigned char enable)
-{
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_VIU_VD1,
- enable ? true : false);
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- enable ? true : false);
-}
-
-void dimv3_top_gate_control(bool top_en, bool mc_en)
-{
- if (top_en) {
- /* enable clkb input */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 0, 1);
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 15, 1);
- /* enable slow clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, mc_en ? 1 : 0, 10, 1);
- /* enable di arb */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 0, 2);
- } else {
- /* disable clkb input */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 0, 1);
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 15, 1);
- /* disable slow clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 10, 1);
- /* disable di arb */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 0, 2);
- }
-}
-
-void dimv3_pre_gate_control(bool gate, bool mc_enable)
-{
- if (gate) {
- /* enable ma pre clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 8, 1);
- /* enable mc clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 11, 1);
- /* enable pd clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 2, 2, 2);
- /* enable motion clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 2, 4, 2);
- /* enable deband clk gate freerun for hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 2, 6, 2);
- /* enable input mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 16, 2);
- /* enable mem mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 18, 2);
- /* enable chan2 mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 20, 2);
- /* enable nr wr mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 22, 2);
- /* enable mtn wr mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 2, 24, 2);
- if (mc_enable) {
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 0, 12, 2);
- else
- /* enable me clk always run vlsi issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 3, 12, 2);
- /*
- * enable mc pre mv(wr) mcinfo w/r
- * mif external gate
- */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1,
- 2, 26, 2);
- }
- /* cowork with auto gate to config reg */
- dimv3_DI_Wr_reg_bits(DI_PRE_CTRL, 3, 2, 2);
- } else {
- /* disable ma pre clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 8, 1);
- /* disable mc clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 11, 1);
- /* disable pd clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 1, 2, 2);
- /* disable motion clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 1, 4, 2);
- /* disable deband clk gate freerun for hw issue */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 1, 6, 2);
- /* disable input mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 16, 2);
- /* disable mem mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 18, 2);
- /* disable chan2 mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 20, 2);
- /* disable nr wr mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 22, 2);
- /* disable mtn wr mif external gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1, 1, 24, 2);
- if (mc_enable) {
- /* disable mc pre mv(wr) mcinfo
- * w/r mif external gate
- */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL1,
- 1, 26, 2);
- /* disable me clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL2, 1, 12, 2);
- }
- }
-}
-
-void dimv3_post_gate_control(bool gate)
-{
- if (gate) {
- /* enable clk post div */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 12, 1);
- /* enable post line buf/fifo/mux clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 1, 9, 1);
- /* enable blend1 clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 0, 0, 2);
- /* enable ei clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 0, 2, 2);
- /* enable ei_0 clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 0, 4, 2);
- } else {
- /* disable clk post div */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 12, 1);
- /* disable post line buf/fifo/mux clk */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL0, 0, 9, 1);
- /* disable blend1 clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 1, 0, 2);
- /* disable ei clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 1, 2, 2);
- /* disable ei_0 clk gate */
- dimv3_DI_Wr_reg_bits(VIUB_GCLK_CTRL3, 1, 4, 2);
- }
-}
-
-static void di_async_reset(void)/*2019-01-17 add for debug*/
-{
- /*wrmif async reset*/
- dimv3_RDMA_WR_BITS(VIUB_SW_RESET, 1, 14, 1);
- dimv3_RDMA_WR_BITS(VIUB_SW_RESET, 0, 14, 1);
-}
-
-static void di_pre_rst_frame(void)
-{
- dimv3_RDMA_WR(DI_PRE_CTRL, Rd(DI_PRE_CTRL) | (1 << 31));
-}
-
-static void di_pre_nr_enable(bool on)
-{
- if (on)
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 1, 0, 1);
- else
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 0, 0, 1);
-}
-
-void dimv3_pre_nr_wr_done_sel(bool on)
-{
- if (on) /*wait till response finish*/
- dimv3_RDMA_WR_BITS(DI_CANVAS_URGENT0, 1, 8, 1);
- else
- dimv3_RDMA_WR_BITS(DI_CANVAS_URGENT0, 0, 0, 1);
-}
-
-void dimv3_rst_protect(bool on)
-{
- if (on)
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, 1, 15, 1);
- else
- dimv3_RDMA_WR_BITS(DI_NRWR_Y, 0, 15, 1);
-}
-
-/*bit 10,12,16,18 [3:1]*/
-/*#define PRE_ID_MASK (0x5140e) */
-#define PRE_ID_MASK (0x51400)
-
-/*bit 8,10,14,16*/
-#define PRE_ID_MASK_TL1 (0x14500)
-
-static bool di_pre_idle(void)
-{
- bool ret = false;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if ((dimv3_RDMA_RD(DI_ARB_DBG_STAT_L1C1) &
- PRE_ID_MASK_TL1) == PRE_ID_MASK_TL1)
- ret = true;
- } else {
- if ((dimv3_RDMA_RD(DI_ARB_DBG_STAT_L1C1_OLD) &
- PRE_ID_MASK) == PRE_ID_MASK)
- ret = true;
- }
-
- return ret;
-}
-
-void dimv3_arb_sw(bool on)
-{
- int i;
- u32 REG_VPU_WRARB_REQEN_SLV_L1C1;
- u32 REG_VPU_RDARB_REQEN_SLV_L1C1;
- u32 REG_VPU_ARB_DBG_STAT_L1C1;
- u32 WRARB_onval;
- u32 WRARB_offval;
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1;
- REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1;
- REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1;
- if (on)
- WRARB_onval = 0x3f;
- else
- WRARB_offval = 0x3e;
- } else {
- REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1_OLD;
- REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1_OLD;
- REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1_OLD;
- if (on)
- WRARB_onval = 0x3f;
- else
- WRARB_offval = 0x2b;
- }
-
- if (on) {
- dimv3_RDMA_WR(REG_VPU_WRARB_REQEN_SLV_L1C1, WRARB_onval);
- dimv3_RDMA_WR(REG_VPU_RDARB_REQEN_SLV_L1C1, 0xffff);
- } else {
- /*close arb:*/
- dimv3_RDMA_WR(REG_VPU_WRARB_REQEN_SLV_L1C1, WRARB_offval);
- dimv3_RDMA_WR(REG_VPU_RDARB_REQEN_SLV_L1C1, 0xf1f1);
-
- di_pre_nr_enable(false); /*by Feijun*/
- /*check status*/
- if (!di_pre_idle()) {
- PR_ERR("%s:1:0x[%x]\n", __func__,
- dimv3_RDMA_RD(REG_VPU_ARB_DBG_STAT_L1C1));
- for (i = 0; i < 9; i++) {
- if (di_pre_idle())
- break;
- }
-
- if (!di_pre_idle()) {
- di_pre_rst_frame();
-
- for (i = 0; i < 9; i++) {
- if (di_pre_idle())
- break;
- }
- if (!di_pre_idle())
- PR_ERR("%s:2\n", __func__);
- }
- }
- if (di_pre_idle())
- di_async_reset();
- }
-}
-
-/* keep 0x1700' bit8 bit9 bit11 bit28 : 1*/
-
-void dbgv3_set_DI_PRE_CTRL(void)
-{
- unsigned int val;
- unsigned int mask, tmp;
-
- mask = 0x10000b00;
-
- val = Rd(DI_PRE_CTRL);
- tmp = (~mask) & val;
- tmp = tmp | 0x10000000;
-
- dimv3_DI_Wr(DI_PRE_CTRL, tmp);
-}
-
-/*************************************
- *VIUB_SW_RESET's bits:
- * [1][2]
- * [10][11]
- * [12][13][14]
- * [16][17]
- * [27]
- * [28][31]
- * all bits set 1 and then set 0
- *************************************/
-void div3_async_reset2(void)/*2019-04-05 add for debug*/
-{
- unsigned int mask, val1, val2, val3;
-
- mask = 0x98037c06;
- val1 = Rd(VIUB_SW_RESET);
- val2 = val1 | mask;
-
- dimv3_DI_Wr(VIUB_SW_RESET, val2);
- val3 = val2 & (~mask);
- dimv3_DI_Wr(VIUB_SW_RESET, val3);
- PR_INF("%s:0x%x,0x%x,0x%x\n", __func__, val1, val2, val3);
-}
-
-#define DI_NOP_REG1 (0x2fcb) /* BF2C */
-#define DI_NOP_REG2 (0x2fcd) /* BF34 */
-
-void hv3_dbg_reg_set(unsigned int val)
-{
- struct di_hpst_s *pst = get_hw_pst();
- enum eDI_PST_ST pst_st = pst->state;
- unsigned int valb;
-
- dimv3_DI_Wr(DI_NOP_REG1, val);
-
- valb = pst_st;
- if (pst->curr_ch)
- valb = pst_st | 0x80000000;
-
- dimv3_DI_Wr(DI_NOP_REG2, valb);
-}
-
-/*below for post */
-void postv3_mif_sw(bool on)
-{
- if (on) {
- dimv3_RDMA_WR_BITS(DI_IF0_GEN_REG, 1, 0, 1);
- /*by feijun 2018-11-19*/
- dimv3_RDMA_WR_BITS(DI_IF1_GEN_REG, 1, 0, 1);
- /*by feijun 2018-11-19*/
- dimv3_RDMA_WR_BITS(DI_IF2_GEN_REG, 1, 0, 1);
-
- dimv3_RDMA_WR_BITS(DI_POST_CTRL, 1, 7, 1);
- } else {
- dimv3_RDMA_WR_BITS(DI_IF0_GEN_REG, 0, 0, 1);
- /*by feijun 2018-11-19*/
- dimv3_RDMA_WR_BITS(DI_IF1_GEN_REG, 0, 0, 1);
- /*by feijun 2018-11-19*/
- dimv3_RDMA_WR_BITS(DI_IF2_GEN_REG, 0, 0, 1);
- dimv3_RDMA_WR_BITS(DI_POST_CTRL, 0, 7, 1);
- }
- dimv3_print("%s:%d\n", __func__, on);
-}
-
-void postv3_close_new(void)
-{
- unsigned int data32;
-
- postv3_mif_sw(false);
- data32 = Rd(DI_INTR_CTRL);
- /*intr_mode*/
- dimv3_DI_Wr(DI_INTR_CTRL, (data32 & 0xffff0004) | (3 << 30));
- div3_post_set_flow(1, eDI_POST_FLOW_STEP1_STOP); /*dbg a*/
-}
-
-/*asynchronous rest ,2018-11-19 from feijun: after set reset ,*/
-/*mif setting must set again*/
-void div3_post_reset(void)
-{
-#if 0
- 0x2001 = 0x48300;
- 0x2001 = 0x0;
- 0x2002 = 0x30c1;
- 0x2002 = 0x0;
-
- 0x2001 = 0x483c0;
- 0x2001 = 0x0;
- 0x2002 = 0x3001;
- 0x2002 = 0x0;
-#endif
- Wr(VIUB_SW_RESET, 0x483c0);
- Wr(VIUB_SW_RESET, 0x0);
-
- Wr(VIUB_SW_RESET0, 0x3001);
- Wr(VIUB_SW_RESET0, 0x0);
- PR_INF("%s\n", __func__);
-}
-
-void postv3_dbg_contr(void)
-{
- dimv3_RDMA_WR_BITS(DI_IF0_GEN_REG3, 1, 11, 1);
- dimv3_RDMA_WR_BITS(DI_IF1_GEN_REG3, 1, 11, 1);
- dimv3_RDMA_WR_BITS(DI_IF2_GEN_REG3, 1, 11, 1);
-}
-
-void div3_post_set_flow(unsigned int post_wr_en, enum eDI_POST_FLOW step)
-{
- unsigned int val;
-
- if (!post_wr_en)
- return;
-
- switch (step) {
- case eDI_POST_FLOW_STEP1_STOP:
- /*val = (0xc0200000 | line_num_post_frst);*/
- val = (0xc0000000 | 1);
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, val);
- break;
- case eDI_POST_FLOW_STEP2_START:
- /*val = (0x80200000 | line_num_post_frst);*/
- val = (0x80200000 | 1);
- dimv3_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, val);
- break;
- }
-}
-
-/*add 2019-04-25 for post crash debug*/
-void hpstv3_power_ctr(bool on)
-{
- if (on) {
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- true);
- dimv3_post_gate_control(true);
- dimhv3_enable_di_post_mif(GATE_AUTO);
- } else {
- dimhv3_enable_di_post_mif(GATE_OFF);
- dimv3_post_gate_control(false);
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- false);
- }
- //PR_INF("%s:%d\n", __func__, on);
-}
-
-void hpstv3_dbg_power_ctr_trig(unsigned int cmd)
-{
- if (cmd)
- hpstv3_power_ctr(true);
- else
- hpstv3_power_ctr(false);
-}
-
-void hpstv3_dbg_mem_pd_trig(unsigned int cmd)
-{
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- false);
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- true);
-/* pr_info("%s\n", __func__);*/
-}
-
-void hpstv3_mem_pd_sw(unsigned int on)
-{
- if (on)
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- true);
- else
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
- false);
-}
-
-void hpstv3_vd1_sw(unsigned int on)
-{
- if (on)
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_VIU_VD1,
- true);
- else
- extv3_ops.switch_vpu_mem_pd_vmod(VPU_VIU_VD1,
- false);
-}
-
-void hpstv3_dbg_trig_gate(unsigned int cmd)
-{
- dimv3_post_gate_control(false);
- dimv3_post_gate_control(true);
- PR_INF("%s\n", __func__);
-}
-
-void hpstv3_dbg_trig_mif(unsigned int cmd)
-{
- dimhv3_enable_di_post_mif(GATE_OFF);
- dimhv3_enable_di_post_mif(GATE_AUTO);
- PR_INF("%s\n", __func__);
-}
-
-/**/
-/*
- * enable/disable mc pre mif mcinfo&mv
- */
-static void mc_pre_mif_ctrl_g12(bool enable)
-{
- unsigned char mif_ctrl = 0;
-
- mif_ctrl = enable ? 1 : 0;
- /* enable mcinfo rd mif */
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, mif_ctrl, 10, 1);
- /* enable mv wr mif */
- dimv3_RDMA_WR_BITS(MCVECWR_CTRL, mif_ctrl, 12, 1);
- /* enable mcinfo wr mif */
- dimv3_RDMA_WR_BITS(MCINFWR_CTRL, mif_ctrl, 12, 1);
-}
-
-static void mc_pre_mif_ctrl(bool enable)
-{
- if (enable) {
- /* gate clk */
- dimv3_RDMA_WR_BITS(MCDI_MCVECWR_CTRL, 0, 9, 1);
- /* gate clk */
- dimv3_RDMA_WR_BITS(MCDI_MCINFOWR_CTRL, 0, 9, 1);
- /* mcinfo rd req en =1 */
- dimv3_RDMA_WR_BITS(MCDI_MCINFORD_CTRL, 1, 9, 1);
- /* mv wr req en =1 */
- dimv3_RDMA_WR_BITS(MCDI_MCVECWR_CTRL, 1, 12, 1);
- /* mcinfo wr req en =1 */
- dimv3_RDMA_WR_BITS(MCDI_MCINFOWR_CTRL, 1, 12, 1);
- } else {
- /* no gate clk */
- dimv3_RDMA_WR_BITS(MCDI_MCVECWR_CTRL, 1, 9, 1);
- /* no gate clk */
- dimv3_RDMA_WR_BITS(MCDI_MCINFOWR_CTRL, 1, 9, 1);
- /* mcvec wr req en =0 */
- dimv3_RDMA_WR_BITS(MCDI_MCVECWR_CTRL, 0, 12, 1);
- /* mcinfo wr req en =0 */
- dimv3_RDMA_WR_BITS(MCDI_MCINFOWR_CTRL, 0, 12, 1);
- /* mcinfo rd req en = 0 */
- dimv3_RDMA_WR_BITS(MCDI_MCINFORD_CTRL, 0, 9, 1);
- }
-}
-
-/*
- * enable/disable madi pre mif, mtn&cont
- */
-static void ma_pre_mif_ctrl_g12(bool enable)
-{
- if (enable) {
- /* enable cont wr mif */
- dimv3_RDMA_WR_BITS(CONTWR_CTRL, 1, 12, 1);
- /* enable mtn wr mif */
- dimv3_RDMA_WR_BITS(MTNWR_CTRL, 1, 12, 1);
- /* enable cont rd mif */
- } else {
- dimv3_RDMA_WR_BITS(MTNWR_CTRL, 0, 12, 1);
- dimv3_RDMA_WR_BITS(CONTWR_CTRL, 0, 12, 1);
- /* disable cont rd */
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 0, 25, 1);
- }
-}
-
-/*
- * use logic enable/disable replace mif
- */
-static void ma_pre_mif_ctrl(bool enable)
-{
- if (!enable) {
- /* mtn wr req en =0 */
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 0, 1, 1);
- /* cont wr req en =0 */
- dimv3_RDMA_WR_BITS(DI_MTN_1_CTRL1, 0, 31, 1);
- /* disable cont rd */
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 0, 25, 1);
- }
-}
-
-/*
- * enable/disable inp&chan2&mem&nrwr mif
- */
-static void di_pre_data_mif_ctrl(bool enable)
-{
- if (enable) {
- /* enable input mif*/
- dimv3_DI_Wr(DI_CHAN2_GEN_REG, Rd(DI_CHAN2_GEN_REG) | 0x1);
- dimv3_DI_Wr(DI_MEM_GEN_REG, Rd(DI_MEM_GEN_REG) | 0x1);
- #if 0
- if (Rd_reg_bits(VIU_MISC_CTRL1, 0, 1) == 1) {
- DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
- dimv3_RDMA_WR_BITS(VD2_AFBC_ENABLE, 1, 8, 1);
- } else {
- DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) | 0x1);
- dimv3_RDMA_WR_BITS(VD2_AFBC_ENABLE, 0, 8, 1);
- }
- #else
- if (afbc_is_used()) {
- dimv3_DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
- afbc_input_sw(true);
- } else {
- dimv3_DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) | 0x1);
- afbc_input_sw(false);
- }
- #endif
- /* nrwr no clk gate en=0 */
- /*dim_RDMA_WR_BITS(DI_NRWR_CTRL, 0, 24, 1);*/
- } else {
- /* nrwr no clk gate en=1 */
- /*dim_RDMA_WR_BITS(DI_NRWR_CTRL, 1, 24, 1);*/
- /* nr wr req en =0 */
- dimv3_RDMA_WR_BITS(DI_PRE_CTRL, 0, 0, 1);
- /* disable input mif*/
- dimv3_DI_Wr(DI_CHAN2_GEN_REG, Rd(DI_CHAN2_GEN_REG) & ~0x1);
- dimv3_DI_Wr(DI_MEM_GEN_REG, Rd(DI_MEM_GEN_REG) & ~0x1);
- dimv3_DI_Wr(DI_INP_GEN_REG, Rd(DI_INP_GEN_REG) & ~0x1);
- #if 0
- /* disable AFBC input */
- if (Rd_reg_bits(VIU_MISC_CTRL1, 0, 1) == 1)
- dimv3_RDMA_WR_BITS(VD2_AFBC_ENABLE, 0, 8, 1);
- #else
- /* disable AFBC input */
- if (afbc_is_used())
- afbc_input_sw(false);
-
- #endif
- }
-}
-
-static atomic_t mif_flag;
-void dimhv3_enable_di_pre_mif(bool en, bool mc_enable)
-{
- if (atomic_read(&mif_flag)) {
- PR_ERR("%s:%d,%d:no set\n", __func__, en, mc_enable);
- return;
- }
- if (dimp_get(eDI_MP_pre_mif_gate) && !en) {
- PR_ERR("%s:%d,%d: gate not map\n", __func__, en, mc_enable);
- return;
- }
- atomic_set(&mif_flag, 1);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
- if (mc_enable)
- mc_pre_mif_ctrl_g12(en);
- ma_pre_mif_ctrl_g12(en);
- } else {
- if (mc_enable)
- mc_pre_mif_ctrl(en);
- ma_pre_mif_ctrl(en);
- }
- di_pre_data_mif_ctrl(en);
- atomic_set(&mif_flag, 0);
-}
-
-void dimhv3_combing_pd22_window_config(unsigned int width, unsigned int height)
-{
- unsigned short y1 = 39, y2 = height - 41;
-
- if (height >= 540) {
- y1 = 79;
- y2 = height - 81;
- }
- if (!cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX)) {
- dimv3_DI_Wr_reg_bits(DECOMB_WIND00, 0, 16, 13);/* dcomb x0 */
- /* dcomb x1 */
- dimv3_DI_Wr_reg_bits(DECOMB_WIND00, (width - 1), 0, 13);
- dimv3_DI_Wr_reg_bits(DECOMB_WIND01, 0, 16, 13);/* dcomb y0 */
- dimv3_DI_Wr_reg_bits(DECOMB_WIND01, y1, 0, 13);/* dcomb y1 */
- dimv3_DI_Wr_reg_bits(DECOMB_WIND10, 0, 16, 13);/* dcomb x0 */
- /* dcomb x1 */
- dimv3_DI_Wr_reg_bits(DECOMB_WIND10, (width - 1), 0, 13);
- /* dcomb y0 */
- dimv3_DI_Wr_reg_bits(DECOMB_WIND11, (y1 + 1), 16, 13);
- dimv3_DI_Wr_reg_bits(DECOMB_WIND11, y2, 0, 13);/* dcomb y1 */
- }
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND0_X, 0, 0, 13);/* pd22 x0 */
- /* pd22 x1 */
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND0_X, (width - 1), 16, 13);
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND0_Y, 0, 0, 13);/* pd22 y0 */
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND0_Y, y1, 16, 13);/* pd y1 */
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND1_X, 0, 0, 13);/* pd x0 */
- /* pd x1 */
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND1_X, (width - 1), 16, 13);
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND1_Y, (y1 + 1), 0, 13);/* pd y0 */
- dimv3_DI_Wr_reg_bits(MCDI_PD_22_CHK_WND1_Y, y2, 16, 13);/* pd y2 */
-}
-
-void dimhv3_pulldown_vof_win_config(struct pulldown_detected_s *wins)
-{
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG0_Y,
- wins->regs[0].win_vs, 17, 12);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG0_Y,
- wins->regs[0].win_ve, 1, 12);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG1_Y,
- wins->regs[1].win_vs, 17, 12);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG1_Y,
- wins->regs[1].win_ve, 1, 12);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG2_Y,
- wins->regs[2].win_vs, 17, 12);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG2_Y,
- wins->regs[2].win_ve, 1, 12);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG3_Y,
- wins->regs[3].win_vs, 17, 12);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_REG3_Y,
- wins->regs[3].win_ve, 1, 12);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- (wins->regs[0].win_ve > wins->regs[0].win_vs)
- ? 1 : 0, 16, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- wins->regs[0].blend_mode, 8, 2);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- (wins->regs[1].win_ve > wins->regs[1].win_vs)
- ? 1 : 0, 17, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- wins->regs[1].blend_mode, 10, 2);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- (wins->regs[2].win_ve > wins->regs[2].win_vs)
- ? 1 : 0, 18, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- wins->regs[2].blend_mode, 12, 2);
-
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- (wins->regs[3].win_ve > wins->regs[3].win_vs)
- ? 1 : 0, 19, 1);
- dimv3_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
- wins->regs[3].blend_mode, 14, 2);
-}
-
-void dimhv3_load_regs(struct di_pq_parm_s *di_pq_ptr)
-{
- unsigned int i = 0, j = 0, addr = 0, value = 0, mask = 0, len;
- unsigned int table_name = 0, nr_table = 0;
- bool ctrl_reg_flag = false;
- struct am_reg_s *regs_p = NULL;
-
- if (dimp_get(eDI_MP_pq_load_dbg) == 1)
- return;
- if (dimp_get(eDI_MP_pq_load_dbg) == 2)
- pr_info("[DI]%s hw load 0x%x pq table len %u.\n",
- __func__, di_pq_ptr->pq_parm.table_name,
- di_pq_ptr->pq_parm.table_len);
- if (PTR_RET(di_pq_ptr->regs)) {
- PR_ERR("[DI] table ptr error.\n");
- return;
- }
- pr_info("[DI]%s hw load 0x%x pq table len %u.\n",
- __func__, di_pq_ptr->pq_parm.table_name,
- di_pq_ptr->pq_parm.table_len);
- nr_table = TABLE_NAME_NR | TABLE_NAME_DEBLOCK | TABLE_NAME_DEMOSQUITO;
- regs_p = (struct am_reg_s *)di_pq_ptr->regs;
- len = di_pq_ptr->pq_parm.table_len;
- table_name = di_pq_ptr->pq_parm.table_name;
- for (i = 0; i < len; i++) {
- ctrl_reg_flag = false;
- addr = regs_p->addr;
- value = regs_p->val;
- mask = regs_p->mask;
- if (dimp_get(eDI_MP_pq_load_dbg) == 2)
- pr_info("[%u][0x%x] = [0x%x]&[0x%x]\n",
- i, addr, value, mask);
-
- for (j = 0; j < SKIP_CTRE_NUM; j++) {
- if (addr == ctrl_regs[j])
- break;
- }
-
- if (regs_p->mask != 0xffffffff) {
- value = ((Rd(addr) & (~(mask))) |
- (value & mask));
- }
- regs_p++;
- if (j < SKIP_CTRE_NUM) {
- if (dimp_get(eDI_MP_pq_load_dbg) == 3)
- pr_info("%s skip [0x%x]=[0x%x].\n",
- __func__, addr, value);
- continue;
- }
- if (table_name & nr_table)
- ctrl_reg_flag
- = get_ops_nr()->set_nr_ctrl_reg_table(addr, value);
-
- if (!ctrl_reg_flag)
- dimv3_DI_Wr(addr, value);
- if (dimp_get(eDI_MP_pq_load_dbg) == 2)
- pr_info("[%u][0x%x] = [0x%x] %s\n", i, addr,
- value, Rd(addr) != value ? "fail" : "success");
- }
-}
-
-/*note:*/
-/* function: patch for txl for progressive source */
-/* 480p/576p/720p from hdmi will timeout */
-/* prog_flg: in: 1:progressive; */
-/* cnt: in: di_pre_stru.field_count_for_cont*/
-/* mc_en: in: mcpre_en*/
-void dimhv3_txl_patch_prog(int prog_flg, unsigned int cnt, bool mc_en)
-{
- unsigned int di_mtn_1_ctrl1 = 0; /*ary add tmp*/
-
- if (!prog_flg || !is_meson_txl_cpu())
- return;
-
- /*printk("prog patch\n");*/
- if (cnt >= 3) {
- di_mtn_1_ctrl1 |= 1 << 29;/* enable txt */
-
- if (mc_en) {
- dimv3_RDMA_WR(DI_MTN_CTRL1,
- (0xffffcfff & dimv3_RDMA_RD(DI_MTN_CTRL1)));
-
- /* enable me(mc di) */
- if (cnt == 4) {
- di_mtn_1_ctrl1 &= (~(1 << 30));
- /* enable contp2rd and contprd */
- dimv3_RDMA_WR(MCDI_MOTINEN, 1 << 1 | 1);
- }
- if (cnt == 5)
- dimv3_RDMA_WR(MCDI_CTRL_MODE, 0x1bfff7ff);
- }
- } else {
- if (mc_en) {
- /* txtdet_en mode */
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 0, 1, 1);
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 1, 9, 1);
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 1, 16, 1);
- dimv3_RDMA_WR_BITS(MCDI_CTRL_MODE, 0, 28, 1);
- dimv3_RDMA_WR(MCDI_MOTINEN, 0);
- dimv3_RDMA_WR(DI_MTN_CTRL1,
- (0xffffcfff & dimv3_RDMA_RD(DI_MTN_CTRL1)));
- /* disable me(mc di) */
- }
- dimv3_RDMA_WR(DNR_CTRL, 0);
- }
- dimv3_RDMA_WR(DI_MTN_1_CTRL1, di_mtn_1_ctrl1);
-}
-
-#ifdef DIM_OUT_NV21
-/**********************************************************
- * rebuild setting
- **********************************************************/
-static const unsigned int reg_mifs[EDI_MIFS_NUB][EDI_MIFS_REG_NUB] = {
- { /* pre nr mif */
- DI_NRWR_X,
- DI_NRWR_Y,
- DI_NRWR_CTRL, /*write only once*/
- },
- { /* post wr mif */
- DI_DIWR_X,
- DI_DIWR_Y,
- DI_DIWR_CTRL,
- },
-};
-
-static void dimh_wrmif_switch_buf(struct DI_SIM_MIF_s *cfg_mif,
- const struct reg_acc *ops,
- struct cfg_mifset_s *cfgs,
- enum EDI_MIFSM mifsel)
-{
- const unsigned int *reg;
- unsigned int ctr;
-
- reg = ®_mifs[mifsel][0];
- ctr = 0;
-
- ctr |= ((2 << 26) |
- (cfg_mif->urgent << 16) | /*urgent*/
- /* swap cbcrworking in rgb mode =2: swap cbcr*/
- (cfg_mif->cbcr_swap << 17) |
- /*vcon working in rgb mode =2:*/
- (0 << 18) |
- /* hconv. output even pixel*/
- (0 << 20) |
- /*rgb mode =0, 422 YCBCR to one canvas.*/
- (0 << 22) |
- (0 << 24) |
- (cfg_mif->reg_swap << 30));
-
- if (cfg_mif->set_separate_en == 0) {
- ctr |= (cfg_mif->canvas_num & 0xff); /* canvas index.*/
- } else if (cfg_mif->set_separate_en == 2) {
- ctr |= (cfg_mif->canvas_num & 0x00ff) | /* Y canvas index.*/
- /*CBCR canvas index*/
- (cfg_mif->canvas_num & 0xff00) |
- /*vcon working in rgb mode =2: 3 : output all.*/
- (((cfg_mif->video_mode == 0) ? 0 : 3) << 18) |
- /* hconv. output even pixel */
- (((cfg_mif->video_mode == 2) ? 3 : 0) << 20) |
- (2 << 22); /*enable auto clock gating in nrwr_mif.*/
- }
- dimv3_print("nv21:sw:ctr[0x%x]\n", ctr);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) &&
- ((cfg_mif->bit_mode & 0x3) == 0x3))
- ctr = ctr | (3 << 22);
-
- ops->wr(reg[EDI_MIFS_CTRL], ctr);
-}
-
-static void dimh_wrmif_set(struct DI_SIM_MIF_s *cfg_mif,
- const struct reg_acc *ops,
- struct cfg_mifset_s *cfgs,
- enum EDI_MIFSM mifsel)
-{
- const unsigned int *reg;
- unsigned int ctr;
-
- reg = ®_mifs[mifsel][0];
-
- //dimh_enable_di_post_2
- /*set all*/
-
- if (!cfg_mif->ddr_en)
- return;
-
- ops->wr(reg[EDI_MIFS_X],
- (cfg_mif->l_endian << 31) |
- (cfg_mif->start_x << 16) | /* [29:16]*/
- (cfg_mif->end_x)); /* [13:0] */
- ops->wr(reg[EDI_MIFS_Y],
- (3 << 30) |
- (cfg_mif->start_y << 16) |
- /* wr ext en from gxtvbb */
- (1 << 15) |
- ((cfg_mif->bit_mode & 0x1) << 14) |
- (cfg_mif->end_y));
-
- /* MIFS_CTRL */
- ctr = 0;
- ctr |= (2 << 26) |
- (cfg_mif->urgent << 16) | /*urgent*/
- /* swap cbcrworking in rgb mode =2: swap cbcr */
- (cfg_mif->cbcr_swap << 17) |
- (0 << 18) | /*vcon working in rgb mode =2:*/
- (0 << 20) | /* hconv. output even pixel*/
- /*rgb mode =0, 422 YCBCR to one canvas.*/
- (0 << 22) |
- (0 << 24) |
- (cfg_mif->reg_swap << 30);
- if (cfg_mif->set_separate_en == 0) {
- ctr |= (cfg_mif->canvas_num & 0xff); /* canvas index.*/
- } else if (cfg_mif->set_separate_en == 2) {
- ctr |= (cfg_mif->canvas_num & 0x00ff) | /* Y canvas index.*/
- /*CBCR canvas index*/
- (cfg_mif->canvas_num & 0xff00) |
- /* vcon working in rgb mode =2: 3 : output all.*/
- (((cfg_mif->video_mode == 0) ? 0 : 3) << 18) |
- /* hconv. output even pixel */
- (((cfg_mif->video_mode == 2) ? 3 : 0) << 20) |
- (2 << 22); //enable auto clock gating in nrwr_mif.
- }
- dimv3_print("nv21:set:ctr[0x%x]\n", ctr);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL) &&
- ((cfg_mif->bit_mode & 0x3) == 0x3))
- ctr = ctr | (3 << 22);
-
- ops->wr(reg[EDI_MIFS_CTRL], ctr);
-
- dimv3_print("bit_mode[%d] 0x%x=[0x%x]\n",
- cfg_mif->bit_mode, reg[EDI_MIFS_Y],
- dimv3_RDMA_RD(reg[EDI_MIFS_Y]));
- dimv3_print("0x%x=[0x%x]\n", reg[EDI_MIFS_CTRL],
- dimv3_RDMA_RD(reg[EDI_MIFS_CTRL]));
-}
-#define DIM_VSYNC_WR_MPEG_REG dimv3_VSYNC_WR_MPEG_REG
-#define DIM_VSC_WR_MPG_BT dimv3_VSYNC_WR_MPEG_REG_BITS
-
-const struct reg_acc di_pst_regsetv3 = {
- .wr = DIM_VSYNC_WR_MPEG_REG,
- .rd = NULL,
- .bwr = DIM_VSC_WR_MPG_BT,
- .brd = NULL,
-};
-
-static void dimh_pst_mif_set(struct DI_SIM_MIF_s *cfg_mif,
- unsigned int urgent,
- unsigned int ddr_en)
-{
- //struct cfg_mifset_s mifset;
-
- //cfg_mif->ddr_en = ddr_en;
- cfg_mif->urgent = urgent;
- dimh_wrmif_set(cfg_mif, &di_pst_regsetv3, NULL, EDI_MIFSM_WR);
-}
-
-void dimhv3_pst_mif_update(struct DI_SIM_MIF_s *cfg_mif,
- unsigned int urgent,
- unsigned int ddr_en)
-{
- struct cfg_mifset_s mifset;
-
- mifset.ddr_en = ddr_en;
- mifset.urgent = urgent;
- mifset.cbcr_swap = cfg_mif->cbcr_swap;
- mifset.l_endian = cfg_mif->l_endian;
- mifset.reg_swap = cfg_mif->reg_swap;
- dimh_wrmif_switch_buf(cfg_mif, &di_pst_regsetv3, &mifset, EDI_MIFSM_WR);
-}
-#endif
-
-/**********************************************************/
-void dimv3_init_setting_once(void)
-{
- if (di_get_flg_hw_int())
- return;
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- dimv3_wr_cue_int();
-
- dimv3_hw_init_reg();
-
- di_set_flg_hw_int(true);
-}
-
-int dimv3_seq_file_module_para_hw(struct seq_file *seq)
-{
- seq_puts(seq, "hw---------------\n");
-#if 0
- seq_printf(seq, "%-15s:%d\n", "pq_load_dbg", pq_load_dbg);
- seq_printf(seq, "%-15s:%d\n", "lmv_lock_win_en", lmv_lock_win_en);
- seq_printf(seq, "%-15s:%d\n", "lmv_dist", lmv_dist);
- seq_printf(seq, "%-15s:%d\n", "pr_mcinfo_cnt", pr_mcinfo_cnt);
- seq_printf(seq, "%-15s:%d\n", "offset_lmv", offset_lmv);
- seq_printf(seq, "%-15s:%d\n", "post_ctrl", post_ctrl);
- seq_printf(seq, "%-15s:%d\n", "if2_disable", if2_disable);
- seq_printf(seq, "%-15s:%d\n", "pre_flag", pre_flag);
-
- seq_printf(seq, "%-15s:%d\n", "pre_mif_gate", pre_mif_gate);
- seq_printf(seq, "%-15s:%d\n", "pre_urgent", pre_urgent);
- seq_printf(seq, "%-15s:%d\n", "pre_hold_line", pre_hold_line);
- seq_printf(seq, "%-15s:%d\n", "pre_ctrl, uint", pre_ctrl);
- seq_printf(seq, "%-15s:%d\n", "line_num_post_frst",
- line_num_post_frst);
- seq_printf(seq, "%-15s:%d\n", "line_num_pre_frst", line_num_pre_frst);
- seq_printf(seq, "%-15s:%d\n", "pd22_flg_calc_en", pd22_flg_calc_en);
-
- /***********************/
- seq_printf(seq, "%-15s:%d\n", "mcen_mode", mcen_mode);
- seq_printf(seq, "%-15s:%d\n", "mcuv_en", mcuv_en);
- seq_printf(seq, "%-15s:%d\n", "mcdebug_mode", mcdebug_mode);
- seq_printf(seq, "%-15s:%d\n", "pldn_ctrl_rflsh", pldn_ctrl_rflsh);
-#endif
- return 0;
-}
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/deinterlace_hw.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _DI_HW_H
-#define _DI_HW_H
-#include <linux/amlogic/media/amvecm/amvecm.h>
-
-#include "../deinterlace/di_pqa.h"
-
-/* if post size < 80, filter of ei can't work */
-#define MIN_POST_WIDTH 80
-#define MIN_BLEND_WIDTH 27
-
-#define SKIP_CTRE_NUM 13
-/*move from deinterlace.c*/
-enum eAFBC_REG {
- eAFBC_ENABLE,
- eAFBC_MODE,
- eAFBC_SIZE_IN,
- eAFBC_DEC_DEF_COLOR,
- eAFBC_CONV_CTRL,
- eAFBC_LBUF_DEPTH,
- eAFBC_HEAD_BADDR,
- eAFBC_BODY_BADDR,
- eAFBC_SIZE_OUT,
- eAFBC_OUT_YSCOPE,
- eAFBC_STAT,
- eAFBC_VD_CFMT_CTRL,
- eAFBC_VD_CFMT_W,
- eAFBC_MIF_HOR_SCOPE,
- eAFBC_MIF_VER_SCOPE,
- eAFBC_PIXEL_HOR_SCOPE,
- eAFBC_PIXEL_VER_SCOPE,
- eAFBC_VD_CFMT_H,
-};
-
-enum eAFBC_DEC {
- eAFBC_DEC0,
- eAFBC_DEC1,
-};
-
-#define AFBC_REG_INDEX_NUB (18)
-#define AFBC_DEC_NUB (2)
-
-struct DI_MIF_s {
- unsigned short luma_x_start0;
- unsigned short luma_x_end0;
- unsigned short luma_y_start0;
- unsigned short luma_y_end0;
- unsigned short chroma_x_start0;
- unsigned short chroma_x_end0;
- unsigned short chroma_y_start0;
- unsigned short chroma_y_end0;
- unsigned int nocompress;
- unsigned set_separate_en:2;
- unsigned src_field_mode:1;
- unsigned src_prog:1;
- unsigned video_mode:1;
- unsigned output_field_num:1;
- unsigned bit_mode:2;
- /*
- * unsigned burst_size_y:2; set 3 as default
- * unsigned burst_size_cb:2;set 1 as default
- * unsigned burst_size_cr:2;set 1 as default
- */
- unsigned canvas0_addr0:8;
- unsigned canvas0_addr1:8;
- unsigned canvas0_addr2:8;
-};
-
-struct DI_SIM_MIF_s {
- unsigned short start_x;
- unsigned short end_x;
- unsigned short start_y;
- unsigned short end_y;
- unsigned short canvas_num;
- unsigned int bit_mode :4;
- unsigned int set_separate_en :4; /*ary add below is only for wr buf*/
-
- unsigned int video_mode :4;
- unsigned int ddr_en :1;
- unsigned int urgent :1;
- unsigned int l_endian :1;
- unsigned int cbcr_swap :1;
- unsigned int reg_swap :1; /* 64bits swap */
-
- unsigned int reserved :15;
-};
-
-struct DI_MC_MIF_s {
- unsigned short start_x;
- unsigned short start_y;
- unsigned short end_y;
- unsigned short size_x;
- unsigned short size_y;
- unsigned short canvas_num;
- unsigned short blend_en;
- unsigned short vecrd_offset;
-};
-
-enum gate_mode_e {
- GATE_AUTO,
- GATE_ON,
- GATE_OFF,
-};
-
-struct mcinfo_lmv_s {
- unsigned char lock_flag;
- char lmv;
- unsigned short lock_cnt;
-};
-
-struct di_pq_parm_s {
- struct am_pq_parm_s pq_parm;
- struct am_reg_s *regs;
- struct list_head list;
-};
-
-/***********************************************
- * setting rebuild
- * by ary
- ***********************************************/
-#ifdef MARK_HIS
-enum EDI_MIFSM {
- EDI_MIFSM_NR,
- EDI_MIFSM_WR,
-};
-#endif
-
-enum EDI_MIFSR {
- EDI_MIFS_X,
- EDI_MIFS_Y,
- EDI_MIFS_CTRL,
-};
-
-/*keep same as EDI_MIFSM*/
-#define EDI_MIFS_NUB (2)
-
-/*keep same as EDI_MIFSR*/
-#define EDI_MIFS_REG_NUB (3)
-
-struct cfg_mifset_s {
- bool ddr_en;
- bool urgent;
- bool l_endian; /* little_endian */
- bool cbcr_swap;
- bool reg_swap; /* 64bits swap */
- //unsigned int bit_mode;
-};
-
-/**********************************************/
-void dimv3_read_pulldown_info(unsigned int *glb_frm_mot_num,
- unsigned int *glb_fid_mot_num);
-
-#if 0
-
-void read_new_pulldown_info(struct FlmModReg_t *pFMRegp);
-#endif
-void dimv3_pulldown_info_clear_g12a(void);
-void dimhv3_combing_pd22_window_config(unsigned int width, unsigned int height);
-void dimhv3_hw_init(bool pulldown_en, bool mc_enable);
-void dimhv3_hw_uninit(void);
-void dimhv3_enable_di_pre_aml(struct DI_MIF_s *di_inp_mif,
- struct DI_MIF_s *di_mem_mif,
- struct DI_MIF_s *di_chan2_mif,
- struct DI_SIM_MIF_s *di_nrwr_mif,
- struct DI_SIM_MIF_s *di_mtnwr_mif,
- struct DI_SIM_MIF_s *di_contp2rd_mif,
- struct DI_SIM_MIF_s *di_contprd_mif,
- struct DI_SIM_MIF_s *di_contwr_mif,
- unsigned char madi_en,
- unsigned char pre_field_num,
- unsigned char pre_vdin_link);
-void dimhv3_enable_afbc_input(struct vframe_s *vf);
-
-void dimhv3_mc_pre_mv_irq(void);
-void dimhv3_enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
- struct DI_MC_MIF_s *di_mcinfowr_mif,
- struct DI_MC_MIF_s *di_mcvecwr_mif,
- unsigned char mcdi_en);
-void dimhv3_enable_mc_di_pre_g12(struct DI_MC_MIF_s *di_mcinford_mif,
- struct DI_MC_MIF_s *di_mcinfowr_mif,
- struct DI_MC_MIF_s *di_mcvecwr_mif,
- unsigned char mcdi_en);
-
-void dimhv3_enable_mc_di_post(struct DI_MC_MIF_s *di_mcvecrd_mif,
- int urgent, bool reverse, int invert_mv);
-void dimhv3_enable_mc_di_post_g12(struct DI_MC_MIF_s *di_mcvecrd_mif,
- int urgent, bool reverse, int invert_mv);
-
-void dimhv3_disable_post_deinterlace_2(void);
-void dimhv3_initial_di_post_2(int hsize_post, int vsize_post,
- int hold_line, bool write_en);
-void dimhv3_enable_di_post_2(
- struct DI_MIF_s *di_buf0_mif,
- struct DI_MIF_s *di_buf1_mif,
- struct DI_MIF_s *di_buf2_mif,
- struct DI_SIM_MIF_s *di_diwr_mif,
- struct DI_SIM_MIF_s *di_mtnprd_mif,
- int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
- int di_vpp_en, int di_ddr_en,
- int post_field_num, int hold_line, int urgent,
- int invert_mv, int vskip_cnt
-);
-void dimhv3_post_switch_buffer(
- struct DI_MIF_s *di_buf0_mif,
- struct DI_MIF_s *di_buf1_mif,
- struct DI_MIF_s *di_buf2_mif,
- struct DI_SIM_MIF_s *di_diwr_mif,
- struct DI_SIM_MIF_s *di_mtnprd_mif,
- struct DI_MC_MIF_s *di_mcvecrd_mif,
- int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
- int di_vpp_en, int di_ddr_en,
- int post_field_num, int hold_line, int urgent,
- int invert_mv, bool pd_en, bool mc_enable,
- int vskip_cnt
-);
-void dimv3_post_read_reverse_irq(bool reverse,
- unsigned char mc_pre_flag, bool mc_enable);
-void dimv3_top_gate_control(bool top_en, bool mc_en);
-void dimv3_pre_gate_control(bool enable, bool mc_enable);
-void dimv3_post_gate_control(bool gate);
-void dimv3_set_power_control(unsigned char enable);
-void dimv3_hw_disable(bool mc_enable);
-void dimhv3_enable_di_pre_mif(bool enable, bool mc_enable);
-void dimhv3_enable_di_post_mif(enum gate_mode_e mode);
-
-void dimhv3_combing_pd22_window_config(unsigned int width, unsigned int height);
-void dimhv3_calc_lmv_init(void);
-void dimhv3_calc_lmv_base_mcinfo(unsigned int vf_height,
- unsigned short *mcinfo_adr_v,
- unsigned int mcinfo_size);
-void dimhv3_init_field_mode(unsigned short height);
-void dimv3_film_mode_win_config(unsigned int width, unsigned int height);
-void dimhv3_pulldown_vof_win_config(struct pulldown_detected_s *wins);
-void dimhv3_load_regs(struct di_pq_parm_s *di_pq_ptr);
-void dimv3_pre_frame_reset_g12(unsigned char madi_en, unsigned char mcdi_en);
-void dimv3_pre_frame_reset(void);
-void dimhv3_interrupt_ctrl(unsigned char ma_en,
- unsigned char det3d_en, unsigned char nrds_en,
- unsigned char post_wr, unsigned char mc_en);
-void dimhv3_txl_patch_prog(int prog_flg, unsigned int cnt, bool mc_en);
-bool dimhv3_afbc_is_supported(void);
-
-void dimhv3_afbc_reg_sw(bool on);
-
-void dumpv3_vd2_afbc(void);
-
-int dimv3_print(const char *fmt, ...);
-
-#define DI_MC_SW_OTHER (1 << 0)
-#define DI_MC_SW_REG (1 << 1)
-/*#define DI_MC_SW_POST (1 << 2)*/
-#define DI_MC_SW_IC (1 << 2)
-
-#define DI_MC_SW_ON_MASK (DI_MC_SW_REG | DI_MC_SW_OTHER | DI_MC_SW_IC)
-
-void dimhv3_patch_post_update_mc(void);
-void dimhv3_patch_post_update_mc_sw(unsigned int cmd, bool on);
-
-void dimv3_rst_protect(bool on);
-void dimv3_pre_nr_wr_done_sel(bool on);
-void dimv3_arb_sw(bool on);
-void dbgv3_set_DI_PRE_CTRL(void);
-void div3_async_reset2(void); /*2019-04-05 add for debug*/
-
-enum DI_HW_POST_CTRL {
- DI_HW_POST_CTRL_INIT,
- DI_HW_POST_CTRL_RESET,
-};
-
-void dimhv3_post_ctrl(enum DI_HW_POST_CTRL contr,
- unsigned int post_write_en);
-void dimhv3_int_ctr(unsigned int set_mod, unsigned char ma_en,
- unsigned char det3d_en, unsigned char nrds_en,
- unsigned char post_wr, unsigned char mc_en);
-
-void hv3_dbg_reg_set(unsigned int val);
-
-enum eDI_POST_FLOW {
- eDI_POST_FLOW_STEP1_STOP,
- eDI_POST_FLOW_STEP2_START,
-/* eDI_POST_FLOW_STEP3_RESET_INT,*/
-};
-
-void div3_post_set_flow(unsigned int post_wr_en, enum eDI_POST_FLOW step);
-void postv3_mif_sw(bool on);
-void postv3_dbg_contr(void);
-void postv3_close_new(void);
-void div3_post_reset(void);
-void dimhv3_pst_trig_resize(void);
-
-void hpstv3_power_ctr(bool on);
-void hpstv3_dbg_power_ctr_trig(unsigned int cmd);
-void hpstv3_dbg_mem_pd_trig(unsigned int cmd);
-void hpstv3_dbg_trig_gate(unsigned int cmd);
-void hpstv3_dbg_trig_mif(unsigned int cmd);
-void hpstv3_mem_pd_sw(unsigned int on);
-void hpstv3_vd1_sw(unsigned int on);
-void hprev3_gl_sw(bool on);
-
-void dimv3_init_setting_once(void);
-void dimv3_hw_init_reg(void);
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_api.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/amlogic/media/vpu/vpu.h>
-
-#include "di_api.h"
-/**********************************
- * DI api is used for other module
- *********************************/
-static const struct di_ext_ops di_ext = {
- .di_post_reg_rd = l_DIV3_POST_REG_RD,
- .di_post_wr_reg_bits = l_DIV3_POST_WR_REG_BITS,
-};
-
-void dimv3_attach_to_local(void)
-{
- dil_attach_ext_api(&di_ext);
-}
-
-bool dimv3_attach_ext_api(struct di_ext_ops *di_api)
-{
- #if 1
- if (!di_api)
- return false;
-
- memcpy(di_api, &di_ext, sizeof(struct di_ext_ops));
- #else
- di_api = &di_ext;
- #endif
- return true;
-}
-
-/*EXPORT_SYMBOL(dimv3_attach_ext_api);*/
-
-/**********************************
- * ext_api used by DI
- ********************************/
-#define ARY_TEMP2
-#ifdef ARY_TEMP2
-void extv3_switch_vpu_mem_pd_vmod(unsigned int vmod, bool on)
-{
- switch_vpu_mem_pd_vmod(vmod,
- on ? VPU_MEM_POWER_ON : VPU_MEM_POWER_DOWN);
-}
-
-const struct ext_ops_s extv3_ops = {
- .switch_vpu_mem_pd_vmod = extv3_switch_vpu_mem_pd_vmod,
- /*no use ?*/
-/* .vf_get_receiver_name = vf_get_receiver_name,*/
- .switch_vpu_clk_gate_vmod = switch_vpu_clk_gate_vmod,
- .get_current_vscale_skip_count = get_current_vscale_skip_count,
- .cvs_alloc_table = canvas_pool_alloc_canvas_table,
-};
-
-#else
-void n_switch_vpu_mem_pd_vmod(unsigned int vmod, bool on)
-{
-}
-
-char *n_vf_get_receiver_name(const char *provider_name)
-{
- return "";
-}
-
-void n_switch_vpu_clk_gate_vmod(unsigned int vmod, int flag)
-{
-}
-
-int n_get_current_vscale_skip_count(struct vframe_s *vf)
-{
- return 0;
-}
-
-u32 n_canvas_pool_alloc_canvas_table(const char *owner, u32 *tab,
- int size,
- enum canvas_map_type_e type)
-{
- return 0;
-}
-
-const struct ext_ops_s extv3_ops = {
- .switch_vpu_mem_pd_vmod = n_switch_vpu_mem_pd_vmod,
- .vf_get_receiver_name = n_vf_get_receiver_name,
- .switch_vpu_clk_gate_vmod = n_switch_vpu_clk_gate_vmod,
- .get_current_vscale_skip_count = n_get_current_vscale_skip_count,
- .cvs_alloc_table = n_canvas_pool_alloc_canvas_table,
-};
-
-#endif
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_api.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_API_H__
-#define __DI_API_H__
-
-#include <linux/amlogic/media/canvas/canvas_mgr.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "../di_local/di_local.h"
-#include "../deinterlace/di_pqa.h"
-
-
-/*--------------------------*/
-unsigned int l_DIV3_POST_REG_RD(unsigned int addr);
-int l_DIV3_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
-
-/*--------------------------*/
-bool di_attach_ext_api(struct di_ext_ops *di_api);
-
-/*attach di_ops to di_local*/
-bool dil_attach_ext_api(const struct di_ext_ops *di_api);
-void dimv3_attach_to_local(void);
-
-/*--------------------------*/
-int get_current_vscale_skip_count(struct vframe_s *vf);
-
-#ifdef MARK_SC2
-struct ext_ops_s {
- void (*switch_vpu_mem_pd_vmod)(unsigned int vmod, bool on);
-/* char *(*vf_get_receiver_name)(const char *provider_name);*/
- void (*switch_vpu_clk_gate_vmod)(unsigned int vmod, int flag);
- int (*get_current_vscale_skip_count)(struct vframe_s *vf);
- u32 (*canvas_pool_alloc_canvas_table)(const char *owner, u32 *tab,
- int size,
- enum canvas_map_type_e type);
-};
-#endif
-
-extern const struct ext_ops_s extv3_ops;
-
-/*--------------------------*/
-void dil_get_rev_mem(unsigned long *mstart, unsigned int *msize);
-void dil_get_flg(unsigned int *flg);
-
-#endif /*__DI_API_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_data.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_DATA_H__
-#define __DI_DATA_H__
-
-#endif /*__DI_DATA_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_data_l.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_DATA_L_H__
-#define __DI_DATA_L_H__
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-
-#include <linux/kfifo.h> /*ary add*/
-
-#include "../deinterlace/di_pqa.h"
-
-#define DI_CHANNEL_NUB (2)
-#define DI_CHANNEL_MAX (4)
-#define DIM_K_VFM_NUM (10)
-#define DIM_K_VFM_IN_LIMIT (2)
-#define DIM_K_BUF_IN_LIMIT (8)
-#define DIM_K_BUF_OUT_LIMIT (8)
-
-#define DIM_K_VFM_LIMIT_PRE_READY (3)
-
-/*ei mode for first frame*/
-#define DIM_EI_CNT (3)
-
-#define DIM_K_CODE_DVFM (0x12345678)
-#define DIM_K_CODE_OLD (0x87654321)
-#define DIM_K_CODE_MASK (0xffaa5500)
-#define DIM_K_CODE_LOCAL (DIM_K_CODE_MASK|02)
-#define DIM_K_CODE_POST (DIM_K_CODE_MASK|03)
-#define DIM_K_CODE_INS_POST (DIM_K_CODE_MASK|04)
-
-#define TABLE_FLG_END (0xfffffffe)
-#define TABLE_LEN_MAX (1000)
-#define F_IN(x, a, b) (((x) > (a)) && ((x) < (b)))
-#define COM_M(m, a, b) (((a) & (m)) == ((b) & (m)))
-#define COM_MV(a, m, v) (((a) & (m)) == (v))
-#define COM_ME(a, m) (((a) & (m)) == (m))
-
-#define DI_BIT0 0x00000001
-#define DI_BIT1 0x00000002
-#define DI_BIT2 0x00000004
-#define DI_BIT3 0x00000008
-#define DI_BIT4 0x00000010
-#define DI_BIT5 0x00000020
-#define DI_BIT6 0x00000040
-#define DI_BIT7 0x00000080
-#define DI_BIT8 0x00000100
-#define DI_BIT9 0x00000200
-#define DI_BIT10 0x00000400
-#define DI_BIT11 0x00000800
-#define DI_BIT12 0x00001000
-#define DI_BIT13 0x00002000
-#define DI_BIT14 0x00004000
-#define DI_BIT15 0x00008000
-#define DI_BIT16 0x00010000
-#define DI_BIT17 0x00020000
-#define DI_BIT18 0x00040000
-#define DI_BIT19 0x00080000
-#define DI_BIT20 0x00100000
-#define DI_BIT21 0x00200000
-#define DI_BIT22 0x00400000
-#define DI_BIT23 0x00800000
-#define DI_BIT24 0x01000000
-#define DI_BIT25 0x02000000
-#define DI_BIT26 0x04000000
-#define DI_BIT27 0x08000000
-#define DI_BIT28 0x10000000
-#define DI_BIT29 0x20000000
-#define DI_BIT30 0x40000000
-#define DI_BIT31 0x80000000
-
-/*****************************************
- *
- * vframe mask
- *
- *****************************************/
-
-#define DI_VFM_T_MASK_CHANGE \
- (VIDTYPE_VIU_422 \
- | VIDTYPE_VIU_SINGLE_PLANE \
- | VIDTYPE_VIU_444 \
- | VIDTYPE_INTERLACE \
- | VIDTYPE_COMPRESS \
- | VIDTYPE_MVC)
-
-/*****************************************
- * cma mode
- * this is keep order with dts define
- *****************************************/
-enum eDI_MEM_M {
- eDI_MEM_M_rev = 0,
- eDI_MEM_M_cma = 1,
- eDI_MEM_M_cma_all = 2,
- eDI_MEM_M_codec_a = 3,
- eDI_MEM_M_codec_b = 4,
- eDI_MEM_M_max /**/
-};
-#if 0
-enum EDPST_OUT_MODE {
- EDPST_OUT_MODE_DEF,
- EDPST_OUT_MODE_NV21,
- EDPST_OUT_MODE_NV12,
-};
-#endif
-
-enum EDPST_MODE {
- EDPST_MODE_NV21_8BIT, /*NV21 NV12*/
- EDPST_MODE_422_10BIT_PACK,
- EDPST_MODE_422_10BIT,
- EDPST_MODE_422_8BIT,
-};
-
-struct di_win_s {
- unsigned int x_size;
- unsigned int y_size;
- unsigned int x_st;
- unsigned int y_st;
-};
-
-/* ************************************** */
-/* *************** cfg top ************** */
-/* ************************************** */
-/* also see: di_cfg_top_ctr*/
-enum eDI_CFG_TOP_IDX {
- /* cfg for top */
- EDI_CFG_BEGIN,
- EDI_CFG_CH_NUB,
- EDI_CFG_mem_flg,
- EDI_CFG_first_bypass,
- EDI_CFG_ref_2,
- EDI_CFG_PMODE,
- /* EDI_CFG_PMODE
- * 0:as p;
- * 1:as i;
- * 2:use 2 i buf
- */
- EDI_CFG_KEEP_CLEAR_AUTO,
- EDI_CFG_PRE_RST_OLD_FLOW,
- EDI_CFG_TMODE_1, /*EDIM_TMODE_1_PW_VFM*/
- EDI_CFG_TMODE_2, /*EDIM_TMODE_2_PW_OUT*/
- EDI_CFG_TMODE_3, /*EDIM_TMODE_3_PW_LOCAL*/
- EDI_CFG_DBG,
- EDI_CFG_END,
-
-};
-
-#define cfgeq(a, b) ((div3_cfg_top_get(EDI_CFG_##a) == (b)) ? true : false)
-#define cfgnq(a, b) ((div3_cfg_top_get(EDI_CFG_##a) != (b)) ? true : false)
-#define cfgg(a) div3_cfg_top_get(EDI_CFG_##a)
-#define cfgs(a, b) div3_cfg_top_set(EDI_CFG_##a, b)
-
-#define K_DI_CFG_NUB (EDI_CFG_END - EDI_CFG_BEGIN + 1)
-/* top cfg table struct */
-#define K_DI_CFG_T_FLG_NOTHING (0x00)
-#define K_DI_CFG_T_FLG_DTS (0x01)
-#define K_DI_CFG_T_FLG_NONE (0x80)
-/*used for variable*/
-union di_cfg_tdata_u {
- unsigned int d32;
- struct {
- unsigned int val_df:4,/**/
- val_dts:4,
- val_dbg:4,
- val_c:4,
- dts_en:1,
- dts_have:1,
- dbg_have:1,
- rev_en:1,
- en_update:4,
- reserved:8;
- } b;
-
-};
-
-/*used for init table*/
-struct di_cfg_ctr_s {
- char *dts_name;
-
- enum eDI_CFG_TOP_IDX id;
- unsigned char default_val;
- unsigned char flg;
-};
-
-/* ************************************** */
-/* *************** cfg x *************** */
-/* ************************************** */
-/*also see di_cfgx_ctr*/
-enum eDI_CFGX_IDX {
- /* cfg channel x*/
- eDI_CFGX_BEGIN,
- eDI_CFGX_BYPASS_ALL, /*bypass_all*/
- EDI_CFGX_HOLD_VIDEO, /*hold_video*/
- eDI_CFGX_END,
-
- /* debug cfg x */
- eDI_DBG_CFGX_BEGIN,
- eDI_DBG_CFGX_IDX_VFM_IN,
- eDI_DBG_CFGX_IDX_VFM_OT,
- eDI_DBG_CFGX_END,
-};
-
-#define K_DI_CFGX_NUB (eDI_DBG_CFGX_END - eDI_CFGX_BEGIN + 1)
-
-struct di_cfgx_ctr_s {
- char *name;
- enum eDI_CFGX_IDX id;
- bool default_val;
-};
-
-/* ****************************** */
-enum eDI_SUB_ID {
- DI_SUB_ID_S0, /*DI_SUB_ID_MARST,*/
- DI_SUB_ID_S1,
- DI_SUB_ID_S2,
- DI_SUB_ID_S3,
- /*DI_SUB_ID_NUB,*/
-};
-
-/*debug vframe type */
-struct di_vframe_type_info {
- char *name;
- unsigned int mask;
- char *other;
-};
-
-#ifdef DIM_DEBUG_QUE_ERR
-union dim_dbg_que_u {
- unsigned int u32;
- struct {
- unsigned int buf_type :2,
- buf_index :6,
- que_index :4,
- que_api :4,
- omx_index :8,
- cnt :8;/*hight*/
- } b;
-};
-
-enum EDIM_QUE_API {
- DIM_QUE_IN = 1,
- DIM_QUE_OUT,
- DIM_QUE_OUT_NOT_FIFO,
- DIM_QUE_PEEK,
- DIM_O_IN,
- DIM_O_OUT,
- DIM_O_PEEK,
-};
-
-#define DIM_DBG_QUE_SIZE 25
-
-struct di_dbg_que_s {
- union dim_dbg_que_u que_inf[DIM_DBG_QUE_SIZE];
- unsigned int pos;
- unsigned int en;
- unsigned int cnt;
-};
-
-#define DIM_DBG_MARK (0x55550000)
-#define DIM_PST_A (DIM_DBG_MARK | 0x0000c000)
-
-#endif
-
-struct di_dbg_datax_s {
- struct vframe_s vfm_input; /*debug input vframe*/
- struct vframe_s *pfm_out; /*debug di_get vframe*/
-#ifdef DIM_DEBUG_QUE_ERR
- struct di_dbg_que_s que;
-#endif
-};
-
-/*debug function*/
-enum eDI_DBG_F {
- eDI_DBG_F_00,
- eDI_DBG_F_01,
- eDI_DBG_F_02,
- eDI_DBG_F_03,
- eDI_DBG_F_04,
- eDI_DBG_F_05,
- eDI_DBG_F_06,
- eDI_DBG_F_07,
- eDI_DBG_F_08,
- eDI_DBG_F_09,
-};
-
-struct di_dbg_func_s {
- enum eDI_DBG_F index;
- void (*func)(unsigned int para);
- char *name;
- char *info;
-};
-
-/*register*/
-struct reg_t {
- unsigned int add;
- unsigned int bit;
- unsigned int wid;
-/* unsigned int id;*/
- unsigned int df_val;
- char *name;
- char *bname;
- char *info;
-};
-
-#ifdef MARK_SC2
-struct reg_acc {
- void (*wr)(unsigned int adr, unsigned int val);
- unsigned int (*rd)(unsigned int adr);
- unsigned int (*bwr)(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len);
- unsigned int (*brd)(unsigned int adr, unsigned int start,
- unsigned int len);
-};
-#endif
-
-/**************************************/
-/* time out */
-/**************************************/
-
-enum eDI_TOUT_CONTR {
-/* eDI_TOUT_CONTR_INT,*/
- eDI_TOUT_CONTR_EN,
- eDI_TOUT_CONTR_FINISH,
- eDI_TOUT_CONTR_CHECK,
-
- eDI_TOUT_CONTR_CLEAR,
- eDI_TOUT_CONTR_RESET,
-};
-
-struct di_time_out_s {
- bool en;
- unsigned long timer_start;
- unsigned int timer_thd;
- unsigned int over_flow_cnt;
- bool flg_over;
-/* bool (*do_func)(void);*/
-};
-
-struct di_func_tab_s {
- unsigned int index;
- bool (*func)(void);
-};
-
-/****************************************/
-/* do_table */
-/****************************************/
-
-/*for do_table_ops_s id*/
-#define K_DO_TABLE_ID_PAUSE 0
-#define K_DO_TABLE_ID_STOP 1
-#define K_DO_TABLE_ID_START 2
-
-/*for mark of do_table_ops_s id*/
-#define K_DO_TABLE_CAN_STOP 0x01
-
-/*for op ret*/
-#define K_DO_TABLE_R_B_FINISH 0x01/*bit 0: 0:not finish, 1:finish*/
-/*bit 1: 0: to other index; 1: to next*/
-#define K_DO_TABLE_R_B_NEXT 0x02
-#define K_DO_TABLE_R_B_OTHER 0xf0 /*bit [7:4]: other index*/
-#define K_DO_TABLE_R_B_OTHER_SHIFT 4 /*bit [7:4]: other index*/
-
-#define K_DO_R_FINISH (K_DO_TABLE_R_B_FINISH | K_DO_TABLE_R_B_NEXT)
-#define K_DO_R_NOT_FINISH (0)
-#define K_DO_R_JUMP(a) (K_DO_TABLE_R_B_FINISH | \
- (((a) << K_DO_TABLE_R_B_OTHER_SHIFT) & K_DO_TABLE_R_B_OTHER))
-
-enum eDO_TABLE_CMD {
- eDO_TABLE_CMD_NONE,
- eDO_TABLE_CMD_STOP,
- eDO_TABLE_CMD_START,
- eDO_TABLE_CMD_PAUSE,
- eDO_TABLE_CMD_STEP,
- eDO_TABLE_CMD_STEP_BACK,
-};
-
-struct do_table_ops_s {
- /*bool stop_mark;*/
- unsigned int id;
- unsigned int mark; /*stop / pause*/
- bool (*con)(void *data);/*condition*/
- unsigned int (*do_op)(void *data);
- unsigned int (*do_stop_op)(void *data);
- char *name;
-
-};
-
-struct do_table_s {
- const struct do_table_ops_s *ptab;
- unsigned int size;
- unsigned int op_lst;
- unsigned int op_crr;
- void *data;
- bool do_stop; /*need do stops */
- bool flg_stop; /*have stop */
-
- bool do_pause;
- bool do_step; /*step mode*/
-
- bool flg_repeat;
- char *name;
-
-};
-
-/*************************************/
-
-/**********************/
-/* vframe info */
-/**********************/
-struct di_vinfo_s {
- /*use this for judge type change or not */
- unsigned int ch;
- unsigned int vtype;
- unsigned int src_type;
- unsigned int trans_fmt;
- unsigned int h;
- unsigned int v;
-};
-#if 0 /*move to deinterlace.h*/
-
-/*2019-10-14*/
-struct di_in_inf_s {
- /*use this for judge type change or not */
- unsigned int ch;
- unsigned int vtype_ori; /*only debug*/
- unsigned int src_type;
- unsigned int trans_fmt;
- unsigned int sig_fmt;/*use for mtn*/
- unsigned int h;
- unsigned int w;
-};
-struct dim_wmode_s;
-
-struct dim_wmode_s {
- unsigned int is_afbc :1,
- is_vdin :1,
- is_i :1,
- need_bypass :1,
- is_bypass :1,
- pre_bypass :1,
- post_bypass :1,
- flg_keep :1, /*keep buf*/
-
- trick_mode :1,
- prog_proc_config :1, /*debug only: proc*/
- /**************************************
- *prog_proc_config:
- *1: process p from decoder as field
- *0: process p from decoder as frame
- ***************************************/
- is_invert_tp :1,
- p_as_i :1,
- is_angle :1,
- reserved :19;
- unsigned int vtype;
- unsigned int h;
- unsigned int w;
- unsigned int seq;
-};
-
-//struct dim_vmode_s;
-
-enum EDIM_DISP_TYPE {
- EDIM_DISP_T_NONE,
- EDIM_DISP_T_IN, /*need bypass*/
- EDIM_DISP_T_PRE,
- EDIM_DISP_T_NR,
- EDIM_DISP_T_PST,
-};
-
-struct dim_dvfm_s {
-// unsigned int code_name;/*0x12345678*/
- unsigned int index;
-
- enum EDIM_DISP_TYPE etype;
- struct di_in_inf_s in_inf;
- struct dim_wmode_s wmode;
- struct dim_vmode_s vmode;
- struct vframe_s vframe;/*input cp*/
- void *vfm_in;
- void *di_buf;/*vfm out is in di_buf*/
-};
-#endif
-
-
-/**************************************/
-/* PRE */
-/**************************************/
-enum eDI_PRE_ST {
- eDI_PRE_ST_EXIT,
- eDI_PRE_ST_IDLE, /*swith to next channel?*/
- eDI_PRE_ST_CHECK,
- eDI_PRE_ST_SET,
- eDI_PRE_ST_WAIT_INT,
- eDI_PRE_ST_TIMEOUT,
-};
-
-enum eDI_PRE_ST4 { /*use this for co work with do table*/
- eDI_PRE_ST4_EXIT,
- eDI_PRE_ST4_IDLE, /*swith to next channel?*/
- eDI_PRE_ST4_CHECK, /*check mode do_table and set*/
- eDI_PRE_ST4_DO_TABLE, /* do table statue;*/
-};
-
-struct di_pre_set_s {
- /*use to remember last hw pre setting;*/
- /*cfg: */
- bool cfg_mcpre_en; /*mcpre_en*/
-
- unsigned int in_w;
- unsigned int in_h;
- unsigned int in_type;
- unsigned int src_type;
-};
-struct di_hpre_s;
-
-struct dim_hpre_ops_s {
- struct di_pre_stru_s *pres; /*tmp for ch*/
-/**************************************
- *prob_hw: not depend channel info
- **************************************/
- void (*prob_hw)(struct di_hpre_s *hpre);
- void (*reg_var)(struct di_hpre_s *hpre);
- void (*reg_hw)(struct di_hpre_s *hpre);
- void (*remove_hw)(struct di_hpre_s *hpre);
- void (*unreg_var)(struct di_hpre_s *hpre);
- void (*unreg_hw)(struct di_hpre_s *hpre);
-};
-
-struct di_hpre_s {
- enum eDI_PRE_ST4 pre_st;
- unsigned int curr_ch;
- /*set when have vframe in; clear when int have get*/
- bool hw_flg_busy_pre;
-/* bool trig_unreg;*/ /*add for unreg flow;*/
-/* enum eDI_SUB_ID hw_owner_pre;*/
- bool flg_wait_int;
- struct di_pre_stru_s *pres;
- struct di_post_stru_s *psts;
- struct di_time_out_s tout; /*for time out*/
- bool flg_int_done;
- unsigned int check_recycle_buf_cnt;
-
- struct di_pre_set_s set_lst;
- struct di_pre_set_s set_curr;
-
- struct di_in_inf_s vinf_lst;
- struct di_in_inf_s vinf_curr;
-
- /* use do table to swith mode*/
- struct do_table_s sdt_mode;
-
- unsigned int idle_cnt; /*use this avoid repeat idle <->check*/
- /*dbg flow:*/
- bool dbg_f_en;
- unsigned int dbg_f_lstate;
- unsigned int dbg_f_cnt;
-
- /*canvans*/
- unsigned int di_inp_idx[3];
- struct dim_hpre_ops_s ops;
-};
-
-/**************************************/
-/* POST */
-/**************************************/
-enum eDI_PST_ST {
- eDI_PST_ST_EXIT,
- eDI_PST_ST_IDLE, /*swith to next channel?*/
- eDI_PST_ST_CHECK,
- eDI_PST_ST_SET,
- eDI_PST_ST_WAIT_INT,
- eDI_PST_ST_TIMEOUT,
- eDI_PST_ST_DONE, /*use for bypass_all*/
-};
-
-struct di_hpst_s {
- enum eDI_PST_ST state;
- unsigned int curr_ch;
- /*set when have vframe in; clear when int have get*/
- bool hw_flg_busy_post;
- struct di_pre_stru_s *pres;
- struct di_post_stru_s *psts;
- struct di_time_out_s tout; /*for time out*/
- bool flg_int_done;
-
- /*dbg flow:*/
- bool dbg_f_en;
- unsigned int dbg_f_lstate;
- unsigned int dbg_f_cnt;
- struct vframe_s vf_post;
-
-};
-
-/**************************************/
-/* channel status */
-/**************************************/
-enum EDI_TOP_STATE {
- eDI_TOP_STATE_NOPROB,
- EDI_TOP_STATE_IDLE, /*idle not work*/
- /* STEP1
- * till peek vframe and set irq;before this state, event reg finish
- */
- eDI_TOP_STATE_REG_STEP1,
- eDI_TOP_STATE_REG_STEP1_P1, /*2019-05-21*/
- eDI_TOP_STATE_REG_STEP2, /*till alloc and ready*/
- EDI_TOP_STATE_READY, /*can do DI*/
- eDI_TOP_STATE_BYPASS, /*complet bypass*/
- eDI_TOP_STATE_UNREG_STEP1, /*till pre/post is finish;*/
- /* do unreg and to IDLE.
- * no need to wait cma release after this unreg event finish
- */
- eDI_TOP_STATE_UNREG_STEP2,
-
-};
-
-/**************************************/
-/* thread and cmd */
-/**************************************/
-struct di_task {
- bool flg_init;
- struct semaphore sem;
- wait_queue_head_t wait_queue;
- struct task_struct *thread;
- unsigned int status;
-
- unsigned int wakeup;
- unsigned int delay;
- bool exit;
-#if 1 /*not use cmd*/
-
- /*local event*/
- struct kfifo fifo_cmd;
- spinlock_t lock_cmd;
- bool flg_cmd;
- unsigned int err_cmd_cnt;
-#endif
-};
-
-#define MAX_KFIFO_L_CMD_NUB 32
-
-union DI_L_CMD_BITS {
- unsigned int cmd32;
- struct {
- unsigned int id:8, /*low bit*/
- ch:8, /*channel*/
- p2:8,
- p3:8;
- } b;
-};
-
-#define LCMD1(id, ch) ((id) | ((ch) << 8))
-#define LCMD2(id, ch, p2) ((id) | ((ch) << 8) | ((p2) << 16))
-
-enum eCMD_LOCAL {
- eCMD_NONE,
- eCMD_REG,
- eCMD_UNREG,
- eCMD_READY,
- eCMD_CHG,
- ECMD_RL_KEEP,
- ECMD_RL_KEEP_ALL,
- NR_FINISH,
-};
-
-/**************************************
- *QUE
- *keep same order with di_name_new_que
- **************************************/
-enum QUE_TYPE { /*mast start from 0 */
- QUE_IN_FREE, /*5*/
- QUE_PRE_READY, /*6*/
- QUE_POST_FREE, /*7*/
- QUE_POST_READY, /*8*/
- QUE_POST_BACK, /*new*/
- QUE_POST_DOING,
- QUE_POST_NOBUF,
- QUE_POST_KEEP, /*below use pw_queue_in*/
- QUE_POST_KEEP_BACK,
- /*----------------*/
- QUE_DBG,
- QUE_NUB,
-};
-
-/**************************************
- *QUED
- *keep same order with qued_name
- **************************************/
-enum QUED_TYPE {
- /*fifo:*/
- QUED_T_FREE,
- QUED_T_IN,
- QUED_T_PRE,
- QUED_T_PRE_READY,
- QUED_T_PST,
- QUED_T_PST_READY,
- QUED_T_BACK,
- QUED_T_RECYCL,
- QUED_T_IS_IN, /*input for instance mode*/
- QUED_T_IS_FREE,
- QUED_T_IS_PST_FREE, /*use for post buf out*/
- QUED_T_IS_PST_DOBEF,/*before post doing*/
- //QUED_T_IS_PST_NOBUF,
- QUED_T_PST_DOING,/*?*/
- QUED_T_DBG,
- /*bit map*/
- QUED_T_SPLIT, /*not use, only split*/
- QUED_T_DIS,
- QUED_T_NUB,
-};
-
-enum QUED_KIND {
- QUED_K_FIFO,
- QUED_K_N, /*bit map*/
-};
-
-#define DIM_MAX_QUE_N (32)
-
-struct que_n_s {
- int nub;
- struct mutex mtex;
- unsigned int marsk;
-};
-
-struct que_f_s {
- bool flg; /*1: have reg*/
- struct kfifo fifo;
-};
-
-struct dim_que_s {
- enum QUED_TYPE index;
- enum QUED_KIND type;
- const char *name;
- union {
- struct que_n_s n;
- struct que_f_s f;
- };
-};
-
-/*#define QUE_NUB (5)*/
-enum eDI_BUF_TYPE {
- eDI_BUF_T_IN = 1, /*VFRAME_TYPE_IN*/
- eDI_BUF_T_LOCAL, /*VFRAME_TYPE_LOCAL*/
- eDI_BUF_T_POST, /*VFRAME_TYPE_POST*/
-};
-
-#define MAX_FIFO_SIZE (32)
-
-/**************************************
- *
- * summmary variable
- * also see:di_sum_name_tab
- **************************************/
-
-enum eDI_SUM {
- eDI_SUM_O_PEEK_CNT, /*video_peek_cnt*/
- eDI_SUM_REG_UNREG_CNT, /*di_reg_unreg_cnt*/
- eDI_SUM_NUB,
-};
-
-struct di_sum_s {
- char *name;
- enum eDI_SUM index;
- unsigned int default_val;
-};
-
-/**************************************
- *
- * module para
- * int
- * eDI_MP_SUB_DI_B
- * eDI_MP_SUB_NR_B
- * eDI_MP_SUB_PD_B
- * eDI_MP_SUB_MTN_B
- * eDI_MP_SUB_3D_B
- **************************************/
-enum eDI_MP_UI_T {
- /*keep same order with di_mp_ui_top*/
- eDI_MP_UI_T_BEGIN,
- /**************************************/
- eDI_MP_SUB_DI_B,
-
- eDI_MP_force_prog, /*force_prog bool*/
- edi_mp_combing_fix_en, /*combing_fix_en bool*/
- eDI_MP_cur_lev, /*cur_lev*/
- eDI_MP_pps_dstw, /*pps_dstw*/
- eDI_MP_pps_dsth, /*pps_dsth*/
- eDI_MP_pps_en, /*pps_en*/
- eDI_MP_pps_position, /*pps_position*/
- eDI_MP_pre_enable_mask, /*pre_enable_mask*/
- eDI_MP_post_refresh, /*post_refresh*/
- eDI_MP_nrds_en, /*nrds_en*/
- eDI_MP_bypass_3d, /*bypass_3d*/
- eDI_MP_bypass_trick_mode, /*bypass_trick_mode*/
- eDI_MP_invert_top_bot, /*invert_top_bot */
- eDI_MP_skip_top_bot,
- eDI_MP_force_width,
- eDI_MP_force_height,
- eDI_MP_prog_proc_config,
- eDI_MP_start_frame_drop_count,
- eDI_MP_same_field_top_count, /*long?*/
- eDI_MP_same_field_bot_count, /*long?*/
- eDI_MP_vpp_3d_mode,
- eDI_MP_force_recovery_count,
- eDI_MP_pre_process_time, /*no use?*/
- eDI_MP_bypass_post,
- eDI_MP_post_wr_en,
- eDI_MP_post_wr_support,
- eDI_MP_bypass_post_state,
- eDI_MP_use_2_interlace_buff,
- eDI_MP_debug_blend_mode,
- eDI_MP_nr10bit_support,
- eDI_MP_di_stop_reg_flag,
- eDI_MP_mcpre_en,
- eDI_MP_check_start_drop_prog,
- eDI_MP_overturn, /*? in init*/
- eDI_MP_full_422_pack,
- eDI_MP_cma_print,
- eDI_MP_pulldown_enable,
- eDI_MP_di_force_bit_mode,
- eDI_MP_calc_mcinfo_en,
- eDI_MP_colcfd_thr,
- eDI_MP_post_blend,
- eDI_MP_post_ei,
- eDI_MP_post_cnt,
- eDI_MP_di_log_flag,
- eDI_MP_di_debug_flag,
- eDI_MP_buf_state_log_threshold,
- eDI_MP_di_vscale_skip_enable,
- eDI_MP_di_vscale_skip_count,
- eDI_MP_di_vscale_skip_count_real,
- eDI_MP_det3d_en,
- eDI_MP_post_hold_line,
- eDI_MP_post_urgent,
- eDI_MP_di_printk_flag,
- eDI_MP_force_recovery,
-/* eDI_MP_debug_blend_mode,*/
- eDI_MP_di_dbg_mask,
- eDI_MP_nr_done_check_cnt,
- eDI_MP_pre_hsc_down_en,
- eDI_MP_pre_hsc_down_width,
- eDI_MP_show_nrwr,
- /********deinterlace_hw.c*********/
- eDI_MP_pq_load_dbg,
- eDI_MP_lmv_lock_win_en,
- eDI_MP_lmv_dist,
- eDI_MP_pr_mcinfo_cnt,
- eDI_MP_offset_lmv,
- eDI_MP_post_ctrl,
- eDI_MP_if2_disable,
- eDI_MP_pre_flag,
- eDI_MP_pre_mif_gate,
- eDI_MP_pre_urgent,
- eDI_MP_pre_hold_line,
- eDI_MP_pre_ctrl,
- eDI_MP_line_num_post_frst,
- eDI_MP_line_num_pre_frst,
- eDI_MP_pd22_flg_calc_en,
- eDI_MP_mcen_mode,
- eDI_MP_mcuv_en,
- eDI_MP_mcdebug_mode,
- eDI_MP_pldn_ctrl_rflsh,
- eDI_MP_4k_test,
-
- eDI_MP_SUB_DI_E,
- /**************************************/
- eDI_MP_SUB_NR_B,
- EDI_MP_SUB_DELAY,
- EDI_MP_SUB_DBG_MODE,
- eDI_MP_cue_en,
- eDI_MP_invert_cue_phase,
- eDI_MP_cue_pr_cnt,
- eDI_MP_cue_glb_mot_check_en,
- eDI_MP_glb_fieldck_en,
- eDI_MP_dnr_pr,
- eDI_MP_dnr_dm_en,
- eDI_MP_SUB_NR_E,
- /**************************************/
- eDI_MP_SUB_PD_B,
- eDI_MP_flm22_ratio,
- eDI_MP_pldn_cmb0,
- eDI_MP_pldn_cmb1,
- eDI_MP_flm22_sure_num,
- eDI_MP_flm22_glbpxlnum_rat,
- eDI_MP_flag_di_weave,
- eDI_MP_flm22_glbpxl_maxrow,
- eDI_MP_flm22_glbpxl_minrow,
- eDI_MP_cmb_3point_rnum,
- eDI_MP_cmb_3point_rrat,
- /******film_fw1.c**/
- eDI_MP_pr_pd,
- eDI_MP_prt_flg,
- eDI_MP_flmxx_maybe_num,
- eDI_MP_flm32_mim_frms,
- eDI_MP_flm22_dif01a_flag,
- eDI_MP_flm22_mim_frms,
- eDI_MP_flm22_mim_smfrms,
- eDI_MP_flm32_f2fdif_min0,
- eDI_MP_flm32_f2fdif_min1,
- eDI_MP_flm32_chk1_rtn,
- eDI_MP_flm32_ck13_rtn,
- eDI_MP_flm32_chk2_rtn,
- eDI_MP_flm32_chk3_rtn,
- eDI_MP_flm32_dif02_ratio,
- eDI_MP_flm22_chk20_sml,
- eDI_MP_flm22_chk21_sml,
- eDI_MP_flm22_chk21_sm2,
- eDI_MP_flm22_lavg_sft,
- eDI_MP_flm22_lavg_lg,
- eDI_MP_flm22_stl_sft,
- eDI_MP_flm22_chk5_avg,
- eDI_MP_flm22_chk6_max,
- eDI_MP_flm22_anti_chk1,
- eDI_MP_flm22_anti_chk3,
- eDI_MP_flm22_anti_chk4,
- eDI_MP_flm22_anti_ck140,
- eDI_MP_flm22_anti_ck141,
- eDI_MP_flm22_frmdif_max,
- eDI_MP_flm22_flddif_max,
- eDI_MP_flm22_minus_cntmax,
- eDI_MP_flagdif01chk,
- eDI_MP_dif01_ratio,
- /*******vof_soft_top*****/
- eDI_MP_cmb32_blw_wnd,
- eDI_MP_cmb32_wnd_ext,
- eDI_MP_cmb32_wnd_tol,
- eDI_MP_cmb32_frm_nocmb,
- eDI_MP_cmb32_min02_sft,
- eDI_MP_cmb32_cmb_tol,
- eDI_MP_cmb32_avg_dff,
- eDI_MP_cmb32_smfrm_num,
- eDI_MP_cmb32_nocmb_num,
- eDI_MP_cmb22_gcmb_rnum,
- eDI_MP_flmxx_cal_lcmb,
- eDI_MP_flm2224_stl_sft,
- eDI_MP_SUB_PD_E,
- /**************************************/
- eDI_MP_SUB_MTN_B,
- eDI_MP_force_lev,
- eDI_MP_dejaggy_flag,
- eDI_MP_dejaggy_enable,
- eDI_MP_cmb_adpset_cnt,
- eDI_MP_cmb_num_rat_ctl4,
- eDI_MP_cmb_rat_ctl4_minthd,
- eDI_MP_small_local_mtn,
- eDI_MP_di_debug_readreg,
- eDI_MP_SUB_MTN_E,
- /**************************************/
- eDI_MP_SUB_3D_B,
- eDI_MP_chessbd_vrate,
- eDI_MP_det3d_debug,
-
- eDI_MP_SUB_3D_E,
- /**************************************/
- eDI_MP_UI_T_END,
-};
-
-#define K_DI_MP_UIT_NUB (eDI_MP_UI_T_END - eDI_MP_UI_T_BEGIN + 1)
-
-struct di_mp_uit_s {
- char *name;
- enum eDI_MP_UI_T id;
- int default_val;
-};
-
-/*also see: div3_mpx*/
-enum eDI_MP_UIX_T {
- eDI_MP_UIX_BEGIN,
- eDI_MP_UIX_RUN_FLG, /*run_flag*/
- eDI_MP_UIX_END,
-};
-
-#define K_DI_MP_UIX_NUB (eDI_MP_UIX_END - eDI_MP_UIX_BEGIN + 1)
-
-struct di_mp_uix_s {
- char *name;
- enum eDI_MP_UIX_T id;
- unsigned int default_val;
-};
-
-/**************************************/
-/* DI WORKING MODE */
-/**************************************/
-enum eDI_WORK_MODE {
- eDI_WORK_MODE_NONE,
- eDI_WORK_MODE_bypass_complet,
- eDI_WORK_MODE_bypass_all, /*dim_is_bypass*/
- eDI_WORK_MODE_bypass_pre,
- eDI_WORK_MODE_bypass_post,
- eDI_WORK_MODE_i,
- eDI_WORK_MODE_p_as_i,
- eDI_WORK_MODE_p_as_p,
- eDI_WORK_MODE_p_use_ibuf,
- eDI_WORK_MODE_all,
-
-};
-
-/**************************************/
-/* vframe */
-/**************************************/
-struct dev_vfram_t {
- #if 0
- /*same*/
- unsigned int tmode;
- const char *name;
- unsigned int ch;
- /*status:*/
- bool bypass_complete;
- bool reg; /*use this for vframe reg/unreg*/
- #endif
- /*receiver:*/
- struct vframe_receiver_s di_vf_recv;
- /*provider:*/
- struct vframe_provider_s di_vf_prov;
-
-/* unsigned int data[32]; */ /*null*/
-// struct vframe_operations_s pre_ops;
-};
-
-
-/**********************************************************
- * instance
- * same as vframe
- **********************************************************/
-struct dev_instance {
- struct di_init_parm parm;
- struct di_buffer *in[DIM_K_BUF_IN_LIMIT];
- struct di_buffer *out[DIM_K_BUF_OUT_LIMIT];
-};
-
-#if 0
-union dim_inter_s {
- struct dev_vfram_t dvfm;
- struct dev_instance dinst;
-};
-#else
-struct di_ch_s;
-
-struct dim_itf_ops_s {
- void *(*peek)(struct di_ch_s *pch);
- void *(*get)(struct di_ch_s *pch);
- void (*put)(void *data, struct di_ch_s *pch);
-};
-
-struct dim_inter_s {
- unsigned int tmode;
- const char *name;
- unsigned int ch;
- /*status:*/
- bool bypass_complete;
- bool reg;
- struct dim_itf_ops_s opsi;
- struct dim_itf_ops_s opso;
- void (*op_post_done)(struct di_ch_s *pch);
- struct dim_dvfm_s *(*op_dvfm_fill)(struct di_ch_s *pch);
- void (*op_ins_2_doing)(struct di_ch_s *pch,
- bool bypass,
- struct di_buf_s *di_buf);
- union {
- struct dev_vfram_t dvfm;
- struct dev_instance dinst;
- } u;
-};
-#endif
-
-struct di_ores_s {
- /* same as ori */
- struct di_pre_stru_s di_pre_stru;
- struct di_post_stru_s di_post_stru;
-
- struct di_buf_s di_buf_local[MAX_LOCAL_BUF_NUM * 2];
- struct di_buf_s di_buf_in[MAX_IN_BUF_NUM];
- struct di_buf_s di_buf_post[MAX_POST_BUF_NUM];
- /* ins_post: add for EDIM_TMODE_3_PW_LOCAL*/
- struct di_buffer ins_post[MAX_POST_BUF_NUM];
- struct queue_s queue[QUEUE_NUM];
- struct di_buf_pool_s di_buf_pool[VFRAME_TYPE_NUM];
-
- //struct vframe_s *vframe_in[MAX_IN_BUF_NUM];
- void *vframe_in[MAX_IN_BUF_NUM];
- struct vframe_s vframe_in_dup[MAX_IN_BUF_NUM];
- struct vframe_s vframe_local[MAX_LOCAL_BUF_NUM * 2];
- struct vframe_s vframe_post[MAX_POST_BUF_NUM];
- /* ********** */
-};
-
-/*keep same order with di_cma_state_name*/
-enum eDI_CMA_ST {
- EDI_CMA_ST_IDL,
- EDI_CMA_ST_ALLOC, /*do*/
- EDI_CMA_ST_READY,
- EDI_CMA_ST_RELEASE, /*do*/
- EDI_CMA_ST_PART,
-};
-
-union ens_u {
- unsigned int en_32;
- struct {
- unsigned int
- h_sc_down :1,
- pps_enable :1,
- reserved :30;
- } b;
-};
-
-enum EDIM_TMODE;
-
-struct dim_cfg_s {
- enum EDIM_TMODE tmode;
- unsigned int w_rdup; /*width_roundup*/
- unsigned int f_w; /*force_w: force input*/
- unsigned int f_h; /*force_h*/
-
- unsigned int vfm_bitdepth;
- union ens_u ens;
-};
-
-/**********************************
- * mem
- *********************************/
-struct di_mm_cfg_s {
- /*support max input interlace size*/
- unsigned int di_h;
- unsigned int di_w;
- /**/
- unsigned int num_local;
- unsigned int num_post;
-
- unsigned int size_local;
- unsigned int size_post;
-
- int nr_size;
- int count_size;
- int mcinfo_size;
- int mv_size;
- int mtn_size;
-
- /* alloc di buf as p or i;0: alloc buf as i;
- * 1: alloc buf as p;
- */
- unsigned char buf_alloc_mode;
-};
-
-/*use for reserved and alloc all*/
-struct dim_mm_t_s {
- unsigned long mem_start;
- unsigned int mem_size;
- struct page *total_pages;
-};
-
-struct di_mm_st_s {
- /* use for reserved and alloc all*/
- unsigned long mem_start;
- unsigned int mem_size;
- /* struct page *total_pages;*/
-
- /*unsigned int flag_cma;*/
-
-//no use unsigned int size_local; /*?*/
-//no use unsigned int size_post; /*?*/
- int num_local;
- int num_post; /*for alloc nub*/
-};
-
-struct di_mm_s {
- struct di_mm_cfg_s cfg;
- struct di_mm_st_s sts;
-};
-
-struct dim_pres_s {
- /*bad_frame_throw_count*/
- unsigned int bad_frame;
-};
-/********************************************************************
- * for err
- ********************************************************************/
-#define DIM_ERR_QUE_FIFO DI_BIT0
-
-/********************************************************************
- * for sum
- ********************************************************************/
-struct dim_sum_s {
- /*buf*/
- unsigned int b_pre_free;
- unsigned int b_pst_ready;
- unsigned int b_recyc;
- unsigned int b_pre_ready;
- unsigned int b_pst_free;
- unsigned int b_display;
-};
-
-struct di_ch_s {
- /*struct di_cfgx_s dbg_cfg;*/
- bool cfgx_en[K_DI_CFGX_NUB];
- unsigned int mp_uix[K_DI_MP_UIX_NUB];/*module para x*/
-
- struct di_dbg_datax_s dbg_data;
-
- //struct dev_vfram_t vfm;
- struct dim_inter_s interf;
- struct dentry *dbg_rootx; /*dbg_fs*/
-
- unsigned int ch_id;
- struct di_ores_s rse_ori;
- struct dim_dvfm_s dvfm[DIM_K_VFM_NUM];
- struct dim_que_s qued[QUED_T_NUB];
-
- struct kfifo fifo[QUE_NUB];
- bool flg_fifo[QUE_NUB]; /*have ini: 1; else 0*/
-/* bool sub_act_flg;*/
- /************************/
- /*old glob*/
- /************************/
- /*bypass_state*/
- bool bypass_state;
-
- struct dim_pres_s pret;
- /*video_peek_cnt*/
- unsigned int sum[eDI_SUM_NUB + 1];
- unsigned int sum_get;
- unsigned int sum_put;
- unsigned int sum_pst_done;
- struct dim_sum_s sumx;
- struct dim_cfg_s cfgt;
- struct dim_dvfm_s lst_dvfm;
-// unsigned int pause; /* 2020-05-14 */
- unsigned int err;
-};
-
-struct di_meson_data {
- const char *name;
- /*struct ic_ver icver;*/
- /*struct ddemod_reg_off regoff;*/
-};
-
-struct dim_wq_s {
- char *name;
- unsigned int ch;
- struct workqueue_struct *wq_cma;
- struct work_struct wq_work;
-};
-/*****************************
- * hw timer
- *****************************/
-#define DIM_HTM_W_INPUT DI_BIT16
-#define DIM_HTM_W_LOCAL DI_BIT17
-#define DIM_HTM_W_POST DI_BIT18
-#define DIM_HTM_W_INT DI_BIT19
-
-#define DIM_HTM_WK (DI_BIT0 | DI_BIT1 | DI_BIT2 | DI_BIT3)
-#define DIM_HTM_REG (DI_BIT4 | DI_BIT5 | DI_BIT6 | DI_BIT7)
-
-#define DIM_HTM_WK_BIT (DI_BIT0)
-#define DIM_HTM_REG_BIT (DI_BIT4)
-
-#define DIM_HTM_CONDITION (DIM_HTM_W_INPUT | \
- DIM_HTM_W_LOCAL | \
- DIM_HTM_W_POST | \
- DIM_HTM_W_INT)
-
-/*keep same order with dim_htr_sts_name*/
-enum EHTM_STS {
- EHTM_STS_NONE,
- EHTM_STS_PROB,
- EHTM_STS_WRK,
- EHTM_STS_CANCEL,
-};
-
-struct di_timer_s {
- struct hrtimer hrt;
- unsigned int con;
- enum EHTM_STS sts;
-#if 0
- u64 lst_ht;
- u64 lst_tsk_st;
- u64 lst_tsk_end;
- unsigned int pre_ready_cnt;
- unsigned int pre_get_cnt;
-#endif
-};
-
-/*****************************
- * manager:
- *****************************/
-struct di_mng_s {
- /*workqueue*/
- struct dim_wq_s wq;
-
- /*use enum eDI_CMA_ST*/
- atomic_t cma_mem_state[DI_CHANNEL_NUB];
- /*1:alloc cma, 0:release cma set by mng, read by work que*/
- unsigned char cma_reg_cmd[DI_CHANNEL_NUB];
- enum EDIM_TMODE tmode_pre[DI_CHANNEL_MAX];
-
- /*task:*/
- struct di_task tsk;
- /*timer*/
- struct di_timer_s tim;
-
- /*channel state: use enum eDI_TOP_STATE */
- atomic_t ch_state[DI_CHANNEL_NUB];
-
- bool in_flg[DI_CHANNEL_NUB];
-#if 0
- unsigned long mem_start[DI_CHANNEL_NUB];
- unsigned int mem_size[DI_CHANNEL_NUB];
-#endif
- bool sub_act_flg[DI_CHANNEL_NUB];
- /*struct mutex event_mutex[DI_CHANNEL_NUB];*/
- bool init_flg[DI_CHANNEL_NUB]; /*init_flag*/
- /*bool reg_flg[DI_CHANNEL_NUB];*/ /*reg_flag*/
- unsigned int reg_flg_ch; /*for x ch reg/unreg flg*/
- bool trig_unreg[DI_CHANNEL_NUB];
- bool hw_reg_flg; /*for di_reg_setting/di_unreg_setting*/
- bool act_flg ;/*active_flag*/
-
- bool flg_hw_int; /*only once*/
-
- struct dim_mm_t_s mmt;
- struct di_mm_s mm[DI_CHANNEL_NUB];
-};
-
-/*************************
- *debug register:
- *************************/
-#define K_DI_SIZE_REG_LOG (1000)
-#define K_DI_LAB_MOD (0xf001)
-/*also see: dbg_mode_name*/
-enum eDI_DBG_MOD {
- eDI_DBG_MOD_REGB, /* 0 */
- eDI_DBG_MOD_REGE, /* 1 */
- eDI_DBG_MOD_UNREGB, /* 2 */
- eDI_DBG_MOD_UNREGE, /* 3 */
- eDI_DBG_MOD_PRE_SETB, /* 4 */
- eDI_DBG_MOD_PRE_SETE, /* 5 */
- eDI_DBG_MOD_PRE_DONEB, /* 6 */
- eDI_DBG_MOD_PRE_DONEE, /* 7 */
- eDI_DBG_MOD_POST_SETB, /* 8 */
- eDI_DBG_MOD_POST_SETE, /* 9 */
- eDI_DBG_MOD_POST_IRQB, /* a */
- eDI_DBG_MOD_POST_IRQE, /* b */
- eDI_DBG_MOD_POST_DB, /* c */
- eDI_DBG_MOD_POST_DE, /* d */
- eDI_DBG_MOD_POST_CH_CHG, /* e */
- eDI_DBG_MOD_POST_TIMEOUT, /* F */
-
- eDI_DBG_MOD_RVB, /*10 */
- eDI_DBG_MOD_RVE, /*11 */
-
- eDI_DBG_MOD_POST_RESIZE, /*0x12 */
- eDI_DBG_MOD_END,
-
-};
-
-enum eDI_LOG_TYPE {
- eDI_LOG_TYPE_ALL = 1,
- eDI_LOG_TYPE_REG,
- eDI_LOG_TYPE_MOD,
-};
-
-struct di_dbg_reg {
- unsigned int addr;
- unsigned int val;
- unsigned int st_bit:8,
- b_w:8,
- res:16;
-};
-
-struct di_dbg_mod {
- unsigned int lable; /*0xf001: mean dbg mode*/
- unsigned int ch:8,
- mod:8,
- res:16;
- unsigned int cnt;/*frame cnt*/
-};
-
-union udbg_data {
- struct di_dbg_reg reg;
- struct di_dbg_mod mod;
-};
-
-struct di_dbg_reg_log {
- bool en;
- bool en_reg;
- bool en_mod;
- bool en_all;
- bool en_notoverwrite;
-
- union udbg_data log[K_DI_SIZE_REG_LOG];
- unsigned int pos;
- unsigned int wsize;
- bool overflow;
-};
-
-struct di_dbg_data {
- unsigned int vframe_type; /*use for type info*/
- unsigned int cur_channel;
- struct di_dbg_reg_log reg_log;
-
- unsigned int delay_cnt;/*use for regiter delay*/
-};
-
-struct qued_ops_s {
- bool (*prob)(struct di_ch_s *pch);
- void (*remove)(struct di_ch_s *pch);
- bool (*reg)(struct di_ch_s *pch);
- bool (*unreg)(struct di_ch_s *pch);
- bool (*in)(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int buf_in);
- bool (*out)(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int *buf_o);
- bool (*peek)(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int *buf_o);
- bool (*list)(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int *outbuf,
- unsigned int *rsize);
- unsigned int (*listv3_count)(struct di_ch_s *pch, enum QUED_TYPE qtype);
- bool (*is_in)(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int buf_index);
- bool (*is_empty)(struct di_ch_s *pch, enum QUED_TYPE qtype);
- const char *(*get_name)(struct di_ch_s *pch, enum QUED_TYPE qtype);
- bool (*move)(struct di_ch_s *pch, enum QUED_TYPE qtypef,
- enum QUED_TYPE qtypet, unsigned int *buf_index);
-};
-
-struct di_data_l_s {
- /*bool cfg_en[K_DI_CFG_NUB];*/ /*cfg_top*/
- union di_cfg_tdata_u cfg_en[K_DI_CFG_NUB];
- /*use for debug*/
- unsigned int cfg_sel;
- unsigned int cfg_dbg_mode; /*val or item*/
- /**************/
- int mp_uit[K_DI_MP_UIT_NUB]; /*eDI_MP_UI_T*/
- struct di_ch_s ch_data[DI_CHANNEL_NUB];
- int plane[DI_CHANNEL_NUB]; /*use for debugfs*/
- //struct dim_cfg_s cfg_sys[DI_CHANNEL_NUB]; /**/
- struct di_dbg_data dbg_data;
- struct di_mng_s mng;
- struct di_hpre_s hw_pre;
- struct di_hpst_s hw_pst;
- struct dentry *dbg_root_top; /* dbg_fs*/
- /*pq_ops*/
- const struct pulldown_op_s *ops_pd; /* pulldown */
- const struct detect3d_op_s *ops_3d; /* detect_3d */
- const struct nr_op_s *ops_nr; /* nr */
- const struct mtn_op_s *ops_mtn; /* deinterlace_mtn */
- /*di ops for other module */
- /*struct di_ext_ops *di_api; */
- const struct di_meson_data *mdata;
- /*const struct qued_ops_s *que_op;*/
-};
-
-enum EDI_ST {
- EDI_ST_PRE = DI_BIT0,
- EDI_ST_P_U2I = DI_BIT1,
- EDI_ST_BYPASS = DI_BIT2,
- EDI_ST_P_T = DI_BIT3,
- EDI_ST_P_B = DI_BIT4,
- EDI_ST_I = DI_BIT5,
- EDI_ST_DUMMY = DI_BIT6,
- EDI_ST_AS_LINKA = DI_BIT7,
- EDI_ST_AS_LINKB = DI_BIT8,
- EDI_ST_AS_LINK_ERR1 = DI_BIT9,
- EDI_ST_PRE_DONE = DI_BIT10,
- EDI_ST_VFM_I = DI_BIT11,
- EDI_ST_VFM_P_ASI_T = DI_BIT12,
- EDI_ST_VFM_P_ASI_B = DI_BIT13,
- EDI_ST_VFM_P_U2I = DI_BIT14,
- EDI_ST_VFM_RECYCLE = DI_BIT15,
- EDI_ST_DIS = DI_BIT16,
- EDI_ST_RECYCLE = DI_BIT17,
-};
-
-/**************************************
- *
- * DEBUG infor
- *
- *************************************/
-
-#define DBG_M_C_ALL DI_BIT30 /*all debug close*/
-#define DBG_M_O_ALL DI_BIT31 /*all debug open*/
-
-#define DBG_M_DT DI_BIT0 /*do table work*/
-#define DBG_M_REG DI_BIT1 /*reg/unreg*/
-#define DBG_M_POST_REF DI_BIT2
-#define DBG_M_TSK DI_BIT3
-#define DBG_M_INIT DI_BIT4
-#define DBG_M_EVENT DI_BIT5
-#define DBG_M_FIRSTFRAME DI_BIT6
-#define DBG_M_DBG DI_BIT7
-
-#define DBG_M_POLLING DI_BIT8
-#define DBG_M_ONCE DI_BIT9
-#define DBG_M_KEEP DI_BIT10 /*keep buf*/
-#define DBG_M_MEM DI_BIT11 /*mem alloc release*/
-#define DBG_M_QUED DI_BIT12
-#define DBG_M_HTM DI_BIT13 /*hw timer*/
-#define DBG_M_WQ DI_BIT14 /*work que*/
-
-
-extern unsigned int div3_dbg;
-
-#define dbg_m(mark, fmt, args ...) \
- do { \
- if (div3_dbg & DBG_M_C_ALL) \
- break; \
- if ((div3_dbg & DBG_M_O_ALL) || \
- (div3_dbg & (mark))) { \
- pr_info("dimv3:"fmt, ##args); \
- } \
- } while (0)
-
-#define PR_ERR(fmt, args ...) pr_err("dimv3:err:"fmt, ## args)
-#define PR_WARN(fmt, args ...) pr_err("dimv3:warn:"fmt, ## args)
-#define PR_INF(fmt, args ...) pr_info("dimv3:"fmt, ## args)
-
-#define dbg_dt(fmt, args ...) dbg_m(DBG_M_DT, fmt, ##args)
-#define dbg_reg(fmt, args ...) dbg_m(DBG_M_REG, fmt, ##args)
-#define dbg_post_ref(fmt, args ...) dbg_m(DBG_M_POST_REF, fmt, ##args)
-#define dbg_poll(fmt, args ...) dbg_m(DBG_M_POLLING, fmt, ##args)
-#define dbg_tsk(fmt, args ...) dbg_m(DBG_M_TSK, fmt, ##args)
-
-#define dbg_init(fmt, args ...) dbg_m(DBG_M_INIT, fmt, ##args)
-#define dbg_ev(fmt, args ...) dbg_m(DBG_M_EVENT, fmt, ##args)
-#define dbgv3_first_frame(fmt, args ...) dbg_m(DBG_M_FIRSTFRAME, fmt, ##args)
-#define dbg_dbg(fmt, args ...) dbg_m(DBG_M_DBG, fmt, ##args)
-#define dbg_once(fmt, args ...) dbg_m(DBG_M_ONCE, fmt, ##args)
-#define dbg_qued(fmt, args ...) dbg_m(DBG_M_QUED, fmt, ##args)
-#define dbg_mem(fmt, args ...) dbg_m(DBG_M_MEM, fmt, ##args)
-#define dbg_keep(fmt, args ...) dbg_m(DBG_M_KEEP, fmt, ##args)
-#define dbg_htm(fmt, args ...) dbg_m(DBG_M_HTM, fmt, ##args)
-#define dbg_wq(fmt, args ...) dbg_m(DBG_M_WQ, fmt, ##args)
-
-char *div3_cfgx_get_name(enum eDI_CFGX_IDX idx);
-bool div3_cfgx_get(unsigned int ch, enum eDI_CFGX_IDX idx);
-void div3_cfgx_set(unsigned int ch, enum eDI_CFGX_IDX idx, bool en);
-
-static inline struct di_data_l_s *get_datal(void)
-{
- if (getv3_dim_de_devp())
- return (struct di_data_l_s *)getv3_dim_de_devp()->data_l;
-
- PR_ERR("get_datal:xxx\n");
- return NULL;
-}
-
-static inline struct di_ch_s *get_chdata(unsigned int ch)
-{
- return &get_datal()->ch_data[ch];
-}
-
-static inline struct di_mng_s *get_bufmng(void)
-{
- return &get_datal()->mng;
-}
-
-static inline struct di_dbg_data *get_dbg_data(void)
-{
- return &get_datal()->dbg_data;
-}
-
-static inline struct di_hpre_s *get_hw_pre(void)
-{
- return &get_datal()->hw_pre;
-}
-
-static inline struct di_hpst_s *get_hw_pst(void)
-{
- return &get_datal()->hw_pst;
-}
-
-/****************************************
- * flg_hw_int
- * for hw set once
- ****************************************/
-static inline bool di_get_flg_hw_int(void)
-{
- return get_datal()->mng.flg_hw_int;
-}
-
-static inline void di_set_flg_hw_int(bool on)
-{
- get_datal()->mng.flg_hw_int = on;
-}
-
-/**********************
- *
- * reg log:
- *********************/
-static inline struct di_dbg_reg_log *get_dbg_reg_log(void)
-{
- return &get_datal()->dbg_data.reg_log;
-}
-
-#ifdef DIM_DEBUG_QUE_ERR
-static inline struct di_dbg_que_s *di_get_dbg_que(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].dbg_data.que;
-}
-#endif
-
-/**********************
- *
- * flg_wait_int
- *********************/
-static inline void di_pre_wait_irq_set(bool on)
-{
- get_hw_pre()->flg_wait_int = on;
-}
-
-static inline bool di_pre_wait_irq_get(void)
-{
- return get_hw_pre()->flg_wait_int;
-}
-
-static inline struct di_ores_s *get_orsc(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].rse_ori;
-}
-
-//static inline struct vframe_s **get_vframe_in(unsigned int ch)
-//static inline union dim_itf_u **get_vframe_in(unsigned int ch)
-static inline void **getv3_vframe_in(unsigned int ch)
-{
- return &get_orsc(ch)->vframe_in[0];
-}
-
-static inline struct vframe_s *get_vframe_in_dup(unsigned int ch)
-{
- return &get_orsc(ch)->vframe_in_dup[0];
-}
-
-static inline struct vframe_s *get_vframe_local(unsigned int ch)
-{
- return &get_orsc(ch)->vframe_local[0];
-}
-
-static inline struct vframe_s *get_vframe_post(unsigned int ch)
-{
- return &get_orsc(ch)->vframe_post[0];
-}
-
-static inline struct di_buf_s *get_buf_local(unsigned int ch)
-{
- return &get_orsc(ch)->di_buf_local[0];
-}
-
-static inline struct di_buf_s *get_buf_in(unsigned int ch)
-{
- return &get_orsc(ch)->di_buf_in[0];
-}
-
-static inline struct di_buf_s *get_buf_post(unsigned int ch)
-{
- return &get_orsc(ch)->di_buf_post[0];
-}
-
-static inline struct queue_s *get_queue(unsigned int ch)
-{
- return &get_orsc(ch)->queue[0];
-}
-
-static inline struct di_buf_pool_s *get_buf_pool(unsigned int ch)
-{
- return &get_orsc(ch)->di_buf_pool[0];
-}
-
-static inline struct di_pre_stru_s *get_pre_stru(unsigned int ch)
-{
- return &get_orsc(ch)->di_pre_stru;
-}
-
-static inline struct di_post_stru_s *get_post_stru(unsigned int ch)
-{
- return &get_orsc(ch)->di_post_stru;
-}
-
-static inline struct di_buffer *get_post_ins(unsigned int ch)
-{
- return &get_orsc(ch)->ins_post[0];
-}
-
-static inline enum eDI_SUB_ID get_current_channel(void)
-{
- return get_datal()->dbg_data.cur_channel;
-}
-
-static inline void set_current_channel(unsigned int channel)
-{
- get_datal()->dbg_data.cur_channel = channel;
-}
-
-static inline bool get_init_flag(unsigned char ch)
-{
- return get_bufmng()->init_flg[ch];
-}
-
-static inline void set_init_flag(unsigned char ch, bool on)
-{
- get_bufmng()->init_flg[ch] = on;
-}
-
-extern const unsigned int div3_ch2mask_table[DI_CHANNEL_MAX];
-/******************************************
- *
- * reg / unreg
- *
- *****************************************/
-static inline bool get_reg_flag(unsigned char ch)
-{
- unsigned int flg = get_bufmng()->reg_flg_ch;
- bool ret = false;
-
- if (div3_ch2mask_table[ch] & flg)
- ret = true;
-
- /*dim_print("%s:%d\n", __func__, ret);*/
- return ret;
-}
-
-static inline unsigned int get_reg_flag_all(void)
-{
- return get_bufmng()->reg_flg_ch;
-}
-
-static inline void set_reg_flag(unsigned char ch, bool on)
-{
- unsigned int flg = get_bufmng()->reg_flg_ch;
-
- if (on)
- get_bufmng()->reg_flg_ch = flg | div3_ch2mask_table[ch];
- else
- get_bufmng()->reg_flg_ch = flg & (~div3_ch2mask_table[ch]);
- /*dim_print("%s:%d\n", __func__, get_bufmng()->reg_flg_ch);*/
-}
-
-static inline struct dim_inter_s *get_dev_intf(unsigned int ch)
-{
- if (ch < DI_CHANNEL_NUB)
- //return &get_datal()->ch_data[ch].vfm;
- return &get_datal()->ch_data[ch].interf;
-
- PR_ERR("%s ch overflow %d\n", __func__, ch);
- return &get_datal()->ch_data[0].interf;
-}
-
-/******************************************
- *
- * trig unreg:
- * when unreg: set 1
- * when reg: set 0
- *****************************************/
-
-static inline bool get_flag_trig_unreg(unsigned char ch)
-{
- return get_bufmng()->trig_unreg[ch];
-}
-
-#if 0
-static inline unsigned int get_reg_flag_all(void)
-{
- return get_bufmng()->reg_flg_ch;
-}
-#endif
-
-static inline void set_flag_trig_unreg(unsigned char ch, bool on)
-{
- get_bufmng()->trig_unreg[ch] = on;
-}
-
-static inline bool get_hw_reg_flg(void)
-{
- return get_bufmng()->hw_reg_flg;
-}
-
-static inline void set_hw_reg_flg(bool on)
-{
- get_bufmng()->hw_reg_flg = on;
-}
-
-static inline bool get_or_act_flag(void)
-{
- return get_bufmng()->act_flg;
-}
-
-static inline void set_or_act_flag(bool on)
-{
- get_bufmng()->act_flg = on;
-}
-
-/*sum*/
-static inline void di_sum_set_l(unsigned int ch, enum eDI_SUM id,
- unsigned int val)
-{
- get_chdata(ch)->sum[id] = val;
-}
-
-static inline unsigned int di_sum_inc_l(unsigned int ch, enum eDI_SUM id)
-{
- get_chdata(ch)->sum[id]++;
- return get_chdata(ch)->sum[id];
-}
-
-static inline unsigned int di_sum_get_l(unsigned int ch, enum eDI_SUM id)
-{
- return get_chdata(ch)->sum[id];
-}
-
-/*sum get and put*/
-static inline unsigned int get_sum_g(unsigned int ch)
-{
- return get_datal()->ch_data[ch].sum_get;
-}
-
-static inline void sum_g_inc(unsigned int ch)
-{
- get_datal()->ch_data[ch].sum_get++;
-}
-
-static inline void sum_g_clear(unsigned int ch)
-{
- get_datal()->ch_data[ch].sum_get = 0;
-}
-
-static inline unsigned int get_sum_p(unsigned int ch)
-{
- return get_datal()->ch_data[ch].sum_put;
-}
-
-static inline void sum_p_inc(unsigned int ch)
-{
- get_datal()->ch_data[ch].sum_put++;
-}
-
-static inline void sum_p_clear(unsigned int ch)
-{
- get_datal()->ch_data[ch].sum_put = 0;
-}
-
-static inline struct dim_sum_s *get_sumx(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].sumx;
-}
-
-/*bypass_state*/
-static inline bool di_bypass_state_get(unsigned int ch)
-{
- return get_chdata(ch)->bypass_state;
-}
-
-static inline void di_bypass_state_set(unsigned int ch, bool on)
-{
- get_chdata(ch)->bypass_state = on;
-}
-
-#if 0
-static inline struct semaphore *get_sema(void)
-{
- return &getv3_dim_de_devp()->sema;
-}
-#endif
-
-static inline struct di_task *get_task(void)
-{
- return &get_bufmng()->tsk;
-}
-
-static inline struct di_timer_s *get_htimer(void)
-{
- return &get_bufmng()->tim;
-}
-
-/******************************************
- * pq ops
- *****************************************/
-
-static inline const struct pulldown_op_s *get_ops_pd(void)
-{
- return get_datal()->ops_pd;
-}
-
-static inline const struct detect3d_op_s *get_ops_3d(void)
-{
- return get_datal()->ops_3d;
-}
-
-static inline const struct nr_op_s *get_ops_nr(void)
-{
- return get_datal()->ops_nr;
-}
-
-static inline const struct mtn_op_s *get_ops_mtn(void)
-{
- return get_datal()->ops_mtn;
-}
-
-#if 0
-static inline struct di_ext_ops *get_ops_api(void)
-{
- return get_datal()->di_api;
-}
-#endif
-
-#define di_mpr(x) dimp_get(edi_mp_##x)
-
-/******************************************
- * module para for di
- *****************************************/
-
-static inline int dimp_get(enum eDI_MP_UI_T idx)
-{
- return get_datal()->mp_uit[idx];
-}
-
-static inline void dimp_set(enum eDI_MP_UI_T idx, int val)
-{
- get_datal()->mp_uit[idx] = val;
-}
-
-static inline int dimp_inc(enum eDI_MP_UI_T idx)
-{
- get_datal()->mp_uit[idx]++;
- return get_datal()->mp_uit[idx];
-}
-
-static inline int dimp_dec(enum eDI_MP_UI_T idx)
-{
- get_datal()->mp_uit[idx]--;
- return get_datal()->mp_uit[idx];
-}
-
-/******************************************
- * mm
- *****************************************/
-static inline struct di_mm_s *dim_mm_get(unsigned int ch)
-{
- return &get_datal()->mng.mm[ch];
-}
-
-static inline struct dim_mm_t_s *dim_mmt_get(void)
-{
- return &get_datal()->mng.mmt;
-}
-
-static inline unsigned long di_get_mem_start(unsigned int ch)
-{
- return get_datal()->mng.mm[ch].sts.mem_start;
-}
-
-static inline void di_set_mem_info(unsigned int ch,
- unsigned long mstart,
- unsigned int size)
-{
- get_datal()->mng.mm[ch].sts.mem_start = mstart;
- get_datal()->mng.mm[ch].sts.mem_size = size;
-}
-
-static inline unsigned int di_get_mem_size(unsigned int ch)
-{
- return get_datal()->mng.mm[ch].sts.mem_size;
-}
-
-#if 1
-/****************************************
- * pre hw ops
- ****************************************/
-static inline struct di_pre_stru_s *get_h_ppre(void)
-{
- return get_hw_pre()->ops.pres;
-}
-
-static inline void set_h_ppre(unsigned int ch)
-{
- get_hw_pre()->ops.pres = get_pre_stru(ch);
-}
-
-#endif
-
-static inline unsigned int dim_get_timerms(u64 check_timer)
-{
- return (unsigned int)(jiffies_to_msecs(jiffies_64 - check_timer));
-}
-
-/**/
-void div3_tout_int(struct di_time_out_s *tout, unsigned int thd);
-bool div3_tout_contr(enum eDI_TOUT_CONTR cmd, struct di_time_out_s *tout);
-extern const struct qued_ops_s qued_ops;
-
-#endif /*__DI_DATA_L_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_dbg.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-#include <linux/debugfs.h>
-
-#include "di_data.h"
-#include "di_dbg.h"
-
-#include "di_reg_tab.h"
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-#include "deinterlace_hw.h"
-#include "di_data_l.h"
-#include "di_que.h"
-#include "di_task.h"
-#include "di_prc.h"
-#include "di_pre.h"
-#include "di_post.h"
-#include "di_vfm_test.h"
-/********************************
- *trace:
- *******************************/
-#define CREATE_TRACE_POINTS
-#include "dim_trace.h"
-
-#undef TRACE_INCLUDE_PATH
-#undef TRACE_INCLUDE_FILE
-#define TRACE_INCLUDE_PATH .
-#define TRACE_INCLUDE_FILE dim_trace
-#include <trace/define_trace.h>
-
-/**********************/
-/* data get */
-static struct dentry **dich_get_dbgroot(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].dbg_rootx;
-}
-
-static struct dentry **dich_get_dbgroot_top(void)
-{
- return &get_datal()->dbg_root_top;
-}
-
-static int *di_get_plane(void)
-{
- return &get_datal()->plane[0];
-}
-
-static struct vframe_s *di_get_dbg_vframe_in(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].dbg_data.vfm_input;
-}
-
-static struct vframe_s **di_get_dbg_vframe_out(unsigned int ch)
-{
- return &get_datal()->ch_data[ch].dbg_data.pfm_out;
-}
-
-/********************************
- *timer:
- *******************************/
-
-u64 curv3_to_msecs(void)
-{
- u64 cur = sched_clock();
-
- do_div(cur, NSEC_PER_MSEC);
- return cur;
-}
-
-u64 curv3_to_usecs(void)/*2019*/
-{
- u64 cur = sched_clock();
-
- do_div(cur, NSEC_PER_USEC);
- return cur;
-}
-
-/********************************
- *trace:
- *******************************/
-
-static void trace_pre(unsigned int index, unsigned long ctime)
-{
- trace_dimv3_pre("PRE-IRQ-0", index, ctime);
-}
-
-static void trace_post(unsigned int index, unsigned long ctime)
-{
- trace_dimv3_post("POST-IRQ-1", index, ctime);
-}
-
-#define DI_TRACE_LIMIT 10000
-static void trace_pre_get(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pre_getxx("PRE-GET-01", index, ustime);
-}
-
-static void trace_pre_set(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pre_setxx("PRE-SET-01", index, ustime);
-}
-
-static void trace_pre_ready(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pre_ready("PRE-READY2", index, ustime);
-}
-
-static void trace_post_ready(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_ready("PST-READY3", index, ustime);
-}
-
-static void trace_post_get(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_getxx("PST-GET-04", index, ustime);
-}
-
-static void trace_post_get2(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_get2x("PST-GET-0a", index, ustime);
-}
-
-static void trace_post_set(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_setxx("PST-SET-05", index, ustime);
-}
-
-static void trace_post_irq(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_irxxx("PST-IRQ-06", index, ustime);
-}
-
-static void trace_post_doing(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_doing("PST-DOI-07", index, ustime);
-}
-
-static void trace_post_peek(unsigned int index)
-{
- u64 ustime;
-
- if (div3_get_disp_cnt() > DI_TRACE_LIMIT)
- return;
-
- ustime = curv3_to_usecs();
- trace_dimv3_pst_peekx("PST-PEEK-8", index, ustime);
-}
-
-const struct dim_tr_ops_s dimv3_tr_ops = {
- .pre = trace_pre,
- .post = trace_post,
-
- .pre_get = trace_pre_get,
- .pre_set = trace_pre_set,
- .pre_ready = trace_pre_ready,
- .post_ready = trace_post_ready,
- .post_get = trace_post_get,
- .post_get2 = trace_post_get2,
-
- .post_set = trace_post_set,
- .post_ir = trace_post_irq,
- .post_do = trace_post_doing,
- .post_peek = trace_post_peek,
-};
-
-static unsigned int seq_get_channel(struct seq_file *s)
-{
- int *pCh;
-
- pCh = (int *)s->private;
- return *pCh;
-}
-
-/********************************
- *debug register:
- *******************************/
-/* also see enum eDI_DBG_MOD */
-const char * const dbgv3_mode_name[] = {
- "REGB",
- "REGE",
- "UNREGB",
- "UNREGE",
- "PRE_SETB",
- "PRE_SETE",
- "PRE_DONEB",
- "PRE_DONEE",
- "PST_SETB",
- "PST_SETE",
- "PST_IRQB",
- "PST_IRQE",
- "PST_DB",
- "PST_DE",
- "PST_CH_CHG",
- "PST_TOUT",
- "RVB",
- "RVE",
- "PST_RESIZE"
-};
-
-const char *ddbgv3_get_mod_name(unsigned int mod)
-{
- if (mod >= eDI_DBG_MOD_END)
- return "nothing!";
-
- return dbgv3_mode_name[mod];
-}
-
-void ddbgv3_reg_save(unsigned int addr, unsigned int val,
- unsigned int st, unsigned int bw)
-{
- struct di_dbg_reg dbg_reg;
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
- unsigned int pos;
-
- if (!plog->en_reg)
- return;
- if (plog->en_notoverwrite && plog->overflow)
- return;
-
- pos = plog->pos;
-
- dbg_reg.addr = addr;
- dbg_reg.val = val;
- dbg_reg.st_bit = st;
- dbg_reg.b_w = bw;
- dbg_reg.res = 0;
-
- plog->log[pos].reg = dbg_reg;
- pos++;
- if (pos >= (K_DI_SIZE_REG_LOG - 1)) {
- if (plog->en_notoverwrite) {
- plog->overflow = 1;
-
- } else {
- pos = 0;
- plog->overflow = 1;
- }
- }
- plog->wsize++;
- plog->pos = pos;
-}
-
-/* mod also see: enum eDI_DBG_MOD */
-void dimv3_ddbg_mod_save(unsigned int mod, unsigned int ch, unsigned int cnt)
-{
- struct di_dbg_mod dbg_mod;
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
- unsigned int pos;
-#if 1
-/*--------------------------*/
- if (ch)
- hv3_dbg_reg_set(mod | 0x80000000);
- else
- hv3_dbg_reg_set(mod);
-/*--------------------------*/
-#endif
- if (!plog->en_mod)
- return;
- if (plog->en_notoverwrite && plog->overflow)
- return;
- pos = plog->pos;
-
- dbg_mod.lable = K_DI_LAB_MOD;
- dbg_mod.ch = ch;
- dbg_mod.mod = mod;
- dbg_mod.cnt = cnt;
- dbg_mod.res = 0;
-
- plog->log[pos].mod = dbg_mod;
- pos++;
- if (pos >= (K_DI_SIZE_REG_LOG - 1)) {
- if (plog->en_notoverwrite) {
- plog->overflow = 1;
-
- } else {
- pos = 0;
- plog->overflow = 1;
- }
- }
- plog->wsize++;
- plog->pos = pos;
-}
-
-#if 0
-void ddbgv3_sw(bool on)
-{
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
-
- plog->en = on;
-}
-#else
-
-void ddbgv3_sw(enum eDI_LOG_TYPE mode, bool on)
-{
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
-
- switch (mode) {
- case eDI_LOG_TYPE_ALL:
- plog->en_all = on;
- break;
- case eDI_LOG_TYPE_REG:
- plog->en_reg = on;
- break;
- case eDI_LOG_TYPE_MOD:
- plog->en_mod = on;
- break;
- default:
- PR_WARN("%s:mode overlow:%d\n", __func__, mode);
- break;
- }
-}
-#endif
-void ddbgv3_reg_clear(void)
-{
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
-
- memset(plog, 0, sizeof(struct di_dbg_reg_log));
- plog->en_notoverwrite = 1;
-}
-
-static int ddbg_log_reg_show(struct seq_file *seq, void *v)
-{
- struct di_dbg_reg_log *plog = get_dbg_reg_log();
- unsigned int pos;
- int i;
-
- if (plog->overflow)
- pos = K_DI_SIZE_REG_LOG;
- else
- pos = plog->pos;
-
- seq_printf(seq, "%s:pos=%d,overflow=%d, size=%d\n",
- __func__, plog->pos, plog->overflow, plog->wsize);
-
- for (i = 0; i < pos; i++) {
- if (plog->log[i].mod.lable == K_DI_LAB_MOD) {
- seq_printf(seq, "%d,ch[%d]:cnt[%d]:%s\n",
- i,
- plog->log[i].mod.ch,
- plog->log[i].mod.cnt,
- ddbgv3_get_mod_name(plog->log[i].mod.mod));
- continue;
- }
-
- seq_printf(seq, "\t0x%x,0x%x,%d,%d\n",
- plog->log[i].reg.addr,
- plog->log[i].reg.val,
- plog->log[i].reg.st_bit,
- plog->log[i].reg.b_w);
- }
-
- return 0;
-}
-
-static ssize_t ddbg_log_reg_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, val;
- char buf[80];
- int ret;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- switch (ret) {
- case 2:
- if (item == 0 && val == 0) {
- /*help info:*/
- pr_info("help:\n");
- /*all:*/
- pr_info("\t1 0 : log all disable\n");
- pr_info("\t1 1 : log all enable\n");
- /*reg:*/
- pr_info("\t2 0 : log reg disable\n");
- pr_info("\t2 1 : log reg enable\n");
- /*mod:*/
- pr_info("\t3 0 : log mod disable\n");
- pr_info("\t3 1 : log mod enable\n");
- /*clean:*/
- pr_info("\t4 0 : clear\n");
- break;
- }
- switch (item) {
- case 1:
- case 2:
- case 3:
- pr_info("ddbgv3_sw: %d\n", val);
- ddbgv3_sw(item, val);
- break;
- case 4:
- pr_info("ddbgv3_reg_clear\n");
- ddbgv3_reg_clear();
- break;
- };
-
- break;
- default:
- pr_info("err:please enter: 0 x for help\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/**********************/
-int seq_file_vframe(struct seq_file *seq, void *v, struct vframe_s *pVfm)
-{
- struct canvas_config_s *pcvs;
-
- pcvs = &pVfm->canvas0_config[0];
- if (!pVfm) {
- seq_puts(seq, "war: dump vframe NULL\n");
- return 0;
- }
- seq_printf(seq, "%-15s:0x%p\n", "addr", pVfm);
- seq_printf(seq, "%-15s:%d\n", "index", pVfm->index);
- seq_printf(seq, "%-15s:%d\n", "index_disp", pVfm->index_disp);
- seq_printf(seq, "%-15s:%d\n", "omx_index", pVfm->omx_index);
- seq_printf(seq, "%-15s:0x%x\n", "type", pVfm->type);
- seq_printf(seq, "%-15s:0x%x\n", "type_backup", pVfm->type_backup);
- seq_printf(seq, "%-15s:0x%x\n", "type_original", pVfm->type_original);
- seq_printf(seq, "%-15s:%d\n", "blend_mode", pVfm->blend_mode);
- seq_printf(seq, "%-15s:%d\n", "duration", pVfm->duration);
- seq_printf(seq, "%-15s:%d\n", "duration_pull", pVfm->duration_pulldown);
- seq_printf(seq, "%-15s:%d\n", "pts", pVfm->pts);
-
- seq_printf(seq, "%-15s:%lld\n", "pts_us64", pVfm->pts_us64);
- seq_printf(seq, "%-15s:%d\n", "next_vf_pts_valid",
- pVfm->next_vf_pts_valid);
- seq_printf(seq, "%-15s:%d\n", "next_vf_pts", pVfm->next_vf_pts);
- seq_printf(seq, "%-15s:%d\n", "disp_pts", pVfm->disp_pts);
- seq_printf(seq, "%-15s:%lld\n", "disp_pts_us64", pVfm->disp_pts_us64);
- seq_printf(seq, "%-15s:%lld\n", "timestamp", pVfm->timestamp);
- seq_printf(seq, "%-15s:%d\n", "flag", pVfm->flag);
- seq_printf(seq, "%-15s:0x%x\n", "canvas0Addr", pVfm->canvas0Addr);
- seq_printf(seq, "%-15s:0x%x\n", "canvas1Addr", pVfm->canvas1Addr);
- seq_printf(seq, "%-15s:0x%x\n", "compHeadAddr", pVfm->compHeadAddr);
- seq_printf(seq, "%-15s:0x%x\n", "compBodyAddr", pVfm->compBodyAddr);
- seq_printf(seq, "%-15s:%d\n", "plane_num", pVfm->plane_num);
-
- seq_printf(seq, "%-15s:%d\n", "bufWidth", pVfm->bufWidth);
- seq_printf(seq, "%-15s:%d\n", "width", pVfm->width);
- seq_printf(seq, "%-15s:%d\n", "height", pVfm->height);
- seq_printf(seq, "%-15s:%d\n", "compWidth", pVfm->compWidth);
- seq_printf(seq, "%-15s:%d\n", "compHeight", pVfm->compHeight);
- seq_printf(seq, "%-15s:%d\n", "ratio_control", pVfm->ratio_control);
- seq_printf(seq, "%-15s:%d\n", "bitdepth", pVfm->bitdepth);
- seq_printf(seq, "%-15s:%d\n", "signal_type", pVfm->signal_type);
-
- /*
- * bit 29: present_flag
- * bit 28-26: video_format
- * "component", "PAL", "NTSC", "SECAM",
- * "MAC", "unspecified"
- * bit 25: range "limited", "full_range"
- * bit 24: color_description_present_flag
- * bit 23-16: color_primaries
- * "unknown", "bt709", "undef", "bt601",
- * "bt470m", "bt470bg", "smpte170m", "smpte240m",
- * "film", "bt2020"
- * bit 15-8: transfer_characteristic
- * "unknown", "bt709", "undef", "bt601",
- * "bt470m", "bt470bg", "smpte170m", "smpte240m",
- * "linear", "log100", "log316", "iec61966-2-4",
- * "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
- * "smpte-st-2084", "smpte-st-428"
- * bit 7-0: matrix_coefficient
- * "GBR", "bt709", "undef", "bt601",
- * "fcc", "bt470bg", "smpte170m", "smpte240m",
- * "YCgCo", "bt2020nc", "bt2020c"
- */
- seq_printf(seq, "%-15s:0x%x\n", "orientation", pVfm->orientation);
- seq_printf(seq, "%-15s:0x%x\n", "video_angle", pVfm->video_angle);
- seq_printf(seq, "%-15s:0x%x\n", "source_type", pVfm->source_type);
-
- seq_printf(seq, "%-15s:0x%x\n", "phase", pVfm->phase);
- seq_printf(seq, "%-15s:0x%x\n", "source_mode", pVfm->source_mode);
- seq_printf(seq, "%-15s:0x%x\n", "sig_fmt", pVfm->sig_fmt);
- seq_printf(seq, "%-15s:0x%x\n", "trans_fmt", pVfm->trans_fmt);
-
- seq_printf(seq, "%-15s:0x%x\n", "mode_3d_enable",
- pVfm->mode_3d_enable);
-
- seq_printf(seq, "%-15s:0x%p\n", "early_process_fun",
- pVfm->early_process_fun);
- seq_printf(seq, "%-15s:0x%p\n", "process_fun",
- pVfm->early_process_fun);
- seq_printf(seq, "%-15s:0x%p\n", "private_data",
- pVfm->early_process_fun);
-
-#if 1
- /* vframe properties */
-
-#endif
-
- /* pixel aspect ratio */
- seq_printf(seq, "%-15s:%d\n", "pixel_ratio", pVfm->pixel_ratio);
-
- /* ready from decode on jiffies_64 */
- seq_printf(seq, "%-15s:%d\n", "use_cnt", atomic_read(&pVfm->use_cnt));
- seq_printf(seq, "%-15s:%d\n", "frame_dirty", pVfm->frame_dirty);
- /*
- *prog_proc_config:
- *1: process p from decoder as filed
- *0: process p from decoder as frame
- */
- seq_printf(seq, "%-15s:0x%x\n", "prog_proc_config",
- pVfm->prog_proc_config);
- /* used for indicate current video is motion or static */
- seq_printf(seq, "%-15s:%d\n", "combing_cur_lev",
- pVfm->combing_cur_lev);
- /*canvas:*/
- seq_printf(seq, "%-15s:0x%x\n", "phy_addr",
- pcvs->phy_addr);
- seq_printf(seq, "%-15s:%d\n", "width",
- pcvs->width);
- seq_printf(seq, "%-15s:%d\n", "height",
- pcvs->height);
- seq_printf(seq, "%-15s:%d\n", "block_mode",
- pcvs->block_mode);
-
- return 0;
-}
-
-/**********************/
-/* debug input vframe */
-/**********************/
-void didbgv3_vframe_in_copy(unsigned int ch, struct vframe_s *pvfm)
-{
- struct vframe_s *pvfm_t;
-
- if (!div3_cfgx_get(ch, eDI_DBG_CFGX_IDX_VFM_IN))
- return;
-
- pvfm_t = di_get_dbg_vframe_in(ch);
-
- memcpy(pvfm_t, pvfm, sizeof(struct vframe_s));
-}
-
-static int seq_file_vframe_in_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- if (!div3_cfgx_get(ch, eDI_DBG_CFGX_IDX_VFM_IN)) {
- seq_puts(seq, "war: cfg[eDI_DBG_CFGX_IDX_VFM_IN] disable\n");
- return 0;
- }
-
- seq_file_vframe(seq, v, di_get_dbg_vframe_in(ch));
-
- return 0;
-}
-
-/***********************/
-/* debug output vframe */
-/***********************/
-void didbgv3_vframe_out_save(struct vframe_s *pvfm)
-{
- unsigned int ch;
- struct vframe_s **pvfm_t;
-
- ch = DI_SUB_ID_S0;
- if (!div3_cfgx_get(ch, eDI_DBG_CFGX_IDX_VFM_OT))
- return;
-
- pvfm_t = di_get_dbg_vframe_out(ch);
- *pvfm_t = pvfm;
-}
-
-static int seq_file_vframe_out_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- if (!div3_cfgx_get(ch, eDI_DBG_CFGX_IDX_VFM_OT)) {
- seq_puts(seq, "war: cfg[eDI_DBG_CFGX_IDX_VFM_OT] disable\n");
- return 0;
- }
-
- seq_file_vframe(seq, v, *di_get_dbg_vframe_out(ch));
-
- return 0;
-}
-/**********************************************************
- * debug display vframe
- *********************************************************/
-static int vframe_pstready_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- int itmp;
- struct di_buf_s *p = NULL;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "\t---------------------------";
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(ch, QUE_POST_READY, &tmpa[0], &psize);
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- seq_file_vframe(seq, v, p->vframe);
- seq_printf(seq, "%s\n", splt);
- }
-
- return 0;
-}
-
-/**********************************************************
- * debug display vframe
- *********************************************************/
-static int vframe_preready_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- int itmp;
- struct di_buf_s *p = NULL;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "\t---------------------------";
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
- seq_printf(seq, "pre_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- seq_file_vframe(seq, v, p->vframe);
- seq_printf(seq, "%s\n", splt);
- }
-
- return 0;
-}
-
-/**********************/
-/* debug vframe type */
-/**********************/
-const struct di_vframe_type_info div3_vtype_info[] = {
- {"interlace", VIDTYPE_INTERLACE, NULL},
- {"bottom", VIDTYPE_INTERLACE_BOTTOM, NULL},
-
- {"interllace first", VIDTYPE_INTERLACE_FIRST, NULL},
- {"mvc", VIDTYPE_MVC, NULL},
- {"no video en", VIDTYPE_NO_VIDEO_ENABLE, NULL},
- {"v422", VIDTYPE_VIU_422, NULL},
- {"field", VIDTYPE_VIU_FIELD, NULL},
-
- {"single plane", VIDTYPE_VIU_SINGLE_PLANE, NULL},
- {"v444", VIDTYPE_VIU_444, NULL},
- {"nv21", VIDTYPE_VIU_NV21, NULL},
- {"vscale disable", VIDTYPE_VSCALE_DISABLE, NULL},
- {"cvs toggle", VIDTYPE_CANVAS_TOGGLE, NULL},
- {"pre interlace", VIDTYPE_PRE_INTERLACE, NULL},
- {"high run", VIDTYPE_HIGHRUN, NULL},
- {"compress", VIDTYPE_COMPRESS, NULL},
- {"pic", VIDTYPE_PIC, NULL},
- {"scatter", VIDTYPE_SCATTER, NULL},
- {"vd2", VIDTYPE_VD2, NULL},
- {"compress loss", VIDTYPE_COMPRESS_LOSS, NULL},
- {"comb", VIDTYPE_COMB_MODE, NULL},
- {"tb detect", TB_DETECT_MASK, NULL},
-
- /*finish*/
- {NULL, TABLE_FLG_END, NULL}
-};
-
-static void didbg_vtype_set(unsigned int type)
-{
- get_datal()->dbg_data.vframe_type = type;
-}
-
-static unsigned int didbg_vtype_get(void)
-{
- return get_datal()->dbg_data.vframe_type;
-}
-
-static int seqv3_file_vtype_show(struct seq_file *seq, void *v)
-{
- unsigned int vtype;
- int i;
- unsigned int mask;
-
- i = 0;
- vtype = didbg_vtype_get();
-
- seq_printf(seq, "%s:vtype[0x%x]\n", __func__, vtype);
-
- while (div3_vtype_info[i].name) {
- mask = div3_vtype_info[i].mask;
-
- if ((vtype & mask) == mask) {
- seq_printf(seq, "\t%-15s:y\n", div3_vtype_info[i].name);
- } else {
- if (div3_vtype_info[i].other) {
- seq_printf(seq, "\t%-15s:yes\n",
- div3_vtype_info[i].other);
- } else {
- seq_printf(seq, "\t%-15s:no\n",
- div3_vtype_info[i].name);
- }
- }
- i++;
- }
-
- return 0;
-}
-
-ssize_t seqv3_file_vtype_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- char buf[20];
- int ret;
-
- unsigned int vtype;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
- /*reg, bit, width, val*/
- #if 1
- ret = kstrtouint(buf, 0, &vtype);
- if (ret) {
- pr_info("war:please enter vtype\n");
- return 0;
- }
- pr_info("save type:0x%x", vtype);
- didbg_vtype_set(vtype);
- #else
-
- ret = sscanfxxx(buf, "%x", &vtype);
-
- /*--------------------------*/
-
- switch (ret) {
- case 1:
- pr_info("save type:0x%x", vtype);
- didbg_vtype_set(vtype);
- break;
- default:
- pr_info("war:please enter vtype\n");
- break;
- }
- #endif
- return count;
-}
-
-/**************************************
- *
- * show vframe current
- *
- **************************************/
-static int seq_file_curr_vframe_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
- struct di_buf_s *p = NULL;
- struct vframe_s *pvfm;
- char *splt = "---------------------------";
- char *splt2 = "-------------";
- int itmp;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* post_doing_list */
- /********************************/
- seq_puts(seq, "vfm for: post_doing_list:\n");
- //queue_for_each_entry(p, ch, QUEUE_POST_DOING, list) {
- div3_que_list(ch, QUE_POST_DOING, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- pvfm = p->vframe;
- seq_file_vframe(seq, v, pvfm);
- seq_printf(seq, "%s\n", splt2);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* pre_ready_list */
- /********************************/
- seq_puts(seq, "pre_ready_list:\n");
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
-
- pvfm = p->vframe;
- seq_file_vframe(seq, v, pvfm);
- seq_printf(seq, "%s\n", splt2);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(ch, QUE_POST_READY, &tmpa[0], &psize);
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- pvfm = p->vframe;
- seq_file_vframe(seq, v, pvfm);
- seq_printf(seq, "%s\n", splt2);
- }
- seq_printf(seq, "%s\n", splt);
-
- /********************************/
- /* display_list */
- /********************************/
- seq_puts(seq, "display_list:\n");
- queue_for_each_entry(p, ch, QUEUE_DISPLAY, list) {
- pvfm = p->vframe;
- seq_file_vframe(seq, v, pvfm);
- seq_printf(seq, "%s\n", splt2);
- }
- seq_printf(seq, "%s\n", splt);
-
- return 0;
-}
-
-/**************************************
- *
- * summmary variable
- *
- **************************************/
-static int seq_file_sum_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
- char *sname;
- unsigned int val;
- unsigned int tsize;
- int i;
-
- ch = seq_get_channel(seq);
-
- tsize = div3_sum_get_tab_size();/*ARRAY_SIZE(di_sum_tab);*/
-
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
- for (i = 0; i < tsize; i++) {
- if (!div3_sum_check(ch, i))
- continue;
- div3_sum_get_info(ch, i, &sname, &val);
- seq_printf(seq, "\t%-2d:%-15s:%d\n", i, sname, val);
- }
-
- seq_printf(seq, "%s:finish\n", __func__);
-
- return 0;
-}
-
-/********************************/
-/* state */
-/********************************/
-
-static int seq_file_state_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- dimv3_state_show(seq, v, ch);
-
- seq_printf(seq, "%s:%s\n", "hw_timer", dimv3_htr_get_stsname());
- return 0;
-}
-
-static int seq_file_mif_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- dimv3_dump_mif_size_state_show(seq, v, ch);
-
- return 0;
-}
-
-/********************************/
-/* qued */
-/********************************/
-static int dim_qued_show(struct seq_file *s, void *what)
-{
- int i;
- int *pCh;
- struct di_data_l_s *pdt = get_datal();
- struct di_ch_s *pchd;
-
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "---------------------------";
-
- pCh = (int *)s->private;
-
- pchd = get_chdata(*pCh);
- if (!pdt || !pchd) {
- seq_printf(s, "%s warn:1 do nothing\n", __func__);
- return 0;
- }
-
- /********************************/
- /* free_list */
- /********************************/
- qued_ops.list(pchd, QUED_T_FREE, &tmpa[0], &psize);
- seq_printf(s, "free_list (max %d) (crr %d):\n",
- DIM_K_VFM_NUM, psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
- /********************************/
- /* IN */
- /********************************/
- qued_ops.list(pchd, QUED_T_IN, &tmpa[0], &psize);
- seq_printf(s, "in_list (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
- /********************************/
- /* PRE */
- /********************************/
- qued_ops.list(pchd, QUED_T_PRE, &tmpa[0], &psize);
- seq_printf(s, "pre list (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
- /********************************/
- /* recycle */
- /********************************/
- qued_ops.list(pchd, QUED_T_RECYCL, &tmpa[0], &psize);
- seq_printf(s, "recycle (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
-
- /********************************/
- /* QUED_T_IS_IN */
- /********************************/
- qued_ops.list(pchd, QUED_T_IS_IN, &tmpa[0], &psize);
- seq_printf(s, "is in (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
-
- /********************************/
- /* QUED_T_IS_FREE */
- /********************************/
- qued_ops.list(pchd, QUED_T_IS_FREE, &tmpa[0], &psize);
- seq_printf(s, "IS_FREE (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
-
- /********************************/
- /* QUED_T_IS_PST_FREE */
- /********************************/
- qued_ops.list(pchd, QUED_T_IS_PST_FREE, &tmpa[0], &psize);
- seq_printf(s, "IS_PST_FREE (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
- /********************************/
- /* QUED_T_IS_PST_DOBEF */
- /********************************/
- qued_ops.list(pchd, QUED_T_IS_PST_DOBEF, &tmpa[0], &psize);
- seq_printf(s, "IS_PST_DOBEF (crr %d):\n", psize);
- for (i = 0; i < psize; i++)
- seq_printf(s, "\t%2d,\n", tmpa[i]);
-
- seq_printf(s, "%s\n", splt);
-
- return 0;
-}
-
-/********************************/
-#define DEFINE_SEQ_SHOW_ONLY(__name) \
-static int __name ## _open(struct inode *inode, struct file *file) \
-{ \
- return single_open(file, __name ## _show, inode->i_private); \
-} \
- \
-static const struct file_operations __name ## _fops = { \
- .owner = THIS_MODULE, \
- .open = __name ## _open, \
- .read = seq_read, \
- .llseek = seq_lseek, \
- .release = single_release, \
-}
-
-/*--------------------------*/
-#if 1
-/*note: this define can't used for x*/
-#define DEFINE_SEQ_SHOW_STORE(__name) \
-static int __name ## _open(struct inode *inode, struct file *file) \
-{ \
- return single_open(file, __name ## _show, inode->i_private); \
-} \
- \
-static const struct file_operations __name ## _fops = { \
- .owner = THIS_MODULE, \
- .open = __name ## _open, \
- .read = seq_read, \
- .write = __name ## _store, \
- .llseek = seq_lseek, \
- .release = single_release, \
-}
-#endif
-/*--------------------------*/
-#define DEFINE_SHOW_STORE(__name) \
-static const struct file_operations __name ## _fops = { \
- .owner = THIS_MODULE, \
- .open = simple_open, \
- .read = __name ## _show, \
- .write = __name ## _store, \
-}
-
-/*--------------------------*/
-#define DEFINE_STORE_ONLY(__name) \
-static const struct file_operations __name ## _fops = { \
- .owner = THIS_MODULE, \
- .open = simple_open, \
- .read = NULL, \
- .write = __name ## _store, \
-}
-
-/**********************/
-
-static int rcfgx_show(struct seq_file *s, void *what)
-{
- int i;
- int *pCh;
-
- pCh = (int *)s->private;
-
- seq_printf(s, "%s:ch[%d]\n", __func__, *pCh);
-
- for (i = eDI_CFGX_BEGIN; i < eDI_DBG_CFGX_END; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n", i,
- div3_cfgx_get_name(i),
- div3_cfgx_get(*pCh, i));
- }
-
- return 0;
-}
-
-/*************************************************************/
-static ssize_t wcfgx_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, val;
- char buf[80];
- int ret;
- int *pCh;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pCh = (int *)file->private_data;
- pr_info("%s:ch[%d]\n", __func__, *pCh);
-
- switch (ret) {
- case 2:
- if ((item <= eDI_CFGX_BEGIN) ||
- (item >= eDI_DBG_CFGX_END)) {
- pr_info("war:cfg_item is overflow[%d,%d]:%d\n",
- eDI_CFGX_BEGIN,
- eDI_DBG_CFGX_END,
- item);
- break;
- }
- if (val > 1)
- pr_info("war:cfg value[%d] is not bool\n", val);
-
- pr_info("change cfg:%s\n", div3_cfgx_get_name(item));
- pr_info("\t%d -> %d\n", div3_cfgx_get(*pCh, item), val);
- div3_cfgx_set(*pCh, item, val);
- break;
- default:
- pr_info("err:please enter: cfg_item, value(bool)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/***********************************************
- *
- ***********************************************/
-ssize_t keepv3_buf_clear_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- char buf[20];
- int ret;
-
- unsigned int ch;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
- /*reg, bit, width, val*/
-
- ret = kstrtouint(buf, 0, &ch);
- if (ret) {
- pr_info("war:please enter ch\n");
- return 0;
- }
- pr_info("ch:%d", ch);
-
- if (ch >= DI_CHANNEL_NUB) {
- PR_ERR("%s:ch is overflow %d\n", __func__, ch);
- return 0;
- }
-
- dimv3_dbg_release_keep_all(ch);
-
- return count;
-}
-
-/***************************************************************
- *
- * cfg top
- *
- ***************************************************************/
-static int cfgt_help_show(struct seq_file *s, void *what)
-{
- seq_puts(s, "cat list\n");
- seq_printf(s, "\t%-10s:%s\n", "cfg_ai", "all cfg infor");
- seq_printf(s, "\t%-10s:%s\n", "cfg_av", "all cfg val");
- seq_printf(s, "\t%-10s:%s\n", "cfg_one", "sel val or infor");
- seq_printf(s, "\t%-10s:%s\n", "cfg_sel", "sel infor");
- seq_puts(s, "echo list\n");
-
- seq_printf(s, "\t%-10s:%s\n", "val > cfgw_one",
- "change cfg that have sel");
- seq_printf(s, "\t%-10s:%s\n", "index val > cfgw_index",
- "change cfg by index");
- seq_printf(s, "\t%-10s:%s\n", "mode sel(0/1) index > cfgw_sel",
- "change sel");
-
- return 0;
-}
-
-/*cfg_ai*/
-static int cfgt_itme_all_show(struct seq_file *s, void *what)
-{
- div3_cfgt_show_item_all(s);
- return 0;
-}
-
-/*cfg_av*/
-static int cfgt_val_all_show(struct seq_file *s, void *what)
-{
- div3_cfgt_show_val_all(s);
- return 0;
-}
-
-/*cfg_one*/
-static int cfgt_one_show(struct seq_file *s, void *what)
-{
- if (get_datal()->cfg_dbg_mode)
- div3_cfgt_show_item_sel(s);
- else
- div3_cfgt_show_val_sel(s);
- return 0;
-}
-
-/*cfg_sel*/
-static int cfgt_sel_show(struct seq_file *s, void *what)
-{
- unsigned int i;
-
- i = get_datal()->cfg_sel;
- seq_printf(s, "mode[%d]:index[%d]\n",
- get_datal()->cfg_dbg_mode, i);
-
- if (!div3_cfg_top_check(i))
- return 0;
- seq_printf(s, "%s\n", div3_cfg_top_get_name(i));
-
- return 0;
-}
-
-static ssize_t cfgt_sel_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int sel, index;
- char buf[80];
- int ret;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &sel, &index);
-
- switch (ret) {
- case 2:
- div3_cfgt_set_sel(sel, index);
- break;
- default:
- pr_info("err:please enter: cfg_item, index\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-static ssize_t cfgtw_id_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int index, val;
- char buf[80];
- int ret;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &index, &val);
-
- switch (ret) {
- case 2:
- if (!div3_cfg_top_check(index))
- break;
- pr_info("%s:%d->%d\n",
- div3_cfg_top_get_name(index),
- div3_cfg_top_get(index),
- val);
- div3_cfg_top_set(index, val);
- break;
- default:
- pr_info("err:please enter: cfg_item, index\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-static ssize_t cfgt_one_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int index, val;
- char buf[80];
- int ret;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = kstrtouint(buf, 0, &val);
- if (ret) {
- pr_info("war:please enter val\n");
- return 0;
- }
- index = get_datal()->cfg_sel;
- if (!div3_cfg_top_check(index))
- return count;
-
- pr_info("%s:%d->%d\n",
- div3_cfg_top_get_name(index),
- div3_cfg_top_get(index),
- val);
- div3_cfg_top_set(index, val);
-
- return count;
-}
-
-/*************************************************************/
-
-/***************************************************************
- * parameter show and store for top : DI
- **************************************************************/
-static int mpr_di_show(struct seq_file *s, void *what)
-{
- int i;
-
- seq_printf(s, "%s:\n", __func__);
-
- for (i = eDI_MP_SUB_DI_B; i < eDI_MP_SUB_DI_E; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n",
- i - eDI_MP_SUB_DI_B,
- div3_mp_uit_get_name(i),
- dimp_get(i));
- }
-
- return 0;
-}
-
-static ssize_t mpw_di_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, rid;
- char buf[80];
- int ret, val;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pr_info("%s:\n", __func__);
-
- switch (ret) {
- case 2:
- /*check []*/
- if (item >= (eDI_MP_SUB_DI_E - eDI_MP_SUB_DI_B)) {
- PR_WARN("index is overflow[%d,%d]:%d\n",
- 0,
- eDI_MP_SUB_DI_E - eDI_MP_SUB_DI_B,
- item);
- break;
- }
- rid = item + eDI_MP_SUB_DI_B;
- pr_info("change mp :%s\n",
- div3_mp_uit_get_name(rid));
- pr_info("\t%d -> %d\n", dimp_get(rid), val);
- dimp_set(rid, val);
- break;
- default:
- PR_ERR("please enter: id, value(int)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/***************************************************************
- * parameter show and store for top : nr
- **************************************************************/
-static int mpr_nr_show(struct seq_file *s, void *what)
-{
- int i;
-
- seq_printf(s, "%s:\n", __func__);
-
- for (i = eDI_MP_SUB_NR_B; i < eDI_MP_SUB_NR_E; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n",
- i - eDI_MP_SUB_NR_B,
- div3_mp_uit_get_name(i),
- dimp_get(i));
- }
-
- return 0;
-}
-
-static ssize_t mpw_nr_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, rid;
- char buf[80];
- int ret, val;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pr_info("%s:\n", __func__);
-
- switch (ret) {
- case 2:
- /*check []*/
- if (item >= (eDI_MP_SUB_NR_E - eDI_MP_SUB_NR_B)) {
- PR_WARN("index is overflow[%d,%d]:%d\n",
- 0,
- eDI_MP_SUB_NR_E - eDI_MP_SUB_NR_B,
- item);
- break;
- }
- rid = item + eDI_MP_SUB_NR_B;
- pr_info("change mp:%s\n",
- div3_mp_uit_get_name(rid));
- pr_info("\t%d -> %d\n", dimp_get(rid), val);
- dimp_set(rid, val);
- break;
- default:
- PR_ERR("please enter: id, value(int)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/***************************************************************
- * parameter show and store for top : pulldown
- **************************************************************/
-static int mpr_pd_show(struct seq_file *s, void *what)
-{
- int i;
-
- seq_printf(s, "%s:\n", __func__);
-
- for (i = eDI_MP_SUB_PD_B; i < eDI_MP_SUB_PD_E; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n",
- i - eDI_MP_SUB_PD_B,
- div3_mp_uit_get_name(i),
- dimp_get(i));
- }
-
- return 0;
-}
-
-static ssize_t mpw_pd_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, rid;
- char buf[80];
- int ret, val;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pr_info("%s:\n", __func__);
-
- switch (ret) {
- case 2:
- /*check []*/
- if (item >= (eDI_MP_SUB_PD_E - eDI_MP_SUB_PD_B)) {
- PR_WARN("index is overflow[%d,%d]:%d\n",
- 0,
- eDI_MP_SUB_PD_E - eDI_MP_SUB_PD_B,
- item);
- break;
- }
- rid = item + eDI_MP_SUB_PD_B;
- pr_info("change mp:%s\n",
- div3_mp_uit_get_name(rid));
- pr_info("\t%d -> %d\n", dimp_get(rid), val);
- dimp_set(rid, val);
- break;
- default:
- PR_ERR("please enter: id, value(int)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/***************************************************************
- * parameter show and store for top : mtn
- **************************************************************/
-static int mpr_mtn_show(struct seq_file *s, void *what)
-{
- int i;
-
- seq_printf(s, "%s:\n", __func__);
-
- for (i = eDI_MP_SUB_MTN_B; i < eDI_MP_SUB_MTN_E; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n",
- i - eDI_MP_SUB_MTN_B,
- div3_mp_uit_get_name(i),
- dimp_get(i));
- }
-
- return 0;
-}
-
-static ssize_t mpw_mtn_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, rid;
- char buf[80];
- int ret, val;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pr_info("%s:\n", __func__);
-
- switch (ret) {
- case 2:
- /*check []*/
- if (item >= (eDI_MP_SUB_MTN_E - eDI_MP_SUB_MTN_B)) {
- PR_WARN("index is overflow[%d,%d]:%d\n",
- 0,
- eDI_MP_SUB_MTN_E - eDI_MP_SUB_MTN_B,
- item);
- break;
- }
- rid = item + eDI_MP_SUB_MTN_B;
- pr_info("change mp:%s\n",
- div3_mp_uit_get_name(rid));
- pr_info("\t%d -> %d\n", dimp_get(rid), val);
- dimp_set(rid, val);
- break;
- default:
- PR_ERR("please enter: id, value(int)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-/**********************/
-static int mpxr_show(struct seq_file *s, void *what)
-{
- int i;
- int *pCh;
-
- pCh = (int *)s->private;
-
- seq_printf(s, "%s:ch[%d]\n", __func__, *pCh);
-
- for (i = eDI_MP_UIX_BEGIN; i < eDI_MP_UIX_END; i++) {
- seq_printf(s, "\tidx[%2d]:%-15s:%d\n", i,
- div3_mp_uix_get_name(i),
- div3_mp_uix_get(*pCh, i));
- }
-
- return 0;
-}
-
-/*************************************************************/
-static ssize_t mpxw_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int item, val;
- char buf[80];
- int ret;
- int *pCh;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i", &item, &val);
-
- pCh = (int *)file->private_data;
- pr_info("%s:ch[%d]\n", __func__, *pCh);
-
- switch (ret) {
- case 2:
- if ((item <= eDI_MP_UIX_BEGIN) ||
- (item >= eDI_MP_UIX_END)) {
- PR_WARN("mpxw is overflow[%d,%d]:%d\n",
- eDI_MP_UIX_BEGIN,
- eDI_MP_UIX_END,
- item);
- break;
- }
-
- pr_info("change mp ch[%d]:%s\n", *pCh,
- div3_mp_uix_get_name(item));
- pr_info("\t%d -> %d\n", div3_mp_uix_get(*pCh, item), val);
- div3_mp_uix_set(*pCh, item, val);
- break;
- default:
- PR_ERR("please enter: mpxw, value(unsigned int)\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-static ssize_t buf_cnt_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- int w, h, pflg, mc;
- char buf[80];
- int ret, cnt_flg;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %i %i %i", &w, &h, &pflg, &mc);
-
- pr_info("%s:\n", __func__);
- cnt_flg = 0;
- switch (ret) {
- case 2:
- cnt_flg = 1;
- pflg = 0;
- mc = 1;
- break;
- case 3:
- cnt_flg = 1;
- mc = 1;
- break;
- case 4:
- cnt_flg = 1;
- break;
- default:
- PR_ERR("please enter: w, h, pflg, mc\n");
- return -EINVAL;
- }
-
- if (cnt_flg)
- div3_cnt_buf(w, h, pflg, mc, 1, 1);
- return count;
-}
-
-/**********************/
-void dbgv3_f_post_disable(unsigned int para)
-{
- dimhv3_disable_post_deinterlace_2();
-}
-
-void dbgv3_f_trig_task(unsigned int para)
-{
- taskv3_send_ready();
-}
-
-void dbg_f_trig_eos(unsigned int para)
-{
-#ifdef TST_NEW_INS_INTERFACE
- if (para)
- tst_new_trig_eos(true);
- else
- tst_new_trig_eos(false);
-#endif
-}
-
-const struct di_dbg_func_s div3_func_tab[] = {
- {eDI_DBG_F_00, dbgv3_f_post_disable,
- "dimhv3_disable_post_deinterlace_2", "no para"},
- {eDI_DBG_F_01, dbgv3_f_trig_task,
- "trig task", "no para"},
- {eDI_DBG_F_02, dprev3_dbg_f_trig,
- "trig pre flow debug", "bit[4]:ddebug on/off;bi[3:0]:cnt"},
- {eDI_DBG_F_03, dpstv3_dbg_f_trig,
- "trig post flow debug", "bit[4]:ddebug on/off;bi[3:0]:cnt"},
- {eDI_DBG_F_04, hpstv3_dbg_power_ctr_trig,
- "trig post power", "1: on; 0: off"},
-
- {eDI_DBG_F_05, hpstv3_dbg_mem_pd_trig,
- "trig post mem pd", "no para"},
- {eDI_DBG_F_06, hpstv3_dbg_trig_gate,
- "trig post gate off/on", "no para"},
- {eDI_DBG_F_07, hpstv3_dbg_trig_mif,
- "trig post mif off/free", "no para"},
- {eDI_DBG_F_08, dbg_f_trig_eos,
- "trig EOS for new interface", "1:on;0:off"}
-};
-
-static ssize_t wfunc_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int findex, para;
- char buf[20];
- int ret;
-
- int i;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%i %x", &findex, ¶);
-
- switch (ret) {
- case 2:
- pr_info("func:%d,para=0x%x\n", findex, para);
- for (i = 0; i < ARRAY_SIZE(div3_func_tab); i++) {
- if (i == findex && div3_func_tab[i].index == findex) {
- if (div3_func_tab[i].func)
- div3_func_tab[i].func(para);
- pr_info("func:%s finish\n",
- div3_func_tab[i].name);
- break;
- }
- }
- break;
- default:
- pr_info("warn: please enter function index and para\n");
- return -EINVAL;
- }
-
- return count;
-}
-
-static int rfunc_show(struct seq_file *seq, void *v)
-{
- int i;
-
- seq_puts(seq, "debug function list:\n");
-
- for (i = 0; i < ARRAY_SIZE(div3_func_tab); i++) {
- if (div3_func_tab[i].index != i)
- seq_printf(seq, "warn: index(%d->%d) is not map\n",
- i, div3_func_tab[i].index);
- seq_printf(seq, "index[%d]:%s:%s\n",
- div3_func_tab[i].index,
- div3_func_tab[i].name,
- div3_func_tab[i].info);
- }
- return 0;
-}
-/************************************************************
- *
- ************************************************************/
-static void dbg_wmode(struct seq_file *s, struct dim_wmode_s *pwmode)
-{
-
-
- seq_printf(s, "\t%20s:%d\n", "is_afbc", pwmode->is_afbc);
- seq_printf(s, "\t%20s:%d\n", "is_vdin", pwmode->is_vdin);
- seq_printf(s, "\t%20s:%d\n", "is_i", pwmode->is_i);
- seq_printf(s, "\t%20s:%d\n", "need_bypass", pwmode->need_bypass);
- seq_printf(s, "\t%20s:%d\n", "is_bypass", pwmode->is_bypass);
- seq_printf(s, "\t%20s:%d\n", "pre_bypass", pwmode->pre_bypass);
- seq_printf(s, "\t%20s:%d\n", "post_bypass", pwmode->post_bypass);
- seq_printf(s, "\t%20s:%d\n", "flg_keep", pwmode->flg_keep);
- seq_printf(s, "\t%20s:%d\n", "trick_mode", pwmode->trick_mode);
- seq_printf(s, "\t%20s:%d\n", "prog_proc_config",
- pwmode->prog_proc_config);
- seq_printf(s, "\t%20s:%d\n", "is_invert_tp", pwmode->is_invert_tp);
- seq_printf(s, "\t%20s:%d\n", "p_as_i", pwmode->p_as_i);
- seq_printf(s, "\t%20s:%d\n", "p_use_2i", pwmode->p_use_2i);
- seq_printf(s, "\t%20s:%d\n", "is_top", pwmode->is_top);
- seq_printf(s, "\t%20s:%d\n", "is_angle", pwmode->is_angle);
-
- seq_printf(s, "\t%20s:0x%x\n", "vtype", pwmode->vtype);
- seq_printf(s, "\t%20s:%d\n", "src_h", pwmode->src_h);
- seq_printf(s, "\t%20s:%d\n", "src_w", pwmode->src_w);
- seq_printf(s, "\t%20s:%d\n", "tgt_h", pwmode->tgt_h);
- seq_printf(s, "\t%20s:%d\n", "tgt_w", pwmode->tgt_w);
- seq_printf(s, "\t%20s:%d\n", "o_h", pwmode->o_h);
- seq_printf(s, "\t%20s:%d\n", "o_w", pwmode->o_w);
- seq_printf(s, "\t%20s:%d\n", "seq", pwmode->seq);
- seq_printf(s, "\t%20s:%d\n", "seq_pre", pwmode->seq_pre);
-
-
-}
-
-static void dbg_vmode(struct seq_file *s, struct dim_vmode_s *pvmode)
-{
- char *splt = "---------------------------";
-
- seq_printf(s, "%s\n", splt);
- seq_printf(s, "\t%20s:0x%x\n", "vtype", pvmode->vtype);
- seq_printf(s, "\t%20s:%d\n", "h", pvmode->h);
- seq_printf(s, "\t%20s:%d\n", "w", pvmode->w);
- seq_printf(s, "\t%20s:0x%x\n", "canvas0Addr", pvmode->canvas0Addr);
- seq_printf(s, "\t%20s:0x%x\n", "bitdepth", pvmode->bitdepth);
- seq_printf(s, "\t%20s:0x%x\n", "bit_mode", pvmode->bit_mode);
- seq_printf(s, "\t%20s:0x%x\n", "omx_index", pvmode->omx_index);
-}
-
-static int wmode_pstready_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
- int itmp;
- struct di_buf_s *p = NULL;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "\t---------------------------";
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(ch, QUE_POST_READY, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]); /*new que*/
- seq_printf(seq, "\t type[%d] id[%d]\n", p->type, p->index);
- dbg_wmode(seq, &p->c.wmode);
- dbg_vmode(seq, &p->c.vmode);
- seq_printf(seq, "%s\n", splt);
- }
-
- return 0;
-}
-
-static int wmode_preready_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
- int itmp;
- struct di_buf_s *p = NULL;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "\t---------------------------";
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- /********************************/
- /* pre_ready_list */
- /********************************/
- seq_puts(seq, "pre_ready_list:\n");
- div3_que_list(ch, QUE_PRE_READY, &tmpa[0], &psize);
- for (itmp = 0; itmp < psize; itmp++) {
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]);
- seq_printf(seq, "\t type[%d] id[%d]\n", p->type, p->index);
- dbg_wmode(seq, &p->c.wmode);
- dbg_vmode(seq, &p->c.vmode);
- seq_printf(seq, "%s\n", splt);
- }
-
- return 0;
-}
-
-/************************************************************
- *
- ************************************************************/
-static void dbg_mcinfo_pre(struct seq_file *s, struct mcinfo_pre_s *pmcinfo)
-{
- int i;
-
- struct mcinfo_pre_s {
- unsigned int highvertfrqflg;
- unsigned int motionparadoxflg;
- unsigned int regs[26];/* reg 0x2fb0~0x2fc9 */
- };
- seq_printf(s, "\t%20s:%d\n",
- "highvertfrqflg",
- pmcinfo->highvertfrqflg);
- seq_printf(s, "\t%20s:%d\n",
- "motionparadoxflg",
- pmcinfo->motionparadoxflg);
-
- for (i = 0; i < 26; i++) {
- seq_printf(s, "\treg[%d]:%d\n",
- i,
- pmcinfo->regs[i]);
- }
-}
-
-static int mcinfo_pre_pstready_show(struct seq_file *seq, void *v)
-{
- unsigned int ch;
- int itmp;
- struct di_buf_s *p = NULL;
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- char *splt = "\t---------------------------";
-
- ch = seq_get_channel(seq);
- seq_printf(seq, "%s:ch[%d]\n", __func__, ch);
-
- /********************************/
- /* post_ready_list */
- /********************************/
- div3_que_list(ch, QUE_POST_READY, &tmpa[0], &psize); /*new que*/
- seq_printf(seq, "post_ready_list: curr(%d)\n", psize);
-
- for (itmp = 0; itmp < psize; itmp++) { /*new que*/
- p = pwv3_qindex_2_buf(ch, tmpa[itmp]); /*new que*/
- seq_printf(seq, "\t type[%d] id[%d]\n", p->type, p->index);
- dbg_mcinfo_pre(seq, &p->c.curr_field_mcinfo);
- seq_printf(seq, "%s\n", splt);
- }
-
- return 0;
-}
-
-/**********************/
-static ssize_t reg_show(struct file *file, char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- char buf[80];
-
- ssize_t len;
- int *pInt;
-
- pInt = (int *)file->private_data;
- pr_info("pInt=0x%p,val=%d\n", pInt, *pInt);
-
- len = snprintf(buf, sizeof(buf), "%s\n",
- __func__);
-
- return simple_read_from_buffer(userbuf, count, ppos, buf, len);
-}
-
-static ssize_t reg_store(struct file *file, const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- unsigned int reg, val;
- char buf[80];
- int ret;
- int *pInt;
-
- count = min_t(size_t, count, (sizeof(buf) - 1));
- if (copy_from_user(buf, userbuf, count))
- return -EFAULT;
-
- buf[count] = 0;
-
- ret = sscanf(buf, "%x %i", ®, &val);
-
- switch (ret) {
- case 1:
- pr_info("reg:0x%x\n", reg);
-
- pInt = (int *)file->private_data;
- pr_info("pInt=0x%p,val=%d\n", pInt, *pInt);
- break;
- case 2:
- pr_info("reg:0x%x,val=%d\n", reg, val);
- break;
- default:
- return -EINVAL;
- }
-
- return count;
-}
-/**********************/
-#ifndef TST_NEW_INS_INTERFACE
-int vfmtst_vfmo_show(struct seq_file *s, void *what)
-{
- seq_printf(s, "%s:no new interface\n", __func__);
- return 0;
-}
-int vfmtst_vfmi_show(struct seq_file *s, void *what)
-{
- seq_printf(s, "%s:no new interface\n", __func__);
- return 0;
-
-}
-int vfmtst_bufo_show(struct seq_file *s, void *what)
-{
- seq_printf(s, "%s:no new interface\n", __func__);
- return 0;
-}
-int vfmtst_que_show(struct seq_file *s, void *what)
-{
- seq_printf(s, "%s:no new interface\n", __func__);
- return 0;
-
-}
-
-#endif
-/**********************/
-DEFINE_SEQ_SHOW_ONLY(dimv3_reg_cue_int);
-/**********************/
-DEFINE_SEQ_SHOW_ONLY(rcfgx);
-DEFINE_SEQ_SHOW_ONLY(seq_file_vframe_in);
-DEFINE_SEQ_SHOW_ONLY(seq_file_vframe_out);
-DEFINE_SEQ_SHOW_ONLY(seq_file_state);
-DEFINE_SEQ_SHOW_ONLY(seq_file_mif);
-DEFINE_SEQ_SHOW_ONLY(seq_file_sum);
-
-DEFINE_SEQ_SHOW_ONLY(regv3_con);
-DEFINE_SEQ_SHOW_ONLY(rfunc);
-DEFINE_SEQ_SHOW_ONLY(mpxr);
-DEFINE_SEQ_SHOW_ONLY(mpr_di);
-DEFINE_SEQ_SHOW_ONLY(mpr_nr);
-DEFINE_SEQ_SHOW_ONLY(mpr_pd);
-DEFINE_SEQ_SHOW_ONLY(mpr_mtn);
-DEFINE_SEQ_SHOW_ONLY(dim_qued);
-
-/*cfg top show only*/
-DEFINE_SEQ_SHOW_ONLY(cfgt_help);
-DEFINE_SEQ_SHOW_ONLY(cfgt_itme_all);
-DEFINE_SEQ_SHOW_ONLY(cfgt_val_all);
-
-/*cfg top store only*/
-DEFINE_STORE_ONLY(cfgtw_id);
-
-/*cfg top show/store*/
-DEFINE_SEQ_SHOW_STORE(cfgt_one);
-DEFINE_SEQ_SHOW_STORE(cfgt_sel);
-
-DEFINE_SEQ_SHOW_ONLY(seq_file_curr_vframe);
-
-DEFINE_STORE_ONLY(wcfgx);
-DEFINE_STORE_ONLY(wfunc);
-DEFINE_STORE_ONLY(mpxw);
-DEFINE_STORE_ONLY(mpw_di);
-DEFINE_STORE_ONLY(mpw_nr);
-DEFINE_STORE_ONLY(mpw_pd);
-DEFINE_STORE_ONLY(mpw_mtn);
-DEFINE_STORE_ONLY(buf_cnt);
-DEFINE_STORE_ONLY(keepv3_buf_clear);
-
-DEFINE_SHOW_STORE(reg);
-
-DEFINE_SEQ_SHOW_STORE(seqv3_file_vtype);
-DEFINE_SEQ_SHOW_STORE(ddbg_log_reg);
-
-/*wmode:*/
-DEFINE_SEQ_SHOW_ONLY(wmode_pstready);
-DEFINE_SEQ_SHOW_ONLY(wmode_preready);
-
-/**/
-DEFINE_SEQ_SHOW_ONLY(mcinfo_pre_pstready);
-
-/*vframe*/
-DEFINE_SEQ_SHOW_ONLY(vframe_pstready);
-DEFINE_SEQ_SHOW_ONLY(vframe_preready);
-
-DEFINE_SEQ_SHOW_ONLY(vfmtst_que);
-DEFINE_SEQ_SHOW_ONLY(vfmtst_vfmo);
-DEFINE_SEQ_SHOW_ONLY(vfmtst_vfmi);
-DEFINE_SEQ_SHOW_ONLY(vfmtst_bufo);
-
-/**********************/
-
-struct di_dbgfs_files_t {
- const char *name;
- const umode_t mode;
- const struct file_operations *fops;
-};
-
-static const struct di_dbgfs_files_t di_debugfs_files_top[] = {
- {"vtype", S_IFREG | 0644, &seqv3_file_vtype_fops},
- {"reg_log", S_IFREG | 0644, &ddbg_log_reg_fops},
- {"regctr", S_IFREG | 0644, ®v3_con_fops},
- {"rfunc", S_IFREG | 0644, &rfunc_fops},
- {"wfunc", S_IFREG | 0644, &wfunc_fops},
- {"reg_cue", S_IFREG | 0644, &dimv3_reg_cue_int_fops},
- /*module parameter*/
- {"mr_di", S_IFREG | 0644, &mpr_di_fops},
- {"mw_di", S_IFREG | 0644, &mpw_di_fops},
- {"mr_nr", S_IFREG | 0644, &mpr_nr_fops},
- {"mw_nr", S_IFREG | 0644, &mpw_nr_fops},
- {"mr_pd", S_IFREG | 0644, &mpr_pd_fops},
- {"mw_pd", S_IFREG | 0644, &mpw_pd_fops},
- {"mr_mtn", S_IFREG | 0644, &mpr_mtn_fops},
- {"mw_mtn", S_IFREG | 0644, &mpw_mtn_fops},
- {"buf_cnt", S_IFREG | 0644, &buf_cnt_fops},
- {"keep_clear", S_IFREG | 0644, &keepv3_buf_clear_fops},
- /*cfg*/
- {"cfghelp", S_IFREG | 0644, &cfgt_help_fops},
- {"cfgr_ai", S_IFREG | 0644, &cfgt_itme_all_fops},
- {"cfgr_av", S_IFREG | 0644, &cfgt_val_all_fops},
- {"cfgw_id", S_IFREG | 0644, &cfgtw_id_fops},
- {"cfg_one", S_IFREG | 0644, &cfgt_one_fops},
- {"cfg_sel", S_IFREG | 0644, &cfgt_sel_fops},
- {"tstvfm_que", S_IFREG | 0644, &vfmtst_que_fops},
- {"tstvfm_vfmo", S_IFREG | 0644, &vfmtst_vfmo_fops},
- {"tstvfm_vfmi", S_IFREG | 0644, &vfmtst_vfmi_fops},
- {"tstvfm_bufo", S_IFREG | 0644, &vfmtst_bufo_fops}
-};
-
-static const struct di_dbgfs_files_t di_debugfs_files[] = {
- {"rcfgx", S_IFREG | 0644, &rcfgx_fops},
- {"wcfgx", S_IFREG | 0644, &wcfgx_fops},
- {"rvfm_in", S_IFREG | 0644, &seq_file_vframe_in_fops},
- {"rvfm_out", S_IFREG | 0644, &seq_file_vframe_out_fops},
- {"vfm_pstrdy", S_IFREG | 0644, &vframe_pstready_fops},
- {"vfm_prerdy", S_IFREG | 0644, &vframe_preready_fops},
- {"state", S_IFREG | 0644, &seq_file_state_fops},
- {"dumpmif", S_IFREG | 0644, &seq_file_mif_fops},
- {"test_reg", S_IFREG | 0644, ®_fops},
- {"sum", S_IFREG | 0644, &seq_file_sum_fops},
- {"mpxr", S_IFREG | 0644, &mpxr_fops},
- {"mpxw", S_IFREG | 0644, &mpxw_fops},
- {"vfmc", S_IFREG | 0644, &seq_file_curr_vframe_fops},
- {"qued", S_IFREG | 0644, &dim_qued_fops},
- {"wmode_pstrdy", S_IFREG | 0644, &wmode_pstready_fops},
- {"wmode_prerdy", S_IFREG | 0644, &wmode_preready_fops},
- {"mcinfopre_pstrdy", S_IFREG | 0644, &mcinfo_pre_pstready_fops}
-};
-
-void didbgv3_fs_init(void)
-{
- int i, j;
- char name[5];
- /*char buf[3];*/
-
- struct dentry **root_ent;
-
- struct dentry *ent;
- int *pPlane = di_get_plane();
-
- for (i = 0; i < DI_CHANNEL_NUB; i++) {
-#if 0
- strcpy(name, "di");
- sprintf(buf, "%01d", i);
- strncat(name, buf, sizeof(buf) - 1);
-#endif
- snprintf(name, sizeof(name), "di%01d", i);
- root_ent = dich_get_dbgroot(i);
- if (IS_ERR_OR_NULL(root_ent))
- continue;
- *root_ent = debugfs_create_dir(name, NULL);
- if (IS_ERR_OR_NULL(*root_ent))
- continue;
- *(pPlane + i) = i;
- /*printk("plane 0x%p\n", &plane_ch[i]);*/
- for (j = 0; j < ARRAY_SIZE(di_debugfs_files); j++) {
- ent = debugfs_create_file(di_debugfs_files[j].name,
- di_debugfs_files[j].mode,
- *root_ent, (pPlane + i),
- di_debugfs_files[j].fops);
- if (!ent)
- PR_ERR("debugfs create failed\n");
- }
- }
- /*top*/
- root_ent = dich_get_dbgroot_top();
- if (IS_ERR_OR_NULL(root_ent))
- return;
- *root_ent = debugfs_create_dir("di_top", NULL);
- if (IS_ERR_OR_NULL(*root_ent))
- return;
- for (i = 0; i < ARRAY_SIZE(di_debugfs_files_top); i++) {
- ent = debugfs_create_file(di_debugfs_files_top[i].name,
- di_debugfs_files_top[i].mode,
- *root_ent, NULL,
- di_debugfs_files_top[i].fops);
- if (!ent)
- PR_ERR("debugfs top [%d]create failed\n", i);
- }
-}
-
-void didbgv3_fs_exit(void)
-{
- struct dentry **root_ent;
- int i;
-
- for (i = 0; i < DI_CHANNEL_NUB; i++) {
- root_ent = dich_get_dbgroot(i);
- debugfs_remove_recursive(*root_ent);
- }
-
- /*top*/
- root_ent = dich_get_dbgroot_top();
- debugfs_remove_recursive(*root_ent);
-
- pr_info("%s:finish\n", __func__);
-}
-
-/*-----------------------*/
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_dbg.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_DBG_H__
-#define __DI_DBG_H__
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-
-void didbgv3_fs_init(void);
-void didbgv3_fs_exit(void);
-
-void div3_cfgx_init_val(void);
-
-void didbgv3_vframe_in_copy(unsigned int ch, struct vframe_s *pvfm);
-void didbgv3_vframe_out_save(struct vframe_s *pvfm);
-
-/********************************
- *debug register:
- *******************************/
-void ddbgv3_reg_save(unsigned int addr, unsigned int val,
- unsigned int st, unsigned int bw);
-void dimv3_ddbg_mod_save(unsigned int mod,
- unsigned int ch,
- unsigned int cnt);
-void ddbgv3_sw(unsigned int mode, bool on);
-
-/********************************
- *time:
- *******************************/
-u64 curv3_to_msecs(void);
-u64 curv3_to_usecs(void); /*2019*/
-
-/********************************
- *trace:
- *******************************/
-struct dim_tr_ops_s {
- void (*pre)(unsigned int index, unsigned long ctime);
- void (*post)(unsigned int index, unsigned long ctime);
- void (*pre_get)(unsigned int index);
- void (*pre_set)(unsigned int index);
- void (*pre_ready)(unsigned int index);
- void (*post_ready)(unsigned int index);
- void (*post_get)(unsigned int index);
- void (*post_get2)(unsigned int index);
- void (*post_set)(unsigned int index);
- void (*post_ir)(unsigned int index);
- void (*post_do)(unsigned int index);
- void (*post_peek)(unsigned int index);
-};
-
-extern const struct dim_tr_ops_s dimv3_tr_ops;
-int seq_file_vframe(struct seq_file *seq, void *v, struct vframe_s *pVfm);
-
-#endif /*__DI_DBG_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_interface.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/semaphore.h>
-#include <linux/kfifo.h>
-#include <linux/spinlock.h>
-
-#include "deinterlace.h"
-#include "di_data_l.h"
-#include "di_pre.h"
-#include "di_prc.h"
-#include "di_dbg.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_vframe.h"
-
-#ifdef HIS_V3
-const struct di_init_parm dim_cfg_parm_default = {
- .work_mode = WORK_MODE_PRE_POST,
- .buffer_mode = BUFFER_MODE_ALLOC_BUF,
- .ops = {
- .empty_input_done = NULL,
- .fill_output_done = NULL,
- },
-};
-#endif
-/**********************************************************
- * ops
- **********************************************************/
-static void *ins_peek(struct di_ch_s *pch)
-{
- unsigned int index;
-
- if (!qued_ops.peek(pch, QUED_T_IS_IN, &index))
- return NULL;
- return (void *)pch->interf.u.dinst.in[index];
-}
-
-static void *ins_get(struct di_ch_s *pch)
-{
- unsigned int index;
- struct di_buffer *dbuf;
- unsigned int dbg_cnt1, dbg_cnt2;
-
- if (!qued_ops.move(pch,
- QUED_T_IS_IN,
- QUED_T_IS_FREE, &index)) {
- dbg_cnt1 = qued_ops.listv3_count(pch, QUED_T_IS_IN);
- dbg_cnt2 = qued_ops.listv3_count(pch, QUED_T_IS_FREE);
- PR_ERR("ins_get:no space,%d,%d\n", dbg_cnt1, dbg_cnt2);
- return NULL;
- }
- sum_g_inc(pch->ch_id);
- dbuf = pch->interf.u.dinst.in[index];
- pch->interf.u.dinst.in[index] = NULL;
- return (void *)dbuf;
-}
-
-static void ins_put(void *data, struct di_ch_s *pch)
-{
- struct dim_inter_s *pintf = &pch->interf;
- struct di_operations_s *ops;
-
- ops = &pintf->u.dinst.parm.ops;
- if (ops->empty_input_done) {
- sum_p_inc(pch->ch_id);
- ops->empty_input_done((struct di_buffer *)data);
- //debug only dump_stack();
- }
-}
-
-const struct dim_itf_ops_s inst_in_ops = {
- .peek = ins_peek,
- .get = ins_get,
- .put = ins_put,
-};
-
-static int reg_idle_ch(void)
-{
- unsigned int ch;
- struct dim_inter_s *pintf;
- int ret = -1;
- //int i;
- struct di_ch_s *pch;
- struct di_mng_s *pbm = get_bufmng();
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pintf = get_dev_intf(ch);
- pch = get_chdata(ch);
- if ((pbm->tmode_pre[ch] == EDIM_TMODE_2_PW_OUT ||
- pbm->tmode_pre[ch] == EDIM_TMODE_3_PW_LOCAL) &&
- !pintf->reg) {
- #ifdef HIS_V3 //move to dip_init_value_reg
- /*que buf*/
- for (i = 0; i < DIM_K_BUF_IN_LIMIT; i++)
- qued_ops.in(pch, QUED_T_IS_FREE, i);
-
- for (i = 0; i < DIM_K_BUF_OUT_LIMIT; i++)
- qued_ops.in(pch, QUED_T_IS_PST_FREE, i);
- #endif
- /*set reg flg*/
- pintf->reg = true;
- ret = (int)ch;
- dbg_dbg("%s:ch[%d], ret[%d]\n", __func__, ch, ret);
- break;
- }
- dbg_dbg("%s:ch[%d],tmode[%d],reg[%d]\n", __func__,
- ch, pbm->tmode_pre[ch], pintf->reg);
- }
- dbg_dbg("%s:%d\n", __func__, ret);
- return ret;
-}
-/* mode 2 for drop */
-void ins_2_doing(struct di_ch_s *pch, bool bypass, struct di_buf_s *pstdi_buf)
-{
- unsigned int ch = pch->ch_id;
- struct di_buf_s *di_buf = NULL; /*post nobuf buffer*/
- bool ret;
- struct di_buffer *ins_buf, *ins_in;
- unsigned int idx;
- struct dim_inter_s *pintf;
- struct vframe_s *vfmin, *vfmout;
- struct canvas_config_s cvs[2];
-
- if (div3_que_is_empty(ch, QUE_POST_NOBUF))
- return;
-
- if (qued_ops.is_empty(pch, QUED_T_IS_PST_DOBEF))
- return;
-
- di_buf = div3_que_peek(ch, QUE_POST_NOBUF);
- dimv3_print("%s:1:%p,buf[%d],t[%d]\n", __func__, di_buf,
- di_buf->index, di_buf->type);
- trace_buf(di_buf, DIM_QUE_PEEK, QUE_POST_NOBUF,
- (DIM_DBG_MARK | 0x00000001));
- ret = div3_que_out(ch, QUE_POST_NOBUF, di_buf);
- if (!ret) {
- PR_ERR("%s:no buf?\n", __func__);
- return;
- }
-
- pintf = &pch->interf;
- qued_ops.out(pch, QUED_T_IS_PST_DOBEF, &idx);
-
- ins_buf = pintf->u.dinst.out[idx];
- if (!ins_buf) {
- PR_ERR("%s:out is null\n", __func__);
- return;
- }
- di_buf->c.pdvfm->vfm_out = pintf->u.dinst.out[idx];
- pintf->u.dinst.out[idx] = NULL;
- qued_ops.in(pch, QUED_T_IS_PST_FREE, idx);
-
- trace_buf(di_buf, DIM_QUE_OUT, QUE_POST_NOBUF,
- (DIM_DBG_MARK | 0x00000002));
-
- dbg_dbg("%s:ch[%d],type[%d], id[%d]\n", __func__, pch->ch_id,
- di_buf->type, di_buf->index);
- dbg_dbg("ins_buf,type[%d], id[%d]\n",
- ins_buf->mng.type,
- ins_buf->mng.index);
- if (!ins_buf)
- PR_ERR("%s:out2 is null\n", __func__);
-
- /*in*/
- ins_in = (struct di_buffer *)di_buf->c.pdvfm->vfm_in;
- vfmin = ins_in->vf;
- vfmout = ins_buf->vf;
- if (!di_buf->c.wmode.is_eos) {
- /*copy vfm */
- memcpy(&cvs[0], &vfmout->canvas0_config[0], sizeof(cvs));
- memcpy(vfmout, vfmin, sizeof(*vfmout));
- memcpy(&vfmout->canvas0_config[0],
- &cvs[0], sizeof(cvs));
- }
-
- if (!di_buf->c.wmode.is_bypass) {
- //di_buf->nr_adr = ins_buf->phy_addr;
- //di_buf->nr_adr = ins_buf->vf->canvas0_config[0].phy_addr;
- //ins_buf->phy_addr;
- dim_ins_cnt_post_cvs_size2(di_buf, ins_buf, ch);
- } else {
- /* bypass */
- if (di_buf->c.wmode.is_eos) {
- ins_buf->flag |= DI_FLAG_EOS;
- PR_INF("%s:eos\n", __func__);
- } else {
- ins_buf->flag |= DI_FLAG_BUF_BY_PASS;
- }
- dimv3_print("%s:%p bypass\n", __func__, ins_buf);
- }
- dbg_vfmv3(vfmout, 1);
- trace_buf(di_buf, DIM_QUE_IN, QUE_POST_DOING,
- (DIM_DBG_MARK | 0x00000003));
- dimv3_print("%s:%p,buf[%d],t[%d]\n", __func__, di_buf,
- di_buf->index, di_buf->type);
- div3_que_in(ch, QUE_POST_DOING, di_buf);
-
-}
-#define ERR_INDEX (0xffff)
-static unsigned int index_2_ch(int index)
-{
- unsigned int ret;
-
- if (index >= DI_CHANNEL_NUB || index < 0) {
- PR_ERR("instance index is overflow:%d\n", index);
- ret = ERR_INDEX;
- } else {
- ret = (unsigned int)index;
- }
-
- return ret;
-}
-
-/**********************************************************
- * @brief di_create_instance creat di instance
- * @param[in] parm Pointer of parm structure
- * @return di index for success, or fail type if < 0
- **********************************************************/
-int di_create_instance(struct di_init_parm parm)
-{
- int ret;
- unsigned int ch;
- struct dim_inter_s *pintf;
-
- ret = reg_idle_ch();
- if (ret < 0) {
- PR_ERR("%s:no idle ch\n", __func__);
- return DI_ERR_REG_NO_IDLE_CH;
- }
-
- ch = (unsigned int)ret;
- pintf = get_dev_intf(ch);
- /*parm*/
- memcpy(&pintf->u.dinst.parm, &parm, sizeof(struct di_init_parm));
- /*ops in*/
- memcpy(&pintf->opsi, &inst_in_ops, sizeof(struct dim_itf_ops_s));
- pintf->tmode = EDIM_TMODE_2_PW_OUT;
- if (pintf->u.dinst.parm.work_mode == WORK_MODE_PRE_POST) {
- switch (pintf->u.dinst.parm.buffer_mode) {
- case BUFFER_MODE_ALLOC_BUF:
- pintf->tmode = EDIM_TMODE_3_PW_LOCAL;
- break;
- case BUFFER_MODE_USE_BUF:
- pintf->tmode = EDIM_TMODE_2_PW_OUT;
- break;
- default:
- PR_ERR("%s:bmode[%d]\n", __func__,
- pintf->u.dinst.parm.buffer_mode);
- break;
- }
- } else {
- PR_ERR("%s:wmode[%d]\n", __func__,
- pintf->u.dinst.parm.work_mode);
- }
-
- pintf->op_dvfm_fill = dvfmv3_fill_in_ins;
- if (pintf->tmode == EDIM_TMODE_2_PW_OUT) {
- pintf->op_post_done = dimv3_post_de_done_buf_config_ins;
- pintf->op_ins_2_doing = ins_2_doing;
- } else if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL) {
- pintf->op_post_done = dimv3_post_de_done_buf_config_ins_local;
- pintf->op_ins_2_doing = NULL;
- } else {
- pintf->op_ins_2_doing = NULL;
- }
- dipv3_event_reg_chst(ch);
- PR_INF("%s:ch[%d],tmode[%d]\n", __func__, ch, pintf->tmode);
- return ch;
-}
-EXPORT_SYMBOL(di_create_instance);
-
-/**********************************************************
- **
- * @brief di_set_parameter set parameter to di for init
- *
- * @param[in] index instance index
- *
- * @return 0 for success, or fail type if < 0
- *
- **********************************************************/
-int di_destroy_instance(int index)
-{
- struct dim_inter_s *pintf;
- unsigned int ch;
-
- ch = index_2_ch(index);
- if (ch == ERR_INDEX) {
- PR_ERR("%s:index overflow\n", __func__);
- return DI_ERR_INDEX_OVERFLOW;
- }
-
- pintf = get_dev_intf(ch);
- if (!pintf->reg)
- PR_WARN("%s:now not unreg\n", __func__);
-
- pintf->reg = 0;
- dipv3_event_unreg_chst(ch);
-
- return 0;
-}
-EXPORT_SYMBOL(di_destroy_instance);
-
-/**********************************************************
- **
- * @brief di_empty_input_buffer send input date to di
- *
- * @param[in] index instance index
- * @param[in] buffer Pointer of buffer structure
- *
- * @return Success or fail type
- **********************************************************/
-enum DI_ERRORTYPE di_empty_input_buffer(int index, struct di_buffer *buffer)
-{
- struct dim_inter_s *pintf;
- unsigned int ch;
- struct di_ch_s *pch;
- unsigned int buf_index = 0xff;
-
- ch = index_2_ch(index);
- if (ch == ERR_INDEX) {
- PR_ERR("%s:index overflow\n", __func__);
- return DI_ERR_INDEX_OVERFLOW;
- }
- pch = get_chdata(ch);
- pintf = get_dev_intf(ch);
- if (!pintf->reg) {
- PR_WARN("%s:ch[%d] not reg\n", __func__, ch);
- return DI_ERR_INDEX_NOT_ACTIVE;
- }
-
- #if 0
- /*que in IS_*/
- if (!qued_ops.move(pch, QUED_T_IS_FREE, QUED_T_IS_IN, &buf_index)) {
- PR_WARN("%s:ch[%d]:no space for 0x%p\n", __func__, ch, buffer);
- return DI_ERR_IN_NO_SPACE;
- }
- pintf->u.dinst.in[buf_index] = buffer;
- #else
- qued_ops.peek(pch, QUED_T_IS_FREE, &buf_index);
- if (buf_index == 0xff) {
- PR_ERR("%s:no free\n", __func__);
- return DI_ERR_IN_NO_SPACE;
- }
- qued_ops.out(pch, QUED_T_IS_FREE, &buf_index);
- pintf->u.dinst.in[buf_index] = buffer;
- qued_ops.in(pch, QUED_T_IS_IN, buf_index);
-
- #endif
-
-
- return DI_ERR_NONE;
-}
-EXPORT_SYMBOL(di_empty_input_buffer);
-
-static enum DI_ERRORTYPE di_fill_output_buffer_mode2(struct dim_inter_s *pintf,
- struct di_buffer *buffer)
-{
- /*from QUED_T_IS_PST_FREE to QUED_T_IS_PST_DOBEF */
- struct di_ch_s *pch;
- unsigned int buf_index = 0xff;
-
-
- pch = get_chdata(pintf->ch);
- #if 0
- /*que IS_PST*/
- if (!qued_ops.move(pch,
- QUED_T_IS_PST_FREE,
- QUED_T_IS_PST_DOBEF, &buf_index)) {
- PR_WARN("%s:ch[%d]:no space for 0x%p\n", __func__, ch, buffer);
- return DI_ERR_IN_NO_SPACE;
- }
-
- pintf->u.dinst.out[buf_index] = buffer;
- #else
- qued_ops.peek(pch, QUED_T_IS_PST_FREE, &buf_index);
- if (buf_index == 0xff) {
- PR_ERR("%s: NO PST_FREE\n", __func__);
- return DI_ERR_IN_NO_SPACE;
- }
- qued_ops.out(pch, QUED_T_IS_PST_FREE, &buf_index);
- pintf->u.dinst.out[buf_index] = buffer;
- qued_ops.in(pch, QUED_T_IS_PST_DOBEF, buf_index);
-
- #endif
- return DI_ERR_NONE;
-}
-
-static enum DI_ERRORTYPE di_fill_output_buffer_mode3(struct dim_inter_s *pintf,
- struct di_buffer *buffer)
-{
- /*back buf to di */
- struct di_ch_s *pch;
-// unsigned int buf_index = 0xff;
- struct di_buf_s *di_buf = NULL;
-//tmp ulong irq_flag2 = 0;
- unsigned int ch;
-
- ch = pintf->ch;
- pch = get_chdata(ch);
-
- di_buf = (struct di_buf_s *)buffer->private_data;
- if (IS_ERR_OR_NULL(di_buf)) {
- pch->interf.opsi.put(buffer->vf, pch);
- PR_ERR("%s: get vframe %p without di buf\n",
- __func__, buffer);
- return DI_ERR_NONE;
- }
-
- if (di_buf->type == VFRAME_TYPE_POST) {
- // dim_lock_irqfiq_save(irq_flag2);
-
- /*check if in QUE_POST_DISPLAY*/
- /*di_buf->queue_index = QUEUE_DISPLAY;*/
- if (isv3_in_queue(ch, di_buf, QUEUE_DISPLAY)) {
- di_buf->queue_index = -1;
- div3_que_in(ch, QUE_POST_BACK, di_buf);
- //dim_unlock_irqfiq_restore(irq_flag2);
- } else {
- //dim_unlock_irqfiq_restore(irq_flag2);
- PR_ERR("%s:ch[%d]:not in display %d\n", __func__,
- ch,
- di_buf->index);
- }
-
- } else {
- // dim_lock_irqfiq_save(irq_flag2);
- queuev3_in(ch, di_buf, QUEUE_RECYCLE);
- //dim_unlock_irqfiq_restore(irq_flag2);
- }
- dimv3_print("%s: ch[%d];typ[%d];id[%d];omxp[%d]\n", __func__,
- ch,
- di_buf->type, di_buf->index,
- di_buf->vframe->omx_index);
-
- return DI_ERR_NONE;
-}
-
-/**********************************************************
- * @brief di_fill_output_buffer send output buffer to di
- *
- * @param[in] index instance index
- * @param[in] buffer Pointer of buffer structure
- *
- * @return Success or fail type
- *********************************************************/
-enum DI_ERRORTYPE di_fill_output_buffer(int index, struct di_buffer *buffer)
-{
- struct dim_inter_s *pintf;
- unsigned int ch;
- //struct di_ch_s *pch;
- enum DI_ERRORTYPE ret = DI_ERR_NONE;
-
- /*check channel*/
- ch = index_2_ch(index);
- if (ch == ERR_INDEX) {
- PR_ERR("%s:index overflow\n", __func__);
- return DI_ERR_INDEX_OVERFLOW;
- }
-
- pintf = get_dev_intf(ch);
- dimv3_print("%s:ch[%d],ptf ch[%d]\n", __func__, ch, pintf->ch);
- if (!pintf->reg) {
- PR_WARN("%s:ch[%d] not reg\n", __func__, ch);
- return DI_ERR_INDEX_NOT_ACTIVE;
- }
-
- if (pintf->tmode == EDIM_TMODE_2_PW_OUT)
- ret = di_fill_output_buffer_mode2(pintf, buffer);
- else if (pintf->tmode == EDIM_TMODE_3_PW_LOCAL)
- ret = di_fill_output_buffer_mode3(pintf, buffer);
-
- return ret;
-}
-EXPORT_SYMBOL(di_fill_output_buffer);
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_post.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-
-#include "di_data_l.h"
-#include "di_data.h"
-#include "di_dbg.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_prc.h"
-#include "di_post.h"
-
-#include "nr_downscale.h"
-#include "register.h"
-
-void dpostv3_clear(void)/*not been called*/
-{
- struct di_hpst_s *pst = get_hw_pst();
-
- memset(pst, 0, sizeof(struct di_hpst_s));
-}
-
-void dpostv3_init(void)
-{/*reg:*/
- struct di_hpst_s *pst = get_hw_pst();
-
- pst->state = eDI_PST_ST_IDLE;
-
- /*timer out*/
- div3_tout_int(&pst->tout, 40); /*ms*/
-}
-
-void pwv3_use_hw_post(enum eDI_SUB_ID channel, bool on)
-{
- struct di_hpst_s *post = get_hw_pst();
-
- post->hw_flg_busy_post = on;
- if (on)
- post->curr_ch = channel;
-}
-
-static bool pwv3_try_sw_ch_next_post(enum eDI_SUB_ID channel)
-{
- bool ret = false;
-
- struct di_hpst_s *post = get_hw_pst();
- enum eDI_SUB_ID lst_ch, nch;
-
- lst_ch = channel;
-
- nch = pwv3_ch_next_count(lst_ch);
- if (!get_reg_flag(nch) || get_flag_trig_unreg(nch))
- return false;
-
- if (nch != channel)
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_CH_CHG, nch, 0);/*dbg*/
-
- post->curr_ch = nch;
- post->hw_flg_busy_post = true;
- ret = true;
-
- /*dim_print("%s:%d->%d:%d\n", __func__, lst_ch, nch, ret);*/
- return ret;
-}
-
-/*****************************/
-/* debug */
-/*****************************/
-
-/*****************************/
-/* STEP */
-/*****************************/
-
-bool dpstv3_step_idle(void)
-{
- struct di_hpst_s *pst = get_hw_pst();
- bool reflesh = false;
-
- if (!pwv3_try_sw_ch_next_post(pst->curr_ch))
- return false;
-
- pst->pres = get_pre_stru(pst->curr_ch);
- pst->psts = get_post_stru(pst->curr_ch);
- pst->state++;/*tmp*/
- reflesh = true;
-
- return reflesh;
-}
-
-bool dpstv3_step_check(void)
-{
- struct di_hpst_s *pst = get_hw_pst();
- unsigned int ch;
- struct di_post_stru_s *ppost;
- bool reflesh = false;
-
- ch = pst->curr_ch;
- ppost = get_post_stru(ch);
-
- //if (queue_empty(ch, QUEUE_POST_DOING)) {
- if (div3_que_is_empty(ch, QUE_POST_DOING)) {
- ppost->post_peek_underflow++;
- pst->state--;
- return reflesh;
- }
-
- pst->state++;
- reflesh = true;
-
- return reflesh;
-}
-
-bool dpstv3_step_set(void)
-{
- struct di_buf_s *di_buf = NULL;
- //vframe_t *vf_p = NULL;
- struct di_post_stru_s *ppost;
- struct di_hpst_s *pst = get_hw_pst();
- unsigned int ch;
- bool reflesh = false;
- ulong flags = 0;
- struct dim_wmode_s *pwmode;
-
- ch = pst->curr_ch;
- ppost = get_post_stru(ch);
-
- //di_buf = get_di_buf_head(ch, QUEUE_POST_DOING);
- di_buf = div3_que_peek(ch, QUE_POST_DOING);
- trace_buf(di_buf, DIM_QUE_PEEK, QUE_POST_DOING,
- (DIM_DBG_MARK | 0x00000010));
- if (dimv3_check_di_buf(di_buf, 20, ch)) {
- PR_ERR("%s:err1\n", __func__);
- return reflesh;
- }
-
- //vf_p = di_buf->vframe;
- #if 0 /*clear run_early_proc_fun_flag*/
- if (ppost->run_early_proc_fun_flag) {
- if (vf_p->early_process_fun)
- vf_p->early_process_fun = dimv3_do_post_wr_fun;
- }
- #endif
- pwmode = &di_buf->c.wmode;
-
- dimv3_print("%s:%p,%d, t[%d]\n", __func__, di_buf, di_buf->index,
- di_buf->type);
- if (di_buf->c.process_fun_index) { /*not bypass?*/
-
- ppost->post_wr_cnt++;
- spin_lock_irqsave(&plistv3_lock, flags);
- #if 0
- dimv3_post_process(di_buf, 0, vf_p->width - 1,
- 0, vf_p->height - 1, vf_p);
- #else
- dimv3_post_process(di_buf, 0, pwmode->tgt_w - 1,
- 0, pwmode->tgt_h - 1, NULL);
- #endif
- spin_unlock_irqrestore(&plistv3_lock, flags);
-
- /*begin to count timer*/
- div3_tout_contr(eDI_TOUT_CONTR_EN, &pst->tout);
-
- ppost->post_de_busy = 1;
- ppost->irq_time = curv3_to_msecs();
-
- /*state*/
- pst->state++;
- /*reflesh = true;*/
- } else {
- ppost->de_post_process_done = 1; /*trig done*/
- pst->flg_int_done = 1;
-
- /*state*/
- pst->state++;/*pst->state = eDI_PST_ST_DONE;*/
- reflesh = true;
- }
- ppost->cur_post_buf = di_buf;
-
- return reflesh;
-}
-
-bool dpstv3_step_wait_int(void)
-{
- struct di_hpst_s *pst = get_hw_pst();
- unsigned int ch;
- struct di_post_stru_s *ppost;
- bool reflesh = false;
- ulong flags = 0;
- struct dim_inter_s *pitf;
- struct di_ch_s *pch;
-
- ch = pst->curr_ch;
- pch = get_chdata(ch);
- pitf = &pch->interf;
- dimv3_print("%s:ch[%d],done_flg[%d]\n", __func__,
- pst->curr_ch, pst->flg_int_done);
- if (pst->flg_int_done) {
- /*finish to count timer*/
- div3_tout_contr(eDI_TOUT_CONTR_FINISH, &pst->tout);
- spin_lock_irqsave(&plistv3_lock, flags);
- //dim_post_de_done_buf_config(ch);
- pitf->op_post_done(pch);
- spin_unlock_irqrestore(&plistv3_lock, flags);
- pst->flg_int_done = false;
- /*state*/
- pst->state = eDI_PST_ST_IDLE;
- reflesh = true;
- } else {
- /*check if timeout:*/
- if (div3_tout_contr(eDI_TOUT_CONTR_CHECK, &pst->tout)) {
- ppost = get_post_stru(ch);
- PR_WARN("ch[%d]:post timeout[%d]\n", ch,
- ppost->cur_post_buf->c.seq);
- dimv3_ddbg_mod_save(eDI_DBG_MOD_POST_TIMEOUT, ch, 0);
- /*state*/
- pst->state = eDI_PST_ST_TIMEOUT;
- reflesh = true;
- }
- }
- return reflesh;
-}
-
-void dpstv3_timeout(unsigned int ch)
-{
- hpstv3_dbg_mem_pd_trig(0);
- postv3_close_new();
- #if 0
- div3_post_set_flow(1, eDI_POST_FLOW_STEP1_STOP);
- div3_post_reset();
- #endif
- dimhv3_pst_trig_resize();
-}
-
-bool dpstv3_step_timeout(void)
-{
- struct di_hpst_s *pst = get_hw_pst();
- unsigned int ch;
- bool reflesh = false;
- ulong flags = 0;
- struct dim_inter_s *pitf;
- struct di_ch_s *pch;
-
- ch = pst->curr_ch;
- pch = get_chdata(ch);
- pitf = &pch->interf;
- dpstv3_timeout(ch);
- spin_lock_irqsave(&plistv3_lock, flags);
- //dim_post_de_done_buf_config(ch);
- pitf->op_post_done(pch);
- spin_unlock_irqrestore(&plistv3_lock, flags);
- pst->flg_int_done = false;
-
- /*state*/
- pst->state = eDI_PST_ST_IDLE;
- reflesh = true;
-
- return reflesh;
-}
-
-bool dpstv3_step_done(void)/*this step no use ?*/
-{
- struct di_hpst_s *pst = get_hw_pst();
- unsigned int ch;
- bool reflesh = false;
-
- ch = pst->curr_ch;
-/* dim_post_de_done_buf_config(ch);*/
-
- /*state*/
- pst->state = eDI_PST_ST_IDLE;
- reflesh = true;
-
- return reflesh;
-}
-
-const struct di_func_tab_s div3_pst_func_tab[] = {
- {eDI_PST_ST_EXIT, NULL},
- {eDI_PST_ST_IDLE, dpstv3_step_idle},
- {eDI_PST_ST_CHECK, dpstv3_step_check},
- {eDI_PST_ST_SET, dpstv3_step_set},
- {eDI_PST_ST_WAIT_INT, dpstv3_step_wait_int},
- {eDI_PST_ST_TIMEOUT, dpstv3_step_timeout},
- {eDI_PST_ST_DONE, dpstv3_step_done}
-};
-
-const char * const dpstv3_state_name[] = {
- "EXIT",
- "IDLE", /*swith to next channel?*/
- "CHECK",
- "SET",
- "WAIT_INT",
- "TIMEOUT",
- "DONE"
-};
-
-const char *dpstv3_state_name_get(enum eDI_PST_ST state)
-{
- if (state > eDI_PST_ST_DONE)
- return "nothing";
-
- return dpstv3_state_name[state];
-}
-
-bool dpstv3_can_exit(unsigned int ch)
-{
- struct di_hpst_s *pst = get_hw_pst();
- bool ret = false;
-
- if (ch != pst->curr_ch) {
- ret = true;
- } else {
- if (pst->state <= eDI_PST_ST_IDLE)
- ret = true;
- }
- PR_INF("%s:ch[%d]:curr[%d]:stat[%s] ret[%d]\n",
- __func__,
- ch, pst->curr_ch,
- dpstv3_state_name_get(pst->state),
- ret);
- return ret;
-}
-
-static bool dpstv3_process_step2(void)
-{
- struct di_hpst_s *pst = get_hw_pst();
- enum eDI_PST_ST pst_st = pst->state;
- unsigned int ch;
-
- ch = pst->curr_ch;
- if (pst_st > eDI_PST_ST_EXIT)
- dimv3_recycle_post_back(ch);
-
- if ((pst_st <= eDI_PST_ST_DONE) &&
- div3_pst_func_tab[pst_st].func)
- return div3_pst_func_tab[pst_st].func();
- else
- return false;
-}
-
-void dpstv3_dbg_f_trig(unsigned int cmd)
-{
- struct di_task *tsk = get_task();
-
- struct di_hpst_s *pst = get_hw_pst();
-
- if (down_interruptible(&tsk->sem)) {
- PR_ERR("%s:can't get sem\n", __func__);
- return;
- }
-
- /*set on/off and trig*/
- if (cmd & 0x10) {
- pst->dbg_f_en = 1;
- pst->dbg_f_cnt = cmd & 0xf;
- pst->dbg_f_lstate = pst->state;
- } else {
- pst->dbg_f_en = 0;
- }
-
- up(&tsk->sem);
-}
-
-void dpstv3_process(void)
-{
- bool reflesh;
-
- struct di_hpst_s *pst = get_hw_pst();
-
- if (pst->dbg_f_en) {
- if (pst->dbg_f_cnt) {
- dpstv3_process_step2();
- pst->dbg_f_cnt--;
- }
- if (pst->dbg_f_lstate != pst->state) {
- PR_INF("ch[%d]:state:%s->%s\n",
- pst->curr_ch,
- dpstv3_state_name_get(pst->dbg_f_lstate),
- dpstv3_state_name_get(pst->state));
-
- pst->dbg_f_lstate = pst->state;
- }
- return;
- }
-
- reflesh = true;
-
- while (reflesh)
- reflesh = dpstv3_process_step2();
-}
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_post.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_POST_H__
-#define __DI_POST_H__
-
-void dpostv3_init(void);
-void dpstv3_process(void);
-const char *dpstv3_state_name_get(enum eDI_PST_ST state);
-void dpstv3_dbg_f_trig(unsigned int cmd);
-bool dpstv3_can_exit(unsigned int ch);
-
-#endif /*__DI_POST_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pps.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/amlogic/media/registers/regs/di_regs.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "di_pps.h"
-#include "deinterlace.h"
-#include "di_data_l.h"
-#include "register.h"
-
-#include <linux/seq_file.h>
-
-#if 0
-/* pps filter coefficients */
-#define COEF_BICUBIC 0
-#define COEF_3POINT_TRIANGLE 1
-#define COEF_4POINT_TRIANGLE 2
-#define COEF_BILINEAR 3
-#define COEF_2POINT_BILINEAR 4
-#define COEF_BICUBIC_SHARP 5
-#define COEF_3POINT_TRIANGLE_SHARP 6
-#define COEF_3POINT_BSPLINE 7
-#define COEF_4POINT_BSPLINE 8
-#define COEF_3D_FILTER 9
-#define COEF_NULL 0xff
-#define TOTAL_FILTERS 10
-
-#define MAX_NONLINEAR_FACTOR 0x40
-
-const u32 vpp_filter_coefs_bicubic_sharp[] = {
- 3,
- 33 | 0x8000,
- /* 0x01f80090, 0x01f80100, 0xff7f0200, 0xfe7f0300, */
- 0x01fa008c, 0x01fa0100, 0xff7f0200, 0xfe7f0300,
- 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
- 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
- 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
- 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
- 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
- 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
- 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
- 0xf84848f8
-};
-
-const u32 vpp_filter_coefs_bicubic[] = {
- 4,
- 33,
- 0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
- 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
- 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
- 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
- 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
- 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
- 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
- 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
- 0xf84848f8
-};
-
-const u32 vpp_filter_coefs_bilinear[] = {
- 4,
- 33,
- 0x00800000, 0x007e0200, 0x007c0400, 0x007a0600,
- 0x00780800, 0x00760a00, 0x00740c00, 0x00720e00,
- 0x00701000, 0x006e1200, 0x006c1400, 0x006a1600,
- 0x00681800, 0x00661a00, 0x00641c00, 0x00621e00,
- 0x00602000, 0x005e2200, 0x005c2400, 0x005a2600,
- 0x00582800, 0x00562a00, 0x00542c00, 0x00522e00,
- 0x00503000, 0x004e3200, 0x004c3400, 0x004a3600,
- 0x00483800, 0x00463a00, 0x00443c00, 0x00423e00,
- 0x00404000
-};
-
-const u32 vpp_3d_filter_coefs_bilinear[] = {
- 2,
- 33,
- 0x80000000, 0x7e020000, 0x7c040000, 0x7a060000,
- 0x78080000, 0x760a0000, 0x740c0000, 0x720e0000,
- 0x70100000, 0x6e120000, 0x6c140000, 0x6a160000,
- 0x68180000, 0x661a0000, 0x641c0000, 0x621e0000,
- 0x60200000, 0x5e220000, 0x5c240000, 0x5a260000,
- 0x58280000, 0x562a0000, 0x542c0000, 0x522e0000,
- 0x50300000, 0x4e320000, 0x4c340000, 0x4a360000,
- 0x48380000, 0x463a0000, 0x443c0000, 0x423e0000,
- 0x40400000
-};
-
-const u32 vpp_filter_coefs_3point_triangle[] = {
- 3,
- 33,
- 0x40400000, 0x3f400100, 0x3d410200, 0x3c410300,
- 0x3a420400, 0x39420500, 0x37430600, 0x36430700,
- 0x35430800, 0x33450800, 0x32450900, 0x31450a00,
- 0x30450b00, 0x2e460c00, 0x2d460d00, 0x2c470d00,
- 0x2b470e00, 0x29480f00, 0x28481000, 0x27481100,
- 0x26491100, 0x25491200, 0x24491300, 0x234a1300,
- 0x224a1400, 0x214a1500, 0x204a1600, 0x1f4b1600,
- 0x1e4b1700, 0x1d4b1800, 0x1c4c1800, 0x1b4c1900,
- 0x1a4c1a00
-};
-
-/* point_num =4, filt_len =4, group_num = 64, [1 2 1] */
-const u32 vpp_filter_coefs_4point_triangle[] = {
- 4,
- 33,
- 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
- 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
- 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
- 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
- 0x18382808, 0x18382808, 0x17372909, 0x17372909,
- 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
- 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
- 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
- 0x10303010
-};
-
-/*
- *4th order (cubic) b-spline
- *filt_cubic point_num =4, filt_len =4, group_num = 64, [1 5 1]
- */
-const u32 vpp_filter_coefs_4point_bspline[] = {
- 4,
- 33,
- 0x15561500, 0x14561600, 0x13561700, 0x12561800,
- 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
- 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
- 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
- 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
- 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
- 0x05473301, 0x05463401, 0x04453601, 0x04433702,
- 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
- 0x033d3d03
-};
-
-/*3rd order (quadratic) b-spline*/
-/*filt_quadratic, point_num =3, filt_len =3, group_num = 64, [1 6 1] */
-const u32 vpp_filter_coefs_3point_bspline[] = {
- 3,
- 33,
- 0x40400000, 0x3e420000, 0x3c440000, 0x3a460000,
- 0x38480000, 0x364a0000, 0x344b0100, 0x334c0100,
- 0x314e0100, 0x304f0100, 0x2e500200, 0x2c520200,
- 0x2a540200, 0x29540300, 0x27560300, 0x26570300,
- 0x24580400, 0x23590400, 0x215a0500, 0x205b0500,
- 0x1e5c0600, 0x1d5c0700, 0x1c5d0700, 0x1a5e0800,
- 0x195e0900, 0x185e0a00, 0x175f0a00, 0x15600b00,
- 0x14600c00, 0x13600d00, 0x12600e00, 0x11600f00,
- 0x10601000
-};
-
-/*filt_triangle, point_num =3, filt_len =2.6, group_num = 64, [1 7 1] */
-const u32 vpp_filter_coefs_3point_triangle_sharp[] = {
- 3,
- 33,
- 0x40400000, 0x3e420000, 0x3d430000, 0x3b450000,
- 0x3a460000, 0x38480000, 0x37490000, 0x354b0000,
- 0x344c0000, 0x324e0000, 0x314f0000, 0x2f510000,
- 0x2e520000, 0x2c540000, 0x2b550000, 0x29570000,
- 0x28580000, 0x265a0000, 0x245c0000, 0x235d0000,
- 0x215f0000, 0x20600000, 0x1e620000, 0x1d620100,
- 0x1b620300, 0x19630400, 0x17630600, 0x15640700,
- 0x14640800, 0x12640a00, 0x11640b00, 0x0f650c00,
- 0x0d660d00
-};
-
-const u32 vpp_filter_coefs_2point_binilear[] = {
- 2,
- 33,
- 0x80000000, 0x7e020000, 0x7c040000, 0x7a060000,
- 0x78080000, 0x760a0000, 0x740c0000, 0x720e0000,
- 0x70100000, 0x6e120000, 0x6c140000, 0x6a160000,
- 0x68180000, 0x661a0000, 0x641c0000, 0x621e0000,
- 0x60200000, 0x5e220000, 0x5c240000, 0x5a260000,
- 0x58280000, 0x562a0000, 0x542c0000, 0x522e0000,
- 0x50300000, 0x4e320000, 0x4c340000, 0x4a360000,
- 0x48380000, 0x463a0000, 0x443c0000, 0x423e0000,
- 0x40400000
-};
-
-static const u32 *filter_table[] = {
- vpp_filter_coefs_bicubic,
- vpp_filter_coefs_3point_triangle,
- vpp_filter_coefs_4point_triangle,
- vpp_filter_coefs_bilinear,
- vpp_filter_coefs_2point_binilear,
- vpp_filter_coefs_bicubic_sharp,
- vpp_filter_coefs_3point_triangle_sharp,
- vpp_filter_coefs_3point_bspline,
- vpp_filter_coefs_4point_bspline,
- vpp_3d_filter_coefs_bilinear
-};
-
-static int chroma_filter_table[] = {
- COEF_BICUBIC, /* bicubic */
- COEF_3POINT_TRIANGLE,
- COEF_4POINT_TRIANGLE,
- COEF_4POINT_TRIANGLE, /* bilinear */
- COEF_2POINT_BILINEAR,
- COEF_3POINT_TRIANGLE, /* bicubic_sharp */
- COEF_3POINT_TRIANGLE, /* 3point_triangle_sharp */
- COEF_3POINT_TRIANGLE, /* 3point_bspline */
- COEF_4POINT_TRIANGLE, /* 4point_bspline */
- COEF_3D_FILTER /* can not change */
-};
-
-static unsigned int vert_scaler_filter = 0xff;
-module_param(vert_scaler_filter, uint, 0664);
-MODULE_PARM_DESC(vert_scaler_filter, "vert_scaler_filter");
-
-static unsigned int vert_chroma_scaler_filter = 0xff;
-module_param(vert_chroma_scaler_filter, uint, 0664);
-MODULE_PARM_DESC(vert_chroma_scaler_filter, "vert_chroma_scaler_filter");
-
-static unsigned int horz_scaler_filter = 0xff;
-module_param(horz_scaler_filter, uint, 0664);
-MODULE_PARM_DESC(horz_scaler_filter, "horz_scaler_filter");
-
-bool pre_scaler_en = true;
-module_param(pre_scaler_en, bool, 0664);
-MODULE_PARM_DESC(pre_scaler_en, "pre_scaler_en");
-#endif
-/*bicubic*/
-static const unsigned int di_filt_coef0[] = {
- 0x00800000,
- 0x007f0100,
- 0xff7f0200,
- 0xfe7f0300,
- 0xfd7e0500,
- 0xfc7e0600,
- 0xfb7d0800,
- 0xfb7c0900,
- 0xfa7b0b00,
- 0xfa7a0dff,
- 0xf9790fff,
- 0xf97711ff,
- 0xf87613ff,
- 0xf87416fe,
- 0xf87218fe,
- 0xf8701afe,
- 0xf76f1dfd,
- 0xf76d1ffd,
- 0xf76b21fd,
- 0xf76824fd,
- 0xf76627fc,
- 0xf76429fc,
- 0xf7612cfc,
- 0xf75f2ffb,
- 0xf75d31fb,
- 0xf75a34fb,
- 0xf75837fa,
- 0xf7553afa,
- 0xf8523cfa,
- 0xf8503ff9,
- 0xf84d42f9,
- 0xf84a45f9,
- 0xf84848f8
-};
-
-/* 2 point bilinear */
-static const unsigned int di_filt_coef1[] = {
- 0x00800000,
- 0x007e0200,
- 0x007c0400,
- 0x007a0600,
- 0x00780800,
- 0x00760a00,
- 0x00740c00,
- 0x00720e00,
- 0x00701000,
- 0x006e1200,
- 0x006c1400,
- 0x006a1600,
- 0x00681800,
- 0x00661a00,
- 0x00641c00,
- 0x00621e00,
- 0x00602000,
- 0x005e2200,
- 0x005c2400,
- 0x005a2600,
- 0x00582800,
- 0x00562a00,
- 0x00542c00,
- 0x00522e00,
- 0x00503000,
- 0x004e3200,
- 0x004c3400,
- 0x004a3600,
- 0x00483800,
- 0x00463a00,
- 0x00443c00,
- 0x00423e00,
- 0x00404000
-};
-
-/* 2 point bilinear, bank_length == 2*/
-static const unsigned int di_filt_coef2[] = {
- 0x80000000,
- 0x7e020000,
- 0x7c040000,
- 0x7a060000,
- 0x78080000,
- 0x760a0000,
- 0x740c0000,
- 0x720e0000,
- 0x70100000,
- 0x6e120000,
- 0x6c140000,
- 0x6a160000,
- 0x68180000,
- 0x661a0000,
- 0x641c0000,
- 0x621e0000,
- 0x60200000,
- 0x5e220000,
- 0x5c240000,
- 0x5a260000,
- 0x58280000,
- 0x562a0000,
- 0x542c0000,
- 0x522e0000,
- 0x50300000,
- 0x4e320000,
- 0x4c340000,
- 0x4a360000,
- 0x48380000,
- 0x463a0000,
- 0x443c0000,
- 0x423e0000,
- 0x40400000
-};
-
-#define ZOOM_BITS 20
-#define PHASE_BITS 16
-
-static enum f2v_vphase_type_e top_conv_type = F2V_P2P;
-static enum f2v_vphase_type_e bot_conv_type = F2V_P2P;
-static unsigned int prehsc_en;
-static unsigned int prevsc_en;
-
-static const unsigned char f2v_420_in_pos_luma[F2V_TYPE_MAX] = {
-0, 2, 0, 2, 0, 0, 0, 2, 0};
-#if 0
-static const unsigned char f2v_420_in_pos_chroma[F2V_TYPE_MAX] = {
- 1, 5, 1, 5, 2, 2, 1, 5, 2};
-#endif
-static const unsigned char f2v_420_out_pos[F2V_TYPE_MAX] = {
-0, 2, 2, 0, 0, 2, 0, 0, 0};
-
-static void f2v_get_vertical_phase(unsigned int zoom_ratio,
- enum f2v_vphase_type_e type,
- unsigned char bank_length,
- struct pps_f2v_vphase_s *vphase)
-{
- int offset_in, offset_out;
-
- /* luma */
- offset_in = f2v_420_in_pos_luma[type] << PHASE_BITS;
- offset_out = (f2v_420_out_pos[type] * zoom_ratio)
- >> (ZOOM_BITS - PHASE_BITS);
-
- vphase->rcv_num = bank_length;
- if (bank_length == 4 || bank_length == 3)
- vphase->rpt_num = 1;
- else
- vphase->rpt_num = 0;
-
- if (offset_in > offset_out) {
- vphase->rpt_num = vphase->rpt_num + 1;
- vphase->phase =
- ((4 << PHASE_BITS) + offset_out - offset_in) >> 2;
- } else {
- while ((offset_in + (4 << PHASE_BITS)) <= offset_out) {
- if (vphase->rpt_num == 1)
- vphase->rpt_num = 0;
- else
- vphase->rcv_num++;
- offset_in += 4 << PHASE_BITS;
- }
- vphase->phase = (offset_out - offset_in) >> 2;
- }
-}
-
-/*
- * patch 1: inp scaler 0: di wr scaler
- * support: TM2
- * not support: SM1
- */
-void dimv3_pps_config(unsigned char path, int src_w, int src_h,
- int dst_w, int dst_h)
-{
- struct pps_f2v_vphase_s vphase;
-
- int i;
- int hsc_en = 0, vsc_en = 0;
- int vsc_double_line_mode;
- unsigned int p_src_w, p_src_h;
- unsigned int vert_phase_step, horz_phase_step;
- unsigned char top_rcv_num, bot_rcv_num;
- unsigned char top_rpt_num, bot_rpt_num;
- unsigned short top_vphase, bot_vphase;
- unsigned char is_frame;
- int vert_bank_length = 4;
-
- const unsigned int *filt_coef0 = di_filt_coef0;
- /*unsigned int *filt_coef1 = di_filt_coef1;*/
- const unsigned int *filt_coef2 = di_filt_coef2;
-
- vsc_double_line_mode = 0;
-
- if (src_h != dst_h)
- vsc_en = 1;
- if (src_w != dst_w)
- hsc_en = 1;
- /* config hdr size */
- Wr_reg_bits(DI_HDR_IN_HSIZE, dst_w, 0, 13);
- Wr_reg_bits(DI_HDR_IN_VSIZE, dst_h, 0, 13);
- p_src_w = (prehsc_en ? ((src_w + 1) >> 1) : src_w);
- p_src_h = prevsc_en ? ((src_h + 1) >> 1) : src_h;
-
- Wr(DI_SC_HOLD_LINE, 0x10);
-
- if (p_src_w > 2048) {
- /*force vert bank length = 2*/
- vert_bank_length = 2;
- vsc_double_line_mode = 1;
- }
-
- /*write vert filter coefs*/
- Wr(DI_SC_COEF_IDX, 0x0000);
- for (i = 0; i < 33; i++) {
- if (vert_bank_length == 2)
- Wr(DI_SC_COEF, filt_coef2[i]); /*bilinear*/
- else
- Wr(DI_SC_COEF, filt_coef0[i]); /*bicubic*/
- }
-
- /*write horz filter coefs*/
- Wr(DI_SC_COEF_IDX, 0x0100);
- for (i = 0; i < 33; i++)
- Wr(DI_SC_COEF, filt_coef0[i]); /*bicubic*/
-
- if (p_src_h > 2048)
- vert_phase_step = ((p_src_h << 18) / dst_h) << 2;
- else
- vert_phase_step = (p_src_h << 20) / dst_h;
- if (p_src_w > 2048)
- horz_phase_step = ((p_src_w << 18) / dst_w) << 2;
- else
- horz_phase_step = (p_src_w << 20) / dst_w;
-
- is_frame = ((top_conv_type == F2V_IT2P) ||
- (top_conv_type == F2V_IB2P) ||
- (top_conv_type == F2V_P2P));
-
- if (is_frame) {
- f2v_get_vertical_phase(vert_phase_step, top_conv_type,
- vert_bank_length, &vphase);
- top_rcv_num = vphase.rcv_num;
- top_rpt_num = vphase.rpt_num;
- top_vphase = vphase.phase;
-
- bot_rcv_num = 0;
- bot_rpt_num = 0;
- bot_vphase = 0;
- } else {
- f2v_get_vertical_phase(vert_phase_step, top_conv_type,
- vert_bank_length, &vphase);
- top_rcv_num = vphase.rcv_num;
- top_rpt_num = vphase.rpt_num;
- top_vphase = vphase.phase;
-
- f2v_get_vertical_phase(vert_phase_step, bot_conv_type,
- vert_bank_length, &vphase);
- bot_rcv_num = vphase.rcv_num;
- bot_rpt_num = vphase.rpt_num;
- bot_vphase = vphase.phase;
- }
- vert_phase_step = (vert_phase_step << 4);
- horz_phase_step = (horz_phase_step << 4);
-
- Wr(DI_SC_LINE_IN_LENGTH, src_w);
- Wr(DI_SC_PIC_IN_HEIGHT, src_h);
- Wr(DI_VSC_REGION12_STARTP, 0);
- Wr(DI_VSC_REGION34_STARTP, ((dst_h << 16) | dst_h));
- Wr(DI_VSC_REGION4_ENDP, (dst_h - 1));
-
- Wr(DI_VSC_START_PHASE_STEP, vert_phase_step);
- Wr(DI_VSC_REGION0_PHASE_SLOPE, 0);
- Wr(DI_VSC_REGION1_PHASE_SLOPE, 0);
- Wr(DI_VSC_REGION3_PHASE_SLOPE, 0);
- Wr(DI_VSC_REGION4_PHASE_SLOPE, 0);
-
- Wr(DI_VSC_PHASE_CTRL,
- ((vsc_double_line_mode << 17) |
- (!is_frame) << 16) |
- (0 << 15) |
- (bot_rpt_num << 13) |
- (bot_rcv_num << 8) |
- (0 << 7) |
- (top_rpt_num << 5) |
- (top_rcv_num));
- Wr(DI_VSC_INI_PHASE, (bot_vphase << 16) | top_vphase);
- Wr(DI_HSC_REGION12_STARTP, 0);
- Wr(DI_HSC_REGION34_STARTP, (dst_w << 16) | dst_w);
- Wr(DI_HSC_REGION4_ENDP, dst_w - 1);
-
- Wr(DI_HSC_START_PHASE_STEP, horz_phase_step);
- Wr(DI_HSC_REGION0_PHASE_SLOPE, 0);
- Wr(DI_HSC_REGION1_PHASE_SLOPE, 0);
- Wr(DI_HSC_REGION3_PHASE_SLOPE, 0);
- Wr(DI_HSC_REGION4_PHASE_SLOPE, 0);
-
- Wr(DI_HSC_PHASE_CTRL, (1 << 21) | (4 << 16) | 0);
- Wr_reg_bits(DI_SC_TOP_CTRL, (path ? 3 : 0), 29, 2);
- Wr(DI_SC_MISC,
- (prevsc_en << 21) |
- (prehsc_en << 20) | /* prehsc_en */
- (prevsc_en << 19) | /* prevsc_en */
- (vsc_en << 18) | /* vsc_en */
- (hsc_en << 17) | /* hsc_en */
- ((vsc_en | hsc_en) << 16) | /* sc_top_en */
- (1 << 15) | /* vd1 sc out enable */
- (0 << 12) | /* horz nonlinear 4region enable */
- (4 << 8) | /* horz scaler bank length */
- (0 << 5) | /* vert scaler phase field enable */
- (0 << 4) | /* vert nonlinear 4region enable */
- (vert_bank_length << 0) /* vert scaler bank length */
- );
-
- PR_INF("[pps] %s input %d %d output %d %d.\n",
- path ? "pre" : "post", src_w, src_h, dst_w, dst_h);
-}
-
-/*
- * 0x374e ~ 0x376d, 20 regs
- */
-void dimv3_dump_pps_reg(unsigned int base_addr)
-{
- unsigned int i = 0x374e;
-
- pr_info("-----dump pps start-----\n");
- for (i = 0x374e; i < 0x376e; i++) {
- pr_info("[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2),
- i, dimv3_RDMA_RD(i));
- }
- pr_info("-----dump pps end-----\n");
-}
-
-/*
- * di pre h scaling down function
- * only have h scaling down
- * support: sm1 tm2 ...
- * 0x37b0 ~ 0x37b5
- */
-void dimv3_inp_hsc_setting(u32 src_w, u32 dst_w)
-{
- u32 i;
- u32 hsc_en;
- u32 horz_phase_step;
- const int *filt_coef0 = di_filt_coef0;
- /*int *filt_coef1 = di_filt_coef1;*/
- /*int *filt_coef2 = di_filt_coef2;*/
-
- if (src_w == dst_w) {
- hsc_en = 0;
- } else {
- hsc_en = 1;
- /*write horz filter coefs*/
- dimv3_RDMA_WR(DI_VIU_HSC_COEF_IDX, 0x0100);
- for (i = 0; i < 33; i++) /*bicubic*/
- dimv3_RDMA_WR(DI_VIU_HSC_COEF, filt_coef0[i]);
-
- horz_phase_step = (src_w << 20) / dst_w;
- horz_phase_step = (horz_phase_step << 4);
- dimv3_RDMA_WR(DI_VIU_HSC_WIDTHM1,
- (src_w - 1) << 16 | (dst_w - 1));
- dimv3_RDMA_WR(DI_VIU_HSC_PHASE_STEP, horz_phase_step);
- dimv3_RDMA_WR(DI_VIU_HSC_PHASE_CTRL, 0);
- }
- dimv3_RDMA_WR(DI_VIU_HSC_CTRL,
- (4 << 20) | /* initial receive number*/
- (0 << 12) | /* initial pixel ptr*/
- (1 << 10) | /* repeat first pixel number*/
- (0 << 8) | /* sp422 mode*/
- (4 << 4) | /* horz scaler bank length*/
- (0 << 2) | /* phase0 always en*/
- (0 << 1) | /* nearest_en*/
- (hsc_en << 0)); /* hsc_en*/
-}
-
-/*
- * 0x37b0 ~ 0x37b5
- */
-void dimv3_dump_hdownscler_reg(unsigned int base_addr)
-{
- unsigned int i = 0x374e;
-
- pr_info("-----dump hdownscler start-----\n");
- for (i = 0x37b0; i < 0x37b5; i++) {
- pr_info("[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2),
- i, dimv3_RDMA_RD(i));
- }
- pr_info("-----dump hdownscler end-----\n");
-}
-
-int dimv3_seq_file_module_para_pps(struct seq_file *seq)
-{
- seq_puts(seq, "pps---------------\n");
-
- return 0;
-}
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pps.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef DI_PPS_H
-#define DI_PPS_H
-#include <linux/amlogic/media/video_sink/video.h>
-#include <linux/amlogic/media/video_sink/vpp.h>
-#if 0
-#define VPP_FLAG_WIDEMODE_MASK 0x0000000F
-#define VPP_FLAG_INTERLACE_OUT 0x00000010
-#define VPP_FLAG_INTERLACE_IN 0x00000020
-#define VPP_FLAG_CBCR_SEPARATE 0x00000040
-#define VPP_FLAG_ZOOM_SHORTSIDE 0x00000080
-#define VPP_FLAG_AR_MASK 0x0003ff00
-#define VPP_FLAG_AR_BITS 8
-#define VPP_FLAG_PORTRAIT_MODE 0x00040000
-#define VPP_FLAG_VSCALE_DISABLE 0x00080000
-
-#define IDX_H (2 << 8)
-#define IDX_V_Y (1 << 13)
-#define IDX_V_CBCR ((1 << 13) | (1 << 8))
-
-#define ASPECT_4_3 ((3 << 8) / 4)
-#define ASPECT_16_9 ((9 << 8) / 16)
-
-#define SPEED_CHECK_DONE 0
-#define SPEED_CHECK_HSKIP 1
-#define SPEED_CHECK_VSKIP 2
-
-enum f2v_vphase_type_e {
- F2V_IT2IT = 0,
- F2V_IB2IB,
- F2V_IT2IB,
- F2V_IB2IT,
- F2V_P2IT,
- F2V_P2IB,
- F2V_IT2P,
- F2V_IB2P,
- F2V_P2P,
- F2V_TYPE_MAX
-}; /* frame to video conversion type */
-#endif
-
-enum hdr2_scaler_e {
- hdr2_scaler_postdi = 0,
- hdr2_scaler_predi = 1,
-};
-
-struct pps_f2v_vphase_s {
- unsigned char rcv_num;
- unsigned char rpt_num;
- unsigned short phase;
-};
-
-struct ppsfilter_mode_s {
- u32 pps_hf_start_phase_step;
- u32 pps_hf_start_phase_slope;
- u32 pps_hf_end_phase_slope;
- const u32 *pps_vert_coeff;
- const u32 *pps_horz_coeff;
- u32 pps_sc_misc_;
- u32 pps_vsc_start_phase_step;
- u32 pps_hsc_start_phase_step;
- bool pps_pre_vsc_en;
- bool pps_pre_hsc_en;
- u32 pps_vert_filter;
- u32 pps_horz_filter;
- const u32 *pps_chroma_coeff;
- u32 pps_chroma_filter_en;
-};
-
-struct pps_frame_par_s {
- u32 pps_vsc_startp;
- u32 pps_vsc_endp;
- u32 pps_hsc_startp;
- u32 pps_hsc_linear_startp;
- u32 pps_hsc_linear_endp;
- u32 pps_hsc_endp;
- u32 VPP_hf_ini_phase_;
- struct f2v_vphase_s VPP_vf_ini_phase_[9];
- u32 pps_pic_in_height_;
- u32 pps_line_in_length_;
- struct ppsfilter_mode_s pps_filter;
- u32 pps_3d_mode;
- u32 trans_fmt;
- /* bit[1:0] 0: 1 pic,1:two pic one buf,2:tow pic two buf */
- /* bit[2]0:select pic0,1:select pic1 */
- /* bit[3]0:pic0 first,1:pic1 first */
- bool pps_3d_scale;
-};
-
-void dimv3_pps_config(unsigned char path, int src_w, int src_h,
- int dst_w, int dst_h);
-void dimv3_dump_pps_reg(unsigned int base_addr);
-void dimv3_inp_hsc_setting(u32 src_w, u32 dst_w);
-void dimv3_dump_hdownscler_reg(unsigned int base_addr);
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_prc.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-#include <linux/of_fdt.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "deinterlace.h"
-
-#include "di_data_l.h"
-#include "di_data.h"
-#include "di_dbg.h"
-#include "di_sys.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_prc.h"
-#include "di_pre.h"
-#include "di_pre_hw.h"
-#include "di_post.h"
-#include "di_api.h"
-
-/**************************************
- *
- * cfg ctr top
- * bool
- **************************************/
-
-const struct di_cfg_ctr_s div3_cfg_top_ctr[K_DI_CFG_NUB] = {
- /*same order with enum eDI_DBG_CFG*/
- /* cfg for top */
- [EDI_CFG_BEGIN] = {"cfg top begin ", EDI_CFG_BEGIN, 0,
- K_DI_CFG_T_FLG_NONE},
- [EDI_CFG_CH_NUB] = {"ch_nub", EDI_CFG_CH_NUB, 1,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_mem_flg] = {"flag_cma", EDI_CFG_mem_flg,
- eDI_MEM_M_cma,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_first_bypass] = {"first_bypass",
- EDI_CFG_first_bypass,
- 0,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_ref_2] = {"ref_2",
- EDI_CFG_ref_2, 0, K_DI_CFG_T_FLG_NOTHING},
- [EDI_CFG_PMODE] = {"pmode:0:as p;1:as i;2:use 2 i buf",
- EDI_CFG_PMODE,
- 1,
- K_DI_CFG_T_FLG_NOTHING},
- [EDI_CFG_KEEP_CLEAR_AUTO] = {"keep_buf clear auto",
- EDI_CFG_KEEP_CLEAR_AUTO,
- 1,
- K_DI_CFG_T_FLG_NOTHING},
- [EDI_CFG_PRE_RST_OLD_FLOW] = {"pre_rst_old_flow",
- EDI_CFG_PRE_RST_OLD_FLOW,
- 0,
- K_DI_CFG_T_FLG_NOTHING},
-
- [EDI_CFG_TMODE_1] = {"tmode1",
- EDI_CFG_TMODE_1,
- 1,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_TMODE_2] = {"tmode2",
- EDI_CFG_TMODE_2,
- 1,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_TMODE_3] = {"tmode3",
- EDI_CFG_TMODE_3,
- 0,
- K_DI_CFG_T_FLG_DTS},
- [EDI_CFG_DBG] = {"dbg only",
- EDI_CFG_DBG, 0x00, K_DI_CFG_T_FLG_NOTHING},
- [EDI_CFG_END] = {"cfg top end ", EDI_CFG_END, 0,
- K_DI_CFG_T_FLG_NONE},
-
-};
-
-char *div3_cfg_top_get_name(enum eDI_CFG_TOP_IDX idx)
-{
- return div3_cfg_top_ctr[idx].dts_name;
-}
-
-void div3_cfg_top_get_info(unsigned int idx, char **name)
-{
- if (div3_cfg_top_ctr[idx].id != idx)
- PR_ERR("%s:err:idx not map [%d->%d]\n", __func__,
- idx, div3_cfg_top_ctr[idx].id);
-
- *name = div3_cfg_top_ctr[idx].dts_name;
-}
-
-bool div3_cfg_top_check(unsigned int idx)
-{
- unsigned int tsize;
-
- tsize = ARRAY_SIZE(div3_cfg_top_ctr);
- if (idx >= tsize) {
- PR_ERR("%s:err:overflow:%d->%d\n",
- __func__, idx, tsize);
- return false;
- }
- if (div3_cfg_top_ctr[idx].flg & K_DI_CFG_T_FLG_NONE)
- return false;
- if (idx != div3_cfg_top_ctr[idx].id) {
- PR_ERR("%s:%s:err:not map:%d->%d\n",
- __func__,
- div3_cfg_top_ctr[idx].dts_name,
- idx,
- div3_cfg_top_ctr[idx].id);
- return false;
- }
- #if 0
- pr_info("\t%-15s=%d\n", div3_cfg_top_ctr[idx].name,
- div3_cfg_top_ctr[idx].default_val);
- #endif
- return true;
-}
-
-void div3_cfg_top_init_val(void)
-{
- int i;
- union di_cfg_tdata_u *pd;
- const struct di_cfg_ctr_s *pt;
-
- PR_INF("%s:\n", __func__);
- for (i = EDI_CFG_BEGIN; i < EDI_CFG_END; i++) {
- if (!div3_cfg_top_check(i))
- continue;
- pd = &get_datal()->cfg_en[i];
- pt = &div3_cfg_top_ctr[i];
-
- /*di_cfg_top_set(i, di_cfg_top_ctr[i].default_val);*/
- pd->d32 = 0;/*clear*/
- pd->b.val_df = pt->default_val;
- pd->b.val_c = pd->b.val_df;
- }
- PR_INF("%s:finish\n", __func__);
-}
-
-/*after init*/
-void div3_cfg_top_dts(void)
-{
- struct platform_device *pdev = getv3_dim_de_devp()->pdev;
- int i;
- union di_cfg_tdata_u *pd;
- const struct di_cfg_ctr_s *pt;
- int ret;
- unsigned int uval;
-
- if (!pdev) {
- PR_ERR("%s:no pdev\n", __func__);
- return;
- }
- PR_INF("%s\n", __func__);
-
- for (i = EDI_CFG_BEGIN; i < EDI_CFG_END; i++) {
- if (!div3_cfg_top_check(i))
- continue;
- if (!(div3_cfg_top_ctr[i].flg & K_DI_CFG_T_FLG_DTS))
- continue;
-
- pd = &get_datal()->cfg_en[i];
- pt = &div3_cfg_top_ctr[i];
- pd->b.dts_en = 1;
-
- ret = of_property_read_u32(pdev->dev.of_node,
- pt->dts_name,
- &uval);
- if (ret)
- continue;
- PR_INF("\t%s:%d\n", pt->dts_name, uval);
-
- pd->b.dts_have = 1;
- pd->b.val_dts = uval;
- pd->b.val_c = pd->b.val_dts;
- }
- PR_INF("%s end\n", __func__);
-}
-
-/*item: one /all; include table/val*/
-/*val: one /all; only val*/
-static void di_cfgt_show_item_one(struct seq_file *s, unsigned int index)
-{
- union di_cfg_tdata_u *pd;
- const struct di_cfg_ctr_s *pt;
-
- if (!div3_cfg_top_check(index))
- return;
-
- pd = &get_datal()->cfg_en[index];
- pt = &div3_cfg_top_ctr[index];
-
- seq_printf(s, "id:%2d:%-10s\n", index, pt->dts_name);
- /*tab*/
- seq_printf(s, "\t%-5s:0x%2x[%d]\n",
- "tdf", pt->default_val, pt->default_val);
- seq_printf(s, "\t%-5s:%d\n",
- "tdts", pt->flg & K_DI_CFG_T_FLG_DTS);
- /*val*/
- seq_printf(s, "\t%-5s:0x%-4x\n", "d32", pd->d32);
- seq_printf(s, "\t%-5s:0x%2x[%d]\n",
- "vdf", pd->b.val_df, pd->b.val_df);
- seq_printf(s, "\t%-5s:0x%2x[%d]\n",
- "vdts", pd->b.val_dts, pd->b.val_dts);
- seq_printf(s, "\t%-5s:0x%2x[%d]\n",
- "vdbg", pd->b.val_dbg, pd->b.val_dbg);
- seq_printf(s, "\t%-5s:0x%2x[%d]\n", "vc", pd->b.val_c, pd->b.val_c);
- seq_printf(s, "\t%-5s:%d\n", "endts", pd->b.dts_en);
- seq_printf(s, "\t%-5s:%d\n", "hdts", pd->b.dts_have);
- seq_printf(s, "\t%-5s:%d\n", "hdbg", pd->b.dbg_have);
-}
-
-void div3_cfgt_show_item_sel(struct seq_file *s)
-{
- int i = get_datal()->cfg_sel;
-
- di_cfgt_show_item_one(s, i);
-}
-
-void div3_cfgt_set_sel(unsigned int dbg_mode, unsigned int id)
-{
- if (!div3_cfg_top_check(id)) {
- PR_ERR("%s:%d is overflow\n", __func__, id);
- return;
- }
-
- get_datal()->cfg_sel = id;
- get_datal()->cfg_dbg_mode = dbg_mode;
-}
-
-void div3_cfgt_show_item_all(struct seq_file *s)
-{
- int i;
-
- for (i = EDI_CFG_BEGIN; i < EDI_CFG_END; i++)
- di_cfgt_show_item_one(s, i);
-}
-
-static void di_cfgt_show_val_one(struct seq_file *s, unsigned int index)
-{
- union di_cfg_tdata_u *pd;
- const struct di_cfg_ctr_s *pt;
-
- if (!div3_cfg_top_check(index))
- return;
-
- pd = &get_datal()->cfg_en[index];
- pt = &div3_cfg_top_ctr[index];
-
- seq_printf(s, "id:%2d:%-10s\n", index, pt->dts_name);
-
- seq_printf(s, "\t%-5s:0x%-4x\n", "d32", pd->d32);
- seq_printf(s, "\t%-5s:0x%2x[%d]\n", "vc", pd->b.val_c, pd->b.val_c);
-}
-
-void div3_cfgt_show_val_sel(struct seq_file *s)
-{
- unsigned int i = get_datal()->cfg_sel;
-
- di_cfgt_show_val_one(s, i);
-}
-
-void div3_cfgt_show_val_all(struct seq_file *s)
-{
- int i;
-
- for (i = EDI_CFG_BEGIN; i < EDI_CFG_END; i++)
- di_cfgt_show_val_one(s, i);
-}
-
-unsigned int div3_cfg_top_get(enum eDI_CFG_TOP_IDX id)
-{
- union di_cfg_tdata_u *pd;
-
- pd = &get_datal()->cfg_en[id];
- return pd->b.val_c;
-}
-
-void div3_cfg_top_set(enum eDI_CFG_TOP_IDX id, unsigned int val)
-{
- union di_cfg_tdata_u *pd;
-
- pd = &get_datal()->cfg_en[id];
- pd->b.val_dbg = val;
- pd->b.dbg_have = 1;
- pd->b.val_c = val;
-}
-
-/**************************************
- *
- * cfg ctr x
- * bool
- **************************************/
-
-const struct di_cfgx_ctr_s div3_cfgx_ctr[K_DI_CFGX_NUB] = {
- /*same order with enum eDI_DBG_CFG*/
-
- /* cfg channel x*/
- [eDI_CFGX_BEGIN] = {"cfg x begin ", eDI_CFGX_BEGIN, 0},
- /* bypass_all */
- [eDI_CFGX_BYPASS_ALL] = {"bypass_all", eDI_CFGX_BYPASS_ALL, 0},
- [EDI_CFGX_HOLD_VIDEO] = {"hold_video", EDI_CFGX_HOLD_VIDEO, 0},
- [eDI_CFGX_END] = {"cfg x end ", eDI_CFGX_END, 0},
-
- /* debug cfg x */
- [eDI_DBG_CFGX_BEGIN] = {"cfg dbg begin ", eDI_DBG_CFGX_BEGIN, 0},
- [eDI_DBG_CFGX_IDX_VFM_IN] = {"vfm_in", eDI_DBG_CFGX_IDX_VFM_IN, 0},
- [eDI_DBG_CFGX_IDX_VFM_OT] = {"vfm_out", eDI_DBG_CFGX_IDX_VFM_OT, 1},
- [eDI_DBG_CFGX_END] = {"cfg dbg end", eDI_DBG_CFGX_END, 0},
-};
-
-char *div3_cfgx_get_name(enum eDI_CFGX_IDX idx)
-{
- return div3_cfgx_ctr[idx].name;
-}
-
-void div3_cfgx_get_info(enum eDI_CFGX_IDX idx, char **name)
-{
- if (div3_cfgx_ctr[idx].id != idx)
- PR_ERR("%s:err:idx not map [%d->%d]\n", __func__,
- idx, div3_cfgx_ctr[idx].id);
-
- *name = div3_cfgx_ctr[idx].name;
-}
-
-bool div3_cfgx_check(unsigned int idx)
-{
- unsigned int tsize;
-
- tsize = ARRAY_SIZE(div3_cfgx_ctr);
- if (idx >= tsize) {
- PR_ERR("%s:err:overflow:%d->%d\n",
- __func__, idx, tsize);
- return false;
- }
- if (idx != div3_cfgx_ctr[idx].id) {
- PR_ERR("%s:err:not map:%d->%d\n",
- __func__, idx, div3_cfgx_ctr[idx].id);
- return false;
- }
- PR_INF("\t%-15s=%d\n", div3_cfgx_ctr[idx].name,
- div3_cfgx_ctr[idx].default_val);
- return true;
-}
-
-void div3_cfgx_init_val(void)
-{
- int i, ch;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- for (i = eDI_CFGX_BEGIN; i < eDI_DBG_CFGX_END; i++)
- div3_cfgx_set(ch, i, div3_cfgx_ctr[i].default_val);
- }
-}
-
-bool div3_cfgx_get(unsigned int ch, enum eDI_CFGX_IDX idx)
-{
- return get_datal()->ch_data[ch].cfgx_en[idx];
-}
-
-void div3_cfgx_set(unsigned int ch, enum eDI_CFGX_IDX idx, bool en)
-{
- get_datal()->ch_data[ch].cfgx_en[idx] = en;
-}
-
-/**************************************
- *
- * module para top
- * int
- **************************************/
-
-const struct di_mp_uit_s div3_mp_ui_top[] = {
- /*same order with enum eDI_MP_UI*/
- /* for top */
- [eDI_MP_UI_T_BEGIN] = {"module para top begin ",
- eDI_MP_UI_T_BEGIN, 0},
- /**************************************/
- [eDI_MP_SUB_DI_B] = {"di begin ",
- eDI_MP_SUB_DI_B, 0},
- [eDI_MP_force_prog] = {"bool:force_prog:1",
- eDI_MP_force_prog, 1},
- [edi_mp_combing_fix_en] = {"bool:combing_fix_en,def:1",
- edi_mp_combing_fix_en, 1},
- [eDI_MP_cur_lev] = {"int cur_lev,def:2",
- eDI_MP_cur_lev, 2},
- [eDI_MP_pps_dstw] = {"pps_dstw:int",
- eDI_MP_pps_dstw, 0},
- [eDI_MP_pps_dsth] = {"pps_dsth:int",
- eDI_MP_pps_dsth, 0},
- [eDI_MP_pps_en] = {"pps_en:bool",
- eDI_MP_pps_en, 0},
- [eDI_MP_pps_position] = {"pps_position:uint:def:1",
- eDI_MP_pps_position, 1},
- [eDI_MP_pre_enable_mask] = {"pre_enable_mask:bit0:ma;bit1:mc:def:3",
- eDI_MP_pre_enable_mask, 3},
- [eDI_MP_post_refresh] = {"post_refresh:bool",
- eDI_MP_post_refresh, 0},
- [eDI_MP_nrds_en] = {"nrds_en:bool",
- eDI_MP_nrds_en, 0},
- [eDI_MP_bypass_3d] = {"bypass_3d:int:def:1",
- eDI_MP_bypass_3d, 1},
- [eDI_MP_bypass_trick_mode] = {"bypass_trick_mode:int:def:1",
- eDI_MP_bypass_trick_mode, 1},
- [eDI_MP_invert_top_bot] = {"invert_top_bot:int",
- eDI_MP_invert_top_bot, 0},
- [eDI_MP_skip_top_bot] = {"skip_top_bot:int:",
- /*1or2: may affect atv when bypass di*/
- eDI_MP_skip_top_bot, 0},
- [eDI_MP_force_width] = {"force_width:int",
- eDI_MP_force_width, 0},
- [eDI_MP_force_height] = {"force_height:int",
- eDI_MP_force_height, 0},
- [eDI_MP_prog_proc_config] = {"prog_proc_config:int:def:0x23",
-/* prog_proc_config,
- * bit[2:1]: when two field buffers are used,
- * 0 use vpp for blending ,
- * 1 use post_di module for blending
- * 2 debug mode, bob with top field
- * 3 debug mode, bot with bot field
- * bit[0]:
- * 0 "prog vdin" use two field buffers,
- * 1 "prog vdin" use single frame buffer
- * bit[4]:
- * 0 "prog frame from decoder/vdin" use two field buffers,
- * 1 use single frame buffer
- * bit[5]:
- * when two field buffers are used for decoder (bit[4] is 0):
- * 1,handle prog frame as two interlace frames
- * bit[6]:(bit[4] is 0,bit[5] is 0,use_2_interlace_buff is 0): 0,
- * process progress frame as field,blend by post;
- * 1, process progress frame as field,process by normal di
- */
- eDI_MP_prog_proc_config, ((1 << 5) | (1 << 1) | 1)},
- [eDI_MP_start_frame_drop_count] = {"start_frame_drop_count:int:2",
- eDI_MP_start_frame_drop_count, 0}, /*from 2 to 0*/
- [eDI_MP_same_field_top_count] = {"same_field_top_count:long?",
- eDI_MP_same_field_top_count, 0},
- [eDI_MP_same_field_bot_count] = {"same_field_bot_count:long?",
- eDI_MP_same_field_bot_count, 0},
- [eDI_MP_vpp_3d_mode] = {"vpp_3d_mode:int",
- eDI_MP_vpp_3d_mode, 0},
- [eDI_MP_force_recovery_count] = {"force_recovery_count:uint",
- eDI_MP_force_recovery_count, 0},
- [eDI_MP_pre_process_time] = {"pre_process_time:int",
- eDI_MP_pre_process_time, 0},
- [eDI_MP_bypass_post] = {"bypass_post:int",
- eDI_MP_bypass_post, 0},
- [eDI_MP_post_wr_en] = {"post_wr_en:bool:1",
- eDI_MP_post_wr_en, 1},
- [eDI_MP_post_wr_support] = {"post_wr_support:uint",
- eDI_MP_post_wr_support, 0},
- [eDI_MP_bypass_post_state] = {"bypass_post_state:int",
-/* 0, use di_wr_buf still;
- * 1, call dim_pre_de_done_buf_clear to clear di_wr_buf;
- * 2, do nothing
- */
- eDI_MP_bypass_post_state, 0},
- [eDI_MP_use_2_interlace_buff] = {"use_2_interlace_buff:int",
- eDI_MP_use_2_interlace_buff, 0},
- [eDI_MP_debug_blend_mode] = {"debug_blend_mode:int:-1",
- eDI_MP_debug_blend_mode, -1},
- [eDI_MP_nr10bit_support] = {"nr10bit_support:uint",
- /* 0: not support nr10bit, 1: support nr10bit */
- eDI_MP_nr10bit_support, 0},
- [eDI_MP_di_stop_reg_flag] = {"di_stop_reg_flag:uint",
- eDI_MP_di_stop_reg_flag, 0},
- [eDI_MP_mcpre_en] = {"mcpre_en:bool:true",
- eDI_MP_mcpre_en, 1},
- [eDI_MP_check_start_drop_prog] = {"check_start_drop_prog:bool",
- eDI_MP_check_start_drop_prog, 0},
- [eDI_MP_overturn] = {"overturn:bool:?",
- eDI_MP_overturn, 0},
- [eDI_MP_full_422_pack] = {"full_422_pack:bool",
- eDI_MP_full_422_pack, 0},
- [eDI_MP_cma_print] = {"cma_print:bool:1",
- eDI_MP_cma_print, 0},
- [eDI_MP_pulldown_enable] = {"pulldown_enable:bool:1",
- eDI_MP_pulldown_enable, 1},
- [eDI_MP_di_force_bit_mode] = {"di_force_bit_mode:uint:10",
- eDI_MP_di_force_bit_mode, 10},
- [eDI_MP_calc_mcinfo_en] = {"calc_mcinfo_en:bool:1",
- eDI_MP_calc_mcinfo_en, 1},
- [eDI_MP_colcfd_thr] = {"colcfd_thr:uint:128",
- eDI_MP_colcfd_thr, 128},
- [eDI_MP_post_blend] = {"post_blend:uint",
- eDI_MP_post_blend, 0},
- [eDI_MP_post_ei] = {"post_ei:uint",
- eDI_MP_post_ei, 0},
- [eDI_MP_post_cnt] = {"post_cnt:uint",
- eDI_MP_post_cnt, 0},
- [eDI_MP_di_log_flag] = {"di_log_flag:uint",
- eDI_MP_di_log_flag, 0},
- [eDI_MP_di_debug_flag] = {"di_debug_flag:uint",
- eDI_MP_di_debug_flag, 0},
- [eDI_MP_buf_state_log_threshold] = {"buf_state_log_threshold:unit:16",
- eDI_MP_buf_state_log_threshold, 16},
- [eDI_MP_di_vscale_skip_enable] = {"di_vscale_skip_enable:int",
-/*
- * bit[2]: enable bypass all when skip
- * bit[1:0]: enable bypass post when skip
- */
- eDI_MP_di_vscale_skip_enable, 0},
- [eDI_MP_di_vscale_skip_count] = {"di_vscale_skip_count:int",
- eDI_MP_di_vscale_skip_count, 0},
- [eDI_MP_di_vscale_skip_count_real] = {"di_vscale_skip_count_real:int",
- eDI_MP_di_vscale_skip_count_real, 0},
- [eDI_MP_det3d_en] = {"det3d_en:bool",
- eDI_MP_det3d_en, 0},
- [eDI_MP_post_hold_line] = {"post_hold_line:int:8",
- eDI_MP_post_hold_line, 8},
- [eDI_MP_post_urgent] = {"post_urgent:int:1",
- eDI_MP_post_urgent, 1},
- [eDI_MP_di_printk_flag] = {"di_printk_flag:uint",
- eDI_MP_di_printk_flag, 0},
- [eDI_MP_force_recovery] = {"force_recovery:uint:1",
- eDI_MP_force_recovery, 1},
-#if 0
- [eDI_MP_debug_blend_mode] = {"debug_blend_mode:int:-1",
- eDI_MP_debug_blend_mode, -1},
-#endif
- [eDI_MP_di_dbg_mask] = {"di_dbg_mask:uint:0x02",
- eDI_MP_di_dbg_mask, 2},
- [eDI_MP_nr_done_check_cnt] = {"nr_done_check_cnt:uint:5",
- eDI_MP_nr_done_check_cnt, 5},
- [eDI_MP_pre_hsc_down_en] = {"pre_hsc_down_en:bool:0",
- eDI_MP_pre_hsc_down_en, 0},
- [eDI_MP_pre_hsc_down_width] = {"pre_hsc_down_width:int:480",
- eDI_MP_pre_hsc_down_width, 480},
- [eDI_MP_show_nrwr] = {"show_nrwr:bool:0",
- eDI_MP_show_nrwr, 0},
-
- /******deinterlace_hw.c**********/
- [eDI_MP_pq_load_dbg] = {"pq_load_dbg:uint",
- eDI_MP_pq_load_dbg, 0},
- [eDI_MP_lmv_lock_win_en] = {"lmv_lock_win_en:bool",
- eDI_MP_lmv_lock_win_en, 0},
- [eDI_MP_lmv_dist] = {"lmv_dist:short:5",
- eDI_MP_lmv_dist, 5},
- [eDI_MP_pr_mcinfo_cnt] = {"pr_mcinfo_cnt:ushort",
- eDI_MP_pr_mcinfo_cnt, 0},
- [eDI_MP_offset_lmv] = {"offset_lmv:short:100",
- eDI_MP_offset_lmv, 100},
- [eDI_MP_post_ctrl] = {"post_ctrl:uint",
- eDI_MP_post_ctrl, 0},
- [eDI_MP_if2_disable] = {"if2_disable:bool",
- eDI_MP_if2_disable, 0},
- [eDI_MP_pre_flag] = {"pre_flag:ushort:2",
- eDI_MP_pre_flag, 2},
- [eDI_MP_pre_mif_gate] = {"pre_mif_gate:bool",
- eDI_MP_pre_mif_gate, 0},
- [eDI_MP_pre_urgent] = {"pre_urgent:ushort",
- eDI_MP_pre_urgent, 0},
- [eDI_MP_pre_hold_line] = {"pre_hold_line:ushort:10",
- eDI_MP_pre_hold_line, 10},
- [eDI_MP_pre_ctrl] = {"pre_ctrl:uint",
- eDI_MP_pre_ctrl, 0},
- [eDI_MP_line_num_post_frst] = {"line_num_post_frst:ushort:5",
- eDI_MP_line_num_post_frst, 5},
- [eDI_MP_line_num_pre_frst] = {"line_num_pre_frst:ushort:5",
- eDI_MP_line_num_pre_frst, 5},
- [eDI_MP_pd22_flg_calc_en] = {"pd22_flg_calc_en:bool:true",
- eDI_MP_pd22_flg_calc_en, 1},
- [eDI_MP_mcen_mode] = {"mcen_mode:ushort:1",
- eDI_MP_mcen_mode, 1},
- [eDI_MP_mcuv_en] = {"mcuv_en:ushort:1",
- eDI_MP_mcuv_en, 1},
- [eDI_MP_mcdebug_mode] = {"mcdebug_mode:ushort",
- eDI_MP_mcdebug_mode, 0},
- [eDI_MP_pldn_ctrl_rflsh] = {"pldn_ctrl_rflsh:uint:1",
- eDI_MP_pldn_ctrl_rflsh, 1},
- [eDI_MP_4k_test] = {"4_k_input:uint:1",
- eDI_MP_4k_test, 0},
-
- [eDI_MP_SUB_DI_E] = {"di end-------",
- eDI_MP_SUB_DI_E, 0},
- /**************************************/
- [eDI_MP_SUB_NR_B] = {"nr begin",
- eDI_MP_SUB_NR_B, 0},
- [EDI_MP_SUB_DELAY] = {"delay:bool:true",
- EDI_MP_SUB_DELAY, 0},
- [EDI_MP_SUB_DBG_MODE] = {"delay_mode:uint:0",
- EDI_MP_SUB_DBG_MODE, 0},
- [eDI_MP_cue_en] = {"cue_en:bool:true",
- eDI_MP_cue_en, 1},
- [eDI_MP_invert_cue_phase] = {"invert_cue_phase:bool",
- eDI_MP_invert_cue_phase, 0},
- [eDI_MP_cue_pr_cnt] = {"cue_pr_cnt:uint",
- eDI_MP_cue_pr_cnt, 0},
- [eDI_MP_cue_glb_mot_check_en] = {"cue_glb_mot_check_en:bool:true",
- eDI_MP_cue_glb_mot_check_en, 1},
- [eDI_MP_glb_fieldck_en] = {"glb_fieldck_en:bool:true",
- eDI_MP_glb_fieldck_en, 1},
- [eDI_MP_dnr_pr] = {"dnr_pr:bool",
- eDI_MP_dnr_pr, 0},
- [eDI_MP_dnr_dm_en] = {"dnr_dm_en:bool",
- eDI_MP_dnr_dm_en, 0},
- [eDI_MP_SUB_NR_E] = {"nr end-------",
- eDI_MP_SUB_NR_E, 0},
- /**************************************/
- [eDI_MP_SUB_PD_B] = {"pd begin",
- eDI_MP_SUB_PD_B, 0},
- [eDI_MP_flm22_ratio] = {"flm22_ratio:uint:200",
- eDI_MP_flm22_ratio, 200},
- [eDI_MP_pldn_cmb0] = {"pldn_cmb0:uint:1",
- eDI_MP_pldn_cmb0, 1},
- [eDI_MP_pldn_cmb1] = {"pldn_cmb1:uint",
- eDI_MP_pldn_cmb1, 0},
- [eDI_MP_flm22_sure_num] = {"flm22_sure_num:uint:100",
- eDI_MP_flm22_sure_num, 100},
- [eDI_MP_flm22_glbpxlnum_rat] = {"flm22_glbpxlnum_rat:uint:4",
- eDI_MP_flm22_glbpxlnum_rat, 4},
- [eDI_MP_flag_di_weave] = {"flag_di_weave:int:1",
- eDI_MP_flag_di_weave, 1},
- [eDI_MP_flm22_glbpxl_maxrow] = {"flm22_glbpxl_maxrow:uint:16",
- eDI_MP_flm22_glbpxl_maxrow, 16},
- [eDI_MP_flm22_glbpxl_minrow] = {"flm22_glbpxl_minrow:uint:3",
- eDI_MP_flm22_glbpxl_minrow, 3},
- [eDI_MP_cmb_3point_rnum] = {"cmb_3point_rnum:uint",
- eDI_MP_cmb_3point_rnum, 0},
- [eDI_MP_cmb_3point_rrat] = {"cmb_3point_rrat:unit:32",
- eDI_MP_cmb_3point_rrat, 32},
- /********************************/
- [eDI_MP_pr_pd] = {"pr_pd:uint",
- eDI_MP_pr_pd, 0},
- [eDI_MP_prt_flg] = {"prt_flg:bool",
- eDI_MP_prt_flg, 0},
- [eDI_MP_flmxx_maybe_num] = {"flmxx_maybe_num:uint:15",
- /* if flmxx level > flmxx_maybe_num */
- /* mabye flmxx: when 2-2 3-2 not detected */
- eDI_MP_flmxx_maybe_num, 15},
- [eDI_MP_flm32_mim_frms] = {"flm32_mim_frms:int:6",
- eDI_MP_flm32_mim_frms, 6},
- [eDI_MP_flm22_dif01a_flag] = {"flm22_dif01a_flag:int:1",
- eDI_MP_flm22_dif01a_flag, 1},
- [eDI_MP_flm22_mim_frms] = {"flm22_mim_frms:int:60",
- eDI_MP_flm22_mim_frms, 60},
- [eDI_MP_flm22_mim_smfrms] = {"flm22_mim_smfrms:int:40",
- eDI_MP_flm22_mim_smfrms, 40},
- [eDI_MP_flm32_f2fdif_min0] = {"flm32_f2fdif_min0:int:11",
- eDI_MP_flm32_f2fdif_min0, 11},
- [eDI_MP_flm32_f2fdif_min1] = {"flm32_f2fdif_min1:int:11",
- eDI_MP_flm32_f2fdif_min1, 11},
- [eDI_MP_flm32_chk1_rtn] = {"flm32_chk1_rtn:int:25",
- eDI_MP_flm32_chk1_rtn, 25},
- [eDI_MP_flm32_ck13_rtn] = {"flm32_ck13_rtn:int:8",
- eDI_MP_flm32_ck13_rtn, 8},
- [eDI_MP_flm32_chk2_rtn] = {"flm32_chk2_rtn:int:16",
- eDI_MP_flm32_chk2_rtn, 16},
- [eDI_MP_flm32_chk3_rtn] = {"flm32_chk3_rtn:int:16",
- eDI_MP_flm32_chk3_rtn, 16},
- [eDI_MP_flm32_dif02_ratio] = {"flm32_dif02_ratio:int:8",
- eDI_MP_flm32_dif02_ratio, 8},
- [eDI_MP_flm22_chk20_sml] = {"flm22_chk20_sml:int:6",
- eDI_MP_flm22_chk20_sml, 6},
- [eDI_MP_flm22_chk21_sml] = {"flm22_chk21_sml:int:6",
- eDI_MP_flm22_chk21_sml, 6},
- [eDI_MP_flm22_chk21_sm2] = {"flm22_chk21_sm2:int:10",
- eDI_MP_flm22_chk21_sm2, 10},
- [eDI_MP_flm22_lavg_sft] = {"flm22_lavg_sft:int:4",
- eDI_MP_flm22_lavg_sft, 4},
- [eDI_MP_flm22_lavg_lg] = {"flm22_lavg_lg:int:24",
- eDI_MP_flm22_lavg_lg, 24},
- [eDI_MP_flm22_stl_sft] = {"flm22_stl_sft:int:7",
- eDI_MP_flm22_stl_sft, 7},
- [eDI_MP_flm22_chk5_avg] = {"flm22_chk5_avg:int:50",
- eDI_MP_flm22_chk5_avg, 50},
- [eDI_MP_flm22_chk6_max] = {"flm22_chk6_max:int:20",
- eDI_MP_flm22_chk6_max, 20},
- [eDI_MP_flm22_anti_chk1] = {"flm22_anti_chk1:int:61",
- eDI_MP_flm22_anti_chk1, 61},
- [eDI_MP_flm22_anti_chk3] = {"flm22_anti_chk3:int:140",
- eDI_MP_flm22_anti_chk3, 140},
- [eDI_MP_flm22_anti_chk4] = {"flm22_anti_chk4:int:128",
- eDI_MP_flm22_anti_chk4, 128},
- [eDI_MP_flm22_anti_ck140] = {"flm22_anti_ck140:int:32",
- eDI_MP_flm22_anti_ck140, 32},
- [eDI_MP_flm22_anti_ck141] = {"flm22_anti_ck141:int:80",
- eDI_MP_flm22_anti_ck141, 80},
- [eDI_MP_flm22_frmdif_max] = {"flm22_frmdif_max:int:50",
- eDI_MP_flm22_frmdif_max, 50},
- [eDI_MP_flm22_flddif_max] = {"flm22_flddif_max:int:100",
- eDI_MP_flm22_flddif_max, 100},
- [eDI_MP_flm22_minus_cntmax] = {"flm22_minus_cntmax:int:2",
- eDI_MP_flm22_minus_cntmax, 2},
- [eDI_MP_flagdif01chk] = {"flagdif01chk:int:1",
- eDI_MP_flagdif01chk, 1},
- [eDI_MP_dif01_ratio] = {"dif01_ratio:int:10",
- eDI_MP_dif01_ratio, 10},
- /*************vof_soft_top**************/
- [eDI_MP_cmb32_blw_wnd] = {"cmb32_blw_wnd:int:180",
- eDI_MP_cmb32_blw_wnd, 180},
- [eDI_MP_cmb32_wnd_ext] = {"cmb32_wnd_ext:int:11",
- eDI_MP_cmb32_wnd_ext, 11},
- [eDI_MP_cmb32_wnd_tol] = {"cmb32_wnd_tol:int:4",
- eDI_MP_cmb32_wnd_tol, 4},
- [eDI_MP_cmb32_frm_nocmb] = {"cmb32_frm_nocmb:int:40",
- eDI_MP_cmb32_frm_nocmb, 40},
- [eDI_MP_cmb32_min02_sft] = {"cmb32_min02_sft:int:7",
- eDI_MP_cmb32_min02_sft, 7},
- [eDI_MP_cmb32_cmb_tol] = {"cmb32_cmb_tol:int:10",
- eDI_MP_cmb32_cmb_tol, 10},
- [eDI_MP_cmb32_avg_dff] = {"cmb32_avg_dff:int:48",
- eDI_MP_cmb32_avg_dff, 48},
- [eDI_MP_cmb32_smfrm_num] = {"cmb32_smfrm_num:int:4",
- eDI_MP_cmb32_smfrm_num, 4},
- [eDI_MP_cmb32_nocmb_num] = {"cmb32_nocmb_num:int:20",
- eDI_MP_cmb32_nocmb_num, 20},
- [eDI_MP_cmb22_gcmb_rnum] = {"cmb22_gcmb_rnum:int:8",
- eDI_MP_cmb22_gcmb_rnum, 8},
- [eDI_MP_flmxx_cal_lcmb] = {"flmxx_cal_lcmb:int:1",
- eDI_MP_flmxx_cal_lcmb, 1},
- [eDI_MP_flm2224_stl_sft] = {"flm2224_stl_sft:int:7",
- eDI_MP_flm2224_stl_sft, 7},
- [eDI_MP_SUB_PD_E] = {"pd end------",
- eDI_MP_SUB_PD_E, 0},
- /**************************************/
- [eDI_MP_SUB_MTN_B] = {"mtn begin",
- eDI_MP_SUB_MTN_B, 0},
- [eDI_MP_force_lev] = {"force_lev:int:0xff",
- eDI_MP_force_lev, 0xff},
- [eDI_MP_dejaggy_flag] = {"dejaggy_flag:int:-1",
- eDI_MP_dejaggy_flag, -1},
- [eDI_MP_dejaggy_enable] = {"dejaggy_enable:int:1",
- eDI_MP_dejaggy_enable, 1},
- [eDI_MP_cmb_adpset_cnt] = {"cmb_adpset_cnt:int",
- eDI_MP_cmb_adpset_cnt, 0},
- [eDI_MP_cmb_num_rat_ctl4] = {"cmb_num_rat_ctl4:int:64:0~255",
- eDI_MP_cmb_num_rat_ctl4, 64},
- [eDI_MP_cmb_rat_ctl4_minthd] = {"cmb_rat_ctl4_minthd:int:64",
- eDI_MP_cmb_rat_ctl4_minthd, 64},
- [eDI_MP_small_local_mtn] = {"small_local_mtn:uint:70",
- eDI_MP_small_local_mtn, 70},
- [eDI_MP_di_debug_readreg] = {"di_debug_readreg:int",
- eDI_MP_di_debug_readreg, 0},
- [eDI_MP_SUB_MTN_E] = {"mtn end----",
- eDI_MP_SUB_MTN_E, 0},
- /**************************************/
- [eDI_MP_SUB_3D_B] = {"3d begin",
- eDI_MP_SUB_3D_B, 0},
- [eDI_MP_chessbd_vrate] = {"chessbd_vrate:int:29",
- eDI_MP_chessbd_vrate, 29},
- [eDI_MP_det3d_debug] = {"det3d_debug:bool:0",
- eDI_MP_det3d_debug, 0},
- [eDI_MP_SUB_3D_E] = {"3d begin",
- eDI_MP_SUB_3D_E, 0},
-
- /**************************************/
- [eDI_MP_UI_T_END] = {"module para top end ", eDI_MP_UI_T_END, 0}
-};
-
-bool div3_mp_uit_check(unsigned int idx)
-{
- unsigned int tsize;
-
- tsize = ARRAY_SIZE(div3_mp_ui_top);
- if (idx >= tsize) {
- PR_ERR("div3_mp_uit_check:err:overflow:%d->%d\n",
- idx, tsize);
- return false;
- }
- if (idx != div3_mp_ui_top[idx].id) {
- PR_ERR("%s:err:not map:%d->%d\n",
- __func__, idx, div3_mp_ui_top[idx].id);
- return false;
- }
- dbg_init("\t%-15s=%d\n", div3_mp_ui_top[idx].name,
- div3_mp_ui_top[idx].default_val);
- return true;
-}
-
-char *div3_mp_uit_get_name(enum eDI_MP_UI_T idx)
-{
- return div3_mp_ui_top[idx].name;
-}
-
-void div3_mp_uit_init_val(void)
-{
- int i;
-
- for (i = eDI_MP_UI_T_BEGIN; i < eDI_MP_UI_T_END; i++) {
- if (!div3_mp_uit_check(i))
- continue;
- dimp_set(i, div3_mp_ui_top[i].default_val);
- }
-}
-#if 0
-int di_mp_uit_get(enum eDI_MP_UI_T idx)
-{
- return get_datal()->mp_uit[idx];
-}
-
-void di_mp_uit_set(enum eDI_MP_UI_T idx, int val)
-{
- get_datal()->mp_uit[idx] = val;
-}
-#endif
-
-/**************************************
- *
- * module para x
- * unsigned int
- **************************************/
-
-const struct di_mp_uix_s div3_mpx[] = {
- /*same order with enum eDI_MP_UI*/
-
- /* module para for channel x*/
- [eDI_MP_UIX_BEGIN] = {"module para x begin ", eDI_MP_UIX_BEGIN, 0},
- /*debug: run_flag*/
- [eDI_MP_UIX_RUN_FLG] = {"run_flag(0:run;1:pause;2:step)",
- eDI_MP_UIX_RUN_FLG, DI_RUN_FLAG_RUN},
- [eDI_MP_UIX_END] = {"module para x end ", eDI_MP_UIX_END, 0}
-
-};
-
-bool div3_mp_uix_check(unsigned int idx)
-{
- unsigned int tsize;
-
- tsize = ARRAY_SIZE(div3_mpx);
- if (idx >= tsize) {
- PR_ERR("%s:err:overflow:%d->%d\n",
- __func__, idx, tsize);
- return false;
- }
- if (idx != div3_mpx[idx].id) {
- PR_ERR("%s:err:not map:%d->%d\n",
- __func__, idx, div3_mpx[idx].id);
- return false;
- }
- dbg_init("\t%-15s=%d\n", div3_mpx[idx].name, div3_mpx[idx].default_val);
-
- return true;
-}
-
-char *div3_mp_uix_get_name(enum eDI_MP_UIX_T idx)
-{
- return div3_mpx[idx].name;
-}
-
-void div3_mp_uix_init_val(void)
-{
- int i, ch;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- dbg_init("%s:ch[%d]\n", __func__, ch);
- for (i = eDI_MP_UIX_BEGIN; i < eDI_MP_UIX_END; i++) {
- if (ch == 0) {
- if (!div3_mp_uix_check(i))
- continue;
- }
- div3_mp_uix_set(ch, i, div3_mpx[i].default_val);
- }
- }
-}
-
-unsigned int div3_mp_uix_get(unsigned int ch, enum eDI_MP_UIX_T idx)
-{
- return get_datal()->ch_data[ch].mp_uix[idx];
-}
-
-void div3_mp_uix_set(unsigned int ch, enum eDI_MP_UIX_T idx, unsigned int val)
-{
- get_datal()->ch_data[ch].mp_uix[idx] = val;
-}
-
-bool div3_is_pause(unsigned int ch)
-{
- unsigned int run_flag;
-
- run_flag = div3_mp_uix_get(ch, eDI_MP_UIX_RUN_FLG);
-
- if (run_flag == DI_RUN_FLAG_PAUSE ||
- run_flag == DI_RUN_FLAG_STEP_DONE)
- return true;
-
- return false;
-}
-
-void div3_pause_step_done(unsigned int ch)
-{
- unsigned int run_flag;
-
- run_flag = div3_mp_uix_get(ch, eDI_MP_UIX_RUN_FLG);
- if (run_flag == DI_RUN_FLAG_STEP) {
- div3_mp_uix_set(ch, eDI_MP_UIX_RUN_FLG,
- DI_RUN_FLAG_STEP_DONE);
- }
-}
-
-void div3_pause(unsigned int ch, bool on)
-{
- PR_INF("%s:%d\n", __func__, on);
- if (on)
- div3_mp_uix_set(ch, eDI_MP_UIX_RUN_FLG,
- DI_RUN_FLAG_PAUSE);
- else
- div3_mp_uix_set(ch, eDI_MP_UIX_RUN_FLG,
- DI_RUN_FLAG_RUN);
-}
-
-/**************************************
- *
- * summmary variable
- *
- **************************************/
-const struct di_sum_s div3_sum_tab[] = {
- /*video_peek_cnt*/
- [eDI_SUM_O_PEEK_CNT] = {"o_peek_cnt", eDI_SUM_O_PEEK_CNT, 0},
- /*di_reg_unreg_cnt*/
- [eDI_SUM_REG_UNREG_CNT] = {
- "di_reg_unreg_cnt", eDI_SUM_REG_UNREG_CNT, 100},
-
- [eDI_SUM_NUB] = {"end", eDI_SUM_NUB, 0}
-};
-
-unsigned int div3_sum_get_tab_size(void)
-{
- return ARRAY_SIZE(div3_sum_tab);
-}
-
-bool div3_sum_check(unsigned int ch, enum eDI_SUM id)
-{
- unsigned int tsize;
-
- tsize = ARRAY_SIZE(div3_sum_tab);
-
- if (id >= tsize) {
- PR_ERR("%s:err:overflow:tsize[%d],id[%d]\n",
- __func__, tsize, id);
- return false;
- }
- if (div3_sum_tab[id].index != id) {
- PR_ERR("%s:err:table:id[%d],tab_id[%d]\n",
- __func__, id, div3_sum_tab[id].index);
- return false;
- }
- return true;
-}
-
-void div3_sum_reg_init(unsigned int ch)
-{
- unsigned int tsize;
- int i;
-
- tsize = ARRAY_SIZE(div3_sum_tab);
-
- dbg_init("%s:ch[%d]\n", __func__, ch);
- for (i = 0; i < tsize; i++) {
- if (!div3_sum_check(ch, i))
- continue;
- dbg_init("\t:%d:name:%s,%d\n", i, div3_sum_tab[i].name,
- div3_sum_tab[i].default_val);
- di_sum_set_l(ch, i, div3_sum_tab[i].default_val);
- }
-}
-
-void div3_sum_get_info(unsigned int ch, enum eDI_SUM id, char **name,
- unsigned int *pval)
-{
- *name = div3_sum_tab[id].name;
- *pval = div3_sum_get(ch, id);
-}
-
-void div3_sum_set(unsigned int ch, enum eDI_SUM id, unsigned int val)
-{
- if (!div3_sum_check(ch, id))
- return;
-
- di_sum_set_l(ch, id, val);
-}
-
-unsigned int div3_sum_inc(unsigned int ch, enum eDI_SUM id)
-{
- if (!div3_sum_check(ch, id))
- return 0;
- return di_sum_inc_l(ch, id);
-}
-
-unsigned int div3_sum_get(unsigned int ch, enum eDI_SUM id)
-{
- if (!div3_sum_check(ch, id))
- return 0;
- return di_sum_get_l(ch, id);
-}
-
-/**********************************/
-void dimv3_sumx_clear(unsigned int ch)
-{
- struct dim_sum_s *psumx = get_sumx(ch);
-
- memset(psumx, 0, sizeof(*psumx));
-}
-
-void dimv3_sumx_set(unsigned int ch)
-{
- struct dim_sum_s *psumx = get_sumx(ch);
- struct di_mm_s *mm = dim_mm_get(ch);
- unsigned int pst_kee;
-
- psumx->b_pre_free = listv3_count(ch, QUEUE_LOCAL_FREE);
- psumx->b_pre_ready = div3_que_list_count(ch, QUE_PRE_READY);
- psumx->b_pst_free = div3_que_list_count(ch, QUE_POST_FREE);
- psumx->b_pst_ready = div3_que_list_count(ch, QUE_POST_READY);
- psumx->b_recyc = listv3_count(ch, QUEUE_RECYCLE);
- psumx->b_display = listv3_count(ch, QUEUE_DISPLAY);
-
- pst_kee = div3_que_list_count(ch, QUE_POST_KEEP);
-
- if (pst_kee &&
- (pst_kee + psumx->b_display) > (mm->cfg.num_post - 3))
- taskv3_send_cmd(LCMD1(ECMD_RL_KEEP_ALL, ch));
-}
-
-/****************************/
-/*call by event*/
-/****************************/
-void dipv3_even_reg_init_val(unsigned int ch)
-{
-}
-
-void dipv3_even_unreg_val(unsigned int ch)
-{
-}
-
-/****************************/
-static void dip_cma_init_val(void)
-{
- unsigned int ch;
- struct di_mng_s *pbm = get_bufmng();
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- /* CMA state */
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_IDL);
-
- /* CMA reg/unreg cmd */
- pbm->cma_reg_cmd[ch] = 0;
- }
-}
-
-void dipv3_cma_close(void)
-{
- unsigned int ch;
- struct di_mng_s *pbm = get_bufmng();
-
- if (dipv3_cma_st_is_idl_all())
- return;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- if (!dipv3_cma_st_is_idle(ch)) {
- dimv3_cma_top_release(ch);
- PR_INF("%s:force release ch[%d]", __func__, ch);
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_IDL);
-
- pbm->cma_reg_cmd[ch] = 0;
- }
- }
-}
-
-static void dip_wq_cma_handler(struct work_struct *work)
-{
- struct di_mng_s *pbm = get_bufmng();
- enum eDI_CMA_ST cma_st;
- bool do_flg;
- struct dim_wq_s *wq = container_of(work, struct dim_wq_s, wq_work);
-
- unsigned int ch = wq->ch;
-
- do_flg = false;
- cma_st = dipv3_cma_get_st(ch);
- dbg_wq("%s:ch[%d],cmd[%d],st[%d]\n",
- __func__, ch, pbm->cma_reg_cmd[ch], cma_st);
- switch (cma_st) {
- case EDI_CMA_ST_IDL:
- if (pbm->cma_reg_cmd[ch]) {
- do_flg = true;
- /*set:alloc:*/
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_ALLOC);
- if (dimv3_cma_top_alloc(ch)) {
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_READY);
- }
- }
- break;
- case EDI_CMA_ST_READY:
-
- if (!pbm->cma_reg_cmd[ch]) {
- do_flg = true;
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_RELEASE);
- dimv3_cma_top_release(ch);
- if (div3_que_is_empty(ch, QUE_POST_KEEP))
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_IDL);
- else
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_PART);
- }
- break;
- case EDI_CMA_ST_PART:
- if (pbm->cma_reg_cmd[ch]) {
- do_flg = true;
- /*set:alloc:*/
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_ALLOC);
- if (dimv3_cma_top_alloc(ch)) {
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_READY);
- }
- } else {
- do_flg = true;
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_RELEASE);
- dimv3_cma_top_release(ch);
- if (div3_que_is_empty(ch, QUE_POST_KEEP))
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_IDL);
- else
- atomic_set(&pbm->cma_mem_state[ch],
- EDI_CMA_ST_PART);
-
- }
-
- break;
- case EDI_CMA_ST_ALLOC: /*do*/
- case EDI_CMA_ST_RELEASE:/*do*/
- default:
- break;
- }
- if (!do_flg)
- PR_INF("\tch[%d],do nothing[%d]\n", ch, cma_st);
- else
- taskv3_send_ready();
-
- dbg_wq("%s:end\n", __func__);
-}
-
-static void dip_wq_prob(void)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- pbm->wq.wq_cma = create_singlethread_workqueue("deinterlace");
- INIT_WORK(&pbm->wq.wq_work, dip_wq_cma_handler);
-}
-
-static void dip_wq_ext(void)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- cancel_work_sync(&pbm->wq.wq_work);
- destroy_workqueue(pbm->wq.wq_cma);
- pr_info("%s:finish\n", __func__);
-}
-
-void dipv3_wq_cma_run(unsigned char ch, bool reg_cmd)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- dbg_wq("%s:ch[%d] [%d]\n", __func__, ch, reg_cmd);
- if (reg_cmd)
- pbm->cma_reg_cmd[ch] = 1;
- else
- pbm->cma_reg_cmd[ch] = 0;
-
- pbm->wq.ch = ch;
- queue_work(pbm->wq.wq_cma, &pbm->wq.wq_work);
-}
-
-bool dipv3_cma_st_is_ready(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
- bool ret = false;
-
- if (atomic_read(&pbm->cma_mem_state[ch]) == EDI_CMA_ST_READY)
- ret = true;
-
- return ret;
-}
-
-bool dipv3_cma_st_is_idle(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
- bool ret = false;
-
- if (atomic_read(&pbm->cma_mem_state[ch]) == EDI_CMA_ST_IDL)
- ret = true;
-
- return ret;
-}
-
-bool dipv3_cma_st_is_idl_all(void)
-{
- unsigned int ch;
- struct di_mng_s *pbm = get_bufmng();
- bool ret = true;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- if (atomic_read(&pbm->cma_mem_state[ch]) != EDI_CMA_ST_IDL) {
- ret = true;
- break;
- }
- }
- return ret;
-}
-
-enum eDI_CMA_ST dipv3_cma_get_st(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- return atomic_read(&pbm->cma_mem_state[ch]);
-}
-
-const char * const div3_cma_state_name[] = {
- "IDLE",
- "do_alloc",
- "READY",
- "do_release",
- "PART"
-};
-
-const char *div3_cma_dbg_get_st_name(unsigned int ch)
-{
- enum eDI_CMA_ST st = dipv3_cma_get_st(ch);
- const char *p = "overflow";
-
- if (st < ARRAY_SIZE(div3_cma_state_name))
- p = div3_cma_state_name[st];
- return p;
-}
-
-void dipv3_cma_st_set_ready_all(void)
-{
- unsigned int ch;
- struct di_mng_s *pbm = get_bufmng();
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++)
- atomic_set(&pbm->cma_mem_state[ch], EDI_CMA_ST_READY);
-}
-
-/****************************/
-/*channel STATE*/
-/****************************/
-void dipv3_chst_set(unsigned int ch, enum EDI_TOP_STATE chst)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- atomic_set(&pbm->ch_state[ch], chst);
-}
-
-enum EDI_TOP_STATE dipv3_chst_get(unsigned int ch)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- return atomic_read(&pbm->ch_state[ch]);
-}
-
-void dipv3_chst_init(void)
-{
- unsigned int ch;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++)
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
-}
-
-int dipv3_event_reg_chst(unsigned int ch)
-{
- enum EDI_TOP_STATE chst;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- bool err_flg = false;
- bool ret = 0;
- struct di_ch_s *pch;
-
- dbg_dbg("%s:ch[%d]\n", __func__, ch);
-
- if (get_reg_flag(ch)) {
- PR_ERR("no muti instance.\n");
- return -1;
- }
- pch = get_chdata(ch);
- chst = dipv3_chst_get(ch);
-#if 0 /*move*/
- if (chst > eDI_TOP_STATE_NOPROB)
- set_flag_trig_unreg(ch, false);
-#endif
- switch (chst) {
- case EDI_TOP_STATE_IDLE:
-
- queuev3_init2(ch);
- div3_que_init(ch);
- /*di_vframe_reg(ch);*/
- #if 1
- /*need call below two function before dvfm_fill_in*/
- dimv3_reg_cfg_sys(pch);
- dipv3_init_value_reg(ch);
- #endif
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP1);
- dimv3_htr_start(ch);
- taskv3_send_cmd(LCMD1(eCMD_REG, ch));
- dbg_dbg("reg ok\n");
- break;
- case eDI_TOP_STATE_REG_STEP1:
- case eDI_TOP_STATE_REG_STEP1_P1:
- case eDI_TOP_STATE_REG_STEP2:
- case EDI_TOP_STATE_READY:
- case eDI_TOP_STATE_BYPASS:
- PR_WARN("have reg\n");
- ret = false;
- break;
- case eDI_TOP_STATE_UNREG_STEP1:
- case eDI_TOP_STATE_UNREG_STEP2:
- /*wait*/
- ppre->reg_req_flag_cnt = 0;
- while (dipv3_chst_get(ch) != EDI_TOP_STATE_IDLE) {
- usleep_range(10000, 10001);
- if (ppre->reg_req_flag_cnt++ >
- dimv3_get_reg_unreg_cnt()) {
- dimv3_reg_timeout_inc();
- PR_ERR("%s,ch[%d] reg timeout!!!\n",
- __func__, ch);
- err_flg = true;
- ret = false;
- break;
- }
- }
- if (!err_flg) {
- /*same as IDLE*/
- queuev3_init2(ch);
- div3_que_init(ch);
- /*di_vframe_reg(ch);*/
- #if 1
- /*need call below two function before dvfm_fill_in*/
- dimv3_reg_cfg_sys(pch);
- dipv3_init_value_reg(ch);
- #endif
-
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP1);
- taskv3_send_cmd(LCMD1(eCMD_REG, ch));
- dbg_dbg("reg retry ok\n");
- }
- break;
- case eDI_TOP_STATE_NOPROB:
- default:
- ret = false;
- PR_ERR("err: not prob[%d]\n", chst);
-
- break;
- }
- dbg_ev("ch[%d]:reg end\n", ch);
-
- return ret;
-}
-
-bool dipv3_event_unreg_chst(unsigned int ch)
-{
- enum EDI_TOP_STATE chst, chst2;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- bool ret = false;
- bool err_flg = false;
- unsigned int cnt;
-
- chst = dipv3_chst_get(ch);
- dbg_reg("%s:ch[%d]:%s\n", __func__, ch, dipv3_chst_get_name(chst));
- #if 0
- if (chst > eDI_TOP_STATE_IDLE)
- set_reg_flag(ch, false);/*set_flag_trig_unreg(ch, true);*/
- #endif
- if (chst > eDI_TOP_STATE_NOPROB)
- set_flag_trig_unreg(ch, true);
-
- switch (chst) {
- case EDI_TOP_STATE_READY:
-
- //di_vframe_unreg(ch);
- dimv3_htr_stop(ch);
- /*trig unreg*/
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP1);
- taskv3_send_cmd(LCMD1(eCMD_UNREG, ch));
- /*debug only di_dbg = di_dbg|DBG_M_TSK;*/
-
- /*wait*/
- ppre->unreg_req_flag_cnt = 0;
- chst2 = dipv3_chst_get(ch);
-
- while (chst2 != EDI_TOP_STATE_IDLE) {
- taskv3_send_ready();
- usleep_range(10000, 10001);
- /*msleep(5);*/
- if (ppre->unreg_req_flag_cnt++
- > dimv3_get_reg_unreg_cnt()) {
- dimv3_reg_timeout_inc();
- PR_ERR("%s:ch[%d] unreg timeout!!!\n",
- __func__, ch);
- /*dim_unreg_process();*/
- err_flg = true;
- break;
- }
- #if 0 /*debug only*/
- dbg_reg("\tch[%d]:s[%s],ecnt[%d]\n",
- ch,
- dipv3_chst_get_name(chst2),
- ppre->unreg_req_flag_cnt);
- #endif
- chst2 = dipv3_chst_get(ch);
- }
-
- /*debug only di_dbg = di_dbg & (~DBG_M_TSK);*/
- dbg_reg("%s:ch[%d] ready end\n", __func__, ch);
- #if 0
- if (!err_flg)
- set_reg_flag(ch, false);
- #endif
- break;
- case eDI_TOP_STATE_BYPASS:
- /*from bypass complet to unreg*/
- //di_vframe_unreg(ch);
- div3_unreg_variable(ch);
-
- set_reg_flag(ch, false);
- dimv3_htr_stop(ch);
- if (!get_reg_flag_all()) {
- div3_unreg_setting();
- dprev3_init();
- dpostv3_init();
- }
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
- ret = true;
-
- break;
- case EDI_TOP_STATE_IDLE:
- PR_WARN("have unreg\n");
- break;
- case eDI_TOP_STATE_REG_STEP1:
- dbg_dbg("%s:in reg step1\n", __func__);
- //di_vframe_unreg(ch);
- set_reg_flag(ch, false);
-
- dimv3_htr_stop(ch);
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
-
- ret = true;
- break;
- case eDI_TOP_STATE_REG_STEP1_P1:
- /*wait:*/
- cnt = 0;
- chst2 = dipv3_chst_get(ch);
- while (chst2 == eDI_TOP_STATE_REG_STEP1_P1 || cnt < 5) {
- taskv3_send_ready();
- usleep_range(3000, 3001);
- cnt++;
- }
- if (cnt >= 5)
- PR_ERR("%s:ch[%d] in p1 timeout\n", __func__, ch);
-
- set_reg_flag(ch, false);
-
- //di_vframe_unreg(ch);
- dimv3_htr_stop(ch);
- /*trig unreg*/
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP1);
- taskv3_send_cmd(LCMD1(eCMD_UNREG, ch));
- /*debug only di_dbg = di_dbg|DBG_M_TSK;*/
-
- /*wait*/
- ppre->unreg_req_flag_cnt = 0;
- chst2 = dipv3_chst_get(ch);
-
- while (chst2 != EDI_TOP_STATE_IDLE) {
- taskv3_send_ready();
- usleep_range(10000, 10001);
- /*msleep(5);*/
- if (ppre->unreg_req_flag_cnt++
- > dimv3_get_reg_unreg_cnt()) {
- dimv3_reg_timeout_inc();
- PR_ERR("%s:ch[%d] unreg timeout!!!\n",
- __func__,
- ch);
- /*di_unreg_process();*/
- err_flg = true;
- break;
- }
-
- chst2 = dipv3_chst_get(ch);
- }
-
- /*debug only di_dbg = di_dbg & (~DBG_M_TSK);*/
- dbg_reg("%s:ch[%d] ready end\n", __func__, ch);
- ret = true;
-
- break;
- case eDI_TOP_STATE_REG_STEP2:
- //di_vframe_unreg(ch);
- div3_unreg_variable(ch);
- set_reg_flag(ch, false);
- dimv3_htr_stop(ch);
- if (!get_reg_flag_all()) {
- div3_unreg_setting();
- dprev3_init();
- dpostv3_init();
- }
-
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
-
- ret = true;
- break;
- case eDI_TOP_STATE_UNREG_STEP1:
- case eDI_TOP_STATE_UNREG_STEP2:
- taskv3_send_cmd(LCMD1(eCMD_UNREG, ch));
-
- /*wait*/
- ppre->unreg_req_flag_cnt = 0;
- while (dipv3_chst_get(ch) != EDI_TOP_STATE_IDLE) {
- usleep_range(10000, 10001);
- if (ppre->unreg_req_flag_cnt++ >
- dimv3_get_reg_unreg_cnt()) {
- dimv3_reg_timeout_inc();
- PR_ERR("%s:unreg_reg_flag timeout!!!\n",
- __func__);
- //di_vframe_unreg(ch);
- dimv3_htr_stop(ch);
- err_flg = true;
- break;
- }
- }
- break;
- case eDI_TOP_STATE_NOPROB:
- default:
- PR_ERR("err: not prob[%d]\n", chst);
- break;
- }
- if (err_flg)
- ret = false;
-
- dbg_ev("ch[%d] ret[%d]unreg end\n", ch, ret);
-
- return ret;
-}
-
-/*process for reg and unreg cmd*/
-void dipv3_chst_process_reg(unsigned int ch)
-{
- enum EDI_TOP_STATE chst;
- //struct vframe_s *vframe;
- void *vframe;
-// struct di_pre_stru_s *ppre = get_pre_stru(ch);
- bool reflesh = true;
- struct di_hpre_s *pre = get_hw_pre();
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm;
-
- while (reflesh) {
- reflesh = false;
-
- chst = dipv3_chst_get(ch);
-
- /*dbg_reg("%s:ch[%d]%s\n", __func__, ch, dipv3_chst_get_name(chst));*/
-
- switch (chst) {
- case eDI_TOP_STATE_NOPROB:
- case EDI_TOP_STATE_IDLE:
- break;
- case eDI_TOP_STATE_REG_STEP1:/*wait peek*/
- //dim_htr_start();
- pch = get_chdata(ch);
- vframe = pch->interf.opsi.peek(pch);//pw_vf_peek(ch);
-
- if (vframe) {
- dimv3_tr_ops.pre_get(0);
- set_flag_trig_unreg(ch, false);
- #if 0
- di_reg_variable(ch);
-
- /*?how about bypass ?*/
- if (ppre->bypass_flag) {
- /* complete bypass */
- setv3_bypass2_complete(ch, true);
- if (!get_reg_flag_all()) {
- /*first channel reg*/
- dprev3_init();
- dpostv3_init();
- div3_reg_setting(ch, vframe);
- }
- dipv3_chst_set(ch, eDI_TOP_STATE_BYPASS);
- set_reg_flag(ch, true);
- } else {
- setv3_bypass2_complete(ch, false);
- if (!get_reg_flag_all()) {
- /*first channel reg*/
- dprev3_init();
- dpostv3_init();
- div3_reg_setting(ch, vframe);
- }
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP2);
- }
- #else
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP1_P1);
- #endif
-
- reflesh = true;
- }
- break;
- case eDI_TOP_STATE_REG_STEP1_P1:
- pch = get_chdata(ch);
- vframe = pch->interf.opsi.peek(pch);//pw_vf_peek(ch);
- if (!vframe) {
- PR_ERR("%s:p1 vfm nop\n", __func__);
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP1);
-
- break;
- }
- #if 0 /*move to reg_step1*/
- /*need call below two function before dvfm_fill_in*/
- dimv3_reg_cfg_sys(pch);
- dipv3_init_value_reg(ch);
- #endif
- pdvfm = pch->interf.op_dvfm_fill(pch);//dvfm_fill_in(pch);
- if (!pdvfm)
- break;
-
- //di_reg_variable(ch, pdvfm);
- /*pre ops*/
- set_h_ppre(ch);
- if (pre && pre->ops.reg_var)
- pre->ops.reg_var(pre);
-
- /*di_reg_process_irq(ch);*/ /*check if bypass*/
-
- /*?how about bypass ?*/
- //if (ppre->bypass_flag) {
- if (pdvfm->wmode.need_bypass) {
- /* complete bypass */
- setv3_bypass2_complete(ch, true);
- di_reg_variable_needbypass(ch, pdvfm);
- if (!get_reg_flag_all()) {
- /*first channel reg*/
- dprev3_init();
- dpostv3_init();
- pdvfm->wmode.src_h = 480;/*only use for reg*/
- pdvfm->wmode.src_w = 720;
- div3_reg_setting(ch, vframe, &pdvfm->wmode);
- /*pre ops*/
- if (pre && pre->ops.reg_hw)
- pre->ops.reg_hw(pre);
- }
- dipv3_chst_set(ch, eDI_TOP_STATE_BYPASS);
- set_reg_flag(ch, true);
- dimv3_htr_con_update((DIM_HTM_REG_BIT << ch), false);
- dimv3_htr_con_update(DIM_HTM_W_INPUT, true);
- } else {
- setv3_bypass2_complete(ch, false);
- di_reg_variable_normal(ch, pdvfm);
- if (!get_reg_flag_all()) {
- /*first channel reg*/
- dprev3_init();
- dpostv3_init();
- div3_reg_setting(ch, vframe, &pdvfm->wmode);
- /*pre ops*/
- if (pre && pre->ops.reg_hw)
- pre->ops.reg_hw(pre);
- }
- /*this will cause first local buf not alloc*/
- /*dimv3_bypass_first_frame(ch);*/
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP2);
- dimv3_htr_con_update((DIM_HTM_REG_BIT << ch), false);
- dimv3_htr_con_update(DIM_HTM_W_INPUT, true);
- /*set_reg_flag(ch, true);*/
- }
-
- reflesh = true;
- break;
- case eDI_TOP_STATE_REG_STEP2:/*now no change to do*/
- if (dipv3_cma_get_st(ch) == EDI_CMA_ST_READY) {
- if (div3_cfg_top_get(EDI_CFG_first_bypass)) {
- if (get_sum_g(ch) == 0)
- dimv3_bypass_first_frame(ch);
- else
- PR_INF("ch[%d],g[%d]\n",
- ch, get_sum_g(ch));
- }
- dipv3_chst_set(ch, EDI_TOP_STATE_READY);
- set_reg_flag(ch, true);
- /*move to step1 dimv3_bypass_first_frame(ch);*/
- }
- break;
- case EDI_TOP_STATE_READY:
-
- break;
- case eDI_TOP_STATE_BYPASS:
- /*do nothing;*/
- break;
- case eDI_TOP_STATE_UNREG_STEP1:
-
-#if 0
- if (!get_reg_flag(ch)) { /*need wait pre/post done*/
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP2);
- reflesh = true;
- }
-#else
- /*debug only dbg_reg("%s:UNREG_STEP1\n", __func__);*/
-
- if (dprev3_can_exit(ch) && dpstv3_can_exit(ch)) {
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP2);
- set_reg_flag(ch, false);
- reflesh = true;
- }
-#endif
- break;
- case eDI_TOP_STATE_UNREG_STEP2:
- /*debug only dbg_reg("%s:ch[%d]:UNREG_STEP2\n",__func__, ch);*/
- div3_unreg_variable(ch);
-
- /*pre ops*/
- set_h_ppre(ch);
- if (pre && pre->ops.unreg_var)
- pre->ops.unreg_var(pre);
-
- //dim_htr_stop(ch);
- if (!get_reg_flag_all()) {
- div3_unreg_setting();
- /*pre ops*/
- if (pre && pre->ops.unreg_hw)
- pre->ops.unreg_hw(pre);
- dprev3_init();
- dpostv3_init();
- }
-
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
- /*debug only dbg_reg("ch[%d]UNREG_STEP2 end\n",ch);*/
- break;
- }
- }
-}
-
-void dipv3_chst_process_ch(void)
-{
- unsigned int ch;
- unsigned int chst;
- struct di_hpre_s *pre = get_hw_pre();
- struct di_ch_s *pch = NULL;
- struct dim_dvfm_s *pdvfm;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- chst = dipv3_chst_get(ch);
- if (chst > EDI_TOP_STATE_IDLE)
- pch = get_chdata(ch);
-
- switch (chst) {
- case eDI_TOP_STATE_REG_STEP2:
- //pr_info("x2\n");
- if (dipv3_cma_get_st(ch) == EDI_CMA_ST_READY) {
- if (div3_cfg_top_get(EDI_CFG_first_bypass)) {
- if (get_sum_g(ch) == 0)
- dimv3_bypass_first_frame(ch);
- else
- PR_INF("ch[%d],g[%d]\n",
- ch, get_sum_g(ch));
- }
- dipv3_chst_set(ch, EDI_TOP_STATE_READY);
- set_reg_flag(ch, true);
- }
- break;
-#if 1
- case eDI_TOP_STATE_UNREG_STEP1:
- dvfmv3_recycle(pch);
- if (dprev3_can_exit(ch) && dpstv3_can_exit(ch)) {
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP2);
- set_reg_flag(ch, false);
- }
-
- break;
-#endif
- case eDI_TOP_STATE_UNREG_STEP2:
- dbg_reg("%s:ch[%d]:at UNREG_STEP2\n", __func__, ch);
- div3_unreg_variable(ch);
- /*pre ops*/
- set_h_ppre(ch);
-
- //dim_htr_stop(ch);
- if (pre && pre->ops.unreg_var)
- pre->ops.unreg_var(pre);
-
- if (!get_reg_flag_all()) {
- div3_unreg_setting();
- if (pre && pre->ops.unreg_hw)
- pre->ops.unreg_hw(pre);
- dprev3_init();
- dpostv3_init();
- }
-
- dipv3_chst_set(ch, EDI_TOP_STATE_IDLE);
- dbg_reg("ch[%d]STEP2 end\n", ch);
- break;
- case EDI_TOP_STATE_READY:
- dvfmv3_recycle(pch);
- pch->interf.op_dvfm_fill(pch);//dvfm_fill_in(pch);
- dimv3_post_keep_back_recycle(ch);
- dimv3_sumx_set(ch);
- break;
- case eDI_TOP_STATE_BYPASS:
- //pr_info("x0\n");
- dvfmv3_recycle(pch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- if (pdvfm && !pdvfm->wmode.need_bypass) {
- pr_info("x1\n");
- setv3_bypass2_complete(ch, false);
- di_reg_variable_normal(ch, pdvfm);
- dipv3_chst_set(ch, eDI_TOP_STATE_REG_STEP2);
- //dvfm_fill_in(pch);
- pch->interf.op_dvfm_fill(pch);
- }
-
- break;
- }
- }
-}
-
-bool dipv3_chst_change_2unreg(void)
-{
- unsigned int ch;
- unsigned int chst;
- bool ret = false;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- chst = dipv3_chst_get(ch);
- dbg_poll("[%d]%d\n", ch, chst);
- if (chst == eDI_TOP_STATE_UNREG_STEP1) {
- dbg_reg("%s:ch[%d]to UNREG_STEP2\n", __func__, ch);
- set_reg_flag(ch, false);
- dipv3_chst_set(ch, eDI_TOP_STATE_UNREG_STEP2);
- ret = true;
- }
- }
- return ret;
-}
-
-/****************************************************************
- * tmode
- ****************************************************************/
-void dimv3_tmode_preset(void)
-{
- struct di_mng_s *pbm = get_bufmng();
- unsigned int ch;
- unsigned int cnt;
-
- /*EDIM_TMODE_1_PW_VFM*/
- cnt = min_t(size_t, DI_CHANNEL_NUB, cfgg(TMODE_1));
- for (ch = 0; ch < cnt; ch++)
- pbm->tmode_pre[ch] = EDIM_TMODE_1_PW_VFM;
-
- /*EDIM_TMODE_2_PW_OUT*/
- cnt += cfgg(TMODE_2);
- cnt = min_t(size_t, DI_CHANNEL_NUB, cnt);
- for (; ch < cnt; ch++)
- pbm->tmode_pre[ch] = EDIM_TMODE_2_PW_OUT;
-
- /*EDIM_TMODE_3_PW_LOCAL*/
- cnt += cfgg(TMODE_3);
- cnt = min_t(size_t, DI_CHANNEL_NUB, cnt);
- for (; ch < cnt; ch++)
- pbm->tmode_pre[ch] = EDIM_TMODE_3_PW_LOCAL;
-
- /*dbg*/
- PR_INF("dimv3_tmode_preset:\n");
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++)
- PR_INF("\tch[%d]:tmode[%d]\n", ch, pbm->tmode_pre[ch]);
-}
-
-void dim_tmode_set(unsigned int ch, enum EDIM_TMODE tmode)
-{
- struct di_mng_s *pbm = get_bufmng();
-
- if (ch >= DI_CHANNEL_NUB)
- return;
-
- pbm->tmode_pre[ch] = tmode;
-}
-
-bool dimv3_tmode_is_localpost(unsigned int ch)
-{
-// struct di_mng_s *pbm = get_bufmng();
- struct di_ch_s *pch;
-
- if (ch >= DI_CHANNEL_NUB) {
- PR_ERR("%s:ch[%d]\n", __func__, ch);
- return false;
- }
- pch = get_chdata(ch);
-
- if (pch->interf.tmode == EDIM_TMODE_2_PW_OUT)
- return false;
- return true;
-}
-#if 0
-void di_reg_flg_check(void)
-{
- int ch;
- unsigned int chst;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++)
- chst = dipv3_chst_get(ch);
-}
-#endif
-
-void dipv3_hw_process(void)
-{
- div3_dbg_task_flg = 5;
- dprev3_process();
- div3_dbg_task_flg = 6;
- prev3_mode_setting();
- div3_dbg_task_flg = 7;
- dpstv3_process();
- div3_dbg_task_flg = 8;
-}
-
-const char * const div3_top_state_name[] = {
- "NOPROB",
- "IDLE",
- "REG_STEP1",
- "REG_P1",
- "REG_STEP2",
- "READY",
- "BYPASS",
- "UNREG_STEP1",
- "UNREG_STEP2"
-};
-
-const char *dipv3_chst_get_name_curr(unsigned int ch)
-{
- const char *p = "";
- enum EDI_TOP_STATE chst;
-
- chst = dipv3_chst_get(ch);
-
- if (chst < ARRAY_SIZE(div3_top_state_name))
- p = div3_top_state_name[chst];
-
- return p;
-}
-
-const char *dipv3_chst_get_name(enum EDI_TOP_STATE chst)
-{
- const char *p = "";
-
- if (chst < ARRAY_SIZE(div3_top_state_name))
- p = div3_top_state_name[chst];
-
- return p;
-}
-/***********************************************
- *mm cfg
- **********************************************/
-static const struct di_mm_cfg_s c_mm_cfg_normal = {
- .di_h = 1088,
- .di_w = 1920,
- .num_local = MAX_LOCAL_BUF_NUM,
- .num_post = MAX_POST_BUF_NUM,
-};
-
-/**********************************/
-/* TIME OUT CHEKC api*/
-/**********************************/
-
-void div3_tout_int(struct di_time_out_s *tout, unsigned int thd)
-{
- tout->en = false;
- tout->timer_start = 0;
- tout->timer_thd = thd;
-}
-
-bool div3_tout_contr(enum eDI_TOUT_CONTR cmd, struct di_time_out_s *tout)
-{
- unsigned long ctimer;
- unsigned long diff;
- bool ret = false;
-
- ctimer = curv3_to_msecs();
-
- switch (cmd) {
- case eDI_TOUT_CONTR_EN:
- tout->en = true;
- tout->timer_start = ctimer;
- break;
- case eDI_TOUT_CONTR_FINISH:
- if (tout->en) {
- diff = ctimer - tout->timer_start;
-
- if (diff > tout->timer_thd) {
- tout->over_flow_cnt++;
-
- if (tout->over_flow_cnt > 0xfffffff0) {
- tout->over_flow_cnt = 0;
- tout->flg_over = 1;
- }
- #if 0
- if (tout->do_func)
- tout->do_func();
-
- #endif
- ret = true;
- }
- tout->en = false;
- }
- break;
-
- case eDI_TOUT_CONTR_CHECK: /*if time is overflow, disable timer*/
- if (tout->en) {
- diff = ctimer - tout->timer_start;
-
- if (diff > tout->timer_thd) {
- tout->over_flow_cnt++;
-
- if (tout->over_flow_cnt > 0xfffffff0) {
- tout->over_flow_cnt = 0;
- tout->flg_over = 1;
- }
- #if 0
- if (tout->do_func)
- tout->do_func();
-
- #endif
- ret = true;
- tout->en = false;
- }
- }
- break;
- case eDI_TOUT_CONTR_CLEAR:
- tout->en = false;
- tout->timer_start = ctimer;
- break;
- case eDI_TOUT_CONTR_RESET:
- tout->en = true;
- tout->timer_start = ctimer;
- break;
- }
-
- return ret;
-}
-
-const unsigned int div3_ch2mask_table[DI_CHANNEL_MAX] = {
- DI_BIT0,
- DI_BIT1,
- DI_BIT2,
- DI_BIT3,
-};
-/****************************************
- *bit control
- ****************************************/
-static const unsigned int bit_tab[32] = {
- DI_BIT0,
- DI_BIT1,
- DI_BIT2,
- DI_BIT3,
- DI_BIT4,
- DI_BIT5,
- DI_BIT6,
- DI_BIT7,
- DI_BIT8,
- DI_BIT9,
- DI_BIT10,
- DI_BIT11,
- DI_BIT12,
- DI_BIT13,
- DI_BIT14,
- DI_BIT15,
- DI_BIT16,
- DI_BIT17,
- DI_BIT18,
- DI_BIT19,
- DI_BIT20,
- DI_BIT21,
- DI_BIT22,
- DI_BIT23,
- DI_BIT24,
- DI_BIT25,
- DI_BIT26,
- DI_BIT27,
- DI_BIT28,
- DI_BIT29,
- DI_BIT30,
- DI_BIT31
-};
-
-void bsetv3(unsigned int *p, unsigned int bitn)
-{
- *p = *p | bit_tab[bitn];
-}
-
-void bclrv3(unsigned int *p, unsigned int bitn)
-{
- *p = *p & (~bit_tab[bitn]);
-}
-
-bool bgetv3(unsigned int *p, unsigned int bitn)
-{
- return (*p & bit_tab[bitn]) ? true : false;
-}
-
-/****************************************/
-/* do_table */
-/****************************************/
-
-/*for do_table_working*/
-#define K_DO_TABLE_LOOP_MAX 15
-
-const struct do_table_s dov3_table_def = {
- .ptab = NULL,
- .data = NULL,
- .size = 0,
- .op_lst = K_DO_TABLE_ID_STOP,
- .op_crr = K_DO_TABLE_ID_STOP,
- .do_stop = 0,
- .flg_stop = 0,
- .do_pause = 0,
- .do_step = 0,
- .flg_repeat = 0,
-
-};
-
-void dov3_table_init(struct do_table_s *pdo,
- const struct do_table_ops_s *ptable,
- unsigned int size_tab)
-{
- memcpy(pdo, &dov3_table_def, sizeof(struct do_table_s));
-
- if (ptable) {
- pdo->ptab = ptable;
- pdo->size = size_tab;
- }
-}
-
-/*if change to async?*/
-/* now only call in same thread */
-void dov3_talbe_cmd(struct do_table_s *pdo, enum eDO_TABLE_CMD cmd)
-{
- switch (cmd) {
- case eDO_TABLE_CMD_NONE:
- PR_INF("test:%s\n", __func__);
- break;
- case eDO_TABLE_CMD_STOP:
- pdo->do_stop = true;
- break;
- case eDO_TABLE_CMD_START:
- if (pdo->op_crr == K_DO_TABLE_ID_STOP) {
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr = K_DO_TABLE_ID_START;
- pdo->do_stop = false;
- pdo->flg_stop = false;
- } else if (pdo->op_crr == K_DO_TABLE_ID_PAUSE) {
- pdo->op_crr = pdo->op_lst;
- pdo->op_lst = K_DO_TABLE_ID_PAUSE;
- pdo->do_pause = false;
- } else {
- PR_INF("crr is [%d], not start\n", pdo->op_crr);
- }
- break;
- case eDO_TABLE_CMD_PAUSE:
- if (pdo->op_crr <= K_DO_TABLE_ID_STOP) {
- /*do nothing*/
- } else {
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr = K_DO_TABLE_ID_PAUSE;
- pdo->do_pause = true;
- }
- break;
- case eDO_TABLE_CMD_STEP:
- pdo->do_step = true;
- break;
- case eDO_TABLE_CMD_STEP_BACK:
- pdo->do_step = false;
- break;
- default:
- break;
- }
-}
-
-bool dov3_table_is_crr(struct do_table_s *pdo, unsigned int state)
-{
- if (pdo->op_crr == state)
- return true;
- return false;
-}
-
-void dov3_table_working(struct do_table_s *pdo)
-{
- const struct do_table_ops_s *pcrr;
- unsigned int ret = 0;
- unsigned int next;
- bool flash = false;
- unsigned int cnt = 0; /*proction*/
- unsigned int lst_id; /*dbg only*/
- char *name = ""; /*dbg only*/
- bool need_pr = false; /*dbg only*/
-
- if (!pdo || !pdo->ptab) {
- PR_ERR("no pdo or ptab\n");
- return;
- }
-
- if (pdo->op_crr >= pdo->size) {
- PR_ERR("di:err:%s:crr=%d,size=%d\n",
- __func__,
- pdo->op_crr,
- pdo->size);
- return;
- }
-
- pcrr = pdo->ptab + pdo->op_crr;
-
- if (pdo->name)
- name = pdo->name;
- /*stop ?*/
- if (pdo->do_stop &&
- (pcrr->mark & K_DO_TABLE_CAN_STOP)) {
- dbg_dt("%s:do stop\n", name);
-
- /*do stop*/
- if (pcrr->do_stop_op)
- pcrr->do_stop_op(pdo->data);
- /*set status*/
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr = K_DO_TABLE_ID_STOP;
- pdo->flg_stop = true;
- pdo->do_stop = false;
-
- return;
- }
-
- /*pause?*/
- if (pdo->op_crr == K_DO_TABLE_ID_STOP ||
- pdo->op_crr == K_DO_TABLE_ID_PAUSE)
- return;
-
- do {
- flash = false;
- cnt++;
- if (cnt > K_DO_TABLE_LOOP_MAX) {
- PR_ERR("di:err:%s:loop more %d\n", name, cnt);
- break;
- }
-
- /*stop again? */
- if (pdo->do_stop &&
- (pcrr->mark & K_DO_TABLE_CAN_STOP)) {
- /*do stop*/
- dbg_dt("%s: do stop in loop\n", name);
- if (pcrr->do_stop_op)
- pcrr->do_stop_op(pdo->data);
- /*set status*/
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr = K_DO_TABLE_ID_STOP;
- pdo->flg_stop = true;
- pdo->do_stop = false;
-
- break;
- }
-
- /*debug:*/
- lst_id = pdo->op_crr;
- need_pr = true;
-
- if (pcrr->con) {
- if (pcrr->con(pdo->data))
- ret = pcrr->do_op(pdo->data);
- else
- break;
-
- } else {
- ret = pcrr->do_op(pdo->data);
- dbg_dt("do_table:do:%d:ret=0x%x\n", pcrr->id, ret);
- }
-
- /*not finish, keep current status*/
- if ((ret & K_DO_TABLE_R_B_FINISH) == 0) {
- dbg_dt("%s:not finish,wait\n", __func__);
- break;
- }
-
- /*fix to next */
- if (ret & K_DO_TABLE_R_B_NEXT) {
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr++;
- if (pdo->op_crr >= pdo->size) {
- pdo->op_crr = pdo->flg_repeat ?
- K_DO_TABLE_ID_START
- : K_DO_TABLE_ID_STOP;
- dbg_dt("%s:to end,%d\n", __func__,
- pdo->op_crr);
- break;
- }
- /*return;*/
- flash = true;
- } else {
- next = ((ret & K_DO_TABLE_R_B_OTHER) >>
- K_DO_TABLE_R_B_OTHER_SHIFT);
- if (next < pdo->size) {
- pdo->op_lst = pdo->op_crr;
- pdo->op_crr = next;
- if (next > K_DO_TABLE_ID_STOP)
- flash = true;
- else
- flash = false;
- } else {
- PR_ERR("%s: next[%d] err:\n",
- __func__, next);
- }
- }
- /*debug 1:*/
- need_pr = false;
- if (lst_id != pdo->op_crr) {
- dbg_dt("do_table:%s:%s->%s\n", pdo->name,
- pdo->ptab[lst_id].name,
- pdo->ptab[pdo->op_crr].name);
- }
-
- pcrr = pdo->ptab + pdo->op_crr;
- } while (flash && !pdo->do_step);
-
- /*debug 2:*/
- if (need_pr) {
- if (lst_id != pdo->op_crr) {
- dbg_dt("do_table2:%s:%s->%s\n", pdo->name,
- pdo->ptab[lst_id].name,
- pdo->ptab[pdo->op_crr].name);
- }
- }
-}
-
-/********************************************************************
- * dvfm
- *******************************************************************/
-void dvfm_prob(struct di_ch_s *pch)
-{
- int i;
- struct dim_dvfm_s *pdvfm;
-
- if (!pch)
- return;
-
- for (i = 0; i < DIM_K_VFM_NUM; i++) {
- pdvfm = &pch->dvfm[i];
- /*clear*/
- memset(pdvfm, 0, sizeof(*pdvfm));
-
- /*set code*/
-// pdvfm->code_name = DIM_K_CODE_DVFM;
- pdvfm->index = i;
- }
-}
-
-void dvfm_reg(struct di_ch_s *pch)
-{
- dvfm_prob(pch);
-}
-
-struct dim_dvfm_s *dvfmv3_get(struct di_ch_s *pch, enum QUED_TYPE qtype)
-{
- struct dim_dvfm_s *pdvfm;
- unsigned int dvfm_id;
- bool ret;
-
- if (!pch) {
- PR_ERR("%s:p is null\n", __func__);
- return NULL;
- }
-
- ret = qued_ops.out(pch, qtype, &dvfm_id);
-
- if (!ret ||
- dvfm_id >= DIM_K_VFM_NUM) {
- PR_ERR("%s:ch[%d]:que:%s:get failed:ret[%d],id[0x%x]\n",
- __func__,
- pch->ch_id,
- qued_ops.get_name(pch, qtype),
- ret, dvfm_id);
- return NULL;
- }
-
- pdvfm = &pch->dvfm[dvfm_id];
- if (!pdvfm)
- return NULL;
-
- return pdvfm;
-}
-
-struct dim_dvfm_s *dvfmv3_peek(struct di_ch_s *pch, enum QUED_TYPE qtype)
-{
- struct dim_dvfm_s *pdvfm;
- unsigned int dvfm_id;
- bool ret;
-
- if (!pch) {
- PR_ERR("%s:p is null\n", __func__);
- return NULL;
- }
-
- ret = qued_ops.peek(pch, qtype, &dvfm_id);
-
- if (ret && dvfm_id >= DIM_K_VFM_NUM) {
- PR_ERR("%s:ch[%d]:que:%s:get failed:ret[%d],id[%d]\n",
- __func__,
- pch->ch_id,
- qued_ops.get_name(pch, qtype),
- ret, dvfm_id);
- return NULL;
- }
-
- if (!ret) /*empty*/
- pdvfm = NULL;
- else
- pdvfm = &pch->dvfm[dvfm_id];
-
- return pdvfm;
-}
-
-#define VFM_NEED_BYPASS (VIDTYPE_MVC | \
- VIDTYPE_VIU_444 | \
- VIDTYPE_PIC)
-
-/* for dvfm_fill_in use*/
-bool dimv3_need_bypass2(struct di_in_inf_s *in_inf, struct vframe_s *vf)
-{
- struct di_mm_s *mm;
-
- if (!in_inf || !vf)
- return true;
-
- mm = dim_mm_get(in_inf->ch);
-
- if (!mm)
- return true;
-
- /*vfm type*/
- if (vf->type & VFM_NEED_BYPASS)
- return true;
- if (vf->source_type == VFRAME_SOURCE_TYPE_PPMGR)
- return true;
-#if 1
- if (vfv3_type_is_prog(vf->type)) {/*temp bypass p*/
- return true;
- }
-#endif
- /*true bypass for 720p above*/
- if ((vf->flag & VFRAME_FLAG_GAME_MODE) &&
- (vf->width > 720))
- return true;
- /*support G12A and TXLX platform*/
- if (vf->type & VIDTYPE_COMPRESS) {
- if (!dimhv3_afbc_is_supported())
- return true;
- }
-
- if ((in_inf->w > mm->cfg.di_w) ||
- (in_inf->h > mm->cfg.di_h))
- return true;
-
- if ((dimp_get(eDI_MP_di_debug_flag) >> 20) & 0x1)
- return true;
-
- return false;
-}
-
-void dimv3_polic_cfg(unsigned int cmd, bool on)
-{
- //struct dim_policy_s *pp;
-#ifdef TST_NEW_INS_RUN_Q
- if (dil_get_diffver_flag() != 1)
- return;
-#endif
-#if 0
- pp = get_dpolicy();
- switch (cmd) {
- case K_DIM_BYPASS_CLEAR_ALL:
- pp->cfg_d32 = 0x0;
- break;
- case K_DIM_I_FIRST:
- pp->cfg_b.i_first = on;
- break;
- case K_DIM_BYPASS_ALL_P:
- pp->cfg_b.bypass_all_p = on;
- break;
- default:
- PR_WARN("%s:cmd is overflow[%d]\n", __func__, cmd);
- break;
- }
-#endif
-}
-EXPORT_SYMBOL(dimv3_polic_cfg);
-
-unsigned int dimv3_get_trick_mode(void)
-{
- unsigned int trick_mode;
-
- if (dimp_get(eDI_MP_bypass_trick_mode)) {
- int trick_mode_fffb = 0;
- int trick_mode_i = 0;
-
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x1)
- query_video_status(0, &trick_mode_fffb);
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x2)
- query_video_status(1, &trick_mode_i);
- trick_mode =
- trick_mode_fffb | (trick_mode_i << 1);
-
- return trick_mode;
- }
- return 0;
-}
-/**********************************
- *diff with dim_is_bypass
- * delet di_vscale_skip_enable
- * use vf_in replace ppre
- * for dvfm_fill_in
- **********************************/
-bool isv3_bypass2(struct vframe_s *vf_in, struct di_ch_s *pch,
- unsigned int *reason)
-{
- if (div3_cfgx_get(pch->ch_id, eDI_CFGX_BYPASS_ALL)) {
- *reason = 1;
- return true;
- }
- #if 0
- /*?*/
- if (dimp_get(eDI_MP_bypass_trick_mode)) {
- int trick_mode_fffb = 0;
- int trick_mode_i = 0;
-
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x1)
- query_video_status(0, &trick_mode_fffb);
- if (dimp_get(eDI_MP_bypass_trick_mode) & 0x2)
- query_video_status(1, &trick_mode_i);
- pdvfm->wmode.trick_mode =
- trick_mode_fffb | (trick_mode_i << 1);
- if (pdvfm->wmode.trick_mode)
- return true;
- }
- #endif
- /* check vframe */
- //vf_in = pdvfm->vfm_in;
- if (!vf_in)
- return false;
-
- if ((vf_in->width < 16) || (vf_in->height < 16)) {
- *reason = 2;
- return true;
- }
-
- if (dimp_get(eDI_MP_bypass_3d) &&
- (vf_in->trans_fmt != 0)) {
- *reason = 3;
- return true;
- }
-
-/*prot is conflict with di post*/
- if (vf_in->video_angle) {
- *reason = 4;
- return true;
- }
-
- return false;
-}
-
-void dimv3_reg_cfg_sys(struct di_ch_s *pch)
-{
- //struct di_data_l_s *pdata = get_datal(void)
- bool bit10_pack_patch = false;
- unsigned int width_roundup = 2;
- struct di_mng_s *pbm = get_bufmng();
- unsigned int ch;
-
- if (!pch)
- return;
-
- /*set width_roundup*/
- bit10_pack_patch = (is_meson_gxtvbb_cpu() ||
- is_meson_gxl_cpu() ||
- is_meson_gxm_cpu());
-
- pch->cfgt.w_rdup = bit10_pack_patch ? 16 : width_roundup;
-
- /*set force_w | force_h*/
- pch->cfgt.f_w = dimp_get(eDI_MP_force_width);
- pch->cfgt.f_h = dimp_get(eDI_MP_force_height);
- if (dimp_get(eDI_MP_di_force_bit_mode) == 10) {
- if (pch->cfgt.f_w) {
- pch->cfgt.f_w =
- roundup(pch->cfgt.f_w, width_roundup);
- }
- }
-
- if (dimp_get(eDI_MP_di_force_bit_mode) == 10) {
- pch->cfgt.vfm_bitdepth = (BITDEPTH_Y10);
- if (dimp_get(eDI_MP_full_422_pack))
- pch->cfgt.vfm_bitdepth |= (FULL_PACK_422_MODE);
- } else {
- pch->cfgt.vfm_bitdepth = (BITDEPTH_Y8);
- }
-
- pch->cfgt.ens.en_32 = 0;
- if (dimp_get(eDI_MP_pre_hsc_down_en))
- pch->cfgt.ens.b.h_sc_down = 1;
-
- if (dimp_get(eDI_MP_pps_en))
- pch->cfgt.ens.b.pps_enable = 1;
-
- if (cfgg(PMODE) == 2) { /*use 2 i buf*/
- dimp_set(eDI_MP_prog_proc_config, 0x03);
- }
-
- /*tmode*/
- ch = pch->ch_id;
- pch->cfgt.tmode = pbm->tmode_pre[ch];
-}
-
-unsigned int topv3_bot_config(unsigned int vtype)
-{
- unsigned int vfm_type = vtype;
-
- if ((vfm_type & VIDTYPE_TYPEMASK) ==
- VIDTYPE_INTERLACE_TOP) {
- vfm_type &= (~VIDTYPE_TYPEMASK);
- vfm_type |= VIDTYPE_INTERLACE_BOTTOM;
- } else {
- vfm_type &= (~VIDTYPE_TYPEMASK);
- vfm_type |= VIDTYPE_INTERLACE_TOP;
- }
- return vfm_type;
-}
-
-void dvfmv3_recycle(struct di_ch_s *pch)
-{
- int i;
- struct dim_dvfm_s *pdvfm;
- unsigned int back_in;
-
- for (i = 0; i < DIM_K_VFM_NUM; i++) {
- pdvfm = dvfmv3_peek(pch, QUED_T_RECYCL);
- if (!pdvfm)
- break;
- pdvfm = dvfmv3_get(pch, QUED_T_RECYCL);
-// back_c = pdvfm->code_name;
- back_in = pdvfm->index;
-
- memset(pdvfm, 0, sizeof(*pdvfm));
-// pdvfm->code_name = back_c;
- pdvfm->index = back_in;
- qued_ops.in(pch, QUED_T_FREE, pdvfm->index);
- }
-}
-
-/****************************/
-void dipv3_init_value_reg(unsigned int ch)
-{
- struct di_post_stru_s *ppost;
-// struct di_buf_s *keep_post_buf;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- struct di_ch_s *pch = get_chdata(ch);
-// struct di_data_l_s *pdt = get_datal();
-// struct dim_dvfm_s *pdvfm;
- int i;
-
- if (!pch)
- return;
-
- PR_INF("%s:\n", __func__);
-
- /*post*/
- ppost = get_post_stru(ch);
- /*keep buf:*/
- /*keep_post_buf = ppost->keep_buf_post;*/
-
- memset(ppost, 0, sizeof(struct di_post_stru_s));
- ppost->next_canvas_id = 1;
-
- /*pre*/
- memset(ppre, 0, sizeof(struct di_pre_stru_s));
-
- /*clear dvfm*/
- dvfm_reg(pch);
-
- /*qued*/
- qued_ops.reg(pch);
-
- /*put all dvfm to free*/
- for (i = 0; i < DIM_K_VFM_NUM; i++)
- qued_ops.in(pch, QUED_T_FREE, i);
-
- if ((pch->interf.tmode == EDIM_TMODE_2_PW_OUT ||
- pch->interf.tmode == EDIM_TMODE_3_PW_LOCAL)) {
- /*que buf*/
- for (i = 0; i < DIM_K_BUF_IN_LIMIT; i++)
- qued_ops.in(pch, QUED_T_IS_FREE, i);
-
- for (i = 0; i < DIM_K_BUF_OUT_LIMIT; i++)
- qued_ops.in(pch, QUED_T_IS_PST_FREE, i);
- } else {
- PR_INF("%s:tmod[%d]\n", __func__, pch->interf.tmode);
- }
- /*last dvfm*/
- memset(&pch->lst_dvfm, 0, sizeof(struct dim_dvfm_s));
-
- di_bypass_state_set(ch, false);
-}
-
-static bool dip_init_value(void) /*call in prob*/
-{
- unsigned int ch;
- struct di_post_stru_s *ppost;
- struct di_mm_s *mm;// = dim_mm_get();
- struct dim_mm_t_s *mmt = dim_mmt_get();
- //struct di_data_l_s *pdata = get_datal();
- struct di_ch_s *pch;
- bool ret = false;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- /*ch_data*/
- pch = get_chdata(ch);
- pch->ch_id = ch;
-
- /*ppost*/
- ppost = get_post_stru(ch);
- memset(ppost, 0, sizeof(struct di_post_stru_s));
- ppost->next_canvas_id = 1;
-
- /*que*/
- ret = div3_que_alloc(ch);
- if (ret) {
- pwv3_queue_clear(ch, QUE_POST_KEEP);
- pwv3_queue_clear(ch, QUE_POST_KEEP_BACK);
- }
-
- mm = dim_mm_get(ch);
-
- memcpy(&mm->cfg, &c_mm_cfg_normal, sizeof(struct di_mm_cfg_s));
-
- /*qued*/
- qued_ops.prob(pch);
-
- /*dvfm*/
- dvfm_prob(pch);
- }
- /*mmm top*/
- mmt->mem_start = 0;
- mmt->mem_size = 0;
- mmt->total_pages = NULL;
- set_current_channel(0);
-
- return ret;
-}
-
-/******************************************
- * pq ops
- *****************************************/
-void dipv3_init_pq_ops(void)
-{
- di_attach_ops_pulldown(&get_datal()->ops_pd);
- di_attach_ops_3d(&get_datal()->ops_3d);
- di_attach_ops_nr(&get_datal()->ops_nr);
- di_attach_ops_mtn(&get_datal()->ops_mtn);
-
- dimv3_attach_to_local();
-}
-
-/**********************************/
-void dipv3_clean_value(void)
-{
- unsigned int ch;
- struct di_data_l_s *pdt = get_datal();
- struct di_ch_s *pch;
-
- if (!pdt)
- return;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- /*que*/
- div3_que_release(ch);
-
- /*qued*/
- pch = get_chdata(ch);
- qued_ops.remove(pch);
- }
-}
-
-bool dipv3_prob(void)
-{
- bool ret = true;
-
- ret = dip_init_value();
-
- div3_cfgx_init_val();
- div3_cfg_top_init_val();
- div3_mp_uit_init_val();
- div3_mp_uix_init_val();
-
- dimv3_tmode_preset(); /*need before vframe*/
-
- devv3_vframe_init();
- didbgv3_fs_init();
- dip_wq_prob();
- dip_cma_init_val();
- dipv3_chst_init();
-
- dprev3_init();
- dpostv3_init();
-
- hprev3_prob();
- dipv3_init_pq_ops();
-
-
- return ret;
-}
-
-void dipv3_exit(void)
-{
- dip_wq_ext();
- devv3_vframe_exit();
- dipv3_clean_value();
- didbgv3_fs_exit();
-}
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_prc.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_PRC_H__
-#define __DI_PRC_H__
-
-bool dipv3_prob(void);
-void dipv3_exit(void);
-
-void dipv3_even_reg_init_val(unsigned int ch);
-void dipv3_even_unreg_val(unsigned int ch);
-
-/************************/
-/* CMA */
-/************************/
-void dipv3_wq_cma_run(unsigned char ch, bool reg_cmd);
-bool dipv3_cma_st_is_ready(unsigned int ch);
-bool dipv3_cma_st_is_idle(unsigned int ch);
-bool dipv3_cma_st_is_idl_all(void);
-enum eDI_CMA_ST dipv3_cma_get_st(unsigned int ch);
-void dipv3_cma_st_set_ready_all(void);
-void dipv3_cma_close(void);
-const char *div3_cma_dbg_get_st_name(unsigned int ch);
-
-/*************************/
-/* STATE*/
-/*************************/
-int dipv3_event_reg_chst(unsigned int ch);
-bool dipv3_event_unreg_chst(unsigned int ch);
-void dipv3_chst_process_reg(unsigned int ch);
-
-void dipv3_hw_process(void);
-
-void dipv3_chst_process_ch(void);
-bool dipv3_chst_change_2unreg(void);
-
-enum EDI_TOP_STATE dipv3_chst_get(unsigned int ch);
-const char *dipv3_chst_get_name_curr(unsigned int ch);
-const char *dipv3_chst_get_name(enum EDI_TOP_STATE chst);
-
-/**************************************
- *
- * summmary variable
- *
- **************************************/
-void div3_sum_reg_init(unsigned int ch);
-void div3_sum_set(unsigned int ch, enum eDI_SUM id, unsigned int val);
-unsigned int div3_sum_inc(unsigned int ch, enum eDI_SUM id);
-unsigned int div3_sum_get(unsigned int ch, enum eDI_SUM id);
-void div3_sum_get_info(unsigned int ch, enum eDI_SUM id, char **name,
- unsigned int *pval);
-unsigned int div3_sum_get_tab_size(void);
-bool div3_sum_check(unsigned int ch, enum eDI_SUM id);
-
-/**************************************
- *
- * cfg ctr top
- * bool
- **************************************/
-bool div3_cfg_top_check(unsigned int idx);
-char *div3_cfg_top_get_name(enum eDI_CFG_TOP_IDX idx);
-void div3_cfg_top_get_info(unsigned int idx, char **name);
-void div3_cfg_top_init_val(void);
-void div3_cfg_top_dts(void);
-unsigned int div3_cfg_top_get(enum eDI_CFG_TOP_IDX id);
-void div3_cfg_top_set(enum eDI_CFG_TOP_IDX id, unsigned int en);
-void div3_cfgt_show_item_sel(struct seq_file *s);
-void div3_cfgt_show_item_all(struct seq_file *s);
-void div3_cfgt_show_val_sel(struct seq_file *s);
-void div3_cfgt_show_val_all(struct seq_file *s);
-void div3_cfgt_set_sel(unsigned int dbg_mode, unsigned int id);
-
-/**************************************
- *
- * cfg ctr x
- * bool
- **************************************/
-char *div3_cfgx_get_name(enum eDI_CFGX_IDX idx);
-void div3_cfgx_get_info(enum eDI_CFGX_IDX idx, char **name);
-void div3_cfgx_init_val(void);
-bool div3_cfgx_get(unsigned int ch, enum eDI_CFGX_IDX idx);
-void div3_cfgx_set(unsigned int ch, enum eDI_CFGX_IDX idx, bool en);
-
-/**************************************
- *
- * module para top
- * int
- **************************************/
-char *div3_mp_uit_get_name(enum eDI_MP_UI_T idx);
-void div3_mp_uit_init_val(void);
-//int di_mp_uit_get(enum eDI_MP_UI_T idx);
-//void di_mp_uit_set(enum eDI_MP_UI_T idx, int val);
-
-/**************************************
- *
- * module para x
- * unsigned int
- **************************************/
-char *div3_mp_uix_get_name(enum eDI_MP_UIX_T idx);
-void div3_mp_uix_init_val(void);
-unsigned int div3_mp_uix_get(unsigned int ch, enum eDI_MP_UIX_T idx);
-void div3_mp_uix_set(unsigned int ch, enum eDI_MP_UIX_T idx,
- unsigned int val);
-
-/****************************************/
-/* do_table */
-/****************************************/
-void dov3_table_init(struct do_table_s *pdo,
- const struct do_table_ops_s *ptable,
- unsigned int size_tab);
-/* now only call in same thread */
-void dov3_talbe_cmd(struct do_table_s *pdo, enum eDO_TABLE_CMD cmd);
-void dov3_table_working(struct do_table_s *pdo);
-bool dov3_table_is_crr(struct do_table_s *pdo, unsigned int state);
-
-enum eDI_SUB_ID pwv3_ch_next_count(enum eDI_SUB_ID channel);
-
-void dipv3_init_value_reg(unsigned int ch);
-
-bool div3_is_pause(unsigned int ch);
-void div3_pause_step_done(unsigned int ch);
-void div3_pause(unsigned int ch, bool on);
-
-void dimv3_tst_4k_reg_val(void);
-unsigned int dimv3_get_trick_mode(void);
-
-/****************************************
- *bit control
- ****************************************/
-void bsetv3(unsigned int *p, unsigned int bitn);
-void bclrv3(unsigned int *p, unsigned int bitn);
-bool bgetv3(unsigned int *p, unsigned int bitn);
-
-/**************************************
- * get and put in QUED_T_IN
- **************************************/
-struct dim_dvfm_s *dvfmv3_peek(struct di_ch_s *pch, enum QUED_TYPE qtype);
-struct dim_dvfm_s *dvfmv3_get(struct di_ch_s *pch, enum QUED_TYPE qtype);
-void dvfmv3_recycle(struct di_ch_s *pch);
-void dvfmv3_pre_bypassall(struct di_ch_s *pch);
-void dimv3_reg_cfg_sys(struct di_ch_s *pch);
-
-/***************************************
- *
- **************************************/
-void dimv3_sumx_clear(unsigned int ch);
-void dimv3_sumx_set(unsigned int ch);
-/**************************************
- *
- **************************************/
-bool dimv3_tmode_is_localpost(unsigned int ch);
-
-bool dimv3_need_bypass2(struct di_in_inf_s *in_inf, struct vframe_s *vf);
-bool isv3_bypass2(struct vframe_s *vf_in, struct di_ch_s *pch,
- unsigned int *reason);
-unsigned int topv3_bot_config(unsigned int vtype);
-
-
-#endif /*__DI_PRC_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pre.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-
-#include "di_data_l.h"
-#include "di_data.h"
-#include "di_dbg.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_prc.h"
-#include "di_pre.h"
-#include "di_pres.h"
-
-#include "nr_downscale.h"
-#include "register.h"
-
-unsigned int div3_get_other_ch(unsigned int curr)
-{
- return curr ? 0 : 1;
-}
-#if 0
-bool is_bypass_i_p(void)
-{
- bool ret = false;
- struct di_hpre_s *pre = get_hw_pre();
- struct di_in_inf_s *vc = &pre->vinf_curr;
- #if 0
- struct di_vinfo_s *vl = &pre->vinf_lst;
-
- if (vl->ch != vc->ch &&
- vf_type_is_interlace(vl->vtype) &&
- vfv3_type_is_prog(vc->vtype)) {
- ret = true;
- }
- #else
- unsigned int ch_c, ch_l;
-
- struct di_pre_stru_s *ppre_c, *ppre_l;
-
- if (!get_reg_flag(0) ||
- !get_reg_flag(1))
- return ret;
-
- ch_c = vc->ch;
- ch_l = (ch_c ? 0 : 1);
- ppre_c = get_pre_stru(ch_c);
- ppre_l = get_pre_stru(ch_l);
- if (vf_type_is_interlace(ppre_l->cur_inp_type) &&
- vfv3_type_is_prog(ppre_c->cur_inp_type)) {
- ret = true;
- dimv3_print("ch[%d]:bypass p\n", ch_c);
- }
- #endif
-
- return ret;
-}
-#endif
-void dprev3_clear(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- memset(pre, 0, sizeof(struct di_hpre_s));
-}
-
-void dprev3_init(void)
-{/*reg:*/
- struct di_hpre_s *pre = get_hw_pre();
-
- pre->pre_st = eDI_PRE_ST_IDLE;
-
- /*timer out*/
- div3_tout_int(&pre->tout, 40); /*ms*/
-}
-
-void pwv3_use_hw_pre(enum eDI_SUB_ID channel, bool on)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- pre->hw_flg_busy_pre = on;
- if (on)
- pre->curr_ch = channel;
-}
-
-enum eDI_SUB_ID pwv3_ch_next_count(enum eDI_SUB_ID channel)
-{
- int i;
- unsigned int lch, nch;
-
- nch = channel;
- for (i = 0; i < DI_CHANNEL_NUB; i++) {
- lch = channel + i + 1;
- if (lch >= DI_CHANNEL_NUB)
- lch -= DI_CHANNEL_NUB;
- #if 0
- if (pbm->sub_act_flg[lch]) {
- nch = lch;
- break;
- }
- #else
- if (get_reg_flag(lch) &&
- !get_flag_trig_unreg(lch) &&
- !isv3_bypss2_complete(lch)) {
- nch = lch;
- break;
- }
- #endif
- }
- return nch;
-}
-
-/****************************************/
-static bool pw_try_sw_ch_next_pre(enum eDI_SUB_ID channel)
-{
- bool ret = false;
- struct di_hpre_s *pre = get_hw_pre();
- enum eDI_SUB_ID lst_ch, nch;
-
- lst_ch = channel;
-
- nch = pwv3_ch_next_count(lst_ch);
- if (!get_reg_flag(nch) ||
- get_flag_trig_unreg(nch) ||
- isv3_bypss2_complete(nch))
- return false;
-
- pre->curr_ch = nch;
- pre->hw_flg_busy_pre = true;
- ret = true;
-
- /*dim_print("%s:%d->%d:%d\n", __func__, lst_ch, nch, ret);*/
- return ret;
-}
-
-/*****************************/
-/* debug */
-/*****************************/
-
-unsigned int div3_dbg_pre_cnt;
-
-void dbgv3_cnt_begin(void)
-{
- div3_dbg_pre_cnt = 0x10;
-}
-
-void dbgv3_cnt_print(void)
-{
- if (div3_dbg_pre_cnt < 0xf)
- return;
-
- if (div3_dbg_pre_cnt > 0x10) {
- div3_dbg_pre_cnt++;
- PR_INF("[%d]\n", div3_dbg_pre_cnt);
- }
-
- if (div3_dbg_pre_cnt > 0x15)
- div3_dbg_pre_cnt = 0;
-}
-
-/*****************************/
-/* STEP */
-/*****************************/
-void dprev3_recyc(unsigned int ch)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- pre->check_recycle_buf_cnt = 0;
- while (dimv3_check_recycle_buf(ch) & 1) {
- if (pre->check_recycle_buf_cnt++ > MAX_IN_BUF_NUM) {
- di_pr_info("%s: dimv3_check_recycle_buf time out!!\n",
- __func__);
- break;
- }
- }
-}
-
-void dprev3_vdoing(unsigned int ch)
-{
- struct di_post_stru_s *ppost = get_post_stru(ch);
-
- ppost->di_post_process_cnt = 0;
- while (dimv3_pst_vframe_top(ch)) {
- if (ppost->di_post_process_cnt++ >
- MAX_POST_BUF_NUM) {
- di_pr_info("%s: dimv3_process_post_vframe time out!!\n",
- __func__);
- break;
- }
- }
-}
-
-bool dprev3_can_exit(unsigned int ch)
-{
- struct di_hpre_s *pre = get_hw_pre();
- bool ret = false;
-
- if (ch != pre->curr_ch) {
- ret = true;
- } else {
- if (pre->pre_st <= eDI_PRE_ST4_IDLE)
- ret = true;
- }
- PR_INF("%s:ch[%d]:curr[%d]:stat[%s] ret[%d]\n",
- __func__,
- ch, pre->curr_ch,
- dprev3_state4_name_get(pre->pre_st),
- ret);
- return ret;
-}
-
-void dprev3_dbg_f_trig(unsigned int cmd)
-{
- struct di_task *tsk = get_task();
-
- struct di_hpre_s *pre = get_hw_pre();
-
- if (down_interruptible(&tsk->sem)) {
- PR_ERR("%s:can't get sem\n", __func__);
- return;
- }
-
- /*set on/off and trig*/
- if (cmd & 0x10) {
- pre->dbg_f_en = 1;
- pre->dbg_f_cnt = cmd & 0xf;
- pre->dbg_f_lstate = pre->pre_st;
- } else {
- pre->dbg_f_en = 0;
- }
-
- up(&tsk->sem);
-}
-
-void dprev3_process(void)
-{
- bool reflesh;
- struct di_hpre_s *pre = get_hw_pre();
-
- if (pre->dbg_f_en) {
- if (pre->dbg_f_cnt) {
- dprev3_process_step4();
- pre->dbg_f_cnt--;
- }
- if (pre->dbg_f_lstate != pre->pre_st) {
- PR_INF("ch[%d]:state:%s->%s\n",
- pre->curr_ch,
- dprev3_state4_name_get(pre->dbg_f_lstate),
- dprev3_state4_name_get(pre->pre_st));
-
- pre->dbg_f_lstate = pre->pre_st;
- }
- return;
- }
-
- reflesh = true;
-
- while (reflesh) {
- reflesh = dprev3_process_step4();
- #if 0 /*debug only*/
- dbg_tsk("ch[%d]:st[%s]r[%d]\n", pre->curr_ch,
- dprev3_state4_name_get(pre->pre_st), reflesh);
- #endif
- }
-}
-
-enum eDI_PRE_MT {
- eDI_PRE_MT_CHECK = K_DO_TABLE_ID_START,
- eDI_PRE_MT_SET,
- eDI_PRE_MT_WAIT_INT,
- eDI_PRE_MT_TIME_OUT,
-};
-
-/*use do_table:*/
-unsigned int dprev3_mtotal_check(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- unsigned int ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);//K_DO_R_NOT_FINISH;
-
- if ((prev3_run_flag == DI_RUN_FLAG_RUN) ||
- (prev3_run_flag == DI_RUN_FLAG_STEP)) {
- if (prev3_run_flag == DI_RUN_FLAG_STEP)
- prev3_run_flag = DI_RUN_FLAG_STEP_DONE;
- /*dim_print("%s:\n", __func__);*/
- if (dim_pre_de_buf_config_top(pre->curr_ch))
- ret = K_DO_R_FINISH;
- else
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
-
- dimv3_dbg_pre_cnt(pre->curr_ch, "x");
- }
-
- return ret;
-}
-
-unsigned int dprev3_mtotal_set(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- ulong flags = 0;
-
- /*dim_print("%s:\n", __func__);*/
- spin_lock_irqsave(&plistv3_lock, flags);
- dimv3_pre_de_process(pre->curr_ch);
- spin_unlock_irqrestore(&plistv3_lock, flags);
- /*begin to count timer*/
- div3_tout_contr(eDI_TOUT_CONTR_EN, &pre->tout);
-
- return K_DO_R_FINISH;
-}
-
-enum eDI_WAIT_INT {
- eDI_WAIT_INT_NEED_WAIT,
- eDI_WAIT_INT_HAVE_INT,
- eDI_WAIT_INT_TIME_OUT,
-};
-
-/*
- *return: enum eDI_WAIT_INT
- *
- */
-enum eDI_WAIT_INT div3_pre_wait_int(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- ulong flags = 0;
- /*struct di_pre_stru_s *ppre;*/
- struct di_ch_s *pch;
-
- enum eDI_WAIT_INT ret = eDI_WAIT_INT_NEED_WAIT;
-
- pch = get_chdata(pre->curr_ch);
- if (pre->flg_int_done) {
- /*have INT done flg*/
- /*DI_INTR_CTRL[bit 0], NRWR_done, set by
- * hardware when NRWR is done,clear by write 1
- * by code;[bit 1]
- * MTNWR_done, set by hardware when MTNWR
- * is done, clear by write 1 by code;these two
- * bits have nothing to do with
- * DI_INTR_CTRL[16](NRW irq mask, 0 to enable
- * irq) and DI_INTR_CTRL[17]
- * (MTN irq mask, 0 to enable irq).two
- * interrupts are raised if both
- * DI_INTR_CTRL[16] and DI_INTR_CTRL[17] are 0
- */
-#if 0
- data32 = Rd(DI_INTR_CTRL);
- if (((data32 & 0x1) &&
- ((ppre->enable_mtnwr == 0) || (data32 & 0x2))) ||
- (ppre->pre_de_clear_flag == 2)) {
- dimv3_RDMA_WR(DI_INTR_CTRL, data32);
- }
-#endif
- di_pre_wait_irq_set(false);
- /*finish to count timer*/
- div3_tout_contr(eDI_TOUT_CONTR_FINISH, &pre->tout);
- spin_lock_irqsave(&plistv3_lock, flags);
-
- dimv3_pre_de_done_buf_config(pch, false);
-
- pre->flg_int_done = 0;
-
- dprev3_recyc(pre->curr_ch);
- dprev3_vdoing(pre->curr_ch);
-
- spin_unlock_irqrestore(&plistv3_lock, flags);
-#if 0
- ppre = get_pre_stru(pre->curr_ch);
-
- if (ppre->field_count_for_cont == 1) {
- usleep_range(2000, 2001);
- pr_info("delay 1ms\n");
- }
-#endif
-
- ret = eDI_WAIT_INT_HAVE_INT;
-
- } else {
- /*check if timeout:*/
- if (div3_tout_contr(eDI_TOUT_CONTR_CHECK, &pre->tout)) {
- di_pre_wait_irq_set(false);
- /*return K_DO_R_FINISH;*/
- ret = eDI_WAIT_INT_TIME_OUT;
- }
- }
- /*debug:*/
- if (dbgv3_first_cnt_pre)
- dbgv3_first_frame("ch[%d],w_int[%d]\n", pre->curr_ch, ret);
-
- return ret;
-}
-
-unsigned int dprev3_mtotal_wait_int(void *data)
-{
- enum eDI_WAIT_INT wret;
- unsigned int ret = K_DO_R_NOT_FINISH;
-
- wret = div3_pre_wait_int(NULL);
- switch (wret) {
- case eDI_WAIT_INT_NEED_WAIT:
- ret = K_DO_R_NOT_FINISH;
- break;
- case eDI_WAIT_INT_HAVE_INT:
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
- break;
- case eDI_WAIT_INT_TIME_OUT:
- ret = K_DO_R_FINISH;
- break;
- }
- return ret;
-}
-
-void dprev3_mtotal_timeout_contr(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
- struct di_ch_s *pch;
-
- pch = get_chdata(pre->curr_ch);
- if (!pch) {
- PR_ERR("%s:no pch\n", __func__);
- return;
- }
- /*move from di_pre_trigger_work*/
- if (dimp_get(eDI_MP_di_dbg_mask) & 4)
- dimv3_dump_mif_size_state(pre->pres, pre->psts);
-
-
- dimhv3_enable_di_pre_mif(false, dimp_get(eDI_MP_mcpre_en));
- if (div3_get_dts_nrds_en())
- dimv3_nr_ds_hw_ctrl(false);
- pre->pres->pre_de_irq_timeout_count++;
-
- pre->pres->pre_de_busy = 0;
- pre->pres->pre_de_clear_flag = 2;
- if ((dimp_get(eDI_MP_di_dbg_mask) & 0x2)) {
- PR_INF("ch[%d]*****wait %d timeout 0x%x(%d ms)*****\n",
- pre->curr_ch,
- pre->pres->field_count,
- Rd(DI_INTR_CTRL),
- (unsigned int)(curv3_to_msecs() -
- pre->pres->irq_time[1]));
- }
- /*******************************/
-
- /*******************************/
- dimv3_pre_de_done_buf_config(pch, true);
-
- dprev3_recyc(pre->curr_ch);
- dprev3_vdoing(pre->curr_ch);
- /*******************************/
- /*dpre_recyc(pre->curr_ch);*/
-}
-
-unsigned int dprev3_mtotal_timeout(void *data)
-{
- ulong flags = 0;
-
- spin_lock_irqsave(&plistv3_lock, flags);
- dprev3_mtotal_timeout_contr();
- spin_unlock_irqrestore(&plistv3_lock, flags);
-
- return K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
-}
-
-const struct do_table_ops_s prv3_mode_total[] = {
- /*fix*/
- [K_DO_TABLE_ID_PAUSE] = {
- .id = K_DO_TABLE_ID_PAUSE,
- .mark = 0,
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "pause",
- },
- [K_DO_TABLE_ID_STOP] = {
- .id = K_DO_TABLE_ID_STOP,
- .mark = 0,
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "stop",
- },
- /******************/
- [K_DO_TABLE_ID_START] = { /*eDI_PRE_MT_CHECK*/
- .id = K_DO_TABLE_ID_START,
- .mark = 0,
- .con = NULL,
- .do_op = dprev3_mtotal_check,
- .do_stop_op = NULL,
- .name = "start-check",
- },
- [eDI_PRE_MT_SET] = {
- .id = eDI_PRE_MT_SET,
- .mark = 0,
- .con = NULL,
- .do_op = dprev3_mtotal_set,
- .do_stop_op = NULL,
- .name = "set",
- },
- [eDI_PRE_MT_WAIT_INT] = {
- .id = eDI_PRE_MT_WAIT_INT,
- .mark = 0,
- .con = NULL,
- .do_op = dprev3_mtotal_wait_int,
- .do_stop_op = NULL,
- .name = "wait_int",
- },
- [eDI_PRE_MT_TIME_OUT] = {
- .id = eDI_PRE_MT_TIME_OUT,
- .mark = 0,
- .con = NULL,
- .do_op = dprev3_mtotal_timeout,
- .do_stop_op = NULL,
- .name = "timeout",
- }
-};
-
-/****************************
- *
- * mode for bypass all
- *
- ****************************/
-unsigned int dpre_mbypass_set(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- struct di_ch_s *pch;
- unsigned int ret = K_DO_R_NOT_FINISH;
-
- pch = get_chdata(pre->curr_ch);
-
- if ((prev3_run_flag == DI_RUN_FLAG_RUN) ||
- (prev3_run_flag == DI_RUN_FLAG_STEP)) {
- if (prev3_run_flag == DI_RUN_FLAG_STEP)
- prev3_run_flag = DI_RUN_FLAG_STEP_DONE;
- /*dim_print("%s:\n", __func__);*/
- dim_pre_de_buf_config_bypass(pch->ch_id);
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
-
- dimv3_dbg_pre_cnt(pre->curr_ch, "x");
- }
-
- return ret;
-}
-
-const struct do_table_ops_s pr_mode_bypass[] = {
- /*fix*/
- [K_DO_TABLE_ID_PAUSE] = {
- .id = K_DO_TABLE_ID_PAUSE,
- .mark = 0,
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "pause",
- },
- [K_DO_TABLE_ID_STOP] = {
- .id = K_DO_TABLE_ID_STOP,
- .mark = 0,
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "stop",
- },
- /******************/
- [K_DO_TABLE_ID_START] = { /*eDI_PRE_MT_CHECK*/
- .id = K_DO_TABLE_ID_START,
- .mark = 0,
- .con = NULL,
- .do_op = dpre_mbypass_set,
- .do_stop_op = NULL,
- .name = "bypass_set",
- }
-};
-
-/********************************************************************
- *
- * mode for p as i mode
- *
- ********************************************************************/
-enum eDI_PRE_MP {
- eDI_PRE_MP_CHECK = K_DO_TABLE_ID_START,
- eDI_PRE_MP_SET,
- eDI_PRE_MP_WAIT_INT,
- eDI_PRE_MP_TIME_OUT,
- eDI_PRE_MP_CHECK2,
- eDI_PRE_MP_SET2,
- eDI_PRE_MP_WAIT_INT2,
- eDI_PRE_MP_TIME_OUT2,
-};
-
-static unsigned int dpre_mp_check(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- unsigned int ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);//K_DO_R_NOT_FINISH;
-
- if ((prev3_run_flag == DI_RUN_FLAG_RUN) ||
- (prev3_run_flag == DI_RUN_FLAG_STEP)) {
- if (prev3_run_flag == DI_RUN_FLAG_STEP)
- prev3_run_flag = DI_RUN_FLAG_STEP_DONE;
- /*dim_print("%s:\n", __func__);*/
- if (dim_pre_de_buf_config_p_asi_t(pre->curr_ch)) {
- /*pre->flg_wait_int = false;*/
- /*pre_p_asi_set_next(pre->curr_ch);*/
- ret = K_DO_R_FINISH;
- } else {
- /*pre->flg_wait_int = false;*/
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
- }
- dimv3_dbg_pre_cnt(pre->curr_ch, "x");
- }
-
- return ret;
-}
-
-static unsigned int dpre_mp_check2(void *data)
-{
- struct di_hpre_s *pre = get_hw_pre();
- unsigned int ret = K_DO_R_NOT_FINISH;
-
- if (dim_pre_de_buf_config_p_asi_b(pre->curr_ch)) {
- /*pre->flg_wait_int = false;*/
- ret = K_DO_R_FINISH;
- }
- #if 0
- else {
- PR_ERR("%s:not second?ch[%d]\n", __func__, pre->curr_ch);
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
- }
- #endif
-
- return ret;
-}
-
-static unsigned int dpre_mp_wait_int(void *data)
-{
- enum eDI_WAIT_INT wret;
- unsigned int ret = K_DO_R_NOT_FINISH;
-
- wret = div3_pre_wait_int(NULL);
- switch (wret) {
- case eDI_WAIT_INT_NEED_WAIT:
- ret = K_DO_R_NOT_FINISH;
- break;
- case eDI_WAIT_INT_HAVE_INT:
- ret = K_DO_R_JUMP(eDI_PRE_MP_CHECK2);
- break;
- case eDI_WAIT_INT_TIME_OUT:
- ret = K_DO_R_FINISH;
- break;
- }
- return ret;
-}
-
-static unsigned int dpre_mp_wait_int2(void *data)
-{
- enum eDI_WAIT_INT wret;
- unsigned int ret = K_DO_R_NOT_FINISH;
-
- wret = div3_pre_wait_int(NULL);
- switch (wret) {
- case eDI_WAIT_INT_NEED_WAIT:
- ret = K_DO_R_NOT_FINISH;
- break;
- case eDI_WAIT_INT_HAVE_INT:
- ret = K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
- break;
- case eDI_WAIT_INT_TIME_OUT:
- ret = K_DO_R_FINISH;
- break;
- }
- return ret;
-}
-
-static unsigned int dpre_mp_timeout(void *data)
-{
- dprev3_mtotal_timeout_contr();
-
- return K_DO_R_FINISH;
-}
-
-static unsigned int dpre_mp_timeout2(void *data)
-{
- dprev3_mtotal_timeout_contr();
-
- return K_DO_R_JUMP(K_DO_TABLE_ID_STOP);
-}
-
-const struct do_table_ops_s pre_mode_prog_as_i[] = {
- /*fix*/
- [K_DO_TABLE_ID_PAUSE] = {
- .id = K_DO_TABLE_ID_PAUSE,
- .mark = 0,
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "pause",
- },
- [K_DO_TABLE_ID_STOP] = {
- .id = K_DO_TABLE_ID_STOP,
- .mark = 0, /*stop / pause*/
- .con = NULL,
- .do_op = NULL,
- .do_stop_op = NULL,
- .name = "stop",
- },
- /******************/
- [K_DO_TABLE_ID_START] = { /*eDI_PRE_MP_CHECK*/
- .id = K_DO_TABLE_ID_START,
- .mark = 0, /*stop / pause*/
- .con = NULL,
- .do_op = dpre_mp_check,
- .do_stop_op = NULL,
- .name = "start-check",
- },
- [eDI_PRE_MP_SET] = {
- .id = eDI_PRE_MP_SET,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dprev3_mtotal_set,
- .do_stop_op = NULL,
- .name = "pset",
- },
- [eDI_PRE_MP_WAIT_INT] = {
- .id = eDI_PRE_MP_WAIT_INT,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dpre_mp_wait_int,
- .do_stop_op = NULL,
- .name = "pwait_int",
- },
- [eDI_PRE_MP_TIME_OUT] = {
- .id = eDI_PRE_MP_TIME_OUT,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dpre_mp_timeout,
- .do_stop_op = NULL,
- .name = "ptimeout",
- },
- /******/
- [eDI_PRE_MP_CHECK2] = { /*eDI_PRE_MP_CHECK2*/
- .id = eDI_PRE_MP_CHECK2,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dpre_mp_check2,
- .do_stop_op = NULL,
- .name = "start-check",
- },
- [eDI_PRE_MP_SET2] = {
- .id = eDI_PRE_MP_SET2,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dprev3_mtotal_set,
- .do_stop_op = NULL,
- .name = "psetp2",
- },
- [eDI_PRE_MP_WAIT_INT2] = {
- .id = eDI_PRE_MP_WAIT_INT2,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dpre_mp_wait_int2,
- .do_stop_op = NULL,
- .name = "pwait_int2",
- },
- [eDI_PRE_MP_TIME_OUT2] = {
- .id = eDI_PRE_MP_TIME_OUT2,
- .mark = 0, /*stop / pause*/
- .con = NULL, /*condition*/
- .do_op = dpre_mp_timeout2,
- .do_stop_op = NULL,
- .name = "ptimeout2",
- }
-
-};
-
-void prev3_mode_setting(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- if (pre->pre_st != eDI_PRE_ST4_DO_TABLE)
- return;
-
- dov3_table_working(&pre->sdt_mode);
-}
-
-/*--------------------------*/
-#if 0
-enum eDI_WORK_MODE pre_cfg_count_mode(unsigned int ch, struct vframe_s *vframe)
-{
- enum eDI_WORK_MODE pmode;
-
- if (isv3_bypass2(vframe, ch)) {
- pmode = eDI_WORK_MODE_bypass_all;
- return pmode;
- }
-
- if (COM_ME(vframe->type, VIDTYPE_INTERLACE)) {
- /*interlace:*/
- pmode = eDI_WORK_MODE_i;
- return pmode;
- }
-
- if (dimp_get(eDI_MP_prog_proc_config) & 0x10)
- pmode = eDI_WORK_MODE_p_as_p;
- else if (is_from_vdin(vframe))
- pmode = eDI_WORK_MODE_p_use_ibuf;
- else
- pmode = eDI_WORK_MODE_p_as_i;
-
- return pmode;
-}
-#endif
-unsigned int dprev3_check_mode(unsigned int ch)
-{
- //struct vframe_s *vframe;
-// unsigned int mode;
- enum eDI_WORK_MODE pmode;
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm;
-
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in)
- return eDI_WORK_MODE_NONE;
-
- //vframe = pdvfm->vfm_in;
-
- if (pdvfm->wmode.is_bypass) {
- pmode = eDI_WORK_MODE_bypass_all;
- return pmode;
- }
-
- if (pdvfm->wmode.is_i) {
- /*interlace:*/
- pmode = eDI_WORK_MODE_i;
- return pmode;
- }
-
- #if 0
- if (dimp_get(eDI_MP_prog_proc_config) & 0x10)
- pmode = eDI_WORK_MODE_p_as_p;
- else if (is_from_vdin(vframe) ||
- (dimp_get(eDI_MP_use_2_interlace_buff) & 0x02))
- pmode = eDI_WORK_MODE_p_use_ibuf;
- else
- pmode = eDI_WORK_MODE_p_as_i;
- #else
- if (pdvfm->wmode.p_as_i)
- pmode = eDI_WORK_MODE_p_as_i;
- else if (pdvfm->wmode.is_vdin)
- pmode = eDI_WORK_MODE_p_as_p;
- else
- pmode = eDI_WORK_MODE_p_use_ibuf;
- #endif
- return pmode;
-
-}
-
-/*--------------------------*/
-bool dprev3_step4_idle(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
- bool reflesh = false;
- unsigned int ch;
-
- ch = pre->curr_ch;
- if (!pw_try_sw_ch_next_pre(ch))
- return false;
-
- if (pre->idle_cnt >= DI_CHANNEL_NUB) {
- pre->idle_cnt = 0;
- return false;
- }
- pre->pres = get_pre_stru(pre->curr_ch);
- pre->psts = get_post_stru(pre->curr_ch);
-
- /*state*/
- pre->pre_st++;/*tmp*/
- reflesh = true;
-
- return reflesh;
-}
-
-bool dprev3_step4_check(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
- bool reflesh = false;
- unsigned int mode;
-
- /*get vframe and select mode
- * now: fix use total table
- */
-
- mode = dprev3_check_mode(pre->curr_ch);
-
- if (mode == eDI_WORK_MODE_NONE) {
- pre->pre_st--;
- pre->idle_cnt++;
- return true;
- }
- pre->idle_cnt = 0;
- if (mode == eDI_WORK_MODE_p_as_i) {
- dov3_table_init(&pre->sdt_mode,
- &pre_mode_prog_as_i[0],
- ARRAY_SIZE(pre_mode_prog_as_i));
-
- } else if (mode == eDI_WORK_MODE_bypass_all) {
- dov3_table_init(&pre->sdt_mode,
- &pr_mode_bypass[0],
- ARRAY_SIZE(pr_mode_bypass));
-
- } else {
- dov3_table_init(&pre->sdt_mode,
- &prv3_mode_total[0],
- ARRAY_SIZE(prv3_mode_total));
- }
- dov3_talbe_cmd(&pre->sdt_mode, eDO_TABLE_CMD_START);
-
- /*state*/
- pre->pre_st++;
- reflesh = true;
-
- return reflesh;
-}
-
-bool dprev3_step4_do_table(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
- bool reflesh = false;
-
- if (dov3_table_is_crr(&pre->sdt_mode, K_DO_TABLE_ID_STOP)) {
- pre->pre_st = eDI_PRE_ST4_IDLE;
- reflesh = true;
- }
- return reflesh;
-}
-
-const struct di_func_tab_s div3_pre_func_tab4[] = {
- {eDI_PRE_ST4_EXIT, NULL},
- {eDI_PRE_ST4_IDLE, dprev3_step4_idle},
- {eDI_PRE_ST4_CHECK, dprev3_step4_check},
- {eDI_PRE_ST4_DO_TABLE, dprev3_step4_do_table},
-};
-
-const char * const dprev3_state_name4[] = {
- "EXIT",
- "IDLE", /*swith to next channel?*/
- "CHECK",
- "DO_TABLE"
-};
-
-const char *dprev3_state4_name_get(enum eDI_PRE_ST4 state)
-{
- if (state > eDI_PRE_ST4_DO_TABLE)
- return "nothing";
-
- return dprev3_state_name4[state];
-}
-
-bool dprev3_process_step4(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
- enum eDI_PRE_ST4 pre_st = pre->pre_st;
- ulong flags = 0;
-
- if (pre_st > eDI_PRE_ST4_EXIT) {
- spin_lock_irqsave(&plistv3_lock, flags);
- dimv3_recycle_post_back(pre->curr_ch);
- dprev3_recyc(pre->curr_ch);
- dprev3_vdoing(pre->curr_ch);
- spin_unlock_irqrestore(&plistv3_lock, flags);
- }
- if ((pre_st <= eDI_PRE_ST4_DO_TABLE) &&
- div3_pre_func_tab4[pre_st].func) {
- return div3_pre_func_tab4[pre_st].func();
- }
-
- return false;
-}
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pre.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_PRE_H__
-#define __DI_PRE_H__
-
-void dprev3_process(void);
-
-void dprev3_init(void);
-
-const char *dprev3_state_name_get(enum eDI_PRE_ST state);
-void dprev3_dbg_f_trig(unsigned int cmd);
-void prev3_vinfo_set(unsigned int ch, struct di_in_inf_s *pinf);
-
-unsigned int isv3_vinfo_change(unsigned int ch);
-bool dprev3_can_exit(unsigned int ch);
-//no use bool is_bypass_i_p(void);
-bool dimv3_bypass_detect(unsigned int ch, struct vframe_s *vfm);
-
-void prev3_mode_setting(void);
-bool dprev3_process_step4(void);
-const char *dprev3_state4_name_get(enum eDI_PRE_ST4 state);
-
-#endif /*__DI_PRE_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pre_hw.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-
-#include "di_data_l.h"
-#include "di_data.h"
-#include "di_dbg.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_prc.h"
-#include "di_pre.h"
-
-#include "nr_downscale.h"
-#include "register.h"
-
-#if 0
-/****************************************
- * 1. copy curr to last
- * 2. set curr
- ****************************************/
-void prev3_vinfo_set(unsigned int ch,
- struct vframe_s *ori_vframe)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- struct di_vinfo_s *vc = &pre->vinf_curr;
- struct di_vinfo_s *vl = &pre->vinf_lst;
-
- memcpy(vl, vc, sizeof(struct di_vinfo_s));
-
- vc->ch = ch;
- vc->vtype = ori_vframe->type;
- vc->src_type = ori_vframe->source_type;
- vc->trans_fmt = ori_vframe->trans_fmt;
-
- if (COM_ME(ori_vframe->type, VIDTYPE_COMPRESS)) {
- vc->h = ori_vframe->compWidth;
- vc->v = ori_vframe->compHeight;
- } else {
- vc->h = ori_vframe->width;
- vc->v = ori_vframe->height;
- }
-}
-
-/****************************************
- * compare current vframe info with last
- * return
- * 0. no change
- * 1. video format channge
- * 2. scan mode channge?
- ****************************************/
-unsigned int isv3_vinfo_change(unsigned int ch)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- struct di_vinfo_s *vc = &pre->vinf_curr;
- struct di_vinfo_s *vl = &pre->vinf_lst;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- unsigned int ret = 0;
-
- if (vc->src_type != vl->src_type ||
- !COM_M(DI_VFM_T_MASK_CHANGE, vc->vtype, vl->vtype) ||
- vc->v != vl->v ||
- vc->h != vl->h ||
- vc->trans_fmt != vl->trans_fmt) {
- /* video format changed */
- ret = 1;
- } else if (!COM_M(VIDTYPE_VIU_FIELD, vc->vtype, vl->vtype))
- /* just scan mode changed */
- ret = 2;
-
- if (ret) {
- dimv3_print(
- "%s:ch[%d]: %dth source change 2: 0x%x/%d/%d/%d=>0x%x/%d/%d/%d\n",
- __func__,
- ch,
- /*jiffies_to_msecs(jiffies_64),*/
- ppre->in_seq,
- vl->vtype,
- vl->h,
- vl->v,
- vl->src_type,
- vc->vtype,
- vc->h,
- vc->v,
- vc->src_type);
- }
-
- return ret;
-}
-#endif
-/****************************************
- * 1. copy curr to last
- * 2. set curr
- ****************************************/
-void prev3_vinfo_set(unsigned int ch, struct di_in_inf_s *pinf)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- struct di_in_inf_s *vc = &pre->vinf_curr;
- struct di_in_inf_s *vl = &pre->vinf_lst;
-
- memcpy(vl, vc, sizeof(struct di_in_inf_s));
-
- *vc = *pinf;
-}
-
-/****************************************
- * compare current vframe info with last
- * return
- * 0. no change
- * 1. video format channge
- * 2. scan mode channge?
- ****************************************/
-unsigned int isv3_vinfo_change(unsigned int ch)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- struct di_in_inf_s *vc = &pre->vinf_curr;
- struct di_in_inf_s *vl = &pre->vinf_lst;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- unsigned int ret = 0;
-
- if (vc->src_type != vl->src_type ||
- !COM_M(DI_VFM_T_MASK_CHANGE, vc->vtype_ori, vl->vtype_ori) ||
- vc->w != vl->w ||
- vc->h != vl->h ||
- vc->trans_fmt != vl->trans_fmt) {
- /* video format changed */
- ret = 1;
- } else if (!COM_M(VIDTYPE_VIU_FIELD, vc->vtype_ori, vl->vtype_ori))
- /* just scan mode changed */
- ret = 2;
-
- if (ret) {
- dimv3_print(
- "%s:ch[%d]: %dth source change 2: 0x%x/%d/%d/%d=>0x%x/%d/%d/%d\n",
- __func__,
- ch,
- /*jiffies_to_msecs(jiffies_64),*/
- ppre->in_seq,
- vl->vtype_ori,
- vl->h,
- vl->w,
- vl->src_type,
- vc->vtype_ori,
- vc->h,
- vc->w,
- vc->src_type);
- }
-
- return ret;
-}
-
-unsigned char isv3_source_change_dfvm(struct dim_dvfm_s *plstdvfm,
- struct dim_dvfm_s *pdvfm,
- unsigned int ch)
-{
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
-
-#define VFRAME_FORMAT_MASK \
- (VIDTYPE_VIU_422 | VIDTYPE_VIU_SINGLE_PLANE | VIDTYPE_VIU_444 | \
- VIDTYPE_MVC)
-
-#if 0
- if ((ppre->cur_width != vframe->width) ||
- (ppre->cur_height != vframe->height) ||
- (((ppre->cur_inp_type & VFRAME_FORMAT_MASK) !=
- (vframe->type & VFRAME_FORMAT_MASK)) &&
- (!is_handle_prog_frame_as_interlace(vframe))) ||
- (ppre->cur_source_type != vframe->source_type)) {
- /* video format changed */
- return 1;
- } else if (((ppre->cur_prog_flag != is_progressive(vframe)) &&
- (!is_handle_prog_frame_as_interlace(vframe))) ||
- ((ppre->cur_inp_type & VIDTYPE_VIU_FIELD) !=
- (vframe->type & VIDTYPE_VIU_FIELD))
- ) {
- /* just scan mode changed */
- if (!ppre->force_interlace)
- pr_dbg("DI I<->P.\n");
- return 2;
- }
- return 0;
-#endif
- /*********************************************/
-// struct dim_dvfm_s *plstdvfm = &ppre->lst_dvfm;
- if (plstdvfm->in_inf.h != pdvfm->in_inf.h ||
- plstdvfm->in_inf.w != pdvfm->in_inf.w ||
- !COM_M(VFRAME_FORMAT_MASK,
- plstdvfm->wmode.vtype,
- pdvfm->wmode.vtype) ||
- plstdvfm->in_inf.src_type != pdvfm->in_inf.src_type) {
- /* video format changed */
- return 1;
- } else if (plstdvfm->wmode.is_i != pdvfm->wmode.is_i ||
- !COM_M(VIDTYPE_VIU_FIELD,
- plstdvfm->wmode.vtype,
- pdvfm->wmode.vtype)) {
- /* just scan mode changed */
- if (!ppre->force_interlace)
- pr_dbg("DI I<->P.\n");
- return 2;
- }
-
- return 0;
-}
-
-void dimv3_set_pre_dfvm(struct dim_dvfm_s *plstdvfm,
- struct dim_dvfm_s *pdvfm)
-{
-// struct di_pre_stru_s *ppre = get_pre_stru(ch);
-// struct dim_dvfm_s *plstdvfm = &ppre->lst_dvfm;
-
- plstdvfm->in_inf = pdvfm->in_inf;
- plstdvfm->wmode = pdvfm->wmode;
-}
-
-void dimv3_set_pre_dfvm_last_bypass(struct di_ch_s *pch)
-{
- struct dim_dvfm_s *plstdvfm;
-
- plstdvfm = &pch->lst_dvfm;
- plstdvfm->in_inf.h = 0;
- plstdvfm->in_inf.w = 0;
-}
-#if 0
-bool dimv3_bypass_detect(unsigned int ch, struct vframe_s *vfm)
-{
- bool ret = false;
-
- if (!vfm)
- return ret;
- prev3_vinfo_set(ch, vfm);
- if (isv3_vinfo_change(ch)) {
- if (!isv3_bypass2(vfm, ch)) {
- setv3_bypass2_complete(ch, false);
- PR_INF("%s:\n", __func__);
- /*task_send_ready();*/
- taskv3_send_cmd(LCMD1(eCMD_CHG, ch));
- ret = true;
- }
- }
- return ret;
-}
-#endif
-/****************************************
- *
- ****************************************/
-static void hpre_prob_hw(struct di_hpre_s *hpre)
-{
-
-}
-
-static void hpre_reg_var(struct di_hpre_s *hpre)
-{
-#if 0
- struct di_pre_stru_s *ppre;
-
- set_h_ppre(ch);
- /*cfg for reg*/
- dimv3_tst_4k_reg_val();
-
- /*clear pre*/
- ppre = hpre->ops.pres;
- memset(ppre, 0, sizeof(struct di_pre_stru_s));
-#endif
-}
-
-static void hpre_reg_hw(struct di_hpre_s *hpre)
-{
-
-}
-
-static void hpre_remove_hw(struct di_hpre_s *hpre)
-{
-
-}
-
-static void hpre_unreg_var(struct di_hpre_s *hpre)
-{
-
-}
-
-static void hpre_unreg_hw(struct di_hpre_s *hpre)
-{
-
-}
-
-static const struct dim_hpre_ops_s dim_hpre_ops = {
- .prob_hw = hpre_prob_hw,
- .reg_var = hpre_reg_var,
- .reg_hw = hpre_reg_hw,
- .remove_hw = hpre_remove_hw,
- .unreg_var = hpre_unreg_var,
- .unreg_hw = hpre_unreg_hw,
-
-};
-
-void hprev3_prob(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- memcpy(&pre->ops, &dim_hpre_ops, sizeof(struct dim_hpre_ops_s));
- set_h_ppre(0);
-}
-
-void hprev3_remove(void)
-{
- struct di_hpre_s *pre = get_hw_pre();
-
- memset(&pre->ops, 0, sizeof(struct dim_hpre_ops_s));
-}
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pre_hw.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_PRE_HW_H__
-#define __DI_PRE_HW_H__
-
-void hprev3_prob(void);
-void hprev3_remove(void);
-unsigned char isv3_source_change_dfvm(struct dim_dvfm_s *plstdvfm,
- struct dim_dvfm_s *pdvfm,
- unsigned int ch);
-void dimv3_set_pre_dfvm(struct dim_dvfm_s *plstdvfm,
- struct dim_dvfm_s *pdvfm);
-void dimv3_set_pre_dfvm_last_bypass(struct di_ch_s *pch);
-
-#endif /*__DI_PRE_HW_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pres.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/semaphore.h>
-#include <linux/workqueue.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/major.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/cdev.h>
-#include <linux/proc_fs.h>
-#include <linux/list.h>
-#include <linux/of_reserved_mem.h>
-#include <linux/of_irq.h>
-#include <linux/uaccess.h>
-#include <linux/of_fdt.h>
-#include <linux/cma.h>
-#include <linux/dma-contiguous.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/amlogic/iomap.h>
-#include <linux/amlogic/media/codec_mm/codec_mm.h>
-#include <linux/amlogic/cpu_version.h>
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-#include <linux/amlogic/media/canvas/canvas.h>
-#include <linux/amlogic/media/canvas/canvas_mgr.h>
-#include <linux/amlogic/media/frame_provider/tvin/tvin_v4l2.h>
-#include <linux/amlogic/media/vout/vinfo.h>
-#include <linux/amlogic/media/vout/vout_notify.h>
-#include <linux/amlogic/media/vpu/vpu.h>
-#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
-#include <linux/amlogic/media/rdma/rdma_mgr.h>
-#endif
-#include <linux/amlogic/media/video_sink/video.h>
-#include "register.h"
-#include "deinterlace.h"
-#include "deinterlace_dbg.h"
-#include "nr_downscale.h"
-
-
-#include "di_data_l.h"
-#include "di_dbg.h"
-#include "di_pps.h"
-#include "di_pre.h"
-#include "di_prc.h"
-#include "di_task.h"
-#include "di_vframe.h"
-#include "di_que.h"
-#include "di_api.h"
-#include "di_sys.h"
-#include "di_pre_hw.h"
-
-/*2018-07-18 add debugfs*/
-#include <linux/seq_file.h>
-#include <linux/debugfs.h>
-
-/*
- * add dummy buffer to pre ready queue
- */
-//static
-void addv3_dummy_vframe_type_pre(struct di_buf_s *src_buf, unsigned int ch)
-{
- struct di_buf_s *di_buf_tmp = NULL;
-
- if (!queuev3_empty(ch, QUEUE_LOCAL_FREE)) {
- di_buf_tmp = getv3_di_buf_head(ch, QUEUE_LOCAL_FREE);
- if (di_buf_tmp) {
- dimv3_print("addv3_dummy_vframe_type_pre\n");
- queuev3_out(ch, di_buf_tmp);
- di_buf_tmp->c.pre_ref_count = 0;
- di_buf_tmp->c.post_ref_count = 0;
- di_buf_tmp->c.post_proc_flag = 3;
- di_buf_tmp->c.new_format_flag = 0;
- di_buf_tmp->c.sts |= EDI_ST_DUMMY;
- if (!IS_ERR_OR_NULL(src_buf)) {
- #if 0
- memcpy(di_buf_tmp->vframe, src_buf->vframe,
- sizeof(vframe_t));
- #endif
- di_buf_tmp->c.wmode = src_buf->c.wmode;
- }
- div3_que_in(ch, QUE_PRE_READY, di_buf_tmp);
- }
- }
-}
-
-#ifdef HIS_V3
-void dimv3_pre_de_done_buf_config(struct di_ch_s *pch, bool flg_timeout)
-{
- ulong irq_flag2 = 0;
- int tmp_cur_lev;
- struct di_buf_s *post_wr_buf = NULL;
- unsigned int glb_frame_mot_num = 0;
- unsigned int glb_field_mot_num = 0;
-// struct di_ch_s *pch;
-// struct dim_dvfm_s *pdvfm;
- unsigned int channel = pch->ch_id;
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- dimv3_dbg_pre_cnt(channel, "d1");
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_DONEB,
- channel, ppre->in_seq);/*dbg*/
- if (ppre->di_wr_buf) {
- //dim_tr_ops.pre_ready(ppre->di_wr_buf->vframe->omx_index);
- if (ppre->pre_throw_flag > 0) {
- ppre->di_wr_buf->c.throw_flag = 1;
- ppre->pre_throw_flag--;
- } else {
- ppre->di_wr_buf->c.throw_flag = 0;
- }
-
- ppre->di_post_wr_buf = ppre->di_wr_buf;
- post_wr_buf = ppre->di_post_wr_buf;
-
- if (post_wr_buf && !ppre->cur_prog_flag &&
- !flg_timeout) {/*ary: i mode ?*/
- dimv3_read_pulldown_info(&glb_frame_mot_num,
- &glb_field_mot_num);
- if (dimp_get(eDI_MP_pulldown_enable))
- /*pulldown_detection*/
- get_ops_pd()->detection(&post_wr_buf->c.pd_config,
- ppre->mtn_status,
- dimv3_get_overturn(),
- /*ppre->di_inp_buf->vframe*/
- &ppre->dvfm->vframe);
- /*if (combing_fix_en)*/
- //if (di_mpr(combing_fix_en)) {
- if (ppre->combing_fix_en) {
- tmp_cur_lev /*cur_lev*/
- = get_ops_mtn()->adaptive_combing_fixing(
- ppre->mtn_status,
- glb_field_mot_num,
- glb_frame_mot_num,
- dimp_get(eDI_MP_di_force_bit_mode));
- dimp_set(eDI_MP_cur_lev, tmp_cur_lev);
- }
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
- get_ops_nr()->adaptive_cue_adjust(
- glb_frame_mot_num,
- glb_field_mot_num);
- dimv3_pulldown_info_clear_g12a();
- }
-
- if (ppre->cur_prog_flag) { /*progressive*/
- if (ppre->prog_proc_type == 0) { /*p as i */
- /* di_mem_buf_dup->vfrme
- * is either local vframe,
- * or bot field of vframe from in_list
- */
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p
- = ppre->di_chan2_buf_dup_p;
- ppre->di_chan2_buf_dup_p
- = ppre->di_wr_buf;
-
- } else {
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- /*recycle the progress throw buffer*/
- if (ppre->di_wr_buf->c.throw_flag) {
- ppre->di_wr_buf->
- c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
-
- } else {
- ppre->di_mem_buf_dup_p
- = ppre->di_wr_buf;
- }
-
- }
-
- ppre->di_wr_buf->c.seq
- = ppre->pre_ready_seq++;
- ppre->di_wr_buf->c.post_ref_count = 0;
- ppre->di_wr_buf->c.left_right
- = ppre->left_right;
- if (ppre->source_change_flag) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- ppre->source_change_flag = 0;
- } else {
- ppre->di_wr_buf->c.new_format_flag = 0;
- }
- if (di_bypass_state_get(channel) == 1) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- /*bypass_state = 0;*/
- di_bypass_state_set(channel, false);
-
- }
- if (ppre->di_post_wr_buf)
- div3_que_in(channel, QUE_PRE_READY,
- ppre->di_post_wr_buf);
-
- if (ppre->di_wr_buf) {
- ppre->di_post_wr_buf = NULL;
- ppre->di_wr_buf = NULL;
- }
- } else {
- /*i mode*/
- ppre->di_mem_buf_dup_p->c.pre_ref_count = 0;
- ppre->di_mem_buf_dup_p = NULL;
- if (ppre->di_chan2_buf_dup_p) {
- ppre->di_mem_buf_dup_p =
- ppre->di_chan2_buf_dup_p;
-
- }
- ppre->di_chan2_buf_dup_p = ppre->di_wr_buf;
-
- if (ppre->source_change_flag) {
- /* add dummy buf, will not be displayed */
- addv3_dummy_vframe_type_pre(post_wr_buf,
- channel);
- }
- ppre->di_wr_buf->c.seq = ppre->pre_ready_seq++;
- ppre->di_wr_buf->c.left_right = ppre->left_right;
- ppre->di_wr_buf->c.post_ref_count = 0;
-
- if (ppre->source_change_flag) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- ppre->source_change_flag = 0;
- } else {
- ppre->di_wr_buf->c.new_format_flag = 0;
- }
- if (di_bypass_state_get(channel) == 1) {
- ppre->di_wr_buf->c.new_format_flag = 1;
- /*bypass_state = 0;*/
- di_bypass_state_set(channel, false);
-
- }
-
- if (ppre->di_post_wr_buf)
- div3_que_in(channel, QUE_PRE_READY,
- ppre->di_post_wr_buf);
-
- dimv3_print("%s: %s[%d] => pre_ready_list\n", __func__,
- vframe_type_name[ppre->di_wr_buf->type],
- ppre->di_wr_buf->index);
-
- if (ppre->di_wr_buf) {
- ppre->di_post_wr_buf = NULL;
-
- ppre->di_wr_buf = NULL;
- }
- }
- }
-
- if (ppre->di_inp_buf) {
- di_lock_irqfiq_save(irq_flag2);
- queuev3_in(channel, ppre->di_inp_buf, QUEUE_RECYCLE);
- ppre->di_inp_buf = NULL;
- di_unlock_irqfiq_restore(irq_flag2);
- }
- dimv3_print("%s\n", __func__);
- #ifdef HIS_V3
- if (ppre->dvfm) { /*ary tmp : dvfm recycle*/
- pch = get_chdata(channel);
- pdvfm = dvfmv3_get(pch, QUED_T_PRE);
- if (ppre->dvfm->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- ppre->dvfm->index,
- pdvfm->index);
- return;
- }
-
- qued_ops.in(pch, QUED_T_RECYCL, ppre->dvfm->index);
- ppre->dvfm = NULL;
- } else{
- dimv3_print("%s:warn:no dvfm\n", __func__);
- }
- #else
-
- #endif
- dimv3_ddbg_mod_save(eDI_DBG_MOD_PRE_DONEE,
- channel, ppre->in_seq); /*dbg*/
-
- dimv3_dbg_pre_cnt(channel, "d2");
-}
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_pres.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_PRES_H__
-#define __DI_PRES_H__
-
-void dimv3_pre_de_done_buf_config(struct di_ch_s *pch,
- bool flg_timeout);
-void addv3_dummy_vframe_type_pre(struct di_buf_s *src_buf, unsigned int ch);
-
-void div3_vf_l_put(struct vframe_s *vf, struct di_ch_s *pch);
-struct vframe_s *div3_vf_l_get(struct di_ch_s *pch);
-struct vframe_s *div3_vf_l_peek(struct di_ch_s *pch);
-
-#endif /*__DI_PRES_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_que.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-#include <linux/kfifo.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/debug_ftrace_ramoops.h>
-#include "deinterlace.h"
-
-#include "di_data_l.h"
-#include "di_que.h"
-#include "di_vframe.h"
-
-#include "di_prc.h"
-
-#ifdef DIM_DEBUG_QUE_ERR
-static void dim_dbg_que(union dim_dbg_que_u *dbg)
-{
- struct di_dbg_que_s *pd = di_get_dbg_que(0);
- unsigned int pos;
- union dim_dbg_que_u ldbg;
-
- if (!pd->en)
- return;
- pd->cnt++;
-
- if (pd->cnt > 254)
- pd->cnt = 0;
- pos = pd->pos;
- ldbg = *dbg;
- pd->que_inf[pos].u32 = ldbg.u32;
- pd->que_inf[pos].b.cnt = pd->cnt;
- pd->pos++;
-
- if (pd->pos >= DIM_DBG_QUE_SIZE)
- pd->pos = 0;
-
-}
-
-void dim_dbg_que_int(void)
-{
- struct di_dbg_que_s *pd = di_get_dbg_que(0);
-
- memset(pd, 0, sizeof(*pd));
- pd->en = 1;
-}
-
-void dim_dbg_que_disable(void)
-{
- struct di_dbg_que_s *pd = di_get_dbg_que(0);
-
- pd->en = 0;
-}
-
-void dim_dbg_que_out(void)
-{
- struct di_dbg_que_s *pd = di_get_dbg_que(0);
- int i;
-
- for (i = 0; i < DIM_DBG_QUE_SIZE; i++)
- pr_info("%d:0x%x\n", i, pd->que_inf[i].u32);
-
- memset(pd, 0, sizeof(*pd));
- pd->en = 1;
-}
-
-void trace_buf(struct di_buf_s *di_buf,
- unsigned int q_api, unsigned int q_index,
- unsigned int tag)
-{
- union dim_dbg_que_u dbg;
-
- if (q_index != QUE_POST_DOING &&
- q_index != QUE_POST_NOBUF)
- return;
-
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index)&0xff;
- dbg.b.que_api = q_api;
- dbg.b.que_index = q_index;
-
- pstore_ftrace_io_tag(tag, dbg.u32);
-}
-#endif /*DIM_DEBUG_QUE_ERR*/
-
-/*********************************************
- *also see enum QUE_TYPE
- ********************************************/
-const char * const div3_name_new_que[QUE_NUB] = {
- "QUE_IN_FREE", /*0*/
- "QUE_PRE_READY", /*1*/
- "QUE_POST_FREE", /*2*/
- "QUE_POST_READY", /*3*/
- "QUE_POST_BACK", /*4*/
- "QUE_POST_DOING",
- "QUE_POST_NOBUF",
- "QUE_POST_KEEP",
- "QUE_POST_KEEP_BACK",
- "QUE_DBG",
-/* "QUE_NUB",*/
-
-};
-
-#define que_dbg dimv3_print
-
-void pwv3_queue_clear(unsigned int ch, enum QUE_TYPE qtype)
-{
- struct di_ch_s *pch = get_chdata(ch);
-
-#if 0
- if (qtype >= QUE_NUB)
- return;
-#endif
- dbg_dbg("%s:que reset t[%d]\n", __func__, qtype);
- kfifo_reset(&pch->fifo[qtype]);
-}
-
-bool pwv3_queue_in(unsigned int ch, enum QUE_TYPE qtype, unsigned int buf_index)
-{
- struct di_ch_s *pch = get_chdata(ch);
-
-#if 0
- if (qtype >= QUE_NUB)
- return false;
-#endif
- if (kfifo_in(&pch->fifo[qtype], &buf_index, sizeof(unsigned int))
- != sizeof(unsigned int))
- return false;
-#if 0
-
- /*below for debug: save in que*/
- if (qtype <= QUE_POST_RECYC) {
- if (buf_index >= MAX_POST_BUF_NUM) {
- pr_err("%s:err:overflow?[%d]\n", __func__, buf_index);
- } else {
- ppw = &pch->lpost_buf[buf_index];
- ppw->in_qtype = qtype;
- }
- }
-#endif
- return true;
-}
-
-bool pwv3_queue_out(unsigned int ch, enum QUE_TYPE qtype,
- unsigned int *buf_index)
-{
- struct di_ch_s *pch = get_chdata(ch);
- unsigned int index;
-
-#if 0
- if (qtype >= QUE_NUB)
- return false;
-#endif
- if (kfifo_out(&pch->fifo[qtype], &index, sizeof(unsigned int))
- != sizeof(unsigned int)) {
- PR_ERR("%s:ch[%d],qtye[%d],buf[%d]\n",
- __func__, ch, qtype, *buf_index);
- return false;
- }
-
- *buf_index = index;
-
- return true;
-}
-
-static bool pw_queue_peek(unsigned int ch, enum QUE_TYPE qtype,
- unsigned int *buf_index)
-{
- struct di_ch_s *pch = get_chdata(ch);
- unsigned int index;
-
-#if 0
- if (qtype >= QUE_NUB)
- return false;
-#endif
-
- if (kfifo_out_peek(&pch->fifo[qtype], &index, sizeof(unsigned int))
- != sizeof(unsigned int))
- return false;
-
- *buf_index = index;
-
- return true;
-}
-
-bool pwv3_queue_move(unsigned int ch, enum QUE_TYPE qtypef,
- enum QUE_TYPE qtypet, unsigned int *oindex)
-{
- struct di_ch_s *pch = get_chdata(ch);
- unsigned int index;
-
- /*struct di_post_buf_s *ppw;*/ /*debug only*/
-
-#if 0
- if (qtypef >= QUE_NUB || qtypet >= QUE_NUB)
- return false;
-#endif
- if (kfifo_out(&pch->fifo[qtypef], &index, sizeof(unsigned int))
- != sizeof(unsigned int)) {
- PR_ERR("qtypef[%d] is empty\n", qtypef);
- return false;
- }
- if (kfifo_in(&pch->fifo[qtypet], &index, sizeof(unsigned int))
- != sizeof(unsigned int)) {
- PR_ERR("qtypet[%d] is full\n", qtypet);
- return false;
- }
-
- *oindex = index;
-#if 0
- if (qtypet <= QUE_POST_RECYC) {
- /*below for debug: save in que*/
- if (index >= MAX_POST_BUF_NUM) {
- pr_err("%s:err:overflow?[%d]\n", __func__, index);
- } else {
- ppw = &pch->lpost_buf[index];
- ppw->in_qtype = qtypet;
- }
- }
-#endif
- return true;
-}
-
-bool pwv3_queue_empty(unsigned int ch, enum QUE_TYPE qtype)
-{
- struct di_ch_s *pch = get_chdata(ch);
-
- if (kfifo_is_empty(&pch->fifo[qtype]))
- return true;
-
- return false;
-}
-
-/**********************************************************
- *
- **********************************************************/
-int div3_que_list_count(unsigned int ch, enum QUE_TYPE qtype)
-{
- struct di_ch_s *pch = get_chdata(ch);
- unsigned int length;
-
-#if 0
- if (qtype >= QUE_NUB)
- return -1;
-#endif
- length = kfifo_len(&pch->fifo[qtype]);
- length = length / sizeof(unsigned int);
-
- return length;
-}
-
-/***************************************/
-/*outbuf : array size MAX_FIFO_SIZE*/
-/***************************************/
-bool div3_que_list(unsigned int ch, enum QUE_TYPE qtype, unsigned int *outbuf,
- unsigned int *rsize)
-{
- struct di_ch_s *pch = get_chdata(ch);
-/* unsigned int tmp[MAX_FIFO_SIZE + 1];*/
- int i;
- unsigned int index;
- bool ret = false;
-
- /*que_dbg("%s:begin\n", __func__);*/
- for (i = 0; i < MAX_FIFO_SIZE; i++)
- outbuf[i] = 0xff;
-
- if (kfifo_is_empty(&pch->fifo[qtype])) {
- que_dbg("\t%d:empty\n", qtype);
- *rsize = 0;
- return true;
- }
-
- ret = true;
- memcpy(&pch->fifo[QUE_DBG], &pch->fifo[qtype],
- sizeof(pch->fifo[qtype]));
-
-#if 0
- if (kfifo_is_empty(&pbm->fifo[QUE_DBG]))
- pr_err("%s:err, kfifo can not copy?\n", __func__);
-
-#endif
- i = 0;
- *rsize = 0;
-
- while (kfifo_out(&pch->fifo[QUE_DBG], &index, sizeof(unsigned int))
- == sizeof(unsigned int)) {
- outbuf[i] = index;
- /*pr_info("%d->%d\n",i,index);*/
- i++;
- }
- *rsize = div3_que_list_count(ch, qtype);
- #if 0 /*debug only*/
- que_dbg("%s: size[%d]\n", div3_name_new_que[qtype], *rsize);
- for (i = 0; i < *rsize; i++)
- que_dbg("%d,", outbuf[i]);
-
- que_dbg("\n");
- #endif
- /*que_dbg("finish\n");*/
-
- return ret;
-}
-
-int div3_que_is_empty(unsigned int ch, enum QUE_TYPE qtype)
-{
- struct di_ch_s *pch = get_chdata(ch);
-
-#if 0
- if (qtype >= QUE_NUB)
- return -1;
-#endif
- return kfifo_is_empty(&pch->fifo[qtype]);
-}
-
-void div3_que_init(unsigned int ch)
-{
- int i;
-
- for (i = 0; i < QUE_NUB; i++) {
- if (i == QUE_POST_KEEP ||
- i == QUE_POST_KEEP_BACK)
- continue;
- pwv3_queue_clear(ch, i);
- }
-}
-
-bool div3_que_alloc(unsigned int ch)
-{
- int i;
- int ret;
- bool flg_err;
- struct di_ch_s *pch = get_chdata(ch);
-
- /*kfifo----------------------------*/
- flg_err = 0;
- for (i = 0; i < QUE_NUB; i++) {
- ret = kfifo_alloc(&pch->fifo[i],
- sizeof(unsigned int) * MAX_FIFO_SIZE,
- GFP_KERNEL);
- if (ret < 0) {
- flg_err = 1;
- PR_ERR("%s:%d:can't get kfifo\n", __func__, i);
- break;
- }
- pch->flg_fifo[i] = 1;
- }
-#if 0
- /*canvas-----------------------------*/
- canvas_alloc();
-#endif
-/* pdp_clear();*/
-
- if (!flg_err) {
- /*pbm->flg_fifo = 1;*/
- PR_INF("%s:ok\n", __func__);
- ret = true;
- } else {
- div3_que_release(ch);
- ret = false;
- }
-
- return ret;
-}
-
-void div3_que_release(unsigned int ch)
-{
- struct di_ch_s *pch = get_chdata(ch);
- int i;
-
-/* canvas_release();*/
- for (i = 0; i < QUE_NUB; i++) {
- if (pch->flg_fifo[i]) {
- kfifo_free(&pch->fifo[i]);
- pch->flg_fifo[i] = 0;
- }
- }
-
- PR_INF("%s:ok\n", __func__);
-}
-
-/********************************************
- *get di_buf from index that same in que
- * (di_buf->type << 8) | (di_buf->index)
- ********************************************/
-struct di_buf_s *pwv3_qindex_2_buf(unsigned int ch, unsigned int qindex)
-{
- union uDI_QBUF_INDEX index;
- struct di_buf_s *di_buf;
- struct di_buf_pool_s *pbuf_pool = get_buf_pool(ch);
-
- index.d32 = qindex;
- di_buf = &pbuf_pool[index.b.type - 1].di_buf_ptr[index.b.index];
-
- return di_buf;
-}
-
-/********************************************/
-/*get di_buf from index that same in que*/
-/*(di_buf->type << 8) | (di_buf->index)*/
-/********************************************/
-static unsigned int pw_buf_2_qindex(unsigned int ch, struct di_buf_s *pdi_buf)
-{
- union uDI_QBUF_INDEX index;
-
- index.b.index = pdi_buf->index;
- index.b.type = pdi_buf->type;
- return index.d32;
-}
-
-/*di_buf is out*/
-struct di_buf_s *div3_que_out_to_di_buf(unsigned int ch, enum QUE_TYPE qtype)
-{
- unsigned int q_index;
- struct di_buf_s *pdi_buf = NULL;
-
- if (!pw_queue_peek(ch, qtype, &q_index)) {
- PR_ERR("%s:no buf\n", __func__);
- return pdi_buf;
- }
-
- pdi_buf = pwv3_qindex_2_buf(ch, q_index);
- if (!pdi_buf) {
- PR_ERR("%s:buf is null[%d]\n", __func__, q_index);
- return NULL;
- }
-
- pwv3_queue_out(ch, qtype, &q_index);
- pdi_buf->queue_index = -1;
-
- return pdi_buf;
-}
-
-#if 0
-/*di_buf is input*/
-bool div3_que_out(unsigned int ch, enum QUE_TYPE qtype, struct di_buf_s *di_buf)
-{
- unsigned int q_index;
- unsigned int q_index2;
-#ifdef DIM_DEBUG_QUE_ERR
- union dim_dbg_que_u dbg;
-#endif
- if (!pw_queue_peek(ch, qtype, &q_index)) {
- PR_ERR("%s:no buf ch[%d], qtype[%d], buf[%d,%d]\n", __func__,
- ch, qtype, di_buf->type, di_buf->index);
-#ifdef DIM_DEBUG_QUE_ERR
- dump_stack();
- dim_dbg_que_disable();
- dim_dbg_que_out();
-#endif
- return false;
- }
-
- q_index2 = pw_buf_2_qindex(ch, di_buf);
- if (q_index2 != q_index) {
- PR_ERR("di:%s:%d not map[0x%x,0x%x]\n", __func__,
- qtype, q_index2, q_index);
-#ifdef DIM_DEBUG_QUE_ERR
- dump_stack();
- dim_dbg_que_disable();
- dim_dbg_que_out();
-#endif
- return false;
- }
-#ifdef DIM_DEBUG_QUE_ERR
- /*dbg*/
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index)&0xff;
- dbg.b.que_api = DIM_QUE_OUT;
- dbg.b.que_index = qtype;
- dim_dbg_que(&dbg);
-#endif
- pwv3_queue_out(ch, qtype, &q_index);
- di_buf->queue_index = -1;
- return true;
-}
-#else
-/*di_buf is input*/
-bool div3_que_out(unsigned int ch, enum QUE_TYPE qtype, struct di_buf_s *di_buf)
-{
- unsigned int q_index;
- unsigned int q_index2;
- struct di_buf_s *dbuf;
-
-#ifdef DIM_DEBUG_QUE_ERR
- union dim_dbg_que_u dbg;
-#endif
- if (!pw_queue_peek(ch, qtype, &q_index)) {
- PR_ERR("%s:no buf ch[%d], qtype[%d], buf[%d,%d]\n", __func__,
- ch, qtype, di_buf->type, di_buf->index);
-#ifdef DIM_DEBUG_QUE_ERR
- dump_stack();
- dim_dbg_que_disable();
- dim_dbg_que_out();
-#endif
- return false;
- }
-
- pwv3_queue_out(ch, qtype, &q_index2);
- dbuf = pwv3_qindex_2_buf(ch, q_index2);
- dbg_qued("%s:%s:t[%d],id[%d]\n", __func__,
- div3_name_new_que[qtype], dbuf->type, dbuf->index);
-
- /*check*/
- if (dbuf->index != di_buf->index)
- PR_ERR("%s:not map\n", __func__);
-
-#ifdef DIM_DEBUG_QUE_ERR
- /*dbg*/
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index) & 0xff;
- dbg.b.que_api = DIM_QUE_OUT;
- dbg.b.que_index = qtype;
- dim_dbg_que(&dbg);
- trace_buf(di_buf, DIM_QUE_OUT, qtype,
- (DIM_DBG_MARK | 0x00008000));
-#endif
-
- dbuf->queue_index = -1;
- return true;
-}
-
-#endif
-bool div3_que_in(unsigned int ch, enum QUE_TYPE qtype, struct di_buf_s *di_buf)
-{
- unsigned int q_index;
-#ifdef DIM_DEBUG_QUE_ERR
- union dim_dbg_que_u dbg;
-#endif
-
- if (!di_buf) {
- PR_ERR("%s:di_buf is NULL,ch[%d],qtype[%d]\n",
- __func__, ch, qtype);
- return false;
- }
- if (di_buf->queue_index != -1) {
- PR_ERR("%s:buf in some que,ch[%d],qt[%d],qi[%d],bi[%d]\n",
- __func__,
- ch, qtype, di_buf->queue_index, di_buf->index);
-#ifdef DIM_DEBUG_QUE_ERR
- dump_stack();
- dim_dbg_que_disable();
- dim_dbg_que_out();
-#endif
- #ifdef HIS_V3
- return false;
- #else
- di_buf->queue_index = -1;
- #endif
- }
-#ifdef DIM_DEBUG_QUE_ERR
- /*dbg*/
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index) & 0xff;
- dbg.b.que_api = DIM_QUE_IN;
- dbg.b.que_index = qtype;
- dim_dbg_que(&dbg);
- trace_buf(di_buf, DIM_QUE_IN, qtype,
- (DIM_DBG_MARK | 0x00008000));
-#endif
- q_index = pw_buf_2_qindex(ch, di_buf);
-
- if (!pwv3_queue_in(ch, qtype, q_index)) {
- PR_ERR("%s:can't que in,ch[%d],qtype[%d],q_index[%d]\n",
- __func__,
- ch, qtype, q_index);
- return false;
- }
- di_buf->queue_index = qtype + QUEUE_NUM;
- dbg_qued("%s:%s:t[%d],id[%d]\n", __func__,
- div3_name_new_que[qtype], di_buf->type, di_buf->index);
-
- if (qtype == QUE_PRE_READY)
- dimv3_print("di:pre_ready in %d\n", di_buf->index);
-
- return true;
-}
-
-bool div3_que_is_in_que(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf)
-{
- unsigned int q_index;
- unsigned int arr[MAX_FIFO_SIZE + 1];
- unsigned int asize = 0;
- bool ret = false;
- unsigned int i;
-
- if (!di_buf)
- return false;
-
- q_index = pw_buf_2_qindex(ch, di_buf);
-
- div3_que_list(ch, qtype, &arr[0], &asize);
-
- if (asize == 0)
- return ret;
-
- for (i = 0; i < asize; i++) {
- if (arr[i] == q_index) {
- ret = true;
- break;
- }
- }
- return ret;
-}
-
-/* clear and rebuild que*/
-bool div3_que_out_not_fifo(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf)
-{
- unsigned int q_index;
- unsigned int arr[MAX_FIFO_SIZE + 1];
- unsigned int asize = 0;
- unsigned int i;
- bool ret = false;
-#ifdef DIM_DEBUG_QUE_ERR
- union dim_dbg_que_u dbg;
-#endif
-
- if (!pw_queue_peek(ch, qtype, &q_index))
- return false;
-
- q_index = pw_buf_2_qindex(ch, di_buf);
-
- div3_que_list(ch, qtype, &arr[0], &asize);
-
- pwv3_queue_clear(ch, qtype);
-
- if (asize == 0) {
- PR_ERR("%s:size 0\n", __func__);
- return ret;
- }
-
- for (i = 0; i < asize; i++) {
- if (arr[i] == q_index) {
- ret = true;
- di_buf->queue_index = -1;
- continue;
- }
- pwv3_queue_in(ch, qtype, arr[i]);
- }
- if (!ret) {
- PR_ERR("%s:not find:%d\n", __func__, di_buf->index);
- } else {
-#ifdef DIM_DEBUG_QUE_ERR
- /*dbg*/
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index) & 0xff;
- dbg.b.que_api = DIM_QUE_OUT_NOT_FIFO;
- dbg.b.que_index = qtype;
- dim_dbg_que(&dbg);
-#endif
- }
-
- return ret;
-}
-
-/*same as get_di_buf_head*/
-struct di_buf_s *div3_que_peek(unsigned int ch, enum QUE_TYPE qtype)
-{
- struct di_buf_s *di_buf = NULL;
- unsigned int q_index;
-
- if (!pw_queue_peek(ch, qtype, &q_index))
- return di_buf;
- di_buf = pwv3_qindex_2_buf(ch, q_index);
- trace_buf(di_buf, DIM_QUE_PEEK, qtype,
- (DIM_DBG_MARK | 0x00008000));
-
- return di_buf;
-}
-
-bool div3_que_type_2_new(unsigned int q_type, enum QUE_TYPE *nqtype)
-{
- if (!F_IN(q_type, QUEUE_NEW_THD_MIN, QUEUE_NEW_THD_MAX))
- return false;
- *nqtype = (enum QUE_TYPE)(q_type - QUEUE_NUM);
-
- return true;
-}
-
-/**********************************************************/
-/**********************************************************/
-/*ary add this function for reg ini value, no need wait peek*/
-void queuev3_init2(unsigned int channel)
-{
- int i, j;
- struct queue_s *pqueue = get_queue(channel);
-
- for (i = 0; i < QUEUE_NUM; i++) {
- queue_t *q = &pqueue[i];
-
- for (j = 0; j < MAX_QUEUE_POOL_SIZE; j++)
- q->pool[j] = 0;
-
- q->in_idx = 0;
- q->out_idx = 0;
- q->num = 0;
- q->type = 0;
- if ((i == QUEUE_RECYCLE) ||
- (i == QUEUE_DISPLAY) ||
- (i == QUEUE_TMP)
- /*|| (i == QUEUE_POST_DOING)*/)
- q->type = 1;
-
-#ifdef HIS_V3
- if ((i == QUEUE_LOCAL_FREE) && dim_get_use_2_int_buf())
- q->type = 2;
-#endif
- }
-}
-
-void queuev3_init(unsigned int channel, int local_buffer_num)
-{
- int i, j;
- struct di_buf_s *pbuf_local = get_buf_local(channel);
- struct di_buf_s *pbuf_in = get_buf_in(channel);
- struct di_buf_s *pbuf_post = get_buf_post(channel);
- struct queue_s *pqueue = get_queue(channel);
- struct di_buf_pool_s *pbuf_pool = get_buf_pool(channel);
-
- for (i = 0; i < QUEUE_NUM; i++) {
- queue_t *q = &pqueue[i];
-
- for (j = 0; j < MAX_QUEUE_POOL_SIZE; j++)
- q->pool[j] = 0;
-
- q->in_idx = 0;
- q->out_idx = 0;
- q->num = 0;
- q->type = 0;
- if ((i == QUEUE_RECYCLE) ||
- (i == QUEUE_DISPLAY) ||
- (i == QUEUE_TMP)
- /*||(i == QUEUE_POST_DOING)*/
- )
- q->type = 1;
-
- if ((i == QUEUE_LOCAL_FREE) &&
- dimp_get(eDI_MP_use_2_interlace_buff))
- q->type = 2;
- }
- if (local_buffer_num > 0) {
- pbuf_pool[VFRAME_TYPE_IN - 1].di_buf_ptr = &pbuf_in[0];
- pbuf_pool[VFRAME_TYPE_IN - 1].size = MAX_IN_BUF_NUM;
-
- pbuf_pool[VFRAME_TYPE_LOCAL - 1].di_buf_ptr = &pbuf_local[0];
- pbuf_pool[VFRAME_TYPE_LOCAL - 1].size = local_buffer_num;
-
- pbuf_pool[VFRAME_TYPE_POST - 1].di_buf_ptr = &pbuf_post[0];
- pbuf_pool[VFRAME_TYPE_POST - 1].size = MAX_POST_BUF_NUM;
- }
-}
-
-struct di_buf_s *getv3_di_buf_head(unsigned int channel, int queue_idx)
-{
- struct queue_s *pqueue = get_queue(channel);
- queue_t *q = &pqueue[queue_idx];
- int idx;
- unsigned int pool_idx, di_buf_idx;
- struct di_buf_s *di_buf = NULL;
- struct di_buf_pool_s *pbuf_pool = get_buf_pool(channel);
- enum QUE_TYPE nqtype;/*new que*/
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s:<%d:%d,%d,%d>\n", __func__, queue_idx,
- q->num, q->in_idx, q->out_idx);
- /* ****new que***** */
- if (div3_que_type_2_new(queue_idx, &nqtype))
- return div3_que_peek(channel, nqtype);
-
- /* **************** */
-
- if (q->num > 0) {
- if (q->type == 0) {
- idx = q->out_idx;
- } else {
- for (idx = 0; idx < MAX_QUEUE_POOL_SIZE; idx++)
- if (q->pool[idx] != 0)
- break;
- }
- if (idx < MAX_QUEUE_POOL_SIZE) {
- pool_idx = ((q->pool[idx] >> 8) & 0xff) - 1;
- di_buf_idx = q->pool[idx] & 0xff;
-
- if (pool_idx < VFRAME_TYPE_NUM) {
- if (di_buf_idx < pbuf_pool[pool_idx].size)
- di_buf = &pbuf_pool[pool_idx].di_buf_ptr[di_buf_idx];
- }
- }
- }
-
- if ((di_buf) && ((((pool_idx + 1) << 8) | di_buf_idx) !=
- ((di_buf->type << 8) | (di_buf->index)))) {
- pr_dbg("%s: Error (%x,%x)\n", __func__,
- (((pool_idx + 1) << 8) | di_buf_idx),
- ((di_buf->type << 8) | (di_buf->index)));
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(2);
- dimv3_vcry_set_log_q_idx(queue_idx);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- di_buf = NULL;
- }
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE) {
- if (di_buf)
- dimv3_print("%s: 0x%p(%d,%d)\n", __func__, di_buf,
- pool_idx, di_buf_idx);
- else
- dimv3_print("%s: 0x%p\n", __func__, di_buf);
- }
-
- return di_buf;
-}
-
-/*ary: note:*/
-/*a. di_buf->queue_index = -1*/
-/*b. */
-void queuev3_out(unsigned int channel, struct di_buf_s *di_buf)
-{
- int i;
- queue_t *q;
- struct queue_s *pqueue = get_queue(channel);
- enum QUE_TYPE nqtype;/*new que*/
-#ifdef DIM_DEBUG_QUE_ERR
- union dim_dbg_que_u dbg;
-#endif
-
- if (!di_buf) {
- PR_ERR("queuev3_out:Error\n");
-
- if (dimv3_vcry_get_flg() == 0)
- dimv3_vcry_set_log_reason(3);
-
- dimv3_vcry_flg_inc();
- return;
- }
- /* ****new que***** */
- if (div3_que_type_2_new(di_buf->queue_index, &nqtype)) {
- div3_que_out(channel, nqtype, di_buf); /*?*/
- return;
- }
-#ifdef DIM_DEBUG_QUE_ERR
- /*dbg*/
- dbg.b.buf_index = di_buf->index;
- dbg.b.buf_type = di_buf->type;
- dbg.b.omx_index = (di_buf->c.vmode.omx_index) & 0xff;
- dbg.b.que_api = DIM_O_OUT;
- dbg.b.que_index = di_buf->queue_index;
- dim_dbg_que(&dbg);
-
-#endif
- /* **************** */
-
- if (di_buf->queue_index >= 0 && di_buf->queue_index < QUEUE_NUM) {
- q = &pqueue[di_buf->queue_index];
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s:<%d:%d,%d,%d> 0x%p\n", __func__,
- di_buf->queue_index, q->num, q->in_idx,
- q->out_idx, di_buf);
-
- if (q->num > 0) {
- if (q->type == 0) {
- if (q->pool[q->out_idx] ==
- ((di_buf->type << 8) | (di_buf->index))) {
- q->num--;
- q->pool[q->out_idx] = 0;
- q->out_idx++;
- if (q->out_idx >= MAX_QUEUE_POOL_SIZE)
- q->out_idx = 0;
- di_buf->queue_index = -1;
- } else {
- PR_ERR(
- "%s: Error (%d, %x,%x)\n",
- __func__,
- di_buf->queue_index,
- q->pool[q->out_idx],
- ((di_buf->type << 8) |
- (di_buf->index)));
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(4);
- dimv3_vcry_set_log_q_idx(di_buf->queue_index);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- } else if (q->type == 1) {
- int pool_val =
- (di_buf->type << 8) | (di_buf->index);
- for (i = 0; i < MAX_QUEUE_POOL_SIZE; i++) {
- if (q->pool[i] == pool_val) {
- q->num--;
- q->pool[i] = 0;
- di_buf->queue_index = -1;
- break;
- }
- }
- if (i == MAX_QUEUE_POOL_SIZE) {
- PR_ERR("%s: Error\n", __func__);
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(5);
- dimv3_vcry_set_log_q_idx(di_buf->queue_index);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- } else if (q->type == 2) {
- int pool_val =
- (di_buf->type << 8) | (di_buf->index);
- if ((di_buf->index < MAX_QUEUE_POOL_SIZE) &&
- (q->pool[di_buf->index] == pool_val)) {
- q->num--;
- q->pool[di_buf->index] = 0;
- di_buf->queue_index = -1;
- } else {
- PR_ERR("%s: Error\n", __func__);
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(5);
- dimv3_vcry_set_log_q_idx(di_buf->queue_index);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- }
- }
- } else {
- PR_ERR("%s: t[%d] d[%d] is not right\n",
- __func__, di_buf->type, di_buf->index);
- dump_stack();
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(6);
- dimv3_vcry_set_log_q_idx(0);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s done\n", __func__);
-}
-
-void queuev3_out_dbg(unsigned int channel, struct di_buf_s *di_buf)
-{
- int i;
- queue_t *q;
- struct queue_s *pqueue = get_queue(channel);
- enum QUE_TYPE nqtype;/*new que*/
-
- if (!di_buf) {
- PR_ERR("%s:Error\n", __func__);
-
- if (dimv3_vcry_get_flg() == 0)
- dimv3_vcry_set_log_reason(3);
-
- dimv3_vcry_flg_inc();
- return;
- }
- /* ****new que***** */
- if (div3_que_type_2_new(di_buf->queue_index, &nqtype)) {
- div3_que_out(channel, nqtype, di_buf); /*?*/
- PR_INF("dbg1:nqtype=%d\n", nqtype);
- return;
- }
- /* **************** */
-
- if (di_buf->queue_index >= 0 && di_buf->queue_index < QUEUE_NUM) {
- q = &pqueue[di_buf->queue_index];
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s:<%d:%d,%d,%d> 0x%p\n", __func__,
- di_buf->queue_index, q->num, q->in_idx,
- q->out_idx, di_buf);
-
- if (q->num > 0) {
- if (q->type == 0) {
- pr_info("dbg3\n");
- if (q->pool[q->out_idx] ==
- ((di_buf->type << 8) | (di_buf->index))) {
- q->num--;
- q->pool[q->out_idx] = 0;
- q->out_idx++;
- if (q->out_idx >= MAX_QUEUE_POOL_SIZE)
- q->out_idx = 0;
- di_buf->queue_index = -1;
- } else {
- PR_ERR(
- "%s: Error (%d, %x,%x)\n",
- __func__,
- di_buf->queue_index,
- q->pool[q->out_idx],
- ((di_buf->type << 8) |
- (di_buf->index)));
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(4);
- dimv3_vcry_set_log_q_idx(di_buf->queue_index);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- } else if (q->type == 1) {
- int pool_val =
- (di_buf->type << 8) | (di_buf->index);
- for (i = 0; i < MAX_QUEUE_POOL_SIZE; i++) {
- if (q->pool[i] == pool_val) {
- q->num--;
- q->pool[i] = 0;
- di_buf->queue_index = -1;
- break;
- }
- }
- PR_INF("dbg2:i=%d,qindex=%d\n", i,
- di_buf->queue_index);
- if (i == MAX_QUEUE_POOL_SIZE) {
- PR_ERR("%s: Error\n", __func__);
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(5);
- dimv3_vcry_set_log_q_idx(di_buf->queue_index);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- } else if (q->type == 2) {
- int pool_val =
- (di_buf->type << 8) | (di_buf->index);
-
- PR_INF("dbg4\n");
- if ((di_buf->index < MAX_QUEUE_POOL_SIZE) &&
- (q->pool[di_buf->index] == pool_val)) {
- q->num--;
- q->pool[di_buf->index] = 0;
- di_buf->queue_index = -1;
- } else {
- PR_ERR("%s: Error\n", __func__);
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set
- (5,
- di_buf->queue_index,
- di_buf);
- }
- dimv3_vcry_flg_inc();
- }
- }
- }
- } else {
- PR_ERR("%s: Error, queue_index %d is not right\n",
- __func__, di_buf->queue_index);
-
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(6);
- dimv3_vcry_set_log_q_idx(0);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- }
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s done\n", __func__);
-}
-
-/***************************************/
-/* set di_buf->queue_index*/
-/***************************************/
-void queuev3_in(unsigned int channel, struct di_buf_s *di_buf, int queue_idx)
-{
- queue_t *q = NULL;
- struct queue_s *pqueue = get_queue(channel);
- enum QUE_TYPE nqtype;/*new que*/
-
- if (!di_buf) {
- PR_ERR("%s:Error\n", __func__);
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(7);
- dimv3_vcry_set_log_q_idx(queue_idx);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- return;
- }
- /* ****new que***** */
- if (div3_que_type_2_new(queue_idx, &nqtype)) {
- div3_que_in(channel, nqtype, di_buf);
- return;
- }
- /* **************** */
- if (di_buf->queue_index != -1) {
- dump_stack();
- PR_ERR("%s:%s[%d] queue_index(%d) is not -1, to que[%d]\n",
- __func__, dimv3_get_vfm_type_name(di_buf->type),
- di_buf->index, di_buf->queue_index, queue_idx);
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(8);
- dimv3_vcry_set_log_q_idx(queue_idx);
- dimv3_vcry_set_log_di_buf(di_buf);
- }
- dimv3_vcry_flg_inc();
- return;
- }
- q = &pqueue[queue_idx];
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s:<%d:%d,%d,%d> 0x%p\n", __func__, queue_idx,
- q->num, q->in_idx, q->out_idx, di_buf);
-
- if (q->type == 0) {
- q->pool[q->in_idx] = (di_buf->type << 8) | (di_buf->index);
- di_buf->queue_index = queue_idx;
- q->in_idx++;
- if (q->in_idx >= MAX_QUEUE_POOL_SIZE)
- q->in_idx = 0;
-
- q->num++;
- } else if (q->type == 1) {
- int i;
-
- for (i = 0; i < MAX_QUEUE_POOL_SIZE; i++) {
- if (q->pool[i] == 0) {
- q->pool[i] =
- (di_buf->type << 8) | (di_buf->index);
- di_buf->queue_index = queue_idx;
- q->num++;
- break;
- }
- }
- if (i == MAX_QUEUE_POOL_SIZE) {
- pr_dbg("%s: Error\n", __func__);
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(9);
- dimv3_vcry_set_log_q_idx(queue_idx);
- }
- dimv3_vcry_flg_inc();
- }
- } else if (q->type == 2) {
- if ((di_buf->index < MAX_QUEUE_POOL_SIZE) &&
- (q->pool[di_buf->index] == 0)) {
- q->pool[di_buf->index] =
- (di_buf->type << 8) | (di_buf->index);
- di_buf->queue_index = queue_idx;
- q->num++;
- } else {
- pr_dbg("%s: Error\n", __func__);
- if (dimv3_vcry_get_flg() == 0) {
- dimv3_vcry_set_log_reason(9);
- dimv3_vcry_set_log_q_idx(queue_idx);
- }
- dimv3_vcry_flg_inc();
- }
- }
-
- if (dimp_get(eDI_MP_di_log_flag) & DI_LOG_QUEUE)
- dimv3_print("%s done\n", __func__);
-}
-
-int listv3_count(unsigned int channel, int queue_idx)
-{
- struct queue_s *pqueue;
- enum QUE_TYPE nqtype;/*new que*/
-
- /* ****new que***** */
- if (div3_que_type_2_new(queue_idx, &nqtype)) {
- PR_ERR("%s:err: over flow\n", __func__);
- return div3_que_list_count(channel, nqtype);
- }
- /* **************** */
-
- pqueue = get_queue(channel);
- return pqueue[queue_idx].num;
-}
-
-bool queuev3_empty(unsigned int channel, int queue_idx)
-{
- struct queue_s *pqueue;
- bool ret;
- enum QUE_TYPE nqtype;/*new que*/
-
- /* ****new que***** */
- if (div3_que_type_2_new(queue_idx, &nqtype)) {
- PR_ERR("%s:err: over flow\n", __func__);
- return div3_que_is_empty(channel, nqtype);
- }
- /* **************** */
-
- pqueue = get_queue(channel);
- ret = (pqueue[queue_idx].num == 0);
-
- return ret;
-}
-
-bool isv3_in_queue(unsigned int channel, struct di_buf_s *di_buf, int queue_idx)
-{
- bool ret = 0;
- struct di_buf_s *p = NULL;
- int itmp;
- unsigned int overflow_cnt;
- enum QUE_TYPE nqtype;/*new que*/
-
- /* ****new que***** */
- if (div3_que_type_2_new(queue_idx, &nqtype))
- return div3_que_is_in_que(channel, nqtype, di_buf);
-
- /* **************** */
-
- overflow_cnt = 0;
- if (!di_buf || (queue_idx < 0) || (queue_idx >= QUEUE_NUM)) {
- ret = 0;
- dimv3_print("%s: not in queue:%d!!!\n", __func__, queue_idx);
- return ret;
- }
- queue_for_each_entry(p, channel, queue_idx, list) {
- if (p == di_buf) {
- ret = 1;
- break;
- }
- if (overflow_cnt++ > MAX_QUEUE_POOL_SIZE) {
- ret = 0;
- dimv3_print("%s: overflow_cnt!!!\n", __func__);
- break;
- }
- }
- return ret;
-}
-
-void qued_remove(struct di_ch_s *pch)
-{
- struct dim_que_s *pdque;
- int i;
-
- if (!pch)
- return;
-
- for (i = 0; i < QUED_T_SPLIT; i++) {
- pdque = &pch->qued[i];
- if (pdque->f.flg) {
- kfifo_free(&pdque->f.fifo);
- pdque->f.flg = 0;
- }
- }
-
- PR_INF("%s:ok\n", __func__);
-}
-
-bool qued_prob(struct di_ch_s *pch)
-{
- int i;
- int ret;
- bool flg_err;
- //struct di_ch_s *pch = get_chdata(ch);
- struct dim_que_s *pdque;
- unsigned int cnt = sizeof(unsigned int);
-
- if (!pch)
- return false;
-
- //pdque = &pch->qued[0];
- /*kfifo----------------------------*/
- flg_err = 0;
- for (i = 0; i < QUED_T_SPLIT; i++) {
- pdque = &pch->qued[i];
- ret = kfifo_alloc(&pdque->f.fifo,
- cnt * MAX_FIFO_SIZE,
- GFP_KERNEL);
- if (ret < 0) {
- flg_err = 1;
- PR_ERR("%s:%d:can't get kfifo\n", __func__, i);
- bsetv3(&pch->err, DIM_ERR_QUE_FIFO);
- break;
- }
- pdque->f.flg = 1;
- }
-
- if (flg_err) {
- qued_remove(pch);
- return false;
- }
- bclrv3(&pch->err, DIM_ERR_QUE_FIFO);
-
- /*mutex*/
- for (i = QUED_T_SPLIT; i < QUED_T_NUB; i++) {
- pdque = &pch->qued[i];
- mutex_init(&pdque->n.mtex);
- }
-
- PR_INF("%s:ok\n", __func__);
-
- return true;
-}
-
-static const char * const qued_name[] = {
- "FREE",
- "IN",
- "PRE",
- "PRE_READY",
- "PST",
- "PST_READY",
- "BACK",
- "RECYCLE",
- "IS_IN",
- "IS_FREE",
- "IS_PST_FREE",
- "IS_PST_DOBEF",
- //"IS_PST_NOBUF",
- "PST_DOING",
- "DBG",
- "SPLIT", /*not use, only split*/
- "DIS",
- "NUB"
-};
-
-const char *qued_get_name(struct di_ch_s *pch, enum QUED_TYPE qtype)
-{
- struct dim_que_s *pdque;
-// unsigned int cnt = sizeof (unsigned int);
-
- if (!pch)
- return NULL;
-
- pdque = &pch->qued[qtype];
-
- return pdque->name;
-}
-
-bool qued_reg(struct di_ch_s *pch)
-{
- //struct di_ch_s *pch = get_chdata(ch);
-// struct dim_dvfm_s *pdvfm;
- struct dim_que_s *pdque;
- int i;
-
- if (!pch)
- return false;
-
- for (i = 0; i < QUED_T_NUB; i++) {
- pdque = &pch->qued[i];
- pdque->index = i;
- if (i < sizeof(qued_name))
- pdque->name = qued_name[i];
-
- if (i < QUED_T_SPLIT) { /*fifo que*/
- pdque->type = QUED_K_FIFO;
- dbg_dbg("%s:que reset t[%s]\n", __func__, pdque->name);
- kfifo_reset(&pdque->f.fifo);
- } else { /*QUED_K_N*/
- pdque->type = QUED_K_N;
- pdque->n.marsk = 0;
- pdque->n.nub = 0;
- }
- }
- return true;
-}
-
-bool qued_unreg(struct di_ch_s *pch)
-{
- return true;
-}
-
-bool qued_in(struct di_ch_s *pch, enum QUED_TYPE qtype, unsigned int buf_index)
-{
- struct dim_que_s *pdque;
- unsigned int cnt = sizeof(unsigned int);
-// bool ret;
-
- if (!pch)
- return false;
- pdque = &pch->qued[qtype];
-
- if (pdque->type == QUED_K_FIFO) {
- if (kfifo_in(&pdque->f.fifo, &buf_index, cnt) != cnt) {
- PR_ERR("%s:ch[%d]f:q[%s][%d]\n", __func__,
- pch->ch_id,
- qued_get_name(pch, qtype),
- buf_index);
- return false;
- }
- dbg_qued("%s:ch[%d],q[%s],id[%d]\n",
- __func__,
- pch->ch_id,
- qued_name[qtype],
- buf_index);
- return true;
- }
-
- /*QUED_K_N*/
- mutex_lock(&pdque->n.mtex);
- if (bgetv3(&pdque->n.marsk, buf_index)) { /*check*/
- PR_ERR("%s:ch[%d],q[%s],b[%d] have set\n",
- __func__, pch->ch_id,
- qued_get_name(pch, qtype),
- buf_index);
- mutex_unlock(&pdque->n.mtex);
- return false;
- }
- bsetv3(&pdque->n.marsk, buf_index);
- pdque->n.nub++;
- mutex_unlock(&pdque->n.mtex);
-
- dbg_qued("%s:ch[%d],q[%s],id[%d]\n",
- __func__,
- pch->ch_id,
- qued_name[qtype],
- buf_index);
- return true;
-}
-
-bool qued_out(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int *buf_index)
-{
- struct dim_que_s *pdque;
- unsigned int cnt = sizeof(unsigned int);
-
- if (!pch)
- return false;
- pdque = &pch->qued[qtype];
-
- if (pdque->type == QUED_K_FIFO) {
- if (kfifo_out(&pdque->f.fifo, buf_index, cnt) != cnt)
- return false;
-
- dbg_qued("%s:ch[%d],q[%s],id[%d]\n",
- __func__,
- pch->ch_id,
- qued_name[qtype],
- *buf_index);
- return true;
- }
-
- /*QUED_K_N*/
- mutex_lock(&pdque->n.mtex);
- if (!bgetv3(&pdque->n.marsk, *buf_index)) { /*check*/
- PR_ERR("%s:ch[%d],q[%d],b[%d] have set\n",
- __func__, pch->ch_id, qtype, *buf_index);
- mutex_unlock(&pdque->n.mtex);
- return false;
- }
- bclrv3(&pdque->n.marsk, *buf_index);
- pdque->n.nub--;
- mutex_unlock(&pdque->n.mtex);
-
- dbg_qued("%s:ch[%d],q[%s],id[%d]\n",
- __func__,
- pch->ch_id,
- qued_name[qtype],
- *buf_index);
- return true;
-}
-
-bool qued_move(struct di_ch_s *pch, enum QUED_TYPE qtypef,
- enum QUED_TYPE qtypet, unsigned int *buf_index)
-{
- struct dim_que_s *pdquef, *pdquet;
- unsigned int cnt = sizeof(unsigned int);
-// bool ret;
- unsigned int index;
-
- if (!pch) {
- PR_ERR("%s:no pch\n", __func__);
- return false;
- }
- pdquef = &pch->qued[qtypef];
- pdquet = &pch->qued[qtypet];
-
- if (pdquef->type != QUED_K_FIFO ||
- pdquet->type != QUED_K_FIFO) {
- PR_ERR("%s: don't support nfiko\n", __func__);
- return false;
- }
-
- if (kfifo_is_empty(&pdquef->f.fifo) || kfifo_is_full(&pdquet->f.fifo)) {
- PR_ERR("%s:que full or empty\n", __func__);
- PR_ERR("f:q[%s],t:q[%s]\n", qued_name[qtypef],
- qued_name[qtypet]);
- dump_stack();
- return false;
- }
-
- if (kfifo_out(&pdquef->f.fifo, &index, cnt) != cnt) {
- PR_ERR("%s:ch[%d]f:q[%s][%d]\n", __func__,
- pch->ch_id,
- qued_get_name(pch, qtypef),
- index);
- return false;
- }
-
- if (kfifo_in(&pdquet->f.fifo, &index, cnt) != cnt) {
- PR_ERR("%s:ch[%d]f:q[%s][%d]\n", __func__,
- pch->ch_id,
- qued_get_name(pch, qtypet),
- index);
- return false;
- }
- dbg_qued("%s:ch[%d],qf[%s],id[%d],ft[%s]\n",
- __func__,
- pch->ch_id,
- qued_name[qtypef], index,
- qued_name[qtypet]);
-
- *buf_index = index;
- return true;
-}
-
-bool qued_peek(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int *buf_index)
-{
- struct dim_que_s *pdque;
- unsigned int cnt = sizeof(unsigned int);
-
- if (!pch)
- return false;
- pdque = &pch->qued[qtype];
-
- if (pdque->type == QUED_K_FIFO) {
- if (kfifo_out_peek(&pdque->f.fifo, buf_index, cnt) != cnt)
- return false;
-
- return true;
- }
-
- PR_ERR("q:%s no peek function\n", qued_get_name(pch, qtype));
- return false;
-}
-
-#ifdef HIS_V3
-bool qued_move(struct di_ch_s *pch, enum QUED_TYPE qtypef, enum QUE_TYPE qtypet,
- unsigned int *oindex)
-{
- struct dim_que_s *pdquef, *pdquet;
- unsigned int cnt = sizeof(unsigned int);
-
- if (!pch)
- return;
- pdquef = &pch->qued[qtypef];
- pdquet = &pch->qued[qtypet];
-
- if (pdquef->type == QUED_K_FIFO &&
- pdquet->type == QUED_K_FIFO) {
- }
-}
-#endif
-
-bool qued_list(struct di_ch_s *pch, enum QUED_TYPE qtype, unsigned int *outbuf,
- unsigned int *rsize)
-{
- struct dim_que_s *pdque, *pdque_tmp;
- unsigned int cnt = sizeof(unsigned int);
- int i;
- unsigned int index;
- unsigned int mask;
-
- if (!pch)
- return false;
- pdque = &pch->qued[qtype];
-
- /*que_dbg("%s:begin\n", __func__);*/
- for (i = 0; i < MAX_FIFO_SIZE; i++)
- outbuf[i] = 0xff;
-
- if (pdque->type == QUED_K_FIFO) {
- pdque_tmp = &pch->qued[QUED_T_DBG];
-
- if (kfifo_is_empty(&pdque->f.fifo)) {
- que_dbg("\t%d:empty\n", qtype);
- *rsize = 0;
- return true;
- }
-
- memcpy(&pdque_tmp->f.fifo, &pdque->f.fifo,
- sizeof(pdque_tmp->f.fifo));
-
- i = 0;
- *rsize = 0;
-
- while (kfifo_out(&pdque_tmp->f.fifo, &index, cnt) == cnt) {
- outbuf[i] = index;
- /*pr_info("%d->%d\n",i,index);*/
- i++;
- }
- *rsize = i;
-
- return true;
- }
-
- /*QUED_K_N*/
- mutex_lock(&pdque->n.mtex);
- mask = pdque->n.marsk;
- *rsize = pdque->n.nub;
- mutex_unlock(&pdque->n.mtex);
-
- cnt = 0;
- for (i = 0; i < MAX_FIFO_SIZE; i++) {
- if (mask & 0x01) {
- outbuf[cnt] = i;
- cnt++;
- }
- mask >>= 1;
- }
-
- #ifdef HIS_V3 /*debug only*/
- que_dbg("%s: size[%d]\n", div3_name_new_que[qtype], *rsize);
- for (i = 0; i < *rsize; i++)
- que_dbg("%d,", outbuf[i]);
-
- que_dbg("\n");
- #endif
-
- return true;
-}
-
-unsigned int qued_list_count(struct di_ch_s *pch, enum QUED_TYPE qtype)
-{
- struct dim_que_s *pdque;
- unsigned int cnt = sizeof(unsigned int);
- unsigned int length = 0;
-
- if (!pch)
- return 0;
- pdque = &pch->qued[qtype];
-
- if (pdque->type == QUED_K_FIFO) {
- length = kfifo_len(&pdque->f.fifo);
- length = length / cnt;
-
- return length;
- }
-
- /*QUED_K_N*/
- mutex_lock(&pdque->n.mtex);
- length = pdque->n.nub;
- mutex_unlock(&pdque->n.mtex);
-
- return length;
-}
-
-bool qued_is_in_que(struct di_ch_s *pch, enum QUED_TYPE qtype,
- unsigned int buf_index)
-{
-// unsigned int q_index;
- unsigned int arr[MAX_FIFO_SIZE + 1];
- unsigned int asize = 0;
- bool ret = false;
- unsigned int i;
-// struct dim_que_s *pdque;
-
- if (!pch)
- return false;
-
- qued_list(pch, qtype, &arr[0], &asize);
-
- if (asize == 0)
- return ret;
-
- for (i = 0; i < asize; i++) {
- if (arr[i] == buf_index) {
- ret = true;
- break;
- }
- }
- return ret;
-}
-
-bool qued_empty(struct di_ch_s *pch, enum QUED_TYPE qtype)
-{
- struct dim_que_s *pdque;
-// unsigned int cnt = sizeof (unsigned int);
-
- if (!pch)
- return true;
-
- pdque = &pch->qued[qtype];
-
- if (pdque->type == QUED_K_FIFO) {
- if (kfifo_is_empty(&pdque->f.fifo))
- return true;
- return false;
- }
-
- /*QUED_K_N*/
- if (pdque->n.nub == 0)
- return true;
-
- return false;
-}
-
-const struct qued_ops_s qued_ops = {
- .prob = qued_prob,
- .remove = qued_remove,
- .reg = qued_reg,
- .unreg = qued_unreg,
- .in = qued_in,
- .out = qued_out,
- .peek = qued_peek,
- .list = qued_list,
- .listv3_count = qued_list_count,
- .is_in = qued_is_in_que,
- .is_empty = qued_empty,
- .get_name = qued_get_name,
- .move = qued_move,
-};
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_que.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_QUE_H__
-#define __DI_QUE_H__
-
-void queuev3_init(unsigned int channel, int local_buffer_num);
-void queuev3_out(unsigned int channel, struct di_buf_s *di_buf);
-void queuev3_in(unsigned int channel, struct di_buf_s *di_buf,
- int queue_idx);
-int listv3_count(unsigned int channel, int queue_idx);
-bool queuev3_empty(unsigned int channel, int queue_idx);
-bool isv3_in_queue(unsigned int channel, struct di_buf_s *di_buf,
- int queue_idx);
-struct di_buf_s *getv3_di_buf_head(unsigned int channel,
- int queue_idx);
-
-void queuev3_init2(unsigned int channel);
-
-/*new buf:*/
-bool pwv3_queue_in(unsigned int ch, enum QUE_TYPE qtype,
- unsigned int buf_index);
-bool pwv3_queue_out(unsigned int ch, enum QUE_TYPE qtype,
- unsigned int *buf_index);
-bool pwv3_queue_empty(unsigned int ch, enum QUE_TYPE qtype);
-void pwv3_queue_clear(unsigned int ch, enum QUE_TYPE qtype);
-
-/******************************************/
-/*new api*/
-/******************************************/
-union uDI_QBUF_INDEX {
- unsigned int d32;
- struct {
- unsigned int index:8, /*low*/
- type:8,
- reserved0:16;
- } b;
-};
-
-void div3_que_init(unsigned int ch);
-bool div3_que_alloc(unsigned int ch);
-void div3_que_release(unsigned int ch);
-
-int div3_que_is_empty(unsigned int ch, enum QUE_TYPE qtype);
-bool div3_que_out(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf);
-
-struct di_buf_s *div3_que_out_to_di_buf(unsigned int ch,
- enum QUE_TYPE qtype);
-bool div3_que_out_not_fifo(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf);
-
-bool div3_que_in(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf);
-bool div3_que_is_in_que(unsigned int ch, enum QUE_TYPE qtype,
- struct di_buf_s *di_buf);
-struct di_buf_s *div3_que_peek(unsigned int ch, enum QUE_TYPE qtype);
-bool div3_que_type_2_new(unsigned int q_type, enum QUE_TYPE *nqtype);
-int div3_que_list_count(unsigned int ch, enum QUE_TYPE qtype);
-bool div3_que_list(unsigned int ch, enum QUE_TYPE qtype,
- unsigned int *outbuf, unsigned int *rsize);
-
-struct di_buf_s *pwv3_qindex_2_buf(unsigned int ch, unsigned int qindex);
-
-void queuev3_out_dbg(unsigned int channel, struct di_buf_s *di_buf);
-
-#ifdef DIM_DEBUG_QUE_ERR
-void dim_dbg_que_int(void);
-void dim_dbg_que_disable(void);
-void dim_dbg_que_out(void);
-void trace_buf(struct di_buf_s *di_buf,
- unsigned int q_api, unsigned int q_index,
- unsigned int tag);
-
-#endif
-#endif /*__DI_QUE_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_reg_tab.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/seq_file.h>
-
-#include <linux/amlogic/iomap.h>
-
-#include "deinterlace.h"
-#include "di_data_l.h"
-#include "register.h"
-
-static const struct reg_t rtab_contr[] = {
- /*--------------------------*/
- {VD1_AFBCD0_MISC_CTRL, 20, 2, 0, "VD1_AFBCD0_MISC_CTRL",
- "vd1_go_field_sel",
- "0: gofile;1: post;2: pre"},
- {VD1_AFBCD0_MISC_CTRL, 9, 1, 0, "",
- "afbc0_mux_vpp_mad",
- "afbc0 to 0:vpp; 1:di"},
- {VD1_AFBCD0_MISC_CTRL, 8, 1, 0, "",
- "di_mif0_en",
- ":mif to 0-vpp;1-di"},
- /*--------------------------*/
- {DI_POST_CTRL, 12, 1, 0, "DI_POST_CTRL",
- "di_post_viu_link",
- ""},
- {DI_POST_CTRL, 8, 1, 0, "",
- "di_vpp_out_en",
- ""},
- /*--------------------------*/
- {VIU_MISC_CTRL0, 20, 1, 0, "VIU_MISC_CTRL0",
- "?",
- "?"},
- {VIU_MISC_CTRL0, 18, 1, 0, "",
- "Vdin0_wr_out_ctrl",
- "0: nr_inp to vdin; 1: vdin wr dout"},
- {VIU_MISC_CTRL0, 17, 1, 0, "",
- "Afbc_inp_sel",
- "0: mif to INP; 1: afbc to INP"},
- {VIU_MISC_CTRL0, 16, 1, 0, "",
- "di_mif0_en",
- " vd1(afbc) to di post(if0) enable"},
- /*--------------------------*/
- {DI_IF1_GEN_REG, 0, 1, 0, "DI_IF1_GEN_REG",
- "enable",
- ""},
-
- /*--------------------------*/
- {DI_IF1_GEN_REG3, 8, 2, 0, "DI_IF1_GEN_REG3",
- "cntl_bits_mode",
- "0:8bit;1:10bit 422;2:10bit 444"},
-
- /*--------------------------*/
- {DI_IF2_GEN_REG3, 8, 2, 0, "DI_IF2_GEN_REG3",
- "cntl_bits_mode",
- "0:8bit;1:10bit 422;2:10bit 444"},
-
- /*--------------------------*/
- {DI_IF0_GEN_REG3, 8, 2, 0, "DI_IF0_GEN_REG3",
- "cntl_bits_mode",
- "0:8bit;1:10bit 422;2:10bit 444"},
-
- /*--------------------------*/
- {DI_POST_GL_CTRL, 31, 1, 0, "DI_POST_GL_CTRL",
- "post count enable",
- ""},
- {DI_POST_GL_CTRL, 30, 1, 0, "",
- "post count reset",
- ""},
- {DI_POST_GL_CTRL, 16, 14, 0, "",
- "total line number for post count",
- ""},
- {DI_POST_GL_CTRL, 0, 14, 0, "",
- "the line number of post frame reset",
- ""},
-
- {TABLE_FLG_END, 0, 0, 0, "end", "end", ""}
-
-};
-
-/**********************/
-/* debug register */
-/**********************/
-static unsigned int get_reg_bits(unsigned int val, unsigned int bstart,
- unsigned int bw)
-{
- return((val &
- (((1L << bw) - 1) << bstart)) >> (bstart));
-}
-
-static void dbg_reg_tab(struct seq_file *s, const struct reg_t *pRegTab)
-{
- struct reg_t creg;
- int i;
- unsigned int l_add;
- unsigned int val32 = 1, val;
- char *bname;
- char *info;
-
- i = 0;
- l_add = 0;
- creg = pRegTab[i];
-
- do {
- if (creg.add != l_add) {
- val32 = Rd(creg.add); /*RD*/
- seq_printf(s, "add:0x%x = 0x%08x, %s\n",
- creg.add, val32, creg.name);
- l_add = creg.add;
- }
- val = get_reg_bits(val32, creg.bit, creg.wid); /*RD_B*/
-
- if (creg.bname)
- bname = creg.bname;
- else
- bname = "";
- if (creg.info)
- info = creg.info;
- else
- info = "";
-
- seq_printf(s, "\tbit[%d,%d]:\t0x%x[%d]:\t%s:\t%s\n",
- creg.bit, creg.wid, val, val, bname, info);
-
- i++;
- creg = pRegTab[i];
- if (i > TABLE_LEN_MAX) {
- PR_WARN("too long, stop\n");
- break;
- }
- } while (creg.add != TABLE_FLG_END);
-}
-
-int regv3_con_show(struct seq_file *seq, void *v)
-{
- dbg_reg_tab(seq, &rtab_contr[0]);
- return 0;
-}
-
-static const struct reg_t rtab_cue_int[] = {
- /*--------------------------*/
- {NR2_CUE_CON_DIF0, 0, 32, 0x1400, "NR2_CUE_CON_DIF0",
- NULL,
- NULL},
- {NR2_CUE_CON_DIF1, 0, 32, 0x80064, "NR2_CUE_CON_DIF1",
- NULL,
- NULL},
- {NR2_CUE_CON_DIF2, 0, 32, 0x80064, "NR2_CUE_CON_DIF2",
- NULL,
- NULL},
- {NR2_CUE_CON_DIF3, 0, 32, 0x80a0a, "NR2_CUE_CON_DIF3",
- NULL,
- NULL},
- {NR2_CUE_PRG_DIF, 0, 32, 0x80a0a, "NR2_CUE_PRG_DIF",
- NULL,
- NULL},
- {TABLE_FLG_END, 0, 0, 0, "end", "end", ""}
- /*--------------------------*/
-};
-
-/************************************************
- * register table
- ************************************************/
-static bool di_g_rtab_cue(const struct reg_t **tab, unsigned int *tabsize)
-{
- *tab = &rtab_cue_int[0];
- *tabsize = ARRAY_SIZE(rtab_cue_int);
-
- return true;
-}
-
-static unsigned int dim_reg_read(unsigned int addr)
-{
- return aml_read_vcbus(addr);
-}
-
-static const struct reg_acc di_pre_regset = {
- .wr = dimv3_DI_Wr,
- .rd = dim_reg_read,
- .bwr = dimv3_RDMA_WR_BITS,
- .brd = dimv3_RDMA_RD_BITS,
-};
-
-static bool di_wr_tab(const struct reg_acc *ops,
- const struct reg_t *ptab, unsigned int tabsize)
-{
- int i;
- const struct reg_t *pl;
-
- pl = ptab;
-
- if (!ops ||
- !tabsize ||
- !ptab)
- return false;
-
- for (i = 0; i < tabsize; i++) {
- if (pl->add == TABLE_FLG_END ||
- i > TABLE_LEN_MAX) {
- break;
- }
-
- if (pl->wid == 32)
- ops->wr(pl->add, pl->df_val);
- else
- ops->bwr(pl->add, pl->df_val, pl->bit, pl->wid);
-
- pl++;
- }
-
- return true;
-}
-
-bool dimv3_wr_cue_int(void)
-{
- const struct reg_t *ptab;
- unsigned int tabsize;
-
- di_g_rtab_cue(&ptab, &tabsize);
- di_wr_tab(&di_pre_regset,
- ptab,
- tabsize);
- //PR_INF("%s:finish\n", __func__);
-
- return true;
-}
-
-int dimv3_reg_cue_int_show(struct seq_file *seq, void *v)
-{
- dbg_reg_tab(seq, &rtab_cue_int[0]);
- return 0;
-}
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_reg_tab.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_REG_TABL_H__
-#define __DI_REG_TABL_H__
-
-int regv3_con_show(struct seq_file *seq, void *v);
-
-bool dimv3_wr_cue_int(void);
-int dimv3_reg_cue_int_show(struct seq_file *seq, void *v);
-
-#endif /*__DI_REG_TABL_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_sys.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/semaphore.h>
-#include <linux/workqueue.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/major.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/cdev.h>
-#include <linux/proc_fs.h>
-#include <linux/list.h>
-#include <linux/of_reserved_mem.h>
-#include <linux/of_irq.h>
-#include <linux/uaccess.h>
-#include <linux/of_fdt.h>
-#include <linux/cma.h>
-#include <linux/dma-contiguous.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/of_device.h>
-
-#include <linux/amlogic/media/vfm/vframe.h>
-
-/*dma_get_cma_size_int_byte*/
-#include <linux/amlogic/media/codec_mm/codec_mm.h>
-
-#include "deinterlace_dbg.h"
-#include "deinterlace.h"
-#include "di_data_l.h"
-#include "di_data.h"
-#include "di_dbg.h"
-#include "di_vframe.h"
-#include "di_vfm_test.h"
-#include "di_task.h"
-#include "di_prc.h"
-#include "di_sys.h"
-#include "di_api.h"
-#include "di_que.h"
-#include "di_pre_hw.h"
-
-#include "register.h"
-#include "nr_downscale.h"
-
-static di_dev_t *di_pdev;
-
-struct di_dev_s *getv3_dim_de_devp(void)
-{
- return di_pdev;
-}
-
-unsigned int div3_get_dts_nrds_en(void)
-{
- return getv3_dim_de_devp()->nrds_enable;
-}
-
-u8 *dimv3_vmap(ulong addr, u32 size, bool *bflg)
-{
- u8 *vaddr = NULL;
- ulong phys = addr;
- u32 offset = phys & ~PAGE_MASK;
- u32 npages = PAGE_ALIGN(size) / PAGE_SIZE;
- struct page **pages = NULL;
- pgprot_t pgprot;
- int i;
-
- if (!PageHighMem(phys_to_page(phys)))
- return phys_to_virt(phys);
-
- if (offset)
- npages++;
-
- pages = vmalloc(sizeof(struct page *) * npages);
- if (!pages)
- return NULL;
-
- for (i = 0; i < npages; i++) {
- pages[i] = phys_to_page(phys);
- phys += PAGE_SIZE;
- }
-
- /*nocache*/
- pgprot = pgprot_writecombine(PAGE_KERNEL);
-
- vaddr = vmap(pages, npages, VM_MAP, pgprot);
- if (!vaddr) {
- PR_ERR("the phy(%lx) vmaped fail, size: %d\n",
- addr - offset, npages << PAGE_SHIFT);
- vfree(pages);
- return NULL;
- }
-
- vfree(pages);
-#ifdef HIS_V3
- if (debug_mode & 0x20) {
- dimv3_print("[HIGH-MEM-MAP] %s, pa(%lx) to va(%p), size: %d\n",
- __func__, addr, vaddr + offset,
- npages << PAGE_SHIFT);
- }
-#endif
- *bflg = true;
-
- return vaddr + offset;
-}
-
-void dimv3_unmap_phyaddr(u8 *vaddr)
-{
- void *addr = (void *)(PAGE_MASK & (ulong)vaddr);
-
- vunmap(addr);
-}
-
-void dimv3_mcinfo_v_alloc(struct di_buf_s *pbuf, unsigned int bsize)
-{
- if (!dimp_get(eDI_MP_lmv_lock_win_en) ||
- pbuf->mcinfo_alloc_flg)
- return;
-
- pbuf->mcinfo_adr_v = (unsigned short *)dimv3_vmap(pbuf->mcinfo_adr,
- bsize,
- &pbuf->mcinfo_alloc_flg);
-
- if (!pbuf->mcinfo_adr_v)
- PR_ERR("%s:%d\n", __func__, pbuf->index);
- else
- PR_INF("mcinfo v [%d], ok\n", pbuf->index);
-}
-
-void dimv3_mcinfo_v_release(struct di_buf_s *pbuf)
-{
- if (pbuf->mcinfo_alloc_flg) {
- dimv3_unmap_phyaddr((u8 *)pbuf->mcinfo_adr_v);
- pbuf->mcinfo_alloc_flg = false;
- PR_INF("%s [%d], ok\n", __func__, pbuf->index);
- }
-}
-
-/********************************************
- * mem
- *******************************************/
-#ifdef CONFIG_CMA
-/**********************************************************
- * ./include/linux/amlogic/media/codec_mm/codec_mm.h:
- * unsigned long codec_mm_alloc_for_dma(const char *owner,
- * int page_cnt,
- * int align2n,
- * int memflags);
- * int codec_mm_free_for_dma(const char *owner,
- * unsigned long phy_addr);
- * void *codec_mm_phys_to_virt(unsigned long phy_addr);
- ***********************************************************/
-
-#define TVP_MEM_PAGES 0xffff
-
-/**********************************************************
- * alloc mm from codec mm
- * o: out:
- * return:
- * true: seccuss
- * false: failed
- ***********************************************************/
-static bool mm_codec_alloc(const char *owner, size_t count,
- int cma_mode,
- struct dim_mm_s *o)
-{
- int flags = 0;
- bool istvp = false;
-
- if (codec_mm_video_tvp_enabled()) {
- istvp = true;
- flags |= CODEC_MM_FLAGS_TVP;
- } else {
- flags |= CODEC_MM_FLAGS_RESERVED | CODEC_MM_FLAGS_CPU;
- }
-
- if (cma_mode == 4 && !istvp)
- flags = CODEC_MM_FLAGS_CMA_FIRST |
- CODEC_MM_FLAGS_CPU;
-
- o->addr = codec_mm_alloc_for_dma(owner,
- count,
- 0,
- flags);
-
- if (o->addr == 0) {
- /*failed*/
- PR_ERR("%s: failed\n", __func__);
- return false;
- }
-
- if (istvp)
- o->ppage = (struct page *)TVP_MEM_PAGES;
- else
- o->ppage = codec_mm_phys_to_virt(o->addr);
-
- /*PR_INF("%s:page:0x%p,add:0x%lx\n", __func__, o->ppage, o->addr);*/
- return true;
-}
-
-/**********************************************************
- * ./include/linux/dma-contiguous.h:
- * struct page *dma_alloc_from_contiguous(struct device *dev,
- * size_t count,
- * unsigned int order);
- * bool dma_release_from_contiguous(struct device *dev,
- * struct page *pages,
- * int count);
- *
- ***********************************************************/
-
-/**********************************************************
- * alloc mm by cma
- * o: out:
- * return:
- * true: seccuss
- * false: failed
- ***********************************************************/
-static bool mm_cma_alloc(struct device *dev, size_t count,
- struct dim_mm_s *o)
-{
- o->ppage = dma_alloc_from_contiguous(dev, count, 0);
- if (o->ppage) {
- o->addr = page_to_phys(o->ppage);
- return true;
- }
- PR_ERR("%s: failed\n", __func__);
- return false;
-}
-
-static bool dim_mm_alloc(int cma_mode, size_t count, struct dim_mm_s *o)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- bool ret;
-
- if (cma_mode == 3 || cma_mode == 4)
- ret = mm_codec_alloc(DEVICE_NAME,
- count,
- cma_mode,
- o);
- else
- ret = mm_cma_alloc(&de_devp->pdev->dev, count, o);
-
- return ret;
-}
-
-static bool dim_mm_release(int cma_mode,
- struct page *pages,
- int count,
- unsigned long addr)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- bool ret = true;
-
- if (cma_mode == 3 || cma_mode == 4)
- codec_mm_free_for_dma(DEVICE_NAME, addr);
- else
- ret = dma_release_from_contiguous(&de_devp->pdev->dev,
- pages,
- count);
- return ret;
-}
-
-/***********************************************************/
-static unsigned int dim_cma_alloc_total(struct di_dev_s *de_devp)
-{
- struct dim_mm_t_s *mmt = dim_mmt_get();
-
- /*****************************************************/
- struct dim_mm_s omm;
- bool ret;
-
- ret = dim_mm_alloc(cfgg(mem_flg),
- mmt->mem_size >> PAGE_SHIFT,
- &omm);
-
- if (!ret) /*failed*/
- return 0;
-
- mmt->mem_start = omm.addr;
- mmt->total_pages = omm.ppage;
-
- if (cfgnq(mem_flg, eDI_MEM_M_rev) && de_devp->nrds_enable)
- dimv3_nr_ds_buf_init(cfgg(mem_flg), 0, &de_devp->pdev->dev);
-
- return 1;
-}
-
-static bool dim_cma_release_total(void)
-{
- struct dim_mm_t_s *mmt = dim_mmt_get();
- bool ret = false;
- bool lret = false;
-
- if (!mmt) {
- PR_ERR("%s:mmt is null\n", __func__);
- return lret;
- }
- ret = dim_mm_release(cfgg(mem_flg), mmt->total_pages,
- mmt->mem_size >> PAGE_SHIFT,
- mmt->mem_start);
- if (ret) {
- mmt->total_pages = NULL;
- mmt->mem_start = 0;
- mmt->mem_size = 0;
- lret = true;
- } else {
- PR_ERR("%s:fail.\n", __func__);
- }
-
- return lret;
-}
-
-static unsigned int di_cma_alloc(struct di_dev_s *devp, unsigned int channel)
-{
- unsigned int start_time, end_time, delta_time;
- struct di_buf_s *buf_p = NULL;
- int itmp, alloc_cnt = 0;
-// struct di_pre_stru_s *ppre = get_pre_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
-
-// unsigned int tmpa[MAX_FIFO_SIZE];
-// unsigned int psize;
- struct di_mm_s *mm = dim_mm_get(channel);
- bool aret;
- struct dim_mm_s omm;
-
- start_time = dim_get_timerms(0);
- queue_for_each_entry(buf_p, channel, QUEUE_LOCAL_FREE, list) {
- if (buf_p->pages) {
- PR_ERR("1:%s:buf[%d] page:0x%p alloced skip\n",
- __func__, buf_p->index, buf_p->pages);
- continue;
- }
-
- aret = dim_mm_alloc(cfgg(mem_flg),
- mm->cfg.size_local >> PAGE_SHIFT,
- &omm);
-
- if (!aret) {
- buf_p->pages = NULL;
- PR_ERR("2:%s: alloc failed %d fail.\n",
- __func__,
- buf_p->index);
- return 0;
- }
-
- buf_p->pages = omm.ppage;
- buf_p->nr_adr = omm.addr;
- alloc_cnt++;
- mm->sts.num_local++;
-
- dbg_mem("CMA allocate buf[%d]page:0x%p\n",
- buf_p->index, buf_p->pages);
-
- dbg_mem(" addr 0x%lx ok.\n", buf_p->nr_adr);
- if (mm->cfg.buf_alloc_mode == 0) {
- buf_p->mtn_adr = buf_p->nr_adr +
- mm->cfg.nr_size;
- buf_p->cnt_adr = buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size;
- if (dimv3_get_mcmem_alloc()) {
- buf_p->mcvec_adr = buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size +
- mm->cfg.count_size;
- buf_p->mcinfo_adr =
- buf_p->nr_adr +
- mm->cfg.nr_size +
- mm->cfg.mtn_size +
- mm->cfg.count_size +
- mm->cfg.mv_size;
- dimv3_mcinfo_v_alloc(buf_p,
- mm->cfg.mcinfo_size);
- }
- }
- }
- PR_INF("%s:ch[%d] num_local[%d]:[%d]\n", __func__,
- channel, mm->sts.num_local, alloc_cnt);
-
- if (cfgnq(mem_flg, eDI_MEM_M_rev) && de_devp->nrds_enable)
- dimv3_nr_ds_buf_init(cfgg(mem_flg), 0, &de_devp->pdev->dev);
-
- end_time = dim_get_timerms(0);
- delta_time = end_time - start_time;
- PR_INF("%s:ch[%d] use %u ms(%u~%u)\n",
- __func__,
- channel,
- delta_time, start_time, end_time);
- return 1;
-}
-
-static unsigned int dpst_cma_alloc(struct di_dev_s *devp, unsigned int channel)
-{
- struct di_buf_s *buf_p = NULL;
- int itmp, alloc_cnt = 0;
-
- unsigned int tmpa[MAX_FIFO_SIZE];
- unsigned int psize;
- struct di_mm_s *mm = dim_mm_get(channel);
- bool aret;
- struct dim_mm_s omm;
- u64 time1, time2;
-
- time1 = curv3_to_usecs();
-
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) {
- div3_que_list(channel, QUE_POST_FREE, &tmpa[0], &psize);
-
- for (itmp = 0; itmp < psize; itmp++) {
- buf_p = pwv3_qindex_2_buf(channel, tmpa[itmp]);
-
- if (buf_p->pages) {
- dbg_mem("3:%s:buf[%d] page:0x%p skip\n",
- __func__,
- buf_p->index, buf_p->pages);
- continue;
- }
-
- aret = dim_mm_alloc(cfgg(mem_flg),
- mm->cfg.size_post >> PAGE_SHIFT,
- &omm);
-
- if (!aret) {
- buf_p->pages = NULL;
- PR_ERR("4:%s: buf[%d] fail.\n", __func__,
- buf_p->index);
- return 0;
- }
-
- buf_p->pages = omm.ppage;
- buf_p->nr_adr = omm.addr;
- mm->sts.num_post++;
- alloc_cnt++;
-
- dbg_mem("%s:pbuf[%d]page:0x%p\n",
- __func__,
- buf_p->index, buf_p->pages);
-
- dbg_mem(" addr 0x%lx ok.\n", buf_p->nr_adr);
- }
- PR_INF("%s:num_pst[%d]:[%d]\n", __func__, mm->sts.num_post,
- alloc_cnt);
- }
- time2 = curv3_to_usecs();
-
- PR_INF("%s:ch[%d] use %u us\n",
- __func__,
- channel,
- (unsigned int)(time2 - time1));
-
- return 1;
-}
-
-static void di_cma_release(struct di_dev_s *devp, unsigned int channel)
-{
- unsigned int i, ii, rels_cnt = 0, start_time, end_time, delta_time;
- struct di_buf_s *buf_p;
- struct di_buf_s *pbuf_local = get_buf_local(channel);
- //struct di_buf_s *pbuf_post = get_buf_post(channel);
- //struct di_post_stru_s *ppost = get_post_stru(channel);
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- bool ret;
- struct di_mm_s *mm = dim_mm_get(channel);
-
- start_time = dim_get_timerms(0);
- for (i = 0; (i < mm->cfg.num_local); i++) {
- buf_p = &pbuf_local[i];
- ii = USED_LOCAL_BUF_MAX;
-
- if ((ii >= USED_LOCAL_BUF_MAX) &&
- (buf_p->pages)) {
- dimv3_mcinfo_v_release(buf_p);
- ret = dim_mm_release(cfgg(mem_flg),
- buf_p->pages,
- mm->cfg.size_local >> PAGE_SHIFT,
- buf_p->nr_adr);
- if (ret) {
- buf_p->pages = NULL;
- mm->sts.num_local--;
- rels_cnt++;
-
- dbg_mem("release buf[%d] ok.\n", i);
- } else {
- PR_ERR("%s:release buf[%d] fail.\n",
- __func__, i);
- }
- } else {
- if (!IS_ERR_OR_NULL(buf_p->pages)) {
- dbg_mem("buf[%d] page:0x%p no release.\n",
- buf_p->index, buf_p->pages);
- }
- }
- }
-
- if (de_devp->nrds_enable)
- dimv3_nr_ds_buf_uninit(cfgg(mem_flg), &de_devp->pdev->dev);
-
- if (mm->sts.num_local < 0 || mm->sts.num_post < 0)
- PR_ERR("%s:mm:nub_local=%d,nub_post=%d\n",
- __func__,
- mm->sts.num_local,
- mm->sts.num_post);
- end_time = dim_get_timerms(0);
- delta_time = end_time - start_time;
- PR_INF("%s:ch[%d] release %u buffer use %u ms(%u~%u)\n",
- __func__,
- channel,
- rels_cnt, delta_time, start_time, end_time);
-}
-
-static void dpst_cma_release(struct di_dev_s *devp, unsigned int ch)
-{
- unsigned int i, rels_cnt = 0;
- struct di_buf_s *buf_p;
- //struct di_buf_s *pbuf_local = get_buf_local(channel);
- struct di_buf_s *pbuf_post = get_buf_post(ch);
- //struct di_post_stru_s *ppost = get_post_stru(ch);
- //struct di_dev_s *de_devp = get_dim_de_devp();
- bool ret;
- struct di_mm_s *mm = dim_mm_get(ch);
- u64 time1, time2;
-
- time1 = curv3_to_usecs();
- if (dimp_get(eDI_MP_post_wr_en) && dimp_get(eDI_MP_post_wr_support)) {
- for (i = 0; i < mm->cfg.num_post; i++) {
- buf_p = &pbuf_post[i];
-
- if (div3_que_is_in_que(ch, QUE_POST_KEEP, buf_p))
- continue;
-
- if (!buf_p->pages) {
- PR_INF("2:%s:post buf[%d] is null\n",
- __func__, i);
- continue;
- }
-
- ret = dim_mm_release(cfgg(mem_flg),
- buf_p->pages,
- mm->cfg.size_post >> PAGE_SHIFT,
- buf_p->nr_adr);
- if (ret) {
- buf_p->pages = NULL;
- mm->sts.num_post--;
- rels_cnt++;
- dbg_mem("post buf[%d] ok.\n", i);
- } else {
- PR_ERR("%s:post buf[%d]\n", __func__, i);
- }
- }
- }
- if (mm->sts.num_post < 0)
- PR_ERR("%s:mm:nub_post=%d\n",
- __func__,
- mm->sts.num_post);
-
- time2 = curv3_to_usecs();
-
- PR_INF("%s:ch[%d] %u buffer use %u us\n",
- __func__,
- ch,
- rels_cnt, (unsigned int)(time2 - time1));
-}
-#endif
-
-bool dimv3_cma_top_alloc(unsigned int ch)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- bool ret = false;
-
-#ifdef CONFIG_CMA
- if (di_cma_alloc(de_devp, ch))
- ret = true;
-
- if (ret && dimv3_tmode_is_localpost(ch)) {
- if (dpst_cma_alloc(de_devp, ch))
- ret = true;
- else
- ret = false;
- }
-#endif
- return ret;
-}
-
-bool dimv3_cma_top_release(unsigned int ch)
-{
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- //bool ret;
-
-#ifdef CONFIG_CMA
- di_cma_release(de_devp, ch);
- if (dimv3_tmode_is_localpost(ch))
- dpst_cma_release(de_devp, ch);
-#endif
- return true;
-}
-
-bool dimv3_mm_alloc_api(int cma_mode, size_t count, struct dim_mm_s *o)
-{
- bool ret = false;
-#ifdef CONFIG_CMA
- ret = dim_mm_alloc(cma_mode, count, o);
-#endif
- return ret;
-}
-
-bool dimv3_mm_release_api(int cma_mode,
- struct page *pages,
- int count,
- unsigned long addr)
-{
- bool ret = false;
-
-#ifdef CONFIG_CMA
- ret = dim_mm_release(cma_mode, pages, count, addr);
-#endif
- return ret;
-}
-
-bool dimv3_rev_mem_check(void)
-{
- struct di_dev_s *di_devp = getv3_dim_de_devp();
- struct dim_mm_t_s *mmt = dim_mmt_get();
- unsigned int ch;
- unsigned int o_size;
- unsigned long rmstart;
- unsigned int rmsize;
- unsigned int flg_map;
-
- if (!di_devp) {
- PR_ERR("%s:no dev\n", __func__);
- return false;
- }
- if (!mmt) {
- PR_ERR("%s:mmt\n", __func__);
- return false;
- }
-
- if (cfgeq(mem_flg, eDI_MEM_M_rev) && di_devp->mem_flg)
- return true;
-
- PR_INF("%s\n", __func__);
- dil_get_rev_mem(&rmstart, &rmsize);
- dil_get_flg(&flg_map);
- if (!rmstart) {
- PR_ERR("%s:reserved mem start add is 0\n", __func__);
- return false;
- }
-
- mmt->mem_start = rmstart;
- mmt->mem_size = rmsize;
-
- if (!flg_map)
- di_devp->flags |= DI_MAP_FLAG;
-
- o_size = rmsize / DI_CHANNEL_NUB;
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- di_set_mem_info(ch,
- mmt->mem_start + (o_size * ch), o_size);
- PR_INF("rmem:ch[%d]:start:0x%lx, size:%uB\n",
- ch,
- (mmt->mem_start + (o_size * ch)),
- o_size);
- }
- PR_INF("rmem:0x%lx, size %uMB.\n",
- mmt->mem_start, (mmt->mem_size >> 20));
-
- di_devp->mem_flg = true;
-
- return true;
-}
-
-static void dim_mem_remove(void)
-{
-#ifdef CONFIG_CMA
- dim_cma_release_total();
-#endif
-}
-
-static void dim_mem_prob(void)
-{
- unsigned int mem_flg = cfgg(mem_flg);
- struct di_dev_s *di_devp = getv3_dim_de_devp();
- struct dim_mm_t_s *mmt = dim_mmt_get();
-
- if (mem_flg >= eDI_MEM_M_max) {
- cfgs(mem_flg, eDI_MEM_M_cma);
- PR_ERR("%s:mem_flg overflow[%d], set to def\n",
- __func__, mem_flg);
- mem_flg = cfgg(mem_flg);
- }
-
- switch (mem_flg) {
- case eDI_MEM_M_rev:
- dimv3_rev_mem_check();
- dipv3_cma_st_set_ready_all();
- break;
-#ifdef CONFIG_CMA
- case eDI_MEM_M_cma:
- di_devp->flags |= DI_MAP_FLAG;
- mmt->mem_size
- = dma_get_cma_size_int_byte(&di_devp->pdev->dev);
- PR_INF("mem size from dts:0x%x\n", mmt->mem_size);
- break;
-
- case eDI_MEM_M_cma_all:
- di_devp->flags |= DI_MAP_FLAG;
- mmt->mem_size
- = dma_get_cma_size_int_byte(&di_devp->pdev->dev);
- PR_INF("mem size from dts:0x%x\n", mmt->mem_size);
- if (dim_cma_alloc_total(di_devp))
- dipv3_cma_st_set_ready_all();
- break;
- case eDI_MEM_M_codec_a:
- case eDI_MEM_M_codec_b:
- di_devp->flags |= DI_MAP_FLAG;
-
- if (mmt->mem_size <= 0x800000) {/*need check??*/
- mmt->mem_size = 0x2800000;
-
- if (mem_flg != eDI_MEM_M_codec_a) {
- //no di cma, try use
- //cma from codec mm
- //di_devp->flag_cma = 4;
- cfgs(mem_flg, eDI_MEM_M_codec_b);
- }
- }
- break;
-#endif
- case eDI_MEM_M_max:
- default:
- break;
- }
-}
-
-/********************************************/
-static ssize_t
-show_config(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- int pos = 0;
-
- return pos;
-}
-
-static ssize_t show_tvp_region(struct device *dev,
- struct device_attribute *attr, char *buff)
-{
- ssize_t len = 0;
- /*struct di_dev_s *de_devp = get_dim_de_devp();*/
- struct dim_mm_t_s *mmt = dim_mmt_get();
-
- if (!mmt)
- return 0;
- len = sprintf(buff, "segment DI:%lx - %lx (size:0x%x)\n",
- mmt->mem_start,
- mmt->mem_start + mmt->mem_size - 1,
- mmt->mem_size);
- return len;
-}
-
-static
-ssize_t
-show_log(struct device *dev, struct device_attribute *attr, char *buf)
-{
- return dimv3_read_log(buf);
-}
-
-static ssize_t
-show_frame_format(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- int ret = 0;
- unsigned int channel = get_current_channel(); /*debug only*/
- struct di_pre_stru_s *ppre = get_pre_stru(channel);
-
- if (get_init_flag(channel))
- ret += sprintf(buf + ret, "%s\n",
- ppre->cur_prog_flag
- ? "progressive" : "interlace");
-
- else
- ret += sprintf(buf + ret, "%s\n", "null");
-
- return ret;
-}
-
-static DEVICE_ATTR(frame_format, 0444, show_frame_format, NULL);
-static DEVICE_ATTR(config, 0640, show_config, storev3_config);
-static DEVICE_ATTR(debug, 0200, NULL, storev3_dbg);
-static DEVICE_ATTR(dump_pic, 0200, NULL, storev3_dump_mem);
-static DEVICE_ATTR(log, 0640, show_log, storev3_log);
-static DEVICE_ATTR(provider_vframe_status, 0444, showv3_vframe_status, NULL);
-static DEVICE_ATTR(tvp_region, 0444, show_tvp_region, NULL);
-
-/********************************************/
-static int di_open(struct inode *node, struct file *file)
-{
- di_dev_t *di_in_devp;
-
-/* Get the per-device structure that contains this cdev */
- di_in_devp = container_of(node->i_cdev, di_dev_t, cdev);
- file->private_data = di_in_devp;
-
- return 0;
-}
-
-static int di_release(struct inode *node, struct file *file)
-{
-/* di_dev_t *di_in_devp = file->private_data; */
-
-/* Reset file pointer */
-
-/* Release some other fields */
- file->private_data = NULL;
- return 0;
-}
-
-static long di_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- long ret = 0;
-
- if (_IOC_TYPE(cmd) != _DI_) {
- PR_ERR("%s invalid command: %u\n", __func__, cmd);
- return -EFAULT;
- }
-
-#ifdef HIS_V3
- dbg_reg("no pq\n");
- return 0;
-#endif
- switch (cmd) {
- case AMDI_IOC_SET_PQ_PARM:
- ret = dimv3_pq_load_io(arg);
-
- break;
- default:
- break;
- }
- return ret;
-}
-
-#ifdef CONFIG_COMPAT
-static long di_compat_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- unsigned long ret;
-
- arg = (unsigned long)compat_ptr(arg);
- ret = di_ioctl(file, cmd, arg);
- return ret;
-}
-#endif
-
-static const struct file_operations di_fops = {
- .owner = THIS_MODULE,
- .open = di_open,
- .release = di_release,
- .unlocked_ioctl = di_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = di_compat_ioctl,
-#endif
-};
-
-#define ARY_MATCH (1)
-#ifdef ARY_MATCH
-
-static const struct di_meson_data data_g12a = {
- .name = "dimv3_g12a",
-};
-
-static const struct di_meson_data data_sm1 = {
- .name = "dimv3_sm1",
-};
-
-/* #ifdef CONFIG_USE_OF */
-static const struct of_device_id amlogic_deinterlace_dt_match[] = {
- /*{ .compatible = "amlogic, deinterlace", },*/
- { .compatible = "amlogic, dimv3-g12a",
- .data = &data_g12a,
- }, { .compatible = "amlogic, dimv3-g12b",
- .data = &data_sm1,
- }, { .compatible = "amlogic, dimv3-sm1",
- .data = &data_sm1,
- }, {}
-};
-#endif
-static int dimv3_probe(struct platform_device *pdev)
-{
- int ret = 0;
- struct di_dev_s *di_devp = NULL;
- int i;
- struct di_hpre_s *pre;// = get_hw_pre();
-#ifdef ARY_MATCH
- const struct of_device_id *match;
- struct di_data_l_s *pdata;
-#endif
- PR_INF("%s:*v3*\n", __func__);
-
-#if 1 /*move from init to here*/
-
- di_pdev = kzalloc(sizeof(*di_pdev), GFP_KERNEL);
- if (!di_pdev) {
- PR_ERR("%s fail to allocate memory.\n", __func__);
- goto fail_kmalloc_dev;
- }
-
- /******************/
- ret = alloc_chrdev_region(&di_pdev->devno, 0, DI_COUNT, DEVICE_NAME);
- if (ret < 0) {
- PR_ERR("%s: failed to allocate major number\n", __func__);
- goto fail_alloc_cdev_region;
- }
- PR_INF("%s: major %d\n", __func__, MAJOR(di_pdev->devno));
- di_pdev->pclss = class_create(THIS_MODULE, CLASS_NAME);
- if (IS_ERR(di_pdev->pclss)) {
- ret = PTR_ERR(di_pdev->pclss);
- PR_ERR("%s: failed to create class\n", __func__);
- goto fail_class_create;
- }
-#endif
-
- di_devp = di_pdev;
- /* *********new********* */
- di_pdev->data_l = NULL;
- di_pdev->data_l = kzalloc(sizeof(struct di_data_l_s), GFP_KERNEL);
- if (!di_pdev->data_l) {
- PR_ERR("%s fail to allocate data l.\n", __func__);
- goto fail_kmalloc_datal;
- }
- /*memset(di_pdev->data_l, 0, sizeof(struct di_data_l_s));*/
- //PR_INF("\tdata size: %d\n", sizeof(struct di_data_l_s));
- /************************/
- if (!dipv3_prob()) /*new variable init */
- goto fail_cdev_add;
-
- di_devp->flags |= DI_SUSPEND_FLAG;
- cdev_init(&di_devp->cdev, &di_fops);
- di_devp->cdev.owner = THIS_MODULE;
- ret = cdev_add(&di_devp->cdev, di_devp->devno, DI_COUNT);
- if (ret)
- goto fail_cdev_add;
-
- di_devp->devt = MKDEV(MAJOR(di_devp->devno), 0);
- di_devp->dev = device_create(di_devp->pclss, &pdev->dev,
- di_devp->devt, di_devp, "di%d", 0);
-
- if (!di_devp->dev) {
- pr_error("device_create create error\n");
- goto fail_cdev_add;
- }
- dev_set_drvdata(di_devp->dev, di_devp);
- platform_set_drvdata(pdev, di_devp);
- di_devp->pdev = pdev;
-
-#ifdef ARY_MATCH
- /************************/
- match = of_match_device(amlogic_deinterlace_dt_match,
- &pdev->dev);
- if (!match) {
- PR_ERR("%s,no matched table\n", __func__);
- goto fail_cdev_add;
- }
- pdata = (struct di_data_l_s *)di_pdev->data_l;
- pdata->mdata = match->data;
- PR_INF("match name: %s\n", pdata->mdata->name);
-#endif
-
- ret = of_reserved_mem_device_init(&pdev->dev);
- if (ret != 0)
- PR_INF("no reserved mem.\n");
-
- div3_cfg_top_dts();
-
- /* move to dim_mem_prob dim_rev_mem(di_devp);*/
-
- ret = of_property_read_u32(pdev->dev.of_node,
- "nrds-enable", &di_devp->nrds_enable);
- ret = of_property_read_u32(pdev->dev.of_node,
- "pps-enable", &di_devp->pps_enable);
-
- /*di pre h scaling down :sm1 tm2*/
- /*pre_hsc_down_en;*/
- di_devp->h_sc_down_en = dimp_get(eDI_MP_pre_hsc_down_en);
- di_devp->pps_enable = dimp_get(eDI_MP_pps_en);
-// PR_INF("pps2:[%d]\n", di_devp->h_sc_down_en);
- dim_mem_prob();
-
- /* mutex_init(&di_devp->cma_mutex); */
- INIT_LIST_HEAD(&di_devp->pq_table_list);
-
- atomic_set(&di_devp->pq_flag, 0);
-
- di_devp->pre_irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
- PR_INF("pre_irq:%d\n", di_devp->pre_irq);
- di_devp->post_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
- PR_INF("post_irq:%d\n", di_devp->post_irq);
-
- di_pr_info("%s allocate rdma channel %d.\n", __func__,
- di_devp->rdma_handle);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- dimv3_get_vpu_clkb(&pdev->dev, di_devp);
- #ifdef CLK_TREE_SUPPORT
- clk_prepare_enable(di_devp->vpu_clkb);
- PR_INF("enable vpu clkb.\n");
- #else
- aml_write_hiubus(HHI_VPU_CLKB_CNTL, 0x1000100);
- #endif
- }
- di_devp->flags &= (~DI_SUSPEND_FLAG);
-
- /* set flag to indicate that post_wr is supportted */
- ret = of_property_read_u32(pdev->dev.of_node,
- "post-wr-support",
- &di_devp->post_wr_support);
- if (ret)
- dimp_set(eDI_MP_post_wr_support, 0);/*post_wr_support = 0;*/
- else /*post_wr_support = di_devp->post_wr_support;*/
- dimp_set(eDI_MP_post_wr_support, di_devp->post_wr_support);
-
- ret = of_property_read_u32(pdev->dev.of_node,
- "nr10bit-support",
- &di_devp->nr10bit_support);
- if (ret)
- dimp_set(eDI_MP_nr10bit_support, 0);/*nr10bit_support = 0;*/
- else /*nr10bit_support = di_devp->nr10bit_support;*/
- dimp_set(eDI_MP_nr10bit_support, di_devp->nr10bit_support);
-
-#ifdef DI_USE_FIXED_CANVAS_IDX
- if (dimv3_get_canvas()) {
- pr_dbg("DI get canvas error.\n");
- ret = -EEXIST;
- return ret;
- }
-#endif
-
- device_create_file(di_devp->dev, &dev_attr_config);
- device_create_file(di_devp->dev, &dev_attr_debug);
- device_create_file(di_devp->dev, &dev_attr_dump_pic);
- device_create_file(di_devp->dev, &dev_attr_log);
- device_create_file(di_devp->dev, &dev_attr_provider_vframe_status);
- device_create_file(di_devp->dev, &dev_attr_frame_format);
- device_create_file(di_devp->dev, &dev_attr_tvp_region);
-
- /*pd_device_files_add*/
- get_ops_pd()->prob(di_devp->dev);
-
- get_ops_nr()->nr_drv_init(di_devp->dev);
-
- for (i = 0; i < DI_CHANNEL_NUB; i++) {
- set_init_flag(i, false);
- set_reg_flag(i, false);
- }
-
- set_or_act_flag(true);
- /*PR_INF("\t 11\n");*/
- ret = devm_request_irq(&pdev->dev, di_devp->pre_irq, &dimv3_irq,
- IRQF_SHARED,
- "pre_di", (void *)"pre_di");
- if (di_devp->post_wr_support) {
- ret = devm_request_irq(&pdev->dev, di_devp->post_irq,
- &dimv3_post_irq,
- IRQF_SHARED, "post_di",
- (void *)"post_di");
- }
-
- di_devp->sema_flg = 1; /*di_sema_init_flag = 1;*/
- dimhv3_hw_init(dimp_get(eDI_MP_pulldown_enable),
- dimp_get(eDI_MP_mcpre_en));
-
- dimv3_set_di_flag();
-
- taskv3_start();
- dimv3_htr_prob();
-
- postv3_mif_sw(false);
- #ifdef TST_NEW_INS_INTERFACE
- dtst_prob();
- #endif
-
- dimv3_debugfs_init(); /*2018-07-18 add debugfs*/
-
- dimhv3_patch_post_update_mc_sw(DI_MC_SW_IC, true);
-#ifdef TST_NEW_INS_RUN_Q
- dil_set_diffver_flag(1);
-#endif
- /**/
- pre = get_hw_pre();
- if (pre && pre->ops.prob_hw)
- pre->ops.prob_hw(pre);
- PR_INF("%s:*v3*ok\n", __func__);
- return ret;
-
-fail_cdev_add:
- PR_INF("%s:fail_cdev_add\n", __func__);
- kfree(di_devp->data_l);
- di_devp->data_l = NULL;
-fail_kmalloc_datal:
- PR_INF("%s:fail_kmalloc datal\n", __func__);
-
-#if 1 /*move from init*/
-/*fail_pdrv_register:*/
- class_destroy(di_pdev->pclss);
-fail_class_create:
- unregister_chrdev_region(di_pdev->devno, DI_COUNT);
-fail_alloc_cdev_region:
- kfree(di_pdev);
- di_pdev = NULL;
-fail_kmalloc_dev:
-
- return ret;
-#endif
- return ret;
-}
-
-static int dimv3_remove(struct platform_device *pdev)
-{
- struct di_dev_s *di_devp = NULL;
- struct di_hpre_s *pre = get_hw_pre();
-
- PR_INF("%s:\n", __func__);
-
- di_devp = platform_get_drvdata(pdev);
-
- dimhv3_hw_uninit();
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
- clk_disable_unprepare(di_devp->vpu_clkb);
-
- di_devp->di_event = 0xff;
-
- dimv3_uninit_buf(1, 0);/*channel 0*/
- di_set_flg_hw_int(false);
-
- taskv3_stop();
-
- /*pre ops*/
- if (pre && pre->ops.remove_hw)
- pre->ops.remove_hw(pre);
-
- hprev3_remove();
- #ifdef TST_NEW_INS_INTERFACE
- dtst_exit();
- #endif
-
- dimv3_rdma_exit();
-
-/* Remove the cdev */
- device_remove_file(di_devp->dev, &dev_attr_config);
- device_remove_file(di_devp->dev, &dev_attr_debug);
- device_remove_file(di_devp->dev, &dev_attr_log);
- device_remove_file(di_devp->dev, &dev_attr_dump_pic);
- device_remove_file(di_devp->dev, &dev_attr_provider_vframe_status);
- device_remove_file(di_devp->dev, &dev_attr_frame_format);
- device_remove_file(di_devp->dev, &dev_attr_tvp_region);
- /*pd_device_files_del*/
- get_ops_pd()->remove(di_devp->dev);
- get_ops_nr()->nr_drv_uninit(di_devp->dev);
- cdev_del(&di_devp->cdev);
-#ifdef HIS_V3
- if (di_devp->flag_cma == 2) {
- if (dma_release_from_contiguous(&pdev->dev,
- di_devp->total_pages,
- di_devp->mem_size >> PAGE_SHIFT)) {
- di_devp->total_pages = NULL;
- di_devp->mem_start = 0;
- pr_dbg("DI CMA total release ok.\n");
- } else {
- pr_dbg("DI CMA total release fail.\n");
- }
- if (di_pdev->nrds_enable) {
- dimv3_nr_ds_buf_uninit(di_pdev->flag_cma,
- &pdev->dev);
- }
- }
-#else
- dim_mem_remove();
-#endif
- device_destroy(di_devp->pclss, di_devp->devno);
-
-/* free drvdata */
-
- dev_set_drvdata(&pdev->dev, NULL);
- platform_set_drvdata(pdev, NULL);
-
-#if 1 /*move to remove*/
- class_destroy(di_pdev->pclss);
-
- dimv3_debugfs_exit();
-
- dipv3_exit();
- unregister_chrdev_region(di_pdev->devno, DI_COUNT);
-#endif
-
- kfree(di_devp->data_l);
- di_devp->data_l = NULL;
- kfree(di_pdev);
- di_pdev = NULL;
- PR_INF("%s:finish\n", __func__);
- return 0;
-}
-
-static void dimv3_shutdown(struct platform_device *pdev)
-{
- struct di_dev_s *di_devp = NULL;
- int i;
-
- di_devp = platform_get_drvdata(pdev);
-
- for (i = 0; i < DI_CHANNEL_NUB; i++)
- set_init_flag(i, false);
-
- if (is_meson_txlx_cpu())
- dimv3_top_gate_control(true, true);
- else
- dimv3_DI_Wr(DI_CLKG_CTRL, 0x2);
-
- if (!is_meson_txlx_cpu())
- diextv3_clk_b_sw(false);
-
- PR_INF("%s.\n", __func__);
-}
-
-#ifdef CONFIG_PM
-
-static void di_clear_for_suspend(struct di_dev_s *di_devp)
-{
- unsigned int channel = get_current_channel(); /*tmp*/
-
- PR_INF("%s\n", __func__);
-
- //di_vframe_unreg(channel);/*have flag*/
- dimv3_htr_stop(channel);
- dipv3_cma_close();
- PR_INF("%s end\n", __func__);
-}
-
-/* must called after lcd */
-static int di_suspend(struct device *dev)
-{
- struct di_dev_s *di_devp = NULL;
-
- di_devp = dev_get_drvdata(dev);
- di_devp->flags |= DI_SUSPEND_FLAG;
-
- di_clear_for_suspend(di_devp);
-
- if (!is_meson_txlx_cpu())
- diextv3_clk_b_sw(false);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXHD))
- clk_disable_unprepare(di_devp->vpu_clkb);
- PR_INF("%s\n", __func__);
- return 0;
-}
-
-/* must called before lcd */
-static int di_resume(struct device *dev)
-{
- struct di_dev_s *di_devp = NULL;
-
- PR_INF("%s\n", __func__);
- di_devp = dev_get_drvdata(dev);
-
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
- clk_prepare_enable(di_devp->vpu_clkb);
-
- di_devp->flags &= ~DI_SUSPEND_FLAG;
-
- /************/
- PR_INF("%s finish\n", __func__);
- return 0;
-}
-
-static const struct dev_pm_ops di_pm_ops = {
- .suspend_late = di_suspend,
- .resume_early = di_resume,
-};
-#endif
-#ifndef ARY_MATCH
-/* #ifdef CONFIG_USE_OF */
-static const struct of_device_id amlogic_deinterlace_dt_match[] = {
- /*{ .compatible = "amlogic, deinterlace", },*/
- { .compatible = "amlogic, dim-g12a", },
- {}
-};
-#endif
-/* #else */
-/* #define amlogic_deinterlace_dt_match NULL */
-/* #endif */
-
-static struct platform_driver di_driver = {
- .probe = dimv3_probe,
- .remove = dimv3_remove,
- .shutdown = dimv3_shutdown,
- .driver = {
- .name = DEVICE_NAME,
- .owner = THIS_MODULE,
- .of_match_table = amlogic_deinterlace_dt_match,
-#ifdef CONFIG_PM
- .pm = &di_pm_ops,
-#endif
- }
-};
-
-static int __init dimv3_module_init(void)
-{
- int ret = 0;
-
- PR_INF("%s\n", __func__);
-
- ret = platform_driver_register(&di_driver);
- if (ret != 0) {
- PR_ERR("%s: failed to register driver\n", __func__);
- /*goto fail_pdrv_register;*/
- return -ENODEV;
- }
- PR_INF("%s finish\n", __func__);
- return 0;
-}
-
-static void __exit dimv3_module_exit(void)
-{
- platform_driver_unregister(&di_driver);
- PR_INF("%s: ok.\n", __func__);
-}
-
-module_init(dimv3_module_init);
-module_exit(dimv3_module_exit);
-
-MODULE_DESCRIPTION("AMLOGIC di_multi_v3 driver");
-MODULE_LICENSE("GPL");
-MODULE_VERSION("4.0.0");
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_sys.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_SYS_H__
-#define __DI_SYS_H__
-
-#define DEVICE_NAME "di_multi_v3"
-#define CLASS_NAME "deinterlace"
-
-u8 *dimv3_vmap(ulong addr, u32 size, bool *bflg);
-void dimv3_unmap_phyaddr(u8 *vaddr);
-void dimv3_mcinfo_v_alloc(struct di_buf_s *pbuf, unsigned int bsize);
-void dimv3_mcinfo_v_release(struct di_buf_s *pbuf);
-
-struct dim_mm_s {
- struct page *ppage;
- unsigned long addr;
-};
-
-bool dimv3_mm_alloc_api(int cma_mode, size_t count, struct dim_mm_s *o);
-bool dimv3_mm_release_api(int cma_mode,
- struct page *pages,
- int count,
- unsigned long addr);
-bool dimv3_cma_top_alloc(unsigned int ch);
-bool dimv3_cma_top_release(unsigned int ch);
-bool dimv3_rev_mem_check(void);
-/*--Different DI versions flag---*/
-void dil_set_diffver_flag(unsigned int para);
-
-unsigned int dil_get_diffver_flag(void);
-/*-------------------------*/
-#endif /*__DI_SYS_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_task.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kthread.h> /*ary add*/
-#include <linux/freezer.h>
-#include <linux/semaphore.h>
-#include <linux/kfifo.h>
-#include <linux/spinlock.h>
-
-#include "deinterlace.h"
-#include "di_data_l.h"
-
-#include "di_prc.h"
-
-#include "di_task.h"
-#include "di_vframe.h"
-
-static void task_wakeup(struct di_task *tsk);
-
-unsigned int div3_dbg_task_flg; /*debug only*/
-
-bool taskv3_send_cmd(unsigned int cmd)
-{
- struct di_task *tsk = get_task();
- unsigned int val;
-
- dbg_reg("%s:cmd[%d]:\n", __func__, cmd);
- if (kfifo_is_full(&tsk->fifo_cmd)) {
- if (kfifo_out(&tsk->fifo_cmd, &val, sizeof(unsigned int))
- != sizeof(unsigned int)) {
- PR_ERR("%s:can't out\n", __func__);
- return false;
- }
-
- PR_ERR("%s:lost cmd[%d]\n", __func__, val);
- tsk->err_cmd_cnt++;
- /*return false;*/
- }
- kfifo_in_spinlocked(&tsk->fifo_cmd, &cmd, sizeof(unsigned int),
- &tsk->lock_cmd);
-
- task_wakeup(tsk);
- return true;
-}
-
-void taskv3_send_ready(void)
-{
- struct di_task *tsk = get_task();
-
- task_wakeup(tsk);
-}
-
-#ifdef HIS_V3
-bool task_have_vf(unsigned int ch)
-{
- struct di_task *tsk = get_task();
-
- task_wakeup(tsk);
-}
-#endif
-bool taskv3_get_cmd(unsigned int *cmd)
-{
- struct di_task *tsk = get_task();
- unsigned int val;
-
- if (kfifo_is_empty(&tsk->fifo_cmd))
- return false;
-
- if (kfifo_out(&tsk->fifo_cmd, &val, sizeof(unsigned int))
- != sizeof(unsigned int))
- return false;
-
- *cmd = val;
- return true;
-}
-
-void taskv3_polling_cmd(void)
-{
- int i;
- union DI_L_CMD_BITS cmdbyte;
-
- for (i = 0; i < MAX_KFIFO_L_CMD_NUB; i++) {
- if (!taskv3_get_cmd(&cmdbyte.cmd32))
- break;
- if (cmdbyte.b.id == ECMD_RL_KEEP) {
- dimv3_post_keep_cmd_proc(cmdbyte.b.ch, cmdbyte.b.p2);
- continue;
- } else if (cmdbyte.b.id == ECMD_RL_KEEP_ALL) {
- dimv3_post_keep_release_all_2free(cmdbyte.b.ch);
- continue;
- }
- dipv3_chst_process_reg(cmdbyte.b.ch);
- }
-}
-
-static int task_is_exiting(struct di_task *tsk)
-{
- if (tsk->exit)
- return 1;
-
-/* if (afepriv->dvbdev->writers == 1)
- * if (time_after_eq(jiffies, fepriv->release_jiffies +
- * dvb_shutdown_timeout * HZ))
- * return 1;
- */
- return 0;
-}
-
-static int task_should_wakeup(struct di_task *tsk)
-{
- if (tsk->wakeup) {
- tsk->wakeup = 0;
- /*dbg only dbg_tsk("wkg[%d]\n", di_dbg_task_flg);*/
- return 1;
- }
- return task_is_exiting(tsk);
-}
-
-static void task_wakeup(struct di_task *tsk)
-{
- tsk->wakeup = 1;
- wake_up_interruptible(&tsk->wait_queue);
- /*dbg_tsk("wks[%d]\n", di_dbg_task_flg);*/
-}
-
-static int di_test_thread(void *data)
-{
- struct di_task *tsk = data;
- bool semheld = false;
-
- tsk->delay = HZ;
- tsk->status = 0;
- tsk->wakeup = 0;
- #ifdef HIS_V3
- tsk->reinitialise = 0;
- tsk->needfinish = 0;
- tsk->finishflg = 0;
- #endif
- set_freezable();
- while (1) {
- up(&tsk->sem);/* is locked when we enter the thread... */
-restart:
- wait_event_interruptible_timeout(tsk->wait_queue,
- task_should_wakeup(tsk) ||
- kthread_should_stop() ||
- freezing(current),
- tsk->delay);
- div3_dbg_task_flg = 1;
-
- if (kthread_should_stop() || task_is_exiting(tsk)) {
- /* got signal or quitting */
- if (!down_interruptible(&tsk->sem))
- semheld = true;
- tsk->exit = 1;
- break;
- }
-
- if (try_to_freeze())
- goto restart;
-
- if (down_interruptible(&tsk->sem))
- break;
-#ifdef HIS_V3
- if (tsk->reinitialise) {
- /*dvb_frontend_init(fe);*/
-
- tsk->reinitialise = 0;
- }
-#endif
- div3_dbg_task_flg = 2;
- taskv3_polling_cmd();
- div3_dbg_task_flg = 3;
- dipv3_chst_process_ch();
- div3_dbg_task_flg = 4;
- if (get_reg_flag_all())
- dipv3_hw_process();
-
- div3_dbg_task_flg = 0;
- }
-
- tsk->thread = NULL;
- if (kthread_should_stop())
- tsk->exit = 1;
- else
- tsk->exit = 0;
- /*mb();*/
-
- if (semheld)
- up(&tsk->sem);
-
- task_wakeup(tsk);/*?*/
- return 0;
-}
-
-void taskv3_stop(void/*struct di_task *tsk*/)
-{
- struct di_task *tsk = get_task();
-
-#if 1 /*not use cmd*/
- PR_INF(".");
- /*--------------------*/
- /*cmd buf*/
- if (tsk->flg_cmd) {
- kfifo_free(&tsk->fifo_cmd);
- tsk->flg_cmd = 0;
- }
- /*tsk->lock_cmd = SPIN_LOCK_UNLOCKED;*/
- spin_lock_init(&tsk->lock_cmd);
- tsk->err_cmd_cnt = 0;
- /*--------------------*/
-#endif
- tsk->exit = 1;
- /*mb();*/
-
- if (!tsk->thread)
- return;
-
- kthread_stop(tsk->thread);
-
- sema_init(&tsk->sem, 1);
- tsk->status = 0;
-
- /* paranoia check in case a signal arrived */
- if (tsk->thread)
- PR_ERR("warning: thread %p won't exit\n", tsk->thread);
-}
-
-int taskv3_start(void)
-{
- int ret;
- int flg_err;
- struct di_task *tsk = get_task();
-
- struct task_struct *fe_thread;
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
-
- PR_INF(".");
- flg_err = 0;
-#if 1 /*not use cmd*/
- /*--------------------*/
- /*cmd buf*/
- /*tsk->lock_cmd = SPIN_LOCK_UNLOCKED;*/
- spin_lock_init(&tsk->lock_cmd);
- tsk->err_cmd_cnt = 0;
- ret = kfifo_alloc(&tsk->fifo_cmd,
- sizeof(unsigned int) * MAX_KFIFO_L_CMD_NUB,
- GFP_KERNEL);
- if (ret < 0) {
- tsk->flg_cmd = false;
- PR_ERR("%s:can't get kfifo\n", __func__);
- return -1;
- }
- tsk->flg_cmd = true;
-
-#endif
- /*--------------------*/
- sema_init(&tsk->sem, 1);
- init_waitqueue_head(&tsk->wait_queue);
-
- if (tsk->thread) {
- if (!tsk->exit)
- return 0;
-
- taskv3_stop();
- }
-
- if (signal_pending(current)) {
- if (tsk->flg_cmd) {
- kfifo_free(&tsk->fifo_cmd);
- tsk->flg_cmd = 0;
- }
- return -EINTR;
- }
- if (down_interruptible(&tsk->sem)) {
- if (tsk->flg_cmd) {
- kfifo_free(&tsk->fifo_cmd);
- tsk->flg_cmd = 0;
- }
- return -EINTR;
- }
-
- tsk->status = 0;
- tsk->exit = 0;
- tsk->thread = NULL;
- /*mb();*/
-
- fe_thread = kthread_run(di_test_thread, tsk, "aml-ditest-0");
- if (IS_ERR(fe_thread)) {
- ret = PTR_ERR(fe_thread);
- PR_ERR(" failed to start kthread (%d)\n", ret);
- up(&tsk->sem);
- tsk->flg_init = 0;
- return ret;
- }
-
- sched_setscheduler_nocheck(fe_thread, SCHED_FIFO, ¶m);
- tsk->flg_init = 1;
- tsk->thread = fe_thread;
- return 0;
-}
-
-void dbgv3_task(void)
-{
- struct di_task *tsk = get_task();
-
- tsk->status = 1;
- task_wakeup(tsk);
-}
-
-/********************************************************************
- * hw timer
- ********************************************************************/
-static enum hrtimer_restart dim_hrt_func(struct hrtimer *timer)
-{
- struct di_timer_s *tm;
- int ch;
-
- tm = get_htimer();
-
- if (tm->con & DIM_HTM_REG) {
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- if (!(tm->con & (DIM_HTM_REG_BIT << ch)))
- continue;
- hrtimer_forward_now(&tm->hrt, ms_to_ktime(15));
- taskv3_send_cmd(LCMD1(eCMD_REG, ch));
- }
-
- return HRTIMER_RESTART;
- }
-
- if (tm->con & DIM_HTM_CONDITION) {
- hrtimer_forward_now(&tm->hrt, ms_to_ktime(15));
- taskv3_send_ready();
- //PR_INF(",a,");
- return HRTIMER_RESTART;
- }
- PR_INF(",b,");
- return HRTIMER_NORESTART;
-}
-
-void dimv3_htr_prob(void)
-{
- struct di_timer_s *tm;
-
- tm = get_htimer();
- if (tm->sts != EHTM_STS_NONE) {
- PR_ERR("%s:sts is not none %d\n", __func__, tm->sts);
- return;
- }
- hrtimer_init(&tm->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- tm->hrt.function = dim_hrt_func;
- tm->sts = EHTM_STS_PROB;
-}
-
-void dimv3_htr_start(unsigned int ch)
-{
- struct di_timer_s *tm;
-
- tm = get_htimer();
-
- tm->con |= ((DIM_HTM_WK_BIT | DIM_HTM_REG_BIT) << ch);
-
- if (tm->sts != EHTM_STS_PROB &&
- tm->sts != EHTM_STS_CANCEL) {
- PR_INF("%s:sts:%d,con[0x%x]\n", __func__, tm->sts, tm->con);
- return;
- }
- dbg_htm("%s:\n", __func__);
-
- hrtimer_start(&tm->hrt, ms_to_ktime(10), HRTIMER_MODE_REL);
- tm->sts = EHTM_STS_WRK;
-}
-
-void dimv3_htr_con_update(unsigned int mask, bool on)
-{
- struct di_timer_s *tm;
-
- tm = get_htimer();
-
- if (on)
- tm->con |= mask;
- else
- tm->con &= (~mask);
-
- dbg_htm("%s:0x%x,%d:0x%x\n", __func__, mask, on, tm->con);
-}
-
-void dimv3_htr_stop(unsigned int ch)
-{
- struct di_timer_s *tm;
-
- tm = get_htimer();
- tm->con &= (~(DIM_HTM_WK_BIT << ch));
-
- if (tm->con & DIM_HTM_WK) {
- PR_INF("%s:ch[%d],con[0x%x]\n", __func__, ch, tm->con);
- return;
- }
-
- if (tm->sts != EHTM_STS_WRK) {
- PR_ERR("%s:err sts:%d\n", __func__, tm->sts);
- return;
- }
- dbg_htm("%s:\n", __func__);
- tm->con = 0;
- hrtimer_cancel(&tm->hrt);
- tm->sts = EHTM_STS_CANCEL;
-}
-
-/*keep same order with EHTM_STS*/
-const char * const dim_htr_sts_name[] = {
- "NONE",
- "PROB",
- "WRK",
- "CANCEL"
-};
-
-const char *dimv3_htr_get_stsname(void)
-{
- struct di_timer_s *tm;
-
- tm = get_htimer();
- if (tm->sts < ARRAY_SIZE(dim_htr_sts_name))
- return dim_htr_sts_name[tm->sts];
-
- return "overflow";
-}
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_task.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_TASK_H__
-#define __DI_TASK_H__
-
-extern unsigned int div3_dbg_task_flg; /*debug only*/
-
-enum eTSK_STATE {
- eTSK_STATE_IDLE,
- eTSK_STATE_WORKING,
-};
-
-void taskv3_stop(void);
-int taskv3_start(void);
-
-void dbgv3_task(void);
-
-bool taskv3_send_cmd(unsigned int cmd);
-void taskv3_send_ready(void);
-void dimv3_htr_prob(void);
-void dimv3_htr_start(unsigned int ch);
-void dimv3_htr_stop(unsigned int ch);
-void dimv3_htr_con_update(unsigned int mask, bool on);
-const char *dimv3_htr_get_stsname(void);
-
-#endif /*__DI_TASK_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_vfm_test.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_VFM_TEST_H__
-#define __DI_VFM_TEST_H__
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-
-int vfmtst_que_show(struct seq_file *s, void *what);
-void vfmtst_exit(void);
-void vfmtst_init(void);
-void dtst_prob(void);
-void dtst_exit(void);
-
-int vfmtst_vfmo_show(struct seq_file *s, void *what);
-int vfmtst_vfmi_show(struct seq_file *s, void *what);
-int vfmtst_bufo_show(struct seq_file *s, void *what);
-void tst_new_trig_eos(bool on);
-
-#endif /*__DI_VFM_TEST_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_vframe.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/semaphore.h>
-#include <linux/kfifo.h>
-#include <linux/spinlock.h>
-
-#include "deinterlace.h"
-#include "di_data_l.h"
-#include "di_pre.h"
-#include "di_pres.h"
-#include "di_prc.h"
-#include "di_dbg.h"
-#include "di_que.h"
-#include "di_task.h"
-
-#include "di_vframe.h"
-#include "di_vfm_test.h"
-
-static DEFINE_SPINLOCK(di_lock3);
-
-#define dim_lock_irqfiq_save(irq_flag) \
- spin_lock_irqsave(&di_lock3, irq_flag)
-
-#define dim_unlock_irqfiq_restore(irq_flag) \
- spin_unlock_irqrestore(&di_lock3, irq_flag)
-
-struct dev_vfram_t *getv3_dev_vframe(unsigned int ch)
-{
- if (ch < DI_CHANNEL_NUB)
- //return &get_datal()->ch_data[ch].vfm;
- return &get_datal()->ch_data[ch].interf.u.dvfm;
-
- PR_ERR("%s ch overflow %d\n", __func__, ch);
- return &get_datal()->ch_data[0].interf.u.dvfm;
-}
-
-#if 1//TST_NEW_INS_RUN_Q
-const char * const div3_rev_name[4] = {
- "dimulti.1",
- "deinterlace",
- "dimulti.2",
- "dimulti.3",
-};
-#else
-const char * const div3_rev_name[4] = {
- "deinterlace",
- "dimulti.1",
- "dimulti.2",
- "dimulti.3",
-};
-
-#endif
-static bool dev_vframe_reg(void *data, struct dim_inter_s *pintf)
-{
- struct vframe_receiver_s *preceiver;
- struct dev_vfram_t *pvfm;
- char *provider_name = (char *)data;
- const char *receiver_name = NULL;
-
- pvfm = &pintf->u.dvfm;
- if (pintf->reg) {
- PR_WARN("duplicate reg\n");
- return false;
- }
- vf_reg_provider(&pvfm->di_vf_prov);
- vf_notify_receiver(pintf->name, VFRAME_EVENT_PROVIDER_START, NULL);
- pintf->reg = 1;
-
- if (!provider_name) {
- PR_WARN("%s:provider null\n", __func__);
- return false;
- }
- preceiver = vf_get_receiver(pintf->name);
-
- if (!preceiver) {
- PR_WARN("%s:preceiver null\n", __func__);
- return false;
- }
-
- receiver_name = preceiver->name;
-
- if (!receiver_name) {
- PR_WARN("%s:receiver null\n", __func__);
- return false;
- }
-
- dbg_ev("reg:%s,%s\n", provider_name, receiver_name);
- return true;
-}
-
-void devv3_vframe_unreg(struct dim_inter_s *pintf)
-{
- struct dev_vfram_t *pvfm;
-
- pvfm = &pintf->u.dvfm;
- if (pintf->reg) {
- vf_unreg_provider(&pvfm->di_vf_prov);
- pintf->reg = 0;
- } else {
- PR_WARN("duplicate ureg\n");
- }
-}
-
-static int di_vf_l_states(struct vframe_states *states, unsigned int ch)
-{
- struct di_mm_s *mm = dim_mm_get(ch);
- struct dim_sum_s *psumx = get_sumx(ch);
-
- if (!states)
- return -1;
- states->vf_pool_size = mm->sts.num_local;
- states->buf_free_num = psumx->b_pre_free;
-
- states->buf_avail_num = psumx->b_pst_ready;
- states->buf_recycle_num = psumx->b_recyc;
- if (dimp_get(eDI_MP_di_dbg_mask) & 0x1) {
- di_pr_info("di-pre-ready-num:%d\n", psumx->b_pre_ready);
- di_pr_info("di-display-num:%d\n", psumx->b_display);
- }
- return 0;
-}
-
-static int div3_ori_event_qurey_state(unsigned int channel)
-{
- /*int in_buf_num = 0;*/
- struct vframe_states states;
-
- #ifdef HIS_V3
- if (recovery_flag)
- return RECEIVER_INACTIVE;
- #endif
- /*fix for ucode reset method be break by di.20151230*/
- di_vf_l_states(&states, channel);
- if (states.buf_avail_num > 0)
- return RECEIVER_ACTIVE;
-
- if (pwv3_vf_notify_receiver(
- channel,
- VFRAME_EVENT_PROVIDER_QUREY_STATE,
- NULL) == RECEIVER_ACTIVE)
- return RECEIVER_ACTIVE;
-
- return RECEIVER_INACTIVE;
-}
-
-#ifdef HIS_V3 /*no use*/
-void di_vframe_reg(unsigned int ch)
-{
- struct dev_vfram_t *pvfm;
-
- pvfm = getv3_dev_vframe(ch);
-
- dev_vframe_reg(pvfm);
-}
-
-void di_vframe_unreg(unsigned int ch)
-{
- struct dev_vfram_t *pvfm;
-
- pvfm = getv3_dev_vframe(ch);
- devv3_vframe_unreg(pvfm);
-}
-#endif
-
-/*--------------------------*/
-
-static const char * const di_receiver_event_cmd[] = {
- "",
- "_UNREG",
- "_LIGHT_UNREG",
- "_START",
- NULL, /* "_VFRAME_READY", */
- NULL, /* "_QUREY_STATE", */
- "_RESET",
- NULL, /* "_FORCE_BLACKOUT", */
- "_REG",
- "_LIGHT_UNREG_RETURN_VFRAME",
- NULL, /* "_DPBUF_CONFIG", */
- NULL, /* "_QUREY_VDIN2NR", */
- NULL, /* "_SET_3D_VFRAME_INTERLEAVE", */
- NULL, /* "_FR_HINT", */
- NULL, /* "_FR_END_HINT", */
- NULL, /* "_QUREY_DISPLAY_INFO", */
- NULL /* "_PROPERTY_CHANGED", */
-};
-
-#define VFRAME_EVENT_PROVIDER_CMD_MAX 16
-
-static int di_receiver_event_fun(int type, void *data, void *arg)
-{
- struct dev_vfram_t *pvfm;
- unsigned int ch;
- int ret = 0;
- struct dim_inter_s *pintf;
-// bool retb = false;
- ch = *(int *)arg;
-
- pintf = get_dev_intf(ch);
- pvfm = getv3_dev_vframe(ch);
-
- if (type <= VFRAME_EVENT_PROVIDER_CMD_MAX &&
- di_receiver_event_cmd[type]) {
- dbg_ev("ch[%d]:%s,%d:%s\n", ch, __func__,
- type,
- di_receiver_event_cmd[type]);
- }
-
- switch (type) {
- case VFRAME_EVENT_PROVIDER_UNREG:
- devv3_vframe_unreg(pintf);
- dipv3_event_unreg_chst(ch);
- //dev_vframe_unreg(pintf);
-/* task_send_cmd(LCMD1(eCMD_UNREG, 0));*/
- break;
- case VFRAME_EVENT_PROVIDER_REG:
- if (dev_vframe_reg(data, pintf))
- ret = dipv3_event_reg_chst(ch);
- break;
- case VFRAME_EVENT_PROVIDER_START:
- break;
-
- case VFRAME_EVENT_PROVIDER_LIGHT_UNREG:
- ret = div3_ori_event_light_unreg(ch);
- break;
- case VFRAME_EVENT_PROVIDER_VFRAME_READY:
- /*ret = di_ori_event_ready(ch);*/
- if (isv3_bypss_complete(pintf)) {
- vf_notify_receiver
- (pintf->name,
- VFRAME_EVENT_PROVIDER_VFRAME_READY,
- NULL);
- }
- ret = 0;
- break;
- case VFRAME_EVENT_PROVIDER_QUREY_STATE:
- ret = div3_ori_event_qurey_state(ch);
- break;
- case VFRAME_EVENT_PROVIDER_RESET:
- ret = div3_ori_event_reset(ch);
- break;
- case VFRAME_EVENT_PROVIDER_LIGHT_UNREG_RETURN_VFRAME:
- ret = div3_ori_event_light_unreg_revframe(ch);
- break;
- case VFRAME_EVENT_PROVIDER_QUREY_VDIN2NR:
- ret = div3_ori_event_qurey_vdin2nr(ch);
- break;
- case VFRAME_EVENT_PROVIDER_SET_3D_VFRAME_INTERLEAVE:
- div3_ori_event_set_3D(type, data, ch);
- break;
- case VFRAME_EVENT_PROVIDER_FR_HINT:
- case VFRAME_EVENT_PROVIDER_FR_END_HINT:
- vf_notify_receiver(pintf->name, type, data);
- break;
-
- default:
- break;
- }
-
- return ret;
-}
-
-static const struct vframe_receiver_op_s di_vf_receiver = {
- .event_cb = di_receiver_event_fun
-};
-
-bool vfv3_type_is_prog(unsigned int type)
-{
- bool ret = (type & VIDTYPE_TYPEMASK) == 0 ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_interlace(unsigned int type)
-{
- bool ret = (type & VIDTYPE_INTERLACE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_top(unsigned int type)
-{
- bool ret = ((type & VIDTYPE_TYPEMASK) == VIDTYPE_INTERLACE_TOP)
- ? true : false;
- return ret;
-}
-
-bool vfv3_type_is_bottom(unsigned int type)
-{
- bool ret = ((type & VIDTYPE_INTERLACE_BOTTOM)
- == VIDTYPE_INTERLACE_BOTTOM)
- ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_inter_first(unsigned int type)
-{
- bool ret = (type & VIDTYPE_INTERLACE_TOP) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_mvc(unsigned int type)
-{
- bool ret = (type & VIDTYPE_MVC) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_no_video_en(unsigned int type)
-{
- bool ret = (type & VIDTYPE_NO_VIDEO_ENABLE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_VIU422(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VIU_422) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_VIU_FIELD(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VIU_FIELD) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_VIU_SINGLE(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VIU_SINGLE_PLANE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_VIU444(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VIU_444) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_VIUNV21(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VIU_NV21) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_vscale_dis(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VSCALE_DISABLE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_canvas_toggle(unsigned int type)
-{
- bool ret = (type & VIDTYPE_CANVAS_TOGGLE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_pre_interlace(unsigned int type)
-{
- bool ret = (type & VIDTYPE_PRE_INTERLACE) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_highrun(unsigned int type)
-{
- bool ret = (type & VIDTYPE_HIGHRUN) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_compress(unsigned int type)
-{
- bool ret = (type & VIDTYPE_COMPRESS) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_pic(unsigned int type)
-{
- bool ret = (type & VIDTYPE_PIC) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_scatter(unsigned int type)
-{
- bool ret = (type & VIDTYPE_SCATTER) ? true : false;
-
- return ret;
-}
-
-bool vfv3_type_is_vd2(unsigned int type)
-{
- bool ret = (type & VIDTYPE_VD2) ? true : false;
-
- return ret;
-}
-
-bool isv3_bypss_complete(struct dim_inter_s *pintf)
-{
- return pintf->bypass_complete;
-}
-
-#ifdef HIS_V3
-bool is_reg(unsigned int ch)
-{
- struct dev_vfram_t *pvfm;
-
- pvfm = getv3_dev_vframe(ch);
-
- return pvfm->reg;
-}
-#endif
-
-void setv3_bypass_complete(struct dim_inter_s *pintf, bool on)
-{
- if (on)
- pintf->bypass_complete = true;
- else
- pintf->bypass_complete = false;
-}
-
-void setv3_bypass2_complete(unsigned int ch, bool on)
-{
- struct dim_inter_s *pintf;
-
- pintf = get_dev_intf(ch);
- setv3_bypass_complete(pintf, on);
-}
-
-bool isv3_bypss2_complete(unsigned int ch)
-{
- struct dim_inter_s *pintf;
-
- pintf = get_dev_intf(ch);
-
- return isv3_bypss_complete(pintf);
-}
-
-/**********************************************************
- * vf_fill_post_ready
- * default for CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- * for pw en
- **********************************************************/
-void vfv3_fill_post_ready(struct di_ch_s *pch, struct di_buf_s *di_buf)
-{
- struct vframe_s *tvfm = NULL;
- struct di_buf_s *nr_buf = NULL;
- struct canvas_config_s *pcvs;
- unsigned int pw_en = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support));
- struct dim_dvfm_s *pdvfm;
- struct dim_dvfm_s *pdvfmg;
-
- if (!pw_en) {
- PR_ERR("%s:not pw mode, do nothing\n", __func__);
- return;
- }
- pdvfm = di_buf->c.pdvfm;
- if (!pdvfm) {
- PR_ERR("%s:no pdvfm, do nothing\n", __func__);
- return;
- }
-
- tvfm = di_buf->vframe;
- memcpy(tvfm, &pdvfm->vframe.vfm, sizeof(*tvfm));
- tvfm->private_data = di_buf;
-
- if (di_buf->c.wmode.is_bypass) { /*bypass*/
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
- pdvfmg = dvfmv3_get(pch, QUED_T_PRE);
- di_buf->c.pdvfm = NULL;
- if (pdvfmg->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- pdvfm->index,
- pdvfmg->index);
- return;
- }
-
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- return;
- }
-
- /*bitdepth*/
- tvfm->bitdepth &= ~(BITDEPTH_YMASK | FULL_PACK_422_MODE);
- tvfm->bitdepth |= pch->cfgt.vfm_bitdepth;
-
- /*type*/
- tvfm->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- /* ? add for vpp skip line ref*/
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
-
- tvfm->type &= ~TB_DETECT_MASK;
-
- /*canvans*/
- pcvs = &tvfm->canvas0_config[0];
- if (di_buf->c.process_fun_index != PROCESS_FUN_NULL) {
- nr_buf = di_buf->c.di_buf_dup_p[1];
-
- pcvs->phy_addr = di_buf->nr_adr;
- pcvs->width = di_buf->canvas_width[NR_CANVAS];
- pcvs->height = di_buf->canvas_height;
- pcvs->block_mode = 0;
-
- if (dimp_get(eDI_MP_show_nrwr)) {
- pcvs->phy_addr = nr_buf->nr_adr;
- pcvs->width = nr_buf->canvas_width[NR_CANVAS];
- pcvs->height = nr_buf->canvas_height;
- }
-
- } else {
- /* p use 2 i buf*/
-
- if (!di_buf->c.wmode.p_use_2i) {
- PR_ERR("%s:not p use 2i\n", __func__);
- return;
- }
- nr_buf = di_buf->c.di_buf[0];
- pcvs->phy_addr = nr_buf->nr_adr;
- pcvs->width = nr_buf->canvas_width[NR_CANVAS],
- pcvs->height = nr_buf->canvas_height << 1;
- pcvs->block_mode = 0;
- }
- tvfm->plane_num = 1;
- tvfm->canvas0Addr = -1;
- tvfm->canvas1Addr = -1;
-
- tvfm->early_process_fun = NULL;
- tvfm->process_fun = NULL;
-
- /* 2019-04-22 Suggestions from brian.zhu*/
- tvfm->mem_handle = NULL;
- tvfm->type |= VIDTYPE_DI_PW;
- /* 2019-04-22 */
-
- /*ary tmp : dvfm recycle*/
- //pch = get_chdata(channel);
- pdvfmg = dvfmv3_get(pch, QUED_T_PRE);
- if (pdvfmg->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- pdvfm->index,
- pdvfmg->index);
- return;
- }
- dbg_vfmv3(tvfm, 6);
-
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
-}
-
-/**********************************************************
- * vf_fill_post_ready_ins
- * default for CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- * for pw en
- * 1. vf no need cp
- * 2. only change type bitdepth
- **********************************************************/
-void vfv3_fill_post_ready_ins(struct di_ch_s *pch, struct di_buf_s *di_buf,
- struct di_buffer *buffer)
-{
- struct vframe_s *tvfm = NULL;
- struct di_buffer *ins;
-#ifdef DIM_OUT_NV21
- struct di_hpst_s *pst = get_hw_pst();
-#else
- struct di_buf_s *nr_buf = NULL;
-#endif
- struct canvas_config_s *pcvs, *pcvsf;
- unsigned int pw_en = (dimp_get(eDI_MP_post_wr_en) &&
- dimp_get(eDI_MP_post_wr_support));
- struct dim_dvfm_s *pdvfm;
- struct dim_dvfm_s *pdvfmg;
-
- if (!pw_en) {
- PR_ERR("%s:not pw mode, do nothing\n", __func__);
- return;
- }
- pdvfm = di_buf->c.pdvfm;
- if (!pdvfm) {
- PR_ERR("%s:no pdvfm, do nothing\n", __func__);
- return;
- }
- if (!buffer) {
- PR_ERR("%s:no ins buf\n", __func__);
- return;
- }
-
- if (!di_buf->c.wmode.is_eos &&
- !buffer->vf) {
- PR_ERR("%s:ins buf no vfm:indx[%d]\n", __func__,
- buffer->mng.index);
- return;
- }
-
- if (di_buf->c.wmode.is_eos) {
- pdvfmg = dvfmv3_get(pch, QUED_T_PRE);
- di_buf->c.pdvfm = NULL;
- if (pdvfmg->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- pdvfm->index,
- pdvfmg->index);
- return;
- }
-
- buffer->flag |= DI_FLAG_EOS;
- buffer->flag |= DI_FLAG_BUF_BY_PASS;
- PR_INF("%s:%d:EOS\n", __func__, buffer->mng.index);
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- return;
- }
-
- if (di_buf->c.wmode.is_bypass) { /*bypass*/
- tvfm = buffer->vf;
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
- pdvfmg = dvfmv3_get(pch, QUED_T_PRE);
- di_buf->c.pdvfm = NULL;
- if (pdvfmg->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- pdvfm->index,
- pdvfmg->index);
- return;
- }
- /*input*/
- ins = (struct di_buffer *)pdvfm->vfm_in;
- tvfm->vf_ext = ins->vf;
- dbg_vfmv3(tvfm->vf_ext, 5);
- buffer->flag |= DI_FLAG_BUF_BY_PASS;
- dimv3_print("%s:%p:bypass flg\n", __func__, buffer);
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- return;
- }
-
- tvfm = buffer->vf;
- dimv3_print("%s:ins_buf[%d],vf[%d]\n", __func__,
- buffer->mng.index, buffer->vf->omx_index);
- dimv3_print("\t:di_buf[%d,%d]\n",
- di_buf->index, di_buf->c.vmode.omx_index);
-
- buffer->vf->vf_ext = NULL;
-#ifdef DIM_OUT_NV21
- /*bitdepth*/
- tvfm->bitdepth = pst->vf_post.bitdepth;
-
- /*type*/
- tvfm->type = pst->vf_post.type;
-
- /* ? add for vpp skip line ref*/
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
-
- /*canvans*/
- tvfm->plane_num = pst->vf_post.plane_num;
-#else
- /*bitdepth*/
- tvfm->bitdepth &= ~(BITDEPTH_YMASK | FULL_PACK_422_MODE);
- tvfm->bitdepth |= pch->cfgt.vfm_bitdepth;
-
- /*type*/
- tvfm->type &= ~(0xf807); /*clear*/
- tvfm->type = VIDTYPE_PROGRESSIVE |
- VIDTYPE_VIU_422 |
- VIDTYPE_VIU_SINGLE_PLANE |
- VIDTYPE_VIU_FIELD;
- /* ? add for vpp skip line ref*/
- tvfm->type |= VIDTYPE_PRE_INTERLACE;
-
- tvfm->type &= ~TB_DETECT_MASK;
-#endif
- pcvs = &tvfm->canvas0_config[0];
- //pcvs->phy_addr = buffer->phy_addr;
- //pcvs->block_mode = 0;
-#ifndef DIM_OUT_NV21
- #if 1
- if (di_buf->c.process_fun_index != PROCESS_FUN_NULL) {
- nr_buf = di_buf->c.di_buf_dup_p[1];
-
- //pcvs->phy_addr = di_buf->nr_adr;
- pcvs->width = di_buf->canvas_width[NR_CANVAS];
- pcvs->height = di_buf->canvas_height;
- pcvs->block_mode = 0;
-
- if (dimp_get(eDI_MP_show_nrwr)) {
- pcvs->phy_addr = nr_buf->nr_adr;
- pcvs->width = nr_buf->canvas_width[NR_CANVAS];
- pcvs->height = nr_buf->canvas_height;
- }
-
- } else {
- /* p use 2 i buf*/
-
- if (!di_buf->c.wmode.p_use_2i) {
- PR_ERR("%s:not p use 2i\n", __func__);
- return;
- }
- nr_buf = di_buf->c.di_buf[0];
- //pcvs->phy_addr = nr_buf->nr_adr;
- pcvs->width = nr_buf->canvas_width[NR_CANVAS],
- pcvs->height = nr_buf->canvas_height << 1;
- pcvs->block_mode = 0;
- }
- #endif
- tvfm->plane_num = 1;
-#endif
- tvfm->canvas0Addr = -1;
- tvfm->canvas1Addr = -1;
-#ifdef DIM_OUT_NV21
- #ifdef HIS_V3
- memcpy(&tvfm->canvas0_config[0],
- &pst->vf_post.canvas0_config[0],
- sizeof(tvfm->canvas0_config[0]));
- memcpy(&tvfm->canvas0_config[1],
- &pst->vf_post.canvas0_config[1],
- sizeof(tvfm->canvas0_config[1]));
- #else
- pcvsf = &pst->vf_post.canvas0_config[0];
- if (pcvs->phy_addr != pcvsf->phy_addr)
- PR_ERR("ready not map phy 0x%x, 0x%x", pcvs->phy_addr,
- pcvsf->phy_addr);
- if (pcvs->width != pcvsf->width)
- PR_ERR("ready not map width 0x%x, 0x%x", pcvs->width,
- pcvsf->width);
- if (pcvs->height != pcvsf->height)
- PR_ERR("ready not map height 0x%x, 0x%x", pcvs->height,
- pcvsf->height);
- pcvs->block_mode = pcvsf->block_mode;
- pcvs->endian = pcvsf->endian;
-
- pcvs = &tvfm->canvas0_config[1];
- pcvsf = &pst->vf_post.canvas0_config[1];
- pcvs->block_mode = pcvsf->block_mode;
- pcvs->endian = pcvsf->endian;
- #endif
-#endif
- tvfm->early_process_fun = NULL;
- tvfm->process_fun = NULL;
-
- /* 2019-04-22 Suggestions from brian.zhu*/
- tvfm->mem_handle = NULL;
- tvfm->type |= VIDTYPE_DI_PW;
- /* 2019-04-22 */
- dbg_vfmv3(tvfm, 4);
- /*ary tmp : dvfm recycle*/
- //pch = get_chdata(channel);
- pdvfmg = dvfmv3_get(pch, QUED_T_PRE);
- if (pdvfmg->index != pdvfm->index) {
- PR_ERR("%s:not map:%d->%d\n", __func__,
- pdvfm->index,
- pdvfmg->index);
- return;
- }
-
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
-}
-
-/**************************************
- * get and put in QUED_T_IN
- **************************************/
-struct dim_dvfm_s *dvfmv3_fill_in(struct di_ch_s *pch)
-{
- unsigned int in_nub, free_nub;
-// unsigned int dvfm_id;
- int i;
- struct vframe_s *pvfm;
- struct vframe_s *pvfm_ori;
- //union dim_itf_u *pvfm;
- //union dim_itf_u *pvfm_ori;
- struct dim_dvfm_s *pdvfm;
- unsigned int cfg_prog_proc;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- unsigned int tmpu;
- struct dim_itf_ops_s *pvfmops;// = &pch->interf.dvfm.pre_ops;
- unsigned int reason = 0;
-
- if (!pch)
- return NULL;
- pvfmops = &pch->interf.opsi;
-
- in_nub = qued_ops.listv3_count(pch, QUED_T_IN);
- free_nub = qued_ops.listv3_count(pch, QUED_T_FREE);
- if (in_nub > DIM_K_VFM_IN_LIMIT ||
- !free_nub) {
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- return pdvfm;
- }
- for (i = 0; i < DIM_K_VFM_IN_LIMIT - in_nub; i++) {
- pvfm_ori = (struct vframe_s *)pvfmops->get(pch);
- if (!pvfm_ori)
- break;
- /*****move from pre cfg*********/
- /* if bad vfm put back*/
- if (pch->pret.bad_frame > 0 ||
- pvfm_ori->width > 10000 ||
- pvfm_ori->height > 10000 ||
- div3_cfgx_get(pch->ch_id, EDI_CFGX_HOLD_VIDEO)) {
- if (pvfm_ori->width > 10000 || pvfm_ori->height > 10000)
- pch->pret.bad_frame = 10;
- pch->pret.bad_frame--;
- PR_WARN("%s:ch[%d]:h[%d],w[%d],cnt[%d]\n",
- __func__, pch->ch_id,
- pvfm_ori->height, pvfm_ori->width,
- pch->pret.bad_frame);
- //pw_vf_put(pvfm_ori, pch->ch_id);
- //pw_vfprov_note_put(&pch->interf.dvfm);
- pvfmops->put((void *)pvfm_ori, pch);
- continue;
- }
- /*******************************/
- pdvfm = dvfmv3_get(pch, QUED_T_FREE);
-
- if (!pdvfm) {
- PR_ERR("%s:2\n", __func__);
- //pw_vf_put(pvfm_ori, pch->ch_id);
- pvfmops->put((void *)pvfm_ori, pch);
- break;
- }
- pvfm = &pdvfm->vframe.vfm;
- pdvfm->vfm_in = pvfm_ori;
- memcpy(pvfm, pvfm_ori, sizeof(*pvfm));
- /*update info*/
- pdvfm->etype = EDIM_DISP_T_IN;
- pdvfm->in_inf.ch = pch->ch_id;
- pdvfm->in_inf.vtype_ori = pvfm->type;
-
- pdvfm->in_inf.src_type = pvfm->source_type;
- pdvfm->in_inf.trans_fmt = pvfm->trans_fmt;
- pdvfm->in_inf.sig_fmt = pvfm->sig_fmt;
- pdvfm->in_inf.h = pvfm->height;
- pdvfm->in_inf.w = pvfm->width;
-
- if (IS_COMP_MODE(pvfm->type)) {
- pdvfm->in_inf.h = pvfm->compHeight;
- pdvfm->in_inf.w = pvfm->compWidth;
- pdvfm->wmode.is_afbc = 1;
- }
-
- pdvfm->wmode.o_h = pdvfm->in_inf.h;
- pdvfm->wmode.o_w = pdvfm->in_inf.w;
-
- pdvfm->wmode.vtype = pvfm->type;
- if (VFMT_IS_I(pvfm->type)) {
- pdvfm->wmode.is_i = 1;
- if (VFMT_IS_TOP(pvfm->type))
- pdvfm->wmode.is_top = 1;
- }
-
- if (IS_VDIN_SRC(pvfm->source_type))
- pdvfm->wmode.is_vdin = 1;
-
- if (dimv3_need_bypass2(&pdvfm->in_inf, pvfm)) {
- pdvfm->wmode.need_bypass = 1;
- pdvfm->wmode.is_bypass = 1;
- }
-
- if (isv3_bypass2(&pdvfm->vframe.vfm, pch, &reason))
- pdvfm->wmode.is_bypass = 1;
-
- if (dimv3_get_trick_mode()) {
- pdvfm->wmode.is_bypass = 1;
- pdvfm->wmode.trick_mode = 1;
- }
-
- /*top botom invert ?*/
- if (!pdvfm->wmode.need_bypass &&
- pdvfm->wmode.is_i) {
- pdvfm->wmode.is_invert_tp =
- (pvfm->type & TB_DETECT_MASK) ? 1 : 0;
- if (dimv3_get_invert_tb())
- pdvfm->wmode.is_invert_tp = 1;
-
- /*sw top and bottom flg*/
- if (pdvfm->wmode.is_invert_tp) {
- /*re set*/
- pdvfm->wmode.vtype =
- topv3_bot_config(pvfm->type);
- }
-
- /*note: change input vframe*/
- /*pvfm->type &= ~TB_DETECT_MASK;*/
- }
-
- if (!pdvfm->wmode.need_bypass &&
- !pdvfm->wmode.is_bypass) {
- pdvfm->wmode.src_w = roundup(pdvfm->in_inf.w,
- pch->cfgt.w_rdup);
- /*debug mode: force h/w*/
- if (pch->cfgt.f_w) {
- pdvfm->wmode.src_w = roundup(pch->cfgt.f_w,
- pch->cfgt.w_rdup);
- pdvfm->wmode.o_w = pch->cfgt.f_w;
- }
-
- pdvfm->wmode.src_h = pdvfm->in_inf.h;
- if (pch->cfgt.f_h) {
- pdvfm->wmode.src_h = pch->cfgt.f_h;
- pdvfm->wmode.o_h = pch->cfgt.f_h;
- }
- #ifdef V_DIV4
- if (pdvfm->wmode.is_i) {
- /*v need % 4*/
- pdvfm->wmode.src_h = roundup(pdvfm->wmode.src_h,
- 4);
- }
- #endif
-
- pdvfm->wmode.tgt_w = pdvfm->wmode.src_w;
- pdvfm->wmode.tgt_h = pdvfm->wmode.src_h;
- /*pp scaler*/
- if (de_devp->pps_enable &&
- dimp_get(eDI_MP_pps_position)) {
- tmpu = dimp_get(eDI_MP_pps_dstw);
- if (tmpu != pdvfm->wmode.src_w) {
- pdvfm->wmode.tgt_w = tmpu;
- pdvfm->wmode.o_w = tmpu;
- }
-
- tmpu = dimp_get(eDI_MP_pps_dsth);
- if (tmpu != pdvfm->wmode.src_h) {
- pdvfm->wmode.tgt_h = tmpu;
- pdvfm->wmode.o_h = tmpu;
- }
- } else if (pch->cfgt.ens.b.h_sc_down) {
- tmpu = dimp_get(eDI_MP_pre_hsc_down_width);
- if (tmpu != pdvfm->wmode.src_w) {
- PR_INF("hscd %d to %d\n",
- pdvfm->wmode.src_w,
- tmpu);
- pdvfm->wmode.tgt_w = tmpu;
- pdvfm->wmode.o_w = tmpu;
- }
- }
-
- cfg_prog_proc =
- (unsigned int)dimp_get(eDI_MP_prog_proc_config);
- if (cfg_prog_proc & 0x20)
- pdvfm->wmode.prog_proc_config = 1;
-
- if (!pdvfm->wmode.is_i) { /*p*/
- if (pdvfm->wmode.is_vdin || cfgg(PMODE) == 0) {
- /*p as p*/
- ;
- } else if (pdvfm->wmode.prog_proc_config) {
- pdvfm->wmode.p_as_i = 1;
- pdvfm->wmode.is_top = 1;
- } else if (cfgg(PMODE) == 2) {
- pdvfm->wmode.p_use_2i = 1;
- }
- }
-
- if (pvfm->video_angle)
- pdvfm->wmode.is_angle = 1;
-
- /*vtype*/
- pdvfm->vmode.vtype = pvfm->type & DIM_VFM_MASK_ALL;
- /* use this to check*/
- pdvfm->vmode.canvas0Addr = pvfm->canvas0Addr;
- pdvfm->vmode.canvas1Addr = pvfm->canvas0Addr;
- pdvfm->vmode.h = pdvfm->wmode.src_h;
- pdvfm->vmode.w = pdvfm->wmode.src_w;
- pdvfm->vmode.omx_index = pvfm->omx_index;
- pdvfm->vmode.ready_jiffies64 = pvfm->ready_jiffies64;
- pdvfm->vmode.bitdepth = pvfm->bitdepth;
- /* vtype->bit_mode */
- if (pvfm->bitdepth & BITDEPTH_Y10) {
- if (pvfm->type & VIDTYPE_VIU_444)
- pdvfm->vmode.bit_mode =
- (pvfm->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- else if (pvfm->type & VIDTYPE_VIU_422)
- pdvfm->vmode.bit_mode =
- (pvfm->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- } else {
- pdvfm->vmode.bit_mode = 0;
- }
- }
-
- pdvfm->di_buf = NULL;
-
- /*put*/
- qued_ops.in(pch, QUED_T_IN, pdvfm->index);
- }
-
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- return pdvfm;
-}
-
-struct dim_dvfm_s *dvfmv3_fill_in_ins(struct di_ch_s *pch)
-{
- unsigned int in_nub, free_nub;
-// unsigned int dvfm_id;
- int i;
- struct vframe_s *pvfm;
- struct vframe_s *pvfm_ori;
- //union dim_itf_u *pvfm;
- //union dim_itf_u *pvfm_ori;
- struct dim_dvfm_s *pdvfm;
- unsigned int cfg_prog_proc;
- struct di_dev_s *de_devp = getv3_dim_de_devp();
- unsigned int tmpu;
- struct dim_itf_ops_s *pvfmops;// = &pch->interf.dvfm.pre_ops;
- struct di_buffer *ins_buf;
- unsigned int reason = 0;
-
- if (!pch)
- return NULL;
-
-// if (pch->pause)
-// return NULL;
-
- pvfmops = &pch->interf.opsi;
-
- in_nub = qued_ops.listv3_count(pch, QUED_T_IN);
- free_nub = qued_ops.listv3_count(pch, QUED_T_FREE);
- if (in_nub > DIM_K_VFM_IN_LIMIT ||
- !free_nub) {
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- return pdvfm;
- }
-
- if (prev3_run_flag == DI_RUN_FLAG_RUN) /*avoid print when ppause*/
- dbg_dbg("%s:ch[%d],in[%d]\n", __func__, pch->ch_id, in_nub);
-
- for (i = 0; i < DIM_K_VFM_IN_LIMIT - in_nub; i++) {
- ins_buf = pvfmops->peek(pch);
- if (!ins_buf)
- break;
- ins_buf = (struct di_buffer *)pvfmops->get(pch);
- if (!ins_buf) {
- PR_ERR("%s:can peek but can't get\n", __func__);
- break;
- }
- /*************************************************************/
- if (ins_buf->flag & DI_FLAG_EOS) {
- dbg_dbg("%s:eos\n", __func__);
-
- pdvfm = dvfmv3_get(pch, QUED_T_FREE);
-
- if (!pdvfm) {
- PR_ERR("%s:2\n", __func__);
- //pw_vf_put(pvfm_ori, pch->ch_id);
- //pvfmops->put((void *)pvfm_ori, pch);
- break;
- }
- pdvfm->vfm_in = ins_buf;
- pdvfm->wmode.is_eos = 1;
- pdvfm->wmode.is_bypass = 1;
-
- pdvfm->di_buf = NULL;
-
- /*put*/
- qued_ops.in(pch, QUED_T_IN, pdvfm->index);
-
- /* pause by EOS */
-// pch->pause |= DI_BIT0;
- break;
- }
- /*************************************************************/
- pvfm_ori = ins_buf->vf;
- if (!pvfm_ori) {
- PR_ERR("%s:no vf\n", __func__);
- break;
- }
- dbg_dbg("\t:ins_buf:c[0x%x],id[%d]\n",
- ins_buf->mng.code,
- ins_buf->mng.index);
- dbg_dbg("\t:ad[%p],h[%d],v[%d],tp[0x%x]\n",
- pvfm_ori,
- pvfm_ori->height,
- pvfm_ori->width,
- pvfm_ori->type);
-
- if (pch->pret.bad_frame > 0 ||
- /*****move from pre cfg*********/
- /* if bad vfm put back*/
- pvfm_ori->width > 10000 ||
- pvfm_ori->height > 10000 ||
- div3_cfgx_get(pch->ch_id, EDI_CFGX_HOLD_VIDEO)) {
- if (pvfm_ori->width > 10000 || pvfm_ori->height > 10000)
- pch->pret.bad_frame = 10;
- pch->pret.bad_frame--;
- PR_WARN("%s:ch[%d]:h[%d],w[%d],cnt[%d]\n",
- __func__, pch->ch_id,
- pvfm_ori->height, pvfm_ori->width,
- pch->pret.bad_frame);
- //pw_vf_put(pvfm_ori, pch->ch_id);
- //pw_vfprov_note_put(&pch->interf.dvfm);
- pvfmops->put((void *)ins_buf, pch);
- continue;
- }
- /*******************************/
- pdvfm = dvfmv3_get(pch, QUED_T_FREE);
-
- if (!pdvfm) {
- PR_ERR("%s:2\n", __func__);
- //pw_vf_put(pvfm_ori, pch->ch_id);
- pvfmops->put((void *)pvfm_ori, pch);
- break;
- }
- pvfm = &pdvfm->vframe.vfm;
- pdvfm->vfm_in = ins_buf;
- memcpy(pvfm, pvfm_ori, sizeof(*pvfm));
- memcpy(&pdvfm->vframe.dbuf, ins_buf,
- sizeof(pdvfm->vframe.dbuf));
- /*update info*/
- pdvfm->etype = EDIM_DISP_T_IN;
- pdvfm->in_inf.ch = pch->ch_id;
- pdvfm->in_inf.vtype_ori = pvfm->type;
-
- pdvfm->in_inf.src_type = pvfm->source_type;
- pdvfm->in_inf.trans_fmt = pvfm->trans_fmt;
- pdvfm->in_inf.sig_fmt = pvfm->sig_fmt;
- pdvfm->in_inf.h = pvfm->height;
- pdvfm->in_inf.w = pvfm->width;
-
- if (IS_COMP_MODE(pvfm->type)) {
- pdvfm->in_inf.h = pvfm->compHeight;
- pdvfm->in_inf.w = pvfm->compWidth;
- pdvfm->wmode.is_afbc = 1;
- }
-
- pdvfm->wmode.o_h = pdvfm->in_inf.h;
- pdvfm->wmode.o_w = pdvfm->in_inf.w;
-
- pdvfm->wmode.vtype = pvfm->type;
- if (VFMT_IS_I(pvfm->type)) {
- pdvfm->wmode.is_i = 1;
- if (VFMT_IS_TOP(pvfm->type))
- pdvfm->wmode.is_top = 1;
- }
-
- if (IS_VDIN_SRC(pvfm->source_type))
- pdvfm->wmode.is_vdin = 1;
-
- if (dimv3_need_bypass2(&pdvfm->in_inf, pvfm)) {
- pdvfm->wmode.need_bypass = 1;
- pdvfm->wmode.is_bypass = 1;
- }
-
- if (isv3_bypass2(&pdvfm->vframe.vfm, pch, &reason))
- pdvfm->wmode.is_bypass = 1;
-
- if (dimv3_get_trick_mode()) {
- pdvfm->wmode.is_bypass = 1;
- pdvfm->wmode.trick_mode = 1;
- }
-
- /*top botom invert ?*/
- if (!pdvfm->wmode.need_bypass &&
- pdvfm->wmode.is_i) {
- pdvfm->wmode.is_invert_tp =
- (pvfm->type & TB_DETECT_MASK) ? 1 : 0;
- if (dimv3_get_invert_tb())
- pdvfm->wmode.is_invert_tp = 1;
-
- /*sw top and bottom flg*/
- if (pdvfm->wmode.is_invert_tp) {
- /*re set*/
- pdvfm->wmode.vtype =
- topv3_bot_config(pvfm->type);
- }
-
- /*note: change input vframe*/
- /*pvfm->type &= ~TB_DETECT_MASK;*/
- }
-
- if (!pdvfm->wmode.need_bypass &&
- !pdvfm->wmode.is_bypass) {
- pdvfm->wmode.src_w = roundup(pdvfm->in_inf.w,
- pch->cfgt.w_rdup);
- /*debug mode: force h/w*/
- if (pch->cfgt.f_w) {
- pdvfm->wmode.src_w = roundup(pch->cfgt.f_w,
- pch->cfgt.w_rdup);
- pdvfm->wmode.o_w = pch->cfgt.f_w;
- }
-
- pdvfm->wmode.src_h = pdvfm->in_inf.h;
- if (pch->cfgt.f_h) {
- pdvfm->wmode.src_h = pch->cfgt.f_h;
- pdvfm->wmode.o_h = pch->cfgt.f_h;
- }
- #ifdef V_DIV4
- if (pdvfm->wmode.is_i) {
- /*v need % 4*/
- pdvfm->wmode.src_h = roundup(pdvfm->wmode.src_h,
- 4);
- }
- #endif
- pdvfm->wmode.tgt_w = pdvfm->wmode.src_w;
- pdvfm->wmode.tgt_h = pdvfm->wmode.src_h;
- /*pp scaler*/
- if (de_devp->pps_enable &&
- dimp_get(eDI_MP_pps_position)) {
- tmpu = dimp_get(eDI_MP_pps_dstw);
- if (tmpu != pdvfm->wmode.src_w) {
- pdvfm->wmode.tgt_w = tmpu;
- pdvfm->wmode.o_w = tmpu;
- }
-
- tmpu = dimp_get(eDI_MP_pps_dsth);
- if (tmpu != pdvfm->wmode.src_h) {
- pdvfm->wmode.tgt_h = tmpu;
- pdvfm->wmode.o_h = tmpu;
- }
- } else if (pch->cfgt.ens.b.h_sc_down) {
- tmpu = dimp_get(eDI_MP_pre_hsc_down_width);
- if (tmpu != pdvfm->wmode.src_w) {
- PR_INF("hscd %d to %d\n",
- pdvfm->wmode.src_w,
- tmpu);
- pdvfm->wmode.tgt_w = tmpu;
- pdvfm->wmode.o_w = tmpu;
- }
- }
-
- cfg_prog_proc =
- (unsigned int)dimp_get(eDI_MP_prog_proc_config);
- if (cfg_prog_proc & 0x20)
- pdvfm->wmode.prog_proc_config = 1;
-
- if (!pdvfm->wmode.is_i) { /*p*/
- if (pdvfm->wmode.is_vdin || cfgg(PMODE) == 0) {
- /*p as p*/
- ;
- } else if (pdvfm->wmode.prog_proc_config) {
- pdvfm->wmode.p_as_i = 1;
- pdvfm->wmode.is_top = 1;
- } else if (cfgg(PMODE) == 2) {
- pdvfm->wmode.p_use_2i = 1;
- }
- }
-
- if (pvfm->video_angle)
- pdvfm->wmode.is_angle = 1;
-
- /*vtype*/
- pdvfm->vmode.vtype = pvfm->type & DIM_VFM_MASK_ALL;
- /* use this to check*/
- pdvfm->vmode.canvas0Addr = pvfm->canvas0Addr;
- pdvfm->vmode.canvas1Addr = pvfm->canvas0Addr;
- pdvfm->vmode.h = pdvfm->wmode.src_h;
- pdvfm->vmode.w = pdvfm->wmode.src_w;
- pdvfm->vmode.omx_index = pvfm->index_disp;
- pdvfm->vmode.ready_jiffies64 = pvfm->ready_jiffies64;
- pdvfm->vmode.bitdepth = pvfm->bitdepth;
- /* vtype->bit_mode */
- if (pvfm->bitdepth & BITDEPTH_Y10) {
- if (pvfm->type & VIDTYPE_VIU_444)
- pdvfm->vmode.bit_mode =
- (pvfm->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 2;
- else if (pvfm->type & VIDTYPE_VIU_422)
- pdvfm->vmode.bit_mode =
- (pvfm->bitdepth & FULL_PACK_422_MODE) ?
- 3 : 1;
- } else {
- pdvfm->vmode.bit_mode = 0;
- }
- }
- if (pdvfm->wmode.is_bypass) {
- ins_buf->flag |= DI_FLAG_BUF_BY_PASS;
- dimv3_print("%s:set bypass\n", __func__);
- }
- pdvfm->di_buf = NULL;
- dbg_dbg("\t:index[%d]bypass:is[%d]:n[%d]:r[%d]\n",
- pdvfm->index,
- pdvfm->wmode.is_bypass,
- pdvfm->wmode.need_bypass, reason);
-
- /*put*/
- qued_ops.in(pch, QUED_T_IN, pdvfm->index);
- }
-
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- return pdvfm;
-}
-
-bool dimv3_bypass_first_frame(unsigned int ch)
-{
- struct di_buf_s *di_buf = NULL;
- struct di_buf_s *di_buf_post = NULL;
- struct vframe_s *vframe;
- struct di_pre_stru_s *ppre = get_pre_stru(ch);
- void **pvframe_in = getv3_vframe_in(ch);
- ulong irq_flag2 = 0;
-// struct vframe_operations_s *pvfmops;
- struct di_ch_s *pch;
-
- struct dim_dvfm_s *pdvfm = NULL;
-
- #ifdef HIS_V3
- pch = get_chdata(ch);
- if (!pch) {
- PR_ERR("%s:no pch\n", __func__);
- return false;
- }
- pvfmops = &pch->interf.u.dvfm.pre_ops;
-
- vframe = pvfmops->peek(pch);//pw_vf_peek(ch);
-
- if (!vframe)
- return false;
- if (div3_que_is_empty(ch, QUE_POST_FREE))
- return false;
-
- vframe = pvfmops->get(pch);//pw_vf_get(ch);
-
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch))
- return 0;
-
- memcpy(di_buf->vframe, vframe, sizeof(struct vframe_s));
- di_buf->vframe->private_data = di_buf;
- pvframe_in[di_buf->index] = vframe;
- di_buf->c.seq = ppre->in_seq;
- ppre->in_seq++;
-
- #ifdef HIS_V3
-
- if (vframe->type & VIDTYPE_COMPRESS) { /*?*/
- vframe->width = vframe->compWidth;
- vframe->height = vframe->compHeight;
- }
-
- div3_que_in(ch, QUE_PRE_READY, di_buf);
- #endif
-
- di_buf_post = div3_que_out_to_di_buf(ch, QUE_POST_FREE);
- memcpy(di_buf_post->vframe, vframe, sizeof(struct vframe_s));
- di_buf_post->vframe->private_data = di_buf_post;
- di_lock_irqfiq_save(irq_flag2);
-
- div3_que_in(ch, QUE_POST_READY, di_buf_post);
-
- di_unlock_irqfiq_restore(irq_flag2);
- pwv3_vf_notify_receiver(ch,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
-
- PR_INF("%s:ok\n", __func__);
- #endif
-
- /*************************************************/
-
- /*****************get dvfm****************/
- pch = get_chdata(ch);
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- //plstdvfm = &pch->lst_dvfm;
-
- if (pdvfm)
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (!pdvfm || !pdvfm->vfm_in) {
- PR_ERR("%s:no pdvfm\n", __func__);
- return 0;
- }
- vframe = &pdvfm->vframe.vfm;
-
- di_buf = div3_que_out_to_di_buf(ch, QUE_IN_FREE);
-
- if (dimv3_check_di_buf(di_buf, 10, ch))
- return 0;
- #ifdef HIS_V3
- memcpy(di_buf->vframe, vframe, sizeof(struct vframe_s));
- di_buf->vframe->private_data = di_buf;
- #endif
- pvframe_in[di_buf->index] = pdvfm->vfm_in;
-
- di_buf->c.seq = ppre->in_seq;
- ppre->in_seq++;
-
- pdvfm->wmode.is_bypass = 1;
- di_buf->c.wmode = pdvfm->wmode;
- //------
-
- di_buf_post = div3_que_out_to_di_buf(ch, QUE_POST_FREE);
- memcpy(di_buf_post->vframe, vframe, sizeof(struct vframe_s));
- di_buf_post->vframe->private_data = di_buf_post;
- di_buf_post->c.wmode = di_buf->c.wmode;
-
- dim_lock_irqfiq_save(irq_flag2);
-
- div3_que_in(ch, QUE_POST_READY, di_buf_post);
-
- dim_unlock_irqfiq_restore(irq_flag2);
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- pwv3_vf_notify_receiver(ch,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
- PR_INF("%s:ok\n", __func__);
- return true;
-}
-
-/**********************************************************
- * pre_inp_canvas_config
- * config canvas from vframe
- **********************************************************/
-void prev3_inp_canvas_config(struct di_buf_s *di_buf)
-{
- struct dim_vmode_s *pvmode;
- struct vframe_s *vf;
- struct di_hpre_s *phpre = get_hw_pre();
-
- pvmode = &di_buf->c.vmode;
- vf = &di_buf->c.pdvfm->vframe.vfm;
-
- if (pvmode->canvas0Addr == (u32)-1) {
- canvas_config_config(phpre->di_inp_idx[0],
- &vf->canvas0_config[0]);
- canvas_config_config(phpre->di_inp_idx[1],
- &vf->canvas0_config[1]);
- pvmode->canvas0Addr = (phpre->di_inp_idx[1] << 8) |
- (phpre->di_inp_idx[0]);
-
- if (vf->plane_num == 2) {
- pvmode->canvas0Addr |= (phpre->di_inp_idx[1] << 16);
- } else if (vf->plane_num == 3) {
- canvas_config_config(phpre->di_inp_idx[2],
- &vf->canvas0_config[2]);
- pvmode->canvas0Addr |= (phpre->di_inp_idx[2] << 16);
- }
- pvmode->canvas1Addr = vf->canvas0Addr;
- }
-}
-
-#ifdef HIS_V3
-static void set_reg(unsigned int ch, int on)
-{
- struct dev_vfram_t *pvfm;
-
- pvfm = getv3_dev_vframe(ch);
-
- if (on)
- pvfm->reg = true;
- else
- pvfm->reg = false;
-}
-#endif
-
-static struct vframe_s *di_vf_peek(void *arg)
-{
- unsigned int ch = *(int *)arg;
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm;
-
- /*dim_print("%s:ch[%d]\n",__func__,ch);*/
- if (div3_is_pause(ch))
- return NULL;
-
- pch = get_chdata(ch);
-
- if (isv3_bypss2_complete(ch)) {
- #ifdef HIS_V3
- return pw_vf_peek(ch);
- #else
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- if (pdvfm && pdvfm->vfm_in &&
- pdvfm->wmode.need_bypass) {
- return pdvfm->vfm_in;
- }
- //task_send_ready();/*hw timer*/
- pch->interf.op_dvfm_fill(pch);//dvfm_fill_in(pch);
- return NULL;
-
- #endif
- }
-
- //task_send_ready();/*hw timer*/
- return div3_vf_l_peek(pch);
-}
-
-static struct vframe_s *di_vf_get(void *arg)
-{
- unsigned int ch = *(int *)arg;
- struct vframe_s *vfm = NULL;
- struct di_ch_s *pch;
- struct dim_dvfm_s *pdvfm;
-
- dimv3_tr_ops.post_get2(5);
- if (div3_is_pause(ch))
- return NULL;
-
- div3_pause_step_done(ch);
-
- /*pvfm = get_dev_vframe(ch);*/
- pch = get_chdata(ch);
-
- if (isv3_bypss2_complete(ch)) {
- #ifdef HIS_V3
- return pw_vf_get(ch);
- #endif
- pdvfm = dvfmv3_peek(pch, QUED_T_IN);
- if (pdvfm && pdvfm->vfm_in &&
- pdvfm->wmode.need_bypass) {
- pdvfm = dvfmv3_get(pch, QUED_T_IN);
- if (pdvfm) {
- vfm = pdvfm->vfm_in;
- /*recycle:*/
- pdvfm->vfm_in = NULL;
- qued_ops.in(pch, QUED_T_RECYCL, pdvfm->index);
- }
- } else {
- vfm = NULL;
- }
-
- pch->interf.op_dvfm_fill(pch);//dvfm_fill_in(pch);
- //task_send_ready();/*hw timer*/
- return vfm;
- }
-
- return div3_vf_l_get(pch);
-}
-
-static void di_vf_put(struct vframe_s *vf, void *arg)
-{
- unsigned int ch = *(int *)arg;
- struct di_ch_s *pch;
-
- pch = get_chdata(ch);
-
- if (isv3_bypss2_complete(ch)) {
- //pw_vf_put(vf, ch);
- //pw_vf_notify_provider(ch,
- // VFRAME_EVENT_RECEIVER_PUT, NULL);
- pch->interf.opsi.put(vf, pch);
- return;
- }
-
- div3_vf_l_put(vf, pch);
-}
-
-static int di_event_cb(int type, void *data, void *private_data)
-{
- if (type == VFRAME_EVENT_RECEIVER_FORCE_UNREG) {
- PR_INF("%s: FORCE_UNREG return\n", __func__);
- return 0;
- }
- return 0;
-}
-
-static int di_vf_states(struct vframe_states *states, void *arg)
-{
- unsigned int ch = *(int *)arg;
-
- if (!states)
- return -1;
-
- dimv3_print("%s:ch[%d]\n", __func__, ch);
-
- di_vf_l_states(states, ch);
- return 0;
-}
-
-static const struct vframe_operations_s deinterlace_vf_provider = {
- .peek = di_vf_peek,
- .get = di_vf_get,
- .put = di_vf_put,
- .event_cb = di_event_cb,
- .vf_states = di_vf_states,
-};
-
-#if 1
-#ifdef HIS_V3
-struct vframe_s *pw_vf_get(unsigned int ch)
-{
- sum_g_inc(ch);
- return vf_get(div3_rev_name[ch]);
-}
-
-struct vframe_s *pw_vf_peek(unsigned int ch)
-{
- return vf_peek(div3_rev_name[ch]);
-}
-
-void pw_vf_put(struct vframe_s *vf, unsigned int ch)
-{
- sum_p_inc(ch);
- vf_put(vf, div3_rev_name[ch]);
-}
-
-int pw_vf_notify_provider(unsigned int channel, int event_type, void *data)
-{
- return vf_notify_provider(div3_rev_name[channel], event_type, data);
-}
-
-int pw_vfprov_note_put(struct dev_vfram_t *pvfm)
-{
- return vf_notify_provider(pvfm->name, VFRAME_EVENT_RECEIVER_PUT, NULL);
-}
-#endif
-int pwv3_vf_notify_receiver(unsigned int channel, int event_type, void *data)
-{
- return vf_notify_receiver(div3_rev_name[channel], event_type, data);
-}
-
-void pwv3_vf_light_unreg_provider(unsigned int ch)
-{
- struct dev_vfram_t *pvfm;
- struct vframe_provider_s *prov;
-
- pvfm = getv3_dev_vframe(ch);
-
- prov = &pvfm->di_vf_prov;
- vf_light_unreg_provider(prov);
-}
-
-/**************************/
-
-#ifdef HIS_V3
-struct vframe_s *pw_vf_get2(void *op_arg)
-{
- struct di_ch_s *pch = (struct di_ch_s *)op_arg;
-
- sum_g_inc(pch->ch_id);
- return vf_get(pch->interf.name);
-}
-
-struct vframe_s *pw_vf_peek2(void *op_arg)
-{
- struct di_ch_s *pch = (struct di_ch_s *)op_arg;
-
- return vf_peek(pch->interf.name);
-}
-
-void pw_vf_put2(struct vframe_s *vf, void *op_arg)
-{
- struct di_ch_s *pch = (struct di_ch_s *)op_arg;
-
- sum_p_inc(pch->ch_id);
- vf_put(vf, pch->interf.name);
- vf_notify_provider(pch->interf.name,
- VFRAME_EVENT_RECEIVER_PUT,
- NULL);
-}
-#endif
-#else
-struct vframe_s *pw_vf_get(unsigned int channel)
-{
- return vf_get(VFM_NAME);
-}
-
-struct vframe_s *pw_vf_peek(unsigned int channel)
-{
- return vf_peek(VFM_NAME);
-}
-
-void pw_vf_put(struct vframe_s *vf, unsigned int channel)
-{
- vf_put(vf, VFM_NAME);
-}
-
-int pw_vf_notify_provider(unsigned int channel, int event_type, void *data)
-{
- return vf_notify_provider(VFM_NAME, event_type, data);
-}
-
-int pwv3_vf_notify_receiver(unsigned int channel, int event_type, void *data)
-{
- return vf_notify_receiver(VFM_NAME, event_type, data);
-}
-
-#endif
-
-/**********************************************************
- * ops for interface
- **********************************************************/
-static void *vfm_peek(struct di_ch_s *pch)
-{
- return vf_peek(pch->interf.name);
-}
-
-static void *vfm_get(struct di_ch_s *pch)
-{
- sum_g_inc(pch->ch_id);
- return vf_get(pch->interf.name);
-}
-
-static void vfm_put(void *data, struct di_ch_s *pch)
-{
- struct vframe_s *vf;
-
- vf = (struct vframe_s *)data;
- sum_p_inc(pch->ch_id);
- vf_put(vf, pch->interf.name);
- vf_notify_provider(pch->interf.name,
- VFRAME_EVENT_RECEIVER_PUT,
- NULL);
-}
-
-const struct dim_itf_ops_s vfm_in_ops = {
- .peek = vfm_peek,
- .get = vfm_get,
- .put = vfm_put,
-};
-
-void devv3_vframe_exit(void)
-{
- struct dev_vfram_t *pvfm;
- int ch;
-
- #ifdef TST_NEW_INS_INTERFACE
- vfmtst_exit();
- PR_INF("new ins interface test end\n");
- return;
- #endif
-
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pvfm = getv3_dev_vframe(ch);
- vf_unreg_provider(&pvfm->di_vf_prov);
- vf_unreg_receiver(&pvfm->di_vf_recv);
- }
- PR_INF("%s finish\n", __func__);
-}
-
-/*for prob*/
-void devv3_vframe_init(void)
-{
- struct dev_vfram_t *pvfm;
- int ch;
- struct di_mng_s *pbm = get_bufmng();
- struct dim_inter_s *pintf;
-
- #ifdef TST_NEW_INS_INTERFACE
- vfmtst_init();
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pintf = get_dev_intf(ch);
- pintf->ch = ch;
- }
- PR_INF("new ins interface test enable\n");
- return;
- #endif
- for (ch = 0; ch < DI_CHANNEL_NUB; ch++) {
- pintf = get_dev_intf(ch);
- pintf->ch = ch;
- if (pbm->tmode_pre[ch] != EDIM_TMODE_1_PW_VFM)
- continue;
- pvfm = getv3_dev_vframe(ch);
- pintf->name = div3_rev_name[ch];
-
- /*set_bypass_complete(pvfm, true);*/ /*test only*/
-
- /*receiver:*/
- vf_receiver_init(&pvfm->di_vf_recv, pintf->name,
- &di_vf_receiver, &pintf->ch);
- vf_reg_receiver(&pvfm->di_vf_recv);
-
- /*provider:*/
- vf_provider_init(&pvfm->di_vf_prov, pintf->name,
- &deinterlace_vf_provider, &pintf->ch);
-
- /*ops for local use*/
- //pvfm->pre_ops.peek = pw_vf_peek2;
- //pvfm->pre_ops.put = pw_vf_put2;
- //pvfm->pre_ops.get = pw_vf_get2;
-
- memcpy(&pintf->opsi, &vfm_in_ops, sizeof(struct dim_itf_ops_s));
- pintf->op_post_done = dimv3_post_de_done_buf_config_vfm;
- pintf->op_dvfm_fill = dvfmv3_fill_in;
- pintf->op_ins_2_doing = NULL;
- }
- pr_info("%s finish\n", __func__);
-}
-
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/di_vframe.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __DI_VFRAME_H__
-#define __DI_VFRAME_H__
-
-#include <linux/amlogic/media/vfm/vframe.h>
-#include <linux/amlogic/media/vfm/vframe_provider.h>
-#include <linux/amlogic/media/vfm/vframe_receiver.h>
-
-void devv3_vframe_init(void);
-void devv3_vframe_exit(void);
-//no use void di_vframe_reg(unsigned int ch);
-//void di_vframe_unreg(unsigned int ch);
-
-bool vfv3_type_is_prog(unsigned int type);
-bool vfv3_type_is_interlace(unsigned int type);
-bool vfv3_type_is_top(unsigned int type);
-bool vfv3_type_is_bottom(unsigned int type);
-bool vfv3_type_is_inter_first(unsigned int type);
-bool vfv3_type_is_mvc(unsigned int type);
-bool vfv3_type_is_no_video_en(unsigned int type);
-bool vfv3_type_is_VIU422(unsigned int type);
-bool vfv3_type_is_VIU_FIELD(unsigned int type);
-bool vfv3_type_is_VIU_SINGLE(unsigned int type);
-bool vfv3_type_is_VIU444(unsigned int type);
-bool vfv3_type_is_VIUNV21(unsigned int type);
-bool vfv3_type_is_vscale_dis(unsigned int type);
-bool vfv3_type_is_canvas_toggle(unsigned int type);
-bool vfv3_type_is_pre_interlace(unsigned int type);
-bool vfv3_type_is_highrun(unsigned int type);
-bool vfv3_type_is_compress(unsigned int type);
-bool vfv3_type_is_pic(unsigned int type);
-bool vfv3_type_is_scatter(unsigned int type);
-bool vfv3_type_is_vd2(unsigned int type);
-
-void vfv3_fill_post_ready(struct di_ch_s *pch, struct di_buf_s *di_buf);
-void vfv3_fill_post_ready_ins(struct di_ch_s *pch, struct di_buf_s *di_buf,
- struct di_buffer *buffer);
-struct dim_dvfm_s *dvfmv3_fill_in(struct di_ch_s *pch);
-struct dim_dvfm_s *dvfmv3_fill_in_ins(struct di_ch_s *pch);
-
-extern const char * const div3_rev_name[4];
-
-#ifdef HIS_V3
-struct vframe_s *pw_vf_get(unsigned int ch);
-struct vframe_s *pw_vf_peek(unsigned int ch);
-void pw_vf_put(struct vframe_s *vf, unsigned int ch);
-int pw_vf_notify_provider(unsigned int channel,
- int event_type,
- void *data);
-int pw_vfprov_note_put(struct dev_vfram_t *pvfm);
-#endif
-int pwv3_vf_notify_receiver(unsigned int channel,
- int event_type,
- void *data);
-
-void pwv3_vf_light_unreg_provider(unsigned int ch);
-
-void setv3_bypass2_complete(unsigned int ch, bool on);
-bool isv3_bypss_complete(struct dim_inter_s *pintf);
-bool isv3_bypss2_complete(unsigned int ch);
-
-#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
-void prev3_inp_canvas_config(struct di_buf_s *di_buf);
-#endif
-
-void dimv3_post_de_done_buf_config_vfm(struct di_ch_s *pch);
-void dimv3_post_de_done_buf_config_ins(struct di_ch_s *pch);
-void dimv3_post_de_done_buf_config_ins_local(struct di_ch_s *pch);
-
-//void ins_2_doing(struct di_ch_s *pch);
-
-#endif /*__DI_VFRAME_H__*/
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/dim_trace.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM dim
-
-#if !defined(_DIM_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _DIM_TRACE_H
-
-#include <linux/tracepoint.h>
-
-/* single lifecycle events */
-DECLARE_EVENT_CLASS
- (di_event_class,
- TP_PROTO(const char *name, int field_cnt, unsigned long time),
- TP_ARGS(name, field_cnt, time),
- TP_STRUCT__entry(
- __string(name, name)
- __field(int, field_cnt)
- __field(unsigned long, time)
- ),
- TP_fast_assign(
- __assign_str(name, name);
- __entry->field_cnt = field_cnt;
- __entry->time = time;
- ),
- TP_printk("[%s-%-4dth-%lums]", __get_str(name),
- __entry->field_cnt, __entry->time)
-);
-
-#define DEFINE_DI_EVENT(name) \
-DEFINE_EVENT(di_event_class, name, \
- TP_PROTO(const char *name, int field_cnt, unsigned long time), \
- TP_ARGS(name, field_cnt, time))
-
-DEFINE_DI_EVENT(dimv3_pre);
-DEFINE_DI_EVENT(dimv3_post);
-/*2019-06-18*/
-DEFINE_DI_EVENT(dimv3_pre_getxx);
-DEFINE_DI_EVENT(dimv3_pre_setxx);
-DEFINE_DI_EVENT(dimv3_pre_ready);
-DEFINE_DI_EVENT(dimv3_pst_ready);
-DEFINE_DI_EVENT(dimv3_pst_getxx);
-DEFINE_DI_EVENT(dimv3_pst_setxx);
-DEFINE_DI_EVENT(dimv3_pst_irxxx);
-DEFINE_DI_EVENT(dimv3_pst_doing);
-DEFINE_DI_EVENT(dimv3_pst_peekx);
-DEFINE_DI_EVENT(dimv3_pst_get2x);
-
-#endif /* _DIM_TRACE_H */
-
-#ifdef HIS_V3
-#undef TRACE_INCLUDE_PATH
-#undef TRACE_INCLUDE_FILE
-#define TRACE_INCLUDE_PATH .
-#define TRACE_INCLUDE_FILE deinterlace_trace
-#include <trace/define_trace.h>
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/nr_downscale.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/vmalloc.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/dma-contiguous.h>
-#include <linux/amlogic/iomap.h>
-#include <linux/amlogic/media/canvas/canvas.h>
-#include <linux/amlogic/media/canvas/canvas_mgr.h>
-#include "register.h"
-#include "nr_downscale.h"
-#include "deinterlace.h"
-
-#include "di_data_l.h"
-#include "di_sys.h"
-#include "di_api.h"
-
-static struct nr_ds_s nrds_dev;
-
-static void nr_ds_hw_init(unsigned int width, unsigned int height)
-{
- unsigned char h_step = 0, v_step = 0;
- unsigned int width_out, height_out;
-
- width_out = NR_DS_WIDTH;
- height_out = NR_DS_HEIGHT;
-
- h_step = width / width_out;
- v_step = height / height_out;
-
- /*Switch MIF to NR_DS*/
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, 3, 5, 2);
- /* config dsbuf_ocol*/
- dimv3_RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, width_out, 0, 8);
- /* config dsbuf_orow*/
- dimv3_RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, height_out, 8, 8);
-
- dimv3_RDMA_WR_BITS(NRDSWR_X, (width_out - 1), 0, 13);
- dimv3_RDMA_WR_BITS(NRDSWR_Y, (height_out - 1), 0, 13);
-
- dimv3_RDMA_WR_BITS(NRDSWR_CAN_SIZE, (height_out - 1), 0, 13);
- dimv3_RDMA_WR_BITS(NRDSWR_CAN_SIZE, (width_out - 1), 16, 13);
- /* little endian */
- dimv3_RDMA_WR_BITS(NRDSWR_CAN_SIZE, 1, 13, 1);
-
- dimv3_RDMA_WR_BITS(NR_DS_CTRL, v_step, 16, 6);
- dimv3_RDMA_WR_BITS(NR_DS_CTRL, h_step, 24, 6);
-}
-
-/*
- * init nr ds buffer
- */
-void dimv3_nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start,
- struct device *dev)
-{
- unsigned int i = 0;
- bool ret;
- struct dim_mm_s omm;
-
- if (cma_flag == 0) {
- nrds_dev.nrds_addr = mem_start;
- } else {
- #ifdef HIS_V3
- nrds_dev.nrds_pages = dma_alloc_from_contiguous(dev,
- NR_DS_PAGE_NUM, 0);
- if (nrds_dev.nrds_pages)
- nrds_dev.nrds_addr = page_to_phys(nrds_dev.nrds_pages);
- else
- PR_ERR("DI: alloc nr ds mem error.\n");
- #else
- ret = dimv3_mm_alloc_api(cma_flag, NR_DS_PAGE_NUM, &omm);
- if (ret) {
- nrds_dev.nrds_pages = omm.ppage;
- nrds_dev.nrds_addr = omm.addr;
- } else {
- PR_ERR("alloc nr ds mem error.\n");
- }
-
- #endif
- }
- for (i = 0; i < NR_DS_BUF_NUM; i++)
- nrds_dev.buf[i] = nrds_dev.nrds_addr + (NR_DS_BUF_SIZE * i);
- nrds_dev.cur_buf_idx = 0;
-}
-
-void dimv3_nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev)
-{
- unsigned int i = 0;
-
- if (cma_flag == 0) {
- nrds_dev.nrds_addr = 0;
- } else {
- if (nrds_dev.nrds_pages) {
- #ifdef HIS_V3
- dma_release_from_contiguous(dev,
- nrds_dev.nrds_pages,
- NR_DS_PAGE_NUM);
- #else
- dimv3_mm_release_api(cma_flag,
- nrds_dev.nrds_pages,
- NR_DS_PAGE_NUM,
- nrds_dev.nrds_addr);
- #endif
- nrds_dev.nrds_addr = 0;
- nrds_dev.nrds_pages = NULL;
- } else
- PR_INF("no release nr ds mem.\n");
- }
- for (i = 0; i < NR_DS_BUF_NUM; i++)
- nrds_dev.buf[i] = 0;
- nrds_dev.cur_buf_idx = 0;
-}
-
-/*
- * hw config, alloc canvas
- */
-void dimv3_nr_ds_init(unsigned int width, unsigned int height)
-{
- nr_ds_hw_init(width, height);
- nrds_dev.field_num = 0;
-
- if (nrds_dev.canvas_idx != 0)
- return;
-
- if (extv3_ops.cvs_alloc_table("nr_ds",
- &nrds_dev.canvas_idx, 1,
- CANVAS_MAP_TYPE_1)) {
- PR_ERR("%s alloc nrds canvas error.\n", __func__);
- return;
- }
- PR_INF("%s alloc nrds canvas %u.\n", __func__, nrds_dev.canvas_idx);
-}
-
-/*
- * config nr ds mif, switch buffer
- */
-void dimv3_nr_ds_mif_config(void)
-{
- unsigned long mem_addr = 0;
-
- mem_addr = nrds_dev.buf[nrds_dev.cur_buf_idx];
- canvas_config(nrds_dev.canvas_idx, mem_addr,
- NR_DS_WIDTH, NR_DS_HEIGHT, 0, 0);
- dimv3_RDMA_WR_BITS(NRDSWR_CTRL,
- nrds_dev.canvas_idx, 0, 8);
- dimv3_nr_ds_hw_ctrl(true);
-}
-
-/*
- * enable/disable nr ds mif&hw
- */
-void dimv3_nr_ds_hw_ctrl(bool enable)
-{
- /*Switch MIF to NR_DS*/
- dimv3_RDMA_WR_BITS(VIUB_MISC_CTRL0, enable ? 3 : 2, 5, 2);
- dimv3_RDMA_WR_BITS(NRDSWR_CTRL, enable ? 1 : 0, 12, 1);
- dimv3_RDMA_WR_BITS(NR_DS_CTRL, enable ? 1 : 0, 30, 1);
-}
-
-/*
- * process in irq
- */
-void dimv3_nr_ds_irq(void)
-{
- dimv3_nr_ds_hw_ctrl(false);
- nrds_dev.field_num++;
- nrds_dev.cur_buf_idx++;
- if (nrds_dev.cur_buf_idx >= NR_DS_BUF_NUM)
- nrds_dev.cur_buf_idx = 0;
-}
-
-/*
- * get buf addr&size for dump
- */
-void dimv3_get_nr_ds_buf(unsigned long *addr, unsigned long *size)
-{
- *addr = nrds_dev.nrds_addr;
- *size = NR_DS_BUF_SIZE;
- PR_INF("%s addr 0x%lx, size 0x%lx.\n", __func__, *addr, *size);
-}
-
-/*
- * 0x37f9 ~ 0x37fc 0x3740 ~ 0x3743 8 regs
- */
-void dimv3_dump_nrds_reg(unsigned int base_addr)
-{
- unsigned int i = 0x37f9;
-
- pr_info("-----nrds reg start-----\n");
- pr_info("[0x%x][0x%x]=0x%x\n",
- base_addr + (0x2006 << 2), i, dimv3_RDMA_RD(0x2006));
- for (i = 0x37f9; i < 0x37fd; i++)
- pr_info("[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2), i, dimv3_RDMA_RD(i));
- for (i = 0x3740; i < 0x3744; i++)
- pr_info("[0x%x][0x%x]=0x%x\n",
- base_addr + (i << 2), i, dimv3_RDMA_RD(i));
- pr_info("-----nrds reg end-----\n");
-}
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/nr_downscale.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _NR_DS_H
-#define _NR_DS_H
-
-#define NR_DS_WIDTH 128
-#define NR_DS_HEIGHT 96
-#define NR_DS_BUF_SIZE (96 << 7)
-#define NR_DS_BUF_NUM 6
-#define NR_DS_MEM_SIZE (NR_DS_BUF_SIZE * NR_DS_BUF_NUM)
-#define NR_DS_PAGE_NUM (NR_DS_MEM_SIZE >> PAGE_SHIFT)
-
-struct nr_ds_s {
- unsigned int field_num;
- unsigned long nrds_addr;
- struct page *nrds_pages;
- unsigned int canvas_idx;
- unsigned char cur_buf_idx;
- unsigned long buf[NR_DS_BUF_NUM];
-};
-
-void dimv3_nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start,
- struct device *dev);
-void dimv3_nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev);
-void dimv3_nr_ds_init(unsigned int width, unsigned int height);
-void dimv3_nr_ds_mif_config(void);
-void dimv3_nr_ds_hw_ctrl(bool enable);
-void dimv3_nr_ds_irq(void);
-void dimv3_get_nr_ds_buf(unsigned long *addr, unsigned long *size);
-void dimv3_dump_nrds_reg(unsigned int base_addr);
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/register.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __MACH_DEINTERLACE_REG_ADDR_H_
-#define __MACH_DEINTERLACE_REG_ADDR_H_
-#include <linux/amlogic/iomap.h>
-#include <linux/amlogic/media/registers/regs/di_regs.h>
-#include <linux/amlogic/media/registers/regs/viu_regs.h>
-#include <linux/amlogic/media/registers/regs/vdin_regs.h>
-
-#define Wr(adr, val) aml_write_vcbus(adr, val)
-#define Rd(adr) aml_read_vcbus(adr)
-#define Wr_reg_bits(adr, val, start, len) \
- aml_vcbus_update_bits(adr, \
- ((1 << (len)) - 1) << (start), (val) << (start))
-
-#define Rd_reg_bits(adr, start, len) \
- ((aml_read_vcbus(adr) & \
- (((1UL << (len)) - 1UL) << (start))) >> (start))
-
-unsigned int dimv3_RDMA_WR(unsigned int adr, unsigned int val);
-unsigned int dimv3_RDMA_RD(unsigned int adr);
-unsigned int dimv3_RDMA_WR_BITS(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len);
-unsigned int dimv3_RDMA_RD_BITS(unsigned int adr, unsigned int start,
- unsigned int len);
-void dimv3_DI_Wr(unsigned int addr, unsigned int val);
-void dimv3_DI_Wr_reg_bits(unsigned int adr, unsigned int val,
- unsigned int start, unsigned int len);
-void dimv3_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val);
-unsigned int dimv3_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
- unsigned int val,
- unsigned int start,
- unsigned int len);
-
-#define HHI_VPU_CLKB_CNTL 0x83
-
-#define DI_WRARB_REQEN_SLV_L1C1_OLD 0x2795
-#define DI_RDARB_REQEN_SLV_L1C1_OLD 0x2791
-#define DI_ARB_DBG_STAT_L1C1_OLD 0x27b4
-
-#define VIUB_SW_RESET 0x2001
-#define VIUB_SW_RESET0 0x2002
-#define VIUB_MISC_CTRL0 0x2006
- /* 0xd0108018 */
-#define VIUB_GCLK_CTRL0 0x2007
-#define VIUB_GCLK_CTRL1 0x2008
-#define VIUB_GCLK_CTRL2 0x2009
-#define VIUB_GCLK_CTRL3 0x200a
-/* g12a add debug reg */
-#define DI_DBG_CTRL 0x200b
-#define DI_DBG_CTRL1 0x200c
-#define DI_DBG_SRDY_INF 0x200d
-#define DI_DBG_RRDY_INF 0x200e
-/* txl add if2 */
-#define DI_IF2_GEN_REG 0x2010
-#define DI_IF2_CANVAS0 0x2011
-#define DI_IF2_LUMA_X0 0x2012
-#define DI_IF2_LUMA_Y0 0x2013
-#define DI_IF2_CHROMA_X0 0x2014
-#define DI_IF2_CHROMA_Y0 0x2015
-#define DI_IF2_RPT_LOOP 0x2016
-#define DI_IF2_LUMA0_RPT_PAT 0x2017
-#define DI_IF2_CHROMA0_RPT_PAT 0x2018
-#define DI_IF2_DUMMY_PIXEL 0x2019
-#define DI_IF2_LUMA_FIFO_SIZE 0x201a
-#define DI_IF2_RANGE_MAP_Y 0x201b
-#define DI_IF2_RANGE_MAP_CB 0x201c
-#define DI_IF2_RANGE_MAP_CR 0x201d
-#define DI_IF2_GEN_REG2 0x201e
-#define DI_IF2_FMT_CTRL 0x201f
-#define DI_IF2_FMT_W 0x2020
-#define DI_IF2_URGENT_CTRL 0x2021
-#define DI_IF2_GEN_REG3 0x2022
-/*txl new add end*/
-
-/* g12 new added */
-/* IF0 MIF */
-#define DI_IF0_GEN_REG 0x2030
-#define DI_IF0_CANVAS0 0x2031
-#define DI_IF0_LUMA_X0 0x2032
-#define DI_IF0_LUMA_Y0 0x2033
-#define DI_IF0_CHROMA_X0 0x2034
-#define DI_IF0_CHROMA_Y0 0x2035
-#define DI_IF0_REPEAT_LOOP 0x2036
-#define DI_IF0_LUMA0_RPT_PAT 0x2037
-#define DI_IF0_CHROMA0_RPT_PAT 0x2038
-#define DI_IF0_DUMMY_PIXEL 0x2039
-#define DI_IF0_LUMA_FIFO_SIZE 0x203A
-#define DI_IF0_RANGE_MAP_Y 0x203B
-#define DI_IF0_RANGE_MAP_CB 0x203C
-#define DI_IF0_RANGE_MAP_CR 0x203D
-#define DI_IF0_GEN_REG2 0x203E
-#define DI_IF0_FMT_CTRL 0x203F
-#define DI_IF0_FMT_W 0x2040
-#define DI_IF0_FMT_W 0x2040
-#define DI_IF0_URGENT_CTRL 0x2041
-#define DI_IF0_GEN_REG3 0x2042
-/* AXI ARB */
-#define DI_RDARB_MODE_L1C1 0x2050
-#define DI_RDARB_REQEN_SLV_L1C1 0x2051
-#define DI_RDARB_WEIGH0_SLV_L1C1 0x2052
-#define DI_RDARB_WEIGH1_SLV_L1C1 0x2053
-#define DI_WRARB_MODE_L1C1 0x2054
-#define DI_WRARB_REQEN_SLV_L1C1 0x2055
-#define DI_WRARB_WEIGH0_SLV_L1C1 0x2056
-#define DI_WRARB_WEIGH1_SLV_L1C1 0x2057
-#define DI_RDWR_ARB_STATUS_L1C1 0x2058
-#define DI_ARB_DBG_CTRL_L1C1 0x2059
-#define DI_ARB_DBG_STAT_L1C1 0x205a
-#define DI_RDARB_UGT_L1C1 0x205b
-#define DI_RDARB_LIMT0_L1C1 0x205c
-#define DI_WRARB_UGT_L1C1 0x205d
-#define DI_PRE_GL_CTRL 0x20ab
-#define DI_PRE_GL_THD 0x20ac
-#define DI_POST_GL_CTRL 0x20ad
-#define DI_POST_GL_THD 0x20ae
-
-#define DI_SUB_RDARB_MODE 0x37c0
-#define DI_SUB_RDARB_REQEN_SLV 0x37c1
-#define DI_SUB_RDARB_WEIGH0_SLV 0x37c2
-#define DI_SUB_RDARB_WEIGH1_SLV 0x37c3
-#define DI_SUB_RDARB_UGT 0x37c4
-#define DI_SUB_RDARB_LIMT0 0x37c5
-#define DI_SUB_WRARB_MODE 0x37c6
-#define DI_SUB_WRARB_REQEN_SLV 0x37c7
-#define DI_SUB_WRARB_WEIGH0_SLV 0x37c8
-#define DI_SUB_WRARB_WEIGH1_SLV 0x37c9
-#define DI_SUB_WRARB_UGT 0x37ca
-#define DI_SUB_RDWR_ARB_STATUS 0x37cb
-#define DI_SUB_ARB_DBG_CTRL 0x37cc
-#define DI_SUB_ARB_DBG_STAT 0x37cd
-#define CONTRD_CTRL1 0x37d0
-#define CONTRD_CTRL2 0x37d1
-#define CONTRD_SCOPE_X 0x37d2
-#define CONTRD_SCOPE_Y 0x37d3
-#define CONTRD_RO_STAT 0x37d4
-#define CONT2RD_CTRL1 0x37d5
-#define CONT2RD_CTRL2 0x37d6
-#define CONT2RD_SCOPE_X 0x37d7
-#define CONT2RD_SCOPE_Y 0x37d8
-#define CONT2RD_RO_STAT 0x37d9
-#define MTNRD_CTRL1 0x37da
-#define MTNRD_CTRL2 0x37db
-#define MTNRD_SCOPE_X 0x37dc
-#define MTNRD_SCOPE_Y 0x37dd
-#define MTNRD_RO_STAT 0x37de
-#define MCVECRD_CTRL1 0x37df
-#define MCVECRD_CTRL2 0x37e0
-#define MCVECRD_SCOPE_X 0x37e1
-#define MCVECRD_SCOPE_Y 0x37e2
-#define MCVECRD_RO_STAT 0x37e3
-#define MCINFRD_CTRL1 0x37e4
-#define MCINFRD_CTRL2 0x37e5
-#define MCINFRD_SCOPE_X 0x37e6
-#define MCINFRD_SCOPE_Y 0x37e7
-#define MCINFRD_RO_STAT 0x37e8
-#define CONTWR_X 0x37e9
-#define CONTWR_Y 0x37ea
-#define CONTWR_CTRL 0x37eb
-#define CONTWR_CAN_SIZE 0x37ec
-#define MTNWR_X 0x37ed
-#define MTNWR_Y 0x37ee
-#define MTNWR_CTRL 0x37ef
-#define MTNWR_CAN_SIZE 0x37f0
-#define MCVECWR_X 0x37f1
-#define MCVECWR_Y 0x37f2
-#define MCVECWR_CTRL 0x37f3
-#define MCVECWR_CAN_SIZE 0x37f4
-#define MCINFWR_X 0x37f5
-#define MCINFWR_Y 0x37f6
-#define MCINFWR_CTRL 0x37f7
-#define MCINFWR_CAN_SIZE 0x37f8
-/* DI SCALE */
-#define DI_SCO_FIFO_CTRL 0x374e
-#define DI_SC_TOP_CTRL 0x374f
-#define DI_SC_DUMMY_DATA 0x3750
-#define DI_SC_LINE_IN_LENGTH 0x3751
-#define DI_SC_PIC_IN_HEIGHT 0x3752
-#define DI_SC_COEF_IDX 0x3753
-#define DI_SC_COEF 0x3754
-#define DI_VSC_REGION12_STARTP 0x3755
-#define DI_VSC_REGION34_STARTP 0x3756
-#define DI_VSC_REGION4_ENDP 0x3757
-#define DI_VSC_START_PHASE_STEP 0x3758
-#define DI_VSC_REGION0_PHASE_SLOPE 0x3759
-#define DI_VSC_REGION1_PHASE_SLOPE 0x375a
-#define DI_VSC_REGION3_PHASE_SLOPE 0x375b
-#define DI_VSC_REGION4_PHASE_SLOPE 0x375c
-#define DI_VSC_PHASE_CTRL 0x375d
-#define DI_VSC_INI_PHASE 0x375e
-#define DI_HSC_REGION12_STARTP 0x3760
-#define DI_HSC_REGION34_STARTP 0x3761
-#define DI_HSC_REGION4_ENDP 0x3762
-#define DI_HSC_START_PHASE_STEP 0x3763
-#define DI_HSC_REGION0_PHASE_SLOPE 0x3764
-#define DI_HSC_REGION1_PHASE_SLOPE 0x3765
-#define DI_HSC_REGION3_PHASE_SLOPE 0x3766
-#define DI_HSC_REGION4_PHASE_SLOPE 0x3767
-#define DI_HSC_PHASE_CTRL 0x3768
-#define DI_SC_MISC 0x3769
-#define DI_HSC_PHASE_CTRL1 0x376a
-#define DI_HSC_INI_PAT_CTRL 0x376b
-#define DI_SC_GCLK_CTRL 0x376c
-#define DI_SC_HOLD_LINE 0x376d
-
-/* DI H DOWN SCALER which IC? */
-#define DI_VIU_HSC_WIDTHM1 0x37b0
-#define DI_VIU_HSC_PHASE_STEP 0x37b1
-#define DI_VIU_HSC_CTRL 0x37b2
-#define DI_VIU_HSC_PHASE_CTRL 0x37b3
-#define DI_VIU_HSC_COEF 0x37b4
-#define DI_VIU_HSC_COEF_IDX 0x37b5
-
-/* NR DOWNSAMPLE */
-#define NRDSWR_X 0x37f9
-#define NRDSWR_Y 0x37fa
-#define NRDSWR_CTRL 0x37fb
-#define NRDSWR_CAN_SIZE 0x37fc
-#define NR_DS_BUF_SIZE_REG 0x3740
-#define NR_DS_CTRL 0x3741
-#define NR_DS_OFFSET 0x3742
-#define NR_DS_BLD_COEF 0x3743
-/* di */
-#define DI_IF1_URGENT_CTRL (0x20a3) /* << 2 + 0xd0100000*/
-/* bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 ,
- * low threshold for di inp chroma path
- * bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 ,
- * low threshold for di inp luma path
- */
-#define DI_INP_URGENT_CTRL (0x20a4) /* << 2 + 0xd0100000*/
-/* bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 ,
- * low threshold for di mem chroma path
- * bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 ,
- * low threshold for di mem luma path
- */
-#define DI_MEM_URGENT_CTRL (0x20a5) /* << 2 + 0xd0100000*/
-/* bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 ,
- * low threshold for di chan2 chroma path
- * bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 ,
- * low threshold for di chan2 luma path
- */
-#define DI_CHAN2_URGENT_CTRL (0x20a6) /* << 2 + 0xd0100000*/
-
-#define DI_PRE_CTRL ((0x1700)) /* << 2) + 0xd0100000) */
-/* bit 31, cbus_pre_frame_rst */
-/* bit 30, cbus_pre_soft_rst */
-/* bit 29, pre_field_num */
-/* bit 27:26, mode_444c422 */
-/* bit 25, di_cont_read_en */
-/* bit 24:23, mode_422c444 */
-/* bit 22, mtn_after_nr */
-/* bit 21:16, pre_hold_fifo_lines */
-/* bit 15, nr_wr_by */
-/* bit 14, use_vdin_go_line */
-/* bit 13, di_prevdin_en */
-/* bit 12, di_pre_viu_link */
-/* bit 11, di_pre_repeat */ /*ary : g12a: di_chan3_enable*/
-/* bit 10, di_pre_drop_1st */
-/* bit 9, di_buf2_en */
-/* bit 8, di_chan2_en */
-/* bit 7, prenr_hist_en */
-/* bit 6, chan2_hist_en */
-/* bit 5, hist_check_en */
-/* bit 4, check_after_nr */
-/* bit 3, check222p_en */
-/* bit 2, check322p_en */
-/* bit 1, mtn_en */
-/* bit 0, nr_en */
-/* #define DI_POST_CTRL ((0x1701)) */
-/* bit 31, cbus_post_frame_rst */
-/* bit 30, cbus_post_soft_rst */
-/* bit 29, post_field_num */
-/* bit 21:16, post_hold_fifo_lines */
-/* bit 13, prepost_link */
-/* bit 12, di_post_viu_link */
-/* bit 11, di_post_repeat */
-/* bit 10, di_post_drop_1st */
-/* bit 9, mif0_to_vpp_en */
-/* bit 8, di_vpp_out_en */
-/* bit 7, di_wr_bk_en */
-/* bit 6, di_mux_en */
-/* bit 5, di_blend_en */
-/* bit 4, di_mtnp_read_en */
-/* bit 3, di_mtn_buf_en */
-/* bit 2, di_ei_en */
-/* bit 1, di_buf1_en */
-/* bit 0, di_buf0_en */
-/* #define DI_POST_SIZE ((0x1702)) */
-/* bit 28:16, vsize1post */
-/* bit 12:0, hsize1post */
-#define DI_PRE_SIZE ((0x1703)) /* << 2) + 0xd0100000) */
-/* bit 28:16, vsize1pre */
-/* bit 12:0, hsize1pre */
-#define DI_EI_CTRL0 ((0x1704)) /* << 2) + 0xd0100000) */
-/* bit 23:16, ei0_filter[2:+] abs_diff_left>filter &&
- * ...right>filter && ...top>filter && ...bot>filter -> filter
- */
-/* bit 15:8, ei0_threshold[2:+] */
-/* bit 3, ei0_vertical */
-/* bit 2, ei0_bpscf2 */
-/* bit 1, ei0_bpsfar1 */
-#define DI_EI_CTRL1 ((0x1705)) /* << 2) + 0xd0100000) */
-/* bit 31:24, ei0_diff */
-/* bit 23:16, ei0_angle45 */
-/* bit 15:8, ei0_peak */
-/* bit 7:0, ei0_cross */
-#define DI_EI_CTRL2 ((0x1706)) /* << 2) + 0xd0100000) */
-/* bit 31:24, ei0_close2 */
-/* bit 23:16, ei0_close1 */
-/* bit 15:8, ei0_far2 */
-/* bit 7:0, ei0_far1 */
-#define DI_NR_CTRL0 ((0x1707)) /* << 2) + 0xd0100000) */
-/* bit 26, nr_cue_en */
-/* bit 25, nr2_en */
-#define DI_NR_CTRL1 ((0x1708)) /* << 2) + 0xd0100000) */
-/* bit 31:30, mot_p1txtcore_mode */
-/* bit 29:24, mot_p1txtcore_clmt */
-/* bit 21:16, mot_p1txtcore_ylmt */
-/* bit 15:8, mot_p1txtcore_crate */
-/* bit 7:0, mot_p1txtcore_yrate */
-#define DI_NR_CTRL2 ((0x1709)) /* << 2) + 0xd0100000) */
-/* bit 29:24, mot_curtxtcore_clmt */
-/* bit 21:16, mot_curtxtcore_ylmt */
-/* bit 15:8, mot_curtxtcore_crate */
-/* bit 7:0, mot_curtxtcore_yrate */
-/* `define DI_NR_CTRL3 8'h0a */
-/* no use */
-/* `define DI_MTN_CTRL 8'h0b */
-/* no use */
-#define DI_MTN_CTRL1 ((0x170c)) /* << 2) + 0xd0100000) */
-/* bit 13 , me enable */
-/* bit 12 , me autoenable */
-/* bit 11:8, mtn_paramtnthd */
-/* bit 7:0, mtn_parafltthd */
-#define DI_BLEND_CTRL ((0x170d)) /* << 2) + 0xd0100000) */
-/* bit 31, blend_1_en */
-/* bit 30, blend_mtn_lpf */
-/* bit 28, post_mb_en */
-/* bit 27, blend_mtn3p_max */
-/* bit 26, blend_mtn3p_min */
-/* bit 25, blend_mtn3p_ave */
-/* bit 24, blend_mtn3p_maxtb */
-/* bit 23, blend_mtn_flt_en */
-/* bit 22, blend_data_flt_en */
-/* bit 21:20, blend_top_mode */
-/* bit 19, blend_reg3_enable */
-/* bit 18, blend_reg2_enable */
-/* bit 17, blend_reg1_enable */
-/* bit 16, blend_reg0_enable */
-/* bit 15:14, blend_reg3_mode */
-/* bit 13:12, blend_reg2_mode */
-/* bit 11:10, blend_reg1_mode */
-/* bit 9:8, blend_reg0_mode */
-/* bit 7:0, kdeint */
-/* `define DI_BLEND_CTRL1 8'h0e */
-/* no use */
-/* `define DI_BLEND_CTRL2 8'h0f */
-/* no use */
-#define DI_ARB_CTRL ((0x170f)) /* << 2) + 0xd0100000) */
-/* bit 31:26, di_arb_thd1 */
-/* bit 25:20, di_arb_thd0 */
-/* bit 19, di_arb_tid_mode */
-/* bit 18, di_arb_arb_mode */
-/* bit 17, di_arb_acq_en */
-/* bit 16, di_arb_disable_clk */
-/* bit 15:0, di_arb_req_en */
-#define DI_BLEND_REG0_X ((0x1710)) /* << 2) + 0xd0100000) */
-/* bit 27:16, blend_reg0_startx */
-/* bit 11:0, blend_reg0_endx */
-#define DI_BLEND_REG0_Y ((0x1711)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG1_X ((0x1712)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG1_Y ((0x1713)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG2_X ((0x1714)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG2_Y ((0x1715)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG3_X ((0x1716)) /* << 2) + 0xd0100000) */
-#define DI_BLEND_REG3_Y ((0x1717)) /* << 2) + 0xd0100000) */
-#define DI_CLKG_CTRL ((0x1718)) /* << 2) + 0xd0100000) */
-/* bit 31:24, pre_gclk_ctrl no clk gate control. if ==1,
- * module clk is not gated (always on). [3] for pulldown,[2]
- * for mtn_1,[1] for mtn_0,[0] for nr
- * bit 23:16, post_gclk_ctrl no clk gate control. [4]
- * for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0
- * bit 1, di_gate_all clk shut down. if ==1 ,
- * all di clock shut down
- * bit 0, di_no_clk_gate no clk gate control.
- * if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working.
- */
-#define DI_EI_CTRL3 ((0x1719)) /* << 2) + 0xd0100000) */
-/* bit 31, reg_ei_1 */
-/* bit 30, reg_demon_en */
-/* bit 26:24, reg_demon_mux */
-/* bit 23:20, reg_right_win */
-/* bit 19:16, reg_left_win */
-/* bit 7:4, reg_ei_sadm_quatize_margin */
-/* bit 1:0, reg_ei_sad_relative_mode */
-#define DI_EI_CTRL4 ((0x171a)) /* << 2) + 0xd0100000) */
-/* bit 29, reg_ei_caldrt_ambliike2_biasvertical */
-/* bit 28:24, reg_ei_caldrt_addxla2list_drtmax */
-/* bit 22:20, reg_ei_caldrt_addxla2list_signm0th */
-/* bit 19, reg_ei_caldrt_addxla2list_mode */
-/* bit 18:16, reg_ei_signm_sad_cor_rate */
-/* bit 15:12, reg_ei_signm_sadi_cor_rate */
-/* bit 11:6, reg_ei_signm_sadi_cor_ofst */
-/* bit 5:0, reg_ei_signm_sad_ofst */
-#define DI_EI_CTRL5 ((0x171b)) /* << 2) + 0xd0100000) */
-/* bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd */
-/* bit 26:24, reg_ei_caldrt_cnflctchk_mg */
-/* bit 23:22, reg_ei_caldrt_cnflctchk_ws */
-/* bit 21, reg_ei_caldrt_cnflctchk_en */
-/* bit 20, reg_ei_caldrt_verfrc_final_en */
-/* bit 19, reg_ei_caldrt_verfrc_retimflt_en */
-/* bit 18:16, reg_ei_caldrt_verftc_eithratemth */
-/* bit 15, reg_ei_caldrt_verfrc_retiming_en */
-/* bit 14:12, reg_ei_caldrt_verfrc_bothratemth */
-/* bit 11:9, reg_ei_caldrt_ver_thrd */
-/* bit 8:4, reg_ei_caldrt_addxla2list_drtmin */
-/* bit 3:0, reg_ei_caldrt_addxla2list_drtlimit */
-#define DI_EI_CTRL6 ((0x171c)) /* << 2) + 0xd0100000) */
-/* bit 31:24, reg_ei_caldrt_abext_sad12thhig */
-/* bit 23:16, reg_ei_caldrt_abext_sad00thlow */
-/* bit 15:8, reg_ei_caldrt_abext_sad12thlow */
-/* bit 6:4, reg_ei_caldrt_abext_ratemth */
-/* bit 2:0, reg_ei_caldrt_abext_drtthrd */
-#define DI_EI_CTRL7 ((0x171d)) /* << 2) + 0xd0100000) */
-/* bit 29, reg_ei_caldrt_xlanopeak_codien */
-/* bit 28:24, reg_ei_caldrt_xlanopeak_drtmax */
-/* bit 23, reg_ei_caldrt_xlanopeak_en */
-/* bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha */
-/* bit 28:24, reg_ei_caldrt_abext_mononum12_thrd */
-/* bit 28:24, reg_ei_caldrt_abext_mononum00_thrd */
-/* bit 28:24, reg_ei_caldrt_abext_sad00rate */
-/* bit 28:24, reg_ei_caldrt_abext_sad12rate */
-/* bit 28:24, reg_ei_caldrt_abext_sad00thhig */
-#define DI_EI_CTRL8 ((0x171e)) /* << 2) + 0xd0100000) */
-/* bit 30:28, reg_ei_assign_headtail_magin */
-/* bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode */
-/* bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth */
-/* bit 20, reg_ei_caldrt_histchk_cnfid */
-/* bit 19:16, reg_ei_caldrt_histchk_thrd */
-/* bit 15, reg_ei_caldrt_histchk_abext */
-/* bit 14, reg_ei_caldrt_histchk_npen */
-/* bit 13:11, reg_ei_caldrt_amblike2_drtmg */
-/* bit 10:8, reg_ei_caldrt_amblike2_valmg */
-/* bit 7:4, reg_ei_caldrt_amblike2_alpha */
-/* bit 3:0, reg_ei_caldrt_amblike2_drtth */
-#define DI_EI_CTRL9 ((0x171f)) /* << 2) + 0xd0100000) */
-/* bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3 */
-/* bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en */
-/* bit 26:24, reg_ei_caldrt_conf_drtth */
-/* bit 23:20, reg_ei_caldrt_conf_absdrtth */
-/* bit 19:18, reg_ei_caldrt_abcheck_mode1 */
-/* bit 17:16, reg_ei_caldrt_abcheck_mode0 */
-/* bit 15:12, reg_ei_caldrt_abcheck_drth1 */
-/* bit 11:8, reg_ei_caldrt_abcheck_drth0 */
-/* bit 6:4, reg_ei_caldrt_abpnchk1_th */
-/* bit 1, reg_ei_caldrt_abpnchk1_en */
-/* bit 0, reg_ei_caldrt_abpnchk0_en */
-#define DI_EI_CTRL10 ((0x1793)) /* << 2) + 0xd0100000) */
-/* bit 31:28, reg_ei_caldrt_hstrrgchk_drtth */
-/* bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd */
-/* bit 23:20, reg_ei_caldrt_hstrrgchk_mg */
-/* bit 19, reg_ei_caldrt_hstrrgchk_1sidnul */
-/* bit 18, reg_ei_caldrt_hstrrgchk_excpcnf */
-/* bit 17:16, reg_ei_caldrt_hstrrgchk_ws */
-/* bit 15, reg_ei_caldrt_hstrrgchk_en */
-/* bit 14:13, reg_ei_caldrt_hpncheck_mode */
-/* bit 12, reg_ei_caldrt_hpncheck_mute */
-/* bit 11:9, reg_ei_caldrt_hcnfcheck_mg2 */
-/* bit 8:6, reg_ei_caldrt_hcnfcheck_mg1 */
-/* bit 5:4, reg_ei_caldrt_hcnfcheck_mode */
-/* bit 3:0, reg_ei_caldrt_hcnfcheck_mg2 */
-#define DI_EI_CTRL11 ((0x179e)) /* << 2) + 0xd0100000) */
-/* bit 30:29, reg_ei_amb_detect_mode */
-/* bit 28:24, reg_ei_amb_detect_winth */
-/* bit 23:21, reg_ei_amb_decide_rppth */
-/* bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth */
-/* bit 18:16, reg_ei_retime_lastmappncnfltchk_mode */
-/* bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode */
-/* bit 13:12, reg_ei_retime_lastvertfrcchk_mode */
-/* bit 11:8, reg_ei_retime_lastpnchk_drtth */
-/* bit 6, reg_ei_retime_lastpnchk_en */
-/* bit 5:4, reg_ei_retime_mode */
-/* bit 3, reg_ei_retime_last_en */
-/* bit 2, reg_ei_retime_ab_en */
-/* bit 1, reg_ei_caldrt_hstrvertfrcchk_en */
-/* bit 0, reg_ei_caldrt_hstrrgchk_mode */
-#define DI_EI_CTRL12 ((0x179f)) /* << 2) + 0xd0100000) */
-/* bit 31:28, reg_ei_drtdelay2_lmt */
-/* bit 27:26, reg_ei_drtdelay2_notver_lrwin */
-/* bit 25:24, reg_ei_drtdelay_mode */
-/* bit 23, reg_ei_drtdelay2_mode */
-/* bit 22:20, reg_ei_assign_xla_signm0th */
-/* bit 19, reg_ei_assign_pkbiasvert_en */
-/* bit 18, reg_ei_assign_xla_en */
-/* bit 17:16, reg_ei_assign_xla_mode */
-/* bit 15:12, reg_ei_assign_nlfilter_magin */
-/* bit 11:8, reg_ei_localsearch_maxrange */
-/* bit 7:4, reg_ei_xla_drtth */
-/* bit 3:0, reg_ei_flatmsad_thrd */
-#define DI_EI_CTRL13 ((0x17a8)) /* << 2) + 0xd0100000) */
-/* bit 27:24, reg_ei_int_drt2x_chrdrt_limit */
-/* bit 23:20, reg_ei_int_drt16x_core */
-/* bit 19:16, reg_ei_int_drtdelay2_notver_cancv */
-/* bit 15:8, reg_ei_int_drtdelay2_notver_sadth */
-/* bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth */
-#define DI_EI_XWIN0 ((0x1798)) /* << 2) + 0xd0100000) */
-/* bit 27:16, ei_xend0 */
-/* bit 11:0, ei_xstart0 */
-#define DI_EI_XWIN1 ((0x1799)) /* << 2) + 0xd0100000) */
-/* DEINTERLACE mode check. */
-#define DI_MC_REG0_X ((0x1720)) /* << 2) + 0xd0100000) */
-/* bit 27:16, mc_reg0_start_x */
-/* bit 11:0, mc_reg0_end_x */
-#define DI_MC_REG0_Y ((0x1721)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG1_X ((0x1722)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG1_Y ((0x1723)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG2_X ((0x1724)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG2_Y ((0x1725)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG3_X ((0x1726)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG3_Y ((0x1727)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG4_X ((0x1728)) /* << 2) + 0xd0100000) */
-#define DI_MC_REG4_Y ((0x1729)) /* << 2) + 0xd0100000) */
-#define DI_MC_32LVL0 ((0x172a)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mc_reg2_32lvl */
-/* bit 23:16, mc_reg1_32lvl */
-/* bit 15:8, mc_reg0_32lvl */
-/* bit 7:0, field_32lvl */
-#define DI_MC_32LVL1 ((0x172b)) /* << 2) + 0xd0100000) */
-/* bit 15:8, mc_reg3_32lvl */
-/* bit 7:0, mc_reg4_32lvl */
-#define DI_MC_22LVL0 ((0x172c)) /* << 2) + 0xd0100000) */
-/* bit 31:16, mc_reg0_22lvl */
-/* bit 15:0, field_22lvl */
-#define DI_MC_22LVL1 ((0x172d)) /* << 2) + 0xd0100000) */
-/* bit 31:16, mc_reg2_22lvl */
-/* bit 15:0, mc_reg1_22lvl */
-#define DI_MC_22LVL2 ((0x172e)) /* << 2) + 0xd0100000) */
-/* bit 31:16, mc_reg4_22lvl */
-/* bit 15:0, mc_reg3_22lvl */
-#define DI_MC_CTRL ((0x172f)) /* << 2) + 0xd0100000) */
-/* bit 4, mc_reg4_en */
-/* bit 3, mc_reg3_en */
-/* bit 2, mc_reg2_en */
-/* bit 1, mc_reg1_en */
-/* bit 0, mc_reg0_en */
-#define DI_INTR_CTRL ((0x1730)) /* << 2) + 0xd0100000) */
-#define DI_INFO_ADDR ((0x1731)) /* << 2) + 0xd0100000) */
-#define DI_INFO_DATA ((0x1732)) /* << 2) + 0xd0100000) */
-#define DI_PRE_HOLD ((0x1733)) /* << 2) + 0xd0100000) */
-#define DI_MTN_1_CTRL1 ((0x1740)) /* << 2) + 0xd0100000) */
-/* bit 31, mtn_1_en */
-/* bit 30, mtn_init */
-/* bit 29, di2nr_txt_en */
-/* bit 28, di2nr_txt_mode */
-/* bit 27:24, mtn_def */
-/* bit 23:16, mtn_adp_yc */
-/* bit 15:8, mtn_adp_2c */
-/* bit 7:0, mtn_adp_2y */
-#define DI_MTN_1_CTRL2 ((0x1741)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_ykinter */
-/* bit 23:16, mtn_ckinter */
-/* bit 15:8, mtn_ykintra */
-/* bit 7:0, mtn_ckintra */
-#define DI_MTN_1_CTRL3 ((0x1742)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_tyrate */
-/* bit 23:16, mtn_tcrate */
-/* bit 15: 8, mtn_mxcmby */
-/* bit 7: 0, mtn_mxcmbc */
-#define DI_MTN_1_CTRL4 ((0x1743)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_tcorey */
-/* bit 23:16, mtn_tcorec */
-/* bit 15: 8, mtn_minth */
-/* bit 7: 0, mtn_maxth */
-#define DI_MTN_1_CTRL5 ((0x1744)) /* << 2) + 0xd0100000) */
-/* bit 31:28, mtn_m1b_extnd */
-/* bit 27:24, mtn_m1b_errod */
-/* bit 19:18, mtn_replace_cbyy */
-/* bit 17:16, mtn_replace_ybyc */
-/* bit 15: 8, mtn_core_ykinter */
-/* bit 7: 0, mtn_core_ckinter */
-#define DI_MTN_1_CTRL6 ((0x17a9)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_m1b_extnd */
-/* bit 23:16, mtn_m1b_errod */
-/* bit 15: 8, mtn_core_ykinter */
-/* bit 7: 0, mtn_core_ckinter */
-#define DI_MTN_1_CTRL7 ((0x17aa)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_core_mxcmby */
-/* bit 23:16, mtn_core_mxcmbc */
-/* bit 15: 8, mtn_core_y */
-/* bit 7: 0, mtn_core_c */
-#define DI_MTN_1_CTRL8 ((0x17ab)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_fcore_ykinter */
-/* bit 23:16, mtn_fcore_ckinter */
-/* bit 15: 8, mtn_fcore_ykintra */
-/* bit 7: 0, mtn_fcore_ckintra */
-#define DI_MTN_1_CTRL9 ((0x17ac)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_fcore_2yrate */
-/* bit 23:16, mtn_fcore_2crate */
-/* bit 15: 8, mtn_fcore_y */
-/* bit 7: 0, mtn_fcore_c */
-#define DI_MTN_1_CTRL10 ((0x17ad)) /* << 2) + 0xd0100000) */
-/* bit 27:24, mtn_motfld0 */
-/* bit 19:16, mtn_stlfld0 */
-/* bit 11: 8, mtn_motfld1 */
-/* bit 3: 0, mtn_stlfld1 */
-#define DI_MTN_1_CTRL11 ((0x17ae)) /* << 2) + 0xd0100000) */
-/* bit 27:24, mtn_smotevn */
-/* bit 20:16, mtn_smotodd */
-/* bit 11: 8, mtn_sstlevn */
-/* bit 4: 0, mtn_sstlodd */
-#define DI_MTN_1_CTRL12 ((0x17af)) /* << 2) + 0xd0100000) */
-/* bit 31:24, mtn_mgain */
-/* bit 17:16, mtn_mmode */
-/* bit 15: 8, mtn_sthrd */
-/* bit 4: 0, mtn_sgain */
-/* // DET 3D REG DEFINE BEGIN //// */
-/* // 8'h34~8'h3f */
-#define DET3D_MOTN_CFG ((0x1734)) /* << 2) + 0xd0100000) */
-/* Bit 16, reg_det3d_intr_en Det3d interrupt enable
- * Bit 9:8, reg_Det3D_Motion_Mode
- * U2 Different mode for Motion Calculation of Luma and Chroma:
- * 0: MotY, 1: (2*MotY + (MotU + MotV))/4;
- * 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
- * Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details
- * for coring of Motion Calculations, normalized to 32
- * Bit 3:0, reg_Det3D_Motion_Core_Thrd
- * U4 2X: static coring value for Motion Detection.
- */
-#define DET3D_CB_CFG ((0x1735)) /* << 2) + 0xd0100000) */
-/* Bit 7:4, reg_Det3D_ChessBd_NHV_ofst
- * U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
- *
- * Bit 3:0, reg_Det3D_ChessBd_HV_ofst
- * U4, Noise immune offset for Horizotnal or vertical combing detection.
- */
-#define DET3D_SPLT_CFG ((0x1736)) /* << 2) + 0xd0100000) */
-/* Bit 7:4, reg_Det3D_SplitValid_ratio
- * U4, Ratio between max_value and the avg_value of
- * the edge mapping for split line valid detection.
- * The smaller of this value, the easier of the split line detected.
- * Bit 3:0, reg_Det3D_AvgIdx_ratio U4,Ratio to the avg_value of the
- * edge mapping for split line position estimation.
- */
-/* The smaller of this value,
- * the more samples will be added to the estimation.
- */
-#define DET3D_HV_MUTE ((0x1737)) /* << 2) + 0xd0100000) */
-/* Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute
- * from H/V Edge calculation Top and Bottom border part.
- * Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute
- * from H/V Edge calculation Left and right border part.
- * Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to
- * be mute from ChessBoard statistics calculation in middle part
- * Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to
- * be mute from ChessBoard statistics calculation in middle part
- * Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be
- * mute from 8x8 statistics calculation in each block.
- * Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to
- * be mute from 8x8 statistics calculation in each block.
- */
-#define DET3D_MAT_STA_P1M1 ((0x1738)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1,
- * normalized to 256 (0.8)
- * Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1,
- * normalized to 128 (0.5)
- * Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6
- * U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
- * Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6
- * U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
- */
-#define DET3D_MAT_STA_P1TH ((0x1739)) /* << 2) + 0xd0100000) */
-/* Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to
- * decide P1, X16 (100)
- * Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd
- * offset to decide P1, X16 (80)
- * Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd
- * offset to decide P1, X16 (48)
- */
-#define DET3D_MAT_STA_M1TH ((0x173a)) /* << 2) + 0xd0100000) */
-/* Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to
- * ENG Thrd offset to decide M1, X16 (100)
- * Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4
- * U8 SAD to ENG Thrd offset to decide M1, X16 (80)
- * Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4
- * U8 SAD to ENG Thrd offset to decide M1, X16 (64)
- */
-#define DET3D_MAT_STA_RSFT ((0x173b)) /* << 2) + 0xd0100000) */
-/* Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI
- * calculation result right shift bits to accommodate the 12bits clipping:
- * 0: mainly for images <=720x480:
- * 1: mainly for images <=1366x768:
- * 2: mainly
- * for images <=1920X1080: 2; 3: other higher resolutions
- * Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge
- * Statistics SAD and SAI calculation result right shift bits to
- * accommodate the 12bits clipping:
- * 0: mainly for images <=720x480: 1: mainly for images <=1366x768:
- * 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
- * Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI
- * calculation result right shift bits to accommodate the 12bits clipping:
- * 0: mainly for images <=720x480: 1: mainly for images <=1366x768:
- * 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
- */
-#define DET3D_MAT_SYMTC_TH ((0x173c)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide
- * if the Luma statistics is TB or LR symmetric.
- * Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide
- * if the Chroma (UV) statistics is TB or LR symmetric.
- * Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to
- * decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
- * Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to
- * decide if the Motion statistics is TB or LR symmetric.
- */
-#define DET3D_RO_DET_CB_HOR ((0x173d)) /* << 2) + 0xd0100000) */
-/* Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels
- * of Horizontally Surely NOT matching Chessboard pattern.
- * Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of
- * Pixels of Horizontally Surely matching Chessboard pattern.
- */
-#define DET3D_RO_DET_CB_VER ((0x173e)) /* << 2) + 0xd0100000) */
-/* Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of
- * Pixels of Vertically Surely NOT matching Chessboard pattern.
- * Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number
- * of Pixels of Vertically Surely matching Chessboard pattern.
- */
-#define DET3D_RO_SPLT_HT ((0x173f)) /* << 2) + 0xd0100000) */
-/* Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border
- * detected valid signal for top half picture
- * Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the
- * LR split position estimation for top half picture
- * Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel
- * shifts of LR split position to the (ColMax/2) for top half picture
- * // DET 3D REG DEFINE END ////
- * // NR2 REG DEFINE BEGIN////
- */
-#define NR2_MET_NM_CTRL ((0x1745)) /* << 2) + 0xd0100000) */
-/* Bit 28, reg_NM_reset Reset to the status of the Loop filter.
- * Bit 27:24, reg_NM_calc_length Length mode of the Noise
- * measurement sample number for statistics.
- * 0: 256 samples; 1: 512 samples; 2: 1024 samples;
- * ¡X: 2^(8+x) samples
- * Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
- * Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
- * Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion
- * for condition of pixels included in Luma Noise measurement.
- * Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion
- * for condition of pixels included in Chroma Noise measurement.
- */
-#define NR2_MET_NM_YCTRL ((0x1746)) /* << 2) + 0xd0100000) */
-/* Bit 31:28, reg_NM_YPLL_target Target rate of
- * NM_Ynoise_thrd to mean of the Luma Noise
- * Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP
- * portion motion for condition of pixels included in Luma Noise measurement.
- * Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for
- * Luma channel HP portion motion to decide whether the pixel
- * will be included in Luma noise measurement.
- * Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma
- * channel HP portion motion to decide whether the pixel will be included in
- * Luma noise measurement.
- * Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the
- * Luma noise measurement is lock or not.
- */
-#define NR2_MET_NM_CCTRL ((0x1747)) /* << 2) + 0xd0100000) */
-/* Bit 31:28, reg_NM_CPLL_target
- * Target rate of NM_Cnoise_thrd to mean of the Chroma Noise
- * Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion
- * for condition of pixels included in Chroma Noise measurement.
- * Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel
- * HP portion motion to decide whether the pixel will be
- * included in Chroma noise measurement.
- * Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma
- * channel HP portion motion to decide whether the pixel will be included in
- * Chroma noise measurement.
- * Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma
- * noise measurement is lock or not;
- */
-#define NR2_MET_NM_TNR ((0x1748)) /* << 2) + 0xd0100000) */
-/* Bit 25, ro_NM_TNR_Ylock Read-only register to tell
- * ifLuma channel noise measurement is locked or not.
- * Bit 24, ro_NM_TNR_Clock Read-only register to tell
- * if Chroma channel noise measurement is locked or not.
- * Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma
- * channel noise level. It was 16x of pixel difference in 8 bits of YHPmot.
- * Bit 11:0, ro_NM_TNR_ClevelRead-only register to give Chroma channel noise
- * level.It was 16x of pixel difference in 8 bits of CHPmot.
- */
-#define NR2_MET_NMFRM_TNR_YLEV ((0x1749)) /* << 2) + 0xd0100000) */
-/* Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register
- * to give Luma channel noise level within one frame/field.
- */
-#define NR2_MET_NMFRM_TNR_YCNT ((0x174a)) /* << 2) + 0xd0100000) */
-/* Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels
- * included in Frame/Field based noise level measurement.
- */
-#define NR2_MET_NMFRM_TNR_CLEV ((0x174b)) /* << 2) + 0xd0100000) */
-/* Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register
- * to give Chroma channel noise level within one frame/field.
- */
-#define NR2_MET_NMFRM_TNR_CCNT ((0x174c)) /* << 2) + 0xd0100000) */
-/* Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels
- * included in Frame/Field based noise level measurement.
- */
-#define NR2_3DEN_MODE ((0x174d)) /* << 2) + 0xd0100000) */
-/* Bit 6:4, Blend_3dnr_en_r */
-/* Bit 2:0, Blend_3dnr_en_l */
-#define NR2_IIR_CTRL ((0x174e)) /* << 2) + 0xd0100000) */
-/* Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:
- * 0: 10bits will be store in memory;
- * 1: 9bits will be store in memory;
- * 2: 8bits will be store in memory;
- * 3: 7bits will be store in memory;
- * Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute,
- * Bit 11:8,reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost:
- * Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:
- * 0: 10bits will be store in memory;
- * 1: 9bits will be store in memory;
- * 2: 8bits will be store in memory;
- * 3: 7bits will be store in memory;
- * Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute
- * Bit 3:0,reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost
- */
-#define NR2_SW_EN ((0x174f)) /* << 2) + 0xd0100000) */
-/* Bit 17:8, Clk_gate_ctrl
- * Bit 7, Cfr_enable
- * Bit 5, Det3d_en
- * Bit 4, Nr2_proc_en
- * Bit 0, Nr2_sw_en
- */
-#define NR2_FRM_SIZE ((0x1750)) /* << 2) + 0xd0100000) */
-/* Bit 27:16, Frm_heigh Frame/field height */
-/* Bit 11: 0, Frm_width Frame/field width */
-#define NR2_SNR_SAD_CFG ((0x1751)) /* << 2) + 0xd0100000) */
-/* Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current
- * pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel
- * position SAD by SAD_min;1: do replacements
- * Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame
- * SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);
- * sum = (sum<0) ? 0: (sum>255)? 255: sum;
- * Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD
- * matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
- * Bit 4:0, Sad_coef_num Sad coeffient
- */
-#define NR2_MATNR_SNR_OS ((0x1752)) /* << 2) + 0xd0100000) */
-/* Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control
- * margin for UV channel (X2 to u10 scale)
- * Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control
- * margin for luma channel (X2 to u10 scale)
- */
-#define NR2_MATNR_SNR_NRM_CFG ((0x1753)) /* << 2) + 0xd0100000) */
-/* Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR
- * boosting normalization offset to SAD_max ;
- * Bit 15:8, reg_MATNR_SNR_NRM_max
- * Edge based SNR boosting normalization Max value
- * Bit 7:0, reg_MATNR_SNR_NRM_min
- * Edge based SNR boosting normalization Min value
- */
-#define NR2_MATNR_SNR_NRM_GAIN ((0x1754)) /* << 2) + 0xd0100000) */
-/* Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting
- * normalization Gain for Chrm channel (norm 32 as 1)
- * Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting
- * normalization Gain for Luma channel (norm 32 as 1)
- */
-#define NR2_MATNR_SNR_LPF_CFG ((0x1755)) /* << 2) + 0xd0100000) */
-/* Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF
- * to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH)
- * SNRLPF_yuv[k] = TNRLPF_yuv[k];
- * Bit 13:11,reg_MATNR_SNRLPF_Cmode
- * LPF based SNR filtering mode on CHRM channel:
- * 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4;
- * 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16;
- * 4: TNRLPF; 5 : CurLPF3x3_yuv[];
- * 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
- * Bit 10:8, reg_MATNR_SNRLPF_Ymode
- * LPF based SNR filtering mode on LUMA channel:
- * 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4;
- * 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16;
- * 4: TNRLPF; 5 : CurLPF3x3_yuv[];
- * 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
- * Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to
- * Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
- * Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to
- * Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
- */
-#define NR2_MATNR_SNR_USF_GAIN ((0x1756)) /* << 2) + 0xd0100000) */
-/* Bit 15:8, reg_MATNR_SNR_USF_Cgain
- * Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1)
- * Bit 7:0, reg_MATNR_SNR_USF_Ygain
- * Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1)
- */
-#define NR2_MATNR_SNR_EDGE2B ((0x1757)) /* << 2) + 0xd0100000) */
-/* Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8,
- * Offset for Beta based on Edge.
- * Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8.
- * Gain to SAD_min for Beta based on Edge. (norm 16 as 1)
- */
-#define NR2_MATNR_BETA_EGAIN ((0x1758)) /* << 2) + 0xd0100000) */
-/* Bit 15:8, reg_MATNR_CBeta_Egain U8,
- * Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1)
- * Bit 7:0, reg_MATNR_YBeta_Egain U8,
- * Gain to Edge based Beta for Luma channel. (normalized to 32 as 1)
- */
-#define NR2_MATNR_BETA_BRT ((0x1759)) /* << 2) + 0xd0100000) */
-/* Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4,
- * Beta adjustment based on Brightness high side Limit. (X16 to u8 scale)
- * Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4,
- * Beta adjustment based on Brightness high side slope. Normalized to 16 as 1
- * Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8,
- * Beta adjustment based on Brightness high threshold.(u8 scale)
- * Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4,
- * Beta adjustment based on Brightness low side Limit. (X16 to u8 scale)
- * Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4,
- * Beta adjustment based on Brightness low side slope. Normalized to 16 as 1
- * Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8,
- * Beta adjustment based on Brightness low threshold.(u8 scale)
- */
-#define NR2_MATNR_XBETA_CFG ((0x175a)) /* << 2) + 0xd0100000) */
-/* Bit 19:18, reg_MATNR_CBeta_use_mode U2,
- * Beta options (mux) from beta_motion and beta_edge for Chrm channel;
- * Bit 17:16, reg_MATNR_YBeta_use_mode U2,
- * Beta options (mux) from beta_motion and beta_edge for Luma channel;
- * Bit 15: 8, reg_MATNR_CBeta_Ofst U8,
- * Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux)
- * Bit 7: 0, reg_MATNR_YBeta_Ofst U8,
- * Offset to Beta for Luma channel.(after beta_edge and beta_motion mux)
- */
-#define NR2_MATNR_YBETA_SCL ((0x175b)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_YBeta_scale_min U8,
- * Final step Beta scale low limit for Luma channel;
- * Bit 23:16, reg_MATNR_YBeta_scale_max U8,
- * Final step Beta scale high limit for Luma channe;
- * Bit 15: 8, reg_MATNR_YBeta_scale_gain U8,
- * Final step Beta scale Gain for Luma channel (normalized 32 to 1);
- * Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8,
- * Final step Beta scale offset for Luma channel ;
- */
-#define NR2_MATNR_CBETA_SCL ((0x175c)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_CBeta_scale_min
- * Final step Beta scale low limit for Chrm channel.Similar to Y
- * Bit 23:16, reg_MATNR_CBeta_scale_max U8,
- * Final step Beta scale high limit for Chrm channel.Similar to Y
- * Bit 15: 8, reg_MATNR_CBeta_scale_gain U8,
- * Final step Beta scale Gain for Chrm channel Similar to Y
- * Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8,
- * Final step Beta scale offset for Chrm channel Similar to Y
- */
-#define NR2_SNR_MASK ((0x175d)) /* << 2) + 0xd0100000) */
-/* Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface */
-#define NR2_SAD2NORM_LUT0 ((0x175e)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_SAD2Norm_LUT_3
- * SAD convert normal LUT node 3
- * Bit 23:16, reg_MATNR_SAD2Norm_LUT_2
- * SAD convert normal LUT node 2
- * Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1
- * SAD convert normal LUT node 1
- * Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0
- * SAD convert normal LUT node 0
- */
-#define NR2_SAD2NORM_LUT1 ((0x175f)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_SAD2Norm_LUT_7
- * SAD convert normal LUT node 7
- * Bit 23:16, reg_MATNR_SAD2Norm_LUT_6
- * SAD convert normal LUT node 6
- * Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5
- * SAD convert normal LUT node 5
- * Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4
- * SAD convert normal LUT node 4
- */
-#define NR2_SAD2NORM_LUT2 ((0x1760)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_SAD2Norm_LUT_11
- * SAD convert normal LUT node 11
- * Bit 23:16, reg_MATNR_SAD2Norm_LUT_10
- * SAD convert normal LUT node 10
- * Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9
- * SAD convert normal LUT node 9
- * Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8
- * SAD convert normal LUT node 8
- */
-#define NR2_SAD2NORM_LUT3 ((0x1761)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15 */
-/* Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14 */
-/* Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13 */
-/* Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12 */
-#define NR2_EDGE2BETA_LUT0 ((0x1762)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3 */
-/* Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2 */
-/* Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1 */
-/* Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0 */
-#define NR2_EDGE2BETA_LUT1 ((0x1763)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7 */
-/* Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6 */
-/* Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5 */
-/* Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4 */
-#define NR2_EDGE2BETA_LUT2 ((0x1764)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11 */
-/* Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10 */
-/* Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9 */
-/* Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8 */
-#define NR2_EDGE2BETA_LUT3 ((0x1765)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15 */
-/* Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14 */
-/* Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13 */
-/* Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12 */
-#define NR2_MOTION2BETA_LUT0 ((0x1766)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3 */
-/* Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2 */
-/* Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1 */
-/* Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0 */
-#define NR2_MOTION2BETA_LUT1 ((0x1767)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7 */
-/* Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6 */
-/* Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5 */
-/* Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4 */
-#define NR2_MOTION2BETA_LUT2 ((0x1768)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11 */
-/* Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10 */
-/* Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9 */
-/* Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8 */
-#define NR2_MOTION2BETA_LUT3 ((0x1769)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15 */
-/* Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14 */
-/* Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13 */
-/* Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12 */
-#define NR2_MATNR_MTN_CRTL ((0x176a)) /* << 2) + 0xd0100000) */
-/* Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection
- * mode: 0: Vmot;
- * 1:Ymot/2 + (Umot+Vmot)/4;
- * 2:Ymot/2 + max(Umot,Vmot)/2;
- * 3: max(Ymot,Umot, Vmot)
- * Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection
- * mode: 0:Umot;
- * 1:Ymot/2 + (Umot+Vmot)/4;
- * 2:Ymot/2 + max(Umot,Vmot)/2;
- * 3: max(Ymot,Umot, Vmot)
- * Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection
- * mode: 0: Ymot,
- * 1: Ymot/2 + (Umot+Vmot)/4;
- * 2: Ymot/2 + max(Umot,Vmot)/2;
- * 3: max(Ymot,Umot, Vmot)
- * Bit 13:12, reg_MATNR_mtn_txt_mode
- * Texture detection mode for adaptive coring of HP motion
- * Bit 9: 8, reg_MATNR_mtn_cor_mode
- * Coring selection mode based on texture detection;
- * Bit 6: 4, reg_MATNR_mtn_hpf_mode
- * video mode of current and previous frame/field for MotHPF_yuv[k] calculation:
- * Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous
- * frame/field for MotLPF_yuv[k] calculation:
- */
-#define NR2_MATNR_MTN_CRTL2 ((0x176b)) /* << 2) + 0xd0100000) */
-/* Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter
- * mode for Luma LPF result generation (Cur and Prev);
- * Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to
- * motion_brtlp_uv, normalized to 32 as 1
- * Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to
- * motion_brtlp_y, normalized to 32 as 1
- */
-#define NR2_MATNR_MTN_COR ((0x176c)) /* << 2) + 0xd0100000) */
-/* Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion.
- * Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for
- * Chroma Motion. Normalized to 16 as 1
- * Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion.
- * Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for
- * Luma Motion. Normalized to 16 as 1
- */
-#define NR2_MATNR_MTN_GAIN ((0x176d)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for
- * motion calculation, normalized to 64 as 1
- * Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for
- * motion calculation, normalized to 64 as 1
- * Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for
- * motion calculation, normalized to 32 as 1
- * Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for
- * motion calculation, normalized to 32 as 1
- */
-#define NR2_MATNR_DEGHOST ((0x176e)) /* << 2) + 0xd0100000) */
-/* Bit 8, reg_MATNR_DeGhost_En
- * Enable signal for DeGhost function:0: disable; 1: enable
- * Bit 7:4, reg_MATNR_DeGhost_COS
- * DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
- * Bit 3:0, reg_MATNR_DeGhost_YOS
- * DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
- */
-#define NR2_MATNR_ALPHALP_LUT0 ((0x176f)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaLP_LUT_3
- * Matnr low-pass filter alpha LUT node 3
- */
-/* Bit 23:16, reg_MATNR_AlphaLP_LUT_2
- * Matnr low-pass filter alpha LUT node 2
- */
-/* Bit 15: 8, reg_MATNR_AlphaLP_LUT_1
- * Matnr low-pass filter alpha LUT node 1
- */
-/* Bit 7: 0, reg_MATNR_AlphaLP_LUT_0
- *Matnr low-pass filter alpha LUT node 0
- */
-#define NR2_MATNR_ALPHALP_LUT1 ((0x1770)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaLP_LUT_7
- * Matnr low-pass filter alpha LUT node 7
- */
-/* Bit 23:16, reg_MATNR_AlphaLP_LUT_6
- * Matnr low-pass filter alpha LUT node 6
- */
-/* Bit 15: 8, reg_MATNR_AlphaLP_LUT_5
- * Matnr low-pass filter alpha LUT node 5
- */
-/* Bit 7: 0, reg_MATNR_AlphaLP_LUT_4
- * Matnr low-pass filter alpha LUT node 4
- */
-#define NR2_MATNR_ALPHALP_LUT2 ((0x1771)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaLP_LUT_11
- * Matnr low-pass filter alpha LUT node 11
- */
-/* Bit 23:16, reg_MATNR_AlphaLP_LUT_10
- * Matnr low-pass filter alpha LUT node 10
- */
-/* Bit 15: 8, reg_MATNR_AlphaLP_LUT_9
- * Matnr low-pass filter alpha LUT node 9
- */
-/* Bit 7: 0, reg_MATNR_AlphaLP_LUT_8
- * Matnr low-pass filter alpha LUT node 8
- */
-#define NR2_MATNR_ALPHALP_LUT3 ((0x1772)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaLP_LUT_15
- * Matnr low-pass filter alpha LUT node 15
- */
-/* Bit 23:16, reg_MATNR_AlphaLP_LUT_14
- * Matnr low-pass filter alpha LUT node 14
- */
-/* Bit 15: 8, reg_MATNR_AlphaLP_LUT_13
- * Matnr low-pass filter alpha LUT node 13
- */
-/* Bit 7: 0, reg_MATNR_AlphaLP_LUT_12
- * Matnr low-pass filter alpha LUT node 12
- */
-#define NR2_MATNR_ALPHAHP_LUT0 ((0x1773)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaHP_LUT_3
- * Matnr high-pass filter alpha LUT node 3
- */
-/* Bit 23:16, reg_MATNR_AlphaHP_LUT_2
- * Matnr high-pass filter alpha LUT node 2
- */
-/* Bit 15: 8, reg_MATNR_AlphaHP_LUT_1
- * Matnr high-pass filter alpha LUT node 1
- */
-/* Bit 7: 0, reg_MATNR_AlphaHP_LUT_0
- * Matnr high-pass filter alpha LUT node 0
- */
-#define NR2_MATNR_ALPHAHP_LUT1 ((0x1774)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaHP_LUT_7
- * Matnr high-pass filter alpha LUT node 7
- */
-/* Bit 23:16, reg_MATNR_AlphaHP_LUT_6
- * Matnr high-pass filter alpha LUT node 6
- */
-/* Bit 15: 8, reg_MATNR_AlphaHP_LUT_5
- * Matnr high-pass filter alpha LUT node 5
- */
-/* Bit 7: 0, reg_MATNR_AlphaHP_LUT_4
- * Matnr high-pass filter alpha LUT node 4
- */
-#define NR2_MATNR_ALPHAHP_LUT2 ((0x1775)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaHP_LUT_11
- * Matnr high-pass filter alpha LUT node 11
- */
-/* Bit 23:16, reg_MATNR_AlphaHP_LUT_10
- * Matnr high-pass filter alpha LUT node 10
- */
-/* Bit 15: 8, reg_MATNR_AlphaHP_LUT_9
- * Matnr high-pass filter alpha LUT node 9
- */
-/* Bit 7: 0, reg_MATNR_AlphaHP_LUT_8
- * Matnr high-pass filter alpha LUT node 8
- */
-#define NR2_MATNR_ALPHAHP_LUT3 ((0x1776)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_MATNR_AlphaHP_LUT_15
- * Matnr high-pass filter alpha LUT node 15
- */
-/* Bit 23:16, reg_MATNR_AlphaHP_LUT_14
- * Matnr high-pass filter alpha LUT node 14
- */
-/* Bit 15: 8, reg_MATNR_AlphaHP_LUT_13
- * Matnr high-pass filter alpha LUT node 13
- */
-/* Bit 7: 0, reg_MATNR_AlphaHP_LUT_12
- *Matnr high-pass filter alpha LUT node 12
- */
-#define NR2_MATNR_MTNB_BRT ((0x1777)) /* << 2) + 0xd0100000) */
-/* Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on
- * Brightness high side Limit. (X16 to u8 scale)
- */
-/* Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on
- * Brightness high side slope. Normalized to 16 as 1
- */
-/* Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on
- * Brightness high threshold.(u8 scale)
- */
-/* Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on
- * Brightness low side Limit. (X16 to u8 scale)
- */
-/* Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on
- * Brightness low side slope. Normalized to 16 as 1
- */
-/* Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on
- * Brightness low threshold.(u8 scale)
- */
-#define NR2_CUE_MODE ((0x1778)) /* << 2) + 0xd0100000) */
-/* Bit 9, Cue_enable_r Cue right half frame enable */
-/* Bit 8, Cue_enable_l Cue left half frame enable */
-/* Bit 6:4, reg_CUE_CON_RPLC_mode U3, CUE pixel chroma replace mode; */
-/* Bit 2:0, reg_CUE_CHRM_FLT_mode U3, CUE improvement filter mode, */
-#define NR2_CUE_CON_MOT_TH ((0x1779)) /* << 2) + 0xd0100000) */
-/* Bit 31:24, reg_CUE_CON_Cmot_thrd2 U8, Motion Detection threshold of
- * up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE)
- * Detection (tighter).
- */
-/* Bit 23:16, reg_CUE_CON_Ymot_thrd2 U8, Motion Detection threshold of
- * up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE)
- * Detection (tighter).
- */
-/* Bit 15: 8, reg_CUE_CON_Cmot_thrd U8, Motion Detection threshold of
- * up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection.
- */
-/* Bit 7: 0, reg_CUE_CON_Ymot_thrd U8, Motion Detection threshold of
- * up/mid/down three rows, Luma channel in
- * Chroma Up-sampling Error (CUE) Detection.
- */
-#define NR2_CUE_CON_DIF0 ((0x177a)) /* << 2) + 0xd0100000) */
-/* Bit 15:8, reg_CUE_CON_difP1_thrd U8, P1 field Intra-Field top/below
- * line chroma difference threshold,
- */
-/* Bit 7:0, reg_CUE_CON_difCur_thrd U8, Current Field/Frame Intra-Field
- * up/down line chroma difference threshold,
- */
-#define NR2_CUE_CON_DIF1 ((0x177b)) /* << 2) + 0xd0100000) */
-/* Bit 19:16, reg_CUE_CON_rate0 U4, The Krate to decide CUE by
- * relationship between CUE_diflG and CUE_difEG
- */
-/* Bit 15: 8, reg_CUE_CON_difEG_thrd U8, Theshold to the difference between
- * current Field/Frame middle line to down line color channel(CUE_difEG).
- */
-/* Bit 7: 0, reg_CUE_CON_diflG_thrd U8, Threshold to the difference between
- * P1 field top line to current Field/Frame down line color channel (CUE_diflG).
- */
-#define NR2_CUE_CON_DIF2 ((0x177c)) /* << 2) + 0xd0100000) */
-/* Bit 19:16, reg_CUE_CON_rate1 U4, The Krate to decide CUE by
- * relationship between CUE_difnC and CUE_difEC
- */
-/* Bit 15: 8, reg_CUE_CON_difEC_thrd U8, Theshold to the difference between
- * current Field/Frame middle line to up line color channel(CUE_difEC).
- */
-/* Bit 7: 0, reg_CUE_CON_difnC_thrd U8, Threshold to the difference between
- * P1 field bot line to current Field/Frame up line color channel (CUE_difnC).
- */
-#define NR2_CUE_CON_DIF3 ((0x177d)) /* << 2) + 0xd0100000) */
-/* Bit 19:16, reg_CUE_CON_rate2 U4, The Krate to decide CUE by
- * relationship between CUE_difP1 and CUE_difEP1
- */
-/* Bit 15: 8, reg_CUE_CON_difEP1_thrd U8, Inter-Field top/below line to
- * current field/frame middle line chroma difference (CUE_difEP1) threshold.
- */
-/* Bit 7: 0, reg_CUE_CON_difP1_thrd2 U8, P1 field Intra-Field top/below line
- * chroma difference threshold (tighter),
- */
-/* change from txlx */
-#define DI_EI_DRT_CTRL ((0x1778))
-
-#define DI_EI_DRT_PIXTH ((0x1779))
-
-#define DI_EI_DRT_CORRPIXTH ((0x177a))
-
-#define DI_EI_DRT_RECTG_WAVE ((0x177b))
-
-#define DI_EI_DRT_PIX_DIFFTH ((0x177c))
-
-#define DI_EI_DRT_UNBITREND_TH ((0x177d))
-
-#define NR2_CUE_PRG_DIF ((0x177e)) /* << 2) + 0xd0100000) */
-/* Bit 20, reg_CUE_PRG_Enable Enable bit for progressive video CUE
- * detection.If interlace input video,
- */
-/* Bit 19:16, reg_CUE_PRG_rate U3, The Krate to decide CUE by
- * relationship between CUE_difCur and (CUE_difEC+CUE_difEG)
- */
-/* Bit 15: 8, reg_CUE_PRG_difCEG_thrd U8, Current Frame Intra-Field up-mid and
- * mid-down line chroma difference threshold
- * for progressive video CUE detection,
- */
-/* Bit 7: 0, reg_CUE_PRG_difCur_thrd U8, Current Frame Intra-Field up/down
- * line chroma difference threshold,
- */
-#define NR2_CONV_MODE ((0x177f)) /* << 2) + 0xd0100000) */
-/* Bit 3:2, Conv_c444_mode
- * The format convert mode about 422 to 444 when data read out line buffer
- */
-/* Bit 1:0, Conv_c422_mode
- * the format convert mode about 444 to 422 when data write to line buffer
- */
-/* // NR2 REG DEFINE END //// */
-/* // DET 3D REG DEFINE BEGIN //// */
-/* for gxlx */
-#define DI_EI_DRT_CTRL_GXLX ((0x2028))
-
-#define DI_EI_DRT_PIXTH_GXLX ((0x2029))
-
-#define DI_EI_DRT_CORRPIXTH_GXLX ((0x202a))
-
-#define DI_EI_DRT_RECTG_WAVE_GXLX ((0x202b))
-
-#define DI_EI_DRT_PIX_DIFFTH_GXLX ((0x202c))
-
-#define DI_EI_DRT_UNBITREND_TH_GXLX ((0x202d))
-#define DET3D_RO_SPLT_HB ((0x1780)) /* << 2) + 0xd0100000) */
-/* Bit 24, RO_Det3D_Split_HB_valid
- * U1 horizontal LR split border detected valid signal for top half picture
- */
-/* Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for
- * the LR split position estimation for top half picture
- */
-/* Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of
- * LR split position to the (ColMax/2) for top half picture
- */
-#define DET3D_RO_SPLT_VL ((0x1781)) /* << 2) + 0xd0100000) */
-/* Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split
- * border detected valid signal for top half picture
- */
-/* Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for
- * the LR split position estimation for top half picture
- */
-/* Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of
- * LR split position to the (ColMax/2) for top half picture
- */
-#define DET3D_RO_SPLT_VR ((0x1782)) /* << 2) + 0xd0100000) */
-/* Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border
- * detected valid signal for top half picture
- */
-/* Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for
- * the LR split position estimation for top half picture
- */
-/* Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of
- * LR split position to the (ColMax/2) for top half picture
- */
-#define DET3D_RO_MAT_LUMA_LR ((0x1783)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right
- * decision score for each band (8bands vertically),
- */
-/* it can be -1/0/1:-1: most likely not LR symmetric 0: not sure
- * 1: most likely LR symmetric
- */
-/* Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left
- * right pure symmetric for each band (8bands vertically),
- */
-/* it can be 0/1: 0: not sure 1: most likely LR is pure symmetric */
-/* Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma
- * statistics for LR like decision,
- */
-/* the larger this score, the more confidence that this is a LR 3D video.
- * It is sum of RO_Luma_LR_score[0~7]
- */
-#define DET3D_RO_MAT_LUMA_TB ((0x1784)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom
- * decision score for each band (8bands Horizontally),
- */
-/* Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure
- * symmetric for each band (8bands Horizontally),
- */
-/* Bit 4:0, RO_Luma_TB_sum
- * Total score of 8x8 Luma statistics for TB like decision,
- */
-#define DET3D_RO_MAT_CHRU_LR ((0x1785)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right
- * decision score for each band (8bands vertically),
- */
-/* Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure
- * symmetric for each band (8bands vertically),
- */
-/* Bit 4:0, RO_ChrU_LR_sum
- * Total score of 8x8 ChrU statistics for LR like decision,
- */
-#define DET3D_RO_MAT_CHRU_TB ((0x1786)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom
- * decision score for each band (8bands Horizontally)
- */
-/* Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric
- * for each band (8bands Horizontally)
- */
-/* Bit 4:0, RO_ChrU_TB_sum
- * Total score of 8x8 ChrU statistics for TB like decision
- */
-#define DET3D_RO_MAT_CHRV_LR ((0x1787)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision
- * score for each band (8bands vertically)
- */
-/* Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure
- * symmetric for each band (8bands vertically)
- */
-/* Bit 4:0, RO_ChrV_LR_sum
- * Total score of 8x8 ChrV statistics for LR like decision
- */
-#define DET3D_RO_MAT_CHRV_TB ((0x1788)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision
- * score for each band (8bands Horizontally)
- */
-/* Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure
- * symmetric for each band (8bands Horizontally)
- */
-/* Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics
- * for TB like decision
- */
-#define DET3D_RO_MAT_HEDG_LR ((0x1789)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right
- * decision score for each band (8bands vertically)
- */
-/* Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right
- * pure symmetric for each band (8bands vertically)
- */
-/* Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for
- * LR like decision
- */
-#define DET3D_RO_MAT_HEDG_TB ((0x178a)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom
- * decision score for each band (8bands Horizontally)
- */
-/* Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics
- * Top/Bottompure symmetric for each band (8bands Horizontally)
- */
-/* Bit 4:0, RO_Hedg_TB_sum
- * Total score of 8x8 Hedg statistics for TB like decision
- */
-#define DET3D_RO_MAT_VEDG_LR ((0x178b)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right
- * decision score for each band (8bands vertically)
- */
-/* Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right
- * pure symmetric for each band (8bands vertically)
- */
-/* Bit 4:0, RO_Vedg_LR_sum
- * Total score of 8x8 Vedg statistics for LR like decision
- */
-#define DET3D_RO_MAT_VEDG_TB ((0x178c)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom
- * decision score for each band (8bands Horizontally)
- */
-/* Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure
- * symmetric for each band (8bands Horizontally)
- */
-/* Bit 4:0, RO_Vedg_TB_sum
- * Total score of 8x8 Vedg statistics for TB like decision
- */
-#define DET3D_RO_MAT_MOTN_LR ((0x178d)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Motn_LR_score Motion statistics left right decision
- * score for each band (8bands vertically)
- */
-/* Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure
- * symmetric for each band (8bands vertically)
- */
-/* Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for
- * LR like decision
- */
-#define DET3D_RO_MAT_MOTN_TB ((0x178e)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision
- * score for each band (8bands Horizontally)
- */
-/* Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure
- * symmetric for each band (8bands Horizontally)
- */
-/* Bit 4:0, RO_Motn_TB_sum
- * Total score of 8x8 Motion statistics for TB like decision
- */
-#define DET3D_RO_FRM_MOTN ((0x178f)) /* << 2) + 0xd0100000) */
-/* Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for
- * still image decision in FW.
- */
-/* mat ram read enter addr */
-#define DET3D_RAMRD_ADDR_PORT ((0x179a)) /* << 2) + 0xd0100000) */
-#define DET3D_RAMRD_DATA_PORT ((0x179b)) /* << 2) + 0xd0100000) */
-#define NR2_CFR_PARA_CFG0 ((0x179c)) /* << 2) + 0xd0100000) */
-/* Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma
- * difference calculation mode
- */
-/* Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based
- * phase register that need to be set by FW phase to phase:
- */
-/* this will be calculated based on dbdr_phase of the
- * specific line of this frame.
- */
-/* u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center
- * line is Dr in current line;
- */
-/* Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line
- * Luma/Chroma transition level calculation mode,
- */
-/* Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for
- * CFR block from curAlp and motAlp i.e.
- * 0: motAlp; 1: (motAlp+curAlp)/2;
- * 2: min(motAlp,curAlp); 3: max(motAlp,curAlp);
- */
-/* Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation
- * mode for MA-CFR.
- * 0: top/bot Lumma motion;
- * 1: middle Luma Motion
- * 2: top/bot + middle motion;
- * 3: max(top/tot motion, middle motion)
- */
-#define NR2_CFR_PARA_CFG1 ((0x179d)) /* << 2) + 0xd0100000) */
-/* Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp
- * to alpha that will be used for final blending.
- */
-/* Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the
- * motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as
- * the level of motion that we consider it at moving.
- */
-/* Bit 7: 0, reg_CFR_CurDif_gain
- * gain to CurDif to map to alpha, normalized to 32;
- */
-/* // DET 3D REG DEFINE END //// */
-#define DI_NR_1_CTRL0 ((0x1794)) /* << 2) + 0xd0100000) */
-#define DI_NR_1_CTRL1 ((0x1795)) /* << 2) + 0xd0100000) */
-#define DI_NR_1_CTRL2 ((0x1796)) /* << 2) + 0xd0100000) */
-#define DI_NR_1_CTRL3 ((0x1797)) /* << 2) + 0xd0100000) */
-#define DI_CONTWR_X ((0x17a0)) /* << 2) + 0xd0100000) */
-#define DI_CONTWR_Y ((0x17a1)) /* << 2) + 0xd0100000) */
-#define DI_CONTWR_CTRL ((0x17a2)) /* << 2) + 0xd0100000) */
-#define DI_CONTPRD_X ((0x17a3)) /* << 2) + 0xd0100000) */
-#define DI_CONTPRD_Y ((0x17a4)) /* << 2) + 0xd0100000) */
-#define DI_CONTP2RD_X ((0x17a5)) /* << 2) + 0xd0100000) */
-#define DI_CONTP2RD_Y ((0x17a6)) /* << 2) + 0xd0100000) */
-#define DI_CONTRD_CTRL ((0x17a7)) /* << 2) + 0xd0100000) */
-#define DI_NRWR_X ((0x17c0)) /* << 2) + 0xd0100000) */
-#define DI_NRWR_Y ((0x17c1)) /* << 2) + 0xd0100000) */
-/* bit 31:30 nrwr_words_lim */
-/* bit 29 nrwr_rev_y */
-/* bit 28:16 nrwr_start_y */
-/* bit 15 nrwr_ext_en */
-/* bit 14 Nrwr bit10 mode */
-/* bit 12:0 nrwr_end_y */
-#define DI_NRWR_CTRL ((0x17c2)) /* << 2) + 0xd0100000) */
-/* bit 31 pending_ddr_wrrsp_diwr */
-/* bit 30 nrwr_reg_swap */
-/* bit 29:26 nrwr_burst_lim */
-/* bit 25 nrwr_canvas_syncen */
-/* bit 24 nrwr_no_clk_gate */
-/* bit 23:22 nrwr_rgb_mode
- * 0:422 to one canvas;
- * 1:4:4:4 to one canvas;
- */
-/* bit 21:20 nrwr_hconv_mode */
-/* bit 19:18 nrwr_vconv_mode */
-/* bit 17 nrwr_swap_cbcr */
-/* bit 16 nrwr_urgent */
-/* bit 15:8 nrwr_canvas_index_chroma */
-/* bit 7:0 nrwr_canvas_index_luma */
-#define DI_MTNWR_X ((0x17c3)) /* << 2) + 0xd0100000) */
-#define DI_MTNWR_Y ((0x17c4)) /* << 2) + 0xd0100000) */
-#define DI_MTNWR_CTRL ((0x17c5)) /* << 2) + 0xd0100000) */
-#define DI_DIWR_X ((0x17c6)) /* << 2) + 0xd0100000) */
-#define DI_DIWR_Y ((0x17c7)) /* << 2) + 0xd0100000) */
-/* bit 31:30 diwr_words_lim */
-/* bit 29 diwr_rev_y */
-/* bit 28:16 diwr_start_y */
-/* bit 15 diwr_ext_en */
-/* bit 12:0 diwr_end_y */
-#define DI_DIWR_CTRL ((0x17c8)) /* << 2) + 0xd0100000) */
-/* bit 31 pending_ddr_wrrsp_diwr */
-/* bit 30 diwr_reg_swap */
-/* bit 29:26 diwr_burst_lim */
-/* bit 25 diwr_canvas_syncen */
-/* bit 24 diwr_no_clk_gate */
-/* bit 23:22 diwr_rgb_mode 0:422 to one canvas;
- * 1:4:4:4 to one canvas;
- */
-/* bit 21:20 diwr_hconv_mode */
-/* bit 19:18 diwr_vconv_mode */
-/* bit 17 diwr_swap_cbcr */
-/* bit 16 diwr_urgent */
-/* bit 15:8 diwr_canvas_index_chroma */
-/* bit 7:0 diwr_canvas_index_luma */
-/* `define DI_MTNCRD_X 8'hc9 */
-/* `define DI_MTNCRD_Y 8'hca */
-#define DI_MTNPRD_X ((0x17cb)) /* << 2) + 0xd0100000) */
-#define DI_MTNPRD_Y ((0x17cc)) /* << 2) + 0xd0100000) */
-#define DI_MTNRD_CTRL ((0x17cd)) /* << 2) + 0xd0100000) */
-#define DI_INP_GEN_REG ((0x17ce)) /* << 2) + 0xd0100000) */
-#define DI_INP_CANVAS0 ((0x17cf)) /* << 2) + 0xd0100000) */
-#define DI_INP_LUMA_X0 ((0x17d0)) /* << 2) + 0xd0100000) */
-#define DI_INP_LUMA_Y0 ((0x17d1)) /* << 2) + 0xd0100000) */
-#define DI_INP_CHROMA_X0 ((0x17d2)) /* << 2) + 0xd0100000) */
-#define DI_INP_CHROMA_Y0 ((0x17d3)) /* << 2) + 0xd0100000) */
-#define DI_INP_RPT_LOOP ((0x17d4)) /* << 2) + 0xd0100000) */
-#define DI_INP_LUMA0_RPT_PAT ((0x17d5)) /* << 2) + 0xd0100000) */
-#define DI_INP_CHROMA0_RPT_PAT ((0x17d6)) /* << 2) + 0xd0100000) */
-#define DI_INP_DUMMY_PIXEL ((0x17d7)) /* << 2) + 0xd0100000) */
-#define DI_INP_LUMA_FIFO_SIZE ((0x17d8)) /* << 2) + 0xd0100000) */
-#define DI_INP_RANGE_MAP_Y ((0x17ba)) /* << 2) + 0xd0100000) */
-#define DI_INP_RANGE_MAP_CB ((0x17bb)) /* << 2) + 0xd0100000) */
-#define DI_INP_RANGE_MAP_CR ((0x17bc)) /* << 2) + 0xd0100000) */
-#define DI_INP_GEN_REG2 ((0x1791)) /* << 2) + 0xd0100000) */
-#define DI_INP_FMT_CTRL ((0x17d9)) /* << 2) + 0xd0100000) */
-#define DI_INP_FMT_W ((0x17da)) /* << 2) + 0xd0100000) */
-#define DI_MEM_GEN_REG ((0x17db)) /* << 2) + 0xd0100000) */
-#define DI_MEM_CANVAS0 ((0x17dc)) /* << 2) + 0xd0100000) */
-#define DI_MEM_LUMA_X0 ((0x17dd)) /* << 2) + 0xd0100000) */
-#define DI_MEM_LUMA_Y0 ((0x17de)) /* << 2) + 0xd0100000) */
-#define DI_MEM_CHROMA_X0 ((0x17df)) /* << 2) + 0xd0100000) */
-#define DI_MEM_CHROMA_Y0 ((0x17e0)) /* << 2) + 0xd0100000) */
-#define DI_MEM_RPT_LOOP ((0x17e1)) /* << 2) + 0xd0100000) */
-#define DI_MEM_LUMA0_RPT_PAT ((0x17e2)) /* << 2) + 0xd0100000) */
-#define DI_MEM_CHROMA0_RPT_PAT ((0x17e3)) /* << 2) + 0xd0100000) */
-#define DI_MEM_DUMMY_PIXEL ((0x17e4)) /* << 2) + 0xd0100000) */
-#define DI_MEM_LUMA_FIFO_SIZE ((0x17e5)) /* << 2) + 0xd0100000) */
-#define DI_MEM_RANGE_MAP_Y ((0x17bd)) /* << 2) + 0xd0100000) */
-#define DI_MEM_RANGE_MAP_CB ((0x17be)) /* << 2) + 0xd0100000) */
-#define DI_MEM_RANGE_MAP_CR ((0x17bf)) /* << 2) + 0xd0100000) */
-#define DI_MEM_GEN_REG2 ((0x1792)) /* << 2) + 0xd0100000) */
-#define DI_MEM_FMT_CTRL ((0x17e6)) /* << 2) + 0xd0100000) */
-#define DI_MEM_FMT_W ((0x17e7)) /* << 2) + 0xd0100000) */
-/* #define DI_IF1_GEN_REG ((0x17e8)) + 0xd0100000) */
-#define DI_IF1_CANVAS0 ((0x17e9)) /* << 2) + 0xd0100000) */
-#define DI_IF1_LUMA_X0 ((0x17ea)) /* << 2) + 0xd0100000) */
-#define DI_IF1_LUMA_Y0 ((0x17eb)) /* << 2) + 0xd0100000) */
-#define DI_IF1_CHROMA_X0 ((0x17ec)) /* << 2) + 0xd0100000) */
-#define DI_IF1_CHROMA_Y0 ((0x17ed)) /* << 2) + 0xd0100000) */
-#define DI_IF1_RPT_LOOP ((0x17ee)) /* << 2) + 0xd0100000) */
-#define DI_IF1_LUMA0_RPT_PAT ((0x17ef)) /* << 2) + 0xd0100000) */
-#define DI_IF1_CHROMA0_RPT_PAT ((0x17f0)) /* << 2) + 0xd0100000) */
-#define DI_IF1_DUMMY_PIXEL ((0x17f1)) /* << 2) + 0xd0100000) */
-#define DI_IF1_LUMA_FIFO_SIZE ((0x17f2)) /* << 2) + 0xd0100000) */
-#define DI_IF1_RANGE_MAP_Y ((0x17fc)) /* << 2) + 0xd0100000) */
-#define DI_IF1_RANGE_MAP_CB ((0x17fd)) /* << 2) + 0xd0100000) */
-#define DI_IF1_RANGE_MAP_CR ((0x17fe)) /* << 2) + 0xd0100000) */
-#define DI_IF1_GEN_REG2 ((0x1790)) /* << 2) + 0xd0100000) */
-#define DI_IF1_FMT_CTRL ((0x17f3)) /* << 2) + 0xd0100000) */
-#define DI_IF1_FMT_W ((0x17f4)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_GEN_REG ((0x17f5)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_CANVAS0 ((0x17f6)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_LUMA_X0 ((0x17f7)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_LUMA_Y0 ((0x17f8)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_CHROMA_X0 ((0x17f9)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_CHROMA_Y0 ((0x17fa)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_RPT_LOOP ((0x17fb)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_LUMA0_RPT_PAT ((0x17b0)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_CHROMA0_RPT_PAT ((0x17b1)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_DUMMY_PIXEL ((0x17b2)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_LUMA_FIFO_SIZE ((0x17b3)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_RANGE_MAP_Y ((0x17b4)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_RANGE_MAP_CB ((0x17b5)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_RANGE_MAP_CR ((0x17b6)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_GEN_REG2 ((0x17b7)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_FMT_CTRL ((0x17b8)) /* << 2) + 0xd0100000) */
-#define DI_CHAN2_FMT_W ((0x17b9)) /* << 2) + 0xd0100000) */
-#define DI_CANVAS_URGENT0 ((0x170a)) /* << 2) + 0xd0100000) */
-#define DI_CANVAS_URGENT1 ((0x170b)) /* << 2) + 0xd0100000) */
-#define DI_MTN_CTRL ((0x170b)) /* << 2) + 0xd0100000) */
-#define DI_CANVAS_URGENT2 ((0x170e)) /* << 2) + 0xd0100000) */
-
-#define VD1_IF0_GEN_REG 0x1a50
-/* ((0x1a50 << 2) + 0xd0100000) */
-#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
-/* ((0x1a63 << 2) + 0xd0100000) */
-
-#define VIU_VD1_FMT_CTRL 0x1a68
-/* ((0x1a68 << 2) + 0xd0100000) */
-/* Bit 31 it true, disable clock, otherwise enable clock */
-/* Bit 30 soft rst bit */
-/* Bit 28 if true, horizontal formatter use repeating to */
-/* generete pixel, otherwise use bilinear interpolation */
-/* Bit 27:24 horizontal formatter initial phase */
-/* Bit 23 horizontal formatter repeat pixel 0 enable */
-/* Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 */
-/* Bit 20 horizontal formatter enable */
-/* Bit 19 if true, always use phase0 while vertical formater, */
-/* meaning always repeat data, no interpolation */
-/* Bit 18 if true, disable vertical formatter chroma repeat last line */
-/* Bit 17 veritcal formatter dont need repeat */
-/* line on phase0, 1: enable, 0: disable */
-/* Bit 16 veritcal formatter repeat line 0 enable */
-/* Bit 15:12 vertical formatter skip line num at the beginning */
-/* Bit 11:8 vertical formatter initial phase */
-/* Bit 7:1 vertical formatter phase step (3.4) */
-/* Bit 0 vertical formatter enable */
-#define VIU_VD1_FMT_W 0x1a69
-/* ((0x1a69 << 2) + 0xd0100000) */
-/* Bit 27:16 horizontal formatter width */
-/* Bit 11:0 vertical formatter width */
-
-#define VD1_IF0_GEN_REG2 0x1a6d
-
-#define DI_INP_GEN_REG3 0x20a8
- /* 0xd01082a0 */
-/*bit9:8 bit mode: 0 = 8bits, 1=10bits 422, 2 = 10bits 444 */
-#define DI_MEM_GEN_REG3 0x20a9
- /* 0xd01082a4 */
-/*bit9:8 bit mode: 0 = 8bits, 1=10bits 422, 2 = 10bits 444 */
-#define DI_CHAN2_GEN_REG3 0x20aa
- /* 0xd01082a8 */
-/* dnr Base Addr: 0xd0100000 */
-#define DNR_CTRL ((0x2d00))
-/* Bit 31:17, reserved */
-/* Bit 16, reg_dnr_en,
- * dnr enable . unsigned , default = 1
- */
-/* Bit 15, reg_dnr_db_vdbstep ,
- * vdb step, 0: 4, 1: 8 . unsigned , default = 1
- */
-/* Bit 14, reg_dnr_db_vdbprten ,
- * vdb protectoin enable . unsigned , default = 1
- */
-/* Bit 13, reg_dnr_gbs_difen ,
- * enable dif (between LR and LL/RR) condition for gbs stat..
- * unsigned , default = 0
- */
-/* Bit 12, reg_dnr_luma_en ,
- * enable ycbcr2luma module . unsigned , default = 1
- */
-/* Bit 11:10, reg_dnr_db_mod ,
- * deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical
- * deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3
- */
-/* Bit 9, reg_dnr_db_chrmen ,
- * enable chroma deblocking . unsigned , default = 1
- */
-/* Bit 8, reg_dnr_hvdif_mod ,
- * 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1
- */
-/* Bit 7, reserved */
-/* Bit 6: 4, reg_dnr_demo_lften ,
- * b0: Y b1:U b2:V . unsigned , default = 7
- */
-/* Bit 3, reserved */
-/* Bit 2: 0, reg_dnr_demo_rgten ,
- * b0: Y b1:U b2:V . unsigned , default = 7
- */
-#define DNR_HVSIZE ((0x2d01))
-/* Bit 31:29, reserved */
-/* Bit 28:16, reg_dnr_hsize ,
- * hsize . unsigned , default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 0, reg_dnr_vsize ,
- * vsize . unsigned , default = 0
- */
-#define DNR_DBLK_BLANK_NUM ((0x2d02))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_dblk_hblank_num ,
- * deblock hor blank num . unsigned , default = 16
- */
-/* Bit 7: 0, reg_dblk_vblank_num ,
- * deblock ver blank num . unsigned , default = 45
- */
-#define DNR_BLK_OFFST ((0x2d03))
-/* Bit 31: 7, reserved */
-/* Bit 6: 4, reg_dnr_hbofst ,
- * horizontal block offset may provide by software calc.. unsigned ,
- * default = 0
- */
-/* Bit 3, reserved */
-/* Bit 2: 0, reg_dnr_vbofst ,
- * vertical block offset may provide by software calc.. unsigned , default = 0
- */
-#define DNR_GBS ((0x2d04))
-/* Bit 31: 2, reserved */
-/* Bit 1: 0, reg_dnr_gbs ,
- * global block strength may update by software calc.. unsigned , default = 0
- */
-#define DNR_HBOFFST_STAT ((0x2d05))
-/* Bit 31:24, reg_dnr_hbof_difthd ,
- * dif threshold (>=) between LR and LL/RR. unsigned , default = 2
- */
-/* Bit 23:16, reg_dnr_hbof_edgethd ,
- * edge threshold (<=) for LR . unsigned , default = 32
- */
-/* Bit 15: 8, reg_dnr_hbof_flatthd ,
- * flat threshold (>=) for LR . unsigned , default = 0
- */
-/* Bit 7, reserved */
-/* Bit 6: 4, reg_dnr_hbof_delta ,
- * delta for weighted bin accumulator. unsigned , default = 1
- */
-/* Bit 3, reserved */
-/* Bit 2: 0, reg_dnr_hbof_statmod ,
- * statistic mode for horizontal block offset, 0: count flags for 8-bin,
- * 1: count LRs for 8-bin, 2: count difs for 8-bin,
- * 3: count weighted flags for 8-bin, 4: count flags for first 32-bin,
- * 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin.
- * unsigned , default = 2
- */
-#define DNR_VBOFFST_STAT ((0x2d06))
-/* Bit 31:24, reg_dnr_vbof_difthd ,
- * dif threshold (>=) between Up and Dw. unsigned , default = 1
- */
-/* Bit 23:16, reg_dnr_vbof_edgethd ,
- * edge threshold (<=) for Up/Dw. unsigned , default = 16
- */
-/* Bit 15: 8, reg_dnr_vbof_flatthd ,
- * flat threshold (>=) for Up/Dw. unsigned , default = 0
- */
-/* Bit 7, reserved */
-/* Bit 6: 4, reg_dnr_vbof_delta ,
- * delta for weighted bin accumulator. unsigned , default = 1
- */
-/* Bit 3, reserved */
-/* Bit 2: 0, reg_dnr_vbof_statmod ,
- * statistic mode for vertical block offset, 0: count flags for 8-bin,
- * 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted
- * flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for
- * first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
- */
-#define DNR_GBS_STAT ((0x2d07))
-/* Bit 31:24, reg_dnr_gbs_edgethd ,
- * edge threshold (<=) for LR . unsigned , default = 32
- */
-/* Bit 23:16, reg_dnr_gbs_flatthd ,
- * flat threshold (>=) for LR . unsigned , default = 0
- */
-/* Bit 15: 8, reg_dnr_gbs_varthd ,
- * variation threshold (<=) for Lvar/Rvar. unsigned , default = 16
- */
-/* Bit 7: 0, reg_dnr_gbs_difthd ,
- * dif threshold (>=) between LR and LL/RR. unsigned , default = 2
- */
-#define DNR_STAT_X_START_END ((0x2d08))
-/* Bit 31:30, reserved */
-/* Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24 */
-/* Bit 15:14, reserved */
-/* Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25 */
-#define DNR_STAT_Y_START_END ((0x2d09))
-/* Bit 31:30, reserved */
-/* Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24 */
-/* Bit 15:14, reserved */
-/* Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25 */
-#define DNR_LUMA ((0x2d0a))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_dnr_luma_sqrtshft ,
- * left shift for fast squart of chroma, [0, 4]. unsigned , default = 2
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_dnr_luma_sqrtoffst ,
- * offset for fast squart of chroma. signed , default = 0
- */
-/* Bit 15, reserved */
-/* Bit 14:12, reg_dnr_luma_wcmod ,
- * theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135,
- * 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3
- */
-/* Bit 11: 8, reg_dnr_luma_cshft ,
- * shift for calc. delta part, 0~8, . unsigned , default = 8
- */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_dnr_luma_cgain ,
- * final gain for delta part, 32 normalized to "1". unsigned , default = 4
- */
-#define DNR_DB_YEDGE_THD ((0x2d0b))
-/* Bit 31:24, reg_dnr_db_yedgethd0 ,
- * edge threshold0 for luma . unsigned , default = 12
- */
-/* Bit 23:16, reg_dnr_db_yedgethd1 ,
- * edge threshold1 for luma . unsigned , default = 15
- */
-/* Bit 15: 8, reg_dnr_db_yedgethd2 ,
- * edge threshold2 for luma . unsigned , default = 18
- */
-/* Bit 7: 0, reg_dnr_db_yedgethd3 ,
- * edge threshold3 for luma . unsigned , default = 25
- */
-#define DNR_DB_CEDGE_THD ((0x2d0c))
-/* Bit 31:24, reg_dnr_db_cedgethd0 ,
- * edge threshold0 for chroma . unsigned , default = 12
- */
-/* Bit 23:16, reg_dnr_db_cedgethd1 ,
- * edge threshold1 for chroma . unsigned , default = 15
- */
-/* Bit 15: 8, reg_dnr_db_cedgethd2 ,
- * edge threshold2 for chroma . unsigned , default = 18
- */
-/* Bit 7: 0, reg_dnr_db_cedgethd3 ,
- * edge threshold3 for chroma . unsigned , default = 25
- */
-#define DNR_DB_HGAP ((0x2d0d))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_dnr_db_hgapthd ,
- * horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8
- */
-/* Bit 15: 8, reg_dnr_db_hgapdifthd ,
- * dif thd between hgap and lft/rgt hdifs. unsigned , default = 1
- */
-/* Bit 7: 1, reserved */
-/* Bit 0, reg_dnr_db_hgapmod ,
- * horizontal gap calc. mode, 0: just use current col x,
- * 1: find max between (x-1, x, x+1) . unsigned , default = 0
- */
-#define DNR_DB_HBS ((0x2d0e))
-/* Bit 31: 6, reserved */
-/* Bit 5: 4, reg_dnr_db_hbsup ,
- * horizontal bs up value . unsigned , default = 1
- */
-/* Bit 3: 2, reg_dnr_db_hbsmax ,
- * max value of hbs for global control. unsigned , default = 3
- */
-/* Bit 1: 0, reg_dnr_db_hgbsthd ,
- * gbs thd (>=) for hbs calc. . unsigned , default = 1
- */
-#define DNR_DB_HACT ((0x2d0f))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_dnr_db_hactthd0 ,
- * thd0 of hact, for block classification. unsigned , default = 10
- */
-/* Bit 7: 0, reg_dnr_db_hactthd1 ,
- * thd1 of hact, for block classification. unsigned , default = 32
- */
-#define DNR_DB_YHDELTA_GAIN ((0x2d10))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_dnr_db_yhdeltagain1 ,
- * (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" .
- * unsigned , default = 2
- */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_dnr_db_yhdeltagain2 ,
- * (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" .
- * unsigned , default = 0
- */
-/* Bit 19, reserved */
-/* Bit 18:16, reg_dnr_db_yhdeltagain3 ,
- * (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" .
- * unsigned , default = 0
- */
-/* Bit 15, reserved */
-/* Bit 14: 8, reg_dnr_db_yhdeltaadjoffst ,
- * offset for adjust Y's hdelta (-64, 63). signed , default = 0
- */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_dnr_db_yhdeltaadjgain ,
- * gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32
- */
-#define DNR_DB_YHDELTA2_GAIN ((0x2d11))
-/* Bit 31:30, reserved */
-/* Bit 29:24, reg_dnr_db_yhdelta2gain2 ,
- * gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" .
- * unsigned , default = 8
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_dnr_db_yhdelta2offst2 ,
- * offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_dnr_db_yhdelta2gain3 ,
- * gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" .
- * unsigned , default = 4
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_db_yhdelta2offst3 ,
- * offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0
- */
-#define DNR_DB_CHDELTA_GAIN ((0x2d12))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_dnr_db_chdeltagain1 ,
- * (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1".
- * unsigned , default = 2
- */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_dnr_db_chdeltagain2 ,
- * (p1-q1) gain for UV's delta calc. when bs=2,
- * normalized 8 as "1". unsigned , default = 0
- */
-/* Bit 19, reserved */
-/* Bit 18:16, reg_dnr_db_chdeltagain3 ,
- * (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1".
- * unsigned , default = 0
- */
-/* Bit 15, reserved */
-/* Bit 14: 8, reg_dnr_db_chdeltaadjoffst ,
- * offset for adjust UV's hdelta (-64, 63). signed , default = 0
- */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_dnr_db_chdeltaadjgain ,
- * gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32
- */
-#define DNR_DB_CHDELTA2_GAIN ((0x2d13))
-/* Bit 31:30, reserved */
-/* Bit 29:24, reg_dnr_db_chdelta2gain2 ,
- * gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" .
- * unsigned , default = 8
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_dnr_db_chdelta2offst2 ,
- * offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_dnr_db_chdelta2gain3 ,
- * gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" .
- * unsigned , default = 4
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_db_chdelta2offst3 ,
- * offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
- */
-#define DNR_DB_YC_VEDGE_THD ((0x2d14))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_dnr_db_yvedgethd ,
- * special Y's edge thd for vdb. unsigned , default = 12
- */
-/* Bit 7: 0, reg_dnr_db_cvedgethd ,
- * special UV's edge thd for vdb. unsigned , default = 12
- */
-#define DNR_DB_VBS_MISC ((0x2d15))
-/* Bit 31:24, reg_dnr_db_vgapthd ,
- * vertical gap thd (<=) for very sure blockiness . unsigned , default = 8
- */
-/* Bit 23:16, reg_dnr_db_vactthd ,
- * thd of vact, for block classification . unsigned , default = 10
- */
-/* Bit 15: 8, reg_dnr_db_vgapdifthd ,
- * dif thd between vgap and vact. unsigned , default = 4
- */
-/* Bit 7: 4, reserved */
-/* Bit 3: 2, reg_dnr_db_vbsmax ,
- * max value of vbs for global control. unsigned , default = 2
- */
-/* Bit 1: 0, reg_dnr_db_vgbsthd ,
- * gbs thd (>=) for vbs calc. . unsigned , default = 1
- */
-#define DNR_DB_YVDELTA_GAIN ((0x2d16))
-/* Bit 31:30, reserved */
-/* Bit 29:24, reg_dnr_db_yvdeltaadjgain ,
- * gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32
- */
-/* Bit 23, reserved */
-/* Bit 22:16, reg_dnr_db_yvdeltaadjoffst ,
- * offset for adjust Y's vdelta (-64, 63). signed , default = 0
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_dnr_db_yvdelta2gain ,
- * gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_db_yvdelta2offst ,
- * offset for adjust Y's vdelta2 (-16, 15). signed , default = 0
- */
-#define DNR_DB_CVDELTA_GAIN ((0x2d17))
-/* Bit 31:30, reserved */
-/* Bit 29:24, reg_dnr_db_cvdeltaadjgain ,
- * gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32
- */
-/* Bit 23, reserved */
-/* Bit 22:16, reg_dnr_db_cvdeltaadjoffst ,
- * offset for adjust UV's vdelta (-64, 63). signed , default = 0
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_dnr_db_cvdelta2gain ,
- * gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_db_cvdelta2offst ,
- * offset for adjust UV's vdelta2 (-16, 15). signed , default = 0
- */
-#define DNR_RO_GBS_STAT_LR ((0x2d18))
-/* Bit 31: 0, ro_gbs_stat_lr
- * . unsigned , default = 0
- */
-#define DNR_RO_GBS_STAT_LL ((0x2d19))
-/* Bit 31: 0, ro_gbs_stat_ll
- * . unsigned , default = 0
- */
-#define DNR_RO_GBS_STAT_RR ((0x2d1a))
-/* Bit 31: 0, ro_gbs_stat_rr
- * . unsigned , default = 0
- */
-#define DNR_RO_GBS_STAT_DIF ((0x2d1b))
-/* Bit 31: 0, ro_gbs_stat_dif
- * . unsigned , default = 0
- */
-#define DNR_RO_GBS_STAT_CNT ((0x2d1c))
-/* Bit 31: 0, ro_gbs_stat_cnt
- * . unsigned , default = 0
- */
-#define DNR_RO_HBOF_STAT_CNT_0 ((0x2d1d))
-/* Bit 31: 0, ro_hbof_stat_cnt0
- * . unsigned , default = 0
- */
-#define DNR_RO_HBOF_STAT_CNT_1 ((0x2d1e))
-/* Bit 31: 0, ro_hbof_stat_cnt1
- * . unsigned , default = 0
- */
-#define DNR_RO_HBOF_STAT_CNT_2 ((0x2d1f))
-/* Bit 31: 0, ro_hbof_stat_cnt2
- * . unsigned , default = 0
- */
-#define DNR_RO_HBOF_STAT_CNT_3 ((0x2d20))
-/* Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_4 ((0x2d21))
-/* Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_5 ((0x2d22))
-/* Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_6 ((0x2d23))
-/* Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_7 ((0x2d24))
-/* Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_8 ((0x2d25))
-/* Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_9 ((0x2d26))
-/* Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_10 ((0x2d27))
-/* Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_11 ((0x2d28))
-/* Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_12 ((0x2d29))
-/* Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_13 ((0x2d2a))
-/* Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_14 ((0x2d2b))
-/* Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_15 ((0x2d2c))
-/* Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_16 ((0x2d2d))
-/* Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_17 ((0x2d2e))
-/* Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_18 ((0x2d2f))
-/* Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_19 ((0x2d30))
-/* Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_20 ((0x2d31))
-/* Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_21 ((0x2d32))
-/* Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_22 ((0x2d33))
-/* Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_23 ((0x2d34))
-/* Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_24 ((0x2d35))
-/* Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_25 ((0x2d36))
-/* Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_26 ((0x2d37))
-/* Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_27 ((0x2d38))
-/* Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_28 ((0x2d39))
-/* Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_29 ((0x2d3a))
-/* Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_30 ((0x2d3b))
-/* Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0 */
-#define DNR_RO_HBOF_STAT_CNT_31 ((0x2d3c))
-/* Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_0 ((0x2d3d))
-/* Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_1 ((0x2d3e))
-/* Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_2 ((0x2d3f))
-/* Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_3 ((0x2d40))
-/* Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_4 ((0x2d41))
-/* Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_5 ((0x2d42))
-/* Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_6 ((0x2d43))
-/* Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_7 ((0x2d44))
-/* Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_8 ((0x2d45))
-/* Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_9 ((0x2d46))
-/* Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_10 ((0x2d47))
-/* Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_11 ((0x2d48))
-/* Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_12 ((0x2d49))
-/* Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_13 ((0x2d4a))
-/* Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_14 ((0x2d4b))
-/* Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_15 ((0x2d4c))
-/* Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_16 ((0x2d4d))
-/* Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_17 ((0x2d4e))
-/* Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_18 ((0x2d4f))
-/* Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_19 ((0x2d50))
-/* Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_20 ((0x2d51))
-/* Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_21 ((0x2d52))
-/* Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_22 ((0x2d53))
-/* Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_23 ((0x2d54))
-/* Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_24 ((0x2d55))
-/* Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_25 ((0x2d56))
-/* Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_26 ((0x2d57))
-/* Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_27 ((0x2d58))
-/* Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_28 ((0x2d59))
-/* Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_29 ((0x2d5a))
-/* Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_30 ((0x2d5b))
-/* Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0 */
-#define DNR_RO_VBOF_STAT_CNT_31 ((0x2d5c))
-/* Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0 */
-#define DNR_DM_CTRL ((0x2d60))
-/* Bit 31:13, reserved */
-/* Bit 12, reg_dnr_dm_fedgeflg_en ,
- * enable edge flag calc. of each frame. unsigned , default = 1
- */
-/* Bit 11, reg_dnr_dm_fedgeflg_cl ,
- * clear frame edge flag if needed. unsigned , default = 1
- */
-/* Bit 10, reg_dnr_dm_fedgeflg_df ,
- * user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1
- */
-/* Bit 9, reg_dnr_dm_en ,
- * enable demosquito function . unsigned , default = 1
- */
-/* Bit 8, reg_dnr_dm_chrmen ,
- * enable chrome processing for demosquito. unsigned , default = 1
- */
-/* Bit 7: 6, reg_dnr_dm_level ,
- * demosquito level . unsigned , default = 3
- */
-/* Bit 5: 4, reg_dnr_dm_leveldw0 ,
- * level down when gbs is small. unsigned , default = 1
- */
-/* Bit 3: 2, reg_dnr_dm_leveldw1 ,
- * level down for no edge/flat blocks. unsigned , default = 1
- */
-/* Bit 1: 0, reg_dnr_dm_gbsthd ,
- * small/large threshold for gbs (<=). unsigned , default = 0
- */
-#define DNR_DM_NR_BLND ((0x2d61))
-/* Bit 31:25, reserved */
-/* Bit 24, reg_dnr_dm_defalpen ,
- * enable user define alpha for dm & nr blend. unsigned , default = 0
- */
-/* Bit 23:16, reg_dnr_dm_defalp ,
- * user define alpha for dm & nr blend if enable. unsigned , default = 0
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_dnr_dm_alpgain ,
- * gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32
- */
-/* Bit 7: 0, reg_dnr_dm_alpoffst ,
- * (-128, 127), offset for nr/dm alpha. signed , default = 0
- */
-#define DNR_DM_RNG_THD ((0x2d62))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2 */
-/* Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64 */
-/* Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4 */
-#define DNR_DM_RNG_GAIN_OFST ((0x2d63))
-/* Bit 31:14, reserved */
-/* Bit 13: 8, reg_dnr_dm_rnggain ,
- * normalized 16 as "1" . unsigned , default = 16
- */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0 */
-#define DNR_DM_DIR_MISC ((0x2d64))
-/* Bit 31:30, reserved */
-/* Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1 */
-/* Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0 */
-/* Bit 23:22, reserved */
-/* Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0 */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0 */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31 */
-#define DNR_DM_COR_DIF ((0x2d65))
-/* Bit 31: 4, reserved */
-/* Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3 */
-/* Bit 0, reg_dnr_dm_cordifmod ,
- * 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif.
- * unsigned , default = 1
- */
-#define DNR_DM_FLT_THD ((0x2d66))
-/* Bit 31:24, reg_dnr_dm_fltthd00 ,
- * block flat threshold0 for block average difference when gbs is small,
- * for flat block detection. unsigned , default = 4
- */
-/* Bit 23:16, reg_dnr_dm_fltthd01 ,
- * block flat threshold1 for block average difference when gbs is small,
- * for flat block detection. unsigned , default = 6
- */
-/* Bit 15: 8, reg_dnr_dm_fltthd10 ,
- * block flat threshold0 for block average difference when gbs is large,
- * for flat block detection. unsigned , default = 9
- */
-/* Bit 7: 0, reg_dnr_dm_fltthd11 ,
- * block flat threshold1 for block average difference when gbs is large,
- * for flat block detection. unsigned , default = 12
- */
-#define DNR_DM_VAR_THD ((0x2d67))
-/* Bit 31:24, reg_dnr_dm_varthd00 ,
- * block variance threshold0 (>=) when gbs is small, for flat block
- * detection. unsigned , default = 2
- */
-/* Bit 23:16, reg_dnr_dm_varthd01 ,
- * block variance threshold1 (<=) when gbs is small, for flat block
- * detection. unsigned , default = 15
- */
-/* Bit 15: 8, reg_dnr_dm_varthd10 ,
- * block variance threshold0 (>=) when gbs is large, for flat block
- * detection. unsigned , default = 3
- */
-/* Bit 7: 0, reg_dnr_dm_varthd11 ,
- * block variance threshold1 (<=) when gbs is large, for flat block
- * detection. unsigned , default = 24
- */
-#define DNR_DM_EDGE_DIF_THD ((0x2d68))
-/* Bit 31:24, reg_dnr_dm_edgethd0 ,
- * block edge threshold (<=) when gbs is small, for flat block detection.
- * unsigned , default = 32
- */
-/* Bit 23:16, reg_dnr_dm_edgethd1 ,
- * block edge threshold (<=) when gbs is large, for flat block detection.
- * unsigned , default = 48
- */
-/* Bit 15: 8, reg_dnr_dm_difthd0 ,
- * block dif threshold (<=) when gbs is small, for flat block detection.
- * unsigned , default = 48
- */
-/* Bit 7: 0, reg_dnr_dm_difthd1 ,
- * block dif threshold (<=) when gbs is large, for flat block detection.
- * unsigned , default = 64
- */
-#define DNR_DM_AVG_THD ((0x2d69))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_dnr_dm_avgthd0 ,
- * block average threshold (>=), for flat block detection.
- * unsigned ,default = 160
- */
-/* Bit 7: 0, reg_dnr_dm_avgthd1 ,
- * block average threshold (<=), for flat block detection. unsigned
- * , default = 128
- */
-#define DNR_DM_AVG_VAR_DIF_THD ((0x2d6a))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_dnr_dm_avgdifthd ,
- * block average dif threshold (<) between cur and up block, for flat
- * block detection. unsigned , default = 12
- */
-/* Bit 7: 0, reg_dnr_dm_vardifthd ,
- * block variance dif threshold (>=) between cur and up block, for flat
- * block detection. unsigned , default = 1
- */
-#define DNR_DM_VAR_EDGE_DIF_THD2 ((0x2d6b))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_dnr_dm_varthd2, block variance threshold (>=),
- * for edge block detection.unsigned, default = 24
- */
-/* Bit 15: 8, reg_dnr_dm_edgethd2 ,
- * block edge threshold (>=), for edge block detection. unsigned , default = 40
- */
-/* Bit 7: 0, reg_dnr_dm_difthd2 ,
- * block dif threshold (>=), for edge block detection. unsigned , default = 80
- */
-#define DNR_DM_DIF_FLT_MISC ((0x2d6c))
-/* Bit 31:28, reg_dnr_dm_ldifoob ,
- * pre-defined large dif when pixel out of blocks. unsigned , default = 0
- */
-/* Bit 27:24, reg_dnr_dm_bdifoob ,
- * pre-defined block dif when pixel out of blocks;. unsigned , default = 0
- */
-/* Bit 23:16, reg_dnr_dm_fltalp ,
- * pre-defined alpha for dm and nr blending, when block is flat
- * with mos.. unsigned , default = 200
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_dnr_dm_fltminbdif ,
- * pre-defined min block dif for dm filter,
- * when block is flat with mos.. unsigned , default = 12
- */
-/* Bit 7, reserved */
-/* Bit 6: 2, reg_dnr_dm_difnormgain ,
- * gain for pixel dif normalization for dm filter,
- * normalized 16 as "1". unsigned , default = 16
- */
-/* Bit 1, reg_dnr_dm_difnormen ,
- * enable pixel dif normalization for dm filter. unsigned , default = 1
- */
-/* Bit 0, reg_dnr_dm_difupden ,
- * enable block dif update using max of left, cur, right difs.
- * unsigned , default = 0
- */
-#define DNR_DM_SDIF_LUT0_2 ((0x2d6d))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_sdiflut0 ,
- * normally 0-16 . unsigned , default = 16
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_sdiflut1 ,
- * normally 0-16 . unsigned , default = 14
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_sdiflut2 ,
- * normally 0-16 . unsigned , default = 13
- */
-#define DNR_DM_SDIF_LUT3_5 ((0x2d6e))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_sdiflut3 ,
- * normally 0-16 . unsigned , default = 10
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_sdiflut4 ,
- * normally 0-16 . unsigned , default = 7
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_sdiflut5 ,
- * normally 0-16 . unsigned , default = 5
- */
-#define DNR_DM_SDIF_LUT6_8 ((0x2d6f))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_sdiflut6 ,
- * normally 0-16 . unsigned , default = 3
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_sdiflut7 ,
- * normally 0-16 . unsigned , default = 1
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_sdiflut8 ,
- * normally 0-16 . unsigned , default = 0
- */
-#define DNR_DM_LDIF_LUT0_2 ((0x2d70))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_ldiflut0 ,
- * normally 0-16 . unsigned , default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_ldiflut1 ,
- * normally 0-16 . unsigned , default = 4
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_ldiflut2 ,
- * normally 0-16 . unsigned , default = 12
- */
-#define DNR_DM_LDIF_LUT3_5 ((0x2d71))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_ldiflut3 ,
- * normally 0-16 . unsigned , default = 14
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_ldiflut4 ,
- * normally 0-16 . unsigned , default = 15
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_ldiflut5 ,
- * normally 0-16 . unsigned , default = 16
- */
-#define DNR_DM_LDIF_LUT6_8 ((0x2d72))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_ldiflut6 ,
- * normally 0-16 . unsigned , default = 16
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_ldiflut7 ,
- * normally 0-16 . unsigned , default = 16
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_ldiflut8 ,
- * normally 0-16 . unsigned , default = 16
- */
-#define DNR_DM_DIF2NORM_LUT0_2 ((0x2d73))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_dif2normlut0 ,
- * normally 0-16 . unsigned , default = 16
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_dif2normlut1 ,
- * normally 0-16 . unsigned , default = 5
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_dif2normlut2 ,
- * normally 0-16 . unsigned , default = 3
- */
-#define DNR_DM_DIF2NORM_LUT3_5 ((0x2d74))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_dif2normlut3 ,
- * normally 0-16 . unsigned , default = 2
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_dif2normlut4 ,
- * normally 0-16 . unsigned , default = 2
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_dif2normlut5 ,
- * normally 0-16 . unsigned , default = 1
- */
-#define DNR_DM_DIF2NORM_LUT6_8 ((0x2d75))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_dnr_dm_dif2normlut6 ,
- * normally 0-16 . unsigned , default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_dnr_dm_dif2normlut7 ,
- * normally 0-16 . unsigned , default = 1
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_dnr_dm_dif2normlut8 ,
- * normally 0-16 . unsigned , default = 1
- */
-#define DNR_DM_GMS_THD ((0x2d76))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0 */
-/* Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128 */
-#define DNR_RO_DM_GMS_STAT_CNT ((0x2d77))
-/* Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0 */
-#define DNR_RO_DM_GMS_STAT_MS ((0x2d78))
-/* Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0 */
-/* txl added */
-#define DECOMB_DET_VERT_CON0 (0x2d80)
-#define DECOMB_DET_VERT_CON1 (0x2d81)
-#define DECOMB_DET_EDGE_CON0 (0x2d82)
-#define DECOMB_DET_EDGE_CON1 (0x2d83)
-#define DECOMB_PARA (0x2d84)
-#define DECOMB_BLND_CON0 (0x2d85)
-#define DECOMB_BLND_CON1 (0x2d86)
-#define DECOMB_YC_THRD (0x2d87)
-#define DECOMB_MTN_GAIN_OFST (0x2d88)
-#define DECOMB_CMB_SEL_GAIN_OFST (0x2d89)
-#define DECOMB_WIND00 (0x2d8a)
-#define DECOMB_WIND01 (0x2d8b)
-#define DECOMB_WIND10 (0x2d8c)
-#define DECOMB_WIND11 (0x2d8d)
-#define DECOMB_MODE (0x2d8e)
-#define DECOMB_FRM_SIZE (0x2d8f)
-#define DECOMB_HV_BLANK (0x2d90)
-#define NR2_POLAR3_MODE (0x2d98)
-#define NR2_POLAR3_THRD (0x2d99)
-#define NR2_POLAR3_PARA0 (0x2d9a)
-#define NR2_POLAR3_PARA1 (0x2d9b)
-#define NR2_POLAR3_CTRL (0x2d9c)
-#define NR2_RO_POLAR3_NUMOFPIX (0x2d9d)
-#define NR2_RO_POLAR3_SMOOTHMV (0x2d9e)
-#define NR2_RO_POLAR3_M1 (0x2d9f)
-#define NR2_RO_POLAR3_P1 (0x2da0)
-#define NR2_RO_POLAR3_M2 (0x2da1)
-#define NR2_RO_POLAR3_P2 (0x2da2)
-#define NR2_RO_POLAR3_32 (0x2da3)
-/* txl end */
-
-#define VPU_VD1_MMC_CTRL (0x2703)
-#define VPU_VD2_MMC_CTRL (0x2704)
-#define VPU_DI_IF1_MMC_CTRL (0x2705)
-#define VPU_DI_MEM_MMC_CTRL (0x2706)
-#define VPU_DI_INP_MMC_CTRL (0x2707)
-#define VPU_DI_MTNRD_MMC_CTRL (0x2708)
-#define VPU_DI_CHAN2_MMC_CTRL (0x2709)
-#define VPU_DI_MTNWR_MMC_CTRL (0x270a)
-#define VPU_DI_NRWR_MMC_CTRL (0x270b)
-#define VPU_DI_DIWR_MMC_CTRL (0x270c)
-
-#define MCDI_PD_22_CHK_WND0_X (0x2f59)
-#define MCDI_PD_22_CHK_WND0_Y (0x2f5a)
-#define MCDI_PD_22_CHK_WND1_X (0x2f5b)
-#define MCDI_PD_22_CHK_WND1_Y (0x2f5c)
-#define MCDI_PD_22_CHK_FLG_CNT (0x2f5e)
-/* mc di */
-/* //=================================================================//// */
-/* // memc di core 0 */
-/* //=================================================================//// */
-#define MCDI_HV_SIZEIN ((0x2f00))
-/* Bit 31:29, reserved */
-/* Bit 28:16, reg_mcdi_hsize
- * image horizontal size (number of cols) default=1024
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 0, reg_mcdi_vsize
- * image vertical size (number of rows) default=1024
- */
-#define MCDI_HV_BLKSIZEIN ((0x2f01))
-/* Bit 31, reg_mcdi_vrev default = 0 */
-/* Bit 30, reg_mcdi_hrev default = 0 */
-/* Bit 29:28, reserved */
-/* Bit 27:16, reg_mcdi_blkhsize
- * image horizontal blk size (number of cols) default=1024
- */
-/* Bit 15:13, reserved */
-/* Bit 11: 0, reg_mcdi_blkvsize
- * image vertical blk size (number of rows) default=1024
- */
-#define MCDI_BLKTOTAL ((0x2f02))
-/* Bit 31:24, reserved */
-/* Bit 23: 0, reg_mcdi_blktotal */
-#define MCDI_MOTINEN ((0x2f03))
-/* Bit 31: 2, reserved */
-/* Bit 1, reg_mcdi_motionrefen.
- * enable motion refinement of MA, default = 1
- */
-/* Bit 0, reg_mcdi_motionparadoxen.
- * enable motion paradox detection, default = 1
- */
-#define MCDI_CTRL_MODE ((0x2f04))
-/* Bit 31:28, reserved */
-/* Bit 27:26, reg_mcdi_lmvlocken
- * 0:disable, 1: use max Lmv, 2: use no-zero Lmv,
- * lmv lock enable mode, default = 2
- */
-/* Bit 25, reg_mcdi_reldetrptchken */
-/* 0: unable; 1: enable, enable repeat pattern
- * check (not repeat mv detection) in rel det part, default = 1
- */
-/* Bit 24, reg_mcdi_reldetgmvpd22chken */
-/* 0: unable; 1: enable, enable pull-down 22 mode
- * check in gmv lock mode for rel det, default = 1
- */
-/* Bit 23, reg_mcdi_pd22chken */
-/* 0: unable; 1: enable, enable pull-down 22
- * mode check (lock) function, default = 1
- */
-/* Bit 22, reg_mcdi_reldetlpfen */
-/* 0: unable; 1: enable, enable det value lpf, default = 1 */
-/* Bit 21, reg_mcdi_reldetlmvpd22chken */
-/* 0: unable; 1: enable, enable pull-down 22
- * mode check in lmv lock mode for rel det, default = 1
- */
-/* Bit 20, reg_mcdi_reldetlmvdifchken */
-/* 0: unable; 1: enable, enable lmv dif check
- * in lmv lock mode for rel det, default = 1
- */
-/* Bit 19, reg_mcdi_reldetgmvdifchken */
-/* 0: unable; 1: enable, enable lmv dif check in
- * lmv lock mode for rel det, default = 1
- */
-/* Bit 18, reg_mcdi_reldetpd22chken */
-/* 0: unable; 1: enable, enable pull-down 22
- * mode check for rel det refinement, default = 1
- */
-/* Bit 17, reg_mcdi_reldetfrqchken */
-/* 0: unable; 1: enable, enable mv frequency check in rel det, default = 1 */
-/* Bit 16, reg_mcdi_qmeen */
-/* 0: unable; 1: enable, enable quarter motion estimation, defautl = 1 */
-/* Bit 15, reg_mcdi_refrptmven */
-/* 0: unable; 1: enable, use repeat mv in refinement, default = 1 */
-/* Bit 14, reg_mcdi_refgmven */
-/* 0: unable; 1: enable, use gmv in refinement, default = 1 */
-/* Bit 13, reg_mcdi_reflmven */
-/* 0: unable; 1: enable, use lmvs in refinement, default = 1 */
-/* Bit 12, reg_mcdi_refnmven */
-/* 0: unable; 1: enable, use neighoring mvs in refinement, default = 1 */
-/* Bit 11, reserved */
-/* Bit 10, reg_mcdi_referrfrqchken */
-/* 0: unable; 1: enable, enable mv frquency
- * check while finding min err in ref, default = 1
- */
-/* Bit 9, reg_mcdi_refen */
-/* 0: unable; 1: enable, enable mv refinement, default = 1
- */
-/* Bit 8, reg_mcdi_horlineen */
-/* 0: unable; 1: enable,enable horizontal lines
- * detection by sad map, default = 1
- */
-/* Bit 7, reg_mcdi_highvertfrqdeten */
-/* 0: unable; 1: enable, enable high vertical
- * frequency pattern detection, default = 1
- */
-/* Bit 6, reg_mcdi_gmvlocken */
-/* 0: unable; 1: enable, enable gmv lock mode, default = 1 */
-/* Bit 5, reg_mcdi_rptmven */
-/* 0: unable; 1: enable, enable repeat pattern detection, default = 1 */
-/* Bit 4, reg_mcdi_gmven */
-/* 0: unable; 1: enable, enable global motion estimation, default = 1 */
-/* Bit 3, reg_mcdi_lmven */
-/* 0: unable; 1: enable, enable line mv estimation for hme, default = 1 */
-/* Bit 2, reg_mcdi_chkedgeen */
-/* 0: unable; 1: enable, enable check edge function, default = 1 */
-/* Bit 1, reg_mcdi_txtdeten */
-/* 0: unable; 1: enable, enable texture detection, default = 1 */
-/* Bit 0, reg_mcdi_memcen */
-/* 0: unable; 1: enable, enable of memc di, default = 1 */
-#define MCDI_UNI_MVDST ((0x2f05))
-/* Bit 31:20, reserved */
-/* Bit 19:17, reg_mcdi_unimvdstabsseg0
- * segment0 for uni-mv abs, default = 1
- */
-/* Bit 16:12, reg_mcdi_unimvdstabsseg1
- * segment1 for uni-mv abs, default = 15
- */
-/* Bit 11: 8, reg_mcdi_unimvdstabsdifgain0
- * 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2
- */
-/* Bit 7: 5, reg_mcdi_unimvdstabsdifgain1
- * 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2
- */
-/* Bit 4: 2, reg_mcdi_unimvdstabsdifgain2
- * 2/2, gain2 of uni-mv abs dif beyond segment1,normalized 2 to '1', default = 2
- */
-/* Bit 1: 0, reg_mcdi_unimvdstsgnshft
- * shift for neighboring distance of uni-mv, default = 0
- */
-#define MCDI_BI_MVDST ((0x2f06))
-/* Bit 31:20, reserved */
-/* Bit 19:17, reg_mcdi_bimvdstabsseg0
- * segment0 for bi-mv abs, default = 1
- */
-/* Bit 16:12, reg_mcdi_bimvdstabsseg1
- * segment1 for bi-mv abs, default = 9
- */
-/* Bit 11: 8, reg_mcdi_bimvdstabsdifgain0
- * 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6
- */
-/* Bit 7: 5, reg_mcdi_bimvdstabsdifgain1
- * 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3
- */
-/* Bit 4: 2, reg_mcdi_bimvdstabsdifgain2
- * 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2
- */
-/* Bit 1: 0, reg_mcdi_bimvdstsgnshft
- * shift for neighboring distance of bi-mv, default = 0
- */
-#define MCDI_SAD_GAIN ((0x2f07))
-/* Bit 31:19, reserved */
-/* Bit 18:17, reg_mcdi_unisadcorepxlgain
- * uni-sad core pixels gain, default = 3
- */
-/* Bit 16, reg_mcdi_unisadcorepxlnormen
- * enable uni-sad core pixels normalization, default = 0
- */
-/* Bit 15:11, reserved */
-/* Bit 10: 9, reg_mcdi_bisadcorepxlgain
- * bi-sad core pixels gain, default = 3
- */
-/* Bit 8, reg_mcdi_bisadcorepxlnormen
- * enable bi-sad core pixels normalization, default = 1
- */
-/* Bit 7: 3, reserved */
-/* Bit 2: 1, reg_mcdi_biqsadcorepxlgain
- * bi-qsad core pixels gain, default = 3
- */
-/* Bit 0, reg_mcdi_biqsadcorepxlnormen
- * enable bi-qsad core pixels normalization, default = 1
- */
-#define MCDI_TXT_THD ((0x2f08))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_txtminmaxdifthd,
- * min max dif threshold (>=) for texture detection, default = 24
- */
-/* Bit 15: 8, reg_mcdi_txtmeandifthd,
- * mean dif threshold (<) for texture detection, default = 9
- */
-/* Bit 7: 3, reserved */
-/* Bit 2: 0, reg_mcdi_txtdetthd,
- * texture detecting threshold, 0~4, default = 2
- */
-#define MCDI_FLT_MODESEL ((0x2f09))
-/* Bit 31 reserved */
-/* Bit 30:28, reg_mcdi_flthorlineselmode
- * mode for horizontal line detecting flat calculation,default = 1,same as below
- */
-/* Bit 27 reserved */
-/* Bit 26:24, reg_mcdi_fltgmvselmode
- * mode for gmv flat calculation, default = 4, same as below
- */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_mcdi_fltsadselmode
- * mode for sad flat calculation, default = 2, same as below
- */
-/* Bit 19, reserved */
-/* Bit 18:16, reg_mcdi_fltbadwselmode
- * mode for badw flat calculation, default = 3, same as below
- */
-/* Bit 15, reserved */
-/* Bit 14:12, reg_mcdi_fltrptmvselmode
- * mode for repeat mv flat calculation, default = 4, same as below
- */
-/* Bit 11, reserved */
-/* Bit 10: 8, reg_mcdi_fltbadrelselmode
- * mode for bad rel flat calculation, default = 4, same as below
- */
-/* Bit 7, reserved */
-/* Bit 6: 4, reg_mcdi_fltcolcfdselmode
- * mode for col cfd flat calculation, default = 2, same as below
- */
-/* Bit 3, reserved */
-/* Bit 2: 0, reg_mcdi_fltpd22chkselmode
- * mode for pd22 check flat calculation, default = 2, #
- * 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v,
- * 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre)
- */
-#define MCDI_CHK_EDGE_THD ((0x2f0a))
-/* Bit 23:28, reserved. */
-/* Bit 27:24, reg_mcdi_chkedgedifsadthd.
- * thd (<=) for sad dif check, 0~8, default = 1
- */
-/* Bit 23:16, reserved. */
-/* Bit 15:12, reg_mcdi_chkedgemaxedgethd.
- * max drt of edge, default = 15
- */
-/* Bit 11: 8, reg_mcdi_chkedgeminedgethd.
- * min drt of edge, default = 2
- */
-/* Bit 7, reserved. */
-/* Bit 6: 0, reg_mcdi_chkedgevdifthd.
- * thd for vertical dif in check edge, default = 14
- */
-#define MCDI_CHK_EDGE_GAIN_OFFST ((0x2f0b))
-/* Bit 31:24, reserved. */
-/* Bit 23:20, reg_mcdi_chkedgedifthd1.
- * thd1 for edge dif check (<=), default = 4
- */
-/* Bit 19:16, reg_mcdi_chkedgedifthd0.
- * thd0 for edge dif check (>=), default = 15
- */
-/* Bit :15, reserved. */
-/* Bit 14:10, reg_mcdi_chkedgechklen.
- * total check length for edge check, 1~24 (>0), default = 24
- */
-/* Bit 9: 8, reg_mcdi_chkedgeedgesel.
- * final edge select mode, 0: original start edge, 1: lpf start edge,
- * 2: orignal start+end edge, 3: lpf start+end edge, default = 1
- */
-/* Bit 7: 3, reg_mcdi_chkedgesaddstgain.
- * distance gain for sad calc while getting edges, default = 4
- */
-/* Bit 2, reg_mcdi_chkedgechkmode.
- * edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1
- */
-/* Bit 1, reg_mcdi_chkedgestartedge.
- * edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0
- */
-/* Bit 0, reg_mcdi_chkedgeedgelpf.
- * edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0
- */
-#define MCDI_LMV_RT ((0x2f0c))
-/* BIt 31:15, reserved */
-/* Bit 14:12, reg_mcdi_lmvvalidmode
- * valid mode for lmv calc., 100b:use char det, 010b: use flt,001b: use hori flg
- */
-/* Bit 11:10, reg_mcdi_lmvgainmvmode
- * four modes of mv selection for lmv weight calucluation, default = 1
- */
-/* 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1);
- * 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3);
- * 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
- */
-/* Bit 9, reg_mcdi_lmvinitmode
- * initial lmvs at first row of input field, 0: initial value = 0;
- * 1: initial = 32 (invalid), default = 0
- */
-/* Bit 8, reserved */
-/* Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5 */
-/* Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5 */
-#define MCDI_LMV_GAINTHD ((0x2f0d))
-/* Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96 */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_mcdi_lmvdifthd0
- * dif threshold 0 (<) for small lmv, default = 1
- */
-/* Bit 19:17, reg_mcdi_lmvdifthd1
- * dif threshold 1 (<) for median lmv, default = 2
- */
-/* Bit 16:14, reg_mcdi_lmvdifthd2
- * dif threshold 2 (<) for large lmv, default = 3
- */
-/* Bit 13: 8, reg_mcdi_lmvnumlmt
- * least/limit number of (total number - max0), default = 20
- */
-/* Bit 7: 0, reg_mcdi_lmvfltthd
- * flt cnt thd (<) for lmv, default = 9
- */
-#define MCDI_RPTMV_THD0 ((0x2f0e))
-/* Bit 31:25, reg_mcdi_rptmvslpthd2
- * slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64
- */
-/* Bit 24:20, reg_mcdi_rptmvslpthd1
- * slope thd (>=) between i and i+2/i-2, default = 4
- */
-/* Bit 19:10, reg_mcdi_rptmvampthd2
- * amplitude thd (>=) between max and min, when count cycles, default = 300
- */
-/* Bit 9: 0, reg_mcdi_rptmvampthd1
- * amplitude thd (>=) between average of max and min, default = 400
- */
-#define MCDI_RPTMV_THD1 ((0x2f0f))
-/* Bit 31:28, reserved */
-/* Bit 27:25, reg_mcdi_rptmvcyccntthd
- * thd (>=) of total cycles count, default = 2
- */
-/* Bit 24:21, reg_mcdi_rptmvcycdifthd
- * dif thd (<) of cycles length, default = 3
- */
-/* Bit 20:18, reg_mcdi_rptmvcycvldthd
- * thd (>) of valid cycles number, default = 1
- */
-/* Bit 17:15, reg_mcdi_rptmvhalfcycminthd
- * min length thd (>=) of half cycle, default = 2
- */
-/* Bit 14:11, reg_mcdi_rptmvhalfcycdifthd
- * neighboring half cycle length dif thd (<), default = 5
- */
-/* Bit 10: 8, reg_mcdi_rptmvminmaxcntthd
- * least number of valid max and min, default = 2
- */
-/* Bit 7: 5, reg_mcdi_rptmvcycminthd
- * min length thd (>=) of cycles, default = 2
- */
-/* Bit 4: 0, reg_mcdi_rptmvcycmaxthd
- * max length thd (<) of cycles, default = 17
- */
-#define MCDI_RPTMV_THD2 ((0x2f10))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_rptmvhdifthd0
- * higher hdif thd (>=) (vertical edge) for rpt detection, default = 8
- */
-/* Bit 15: 8, reg_mcdi_rptmvhdifthd1
- * hdif thd (>=) (slope edge) for rpt detection, default = 4
- */
-/* Bit 7: 0, reg_mcdi_rptmvvdifthd
- * vdif thd (>=) (slope edge) for rpt detection, default = 1
- */
-#define MCDI_RPTMV_SAD ((0x2f11))
-/* Bit 31:26, reserved */
-/* Bit 25:16, reg_mcdi_rptmvsaddifthdgain
- * 7x3x(16/16), gain for sad dif thd in rpt mv detection,
- * 0~672, normalized 16 as '1', default = 336
- */
-/* Bit 15:10, reserved */
-/* Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst
- * offset for sad dif thd in rpt mv detection, -512~511, default = 16
- */
-#define MCDI_RPTMV_FLG ((0x2f12))
-/* Bit 31:18, reserved */
-/* Bit 17:16, reg_mcdi_rptmvmode
- * select mode of mvs for repeat motion estimation, 0: hmv,
- * 1: qmv/2, 2 or 3: qmv/4, default = 2
- */
-/* Bit 15: 8, reg_mcdi_rptmvflgcntthd
- * thd (>=) of min count number for rptmv of whole field,
- * for rptmv estimation, default = 64
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_rptmvflgcntrt
- * 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32,
- */
-#define MCDI_RPTMV_GAIN ((0x2f13))
-/* Bit 31:24, reg_mcdi_rptmvlftgain
- * up repeat mv gain for hme, default = 96
- */
-/* Bit 23:16, reg_mcdi_rptmvuplftgain
- * up left repeat mv gain for hme, default = 32
- */
-/* Bit 15: 8, reg_mcdi_rptmvupgain
- * up repeat mv gain for hme, default = 64
- */
-/* Bit 7: 0, reg_mcdi_rptmvuprightgain
- * up right repeat mv gain for hme, default = 32
- */
-#define MCDI_GMV_RT ((0x2f14))
-/* Bit 31, reserved */
-/* Bit 30:24, reg_mcdi_gmvmtnrt0
- * ratio 0 for motion senario, set 127 to 128, normalized 128 as '1',default =32
- */
-/* Bit 23, reserved */
-/* Bit 22:16, reg_mcdi_gmvmtnrt1
- * ratio 1 for motion senario, set 127 to 128 normalized 128 as '1',default = 56
- */
-/* Bit 15, reserved */
-/* Bit 14: 8, reg_mcdi_gmvstlrt0
- * ratio 0 for still senario, set 127 to 128,normalized 128 as '1', default = 56
- */
-/* Bit 7, reserved */
-/* Bit 6: 0, reg_mcdi_gmvstlrt1
- * ratio 1 for still senario, set 127 to 128, normalized 128 as '1',default = 80
- */
-#define MCDI_GMV_GAIN ((0x2f15))
-/* Bit 31:25, reg_mcdi_gmvzeromvlockrt0
- * ratio 0 for locking zero mv, set 127 to 128,
- * normalized 128 as '1', default = 100
- */
-/* Bit 24:18, reg_mcdi_gmvzeromvlockrt1
- * ratio 1 for locking zero mv, set 127 to 128,
- * normalized 128 as '1', default = 112
- */
-/* Bit 17:16, reg_mcdi_gmvvalidmode
- * valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3
- */
-/* Bit 15: 8, reg_mcdi_gmvvxgain
- * gmv's vx gain when gmv locked for hme, default = 0
- */
-/* Bit 7: 0, reg_mcdi_gmvfltthd
- * flat thd (<) for gmv calc. default = 3
- */
-#define MCDI_HOR_SADOFST ((0x2f16))
-/* Bit 31:25, reserved */
-/* Bit 24:16, reg_mcdi_horsaddifthdgain
- * 21*1/8, gain/divisor for sad dif threshold in hor line detection,
- * normalized 8 as '1', default = 21
- */
-/* Bit 15: 8, reg_mcdi_horsaddifthdoffst
- * offset for sad dif threshold in hor line detection, -128~127, default = 0
- */
-/* Bit 7: 0, reg_mcdi_horvdifthd
- * threshold (>=) of vertical dif of next block for
- * horizontal line detection, default = 24
- */
-#define MCDI_REF_MV_NUM ((0x2f17))
-/* Bit 31: 2, reserved */
-/* Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in
- * refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0
- */
-#define MCDI_REF_BADW_THD_GAIN ((0x2f18))
-/* Bit 31:28, reserved */
-/* Bit 27:24, reg_mcdi_refbadwcnt2gain.
- * gain for badwv count num==3, default = 6
- */
-/* Bit 23:20, reg_mcdi_refbadwcnt1gain.
- * gain for badwv count num==2, default = 3
- */
-/* Bit 19:16, reg_mcdi_refbadwcnt0gain.
- * gain for badwv count num==1, default = 1
- */
-/* Bit 15:12, reg_mcdi_refbadwthd3.
- * threshold 3 for detect badweave with largest average luma, default = 4
- */
-/* Bit 11: 8, reg_mcdi_refbadwthd2.
- * threshold 2 for detect badweave with third smallest average luma, default = 3
- */
-/* Bit 7: 4, reg_mcdi_refbadwthd1.
- * threshold 1 for detect badweave with second smallest average luma,default = 2
- */
-/* Bit 3: 0, reg_mcdi_refbadwthd0.
- * threshold 0 for detect badweave with smallest average luma, default = 1
- */
-#define MCDI_REF_BADW_SUM_GAIN ((0x2f19))
-/* Bit 31:13, reserved */
-/* Bit 12: 8, reg_mcdi_refbadwsumgain0.
- * sum gain for r channel, 0~16, default = 8
- */
-/* Bit 7: 5, reserved */
-/* Bit 4, reg_mcdi_refbadwcalcmode.
- * mode for badw calculation, 0:sum, 1:max, default = 0
- */
-/* Bit 3: 0, reserved */
-#define MCDI_REF_BS_THD_GAIN ((0x2f1a))
-/* Bit 31:28, reg_mcdi_refbsudgain1.
- * up & down block stregth gain1, normalized to 8 as '1', default = 2
- */
-/* Bit 27:24, reg_mcdi_refbsudgain0.
- * up & down block stregth gain0, normalized to 8 as '1', default = 4
- */
-/* Bit 23:19, reserved */
-/* Bit 18:16, reg_mcdi_refbslftgain.
- * left block strength gain, default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_refbsthd1.
- * threshold 1 for detect block stregth in refinment, default = 16
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_refbsthd0.
- * threshold 0 for detect block stregth in refinment, default = 8
- */
-#define MCDI_REF_ERR_GAIN0 ((0x2f1b))
-/* Bit 31, reserved */
-/* Bit 30:24, reg_mcdi_referrnbrdstgain.
- * neighoring mv distances gain for err calc. in ref,
- * normalized to 8 as '1', default = 48
- */
-/* Bit 23:20, reserved */
-/* Bit 19:16, reg_mcdi_referrbsgain.
- * bs gain for err calc. in ref, normalized to 8 as '1', default = 4
- */
-/* Bit 15, reserved */
-/* Bit 14: 8, reg_mcdi_referrbadwgain.
- * badw gain for err calc. in ref, normalized to 8 as '1', default = 64
- */
-/* Bit 7: 4, reserved */
-/* Bit 3: 0, reg_mcdi_referrsadgain.
- * sad gain for err calc. in ref, normalized to 8 as '1', default = 4
- */
-#define MCDI_REF_ERR_GAIN1 ((0x2f1c))
-/* Bit 31:20, reserved */
-/* Bit 19:16, reg_mcdi_referrchkedgegain.
- * check edge gain for err calc. in ref, normalized to 8 as '1', default = 4
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_mcdi_referrlmvgain.
- * (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0
- */
-/* Bit 7: 4, reserved */
-/* Bit 3: 0, reg_mcdi_referrgmvgain.
- * (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
- */
-#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d))
-/* Bit 31:28, reserved */
-/* Bit 27:24, reg_mcdi_referrfrqgain.
- * gain for mv frquency, normalized to 4 as '1', default = 10
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_referrfrqmax.
- * max gain for mv frquency check, default = 31
- */
-/* Bit 15, reserved */
-/* Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2.
- * mv dif threshold 2 (<) for mv frquency check, default = 3
- */
-/* Bit 11, reserved */
-/* Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1.
- * mv dif threshold 1 (<) for mv frquency check, default = 2
- */
-/* Bit 7, reserved */
-/* Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0.
- * mv dif threshold 0 (<) for mv frquency check, default = 1
- */
-/* Bit 3: 0, reserved */
-#define MCDI_QME_LPF_MSK ((0x2f1e))
-/* Bit 31:28, reserved */
-/* Bit 27:24, reg_mcdi_qmechkedgelpfmsk0.
- * lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0),
- * normalized to 8 as '1', default = 7
- */
-/* Bit 23:20, reserved */
-/* Bit 19:16, reg_mcdi_qmebslpfmsk0.
- * lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0),
- * normalized to 8 as '1', default = 7
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_mcdi_qmebadwlpfmsk0.
- * lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0),
- * normalized to 8 as '1', default = 7
- */
-/* Bit 7: 4, reserved */
-/* Bit 3: 0, reg_mcdi_qmesadlpfmsk0.
- * lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0),
- * normalized to 8 as '1', default = 7
- */
-#define MCDI_REL_DIF_THD_02 ((0x2f1f))
-/* Bit 31:24, reserved. */
-/* Bit 23:16, reg_mcdi_reldifthd2.
- * thd (<) for (hdif+vdif), default = 9
- */
-/* Bit 15: 8, reg_mcdi_reldifthd1.
- * thd (<) for (vdif), default = 5
- */
-/* Bit 7: 0, reg_mcdi_reldifthd0.
- * thd (>=) for (hdif-vdif), default = 48
- */
-#define MCDI_REL_DIF_THD_34 ((0x2f20))
-/* Bit 31:16, reserved. */
-/* Bit 15: 8, reg_mcdi_reldifthd4.
- * thd (<) for (hdif), default = 255
- */
-/* Bit 7: 0, reg_mcdi_reldifthd3.
- * thd (>=) for (vdif-hdif), default = 48
- */
-#define MCDI_REL_BADW_GAIN_OFFST_01 ((0x2f21))
-/* Bit 31:24, reg_mcdi_relbadwoffst1.
- * offset for badw adj, for flat block, -128~127, default = 0
- */
-/* Bit 23:16, reg_mcdi_relbadwgain1.
- * gain for badw adj, for flat block, default = 128
- */
-/* Bit 15: 8, reg_mcdi_relbadwoffst0.
- * offset for badw adj, for vertical block, -128~127, default = 0
- */
-/* Bit 7: 0, reg_mcdi_relbadwgain0.
- * gain for badw adj, for vertical block, default = 160
- */
-#define MCDI_REL_BADW_GAIN_OFFST_23 ((0x2f22))
-/* Bit 31:24, reg_mcdi_relbadwoffst3.
- * offset for badw adj, for other block, -128~127, default = 0
- */
-/* Bit 23:16, reg_mcdi_relbadwgain3.
- * gain for badw adj, for other block, default = 48
- */
-/* Bit 15: 8, reg_mcdi_relbadwoffst2.
- * offset for badw adj, for horizontal block, -128~127, default = 0
- */
-/* Bit 7: 0, reg_mcdi_relbadwgain2.
- * gain for badw adj, for horizontal block, default = 48
- */
-#define MCDI_REL_BADW_THD_GAIN_OFFST ((0x2f23))
-/* Bit 31:23, reserved. */
-/* Bit 22:16, reg_mcdi_relbadwoffst.
- * offset for badw thd adj, -64~63, default = 0
- */
-/* Bit 15: 8, reserved. */
-/* Bit 7: 0, reg_mcdi_relbadwthdgain.
- * gain0 for badw thd adj, normalized to 16 as '1', default = 16
- */
-#define MCDI_REL_BADW_THD_MIN_MAX ((0x2f24))
-/* Bit 31:18, reserved. */
-/* Bit 17: 8, reg_mcdi_relbadwthdmax.
- * max for badw thd adj, default = 256
- */
-/* Bit 7: 0, reg_mcdi_relbadwthdmin.
- * min for badw thd adj, default = 16
- */
-#define MCDI_REL_SAD_GAIN_OFFST_01 ((0x2f25))
-/* Bit 31:24, reg_mcdi_relsadoffst1.
- * offset for sad adj, for flat block, -128~127, default = 0
- */
-/* Bit 23:20, reserved. */
-/* Bit 19:16, reg_mcdi_relsadgain1.
- * gain for sad adj, for flat block, normalized to 8 as '1', default = 8
- */
-/* Bit 15: 8, reg_mcdi_relsadoffst0.
- * offset for sad adj, for vertical block, -128~127, default = 0
- */
-/* Bit 7: 4, reserved. */
-/* Bit 3: 0, reg_mcdi_relsadgain0.
- * gain for sad adj, for vertical block, normalized to 8 as '1', default = 6
- */
-#define MCDI_REL_SAD_GAIN_OFFST_23 ((0x2f26))
-/* Bit 31:24, reg_mcdi_relsadoffst3.
- * offset for sad adj, for other block, -128~127, default = 0
- */
-/* Bit 23:20, reserved. */
-/* Bit 19:16, reg_mcdi_relsadgain3.
- * gain for sad adj, for other block, normalized to 8 as '1', default = 8
- */
-/* Bit 15: 8, reg_mcdi_relsadoffst2.
- * offset for sad adj, for horizontal block, -128~127, default = 0
- */
-/* Bit 7: 4, reserved. */
-/* Bit 3: 0, reg_mcdi_relsadgain2.
- * gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12
- */
-#define MCDI_REL_SAD_THD_GAIN_OFFST ((0x2f27))
-/* Bit 31:24, reserved. */
-/* Bit 23:16, reg_mcdi_relsadoffst.
- * offset for sad thd adj, -128~127, default = 0
- */
-/* Bit 15:10, reserved. */
-/* Bit 9: 0, reg_mcdi_relsadthdgain.
- * gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42
- */
-#define MCDI_REL_SAD_THD_MIN_MAX ((0x2f28))
-/* Bit 31:27, reserved. */
-/* Bit 26:16, reg_mcdi_relsadthdmax.
- * max for sad thd adj, 21*32, default = 672
- */
-/* Bit 15: 9, reserved. */
-/* Bit 8: 0, reg_mcdi_relsadthdmin.
- * min for sad thd adj, 21*2, default = 42
- */
-#define MCDI_REL_DET_GAIN_00 ((0x2f29))
-/* Bit 31:21, reserved. */
-/* Bit 20:16, reg_mcdi_reldetbsgain0.
- * gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1',
- * default = 8
- */
-/* Bit 15:14, reserved. */
-/* Bit 13: 8, reg_mcdi_reldetbadwgain0.
- * gain0 (gmv locked) for badw, for det. calc.
- * normalized to 16 as '1', default = 12
- */
-/* Bit 7: 5, reserved. */
-/* Bit 4: 0, reg_mcdi_reldetsadgain0.
- * gain0 (gmv locked) for qsad, for det. calc.
- * normalized to 16 as '1', default = 8
- */
-#define MCDI_REL_DET_GAIN_01 ((0x2f2a))
-/* Bit 31:14, reserved. */
-/* Bit 12: 8, reg_mcdi_reldetchkedgegain0.
- * gain0 (gmv locked) for chk_edge, for det. calc.
- * normalized to 16 as '1', default = 2
- */
-/* Bit 7, reserved. */
-/* Bit 6: 0, reg_mcdi_reldetnbrdstgain0.
- * gain0 (gmv locked) for neighoring dist, for det.
- * calc. normalized to 16 as '1', default = 24
- */
-#define MCDI_REL_DET_GAIN_10 ((0x2f2b))
-/* Bit 31:21, reserved. */
-/* Bit 20:16, reg_mcdi_reldetbsgain1.
- * gain1 (lmv locked) for bs, for det. calc. normalized
- * to 16 as '1', default = 0
- */
-/* Bit 15:14, reserved. */
-/* Bit 13: 8, reg_mcdi_reldetbadwgain1.
- * gain1 (lmv locked) for badw, for det. calc.
- * normalized to 16 as '1', default = 8
- */
-/* Bit 7: 5, reserved. */
-/* Bit 4: 0, reg_mcdi_reldetsadgain1.
- * gain1 (lmv locked) for qsad, for det. calc.
- * normalized to 16 as '1', default = 8
- */
-#define MCDI_REL_DET_GAIN_11 ((0x2f2c))
-/* Bit 31:14, reserved. */
-/* Bit 12: 8, reg_mcdi_reldetchkedgegain1.
- * gain1 (lmv locked) for chk_edge, for det. calc.
- * normalized to 16 as '1', default = 0
- */
-/* Bit 7, reserved. */
-/* Bit 6: 0, reg_mcdi_reldetnbrdstgain1.
- * gain1 (lmv locked) for neighoring dist, for det.
- * calc. normalized to 16 as '1', default = 24
- */
-#define MCDI_REL_DET_GAIN_20 ((0x2f2d))
-/* Bit 31:21, reserved. */
-/* Bit 20:16, reg_mcdi_reldetbsgain2.
- * gain2 (no locked) for bs, for det. calc.normalized to 16 as '1', default = 12
- */
-/* Bit 15:14, reserved. */
-/* Bit 13: 8, reg_mcdi_reldetbadwgain2.
- * gain2 (no locked) for badw, for det. calc.
- * normalized to 16 as '1',default = 32
- */
-/* Bit 7: 5, reserved. */
-/* Bit 4: 0, reg_mcdi_reldetsadgain2.
- * gain2 (no locked) for qsad, for det. calc.
- * normalized to 16 as '1', default = 16
- */
-#define MCDI_REL_DET_GAIN_21 ((0x2f2e))
-/* Bit 31:26, reserved */
-/* Bit 25:16, reg_mcdi_reldetoffst.
- * offset for rel calculation, for det. calc. -512~511, default = 0
- */
-/* Bit 15:14, reserved. */
-/* Bit 12: 8, reg_mcdi_reldetchkedgegain2.
- * gain2 (no locked) for chk_edge, for det. calc.
- * normalized to 16 as '1', default = 10
- */
-/* Bit 7, reserved. */
-/* Bit 6: 0, reg_mcdi_reldetnbrdstgain2.
- * gain2 (no locked) for neighoring dist, for det. calc.
- * normalized to 16 as '1', default = 32
- */
-#define MCDI_REL_DET_GMV_DIF_CHK ((0x2f2f))
-/* Bit 31:24, reserved. */
-/* Bit 23:16, reg_mcdi_reldetgmvfltthd.
- * flat thd (>=) for gmv lock decision, default = 0
- */
-/* Bit 15, reserved. */
-/* Bit 14:12, reg_mcdi_reldetgmvdifthd.
- * dif thd (>=) for current mv different from gmv for gmv dif check,
- * actually used in Lmv lock check, default = 3
- */
-/* Bit 11, reserved. */
-/* Bit 10: 8, reg_mcdi_reldetgmvdifmin.
- * min mv dif for gmv dif check, default = 1, note: dif between
- * reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min
- * should be; 0,1,3,7, not work for others
- */
-/* Bit 7: 4, reg_mcdi_reldetgmvdifmax.
- * max mv dif for gmv dif check, default = 4
- */
-/* Bit 3: 1, reserved */
-/* Bit 0, reg_mcdi_reldetgmvdifmvmode.
- * mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0
- */
-#define MCDI_REL_DET_LMV_DIF_CHK ((0x2f30))
-/* Bit 31:24, reserved. */
-/* Bit 23:16, reg_mcdi_reldetlmvfltthd.
- * flat thd (>=) for lmv lock decision, default = 12
- */
-/* Bit 15:14, reserved. */
-/* Bit 13:12, reg_mcdi_reldetlmvlockchkmode.
- * lmv lock check mode, 0:cur Lmv, 1: cur & (last | next),
- * 2: last & cur & next Lmv, default = 1
- */
-/* Bit 11, reserved. */
-/* Bit 10: 8, reg_mcdi_reldetlmvdifmin.
- * min mv dif for lmv dif check, default = 1, note: dif between
- * reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be;
- * 0,1,3,7, not work for others
- */
-/* Bit 7: 4, reg_mcdi_reldetlmvdifmax.
- * max mv dif for lmv dif check, default = 4
- */
-/* Bit 3: 1, reserved */
-/* Bit 0, reg_mcdi_reldetlmvdifmvmode.
- * mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0
- */
-#define MCDI_REL_DET_FRQ_CHK ((0x2f31))
-/* Bit 31:12, reserved. */
-/* Bit 11: 8, reg_mcdi_reldetfrqgain.
- * gain for frequency check, normalized to 4 as '1', default = 10
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetfrqmax.
- * max value for frequency check, default = 31
- */
-#define MCDI_REL_DET_PD22_CHK ((0x2f32))
-/* Bit 31:18, reserved. */
-/* Bit 17: 8, reg_mcdi_reldetpd22chkoffst.
- * offset for pd22 check happened, default = 512
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetpd22chkgain.
- * gain for pd22 check happened, normalized to 8 as '1', default = 12
- */
-#define MCDI_REL_DET_RPT_CHK_ROW ((0x2f33))
-/* Bit 31:27, reserved */
-/* Bit 26:16, reg_mcdi_reldetrptchkendrow.
- * end row (<) number for repeat check, default = 2047
- */
-/* Bit 15:11, reserved */
-/* Bit 10: 0, reg_mcdi_reldetrptchkstartrow.
- * start row (>=) number for repeat check, default = 0
- */
-#define MCDI_REL_DET_RPT_CHK_GAIN_QMV ((0x2f34))
-/* Bit 31:30, reserved */
-/* Bit 29:24, reg_mcdi_reldetrptchkqmvmax.
- * max thd (<) of abs qmv for repeat check, default = 15,
- * note that quarter mv's range is -63~63
- */
-/* Bit 23:22, reserved */
-/* Bit 21:16, reg_mcdi_reldetrptchkqmvmin.
- * min thd (>=) of abs qmv for repeat check, default = 10,
- * note that quarter mv's range is -63~63
- */
-/* Bit 15, reserved/ */
-/* Bit 14: 4, reg_mcdi_reldetrptchkoffst.
- * offset for repeat check, default = 512
- */
-/* Bit 3: 0, reg_mcdi_reldetrptchkgain.
- * gain for repeat check, normalized to 8 as '1', default = 4
- */
-#define MCDI_REL_DET_RPT_CHK_THD_0 ((0x2f35))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_reldetrptchkzerosadthd.
- * zero sad thd (<) for repeat check, default = 255
- */
-/* Bit 15:14, reserved. */
-/* Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd.
- * zero badw thd (>=) for repeat check, default = 16
- */
-/* Bit 7: 4, reserved */
-/* Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd.
- * frequency dif thd (<) for repeat check, 0~10, default = 5
- */
-#define MCDI_REL_DET_RPT_CHK_THD_1 ((0x2f36))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_mcdi_reldetrptchkvdifthd.
- * vertical dif thd (<) for repeat check, default = 16
- */
-/* Bit 7: 0, reg_mcdi_reldetrptchkhdifthd.
- * horizontal dif thd (>=) for repeat check, default = 16
- */
-#define MCDI_REL_DET_LPF_DIF_THD ((0x2f37))
-/* Bit 31:24, reg_mcdi_reldetlpfdifthd3.
- * hdif thd (<) for lpf selection of horizontal block, default = 9
- */
-/* Bit 23:16, reg_mcdi_reldetlpfdifthd2.
- * vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48
- */
-/* Bit 15: 8, reg_mcdi_reldetlpfdifthd1.
- * vdif thd (<) for lpf selection of vertical block, default = 9
- */
-/* Bit 7: 0, reg_mcdi_reldetlpfdifthd0.
- * hdif-vdif thd (>=) for lpf selection of vertical block, default = 48
- */
-#define MCDI_REL_DET_LPF_MSK_00_03 ((0x2f38))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_reldetlpfmsk03.
- * det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_reldetlpfmsk02.
- * det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_reldetlpfmsk01.
- * det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetlpfmsk00.
- * det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8
- */
-#define MCDI_REL_DET_LPF_MSK_04_12 ((0x2f39))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_reldetlpfmsk12.
- * det lpf mask12 for vertical blocks, 0~16, default = 0
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_reldetlpfmsk11.
- * det lpf mask11 for vertical blocks, 0~16, default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_reldetlpfmsk10.
- * det lpf mask10 for vertical blocks, 0~16, default = 16
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetlpfmsk04.
- * det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1
- */
-#define MCDI_REL_DET_LPF_MSK_13_21 ((0x2f3a))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_reldetlpfmsk21.
- * det lpf mask21 for horizontal blocks, 0~16, default = 6
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_reldetlpfmsk20.
- * det lpf mask20 for horizontal blocks, 0~16, default = 8
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_reldetlpfmsk14.
- * det lpf mask14 for vertical blocks, 0~16, default = 0
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetlpfmsk13.
- * det lpf mask13 for vertical blocks, 0~16, default = 0
- */
-#define MCDI_REL_DET_LPF_MSK_22_30 ((0x2f3b))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_reldetlpfmsk30.
- * det lpf mask30 for other blocks, 0~16, default = 16
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_reldetlpfmsk24.
- * det lpf mask24 for horizontal blocks, 0~16, default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_reldetlpfmsk23.
- * det lpf mask23 for horizontal blocks, 0~16, default = 0
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetlpfmsk22.
- * det lpf mask22 for horizontal blocks, 0~16, default = 1
- */
-#define MCDI_REL_DET_LPF_MSK_31_34 ((0x2f3c))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_reldetlpfmsk34.
- * det lpf mask34 for other blocks, 0~16, default = 0
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_reldetlpfmsk33.
- * det lpf mask33 for other blocks, 0~16, default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_reldetlpfmsk32.
- * det lpf mask32 for other blocks, 0~16, default = 0
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_reldetlpfmsk31.
- * det lpf mask31 for other blocks, 0~16, default = 0
- */
-/* Note: there are four group lpf masks from addr 37~3b,
- * each group sum equal to 16.
- */
-#define MCDI_REL_DET_MIN ((0x2f3d))
-/* Bit 31: 7, reserved */
-/* Bit 6: 0, reg_mcdi_reldetmin.
- * min of detected value, default = 16
- */
-#define MCDI_REL_DET_LUT_0_3 ((0x2f3e))
-/* Bit 31:24, reg_mcdi_reldetmaplut3. default = 8 */
-/* Bit 23:16, reg_mcdi_reldetmaplut2. default = 4 */
-/* Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2 */
-/* Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0 */
-#define MCDI_REL_DET_LUT_4_7 ((0x2f3f))
-/* Bit 31:24, reg_mcdi_reldetmaplut7. default = 64 */
-/* Bit 23:16, reg_mcdi_reldetmaplut6. default = 48 */
-/* Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32 */
-/* Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16 */
-#define MCDI_REL_DET_LUT_8_11 ((0x2f40))
-/* Bit 31:24, reg_mcdi_reldetmaplut11. default = 160 */
-/* Bit 23:16, reg_mcdi_reldetmaplut10. default = 128 */
-/* Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96 */
-/* Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80 */
-#define MCDI_REL_DET_LUT_12_15 ((0x2f41))
-/* Bit 31:24, reg_mcdi_reldetmaplut15. default = 255 */
-/* Bit 23:16, reg_mcdi_reldetmaplut14. default = 240 */
-/* Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224 */
-/* Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192 */
-#define MCDI_REL_DET_COL_CFD_THD ((0x2f42))
-/* Bit 31:24, reg_mcdi_reldetcolcfdfltthd.
- * thd for flat smaller than (<) of column cofidence, default = 5
- */
-/* Bit 23:16, reg_mcdi_reldetcolcfdthd1.
- * thd for rel larger than (>=) in rel calc.
- * mode col confidence without gmv locking, default = 160
- */
-/* Bit 15: 8, reg_mcdi_reldetcolcfdthd0.
- * thd for rel larger than (>=) in rel calc.
- * mode col confidence when gmv locked, default = 100
- */
-/* Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd.
- * thd for badw larger than (>=) in qbadw calc.
- * mode of column cofidence, default = 16
- */
-/* Bit 1, reserved */
-/* Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc.
- * mode for column cofidence, 0: use rel, 1: use qbadw, default = 0
- */
-#define MCDI_REL_DET_COL_CFD_AVG_LUMA ((0x2f43))
-/* Bit 31:24, reg_mcdi_reldetcolcfdavgmin1.
- * avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235
- */
-/* Bit 23:16, reg_mcdi_reldetcolcfdavgmax1.
- * avg luma max1 (<) for column cofidence, valid between 16~235, default = 235
- */
-/* Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0.
- * avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16
- */
-/* Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0.
- * avg luma max0 (<) for column cofidence, valid between 16~235, default = 21
- */
-#define MCDI_REL_DET_BAD_THD_0 ((0x2f44))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_mcdi_reldetbadsadthd.
- * thd (>=) for bad sad, default = 120 (480/4)
- */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_mcdi_reldetbadbadwthd.
- * thd (>=) for bad badw, 0~42, default = 12
- */
-#define MCDI_REL_DET_BAD_THD_1 ((0x2f45))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_reldetbadrelfltthd.
- * thd (>=) of flat for bad rel detection, default = 4
- */
-/* Bit 15: 8, reg_mcdi_reldetbadrelthd1.
- * thd (>=) for bad rel without gmv/lmv locked, default = 160
- */
-/* Bit 7: 0, reg_mcdi_reldetbadrelthd0.
- * thd (>=) for bad rel with gmv/lmv locked, default = 120
- */
-#define MCDI_PD22_CHK_THD ((0x2f46))
-/* Bit 31:25, reserved */
-/* Bit 24:16, reg_mcdi_pd22chksaddifthd.
- * sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64
- */
-/* Bit 15:14, reserved */
-/* Bit 13: 8, reg_mcdi_pd22chkqmvthd.
- * thd (>=) of abs qmv for pd22 check, default = 2
- */
-/* Bit 7: 0, reg_mcdi_pd22chkfltthd.
- * thd (>=) of flat for pd22 check, default = 4
- */
-#define MCDI_PD22_CHK_GAIN_OFFST_0 ((0x2f47))
-/* Bit 31:24, reg_mcdi_pd22chkedgeoffst0.
- * offset0 of pd22chkedge from right film22 phase, -128~127, default = 0
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_pd22chkedgegain0.
- * gain0 of pd22chkedge from right film22 phase,
- * normalized to 16 as '1', default = 16
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_mcdi_pd22chkbadwoffst0.
- * offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_pd22chkbadwgain0.
- * gain0 of pd22chkbadw from right film22 phase,
- * normalized to 16 as '1', default = 8
- */
-#define MCDI_PD22_CHK_GAIN_OFFST_1 ((0x2f48))
-/* Bit 31:24, reg_mcdi_pd22chkedgeoffst1.
- * offset1 of pd22chkedge from right film22 phase, -128~127, default = 0
- */
-/* Bit 23:21, reserved */
-/* Bit 20:16, reg_mcdi_pd22chkedgegain1.
- * gain1 of pd22chkedge from right film22 phase,
- * normalized to 16 as '1', default = 16
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_mcdi_pd22chkbadwoffst1.
- * offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_pd22chkbadwgain1.
- * gain1 of pd22chkbadw from right film22 phase,
- * normalized to 16 as '1', default = 12
- */
-#define MCDI_LMV_LOCK_CNT_THD_GAIN ((0x2f49))
-/* Bit 31:20, reserved */
-/* Bit 19:16, reg_mcdi_lmvlockcntmax.
- * max lmv lock count number, default = 6
- */
-/* Bit 15:12, reg_mcdi_lmvlockcntoffst.
- * offset for lmv lock count, -8~7, default = 0
- */
-/* Bit 11: 8, reg_mcdi_lmvlockcntgain.
- * gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_lmvlockcntthd.
- * lmv count thd (>=) before be locked, 1~31, default = 4
- */
-#define MCDI_LMV_LOCK_ABS_DIF_THD ((0x2f4a))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_mcdi_lmvlockdifthd2.
- * lmv dif thd for third part, before locked, default = 1
- */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_mcdi_lmvlockdifthd1.
- * lmv dif thd for second part, before locked, default = 1
- */
-/* Bit 19, reserved */
-/* Bit 18:16, reg_mcdi_lmvlockdifthd0.
- * lmv dif thd for first part, before locked, default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_lmvlockabsmax.
- * max abs (<) of lmv to be locked, default = 24
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_lmvlockabsmin.
- * min abs (>=) of lmv to be locked, default = 1
- */
-#define MCDI_LMV_LOCK_ROW ((0x2f4b))
-/* Bit 31:27, reserved */
-/* Bit 26:16, reg_mcdi_lmvlockendrow.
- * end row (<) for lmv lock, default = 2047
- */
-/* Bit 15:11, reserved */
-/* Bit 10: 0, reg_mcdi_lmvlockstartrow.
- * start row (>=) for lmv lock, default = 0
- */
-#define MCDI_LMV_LOCK_RT_MODE ((0x2f4c))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_mcdi_lmvlockextmode.
- * extend lines for lmv lock check, check how many lines
- * for lmv locking, default = 2
- */
-/* Bit 23:16, reg_mcdi_lmvlockfltcntrt.
- * ratio of flt cnt for lock check, normalized 256 as '1',
- * 255 is set to 256, default = 32
- */
-/* Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1.
- * ratio when use non-zero lmv for lock check,
- * normalized 256 as '1', 255 is set to 256, default = 48
- */
-/* Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0.
- * ratio when use max lmv for lock check, normalized 256 as '1',
-255 is set to 256, default = 106
-*/
-#define MCDI_GMV_LOCK_CNT_THD_GAIN ((0x2f4d))
-/* Bit 31:20, reserved */
-/* Bit 19:16, reg_mcdi_gmvlockcntmax.
- * max gmv lock count number, default = 6
- */
-/* Bit 15:12, reg_mcdi_gmvlockcntoffst.
- * offset for gmv lock count, -8~7, default = 0
- */
-/* Bit 11: 8, reg_mcdi_gmvlockcntgain.
- * gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_gmvlockcntthd.
- * gmv count thd (>=) before be locked, 1~31, default = 4
- */
-#define MCDI_GMV_LOCK_ABS_DIF_THD ((0x2f4e))
-/* Bit 31:27, reserved */
-/* Bit 26:24, reg_mcdi_gmvlockdifthd2.
- * gmv dif thd for third part, before locked, default = 3
- */
-/* Bit 23, reserved */
-/* Bit 22:20, reg_mcdi_gmvlockdifthd1.
- * gmv dif thd for second part, before locked, default = 2
- */
-/* Bit 19, reserved */
-/* Bit 18:16, reg_mcdi_gmvlockdifthd0.
- * gmv dif thd for first part, before locked, default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_gmvlockabsmax.
- * max abs of gmv to be locked, default = 15
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_gmvlockabsmin.
- * min abs of gmv to be locked, default = 1
- */
-#define MCDI_HIGH_VERT_FRQ_DIF_THD ((0x2f4f))
-/* Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd.
- * high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height,
- * set by software, default = 103680
- */
-#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD ((0x2f50))
-/* Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd.
- * high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height,
- * set by software, default = 103680
- */
-#define MCDI_HIGH_VERT_FRQ_RT_GAIN ((0x2f51))
-/* Bit 31:20, reserved */
-/* Bit 19:16, reg_mcdi_highvertfrqcntthd.
- * high_vert_frq count thd (>=) before locked, 1~31, default = 4
- */
-/* Bit 15: 8, reg_mcdi_highvertfrqbadsadrt.
- * ratio for high_vert_frq bad sad count, normalized 256 as '1',
- * 255 is set to 256, default = 24
- */
-/* Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt.
- * ratio for high_vert_frq badw count, normalized 256 as '1',
- * 255 is set to 256, default = 130
- */
-#define MCDI_MOTION_PARADOX_THD ((0x2f52))
-/* Bit 31:29, reserved */
-/* Bit 28:24, reg_mcdi_motionparadoxcntthd.
- * motion paradox count thd (>=) before locked, 1~31, default = 4
- */
-/* Bit 23:22, reserved */
-/* Bit 21:16, reg_mcdi_motionparadoxgmvthd.
- * abs gmv thd (<) of motion paradox, 0~32, note that 32
- * means invalid gmv, be careful, default = 32
- */
-/* Bit 15: 0, reserved */
-#define MCDI_MOTION_PARADOX_RT ((0x2f53))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_motionparadoxbadsadrt.
- * ratio for field bad sad count of motion paradox,
- * normalized 256 as '1', 255 is set to 256, default = 24
- */
-/* Bit 15: 8, reg_mcdi_motionparadoxbadrelrt.
- * ratio for field bad reliabilty count of motion paradox,
- * normalized 256 as '1', 255 is set to 256, default = 120
- */
-/* Bit 7: 0, reg_mcdi_motionparadoxmtnrt.
- * ratio for field motion count of motion paradox,
- * normalized 256 as '1', 255 is set to 256, default = 218
- */
-#define MCDI_MOTION_REF_THD ((0x2f54))
-/* Bit 31:24, reserved */
-/* Bit 23:20, reg_mcdi_motionrefoffst.
- * motion ref additive offset, default = 15
- */
-/* Bit 19:16, reg_mcdi_motionrefgain.
- * motion ref gain, normalized 8 as '1', default = 8
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_motionrefrptmvthd.
- * abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1
- */
-/* Bit 7: 2, reg_mcdi_motionrefqmvthd.
- * min thd (>=) of abs qmv for motion ref,
- * note that quarter mv's range is -63~63, default = 2
- */
-/* Bit 1: 0, reg_mcdi_motionreflpfmode.
- * Mv and (8 x repeat flg) 's lpf mode of motion refinement,
- * 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1
- */
-#define MCDI_REL_COL_REF_RT ((0x2f55))
-/* Bit 31: 8, reserved */
-/* Bit 7: 0, reg_mcdi_relcolrefrt.
- * ratio for column cofidence level against column number,
- * for refinement, default = 135
- */
-#define MCDI_PD22_CHK_THD_RT ((0x2f56))
-/* Bit 31:27, reserved */
-/* Bit 26:16, reg_mcdi_pd22chkfltcntrt.
- * ratio for flat count of field pulldown 22 check, normalized 2048 as '1',
- * 2047 is set to 2048, default = 1
- */
-/* Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count,
- * normalized 256 as '1', 255 is set to 256, default = 100
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_pd22chkcntthd.
- * thd (>=) for pd22 count before locked, 1~31, default = 4
- */
-#define MCDI_CHAR_DET_DIF_THD ((0x2f57))
-/* Bit 31:24, reserved */
-/* Bit 23:16, reg_mcdi_chardetminmaxdifthd.
- * thd (>=) for dif between min and max value, default = 64
- */
-/* Bit 15: 8, reg_mcdi_chardetmaxdifthd.
- * thd (<) for dif between max value, default = 17
- */
-/* Bit 7: 0, reg_mcdi_chardetmindifthd.
- * thd (<) for dif between min value, default = 17
- */
-#define MCDI_CHAR_DET_CNT_THD ((0x2f58))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_chardettotcntthd.
- * thd (>=) for total count, 0~21, default = 18
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_chardetmaxcntthd.
- * thd (>=) for max count, 0~21, default = 1
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_chardetmincntthd.
- * thd (>=) for min count, 0~21, default = 1
- */
-#define MCDI_FIELD_MV ((0x2f60))
-/* Bit 31:24, reg_mcdi_pd22chkcnt */
-/* Bit 23:16, reg_mcdi_fieldgmvcnt */
-/* Bit 15, reg_mcdi_pd22chkflg */
-/* Bit 14, reg_mcdi_fieldgmvlock */
-/* Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv */
-/* Bit 7: 6, reserved */
-/* Bit 5: 0, reg_mcdi_fieldgmv. last field gmv */
-#define MCDI_FIELD_HVF_PRDX_CNT ((0x2f61))
-/* Bit 31:24, reg_mcdi_motionparadoxcnt. */
-/* Bit 23:17, reserved */
-/* Bit 16, reg_mcdi_motionparadoxflg. */
-/* Bit 15: 8, reg_mcdi_highvertfrqcnt. */
-/* Bit 7: 4, reserved */
-/* Bit 3: 2, reg_mcdi_highvertfrqphase. */
-/* Bit 1, reserved */
-/* Bit 0, reg_mcdi_highvertfrqflg. */
-#define MCDI_FIELD_LUMA_AVG_SUM_0 ((0x2f62))
-/* Bit 31: 0, reg_mcdi_fld_luma_avg_sum0. */
-#define MCDI_FIELD_LUMA_AVG_SUM_1 ((0x2f63))
-/* Bit 31: 0, reg_mcdi_fld_luma_avg_sum1. */
-#define MCDI_YCBCR_BLEND_CRTL ((0x2f64))
-/* Bit 31:16, reserved */
-/* Bit 15: 8, reg_mcdi_ycbcrblendgain.
- * ycbcr blending gain for cbcr in ycbcr. default = 0
- */
-/* Bit 7: 2, reserved. */
-/* Bit 1: 0, reg_mcdi_ycbcrblendmode.
- * 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2
- */
-#define MCDI_MCVECWR_CANVAS_SIZE ((0x2f65))
-#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66))
-#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67))
-#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68))
-#define MCDI_LMVLCKSTEXT_0 ((0x2f69))
-#define MCDI_LMVLCKSTEXT_1 ((0x2f6a))
-#define MCDI_LMVLCKEDEXT_0 ((0x2f6b))
-#define MCDI_LMVLCKEDEXT_1 ((0x2f6c))
-#define MCDI_MCVECWR_X ((0x2f92))
-#define MCDI_MCVECWR_Y ((0x2f93))
-#define MCDI_MCVECWR_CTRL ((0x2f94))
-#define MCDI_MCVECRD_X ((0x2f95))
-#define MCDI_MCVECRD_Y ((0x2f96))
-#define MCDI_MCVECRD_CTRL ((0x2f97))
-#define MCDI_MCINFOWR_X ((0x2f98))
-#define MCDI_MCINFOWR_Y ((0x2f99))
-#define MCDI_MCINFOWR_CTRL ((0x2f9a))
-#define MCDI_MCINFORD_X ((0x2f9b))
-#define MCDI_MCINFORD_Y ((0x2f9c))
-#define MCDI_MCINFORD_CTRL ((0x2f9d))
-/* === MC registers ============================================ */
-#define MCDI_MC_CRTL ((0x2f70))
-/* Bit 31: 9, reserved */
-/* Bit 8, reg_mcdi_mcpreflg.
- * flag to use previous field for MC, 0:forward field,
- * 1: previous field, default = 1
- */
-/* Bit 7, reg_mcdi_mcrelrefbycolcfden.
- * enable rel refinement by column cofidence in mc blending, default = 1
- */
-/* Bit 6: 5, reg_mcdi_mclpfen.
- * enable mc pixles/rel lpf, 0:disable, 1: lpf rel,
- * 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0
- */
-/* Bit 4: 2, reg_mcdi_mcdebugmode.
- * enable mc debug mode, 0:disable, 1: split left/right,
- * 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0
- */
-/* Bit 1: 0, reg_mcdi_mcen.
- * mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1
- */
-#define MCDI_MC_LPF_MSK_0 ((0x2f71))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_mclpfmsk02.
- * mc lpf coef. 2 for pixel 0 of current block,normalized 16 as '1', default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_mclpfmsk01.
- * mc lpf coef. 1 for pixel 0 of current block,normalized 16 as '1', default = 9
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_mclpfmsk00.
- * mc lpf coef. 0 for pixel 0 of current block,normalized 16 as '1', default = 7
- */
-#define MCDI_MC_LPF_MSK_1 ((0x2f72))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_mclpfmsk12.
- * mc lpf coef. 2 for pixel 1 of current block,
- * 0~16, normalized 16 as '1', default = 0
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_mclpfmsk11.
- * mc lpf coef. 1 for pixel 1 of current block, 0~16,
- * normalized 16 as '1', default = 11
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_mclpfmsk10.
- * mc lpf coef. 0 for pixel 1 of current block, 0~16,
- * normalized 16 as '1', default = 5
- */
-#define MCDI_MC_LPF_MSK_2 ((0x2f73))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_mclpfmsk22.
- * mc lpf coef. 2 for pixel 2 of current block, 0~16,
- * normalized 16 as '1', default = 1
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_mclpfmsk21.
- * mc lpf coef. 1 for pixel 2 of current block, 0~16,
- * normalized 16 as '1', default = 14
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_mclpfmsk20.
- * mc lpf coef. 0 for pixel 2 of current block, 0~16,
- * normalized 16 as '1', default = 1
- */
-#define MCDI_MC_LPF_MSK_3 ((0x2f74))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_mclpfmsk32.
- * mc lpf coef. 2 for pixel 3 of current block, 0~16,
- * normalized 16 as '1', default = 5
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_mclpfmsk31.
- * mc lpf coef. 1 for pixel 3 of current block, 0~16,
- * normalized 16 as '1', default = 11
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_mclpfmsk30.
- * mc lpf coef. 0 for pixel 3 of current block, 0~16,
- * normalized 16 as '1', default = 0
- */
-#define MCDI_MC_LPF_MSK_4 ((0x2f75))
-/* Bit 31:21, reserved */
-/* Bit 20:16, reg_mcdi_mclpfmsk42.
- * mc lpf coef. 2 for pixel 4 of current block, 0~16,
- * normalized 16 as '1', default = 7
- */
-/* Bit 15:13, reserved */
-/* Bit 12: 8, reg_mcdi_mclpfmsk41.
- * mc lpf coef. 1 for pixel 4 of current block, 0~16,
- * normalized 16 as '1', default = 9
- */
-/* Bit 7: 5, reserved */
-/* Bit 4: 0, reg_mcdi_mclpfmsk40.
- * mc lpf coef. 0 for pixel 4 of current block, 0~16,
- * normalized 16 as '1', default = 0
- */
-#define MCDI_MC_REL_GAIN_OFFST_0 ((0x2f76))
-/* Bit 31:26, reserved */
-/* Bit 25, reg_mcdi_mcmotionparadoxflg.
- * flag of motion paradox, initial with 0 and read from software, default = 0
- */
-/* Bit 24, reg_mcdi_mchighvertfrqflg.
- * flag of high vert frq, initial with 0 and read from software, default = 0
- */
-/* Bit 23:16, reg_mcdi_mcmotionparadoxoffst.
- * offset (rel + offset) for rel (MC blending coef.)
- * refinement if motion paradox
- * detected before MC blending before MC blending, default = 128
- */
-/* Bit 15:12, reserved */
-/* Bit 11: 8, reg_mcdi_mcmotionparadoxgain.
- * gain for rel (MC blending coef.)
- * refinement if motion paradox detected before MC
- * blending, normalized 8 as '1', set 15 to 16, default = 8
- */
-/* Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset
- * (alpha - offset) for motion (MA blending coef.) refinement if high vertical
- * frequency detected before MA blending, default = 15
- */
-/* Bit 3: 0, reg_mcdi_mchighvertfrqgain.
- * gain for motion (MA blending coef.) refinement if high vertical frequency
- * detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8
- */
-#define MCDI_MC_REL_GAIN_OFFST_1 ((0x2f77))
-/* Bit 31:24, reg_mcdi_mcoutofboundrayoffst.
- * offset (rel + offset) for rel (MC blending coef.) refinement
- * if MC pointed out
- * of boundray before MC blending before MC blending, default = 255
- */
-/* Bit 23:20, reserved*/
-/* Bit 19:16, reg_mcdi_mcoutofboundraygain.
- * gain for rel (MC blending coef.) refinement
- * if MC pointed out of boundray before
- * MC blending, normalized 8 as '1', set 15 to 16, default = 8
- */
-/* Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst.
- * offset (rel + offset) for rel (MC blending coef.) refinement
- * if motion paradox
- * detected before MC blending before MC blending, default = 255
- */
-/* Bit 7: 4, reserved. */
-/* Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain.
- * gain for rel (MC blending coef.) refinement
- * if column cofidence failed before MC
- * blending, normalized 8 as '1', set 15 to 16, default = 8
- */
-#define MCDI_MC_COL_CFD_0 ((0x2f78))
-/* Bit 31: 0, mcdi_mc_col_cfd_0.
- * column cofidence value 0 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_1 ((0x2f79))
-/* Bit 31: 0, mcdi_mc_col_cfd_1.
- * column cofidence value 1 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_2 ((0x2f7a))
-/* Bit 31: 0, mcdi_mc_col_cfd_2.
- * column cofidence value 2 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_3 ((0x2f7b))
-/* Bit 31: 0, mcdi_mc_col_cfd_3.
- * column cofidence value 3 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_4 ((0x2f7c))
-/* Bit 31: 0, mcdi_mc_col_cfd_4.
- * column cofidence value 4 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_5 ((0x2f7d))
-/* Bit 31: 0, mcdi_mc_col_cfd_5.
- * column cofidence value 5 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_6 ((0x2f7e))
-/* Bit 31: 0, mcdi_mc_col_cfd_6.
- * column cofidence value 6 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_7 ((0x2f7f))
-/* Bit 31: 0, mcdi_mc_col_cfd_7.
- * column cofidence value 7 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_8 ((0x2f80))
-/* Bit 31: 0, mcdi_mc_col_cfd_8.
- * column cofidence value 8 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_9 ((0x2f81))
-/* Bit 31: 0, mcdi_mc_col_cfd_9.
- * column cofidence value 9 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_10 ((0x2f82))
-/* Bit 31: 0, mcdi_mc_col_cfd_10.
- * column cofidence value 10 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_11 ((0x2f83))
-/* Bit 31: 0, mcdi_mc_col_cfd_11.
- * column cofidence value 11 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_12 ((0x2f84))
-/* Bit 31: 0, mcdi_mc_col_cfd_12.
- * column cofidence value 12 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_13 ((0x2f85))
-/* Bit 31: 0, mcdi_mc_col_cfd_13.
- * column cofidence value 13 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_14 ((0x2f86))
-/* Bit 31: 0, mcdi_mc_col_cfd_14.
- * column cofidence value 14 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_15 ((0x2f87))
-/* Bit 31: 0, mcdi_mc_col_cfd_15.
- * column cofidence value 15 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_16 ((0x2f88))
-/* Bit 31: 0, mcdi_mc_col_cfd_16.
- * column cofidence value 16 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_17 ((0x2f89))
-/* Bit 31: 0, mcdi_mc_col_cfd_17.
- * column cofidence value 17 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_18 ((0x2f8a))
-/* Bit 31: 0, mcdi_mc_col_cfd_18.
- * column cofidence value 18 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_19 ((0x2f8b))
-/* Bit 31: 0, mcdi_mc_col_cfd_19.
- * column cofidence value 19 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_20 ((0x2f8c))
-/* Bit 31: 0, mcdi_mc_col_cfd_20.
- * column cofidence value 20 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_21 ((0x2f8d))
-/* Bit 31: 0, mcdi_mc_col_cfd_21.
- * column cofidence value 21 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_22 ((0x2f8e))
-/* Bit 31: 0, mcdi_mc_col_cfd_22.
- * column cofidence value 22 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_23 ((0x2f8f))
-/* Bit 31: 0, mcdi_mc_col_cfd_23.
- * column cofidence value 23 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_24 ((0x2f90))
-/* Bit 31: 0, mcdi_mc_col_cfd_24.
- * column cofidence value 24 read from software. initial = 0
- */
-#define MCDI_MC_COL_CFD_25 ((0x2f91))
-/* Bit 31: 0, mcdi_mc_col_cfd_25.
- * column cofidence value 25 read from software. initial = 0
- */
-/* ======= PRE RO Registers ==================================== */
-#define MCDI_RO_FLD_LUMA_AVG_SUM ((0x2fa0))
-/* Bit 31: 0, ro_mcdi_fldlumaavgsum.
- * block's luma avg sum of current filed (block based). initial = 0
- */
-#define MCDI_RO_GMV_VLD_CNT ((0x2fa1))
-/* Bit 31: 0, ro_mcdi_gmvvldcnt.
- * valid gmv's count of pre one filed (block based). initial = 0
- */
-#define MCDI_RO_RPT_FLG_CNT ((0x2fa2))
-/* Bit 31: 0, ro_mcdi_rptflgcnt.
- * repeat mv's count of pre one filed (block based). initial = 0
- */
-#define MCDI_RO_FLD_BAD_SAD_CNT ((0x2fa3))
-/* Bit 31: 0, ro_mcdi_fldbadsadcnt.
- * bad sad count of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_FLD_BAD_BADW_CNT ((0x2fa4))
-/* Bit 31: 0, ro_mcdi_fldbadbadwcnt.
- * bad badw count of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_FLD_BAD_REL_CNT ((0x2fa5))
-/* Bit 31: 0, ro_mcdi_fldbadrelcnt.
- * bad rel count of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_FLD_MTN_CNT ((0x2fa6))
-/* Bit 31: 0, ro_mcdi_fldmtncnt.
- * motion count of whole pre one field (pixel based). initial = 0
- */
-#define MCDI_RO_FLD_VLD_CNT ((0x2fa7))
-/* Bit 31: 0, ro_mcdi_fldvldcnt.
- * valid motion count of whole pre one field (pixel based). initial = 0
- */
-#define MCDI_RO_FLD_PD_22_PRE_CNT ((0x2fa8))
-/* Bit 31: 0, ro_mcdi_fldpd22precnt.
- * prevoius pd22 check count of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_FLD_PD_22_FOR_CNT ((0x2fa9))
-/* Bit 31: 0, ro_mcdi_fldpd22forcnt.
- * forward pd22 check count of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_FLD_PD_22_FLT_CNT ((0x2faa))
-/* Bit 31: 0, ro_mcdi_fldpd22fltcnt.
- * flat count (for pd22 check) of whole pre one field (block based). initial = 0
- */
-#define MCDI_RO_HIGH_VERT_FRQ_FLG ((0x2fab))
-/* Bit 31:16, reserved. */
-/* Bit 15: 8, ro_mcdi_highvertfrqcnt.
- * high vertical frequency count till prevoius one field. initial = 0
- */
-/* Bit 7: 3, reserved. */
-/* Bit 2: 1, ro_mcdi_highvertfrqphase.
- * high vertical frequency phase of prevoius one field. initial = 2
- */
-/* Bit 0, ro_mcdi_highvertfrqflg.
- * high vertical frequency flag of prevoius one field. initial = 0
- */
-#define MCDI_RO_GMV_LOCK_FLG ((0x2fac))
-/* Bit 31:16, reserved. */
-/* Bit 15: 8, ro_mcdi_gmvlckcnt.
- * global mv lock count till prevoius one field. initial = 0
- */
-/* Bit 7: 2, ro_mcdi_gmv.
- * global mv of prevoius one field. -31~31, initial = 32 (invalid value)
- */
-/* Bit 1, ro_mcdi_zerogmvlckflg.
- * zero global mv lock flag of prevoius one field. initial = 0
- */
-/* Bit 0, ro_mcdi_gmvlckflg.
- * global mv lock flag of prevoius one field. initial = 0
- */
-#define MCDI_RO_RPT_MV ((0x2fad))
-/* Bit 5: 0, ro_mcdi_rptmv.
- * repeate mv of prevoius one field. -31~31, initial = 32 (invalid value)
- */
-#define MCDI_RO_MOTION_PARADOX_FLG ((0x2fae))
-/* Bit 31:16, reserved. */
-/* Bit 15: 8, ro_mcdi_motionparadoxcnt.
- * motion paradox count till prevoius one field. initial = 0
- */
-/* Bit 7: 1, reserved. */
-/* Bit 0, ro_mcdi_motionparadoxflg.
- * motion paradox flag of prevoius one field. initial = 0
- */
-#define MCDI_RO_PD_22_FLG ((0x2faf))
-/* Bit 31:16, reserved. */
-/* Bit 15: 8, ro_mcdi_pd22cnt.
- * pull down 22 count till prevoius one field. initial = 0
- */
-/* Bit 7: 1, reserved. */
-/* Bit 0, ro_mcdi_pd22flg.
- * pull down 22 flag of prevoius one field. initial = 0
- */
-#define MCDI_RO_COL_CFD_0 ((0x2fb0))
-/* Bit 31: 0, ro_mcdi_col_cfd_0.
- * column cofidence value 0. initial = 0
- */
-#define MCDI_RO_COL_CFD_1 ((0x2fb1))
-/* Bit 31: 0, ro_mcdi_col_cfd_1.
- * column cofidence value 1. initial = 0
- */
-#define MCDI_RO_COL_CFD_2 ((0x2fb2))
-/* Bit 31: 0, ro_mcdi_col_cfd_2.
- * column cofidence value 2. initial = 0
- */
-#define MCDI_RO_COL_CFD_3 ((0x2fb3))
-/* Bit 31: 0, ro_mcdi_col_cfd_3.
- * column cofidence value 3. initial = 0
- */
-#define MCDI_RO_COL_CFD_4 ((0x2fb4))
-/* Bit 31: 0, ro_mcdi_col_cfd_4.
- * column cofidence value 4. initial = 0
- */
-#define MCDI_RO_COL_CFD_5 ((0x2fb5))
-/* Bit 31: 0, ro_mcdi_col_cfd_5.
- * column cofidence value 5. initial = 0
- */
-#define MCDI_RO_COL_CFD_6 ((0x2fb6))
-/* Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0 */
-#define MCDI_RO_COL_CFD_7 ((0x2fb7))
-/* Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0 */
-#define MCDI_RO_COL_CFD_8 ((0x2fb8))
-/* Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0 */
-#define MCDI_RO_COL_CFD_9 ((0x2fb9))
-/* Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0 */
-#define MCDI_RO_COL_CFD_10 ((0x2fba))
-/* Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0 */
-#define MCDI_RO_COL_CFD_11 ((0x2fbb))
-/* Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0 */
-#define MCDI_RO_COL_CFD_12 ((0x2fbc))
-/* Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0 */
-#define MCDI_RO_COL_CFD_13 ((0x2fbd))
-/* Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0 */
-#define MCDI_RO_COL_CFD_14 ((0x2fbe))
-/* Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0 */
-#define MCDI_RO_COL_CFD_15 ((0x2fbf))
-/* Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0 */
-#define MCDI_RO_COL_CFD_16 ((0x2fc0))
-/* Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0 */
-#define MCDI_RO_COL_CFD_17 ((0x2fc1))
-/* Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0 */
-#define MCDI_RO_COL_CFD_18 ((0x2fc2))
-/* Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0 */
-#define MCDI_RO_COL_CFD_19 ((0x2fc3))
-/* Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0 */
-#define MCDI_RO_COL_CFD_20 ((0x2fc4))
-/* Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0 */
-#define MCDI_RO_COL_CFD_21 ((0x2fc5))
-/* Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0 */
-#define MCDI_RO_COL_CFD_22 ((0x2fc6))
-/* Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0 */
-#define MCDI_RO_COL_CFD_23 ((0x2fc7))
-/* Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0 */
-#define MCDI_RO_COL_CFD_24 ((0x2fc8))
-/* Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0 */
-#define MCDI_RO_COL_CFD_25 ((0x2fc9))
-/* Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0 */
-
-#define DIPD_COMB_CTRL0 0x2fd0
-/* Bit 31: 24, cmb_v_dif_min */
-/* Bit 23: 16, cmb_v_dif_max */
-/* Bit 15: 8, cmb_crg_mi */
-/* Bit 7: 0, cmb_crg_max */
-#define DIPD_COMB_CTRL1 0x2fd1
-/* Bit 31: 31, pd_check_en */
-/* Bit 29: 24, cmb_wv_min3 */
-/* Bit 21: 16, cmb_wv_min2 */
-/* Bit 13: 8, cmb_wv_min1 */
-/* Bit 5: 0, cmb_wv_min0 */
-#define DIPD_COMB_CTRL2 0x2fd2
-/* Bit 31: 28, cmb_wnd_cnt1 */
-/* Bit 25: 20, ccnt_cmmin1 */
-/* Bit 19: 16, ccnt_mtmin */
-/* Bit 13: 8, ccnt_cmmin */
-/* Bit 5: 0, cmb_wv_min4 */
-#define DIPD_COMB_CTRL3 0x2fd3
-/* Bit 31: 31, cmb32spcl */
-/* Bit 17: 12, cmb_wnd_mthd */
-/* Bit 11: 4, cmb_abs_nocmb */
-/* Bit 3: 0, cnt_minlen */
-#define DIPD_COMB_CTRL4 0x2fd4
-/* Bit 30: 30, flm_stamtn_en */
-/* Bit 29: 28, in_horflt */
-/* Bit 27: 20, alpha */
-/* Bit 19: 16, thtran_ctmtd */
-/* Bit 15: 8, htran_mnth1 */
-/* Bit 7: 0, htran_mnth0 */
-#define DIPD_COMB_CTRL5 0x2fd5
-/* Bit 31: 24, fld_mindif */
-/* Bit 23: 16, frm_mindif */
-/* Bit 13: 8, flm_smp_mtn_cnt */
-/* Bit 7: 0, flm_smp_mtn_thd */
-#define DIPD_RO_COMB_0 0x2fd6
-#define DIPD_RO_COMB_1 0x2fd7
-#define DIPD_RO_COMB_2 0x2fd8
-#define DIPD_RO_COMB_3 0x2fd9
-#define DIPD_RO_COMB_4 0x2fda
-#define DIPD_RO_COMB_5 0x2fdb
-#define DIPD_RO_COMB_6 0x2fdc
-#define DIPD_RO_COMB_7 0x2fdd
-#define DIPD_RO_COMB_8 0x2fde
-#define DIPD_RO_COMB_9 0x2fdf
-#define DIPD_RO_COMB_10 0x2fe0
-#define DIPD_RO_COMB_11 0x2fe1
-#define DIPD_RO_COMB_12 0x2fe2
-#define DIPD_RO_COMB_13 0x2fe3
-#define DIPD_RO_COMB_14 0x2fe4
-#define DIPD_RO_COMB_15 0x2fe5
-#define DIPD_RO_COMB_16 0x2fe6
-#define DIPD_RO_COMB_17 0x2fe7
-#define DIPD_RO_COMB_18 0x2fe8
-#define DIPD_RO_COMB_19 0x2fe9
-#define DIPD_RO_COMB_20 0x2fea
-#define DIPD_COMB_CTRL6 0x2feb
-/* nr3 */
-#define NR3_MODE 0x2ff0
- /* d010bfc0 */
-#define NR3_COOP_PARA 0x2ff1
-#define NR3_CNOOP_GAIN 0x2ff2
-#define NR3_YMOT_PARA 0x2ff3
-#define NR3_CMOT_PARA 0x2ff4
-#define NR3_SUREMOT_YGAIN 0x2ff5
-#define NR3_SUREMOT_CGAIN 0x2ff6
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/di_multi_v3/register_nr4.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#define NR4_DRT_CTRL ((0x2da4))
-#define NR4_DRT_YSAD_GAIN ((0x2da5))
-#define NR4_DRT_CSAD_GAIN ((0x2da6))
-#define NR4_DRT_SAD_ALP_CORE ((0x2da7))
-#define NR4_DRT_ALP_MINMAX ((0x2da8))
-#define NR4_SNR_CTRL_REG ((0x2da9))
-#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa))
-#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab))
-#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac))
-#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad))
-#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae))
-#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf))
-#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0))
-#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1))
-#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2))
-#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3))
-#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4))
-#define NR4_MTN_CTRL ((0x2db5))
-#define NR4_MTN_REF_PAR0 ((0x2db6))
-#define NR4_MTN_REF_PAR1 ((0x2db7))
-#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8))
-#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9))
-#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba))
-#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb))
-#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc))
-#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd))
-#define NR4_MCNR_MV_CTRL_REG ((0x2dbe))
-#define NR4_MCNR_MV_GAIN0 ((0x2dbf))
-#define NR4_MCNR_LMV_PARM ((0x2dc0))
-#define NR4_MCNR_ALP0_REG (0x2dc1)
-#define NR4_MCNR_ALP1_AND_BET0_REG (0x2dc2)
-#define NR4_MCNR_BET1_AND_BET2_REG (0x2dc3)
-#define NR4_MCNR_AC_DC_CRTL (0x2dc4)
-#define NR4_MCNR_CM_CTRL0 (0x2dc5)
-#define NR4_MCNR_CM_PRAM (0x2dc6)
-#define NR4_MCNR_CM_RSHFT_ALP0 (0x2dc7)
-#define NR4_MCNR_BLUE_CENT (0x2dc8)
-#define NR4_MCNR_BLUE_GAIN_PAR0 (0x2dc9)
-#define NR4_MCNR_BLUE_GAIN_PAR1 (0x2dca)
-#define NR4_MCNR_CM_BLUE_CLIP0 (0x2dcb)
-#define NR4_MCNR_CM_BLUE_CLIP1 (0x2dcc)
-#define NR4_MCNR_GREEN_CENT (0x2dcd)
-#define NR4_MCNR_GREEN_GAIN_PAR0 (0x2dce)
-#define NR4_MCNR_GREEN_GAIN_PAR1 (0x2dcf)
-#define NR4_MCNR_GREEN_CLIP0 (0x2dd0)
-#define NR4_MCNR_GREEN_CLIP2 (0x2dd1)
-#define NR4_MCNR_SKIN_CENT (0x2dd2)
-#define NR4_MCNR_SKIN_GAIN_PAR0 (0x2dd3)
-#define NR4_MCNR_SKIN_GAIN_PAR1 (0x2dd4)
-#define NR4_MCNR_SKIN_CLIP0 (0x2dd5)
-#define NR4_MCNR_SKIN_CLIP1 (0x2dd6)
-#define NR4_MCNR_ALP1_GLB_CTRL (0x2dd7)
-#define NR4_MCNR_DC2NORM_LUT0 (0x2dd8)
-#define NR4_MCNR_DC2NORM_LUT1 (0x2dd9)
-#define NR4_MCNR_DC2NORM_LUT2 (0x2dda)
-#define NR4_MCNR_AC2NORM_LUT0 (0x2ddb)
-#define NR4_MCNR_AC2NORM_LUT1 (0x2ddc)
-#define NR4_MCNR_AC2NORM_LUT2 (0x2ddd)
-#define NR4_MCNR_SAD2ALP0_LUT0 (0x2dde)
-#define NR4_MCNR_SAD2ALP0_LUT1 (0x2ddf)
-#define NR4_MCNR_SAD2ALP0_LUT2 (0x2de0)
-#define NR4_MCNR_SAD2ALP0_LUT3 (0x2de1)
-#define NR4_MCNR_SAD2ALP1_LUT0 (0x2de2)
-#define NR4_MCNR_SAD2ALP1_LUT1 (0x2de3)
-#define NR4_MCNR_SAD2ALP1_LUT2 (0x2de4)
-#define NR4_MCNR_SAD2ALP1_LUT3 (0x2de5)
-#define NR4_MCNR_SAD2BET0_LUT0 (0x2de6)
-#define NR4_MCNR_SAD2BET0_LUT1 (0x2de7)
-#define NR4_MCNR_SAD2BET0_LUT2 (0x2de8)
-#define NR4_MCNR_SAD2BET0_LUT3 (0x2de9)
-#define NR4_MCNR_SAD2BET1_LUT0 (0x2dea)
-#define NR4_MCNR_SAD2BET1_LUT1 (0x2deb)
-#define NR4_MCNR_SAD2BET1_LUT2 (0x2dec)
-#define NR4_MCNR_SAD2BET1_LUT3 (0x2ded)
-#define NR4_MCNR_SAD2BET2_LUT0 (0x2dee)
-#define NR4_MCNR_SAD2BET2_LUT1 (0x2def)
-#define NR4_MCNR_SAD2BET2_LUT2 (0x2df0)
-#define NR4_MCNR_SAD2BET2_LUT3 (0x2df1)
-#define NR4_MCNR_RO_U_SUM (0x2df2)
-#define NR4_MCNR_RO_V_SUM (0x2df3)
-#define NR4_MCNR_RO_GRDU_SUM (0x2df4)
-#define NR4_MCNR_RO_GRDV_SUM (0x2df5)
-#define NR4_TOP_CTRL (0x2dff)
-#define NR4_MCNR_SAD_GAIN (0x3700)
-#define NR4_MCNR_LPF_CTRL (0x3701)
-#define NR4_MCNR_BLD_VS3LUT0 (0x3702)
-#define NR4_MCNR_BLD_VS3LUT1 (0x3703)
-#define NR4_MCNR_BLD_VS3LUT2 (0x3704)
-#define NR4_MCNR_BLD_VS2LUT0 (0x3705)
-#define NR4_MCNR_BLD_VS2LUT1 (0x3706)
-#define NR4_COEFBLT_LUT10 (0x3707)
-#define NR4_COEFBLT_LUT11 (0x3708)
-#define NR4_COEFBLT_LUT12 (0x3709)
-#define NR4_COEFBLT_LUT20 (0x370a)
-#define NR4_COEFBLT_LUT21 (0x370b)
-#define NR4_COEFBLT_LUT22 (0x370c)
-#define NR4_COEFBLT_LUT30 (0x370d)
-#define NR4_COEFBLT_LUT31 (0x370e)
-#define NR4_COEFBLT_LUT32 (0x370f)
-#define NR4_COEFBLT_CONV (0x3710)
-#define NR4_DBGWIN_YX0 (0x3711)
-#define NR4_DBGWIN_YX1 (0x3712)
-#define NR4_NM_X_CFG (0x3713)
-#define NR4_NM_Y_CFG (0x3714)
-#define NR4_NM_SAD_THD (0x3715)
-#define NR4_MCNR_BANDSPLIT_PRAM (0x3716)
-#define NR4_MCNR_ALP1_SGN_COR (0x3717)
-#define NR4_MCNR_ALP1_SGN_PRAM (0x3718)
-#define NR4_MCNR_ALP1_MVX_LUT1 (0x3719)
-#define NR4_MCNR_ALP1_MVX_LUT2 (0x371a)
-#define NR4_MCNR_ALP1_MVX_LUT3 (0x371b)
-#define NR4_MCNR_ALP1_LP_PRAM (0x371c)
-#define NR4_MCNR_ALP1_SGN_LUT1 (0x371d)
-#define NR4_MCNR_ALP1_SGN_LUT2 (0x371e)
-#define NR4_RO_NM_SAD_SUM (0x371f)
-#define NR4_RO_NM_SAD_CNT (0x3720)
-#define NR4_RO_NM_VAR_SUM (0x3721)
-#define NR4_RO_NM_VAR_SCNT (0x3722)
-#define NR4_RO_NM_VAR_MIN_MAX (0x3723)
-#define NR4_RO_NR4_DBGPIX_NUM (0x3724)
-#define NR4_RO_NR4_BLDVS2_SUM (0x3725)
-#define NR4_BLDVS3_SUM (0x3726)
-#define NR4_COEF12_SUM (0x3727)
-#define NR4_COEF123_SUM (0x3728)
-#define NR_DB_FLT_CTRL (0x3738)
-#define NR_DB_FLT_YC_THRD (0x3739)
-#define NR_DB_FLT_RANDLUT (0x373a)
-#define NR_DB_FLT_PXI_THRD (0x373b)
-#define NR_DB_FLT_SEED_Y (0x373c)
-#define NR_DB_FLT_SEED_V (0x373e)
-#define NR_DB_FLT_SEED3 (0x373f)
-#define LBUF_TOP_CTRL (0x2fff)
module_param(dolby_vision_level, uint, 0664);
MODULE_PARM_DESC(dolby_vision_level, "\n dolby_vision_level\n");
+static unsigned int primary_debug;
+module_param(primary_debug, uint, 0664);
+MODULE_PARM_DESC(primary_debug, "\n primary_debug\n");
/* STB: if sink support DV, always output DV*/
/* else always output SDR/HDR */
/* TV: when source is DV, convert to SDR */
MODULE_PARM_DESC(dolby_vision_status, "\n dolby_vision_status\n");
/* delay before first frame toggle when core off->on */
-static uint dolby_vision_wait_delay = 3;
+static uint dolby_vision_wait_delay = 2;
module_param(dolby_vision_wait_delay, uint, 0664);
MODULE_PARM_DESC(dolby_vision_wait_delay, "\n dolby_vision_wait_delay\n");
static int dolby_vision_wait_count;
((g_vtiming >> 16) & 0xff) : g_vsize_add)));
}
if (debug_dolby & 2)
- pr_dolby_dbg("g_hpotch %x, g_vpotch %x\n",
- g_hpotch, g_vpotch);
+ pr_dolby_dbg("core2a g_hpotch %x, g_vpotch %x, reset %d, set_lut %d\n",
+ g_hpotch, g_vpotch, reset, set_lut);
VSYNC_WR_DV_REG(DOLBY_CORE2A_SWAP_CTRL3,
(g_hwidth << 16) | ((g_vtiming & 0xff00) ?
((g_vtiming >> 8) & 0xff) : g_vwidth));
ret |= 2;
}
- if ((osd_graphic_width != new_osd_graphic_width) ||
- (osd_graphic_height != new_osd_graphic_height)) {
- if (debug_dolby & 0x10)
+ if (osd_graphic_width != new_osd_graphic_width ||
+ osd_graphic_height != new_osd_graphic_height) {
+ if (debug_dolby & 0x2)
pr_dolby_dbg("osd changed %d %d-%d %d\n",
osd_graphic_width,
osd_graphic_height,
new_osd_graphic_width,
new_osd_graphic_height);
- /* TODO: since tm2 can change osd pps position */
- if (!is_osd_off && !is_meson_tm2() && !is_meson_sc2()) {
+
+ /* TODO: g12/tm2/sc2/t7 osd pps is after dolby core2, but */
+ /* sometimes osd do crop,should monitor osd size change*/
+ if (!is_osd_off /*&& !is_meson_tm2() && !is_meson_sc2()*/) {
osd_graphic_width = new_osd_graphic_width;
osd_graphic_height = new_osd_graphic_height;
ret |= 2;
}
if (old_dolby_vision_graphic_max !=
dolby_vision_graphic_max) {
- if (debug_dolby & 0x10)
+ if (debug_dolby & 0x2)
pr_dolby_dbg("graphic max changed %d-%d\n",
old_dolby_vision_graphic_max,
dolby_vision_graphic_max);
is_meson_tm2_stbmode() ||
is_meson_sc2()) {
hdr_osd_off();
+ hdr_vd1_off();
set_hdr_module_status(VD1_PATH,
HDR_MODULE_BYPASS);
if (dolby_vision_mask & 4)
type = (type << 8) | *p++;
type = (type << 8) | *p++;
type = (type << 8) | *p++;
- if (type == 0x01000000)
+ if (type == DV_SEI ||
+ (type & 0xffff0000) == DV_AV1_SEI)
return true;
p += size;
}
unsigned int rpu_size = 0;
enum signal_format_e *src_format = (enum signal_format_e *)fmt;
static int parse_process_count;
+ int dump_size = 100;
if (!aux_buf || aux_size == 0)
return 1;
ret = 1;
goto parse_err;
}
- if ((type == 0x01000000) || /* hevc t35 sei */
- ((type & 0xff000000) == 0x14000000)) { /* av1 t35 obu */
+ if ((type == DV_SEI) || /* hevc t35 sei */
+ ((type & 0xffff0000) == DV_AV1_SEI)) { /* av1 t35 obu */
*total_comp_size = 0;
*total_md_size = 0;
- if ((type & 0xff000000) == 0x14000000 &&
+ if ((type & 0xffff0000) == DV_AV1_SEI &&
p[0] == 0xb5 &&
p[1] == 0x00 &&
p[2] == 0x3b &&
meta_buf[i + 14],
meta_buf[i + 15]);
}
-
if (tv_mode) {
if (!p_funcs_tv) {
ret = 1;
spin_unlock_irqrestore(&dovi_lock, flags);
pr_dolby_error(
"meta(%d), pts(%lld) -> metadata parser init fail\n",
- size, vf->pts_us64);
+ rpu_size, vf->pts_us64);
*total_comp_size = backup_comp_size;
*total_md_size = backup_md_size;
ret = 2;
}
md_size = comp_size = 0;
-
if (is_meson_tvmode())
rpu_ret =
p_funcs_tv->metadata_parser_process(
- meta_buf, size,
- comp_buf + *total_comp_size,
+ meta_buf, rpu_size,
+ comp_buf +
+ *total_comp_size,
&comp_size,
md_buf + *total_md_size,
&md_size,
else
rpu_ret =
p_funcs_stb->metadata_parser_process(
- meta_buf, size,
- comp_buf + *total_comp_size,
+ meta_buf, rpu_size,
+ comp_buf +
+ *total_comp_size,
&comp_size,
md_buf + *total_md_size,
&md_size,
if (rpu_ret < 0) {
pr_dolby_error(
"meta(%d), pts(%lld) -> metadata parser process fail\n",
- size, vf->pts_us64);
+ rpu_size, vf->pts_us64);
ret = 3;
} else {
if (*total_comp_size + comp_size
}
p += size;
}
+#ifdef V1_6_1
+ if (atsc_sei) {
+ struct _dv_vui_param_s_ vui_param;
+ u32 len_2086_sei = 0;
+ u32 len_2094_sei = 0;
+ u8 payload_2086_sei[MAX_LENGTH_2086_SEI];
+ u8 payload_2094_sei[MAX_LENGTH_2094_SEI];
+ unsigned char nal_type;
+ unsigned char sei_payload_type = 0;
+ unsigned char sei_payload_size = 0;
+
+ vui_param.i_video_format = (vf->signal_type >> 26) & 7;
+ vui_param.b_video_full_range = (vf->signal_type >> 24) & 2;
+ vui_param.b_colour_description = (vf->signal_type >> 24) & 1;
+ vui_param.i_colour_primaries = (vf->signal_type >> 16) & 0xff;
+ vui_param.i_transfer_characteristics =
+ (vf->signal_type >> 8) & 0xff;
+ vui_param.i_matrix_coefficients = (vf->signal_type) & 0xff;
+ if (debug_dolby & 2)
+ pr_dolby_dbg("vui_param %d, %d, %d, %d, %d, %d\n",
+ vui_param.i_video_format,
+ vui_param.b_video_full_range,
+ vui_param.b_colour_description,
+ vui_param.i_colour_primaries,
+ vui_param.i_transfer_characteristics,
+ vui_param.i_matrix_coefficients);
+
+ p = aux_buf;
+
+ if ((debug_dolby & 0x200) && dump_enable) {
+ pr_dolby_dbg("aux_buf(%d):\n", aux_size);
+ for (i = 0; i < aux_size; i += 8)
+ pr_info("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ p[i],
+ p[i + 1],
+ p[i + 2],
+ p[i + 3],
+ p[i + 4],
+ p[i + 5],
+ p[i + 6],
+ p[i + 7]);
+ }
+ while (p < aux_buf + aux_size - 8) {
+ size = *p++;
+ size = (size << 8) | *p++;
+ size = (size << 8) | *p++;
+ size = (size << 8) | *p++;
+ type = *p++;
+ type = (type << 8) | *p++;
+ type = (type << 8) | *p++;
+ type = (type << 8) | *p++;
+ if (debug_dolby & 2)
+ pr_dolby_dbg("type: 0x%x\n", type);
+
+ /*4 byte size + 4 byte type*/
+ /*1 byte nal_type + 1 byte (layer_id+temporal_id)*/
+ /*1 byte payload type + 1 byte size + payload data*/
+ if (type == 0x02000000) {
+ nal_type = ((*p) & 0x7E) >> 1; /*nal unit type*/
+ if (debug_dolby & 2)
+ pr_dolby_dbg("nal_type: %d\n",
+ nal_type);
+
+ if (nal_type == PREFIX_SEI_NUT ||
+ nal_type == SUFFIX_SEI_NUT) {
+ sei_payload_type = *(p + 2);
+ sei_payload_size = *(p + 3);
+ if (debug_dolby & 2)
+ pr_dolby_dbg("type %d, size %d\n",
+ sei_payload_type,
+ sei_payload_size);
+ if (sei_payload_type ==
+ SEI_MASTERING_DISPLAY_COLOUR_VOLUME) {
+ len_2086_sei =
+ sei_payload_size;
+ memcpy(payload_2086_sei, p + 4,
+ len_2086_sei);
+ } else if (sei_payload_type ==
+ SEI_USER_DATA_REGISTERED_ITU_T_T35) {
+ len_2094_sei =
+ sei_payload_size;
+ memcpy(payload_2094_sei, p + 4,
+ len_2094_sei);
+ }
+ if (len_2086_sei > 0 &&
+ len_2094_sei > 0)
+ break;
+ }
+ }
+ p += size;
+ }
+ if (len_2094_sei > 0) {
+ /* source is VS10 */
+ *total_comp_size = 0;
+ *total_md_size = 0;
+ *src_format = FORMAT_DOVI;
+ p_atsc_md.vui_param = vui_param;
+ p_atsc_md.length_2086_sei = len_2086_sei;
+ memcpy(p_atsc_md.payload_2086_sei, payload_2086_sei,
+ len_2086_sei);
+ p_atsc_md.length_2094_sei = len_2094_sei;
+ memcpy(p_atsc_md.payload_2094_sei, payload_2094_sei,
+ len_2094_sei);
+ size = sizeof(struct _dv_atsc_s_);
+ if (size > sizeof(meta_buf))
+ size = sizeof(meta_buf);
+ memcpy(meta_buf, (unsigned char *)(&p_atsc_md), size);
+ if ((debug_dolby & 4) && dump_enable) {
+ pr_dolby_dbg("metadata(%d):\n", size);
+ for (i = 0; i < size; i += 8)
+ pr_info("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ meta_buf[i],
+ meta_buf[i + 1],
+ meta_buf[i + 2],
+ meta_buf[i + 3],
+ meta_buf[i + 4],
+ meta_buf[i + 5],
+ meta_buf[i + 6],
+ meta_buf[i + 7]);
+ }
+ if (tv_mode) {
+ if (!p_funcs_tv) {
+ ret = 1;
+ goto parse_err;
+ }
+ } else {
+ if (!p_funcs_stb) {
+ ret = 1;
+ goto parse_err;
+ }
+ }
+ /* prepare metadata parser */
+ spin_lock_irqsave(&dovi_lock, flags);
+ parser_ready = 0;
+ reset_flag = 2; /*flag: bit0 flag, bit1 0->dv, 1->atsc*/
+ if (!metadata_parser) {
+ if (is_meson_tvmode()) {
+ metadata_parser =
+ p_funcs_tv->metadata_parser_init(
+ dolby_vision_flags
+ & FLAG_CHANGE_SEQ_HEAD
+ ? 1 : 0);
+ p_funcs_tv->metadata_parser_reset(
+ reset_flag | 1);
+ } else {
+ metadata_parser =
+ p_funcs_stb->metadata_parser_init(
+ dolby_vision_flags
+ & FLAG_CHANGE_SEQ_HEAD
+ ? 1 : 0);
+ p_funcs_stb->metadata_parser_reset(
+ reset_flag | 1);
+ }
+ if (metadata_parser) {
+ parser_ready = 1;
+ if (debug_dolby & 1)
+ pr_dolby_dbg("metadata parser init OK\n");
+ }
+ } else {
+ if (is_meson_tvmode()) {
+ if (p_funcs_tv->metadata_parser_reset(
+ reset_flag |
+ metadata_parser_reset_flag
+ ) == 0)
+ metadata_parser_reset_flag = 0;
+ } else {
+ if (p_funcs_stb->metadata_parser_reset(
+ reset_flag |
+ metadata_parser_reset_flag
+ ) == 0)
+ metadata_parser_reset_flag = 0;
+ }
+ parser_ready = 1;
+ }
+ if (!parser_ready) {
+ spin_unlock_irqrestore(&dovi_lock, flags);
+ pr_dolby_error(
+ "meta(%d), pts(%lld) -> metadata parser init fail\n",
+ size, vf->pts_us64);
+ *total_comp_size = backup_comp_size;
+ *total_md_size = backup_md_size;
+ ret = 2;
+ goto parse_err;
+ }
+
+ md_size = 0;
+ comp_size = 0;
+
+ if (is_meson_tvmode())
+ rpu_ret =
+ p_funcs_tv->metadata_parser_process(
+ meta_buf, size,
+ comp_buf + *total_comp_size,
+ &comp_size,
+ md_buf + *total_md_size,
+ &md_size,
+ true);
+ else
+ rpu_ret =
+ p_funcs_stb->metadata_parser_process(
+ meta_buf, size,
+ comp_buf + *total_comp_size,
+ &comp_size,
+ md_buf + *total_md_size,
+ &md_size,
+ true);
+
+ if (rpu_ret < 0) {
+ pr_dolby_error(
+ "meta(%d), pts(%lld) -> metadata parser process fail\n",
+ size, vf->pts_us64);
+ ret = 3;
+ } else {
+ if (*total_comp_size + comp_size
+ < COMP_BUF_SIZE)
+ *total_comp_size += comp_size;
+ else
+ parser_overflow = true;
+
+ if (*total_md_size + md_size
+ < MD_BUF_SIZE)
+ *total_md_size += md_size;
+ else
+ parser_overflow = true;
+ if (rpu_ret == 1)
+ *ret_flags = 1;
+ ret = 0;
+ }
+ spin_unlock_irqrestore(&dovi_lock, flags);
+ if (parser_overflow) {
+ ret = 2;
+ }
+ }
+ }
+#endif
+
if (*total_md_size) {
if (debug_dolby & 1)
pr_dolby_dbg(
if ((debug_dolby & 4) && dump_enable) {
pr_dolby_dbg("parsed md(%d):\n", *total_md_size);
for (i = 0; i < *total_md_size + 7; i += 8) {
- pr_info("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
md_buf[i],
md_buf[i + 1],
md_buf[i + 2],
md_buf[i + 6],
md_buf[i + 7]);
}
+ pr_dolby_dbg("parsed comp(%d):\n", *total_comp_size);
+ if (*total_comp_size < dump_size)
+ dump_size = *total_comp_size;
+ for (i = 0; i < dump_size + 7; i += 8)
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ comp_buf[i],
+ comp_buf[i + 1],
+ comp_buf[i + 2],
+ comp_buf[i + 3],
+ comp_buf[i + 4],
+ comp_buf[i + 5],
+ comp_buf[i + 6],
+ comp_buf[i + 7]);
}
}
parse_err:
}
#define INORM 50000
+
static u32 bt2020_primaries[3][2] = {
{0.17 * INORM + 0.5, 0.797 * INORM + 0.5}, /* G */
{0.131 * INORM + 0.5, 0.046 * INORM + 0.5}, /* B */
{0.708 * INORM + 0.5, 0.292 * INORM + 0.5}, /* R */
};
+static u32 p3_primaries[3][2] = {
+ {0.265 * INORM + 0.5, 0.69 * INORM + 0.5}, /* G */
+ {0.15 * INORM + 0.5, 0.06 * INORM + 0.5}, /* B */
+ {0.68 * INORM + 0.5, 0.32 * INORM + 0.5}, /* R */
+};
+
static u32 bt2020_white_point[2] = {
0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5
};
+static u32 p3_white_point[2] = {
+ 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5
+};
+
void prepare_hdr10_param(
struct vframe_master_display_colour_s *p_mdc,
struct hdr10_param_s *p_hdr10_param)
uint32_t min_lum = 50;
int primaries_type = 0;
- if (dolby_vision_flags & FLAG_CERTIFICAION) {
+ if (get_primary_policy() == PRIMARIES_NATIVE ||
+ primary_debug == 1 ||
+ (dolby_vision_flags & FLAG_CERTIFICAION)) {
p_hdr10_param->
min_display_mastering_luminance
= min_lum;
p_hdr10_param->max_content_light_level = 0;
p_hdr10_param->max_pic_average_light_level = 0;
return;
+ } else if (get_primary_policy() == PRIMARIES_AUTO ||
+ primary_debug == 2) {
+ p_hdr10_param->
+ min_display_mastering_luminance
+ = min_lum;
+ p_hdr10_param->
+ max_display_mastering_luminance
+ = max_lum;
+ p_hdr10_param->Rx
+ = p3_primaries[2][0];
+ p_hdr10_param->Ry
+ = p3_primaries[2][1];
+ p_hdr10_param->Gx
+ = p3_primaries[0][0];
+ p_hdr10_param->Gy
+ = p3_primaries[0][1];
+ p_hdr10_param->Bx
+ = p3_primaries[1][0];
+ p_hdr10_param->By
+ = p3_primaries[1][1];
+ p_hdr10_param->Wx
+ = p3_white_point[0];
+ p_hdr10_param->Wy
+ = p3_white_point[1];
+ p_hdr10_param->max_content_light_level = 0;
+ p_hdr10_param->max_pic_average_light_level = 0;
+ return;
}
primaries_type = get_primaries_type(p_mdc);
? YUV422_BIT12 : RGB_8BIT, &vsif,
false);
}
- pr_dolby_dbg("send_hdmi_pkt_fake: %s\n",
+ pr_dolby_dbg("send_hdmi_pkt ahead: %s\n",
dovi_ll_enable ? "LL" : "DV");
}
}
static int last_current_format;
int ret = -1;
bool mel_flag = false;
+ int dump_size = 100;
memset(&req, 0, (sizeof(struct provider_aux_req_s)));
memset(&el_req, 0, (sizeof(struct provider_aux_req_s)));
/* check source format */
fmt = get_vframe_src_fmt(vf);
- if (((fmt == VFRAME_SIGNAL_FMT_DOVI) ||
- (fmt == VFRAME_SIGNAL_FMT_INVALID)) &&
+ if ((fmt == VFRAME_SIGNAL_FMT_DOVI ||
+ fmt == VFRAME_SIGNAL_FMT_INVALID) &&
!vf->discard_dv_data) {
+ vf_notify_provider_by_name
+ (dv_provider,
+ VFRAME_EVENT_RECEIVER_GET_AUX_DATA,
+ (void *)&req);
+ }
+ /* use callback aux date first, if invalid, use sei_ptr */
+ if ((!req.aux_buf || !req.aux_size) &&
+ fmt == VFRAME_SIGNAL_FMT_DOVI) {
u32 sei_size = 0;
char *sei;
- vf_notify_provider_by_name(
- dv_provider,
- VFRAME_EVENT_RECEIVER_GET_AUX_DATA,
- (void *)&req);
- /* use aux date first, if invaild, use sei_ptr */
- if ((!req.aux_buf || !req.aux_size) &&
- (fmt == VFRAME_SIGNAL_FMT_DOVI)) {
- if (debug_dolby & 1)
- pr_dolby_dbg("invalid aux buf %p %x, el %d\n",
- req.aux_buf,
- req.aux_size,
- req.dv_enhance_exist);
-
- sei = (char *)get_sei_from_src_fmt(
- vf, &sei_size);
- if (sei && sei_size) {
- req.aux_buf = sei;
- req.aux_size = sei_size;
- req.dv_enhance_exist =
- vf->src_fmt.dual_layer;
- }
+ if (debug_dolby & 1)
+ pr_dolby_dbg("no aux %p %x, el %d from %s, use sei_ptr\n",
+ req.aux_buf,
+ req.aux_size,
+ req.dv_enhance_exist,
+ dv_provider);
+
+ sei = (char *)get_sei_from_src_fmt(
+ vf, &sei_size);
+ if (sei && sei_size) {
+ req.aux_buf = sei;
+ req.aux_size = sei_size;
+ req.dv_enhance_exist =
+ vf->src_fmt.dual_layer;
}
+
}
if (debug_dolby & 1)
- pr_dolby_dbg("dvbldec get vf %p(%d), fmt %d, aux %p %x, el %d\n",
- vf, vf->discard_dv_data, fmt,
+ pr_dolby_dbg("%s get vf %p(%d), fmt %d, aux %p %x, el %d\n",
+ dv_provider, vf, vf->discard_dv_data, fmt,
req.aux_buf,
req.aux_size,
req.dv_enhance_exist);
/* parse meta in base layer */
if (toggle_mode != 2) {
ret = get_md_from_src_fmt(vf);
- if (ret == 1) { /*parse successed*/
+ if (ret == 1) { /*parse succeeded*/
meta_flag_bl = 0;
src_format = FORMAT_DOVI;
memcpy(md_buf[current_id],
total_md_size = vf->src_fmt.md_size;
total_comp_size = vf->src_fmt.comp_size;
ret_flags = vf->src_fmt.parse_ret_flags;
- } else if (ret == 2) { /*parse failed*/
- meta_flag_bl = 1;
- src_format = FORMAT_DOVI;
- pr_dolby_dbg("parser error vf %p\n", vf);
- } else { /*no parse*/
+ if ((debug_dolby & 4) && dump_enable) {
+ pr_dolby_dbg("get md_buf %p, size(%d):\n",
+ vf->src_fmt.md_buf,
+ vf->src_fmt.md_size);
+ for (i = 0; i < total_md_size; i += 8)
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ md_buf[current_id][i],
+ md_buf[current_id][i + 1],
+ md_buf[current_id][i + 2],
+ md_buf[current_id][i + 3],
+ md_buf[current_id][i + 4],
+ md_buf[current_id][i + 5],
+ md_buf[current_id][i + 6],
+ md_buf[current_id][i + 7]);
+ pr_dolby_dbg("get comp(%d):\n",
+ vf->src_fmt.comp_size);
+ if (vf->src_fmt.comp_size < dump_size)
+ dump_size =
+ vf->src_fmt.comp_size;
+ for (i = 0; i < dump_size; i += 8)
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ comp_buf[current_id][i],
+ comp_buf[current_id][i + 1],
+ comp_buf[current_id][i + 2],
+ comp_buf[current_id][i + 3],
+ comp_buf[current_id][i + 4],
+ comp_buf[current_id][i + 5],
+ comp_buf[current_id][i + 6],
+ comp_buf[current_id][i + 7]);
+ }
+ } else { /*no parse or parse failed*/
meta_flag_bl =
parse_sei_and_meta(
vf, &req,
}
if (ret_flags && req.dv_enhance_exist) {
- vf_notify_provider_by_name(
+ if (!strcmp(dv_provider, "dvbldec"))
+ vf_notify_provider_by_name(
dv_provider,
VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL,
(void *)&req);
if (flag < 0) {
new_dovi_setting.video_width = 0;
new_dovi_setting.video_height = 0;
- pr_dolby_error("control_path(%d, %d) failed\n",
- src_format, dst_format);
+
+ pr_dolby_error("control_path(%d, %d) failed %d\n",
+ src_format, dst_format, flag);
+ if ((debug_dolby & 0x2000) && dump_enable &&
+ total_md_size > 0) {
+ pr_dolby_dbg("control_path failed, md(%d):\n",
+ total_md_size);
+ for (i = 0; i < total_md_size + 7; i += 8)
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ md_buf[current_id][i],
+ md_buf[current_id][i + 1],
+ md_buf[current_id][i + 2],
+ md_buf[current_id][i + 3],
+ md_buf[current_id][i + 4],
+ md_buf[current_id][i + 5],
+ md_buf[current_id][i + 6],
+ md_buf[current_id][i + 7]);
+ }
}
return -1; /* do nothing for this frame */
}
unsigned int mode = dolby_vision_mode;
enum signal_format_e check_format;
const struct vinfo_s *vinfo = get_current_vinfo();
+ bool vd1_on = false;
if (single_step_enable) {
if (dolby_vision_flags & FLAG_SINGLE_STEP)
dolby_vision_wait_on = true;
/*dv off->on, delay vfream*/
- if (dolby_vision_policy == 1 &&
+ if (dolby_vision_policy ==
+ DOLBY_VISION_FOLLOW_SOURCE &&
+ dolby_vision_mode ==
+ DOLBY_VISION_OUTPUT_MODE_BYPASS &&
mode ==
DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL &&
dolby_vision_wait_delay > 0) {
dolby_vision_wait_count =
dolby_vision_wait_delay;
- send_hdmi_pkt_ahead(FORMAT_DOVI, vinfo);
+ } else {
+ dolby_vision_wait_count = 0;
}
pr_dolby_dbg("dolby_vision_need_wait src=%d mode=%d\n",
check_format, mode);
}
}
+ /*chip after g12 not used bit VPP_MISC 9:11*/
+ if (is_meson_gxm() || is_meson_txlx() || is_meson_g12()) {
+ if (READ_VPP_DV_REG(VPP_MISC) & (1 << 10))
+ vd1_on = true;
+ } else if (is_meson_tm2() || is_meson_sc2()) {
+ if (READ_VPP_DV_REG(VD1_BLEND_SRC_CTRL) & (1 << 0))
+ vd1_on = true;
+ }
/* don't use run mode when sdr -> dv and vd1 not disable */
- if (dolby_vision_wait_init &&
- (READ_VPP_DV_REG(VPP_MISC) & (1<<10)))
+ if (dolby_vision_wait_init && vd1_on)
dolby_vision_on_count =
dolby_vision_run_mode_delay + 1;
}
- if (dolby_vision_wait_init
- && dolby_vision_wait_count) {
- dolby_vision_wait_count--;
- pr_dolby_dbg("delay wait %d\n",
- dolby_vision_wait_count);
+
+ if (dolby_vision_wait_init && dolby_vision_wait_count > 0) {
+ if (debug_dolby & 8)
+ pr_dolby_dbg("delay wait %d\n",
+ dolby_vision_wait_count);
+
+ if (!get_disable_video_flag(VD1_PATH)) {
+ /*update only after app enable video display,*/
+ /* to distinguish play start and netflix exit*/
+ send_hdmi_pkt_ahead(FORMAT_DOVI, vinfo);
+ dolby_vision_wait_count--;
+ } else {
+ /*exit netflix, still process vf after video disable,*/
+ /*wait init will be on, need reset wait init */
+ dolby_vision_wait_init = false;
+ dolby_vision_wait_count = 0;
+ if (debug_dolby & 8)
+ pr_dolby_dbg("clear dolby_vision_wait_on\n");
+ }
ret = 1;
} else if (dolby_vision_core1_on
&& (dolby_vision_on_count <=
dolby_vision_run_mode_delay))
ret = 1;
+ if (debug_dolby & 8)
+ pr_dolby_dbg("dv wait return %d\n", ret);
+
return ret;
}
}
}
+ if (debug_dolby & 8)
+ pr_dolby_dbg("vf %p, turn_off %d, video_status %d, toggle %d, flag %x\n",
+ vf, video_turn_off, video_status,
+ toggle_mode, dolby_vision_flags);
+
if ((!vf && video_turn_off) ||
(video_status == -1)) {
if (dolby_vision_policy_process(&mode, FORMAT_SDR)) {
DOLBY_VISION_OUTPUT_MODE_BYPASS;
dolby_vision_set_toggle_flag(0);
dolby_vision_wait_on = false;
+ dolby_vision_wait_init = false;
} else
dolby_vision_set_toggle_flag(1);
}
}
EXPORT_SYMBOL(get_dolby_vision_hdr_policy);
+bool chip_support_dv(void)
+{
+ if (is_meson_txlx() || is_meson_gxm() ||
+ is_meson_g12() || is_meson_tm2() ||
+ is_meson_sc2())
+ return true;
+ else
+ return false;
+}
+
int register_dv_functions(const struct dolby_vision_func_s *func)
{
int ret = -1;
dolby_vision_on_in_uboot = 0;
}
+ if (!chip_support_dv()) {
+ pr_info("chip not support dv\n");
+ return ret;
+ }
+
if ((!p_funcs_stb || !p_funcs_tv) && func) {
if (func->control_path && !p_funcs_stb) {
pr_info("*** register_dv_stb_functions.***\n");
void dv_mem_power_on(enum vpu_mod_e mode);
void dv_mem_power_off(enum vpu_mod_e mode);
int get_dv_mem_power_flag(enum vpu_mod_e mode);
+bool get_disable_video_flag(enum vd_path_e vd_path);
+
#endif
module_param(hdr_policy, uint, 0664);
MODULE_PARM_DESC(hdr_policy, "\n current hdr_policy\n");
+/* 0: source: use src meta */
+/* 1: Auto: 601/709=709 P3/2020=P3 */
+/* 2: Native: 601/709=off P3/2020=2020 */
+static uint primary_policy;
+static uint cur_primary_policy;
+module_param(primary_policy, uint, 0664);
+MODULE_PARM_DESC(primary_policy, "\n current primary_policy\n");
+
static int __init boot_hdr_policy(char *str)
{
if (strncmp("1", str, 1) == 0) {
module_param(force_output, uint, 0664);
MODULE_PARM_DESC(force_output, "\n current force_output\n");
+int get_primary_policy(void)
+{
+ return primary_policy;
+}
+EXPORT_SYMBOL(get_primary_policy);
+
int get_hdr_policy(void)
{
int dv_policy = 0;
signal_change_flag |= SIG_HDR_MODE;
}
+ if (get_primary_policy() != cur_primary_policy) {
+ pr_csc(4, "primary policy changed from %d to %d.\n",
+ cur_primary_policy,
+ get_primary_policy());
+ signal_change_flag |= SIG_HDR_MODE;
+ }
+
source_format[VD1_PATH] = get_source_type(VD1_PATH);
source_format[VD2_PATH] = get_source_type(VD2_PATH);
get_cur_vd_signal_type(vd_path);
source_format[vd_path] = get_hdr_source_type();
}
- if ((vf != NULL) && (flags & CSC_FLAG_TOGGLE_FRAME)) {
- hdr10p_meta_updated = hdr10_plus_metadata_update(
- vf, csc_type,
- &hdmitx_hdr10plus_params[vd_path]);
+ if (vf && (flags & (CSC_FLAG_TOGGLE_FRAME | CSC_FLAG_FORCE_SIGNAL))) {
+ hdr10p_meta_updated =
+ hdr10_plus_metadata_update(vf, csc_type,
+ &hdmitx_hdr10plus_params[vd_path]);
if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) ||
(csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) {
vf, csc_type, signal_change_flag,
vinfo, p, vd_path, source_format);
cur_hdr_policy = get_hdr_policy();
+ cur_primary_policy = get_primary_policy();
}
if (
extern int tx_op_color_primary;
extern uint cur_csc_type[VD_PATH_MAX];
+/* 0: source: use src meta */
+/* 1: Auto: 601/709=709 P3/2020=P3 */
+/* 2: Native: 601/709=off P3/2020=2020 */
+#define PRIMARIES_SOURCE 0
+#define PRIMARIES_AUTO 1
+#define PRIMARIES_NATIVE 2
+
int get_hdr_policy(void);
+int get_primary_policy(void);
void set_cur_hdr_policy(uint policy);
enum output_format_e get_force_output(void);
void set_force_output(enum output_format_e output);
dv_hdr_policy = get_dolby_vision_hdr_policy();
}
- if (get_hdr_module_status(vd_path) != HDR_MODULE_ON) {
+ if (get_hdr_module_status(vd_path) != HDR_MODULE_ON &&
+ cur_hdr_policy != 2) {
/* hdr module off or bypass */
sdr_process_mode[vd_path] = PROC_BYPASS;
hdr_process_mode[vd_path] = PROC_BYPASS;
case HDRTYPE_SDR:
/* VD2 source SDR */
if ((target_format[oth_path] ==
+ BT2020) ||
+ (target_format[oth_path] ==
BT2020_PQ) ||
(target_format[oth_path] ==
BT2020_PQ_DYNAMIC)) {
sdr_process_mode[vd_path] =
PROC_SDR_TO_HDR;
target_format[vd_path] =
- BT2020_PQ;
+ target_format[oth_path];
} else if (target_format[oth_path] ==
BT2020_HLG) {
/* other layer on and not sdr */
0.3127 * NORM + 0.5, 0.3290 * NORM + 0.5
};
+static u32 std_p3_primaries[3][2] = {
+ {0.265 * NORM + 0.5, 0.69 * NORM + 0.5}, /* G */
+ {0.15 * NORM + 0.5, 0.06 * NORM + 0.5}, /* B */
+ {0.68 * NORM + 0.5, 0.32 * NORM + 0.5}, /* R */
+};
+
+static u32 std_p3_white_point[2] = {
+ 0.3127 * NORM + 0.5, 0.3290 * NORM + 0.5
+};
+
static u32 std_bt709_prmy[3][2] = {
{0.30 * NORM + 0.5, 0.60 * NORM + 0.5}, /* G */
{0.15 * NORM + 0.5, 0.06 * NORM + 0.5}, /* B */
} else if ((source_type[vd_path] == HDRTYPE_HDR10) ||
(source_type[vd_path] == HDRTYPE_HLG) ||
(source_type[vd_path] == HDRTYPE_HDR10PLUS)) {
- for (i = 0; i < 3; i++)
- for (j = 0; j < 2; j++) {
- src_prmy[i][j] =
- std_bt2020_prmy[(i + 2) % 3][j];
- src_prmy[3][j] = std_bt2020_white_point[j];
- }
+ if (get_primary_policy() == PRIMARIES_AUTO) {
+ for (i = 0; i < 3; i++)
+ for (j = 0; j < 2; j++) {
+ src_prmy[i][j] =
+ std_p3_primaries
+ [(i + 2) % 3][j];
+ src_prmy[3][j] =
+ std_p3_white_point
+ [j];
+ }
+ } else {
+ for (i = 0; i < 3; i++)
+ for (j = 0; j < 2; j++) {
+ src_prmy[i][j] =
+ std_bt2020_prmy[(i + 2) % 3][j];
+ src_prmy[3][j] =
+ std_bt2020_white_point[j];
+ }
+ }
}
- if (vinfo->master_display_info.present_flag) {
+ if (vinfo->master_display_info.present_flag &&
+ (get_primary_policy() == PRIMARIES_SOURCE)) {
p = &vinfo->master_display_info;
for (i = 0; i < 3; i++)
for (j = 0; j < 2; j++) {
unsigned int GMUT_COEF4 = 0;
unsigned int hdr_ctrl = 0;
+ unsigned int hdr_clk_gate = 0;
+ unsigned int cur_hdr_ctrl = 0;
int adpscl_mode = 0;
GMUT_COEF4 = VD1_HDR2_GMUT_COEF4;
hdr_ctrl = VD1_HDR2_CTRL;
+ hdr_clk_gate = VD1_HDR2_CLK_GATE;
} else if (module_sel == VD2_HDR) {
MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = VD2_HDR2_GMUT_COEF4;
hdr_ctrl = VD2_HDR2_CTRL;
+ hdr_clk_gate = VD2_HDR2_CLK_GATE;
} else if (module_sel == OSD1_HDR) {
MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = OSD1_HDR2_GMUT_COEF4;
hdr_ctrl = OSD1_HDR2_CTRL;
+ hdr_clk_gate = OSD1_HDR2_CLK_GATE;
} else if (module_sel == DI_HDR) {
MATRIXI_COEF00_01 = DI_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = DI_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = DI_HDR2_GMUT_COEF4;
hdr_ctrl = DI_HDR2_CTRL;
+ /* hdr_clk_gate = DI_HDR2_CLK_GATE; */
} else if (module_sel == VDIN0_HDR) {
MATRIXI_COEF00_01 = VDIN0_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = VDIN0_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = VDIN0_HDR2_GMUT_COEF4;
hdr_ctrl = VDIN0_HDR2_CTRL;
+ /* hdr_clk_gate = VDIN0_HDR2_CLK_GATE; */
} else if (module_sel == VDIN1_HDR) {
MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = VDIN1_HDR2_GMUT_COEF4;
hdr_ctrl = VDIN1_HDR2_CTRL;
+ /* hdr_clk_gate = VDIN1_HDR2_CLK_GATE; */
}
if (hdr_mtx_param == NULL)
return;
+ /* need change clock gate as freerun */
+ /* when mtx on directly, not rdma op */
+ /* Now only operate osd1/vd1/vd2 hdr core */
+ if (get_cpu_type() <= MESON_CPU_MAJOR_ID_SC2) {
+ if (hdr_clk_gate != 0) {
+ cur_hdr_ctrl = READ_VPP_REG(hdr_ctrl);
+ if (hdr_mtx_param->mtx_on &&
+ !(cur_hdr_ctrl & (1 << 13))) {
+ WRITE_VPP_REG_BITS(hdr_clk_gate, 0xaaa, 0, 12);
+ VSYNC_WR_MPEG_REG_BITS(hdr_clk_gate, 0xaaa,
+ 0, 12);
+ }
+ }
+ }
+
VSYNC_WR_MPEG_REG_BITS(hdr_ctrl,
- hdr_mtx_param->mtx_on, 13, 1);
+ hdr_mtx_param->mtx_on, 13, 1);
+
+ /* recover the clock gate as auto gate by rdma op when mtx off */
+ /* Now only operate osd1/vd1/vd2 hdr core */
+ if (get_cpu_type() <= MESON_CPU_MAJOR_ID_SC2) {
+ if (hdr_clk_gate != 0 && !hdr_mtx_param->mtx_on)
+ VSYNC_WR_MPEG_REG_BITS(hdr_clk_gate, 0, 0, 12);
+ }
if (mtx_sel == HDR_IN_MTX) {
for (i = 0; i < MTX_NUM_PARAM; i++)
static int __init tsync_module_init(void)
{
int r;
+ int chip = -1;
r = class_register(&tsync_class);
video_pid_valid = 0;
demux_pcrscr_valid = 0;
- if (get_cpu_type() == MESON_CPU_MAJOR_ID_SC2)
+ chip = get_cpu_type();
+ if (chip == MESON_CPU_MAJOR_ID_SC2 ||
+ chip == MESON_CPU_MAJOR_ID_S4 ||
+ chip == MESON_CPU_MAJOR_ID_T7)
new_arch = true;
else
new_arch = false;
} else {
tsync_get_demux_pcr(&cur_pcr);
cur_checkin_vpts = get_last_checkin_pts(PTS_TYPE_VIDEO);
- if ((abs(cur_pcr - cur_checkin_vpts) >
+ if (cur_checkin_vpts != 0xffffffff &&
+ (abs(cur_pcr - cur_checkin_vpts) >
PLAY_PCR_INVALID_THRESHOLD) &&
(tsync_pcr_inited_flag & complete_init_flag) &&
tsync_get_new_arch())
u32 osd_v_skip[HW_OSD_COUNT];
u32 secure_enable[HW_OSD_COUNT];
u32 secure_src;
- u32 rdma_delayed_cnt;
+ u32 rdma_delayed_cnt1;
+ u32 rdma_delayed_cnt2;
+ u32 rdma_delayed_cnt3;
u32 osd_reg_check;
u32 fb_mem_free[HW_OSD_COUNT];
struct hw_debug_s osd_debug;
struct device_attribute *attr,
char *buf)
{
- return snprintf(buf, PAGE_SIZE, "%d\n",
- osd_hw.rdma_delayed_cnt);
+ return snprintf(buf, PAGE_SIZE, "%d, %d, %d\n",
+ osd_hw.rdma_delayed_cnt1,
+ osd_hw.rdma_delayed_cnt2,
+ osd_hw.rdma_delayed_cnt3);
}
static ssize_t show_osd_reg_check(struct device *device,
static int vsync_enter_line_max;
static int vsync_exit_line_max;
-static int line_threshold = 90;
+static int line_threshold = 5;
+static int line_threshold_2 = 90;
static int vsync_threshold = 10;
static int vsync_adjust_hit;
MODULE_PARM_DESC(vsync_enter_line_max, "\n vsync_enter_line_max\n");
module_param(vsync_exit_line_max, uint, 0664);
MODULE_PARM_DESC(line_threshold, "\n line_threshold\n");
module_param(line_threshold, uint, 0664);
+MODULE_PARM_DESC(line_threshold_2, "\n line_threshold_2\n");
+module_param(line_threshold_2, uint, 0664);
MODULE_PARM_DESC(vsync_threshold, "\n vsync_threshold\n");
module_param(vsync_threshold, uint, 0664);
MODULE_PARM_DESC(vsync_adjust_hit, "\n vsync_adjust_hit\n");
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM
static bool osd_hdr_on;
#endif
+static bool is_encp(u32 viu_type)
+{
+ u32 viu = VIU1;
+ bool ret = false;
+
+ if (viu_type == VIU1)
+ viu = osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3;
+ else if (viu_type == VIU2)
+ viu = (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) >> 2) & 0x3;
+ if (viu == 2)
+ /* encpi case, for 1080i */
+ ret = true;
+ /* for cvbs is enci */
+ return ret;
+}
static int get_active_begin_line(u32 viu_type)
{
osd_hw.osd_meson_dev.dummy_data | alpha);
}
+static u32 is_scaler_interlaced(u32 index)
+{
+ u32 output_index = 0;
+ u32 osd_sc_interlaced;
+
+ output_index = get_output_device_id(index);
+ if (osd_hw.osd_meson_dev.osd0_sc_independ) {
+ osd_sc_interlaced = osd_hw.field_out_en[output_index];
+ } else {
+ if (index == OSD1)
+ osd_sc_interlaced = osd_hw.field_out_en[output_index];
+ else
+ osd_sc_interlaced = 0;
+ }
+ return osd_sc_interlaced;
+}
+
static void osd_update_disp_freescale_enable(u32 index)
{
u64 hf_phase_step, vf_phase_step;
}
#ifdef NEW_PPS_PHASE
- if (osd_hw.field_out_en[output_index]) {
+ if (is_scaler_interlaced(index)) {
struct osd_f2v_vphase_s vphase;
f2v_get_vertical_phase(
bot_ini_phase = 0;
}
#else
- if (osd_hw.field_out_en[output_index]) /* interface output */
+ if (is_scaler_interlaced(index)) /* interface output */
bot_ini_phase = ((vf_phase_step / 2) >> 4);
else
bot_ini_phase = 0;
data32 = 0x0;
if (shift_workaround) {
vsc_ini_rcv_num++;
- if (osd_hw.field_out_en[output_index])
+ if (is_scaler_interlaced(index))
vsc_bot_rcv_num++;
}
data32 |= (vf_bank_len & 0x7)
| ((vsc_ini_rcv_num & 0xf) << 3)
| ((vsc_ini_rpt_p0_num & 0x3) << 8);
- if (osd_hw.field_out_en[output_index])
+ if (is_scaler_interlaced(index))
data32 |= ((vsc_bot_rcv_num & 0xf) << 11)
| ((vsc_bot_rpt_p0_num & 0x3) << 16)
| (1 << 23);
data32 = top_ini_phase;
if (osd_hw.free_scale_enable[index]) {
data32 |= (bot_ini_phase & 0xffff) << 16;
- if (osd_hw.field_out_en[output_index]) {
+ if (is_scaler_interlaced(index)) {
if (shift_workaround)
src_h--;
if (src_h == dst_h * 2)
int line1;
int line2;
int active_begin_line;
- int vinfo_height;
u32 val, wait_cnt = 0;
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
u32 secure_src = 0;
#endif
+ u32 total_line;
+
blending = &osd_blending;
blend_reg = &(blending->blend_reg);
active_begin_line = get_active_begin_line(VIU1);
line1 = get_enter_encp_line(VIU1);
/* if nearly vsync signal, wait vsync here */
- vinfo_height = osd_hw.field_out_en[output_index] ?
- (osd_hw.vinfo_height[output_index] * 2) :
- osd_hw.vinfo_height[output_index];
- while (line1 >= vinfo_height + active_begin_line *
+ if (osd_hw.field_out_en[VIU1] && is_encp(VIU1)) {
+ total_line = osd_hw.vinfo_height[VIU1] + active_begin_line;
+ if (line1 >= total_line)
+ /* bottom*/
+ line1 -= total_line;
+ } else {
+ total_line = osd_hw.vinfo_height[VIU1] + active_begin_line;
+ }
+
+ while (line1 >= total_line *
(100 - line_threshold) / 100 ||
- line1 <= active_begin_line * line_threshold / 100) {
- osd_log_dbg(MODULE_RENDER,
- "enter osd_setting_order:encp line=%d\n",
- line1);
+ line1 <= active_begin_line * line_threshold_2 / 100) {
/* 0.5ms */
usleep_range(500, 600);
wait_cnt++;
line1 = get_enter_encp_line(VIU1);
}
if (wait_cnt > 0)
- osd_hw.rdma_delayed_cnt++;
+ osd_hw.rdma_delayed_cnt1++;
spin_lock_irqsave(&osd_lock, lock_flags);
if (blending->osd1_freescale_disable)
osd_hw.reg[DISP_FREESCALE_ENABLE].update_func(OSD1);
VSYNCOSD_WR_MPEG_REG(RDMA_DETECT_REG, rdma_dt_cnt);
spin_unlock_irqrestore(&osd_lock, lock_flags);
line2 = get_exit_encp_line(VIU1);
- osd_log_dbg2(MODULE_RENDER,
- "enter osd_setting_order:encp line=%d\n",
- line2);
+ osd_log_dbg(MODULE_RENDER,
+ "osd_setting_order:encp line1=%d, line2=%d, total_line=%d\n",
+ line1, line2, total_line);
osd_wait_vsync_hw_viu1();
val = osd_reg_read(RDMA_DETECT_REG);
+ if (line2 < line1) {
+ osd_hw.rdma_delayed_cnt3++;
+ osd_log_dbg(MODULE_ENCP_STAT, "osd line stat %d,%d, rdma_delayed_cnt3=%d\n",
+ line1, line2, osd_hw.rdma_delayed_cnt3);
+ }
/* if missed, need wait vsync */
if (/*(line2 < line1) || */(val != rdma_dt_cnt)) {
osd_wait_vsync_hw_viu1();
- osd_hw.rdma_delayed_cnt++;
- osd_log_dbg(MODULE_RENDER, "osd line %d,%d\n", line1, line2);
+ osd_hw.rdma_delayed_cnt2++;
+ osd_log_dbg(MODULE_ENCP_STAT, "osd line stat %d,%d val=0x%x, rdma_dt_cnt=0x%x\n",
+ line1, line2, val, rdma_dt_cnt);
}
return 0;
}
void osd_suspend_hw(void)
{
+ wait_vsync_wakeup();
+ wait_vsync_wakeup_viu2();
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL) {
osd_hw.reg_status_save =
osd_reg_read(VPP_MISC) & OSD_RELATIVE_BITS;
void osd_shutdown_hw(void)
{
+ wait_vsync_wakeup();
+ wait_vsync_wakeup_viu2();
#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
if (osd_hw.osd_meson_dev.has_rdma)
enable_rdma(0);
#define MODULE_CURSOR BIT(4)
#define MODULE_VIU2 BIT(5)
#define MODULE_SECURE BIT(6)
+#define MODULE_ENCP_STAT BIT(7)
extern unsigned int osd_log_level;
extern unsigned int osd_log_module;
return -1;
}
aml_pr_info(0, "reserved memory config fail , use CMA.\n");
+ /* display buf0 + display buf1 + input process buf (for ge2d)
+ * 1: output_format_mode == 1 (output is yuv444)
+ * 24M + 24M + 24M = 72M
+ * 2: output_format_mode == 0 (output is nv12),
+ * 16M + 16M + 24M = 56M
+ */
if (picdec_device.output_format_mode) {
if (picdec_device.cma_mode == 0) {
picdec_device.cma_pages =
picdec_device.cma_pages =
dma_alloc_from_contiguous(
&(picdec_device.pdev->dev),
- (48*SZ_1M) >> PAGE_SHIFT, 0);
+ (56 * SZ_1M) >> PAGE_SHIFT, 0);
picdec_device.buffer_start = page_to_phys(
picdec_device.cma_pages);
- picdec_device.buffer_size = (48*SZ_1M);
+ picdec_device.buffer_size = (56 * SZ_1M);
} else{
flags = CODEC_MM_FLAGS_DMA |
CODEC_MM_FLAGS_CMA_CLEAR;
picdec_device.buffer_start =
codec_mm_alloc_for_dma("picdec",
- (48*SZ_1M)/PAGE_SIZE, 0, flags);
- picdec_device.buffer_size = (48*SZ_1M);
+ (56 * SZ_1M) / PAGE_SIZE, 0, flags);
+ picdec_device.buffer_size = (56 * SZ_1M);
}
}
dma_release_from_contiguous(
&picdec_device.pdev->dev,
picdec_device.cma_pages,
- (48*SZ_1M) >> PAGE_SHIFT);
+ (56 * SZ_1M) >> PAGE_SHIFT);
picdec_device.cma_pages = NULL;
}
} else {
ret = picdec_start();
priv->context = NULL;
priv->phyaddr = (unsigned long)picdec_device.assit_buf_start;
- priv->buf_len = (picdec_device.buffer_size/3);
+ priv->buf_len = 24 * SZ_1M; /* max size is 3840*2160*3 (24M) */
file->private_data = priv;
}
return ret;
static unsigned int video_nr_base = 30;
static unsigned int n_devs = 9;
+#define N_DEVS 9
static unsigned int v4lvideo_debug;
-static unsigned int get_count;
-static unsigned int put_count;
-static unsigned int q_count;
-static unsigned int dq_count;
+static unsigned int get_count[N_DEVS];
+static unsigned int put_count[N_DEVS];
+static unsigned int q_count[N_DEVS];
+static unsigned int dq_count[N_DEVS];
static unsigned int cts_use_di;
/*set 1 means video_composer use dec vf when di NR; only debug!!!*/
static unsigned int render_use_dec;
static unsigned int link_fd_count;
static unsigned int link_put_fd_count;
static unsigned int v4lvideo_version = 2;
+static unsigned int total_get_count[N_DEVS];
+static unsigned int total_put_count[N_DEVS];
+static unsigned int total_release_count[N_DEVS];
+static unsigned int inactive_check_disp;
bool di_bypass_p;
/*dec set count mutex*/
static const struct file_operations v4lvideo_file_fops;
+static u32 print_flag;
+
+#define PRINT_ERROR 0X0
+#define PRINT_QUEUE_STATUS 0X0001
+#define PRINT_COUNT 0X0002
+#define PRINT_OTHER 0X0040
+
+int v4l_print(int index, int debug_flag, const char *fmt, ...)
+{
+ if ((print_flag & debug_flag) ||
+ (debug_flag == PRINT_ERROR)) {
+ unsigned char buf[256];
+ int len = 0;
+ va_list args;
+
+ va_start(args, fmt);
+ len = sprintf(buf, "v4lvideo:[%d]", index);
+ vsnprintf(buf + len, 256 - len, fmt, args);
+ pr_info("%s", buf);
+ va_end(args);
+ }
+ return 0;
+}
+
void v4lvideo_dec_count_increase(void)
{
mutex_lock(&mutex_dec_count);
codec_mm_keeper_unmask_keeper(keep_id, delayms);
}
-static void vf_keep(struct v4lvideo_file_s *v4lvideo_file,
+static void vf_keep(struct v4lvideo_dev *dev,
+ struct v4lvideo_file_s *v4lvideo_file,
struct file_private_data *file_private_data)
{
struct vframe_s *vf_p;
int type = MEM_TYPE_CODEC_MM;
int keep_id = 0;
int keep_head_id = 0;
+ u32 flag;
+ u32 inst_id = dev->inst;
if (!file_private_data) {
V4LVID_ERR("vf_keep error: file_private_data is NULL");
vf_p = file_private_data->vf_p;
if (!vf_p || (vf_p != v4lvideo_file->vf_p)) {
- pr_info("v4lvideo: maybe file has been released\n");
- v4lvideo_file->free_before_unreg = true;
+ v4l_print(dev->inst, PRINT_ERROR,
+ "maybe file has been released\n");
+ mutex_lock(&dev->mutex_opened);
+ if (dev->opened) {
+ mutex_unlock(&dev->mutex_opened);
+ v4lvideo_file->free_before_unreg = true;
+ } else {
+ mutex_unlock(&dev->mutex_opened);
+ v4l_print(dev->inst, PRINT_ERROR,
+ "vf keep: device has beed closed\n");
+ flag = v4lvideo_file->flag;
+ if (flag & V4LVIDEO_FLAG_DI_DEC)
+ v4l_print(dev->inst, PRINT_ERROR,
+ "vf keep shold not here");
+ if (v4lvideo_file->vf_type & VIDTYPE_DI_PW) {
+ vf_p = v4lvideo_file->vf_p;
+ dim_post_keep_cmd_release2(vf_p);
+ total_release_count[inst_id]++;
+ }
+ }
return;
}
struct vframe_s *vf_p;
struct vframe_s *vf;
u32 flag;
+ u32 inst_id;
+
+ inst_id = file_private_data->v4l_inst_id;
if (file_private_data->keep_id > 0) {
video_keeper_free_mem(
file_private_data->keep_id, 0);
vf_p = file_private_data->vf_ext_p;
}
- if (vf->type & VIDTYPE_DI_PW)
+ if (vf->type & VIDTYPE_DI_PW) {
dim_post_keep_cmd_release2(vf_p);
+ total_release_count[inst_id]++;
+ v4l_print(inst_id, PRINT_COUNT,
+ "di release1 get=%d, put=%d, release=%d\n",
+ total_get_count[inst_id], total_put_count[inst_id],
+ total_release_count[inst_id]);
+ }
}
static void vf_free_force(struct v4lvideo_file_s *v4lvideo_file)
{
struct vframe_s *vf_p;
u32 flag;
+ u32 inst_id;
+ inst_id = v4lvideo_file->inst_id;
vf_p = v4lvideo_file->vf_p;
flag = v4lvideo_file->flag;
if (flag & V4LVIDEO_FLAG_DI_DEC)
vf_p = v4lvideo_file->vf_ext_p;
- if (v4lvideo_file->vf_type & VIDTYPE_DI_PW)
+ if (v4lvideo_file->vf_type & VIDTYPE_DI_PW) {
dim_post_keep_cmd_release2(vf_p);
+ total_release_count[inst_id]++;
+ v4l_print(inst_id, PRINT_COUNT,
+ "di release2 get=%d, put=%d, release=%d\n",
+ total_get_count[inst_id], total_put_count[inst_id],
+ total_release_count[inst_id]);
+ }
}
void init_file_private_data(struct file_private_data *file_private_data)
//dprintk(dev, 2, "vidioc_open\n");
V4LVID_DBG("v4lvideo open\n");
+ mutex_lock(&dev->mutex_opened);
+ dev->opened = true;
+ mutex_unlock(&dev->mutex_opened);
+ v4l_print(dev->inst, PRINT_COUNT, "open\n");
return 0;
}
{
struct v4lvideo_dev *dev = video_drvdata(file);
int i;
+ u32 inst_id = dev->inst;
V4LVID_DBG("vidioc_close!!!!\n");
if (dev->mapped)
if (dev->fd_num > 0)
dev->fd_num--;
+ mutex_lock(&dev->mutex_opened);
+ dev->opened = false;
+ mutex_unlock(&dev->mutex_opened);
+
+ v4l_print(dev->inst, PRINT_COUNT,
+ "close get=%d, put=%d, release=%d, %d\n",
+ total_get_count[inst_id], total_put_count[inst_id],
+ total_release_count[inst_id],
+ total_get_count[inst_id] - total_put_count[inst_id]
+ - total_release_count[inst_id]);
+
return 0;
}
dev->v4lvideo_file[i].vf_ext_p = file_private_data->vf_ext_p;
dev->v4lvideo_file[i].flag = file_private_data->flag;
dev->v4lvideo_file[i].vf_type = file_private_data->vf_p->type;
+ dev->v4lvideo_file[i].inst_id = file_private_data->v4l_inst_id;
v4l2q_push(&dev->display_queue, &dev->v4lvideo_file[i]);
}
struct file_private_data *file_private_data = NULL;
u32 flag;
struct v4lvideo_file_s *v4lvideo_file;
+ u32 inst_id = dev->inst;
dev->v4lvideo_input[p->index] = *p;
- q_count++;
+ q_count[inst_id]++;
file_vf = fget(p->m.fd);
if (!file_vf) {
pr_err("v4lvideo: qbuf fget fail\n");
if (dev->receiver_register) {
if (flag & V4LVIDEO_FLAG_DI_DEC)
vf_p = vf_ext_p;
+ if (vf_p->type & VIDTYPE_DI_PW)
+ total_put_count[inst_id]++;
vf_put(vf_p, dev->vf_receiver_name);
- put_count++;
+ put_count[inst_id]++;
} else {
vf_free(file_private_data);
pr_err("vidioc_qbuf: vfm is unreg\n");
}
} else {
pr_err("vidioc_qbuf: maybe in unreg\n");
+ if (v4lvideo_file->vf_type & VIDTYPE_DI_PW) {
+ dim_post_keep_cmd_release2(vf_p);
+ total_release_count[inst_id]++;
+ v4l_print(inst_id, PRINT_COUNT,
+ "qbuf: get=%d, put=%d, release=%d\n",
+ total_get_count[inst_id],
+ total_put_count[inst_id],
+ total_release_count[inst_id]);
+ }
}
}
} else {
u64 pts_tmp;
char *provider_name = NULL;
struct vframe_s *vf_ext = NULL;
+ u32 inst_id = dev->inst;
mutex_lock(&dev->mutex_input);
buf = v4l2q_peek(&dev->input_queue);
mutex_unlock(&dev->mutex_input);
return -EAGAIN;
}
+ if (vf->type & VIDTYPE_DI_PW)
+ total_get_count[inst_id]++;
+
if (vf->type & VIDTYPE_V4L_EOS) {
vf_put(vf, dev->vf_receiver_name);
mutex_unlock(&dev->mutex_input);
- put_count++;
+ put_count[inst_id]++;
+ total_put_count[inst_id]++;
return -EAGAIN;
}
+
if (!dev->provider_name) {
provider_name = vf_get_provider_name(
dev->vf_receiver_name);
dev->provider_name ? dev->provider_name : "NULL");
}
- get_count++;
+ get_count[inst_id]++;
vf->omx_index = dev->frame_num;
dev->am_parm.signal_type = vf->signal_type;
dev->am_parm.master_display_colour
}
buf = v4l2q_pop(&dev->input_queue);
+ if (!buf) {
+ dprintk(dev, 0, "pop buf is NULL\n");
+ put_count[inst_id]++;
+ if (vf->type & VIDTYPE_DI_PW)
+ total_put_count[inst_id]++;
+ vf_put(vf, dev->vf_receiver_name);
+ mutex_unlock(&dev->mutex_input);
+ return -EAGAIN;
+ }
dev->vf_wait_cnt = 0;
file_vf = fget(buf->m.fd);
if (!file_vf) {
file_private_data = v4lvideo_get_file_private_data(file_vf, false);
if (!file_private_data) {
+ put_count[inst_id]++;
+ if (vf->type & VIDTYPE_DI_PW)
+ total_put_count[inst_id]++;
+ vf_put(vf, dev->vf_receiver_name);
mutex_unlock(&dev->mutex_input);
fput(file_vf);
pr_err("v4lvideo: file_private_data NULL\n");
file_private_data->vf.src_fmt.md_buf = file_private_data->md.p_md;
file_private_data->vf.src_fmt.comp_buf = file_private_data->md.p_comp;
-
+ file_private_data->v4l_inst_id = dev->inst;
v4lvideo_import_sei_data(
vf, &file_private_data->vf,
dev->provider_name);
}
p->sequence = dev->frame_num++;
//pr_err("dqbuf: frame_num=%d\n", p->sequence);
- dq_count++;
+ dq_count[inst_id]++;
return 0;
}
struct v4lvideo_dev *dev = (struct v4lvideo_dev *)private_data;
struct file_private_data *file_private_data = NULL;
struct v4lvideo_file_s *v4lvideo_file;
+ u32 inst_id = dev->inst;
if (type == VFRAME_EVENT_PROVIDER_UNREG) {
mutex_lock(&dev->mutex_input);
return 0;
}
file_private_data = v4lvideo_file->private_data_p;
- vf_keep(v4lvideo_file, file_private_data);
+ vf_keep(dev, v4lvideo_file, file_private_data);
/*pr_err("unreg:v4lvideo, keep last frame\n");*/
}
mutex_unlock(&dev->mutex_input);
pr_err("unreg:v4lvideo\n");
+ v4l_print(dev->inst, PRINT_COUNT,
+ "unreg get=%d, put=%d, release=%d\n",
+ total_get_count[inst_id], total_put_count[inst_id],
+ total_release_count[inst_id]);
} else if (type == VFRAME_EVENT_PROVIDER_REG) {
mutex_lock(&dev->mutex_input);
v4l2q_init(&dev->display_queue,
dev->first_frame = 0;
dev->last_pts_us64 = U64_MAX;
mutex_unlock(&dev->mutex_input);
- get_count = 0;
- put_count = 0;
- q_count = 0;
- dq_count = 0;
+ get_count[inst_id] = 0;
+ put_count[inst_id] = 0;
+ q_count[inst_id] = 0;
+ dq_count[inst_id] = 0;
pr_err("reg:v4lvideo\n");
} else if (type == VFRAME_EVENT_PROVIDER_QUREY_STATE) {
- if ((dev->vf_wait_cnt > 1) && v4l2q_empty(&dev->display_queue))
- return RECEIVER_INACTIVE;
+ if (dev->vf_wait_cnt > 1) {
+ if (!inactive_check_disp)
+ return RECEIVER_INACTIVE;
+ else if (v4l2q_empty(&dev->display_queue))
+ return RECEIVER_INACTIVE;
+ }
return RECEIVER_ACTIVE;
}
return 0;
v4lvideo_devlist_unlock(flags);
mutex_init(&dev->mutex_input);
+ mutex_init(&dev->mutex_opened);
return 0;
static ssize_t get_count_show(struct class *class,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "get_count: %d\n", get_count);
+ return sprintf(buf, "get_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ get_count[0], get_count[1], get_count[2],
+ get_count[3], get_count[4], get_count[5],
+ get_count[6], get_count[7], get_count[8]);
}
static ssize_t get_count_store(struct class *class,
{
ssize_t r;
int val;
+ int i;
r = kstrtoint(buf, 0, &val);
if (r < 0)
return -EINVAL;
- if (val > 0)
- get_count = val;
- else
- get_count = 0;
+ for (i = 0; i < N_DEVS; i++) {
+ if (val > 0)
+ get_count[i] = val;
+ else
+ get_count[i] = 0;
+ }
return count;
}
static ssize_t put_count_show(struct class *class,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "put_count: %d\n", put_count);
+ return sprintf(buf, "put_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ put_count[0], put_count[1], put_count[2],
+ put_count[3], put_count[4], put_count[5],
+ put_count[6], put_count[7], put_count[8]);
+
}
static ssize_t put_count_store(struct class *class,
{
ssize_t r;
int val;
+ int i;
r = kstrtoint(buf, 0, &val);
if (r < 0)
return -EINVAL;
- if (val > 0)
- put_count = val;
- else
- put_count = 0;
+ for (i = 0; i < N_DEVS; i++) {
+ if (val > 0)
+ put_count[i] = val;
+ else
+ put_count[i] = 0;
+ }
return count;
}
static ssize_t q_count_show(struct class *class,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "q_count: %d\n", q_count);
+ return sprintf(buf, "q_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ q_count[0], q_count[1], q_count[2],
+ q_count[3], q_count[4], q_count[5],
+ q_count[6], q_count[7], q_count[8]);
+
}
static ssize_t q_count_store(struct class *class,
{
ssize_t r;
int val;
+ int i;
r = kstrtoint(buf, 0, &val);
if (r < 0)
return -EINVAL;
- if (val > 0)
- q_count = val;
- else
- q_count = 0;
+ for (i = 0; i < N_DEVS; i++) {
+ if (val > 0)
+ q_count[i] = val;
+ else
+ q_count[i] = 0;
+ }
return count;
}
static ssize_t dq_count_show(struct class *class,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "dq_count: %d\n", dq_count);
+ return sprintf(buf, "dq_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ dq_count[0], dq_count[1], dq_count[2],
+ dq_count[3], dq_count[4], dq_count[5],
+ dq_count[6], dq_count[7], dq_count[8]);
}
static ssize_t dq_count_store(struct class *class,
{
ssize_t r;
int val;
+ int i;
r = kstrtoint(buf, 0, &val);
if (r < 0)
return -EINVAL;
- if (val > 0)
- dq_count = val;
- else
- dq_count = 0;
+ for (i = 0; i < N_DEVS; i++) {
+ if (val > 0)
+ dq_count[i] = val;
+ else
+ dq_count[i] = 0;
+ }
return count;
}
return count;
}
+static ssize_t print_flag_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "print_flag: %d\n", print_flag);
+}
+
+static ssize_t print_flag_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ ssize_t r;
+ int val;
+
+ r = kstrtoint(buf, 0, &val);
+ if (r < 0)
+ return -EINVAL;
+
+ if (val > 0)
+ print_flag = val;
+ else
+ print_flag = 0;
+ return count;
+}
+
+static ssize_t inactive_check_disp_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "inactive_check_disp: %d\n", inactive_check_disp);
+}
+
+static ssize_t inactive_check_disp_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ ssize_t r;
+ int val;
+
+ r = kstrtoint(buf, 0, &val);
+ if (r < 0)
+ return -EINVAL;
+
+ if (val > 0)
+ inactive_check_disp = val;
+ else
+ inactive_check_disp = 0;
+ return count;
+}
+
+static ssize_t total_get_count_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "total_get_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ total_get_count[0], total_get_count[1], total_get_count[2],
+ total_get_count[3], total_get_count[4], total_get_count[5],
+ total_get_count[6], total_get_count[7], total_get_count[8]);
+
+}
+
+static ssize_t total_put_count_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "total_put_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ total_put_count[0], total_put_count[1], total_put_count[2],
+ total_put_count[3], total_put_count[4], total_put_count[5],
+ total_put_count[6], total_put_count[7], total_put_count[8]);
+
+}
+
+static ssize_t total_release_count_show(struct class *class,
+ struct class_attribute *attr, char *buf)
+{
+ return sprintf(buf, "total_release_count: %d,%d,%d,%d,%d,%d,%d,%d,%d\n",
+ total_release_count[0], total_release_count[1],
+ total_release_count[2], total_release_count[3],
+ total_release_count[4], total_release_count[5],
+ total_release_count[6], total_release_count[7],
+ total_release_count[8]);
+}
+
static struct class_attribute v4lvideo_class_attrs[] = {
__ATTR(sei_cnt,
0664,
0664,
vf_dump_show,
vf_dump_store),
+ __ATTR(print_flag,
+ 0664,
+ print_flag_show,
+ print_flag_store),
+ __ATTR(inactive_check_disp,
+ 0664,
+ inactive_check_disp_show,
+ inactive_check_disp_store),
__ATTR_RO(open_fd_count),
__ATTR_RO(release_fd_count),
__ATTR_RO(link_fd_count),
__ATTR_RO(link_put_fd_count),
__ATTR_RO(v4lvideo_version),
+ __ATTR_RO(total_get_count),
+ __ATTR_RO(total_put_count),
+ __ATTR_RO(total_release_count),
__ATTR_NULL
};
u32 flag;
u32 vf_type;
bool free_before_unreg;
+ u32 inst_id;
};
struct v4lvideo_dev {
struct v4lvideo_file_s *v4lvideo_display_queue[V4LVIDEO_POOL_SIZE];
/* mutex_input */
struct mutex mutex_input;
+ /* mutex_opened */
+ struct mutex mutex_opened;
struct v4l2_buffer v4lvideo_input[V4LVIDEO_POOL_SIZE];
struct v4l2_amlogic_parm am_parm;
u8 first_frame;
char *provider_name;
struct v4lvideo_file_s v4lvideo_file[V4LVIDEO_POOL_SIZE];
+ bool opened;
};
enum vframe_source_type {
static u32 drop_cnt_pip;
static u32 receive_count;
static u32 receive_count_pip;
+static u32 total_get_count;
+static u32 total_put_count;
#define PRINT_ERROR 0X0
#define PRINT_QUEUE_STATUS 0X0001
current_count = current_frames->frames_info.frame_count;
for (i = 0; i < current_count; i++) {
file_vf = current_frames->file_vf[i];
- fput(file_vf);
+ if (file_vf) {
+ fput(file_vf);
+ total_put_count++;
+ dev->fput_count++;
+ } else {
+ vc_print(dev->index, PRINT_ERROR,
+ "put_file file_vf null!!!\n");
+ }
}
- dev->fput_count++;
}
static void vf_pop_display_q(struct composer_dev *dev, struct vframe_s *vf)
dis_vf->omx_index);
for (i = 0; i <= repeat_count; i++) {
fput(dis_vf->file_vf);
+ total_put_count++;
dev->fput_count++;
}
} else if (!(dis_vf->flag
repeat_count = dis_vf->repeat_count[dev->index];
for (i = 0; i <= repeat_count; i++) {
fput(dis_vf->file_vf);
+ total_put_count++;
dev->fput_count++;
}
}
if (!is_composer) {
for (i = 0; i <= repeat_count; i++) {
fput(file_vf);
+ total_put_count++;
dev->fput_count++;
}
} else {
frames_info->frame_info[j].composer_fen_fd = -1;
vc_print(dev->index, PRINT_ERROR,
"set frame but not enable\n");
+ return;
}
for (j = 0; j < frames_info->frame_count; j++) {
vc_print(dev->index, PRINT_ERROR, "fget fd fail\n");
return;
}
+ total_get_count++;
dev->received_frames[i].file_vf[j] = file_vf;
if (frames_info->frame_info[j].type == 0) {
if (is_valid_mod_type(file_vf->private_data,
if (!is_composer) {
for (i = 0; i <= repeat_count; i++) {
- if (file_vf)
+ if (file_vf) {
fput(file_vf);
- dev->fput_count++;
+ total_put_count++;
+ dev->fput_count++;
+ } else {
+ vc_print(dev->index, PRINT_ERROR,
+ "put: file_vf is NULL!!!\n");
+ }
}
} else {
videocom_vf_put(vf, dev);
return sprintf(buf, "%d\n", receive_count_pip);
}
+static ssize_t total_get_count_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ ssize_t r;
+ int val;
+
+ r = kstrtoint(buf, 0, &val);
+ if (r < 0)
+ return -EINVAL;
+
+ total_get_count = val;
+ pr_info("set total get count:%d\n", total_get_count);
+ return count;
+}
+
+static ssize_t total_get_count_show(struct class *class,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d\n", total_get_count);
+}
+
+static ssize_t total_put_count_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ ssize_t r;
+ int val;
+
+ r = kstrtoint(buf, 0, &val);
+ if (r < 0)
+ return -EINVAL;
+
+ total_put_count = val;
+ pr_info("set total put count:%d\n", total_put_count);
+ return count;
+}
+
+static ssize_t total_put_count_show(struct class *class,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d\n", total_put_count);
+}
+
static struct class_attribute video_composer_class_attrs[] = {
__ATTR(force_composer, 0664,
force_composer_show,
__ATTR(composer_use_444, 0664,
composer_use_444_show,
composer_use_444_store),
+ __ATTR(total_get_count, 0664,
+ total_get_count_show,
+ total_get_count_store),
+ __ATTR(total_put_count, 0664,
+ total_put_count_show,
+ total_put_count_store),
__ATTR_RO(drop_cnt),
__ATTR_RO(drop_cnt_pip),
__ATTR_RO(receive_count),
#define TRACE_INCLUDE_PATH .
#define TRACE_INCLUDE_FILE video_trace
#include <trace/define_trace.h>
+#ifdef CONFIG_AMLOGIC_MEDIA_MSYNC
+#include <uapi/linux/amlogic/msync.h>
+#endif
static int get_count;
static int get_di_count;
* >1000: speed*(vsync_slow_factor/1000000)
*/
static u32 vsync_slow_factor = 1;
+static int video_delay_val;
/* pts alignment */
static bool vsync_pts_aligned;
#else
if (smooth_sync_enable) {
org_vpts = timestamp_vpts_get();
- if ((abs(org_vpts + vsync_pts_inc - systime) <
- M_PTS_SMOOTH_MAX)
- && (abs(org_vpts + vsync_pts_inc - systime) >
- M_PTS_SMOOTH_MIN)) {
+ if ((abs(org_vpts + vsync_pts_inc + video_delay_val - systime) <
+ M_PTS_SMOOTH_MAX) &&
+ (abs(org_vpts + vsync_pts_inc + video_delay_val - systime)
+ > M_PTS_SMOOTH_MIN)) {
if (!video_frame_repeat_count) {
vpts_ref = org_vpts;
video_frame_repeat_count++;
}
- if ((int)(org_vpts + vsync_pts_inc - systime) > 0) {
+ if ((int)(org_vpts + vsync_pts_inc +
+ video_delay_val - systime) > 0) {
adjust_pts =
vpts_ref + (vsync_pts_inc -
M_PTS_SMOOTH_ADJUST) *
video_frame_repeat_count = 0;
}
}
+ if (video_delay_val && !omx_secret_mode) {
+ expired = ((int)(timestamp_pcrscr_get() +
+ vsync_pts_align - pts - video_delay_val)) >= 0;
+ return expired;
+ }
if (tsync_get_mode() == TSYNC_MODE_PCRMASTER)
expired = (timestamp_pcrscr_get() + vsync_pts_align >= pts) ?
true : false;
else
- expired = (int)(timestamp_pcrscr_get() +
- vsync_pts_align - pts) >= 0;
-
+ expired = ((int)(timestamp_pcrscr_get() +
+ vsync_pts_align - pts)) >= 0;
#ifdef PTS_THROTTLE
if (expired && next_vf && next_vf->next_vf_pts_valid &&
(vsync_slow_factor == 1) &&
}
#endif
-static enum vmode_e old_vmode = VMODE_MAX;
-static enum vmode_e new_vmode = VMODE_MAX;
+static char old_vmode[32];
+static char new_vmode[32];
static inline bool video_vf_disp_mode_check(struct vframe_s *vf)
{
struct provider_disp_mode_req_s req;
if (debug_flag & DEBUG_FLAG_VSYNC_DONONE)
return IRQ_HANDLED;
+#ifdef CONFIG_AMLOGIC_MEDIA_MSYNC
+ msync_vsync_update();
+#endif
+
if (cur_vd1_path_id == 0xff)
cur_vd1_path_id = vd1_path_id;
if (cur_vd2_path_id == 0xff)
/* vout mode detection under old tunnel mode */
if ((vf) && ((vf->type & VIDTYPE_NO_VIDEO_ENABLE) == 0)) {
- if (old_vmode != new_vmode) {
+ if (strcmp(old_vmode, new_vmode)) {
vd_layer[0].property_changed = true;
vd_layer[1].property_changed = true;
pr_info("detect vout mode change!!!!!!!!!!!!\n");
- old_vmode = new_vmode;
+ strcpy(old_vmode, new_vmode);
}
}
toggle_cnt = 0;
(cur_dispbuf, vf,
frame_repeat_count
* vsync_pts_inc) &&
- timestamp_pcrscr_enable_state()) {
+ ((timestamp_pcrscr_enable_state() ||
+ tsync_get_mode() ==
+ TSYNC_MODE_PCRMASTER))) {
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
int iret1 = 0, iret2 = 0;
#endif
/* vout mode detection under new non-tunnel mode */
if (vd_layer[0].dispbuf || vd_layer[1].dispbuf) {
- if (old_vmode != new_vmode) {
+ if (strcmp(old_vmode, new_vmode)) {
vd_layer[0].property_changed = true;
vd_layer[1].property_changed = true;
pr_info("detect vout mode change!!!!!!!!!!!!\n");
- old_vmode = new_vmode;
+ strcpy(old_vmode, new_vmode);
}
}
#define signal_color_primaries ((vf->signal_type >> 16) & 0xff)
#define signal_transfer_characteristic ((vf->signal_type >> 8) & 0xff)
-#define DV_SEI 0x01000000
-#define HDR10P 0x02000000
-
static int check_media_sei(char *sei, u32 sei_size, u32 sei_type)
{
int ret = 0;
type = (type << 8) | *p++;
type = (type << 8) | *p++;
- if (type == sei_type) {
+ if (((sei_type == DV_SEI || sei_type == HDR10P) &&
+ sei_type == type) ||
+ (sei_type == DV_AV1_SEI &&
+ sei_type == (type & 0xffff0000))) {
ret = 1;
break;
}
if (!vf)
return -1;
- /* invaild src fmt case */
+ /* invalid src fmt case */
if (vf->src_fmt.sei_magic_code != SEI_MAGIC_CODE)
return -1;
int src_fmt = -1;
int ret = 0;
#endif
+ int i;
+ char *p;
if (!vf)
return -1;
vf->src_fmt.sei_ptr = sei;
vf->src_fmt.sei_size = size;
vf->src_fmt.dual_layer = false;
+ if (debug_flag & DEBUG_FLAG_OMX_DV_DROP_FRAME) {
+ pr_info("===update vf %p, sei %p, size %d, dual_layer %d===\n",
+ vf, sei, size, dual_layer);
+ if (sei && size > 15) {
+ p = (char *)sei;
+ for (i = 0; i < size; i += 16)
+ pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+ p[i],
+ p[i + 1],
+ p[i + 2],
+ p[i + 3],
+ p[i + 4],
+ p[i + 5],
+ p[i + 6],
+ p[i + 7],
+ p[i + 8],
+ p[i + 9],
+ p[i + 10],
+ p[i + 11],
+ p[i + 12],
+ p[i + 13],
+ p[i + 14],
+ p[i + 15]);
+ }
+ }
if (vf->type & VIDTYPE_MVC) {
vf->src_fmt.fmt = VFRAME_SIGNAL_FMT_MVC;
if (vf->discard_dv_data) {
if (debug_flag & DEBUG_FLAG_OMX_DV_DROP_FRAME)
pr_info("ignore nonstandard dv\n");
- } else if (dual_layer || check_media_sei(sei, size, DV_SEI)) {
+ } else if (dual_layer || check_media_sei(sei, size, DV_SEI) ||
+ check_media_sei(sei, size, DV_AV1_SEI)) {
vf->src_fmt.fmt = VFRAME_SIGNAL_FMT_DOVI;
vf->src_fmt.dual_layer = dual_layer;
#if PARSE_MD_IN_ADVANCE
if (vf->src_fmt.md_buf && vf->src_fmt.comp_buf) {
if (debug_flag & DEBUG_FLAG_OMX_DV_DROP_FRAME)
- pr_info("parse vf %p, sei %p, size %d\n",
- vf, sei, size);
+ pr_info("parse vf %p, sei %p, size %d, md_buf %p\n",
+ vf, sei, size,
+ vf->src_fmt.md_buf);
ret = parse_sei_and_meta_ext
(vf, sei, size,
&vf->src_fmt.comp_size,
{
struct disp_info_s *layer = &glayer_info[0];
static const char * const wide_str[] = {
- "normal", "full stretch", "4-3", "16-9", "non-linear",
+ "normal", "full stretch", "4-3", "16-9", "non-linear-V",
"normal-noscaleup",
"4-3 ignore", "4-3 letter box", "4-3 pan scan", "4-3 combined",
"16-9 ignore", "16-9 letter box", "16-9 pan scan",
- "16-9 combined", "Custom AR", "AFD"
+ "16-9 combined", "Custom AR", "AFD", "non-linear-T"
};
if (layer->wide_mode < ARRAY_SIZE(wide_str)) {
return count;
}
+static ssize_t video_videodelay_store(struct class *class,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ int r;
+ int value;
+
+ r = kstrtoint(buf, 0, &value);
+ if (r < 0)
+ return -EINVAL;
+
+ video_delay_val = value * 90;
+
+ return count;
+}
+
+static ssize_t video_videodelay_show(struct class *cla,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d(%dms)\n", video_delay_val,
+ video_delay_val / 90);
+}
+
#ifdef PTS_TRACE_DEBUG
static ssize_t pts_trace_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
return sprintf(buf, "0x%x\n", test_screen);
}
+
+/* [24] Flag: enable/disable auto background color */
+/* [23:16] Y */
+/* [15: 8] Cb */
+/* [ 7: 0] Cr */
+static ssize_t video_background_show(struct class *cla,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "channel_bg(0x%x) no_channel_bg(0x%x)\n",
+ vd_layer[0].video_en_bg_color,
+ vd_layer[0].video_dis_bg_color);
+}
+
static ssize_t video_rgb_screen_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
return count;
}
+/* [24] Flag: enable/disable auto background color */
+/* [23:16] Y */
+/* [15: 8] Cb */
+/* [ 7: 0] Cr */
+static ssize_t video_background_store(struct class *cla,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ int parsed[2];
+
+ if (likely(parse_para(buf, 2, parsed) == 2)) {
+ pr_info("video bg color, channel(0x%x) no_channel(0x%x)\n",
+ parsed[0], parsed[1]);
+ vd_layer[0].video_en_bg_color = parsed[0];
+ vd_layer[0].video_dis_bg_color = parsed[1];
+ } else {
+ pr_err("video_background: wrong input params\n");
+ return -EINVAL;
+ }
+
+ return count;
+}
+
static ssize_t video_rgb_screen_store(struct class *cla,
struct class_attribute *attr,
const char *buf, size_t count)
return count;
}
+static ssize_t video_nonlinear_t_factor_show(struct class *cla,
+ struct class_attribute *attr,
+ char *buf)
+{
+ u32 factor;
+ struct disp_info_s *layer = &glayer_info[0];
+
+ factor = vpp_get_nonlinear_t_factor(layer);
+
+ return sprintf(buf, "%d\n", factor);
+}
+
+static ssize_t video_nonlinear_t_factor_store(struct class *cla,
+ struct class_attribute *attr,
+ const char *buf, size_t count)
+{
+ int r;
+ u32 factor;
+ struct disp_info_s *layer = &glayer_info[0];
+
+ r = kstrtoint(buf, 0, &factor);
+ if (r < 0)
+ return -EINVAL;
+
+ if (vpp_set_nonlinear_t_factor(layer, factor) == 0)
+ vd_layer[0].property_changed = true;
+
+ return count;
+}
+
static ssize_t video_disable_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
0664,
video_seek_flag_show,
video_seek_flag_store),
+ __ATTR(video_delay_val,
+ 0664,
+ video_videodelay_show,
+ video_videodelay_store),
__ATTR(disable_video,
0664,
video_disable_show,
0644,
vpp_saturation_hue_show,
vpp_saturation_hue_store),
+ __ATTR(video_background,
+ 0644,
+ video_background_show,
+ video_background_store),
__ATTR(test_screen,
0644,
video_test_screen_show,
0644,
video_nonlinear_factor_show,
video_nonlinear_factor_store),
+ __ATTR(nonlinear_t_factor,
+ 0644,
+ video_nonlinear_t_factor_show,
+ video_nonlinear_t_factor_store),
__ATTR(freerun_mode,
0644,
video_freerun_mode_show,
vsync_pts_inc_scale = vinfo->sync_duration_den;
vsync_pts_inc_scale_base = vinfo->sync_duration_num;
spin_unlock_irqrestore(&lock, flags);
- new_vmode = vinfo->mode;
+ strncpy(new_vmode, vinfo->name, 32);
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
pr_info("DOLBY: vout_notify_callback: VOUT_EVENT_MODE_CHANGE\n");
/* force send hdmi pkt in dv code */
vinfo->sync_duration_num;
vsync_pts_inc_scale = vinfo->sync_duration_den;
vsync_pts_inc_scale_base = vinfo->sync_duration_num;
- old_vmode = new_vmode = vinfo->mode;
+ strcpy(old_vmode, vinfo->name);
+ strcpy(new_vmode, vinfo->name);
}
#ifdef CONFIG_AM_VIDEO_LOG
if (vinfo) {
}
EXPORT_SYMBOL(set_video_enabled);
+bool get_disable_video_flag(enum vd_path_e vd_path)
+{
+ if (vd_path == VD1_PATH)
+ return vd_layer[0].disable_video == VIDEO_DISABLE_NORMAL;
+ else if (vd_path == VD2_PATH)
+ return vd_layer[1].disable_video == VIDEO_DISABLE_NORMAL;
+
+ return false;
+}
+EXPORT_SYMBOL(get_disable_video_flag);
+
bool is_di_on(void)
{
bool ret = false;
return force_flush;
}
+static void post_blend_dummy_data_update(void)
+{
+ u32 bg_color;
+
+ if (vd_layer[0].enabled)
+ bg_color = vd_layer[0].video_en_bg_color;
+ else
+ bg_color = vd_layer[0].video_dis_bg_color;
+
+ /* for channel background setting
+ * no auto flag, return
+ */
+ if (!(bg_color & VIDEO_AUTO_POST_BLEND_DUMMY))
+ return;
+
+ if (!legacy_vpp)
+ VSYNC_WR_MPEG_REG(VPP_POST_BLEND_BLEND_DUMMY_DATA,
+ bg_color & 0x00ffffff);
+ else
+ VSYNC_WR_MPEG_REG(VPP_DUMMY_DATA1,
+ bg_color & 0x00ffffff);
+}
+
void vpp_blend_update(
const struct vinfo_s *vinfo)
{
vpp_misc_set);
}
+ post_blend_dummy_data_update();
+
if ((vd_layer[1].dispbuf && video2_off_req) ||
(!vd_layer[1].dispbuf &&
(video1_off_req || video2_off_req)))
return true;
if (cur_vf && new_vf &&
- ((cur_vf->bufWidth != new_vf->bufWidth) ||
+ (((cur_vf->type & VIDTYPE_COMPRESS) &&
+ ((cur_vf->compWidth != new_vf->compWidth) ||
+ (cur_vf->compHeight != new_vf->compHeight))) ||
+ (cur_vf->bufWidth != new_vf->bufWidth) ||
(cur_vf->width != new_vf->width) ||
(cur_vf->height != new_vf->height) ||
(cur_vf->sar_width != new_vf->sar_width) ||
#define CANVAS_TABLE_CNT 1
#endif
+#define VIDEO_AUTO_POST_BLEND_DUMMY BIT(24)
+
#define DISPBUF_TO_PUT_MAX 3
#define MAX_PIP_WINDOW 16
#define VPP_FILER_COEFS_NUM 33
bool need_switch_vf;
bool do_switch;
bool force_black;
+
+ u32 video_en_bg_color;
+ u32 video_dis_bg_color;
};
enum {
#include "video_priv.h"
#define MAX_NONLINEAR_FACTOR 0x40
+#define MAX_NONLINEAR_T_FACTOR 100
/* vpp filter coefficients */
#define COEF_BICUBIC 0
}
}
+/* Trapezoid non-linear mode */
+/* nonlinear_factor: 0x40: 1 : 1 */
+static void calculate_non_linear_ratio_T(
+ unsigned int nonlinear_t_factor,
+ unsigned int width_in,
+ unsigned int width_out,
+ struct vpp_frame_par_s *next_frame_par)
+{
+ u32 ratio, r2_ratio, r1_ratio;
+ u32 region2_hsize_B_max;
+ u32 region2_hsize_A, region2_hsize_B;
+ u32 region1_hsize;
+ u32 phase_step, phase_slope;
+ struct vppfilter_mode_s *vpp_filter =
+ &next_frame_par->vpp_filter;
+
+ ratio = (width_in << 18) / width_out;
+ r2_ratio = (ratio * MAX_NONLINEAR_T_FACTOR /
+ nonlinear_t_factor) << 6;
+ if (r2_ratio < ratio) {
+ pr_info("nonlinear_t_factor(%d) is too large!\n",
+ nonlinear_t_factor);
+ return;
+ }
+ region2_hsize_B_max = (((2 * width_in << 18) / r2_ratio)
+ << 6) - width_out;
+ region2_hsize_B = region2_hsize_B_max;
+ region2_hsize_A = (region2_hsize_B * (r2_ratio >> 6)) >> 18;
+ region1_hsize = (width_out - region2_hsize_B) / 2;
+ r1_ratio = (((width_in - region2_hsize_A) << 18) /
+ (width_out - region2_hsize_B)) << 6;
+ phase_step = 2 * r1_ratio - r2_ratio;
+ phase_slope = (r2_ratio - phase_step) / region1_hsize;
+ vpp_filter->vpp_hf_start_phase_step = phase_step;
+ vpp_filter->vpp_hf_start_phase_slope = phase_slope;
+ vpp_filter->vpp_hf_end_phase_slope =
+ vpp_filter->vpp_hf_start_phase_slope | 0x1000000;
+ next_frame_par->VPP_hsc_linear_startp = region1_hsize - 1;
+ next_frame_par->VPP_hsc_linear_endp =
+ region1_hsize + region2_hsize_B - 1;
+}
+
/*
* V-shape non-linear mode
*/
-static void calculate_non_linear_ratio(
+static void calculate_non_linear_ratio_V(
unsigned int nonlinear_factor,
unsigned int middle_ratio,
unsigned int width_out,
s32 video_layer_global_offset_x, video_layer_global_offset_y;
u32 video_source_crop_top, video_source_crop_left;
u32 video_source_crop_bottom, video_source_crop_right;
- u32 vpp_zoom_ratio, nonlinear_factor;
+ u32 vpp_zoom_ratio, nonlinear_factor, nonlinear_t_factor;
u32 speed_check_width, speed_check_height;
s32 video_layer_top, video_layer_left;
s32 video_layer_width, video_layer_height;
speed_check_width = input->speed_check_width;
speed_check_height = input->speed_check_height;
nonlinear_factor = input->nonlinear_factor;
+ nonlinear_t_factor = input->nonlinear_t_factor;
video_layer_global_offset_x = input->global_offset_x;
video_layer_global_offset_y = input->global_offset_y;
RESTART:
aspect_factor = (vpp_flags & VPP_FLAG_AR_MASK) >> VPP_FLAG_AR_BITS;
/* don't use input->wide_mode */
- wide_mode = vpp_flags & VPP_FLAG_WIDEMODE_MASK;
+ wide_mode = (vpp_flags & VPP_FLAG_WIDEMODE_MASK) >> VPP_WIDEMODE_BITS;
if ((vpp_flags & VPP_FLAG_AR_MASK) == VPP_FLAG_AR_MASK) {
ext_sar = true;
}
/* speical mode did not use ext sar mode */
- if ((wide_mode == VIDEO_WIDEOPTION_NONLINEAR) ||
- (wide_mode == VIDEO_WIDEOPTION_NORMAL_NOSCALEUP))
+ if (wide_mode == VIDEO_WIDEOPTION_NONLINEAR ||
+ wide_mode == VIDEO_WIDEOPTION_NORMAL_NOSCALEUP ||
+ wide_mode == VIDEO_WIDEOPTION_NONLINEAR_T)
ext_sar = false;
/* keep 8 bits resolution for aspect conversion */
aspect_factor, w_in, height_out,
width_out, h_in, aspect_ratio_out >> 2);
- if ((aspect_factor == 0)
- || (wide_mode == VIDEO_WIDEOPTION_FULL_STRETCH)
- || (wide_mode == VIDEO_WIDEOPTION_NONLINEAR)) {
+ if ((aspect_factor == 0) ||
+ wide_mode == VIDEO_WIDEOPTION_FULL_STRETCH ||
+ wide_mode == VIDEO_WIDEOPTION_NONLINEAR ||
+ wide_mode == VIDEO_WIDEOPTION_NONLINEAR_T) {
aspect_factor = 0x100;
height_after_ratio = h_in;
} else if (ext_sar) {
}
if ((wide_mode == VIDEO_WIDEOPTION_NONLINEAR) && (end > start)) {
- calculate_non_linear_ratio(
+ calculate_non_linear_ratio_V(
nonlinear_factor,
ratio_x, end - start,
next_frame_par);
next_frame_par->VPP_hsc_linear_startp =
next_frame_par->VPP_hsc_linear_endp = (start + end) / 2;
}
+ if (wide_mode == VIDEO_WIDEOPTION_NONLINEAR_T &&
+ end > start) {
+ calculate_non_linear_ratio_T(nonlinear_t_factor,
+ w_in, end - start + 1,
+ next_frame_par);
+ }
/*
*check the painful bandwidth limitation and see
next_frame_par->supsc1_vert_ratio = 0;
}
/* step2: judge core0&core1 horizontal enable or disable*/
- if ((hor_sc_multiple_num >= 2) &&
- (vpp_wide_mode != VIDEO_WIDEOPTION_NONLINEAR)) {
+ if (hor_sc_multiple_num >= 2 &&
+ ((vpp_wide_mode != VIDEO_WIDEOPTION_NONLINEAR) &&
+ (vpp_wide_mode != VIDEO_WIDEOPTION_NONLINEAR_T))) {
if ((src_width > sr->core0_v_disable_width_max) ||
((src_width > sr->core0_v_enable_width_max) &&
next_frame_par->supsc0_vert_ratio) ||
next_frame_par->vscale_skip_count = 0;
next_frame_par->hscale_skip_count = 0;
next_frame_par->nocomp = false;
- if (vpp_flags & VPP_FLAG_INTERLACE_IN)
+ if (vpp_flags & VPP_FLAG_INTERLACE_IN ||
+ vpp_flags & VPP_FLAG_INTERLACE_OUT)
next_frame_par->vscale_skip_count++;
if (vpp_flags & VPP_FLAG_INTERLACE_OUT)
height_shift++;
RESTART:
/* don't use input->wide_mode */
- wide_mode = vpp_flags & VPP_FLAG_WIDEMODE_MASK;
+ wide_mode = (vpp_flags & VPP_FLAG_WIDEMODE_MASK) >> VPP_WIDEMODE_BITS;
/*
*if we have ever set a cropped display area for video layer
next_frame_par->VPP_vsc_startp = 0;
next_frame_par->VPP_vsc_endp = 0;
} else {
- next_frame_par->VPP_vsc_startp =
- (vpp_flags & VPP_FLAG_INTERLACE_OUT) ?
- (start >> 1) : start;
- next_frame_par->VPP_vsc_endp =
- (vpp_flags & VPP_FLAG_INTERLACE_OUT) ?
- (end >> 1) : end;
+ next_frame_par->VPP_vsc_startp = start;
+ next_frame_par->VPP_vsc_endp = end;
}
/* set filter co-efficients */
if (skip_policy & 0x40) {
next_frame_par->vscale_skip_count = skip_policy & 0xf;
goto RESTART;
- } else if (skip_policy & 0x80) {
- if ((((vf->width >= 4096) &&
- (!(vf->type & VIDTYPE_COMPRESS))) ||
- (vf->flag & VFRAME_FLAG_HIGH_BANDWIDTH))
- && (next_frame_par->vscale_skip_count == 0)) {
- next_frame_par->vscale_skip_count =
- skip_policy & 0xf;
- goto RESTART;
- }
}
}
/* don't restore the wide mode */
/* input->wide_mode = wide_mode; */
- vpp_flags |= wide_mode | (aspect_ratio << VPP_FLAG_AR_BITS);
+ vpp_flags |= (wide_mode << VPP_WIDEMODE_BITS) |
+ (aspect_ratio << VPP_FLAG_AR_BITS);
if (vinfo->field_height != vinfo->height)
vpp_flags |= VPP_FLAG_INTERLACE_OUT;
return info->nonlinear_factor;
}
+s32 vpp_set_nonlinear_t_factor(struct disp_info_s *info, u32 f)
+{
+ if (f < MAX_NONLINEAR_T_FACTOR) {
+ info->nonlinear_t_factor = f;
+ return 0;
+ }
+ return -1;
+}
+
+u32 vpp_get_nonlinear_t_factor(struct disp_info_s *info)
+{
+ return info->nonlinear_t_factor;
+}
+
void vpp_disp_info_init(
struct disp_info_s *info, u8 id)
{
if (info) {
memset(info, 0, sizeof(struct disp_info_s));
info->nonlinear_factor = MAX_NONLINEAR_FACTOR / 2;
+ info->nonlinear_t_factor = MAX_NONLINEAR_T_FACTOR - 10;
info->zoom_ratio = 100;
info->speed_check_width = 1800;
info->speed_check_height = 1400;
module_param(enable_db_reg, bool, 0644);
MODULE_PARM_DESC(enable_db_reg, "enable/disable tvafe load reg");
+int top_init_en;
+
/*0: atv playmode*/
/*1: atv search mode*/
static bool tvafe_mode;
.callmaster_det = NULL,
};
+static bool white_pattern_reset_pag(enum tvin_port_e port,
+ struct tvafe_cvd2_s cvd2)
+{
+ if (IS_TVAFE_AVIN_SRC(port)) {
+ if (port == TVIN_PORT_CVBS1) {
+ if (av1_plugin_state == 1) {
+ top_init_en = 1;
+ return true;
+ }
+ }
+
+ if (port == TVIN_PORT_CVBS2) {
+ if (av2_plugin_state == 1) {
+ top_init_en = 1;
+ return true;
+ }
+ }
+
+ if (((av1_plugin_state == 0) || (av2_plugin_state == 0)) &&
+ top_init_en && (cvd2.info.state_cnt == 3)) {
+ white_pattern_pga_reset(port);
+ tvafe_pr_info("av1:%u av2:%u\n", av1_plugin_state,
+ av2_plugin_state);
+ top_init_en = 0;
+ return true;
+ }
+ }
+
+ return false;
+}
+
/*
* tvafe signal signal status: signal on/off
*/
if ((port < TVIN_PORT_CVBS0) || (port > TVIN_PORT_CVBS3))
return ret;
+ if (white_pattern_reset_pag(port, tvafe->cvd2))
+ return true;
+
if (tvafe->cvd2.info.smr_cnt++ >= 65536)
tvafe->cvd2.info.smr_cnt = 0;
static unsigned int irq_pol;
-static unsigned int avin_count_times = 3;
+static unsigned int avin_count_times = 5;
static unsigned int avin_timer_time = 10;/*100ms*/
tvafe_pr_info("avin[1].status IN.\n");
/*port opened and plug in,enable clamp*/
/*sync tip close*/
- if (avport_opened == TVAFE_PORT_AV2) {
- W_APB_BIT(TVFE_CLAMP_INTF, 1,
- CLAMP_EN_BIT, CLAMP_EN_WID);
+ if (avport_opened == TVAFE_PORT_AV2)
tvafe_cha2_SYNCTIP_close_config();
}
- }
s_irq_counter1_time = 0;
}
s_counter1_last_state = 1;
av2_plugin_state = 1;
tvafe_pr_info("avin[1].status OUT.\n");
/*port opened but plug out,need disable clamp*/
- if (avport_opened == TVAFE_PORT_AV2) {
+ if (avport_opened == TVAFE_PORT_AV2) {
W_APB_BIT(TVFE_CLAMP_INTF, 0,
- CLAMP_EN_BIT, CLAMP_EN_WID);
- /*restart in tvafe port close*/
+ CLAMP_EN_BIT, CLAMP_EN_WID);
tvafe_cha2_detect_restart_config();
- }
+ }
}
s_irq_counter1_time = 0;
}
tvafe_pr_info("avin[0].status IN.\n");
/*port opened and plug in then enable clamp*/
/*sync tip close*/
- if (avport_opened == TVAFE_PORT_AV1) {
- W_APB_BIT(TVFE_CLAMP_INTF, 1,
- CLAMP_EN_BIT, CLAMP_EN_WID);
+ if (avport_opened == TVAFE_PORT_AV1)
tvafe_cha1_SYNCTIP_close_config();
- }
}
s_irq_counter0_time = 0;
}
/*the EN_SYNC_TIP need be set to "1"*/
/*to sense the plug in operation*/
/*port opened but plug out,need disable clamp*/
- if (avport_opened == TVAFE_PORT_AV1) {
- W_APB_BIT(TVFE_CLAMP_INTF, 0,
- CLAMP_EN_BIT, CLAMP_EN_WID);
- tvafe_cha1_detect_restart_config();
- }
+ if (avport_opened == TVAFE_PORT_AV1) {
+ W_APB_BIT(TVFE_CLAMP_INTF, 0,
+ CLAMP_EN_BIT, CLAMP_EN_WID);
+ tvafe_cha1_detect_restart_config();
+ }
}
s_irq_counter0_time = 0;
}
#define CVD_REG07_PAL 0x03
#define SYNC_SENSITIVITY true
#define NOISE_JUDGE false
-#define PGA_DEFAULT_VAL 0x20
+#define PGA_DEFAULT_VAL 0xa
/*0:NORMAL 1:a little sharper 2:sharper 3:even sharper*/
#define CVD2_FILTER_CONFIG_LEVEL 0
tvafe_pr_info("%s: current fmt is:%s\n",
__func__, tvin_sig_fmt_str(cvd2->config_fmt));
} else if (cvd2->info.state == TVAFE_CVD2_STATE_FIND) {
+ if (IS_TVAFE_AVIN_SRC(cvd2->vd_port)) {
+ if (!cvd2->hw.chroma_lock && cvd2->hw.no_color_burst &&
+ !cvd2->hw.h_lock && !cvd2->hw.no_sig)
+ W_APB_BIT(TVFE_CLAMP_INTF, 0x0,
+ CLAMP_EN_BIT, CLAMP_EN_WID);
+ }
/* manual mode => go directly to the manual format */
try_format_cnt = 0;
if (tvafe_cvd2_condition_shift(cvd2)) {
tvafe_cvd2_try_format(
cvd2, mem, TVIN_SIG_FMT_CVBS_PAL_I);
cvd2->info.state = TVAFE_CVD2_STATE_INIT;
+ if (IS_TVAFE_AVIN_SRC(cvd2->vd_port)) {
+ if (!R_APB_BIT(TVFE_CLAMP_INTF,
+ CLAMP_EN_BIT, CLAMP_EN_WID))
+ W_APB_BIT(TVFE_CLAMP_INTF, 0x1,
+ CLAMP_EN_BIT,
+ CLAMP_EN_WID);
+ }
cvd2->info.ntsc_switch_cnt = 0;
try_format_cnt = 0;
cvd_pr_flag = false;
}
}
+/*
+ * tvafe power control of the module
+ */
+static void tvafe_top_enable_module(bool enable)
+{
+ /* disable */
+ if (!enable) {
+ W_APB_BIT(TVFE_VAFE_CTRL1, 0,
+ VAFE_PGA_EN_BIT, VAFE_PGA_EN_WID);
+ }
+ W_APB_BIT(TVFE_TOP_CTRL, 0, DCLK_ENABLE_BIT, DCLK_ENABLE_WID);
+ tvafe_pr_info("reset module\n");
+ mdelay(5);
+ W_APB_BIT(TVFE_RST_CTRL, 1, DCLK_RST_BIT, DCLK_RST_WID);
+ W_APB_BIT(TVFE_RST_CTRL, 0, DCLK_RST_BIT, DCLK_RST_WID);
+}
+
+static void tvafe_top_init_reg(enum tvin_port_e port)
+{
+ W_APB_BIT(TVFE_TOP_CTRL, 1, DCLK_ENABLE_BIT, DCLK_ENABLE_WID);
+ if (IS_TVAFE_AVIN_SRC(port)) {
+ if (port == TVIN_PORT_CVBS1)
+ W_APB_REG(TVFE_VAFE_CTRL1, 0x0000110e);
+ else
+ W_APB_REG(TVFE_VAFE_CTRL1, 0x0000210e);
+ }
+ tvafe_pr_info("%s ok.\n", __func__);
+}
+
+void white_pattern_pga_reset(enum tvin_port_e port)
+{
+ tvafe_top_enable_module(false);
+ mdelay(80);
+ tvafe_top_init_reg(port);
+ mdelay(10);
+ W_APB_BIT(TVFE_CLAMP_INTF, 1, CLAMP_EN_BIT, CLAMP_EN_WID);
+ mdelay(10);
+}
+
extern int tvafe_adc_get_pll_flag(void);
extern int tvafe_cpu_type(void);
extern void tvafe_clk_gate_ctrl(int status);
+void white_pattern_pga_reset(enum tvin_port_e port);
extern struct mutex pll_mutex;
extern unsigned int cvd_reg87_pal;
"576cvbs",
"pal_m",
"pal_n",
- "ntsc_n",
+ "ntsc_m",
NULL
};
ssize_t aml_CVBS_attr_wss_show(struct class *class,
struct class_attribute *attr, char *buf)
{
- unsigned int enable = ((cvbs_out_reg_read(ENCI_VBI_SETTING)&0xc)
- == 0)?0:1;
- unsigned int line = cvbs_out_reg_read(ENCI_VBI_WSS_LN)+1;
- unsigned int data = cvbs_out_reg_read(ENCI_VBI_WSSDT);
+ unsigned int line = 0;
+ unsigned int data = 0;
+ unsigned int enable = ((cvbs_out_reg_read(ENCI_VBI_SETTING) & 0x3c)
+ == 0) ? 0 : 1;
+ if (get_local_cvbs_mode() == MODE_576CVBS) {
+ line = cvbs_out_reg_read(ENCI_VBI_WSS_LN) + 1;
+ data = cvbs_out_reg_read(ENCI_VBI_WSSDT);
+ } else if (get_local_cvbs_mode() == MODE_480CVBS) {
+ line = cvbs_out_reg_read(ENCI_VBI_CGMS_LN);
+ line >>= 8;
+ line = line + 3;
+
+ data = cvbs_out_reg_read(ENCI_VBI_CGMSDT_L);
+ data >>= wss_info[11].start;
+ data &= 0xff;
+ }
if (enable == 1)
return sprintf(buf, "wss line:%d data 0x%x\n", line, data);
.tmds_clk_div40 = 0,
.tmds_clk = 855000,
.timing = {
- .pixel_freq = 855000,
+ .pixel_freq = 85500,
.h_freq = 47700,
.v_freq = 60015,
.vsync = 60,
for (i = 0; all_fmt_paras[i] != NULL; i++) {
if ((t->hactive == all_fmt_paras[i]->timing.h_active) &&
(t->vactive == all_fmt_paras[i]->timing.v_active)) {
- if (t->hsync &&
- (t->hsync == all_fmt_paras[i]->timing.vsync))
- return all_fmt_paras[i];
+ if (t->vsync) {
+ unsigned int vsync;
+
+ vsync = all_fmt_paras[i]->timing.vsync;
+ if (vsync == 0) {
+ vsync = all_fmt_paras[i]->timing.v_freq;
+ vsync = vsync / 1000;
+ }
+ if (t->vsync == vsync)
+ return all_fmt_paras[i];
+ }
if ((t->hblank && (t->hblank ==
all_fmt_paras[i]->timing.h_blank))
&& (t->vblank && (t->vblank ==
}
}
+static void store_cea_idx(struct rx_cap *prxcap, enum hdmi_vic vic)
+{
+ int i;
+ int already = 0;
+
+ for (i = 0; (i < VIC_MAX_NUM) && (i < prxcap->VIC_count); i++) {
+ if (vic == prxcap->VIC[i]) {
+ already = 1;
+ break;
+ }
+ }
+ if (!already) {
+ prxcap->VIC[prxcap->VIC_count] = vic;
+ prxcap->VIC_count++;
+ }
+}
+
static void Edid_EstablishedTimings(struct rx_cap *prxcap, unsigned char *data)
{
if (data[0] & (1 << 5))
t->vactive = t->hactive * 9 / 16;
break;
}
- t->hsync = (data[1] & 0x3f) + 60;
+ t->vsync = (data[1] & 0x3f) + 60;
para = hdmi_get_vesa_paras(t);
- if (para)
+ if (para) {
t->vesa_timing = para->vic;
+ if (para->vic < HDMITX_VESA_OFFSET) {
+ struct hdmitx_dev *hdev = get_hdmitx_device();
+ struct rx_cap *prxcap = &hdev->rxcap;
+ store_cea_idx(prxcap, para->vic);
+ }
+ }
}
static void Edid_StandardTiming(struct rx_cap *prxcap, unsigned char *data,
}
}
-/* ----------------------------------------------------------- */
-void Edid_ParseCEADetailedTimingDescriptors(struct hdmitx_info *info,
- unsigned char blk_mun, unsigned char BaseAddr,
+static void Edid_ParseCEADetailedTimingDescriptors(struct rx_cap *prxcap,
unsigned char *buff)
{
- unsigned char index_edid;
+ int i;
+ unsigned char *dtd_base = buff;
- for (index_edid = 0; index_edid < blk_mun; index_edid++) {
- BaseAddr += 18;
- /* there is not the TimingDescriptors */
- if ((BaseAddr + 18) > 0x7d)
- break;
+ for (i = 0; i < 4; i++) {
+ Edid_DTD_parsing(prxcap, dtd_base);
+ dtd_base += 0x12;
}
}
struct rx_cap *prxcap = &hdev->rxcap;
unsigned int aud_flag = 0;
- if (blockbuf[0] != 0x02)
+ /* CEA-861 implementations are required to use Tag = 0x02
+ * for the CEA Extension Tag and Sources should ignore
+ * Tags that are not understood. but for Samsung LA32D400E1
+ * its extension tag is 0x0 while other bytes normal,
+ * so continue parse as other sources do
+ */
+ if (blockbuf[0] == 0x0)
+ pr_info(EDID "unkonw Extension Tag detected, continue\n");
+ else if (blockbuf[0] != 0x02)
return -1; /* not a CEA BLOCK. */
end = blockbuf[2]; /* CEA description. */
prxcap->native_Mode = blockbuf[3];
offset++;
for (i = 0 ; i < count ; i++) {
unsigned char VIC;
-
- VIC = blockbuf[offset + i] & (~0x80);
- prxcap->VIC[prxcap->VIC_count] = VIC;
- if (blockbuf[offset + i] & 0x80)
+ /* 7.5.1 Video Data Block Table 58
+ * and CTA-861-G page101: only 1~64
+ * maybe Native Video Format. and
+ * need to take care hdmi2.1 VIC:
+ * 193~253
+ */
+ VIC = blockbuf[offset + i];
+ if (VIC >= 129 && VIC <= 192) {
+ VIC &= (~0x80);
prxcap->native_VIC = VIC;
+ }
+ prxcap->VIC[prxcap->VIC_count] = VIC;
prxcap->VIC_count++;
}
offset += count;
Edid_Y420CMDB_PostProcess(hdev);
hdev->vic_count = prxcap->VIC_count;
- idx = blockbuf[3] & 0xf;
- for (i = 0; i < idx; i++)
- Edid_DTD_parsing(prxcap, &blockbuf[blockbuf[2] + i * 18]);
+ /* dtds in extended blocks */
+ i = 0;
+ offset = blockbuf[2] + i * 18;
+ for ( ; (offset + 18) < 0x7f; i++) {
+ Edid_DTD_parsing(prxcap, &blockbuf[offset]);
+ offset += 18;
+ }
+
if (vfpdb_offset)
Edid_ParsingVFPDB(prxcap, vfpdb_offset);
if ((prxcap->hdmi2ver == 1) &&
prxcap->RxAudioCap[0].cc3 = 1; /* 16bit */
}
-/* add default VICs for DVI case */
+/* add default VICs for all zeroes case */
static void hdmitx_edid_set_default_vic(struct hdmitx_dev *hdmitx_device)
{
struct rx_cap *prxcap = &hdmitx_device->rxcap;
struct hdmi_format_para *para = NULL;
struct dtd *t = &prxcap->dtd[prxcap->dtd_idx];
+ /* if data[0-2] are zeroes, no need parse, and skip*/
+ if (data[0] == 0 && data[1] == 0 && data[2] == 0)
+ return;
memset(t, 0, sizeof(struct dtd));
t->pixel_clock = data[0] + (data[1] << 8);
t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2];
t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) +
((data[10] >> 4) & 0xf);
t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf);
+ t->h_image_size = (((data[14] >> 4) & 0xf) << 8) + data[12];
+ t->v_image_size = ((data[14] & 0xf) << 8) + data[11];
/*
* Special handling of 1080i60hz, 1080i50hz
*/
pr_info(EDID "get dtd%d vic: %d\n",
prxcap->dtd_idx, para->vic);
prxcap->dtd_idx++;
+ if (para->vic < HDMITX_VESA_OFFSET)
+ store_cea_idx(prxcap, para->vic);
+ else
+ store_vesa_idx(prxcap, para->vic);
} else
if (0) /* for debug usage */
dump_dtd_info(t);
}
switch ((data[2] >> 5) & 0x3) {
case 0:
- t->hsync = 50;
+ t->vsync = 50;
break;
case 1:
- t->hsync = 60;
+ t->vsync = 60;
break;
case 2:
- t->hsync = 75;
+ t->vsync = 75;
break;
case 3:
default:
- t->hsync = 85;
+ t->vsync = 85;
break;
}
para = hdmi_get_vesa_paras(t);
Edid_PhyscialSizeParse(&hdmitx_device->rxcap, &EDID_buf[21]);
Edid_DecodeStandardTiming(&hdmitx_device->hdmi_info, &EDID_buf[26], 8);
- Edid_ParseCEADetailedTimingDescriptors(&hdmitx_device->hdmi_info,
- 4, 0x36, &EDID_buf[0]);
+ Edid_ParseCEADetailedTimingDescriptors(&hdmitx_device->rxcap,
+ &EDID_buf[0x36]);
BlockCount = EDID_buf[0x7E];
hdmitx_device->rxcap.blk0_chksum = EDID_buf[0x7F];
if (BlockCount == 0) {
pr_info(EDID "EDID BlockCount=0\n");
- hdmitx_edid_set_default_vic(hdmitx_device);
/* DVI case judgement: only contains one block and
* checksum valid
if (zero_numbers > 120)
hdmitx_device->rxcap.ieeeoui = HDMI_IEEEOUI;
hdmitx_device->vend_id_hit = hdmitx_find_philips(hdmitx_device);
+ hdmitx_edid_set_default_vic(hdmitx_device);
return 0; /* do nothing. */
}
if ((BlockCount > 1) && (i == 1))
CheckSum = 0; /* ignore the block1 data */
else {
- if (((BlockCount == 1) && (i == 1)) ||
- ((BlockCount > 1) && (i == 2)))
+ if ((((BlockCount == 1) && (i == 1)) ||
+ ((BlockCount > 1) && (i == 2))) &&
+ (i * 128 < sizeof(hdmitx_device->EDID_buf)))
Edid_Parse_check_HDMI_VSDB(
hdmitx_device,
&EDID_buf[i * 128]);
EDID_buf[i * 128 + 3]);
ret_val = Edid_ParsingCEADataBlockCollection(
hdmitx_device, &EDID_buf[i * 128]);
- Edid_ParseCEADetailedTimingDescriptors(
- &hdmitx_device->hdmi_info, 5,
- EDID_buf[i * 128 + 2],
- &EDID_buf[i * 128]);
}
}
-
- hdmitx_edid_block_parse(hdmitx_device, &(EDID_buf[i*128]));
+ if (i * 128 < sizeof(hdmitx_device->EDID_buf))
+ hdmitx_edid_block_parse(hdmitx_device,
+ &EDID_buf[i * 128]);
}
/* EDID parsing complete - check if 4k60/50 DV can be truly supported */
pr_info(EDID "not find IEEEOUT\n");
}
- if ((prxcap->ieeeoui != HDMI_IEEEOUI) || (prxcap->ieeeoui == 0x0) ||
- (prxcap->VIC_count == 0))
- hdmitx_edid_set_default_vic(hdmitx_device);
-
/* strictly DVI device judgement */
/* valid EDID & no audio tag & no IEEEOUI */
if (edid_check_valid(&EDID_buf[0]) &&
edid_save_checkvalue(EDID_buf, BlockCount + 1, prxcap);
- i = hdmitx_edid_dump(hdmitx_device, (char *)(hdmitx_device->tmp_buf),
- HDMI_TMP_BUF_SIZE);
- hdmitx_device->tmp_buf[i] = 0;
-
if (!hdmitx_edid_check_valid_blocks(&EDID_buf[0])) {
prxcap->ieeeoui = HDMI_IEEEOUI;
pr_info(EDID "Invalid edid, consider RX as HDMI device\n");
}
}
hdmitx_device->vend_id_hit = hdmitx_find_philips(hdmitx_device);
+ /* For some receivers, they don't claim the screen size
+ * and re-calculate it from the h/v image size from dtd
+ * the unit of screen size is cm, but the unit of image size is mm
+ */
+ if (prxcap->physcial_weight == 0 || prxcap->physcial_height == 0) {
+ struct dtd *t = &prxcap->dtd[0];
+
+ prxcap->physcial_weight = (t->h_image_size + 5) / 10;
+ prxcap->physcial_height = (t->v_image_size + 5) / 10;
+ }
+
+ /* if edid are all zeroes, or no VIC, no vesa dtd, set default vic */
+ if (edid_zero_data(EDID_buf) ||
+ (prxcap->VIC_count == 0 && (prxcap->vesa_timing[0] == 0)))
+ hdmitx_edid_set_default_vic(hdmitx_device);
+
return 0;
}
{"1680x1050p60hz", HDMIV_1680x1050p60hz},
{"1920x1200p60hz", HDMIV_1920x1200p60hz},
{"2160x1200p90hz", HDMIV_2160x1200p90hz},
- {"2560x1080p60hz", HDMIV_2560x1080p60hz},
{"2560x1440p60hz", HDMIV_2560x1440p60hz},
{"2560x1600p60hz", HDMIV_2560x1600p60hz},
{"3440x1440p60hz", HDMIV_3440x1440p60hz},
bool valid = 0;
struct rx_cap *prxcap = NULL;
const struct dv_info *dv = &hdev->rxcap.dv_info;
+ enum hdmi_vic *vesa_t = &hdev->rxcap.vesa_timing[0];
unsigned int rx_max_tmds_clk = 0;
unsigned int calc_tmds_clk = 0;
int i = 0;
int svd_flag = 0;
/* Default max color depth is 24 bit */
enum hdmi_color_depth rx_y444_max_dc = COLORDEPTH_24B;
- enum hdmi_color_depth rx_y422_max_dc = COLORDEPTH_24B;
enum hdmi_color_depth rx_y420_max_dc = COLORDEPTH_24B;
enum hdmi_color_depth rx_rgb_max_dc = COLORDEPTH_24B;
if (!hdev || !para)
return 0;
- if (strcmp(para->sname, "invalid") == 0)
- return 0;
+ if (para->sname)
+ if (strcmp(para->sname, "invalid") == 0)
+ return 0;
/* exclude such as: 2160p60hz YCbCr444 10bit */
switch (para->vic) {
case HDMI_3840x2160p50_16x9:
if ((para->vic & 0xff) == (prxcap->VIC[i] & 0xff))
svd_flag = 1;
}
+ if (para->vic >= HDMITX_VESA_OFFSET) {
+ if (para->cd != COLORDEPTH_24B)
+ return 0;
+ if (para->cs != COLORSPACE_RGB444)
+ return 0;
+ for (i = 0; vesa_t[i] && i < VESA_MAX_TIMING; i++) {
+ struct hdmi_format_para *param = NULL;
+
+ param = hdmi_get_fmt_paras(vesa_t[i]);
+ if (param) {
+ if ((param->vic >= HDMITX_VESA_OFFSET) &&
+ (para->vic == param->vic)) {
+ svd_flag = 1;
+ break;
+ }
+ }
+ }
+ }
if (svd_flag == 0)
return 0;
/* Rx may not support Y422 */
if (!(prxcap->native_Mode & (1 << 4)))
return 0;
- if (prxcap->dc_y444 && prxcap->dc_30bit)
- rx_y422_max_dc = COLORDEPTH_30B;
- if ((prxcap->dc_y444 && prxcap->dc_36bit)
- || (dv->sup_yuv422_12bit))
- rx_y422_max_dc = COLORDEPTH_36B;
- if (para->cd <= rx_y422_max_dc)
- valid = 1;
- else
- valid = 0;
- return valid;
+ return 1;
}
if (para->cs == COLORSPACE_RGB444) {
/* Always assume RX supports RGB444 */
return valid;
}
+static bool check_sd(struct rx_cap *prxcap, const char *_mode,
+ const char *mode, const unsigned int _vic,
+ unsigned int *vic)
+{
+ int i;
+ bool check1 = 0;
+ bool check2 = 0;
+
+ if (strcmp(_mode, mode) == 0) {
+ for (i = 0 ; i < prxcap->VIC_count ; i++) {
+ if (prxcap->VIC[i] == _vic)
+ check1 = 1;
+ }
+ for (i = 0 ; i < prxcap->VIC_count ; i++) {
+ if (prxcap->VIC[i] == (_vic + 1))
+ check2 = 1;
+ }
+ if ((check1 == 1) && (check2 == 0)) {
+ *vic = _vic;
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/* For some TV only support 480p 4:3,
+ *then consider it also supports in disp_cap
+ */
+static bool is_sink_only_sd_4x3(struct hdmitx_dev *hdev,
+ const char *mode, unsigned int *vic)
+{
+ struct rx_cap *prxcap = &hdev->rxcap;
+
+ if (check_sd(prxcap, "480i60hz", mode, HDMI_720x480i60_4x3, vic))
+ return 1;
+ if (check_sd(prxcap, "480p60hz", mode, HDMI_720x480p60_4x3, vic))
+ return 1;
+ if (check_sd(prxcap, "576i50hz", mode, HDMI_720x576i50_4x3, vic))
+ return 1;
+ if (check_sd(prxcap, "576p50hz", mode, HDMI_720x576p50_4x3, vic))
+ return 1;
+
+ return 0;
+}
+
/* force_flag: 0 means check with RX's edid */
/* 1 means no check wich RX's edid */
enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
if (j >= prxcap->VIC_count)
vic = HDMI_Unknown;
}
+ /* if TV only supports 480p/2, add 480p60hz as well */
+ if (is_sink_only_sd_4x3(hdev, disp_mode, &vic)) {
+ pr_info("hdmitx: find SD only 4x3\n");
+ }
}
if ((vic == HDMI_Unknown) &&
(vesa_vic != HDMI_Unknown)) {
#include <linux/version.h>
#include <linux/module.h>
+#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/delay.h>
+#include <linux/debugfs.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/spinlock_types.h>
#include <linux/extcon.h>
+#include <linux/uaccess.h>
/* #include <mach/am_regs.h> */
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
* version 1.1
*/
+#define DEVICE_NAME "amhdmitx"
static int hdmi_authenticated;
+static DEFINE_MUTEX(mutex);
+/* obs_cur, record current obs */
+static struct hdcp_obs_val obs_cur;
+/* if obs_cur is differ than last time, then save to obs_last */
+static struct hdcp_obs_val obs_last;
+static int write_buff(const char *fmt, ...);
+
+static struct hdcplog_buf hdcplog_buf;
+
unsigned int hdcp_get_downstream_ver(void)
{
unsigned int ret = 14;
return one_num == 20;
}
+static int save_obs_val(struct hdmitx_dev *hdev, struct hdcp_obs_val *obs)
+{
+ return hdev->hwop.cntlddc((struct hdmitx_dev *)obs,
+ DDC_HDCP14_SAVE_OBS, 0);
+}
+
+static void pr_obs(struct hdcp_obs_val *obst0, struct hdcp_obs_val *obst1,
+ unsigned int mask)
+{
+ /* if idx > HDCP_LOG_SIZE, then set idx as 0 for wrapping log */
+#define GETBITS(val, start, len) (((val) >> (start)) & ((1 << (len)) - 1))
+#define DIFF_ST(_v1, v0, _s, _l, str) \
+ do { \
+ typeof(_v1) v1 = (_v1); \
+ typeof(_s) s = (_s); \
+ typeof(_l) l = (_l); \
+ if (GETBITS(v1, s, l) != (GETBITS(v0, s, l))) { \
+ write_buff("%s: %x\n", str, GETBITS(v1, s, l)); \
+ } \
+ } while (0)
+
+ if (mask & (1 << 0)) {
+ if (GETBITS(obst1->obs0, 1, 7) != GETBITS(obst0->obs0, 1, 7)) {
+ write_buff("StateA: %x SubStateA: %x\n",
+ GETBITS(obst1->obs0, 4, 4),
+ GETBITS(obst1->obs0, 1, 3));
+ }
+ DIFF_ST(obst1->obs0, obst0->obs0, 0, 1, "hdcpengaged");
+ }
+ if (mask & (1 << 1)) {
+ DIFF_ST(obst1->obs1, obst0->obs1, 4, 3, "StateOEG");
+ DIFF_ST(obst1->obs1, obst0->obs1, 0, 4, "StateR");
+ }
+ if (mask & (1 << 2)) {
+ DIFF_ST(obst1->obs2, obst0->obs2, 3, 3, "StateE");
+ DIFF_ST(obst1->obs2, obst0->obs2, 0, 3, "StateEEG");
+ }
+ if (mask & (1 << 3)) {
+ DIFF_ST(obst1->obs3, obst0->obs3, 7, 1, "RSVD");
+ DIFF_ST(obst1->obs3, obst0->obs3, 6, 1, "Repeater");
+ DIFF_ST(obst1->obs3, obst0->obs3, 5, 1, "KSV_FIFO_Ready");
+ DIFF_ST(obst1->obs3, obst0->obs3, 4, 1, "Fast_i2c");
+ DIFF_ST(obst1->obs3, obst0->obs3, 3, 1, "RSVD2");
+ DIFF_ST(obst1->obs3, obst0->obs3, 2, 1, "Hdmi_mode");
+ DIFF_ST(obst1->obs3, obst0->obs3, 1, 1, "Features1.1");
+ DIFF_ST(obst1->obs3, obst0->obs3, 0, 1, "Fast_Reauth");
+ }
+ if (mask & (1 << 4)) {
+ DIFF_ST(obst1->intstat, obst0->intstat, 7, 1, "hdcp_engaged");
+ DIFF_ST(obst1->intstat, obst0->intstat, 6, 1, "hdcp_failed");
+ DIFF_ST(obst1->intstat, obst0->intstat, 4, 1, "i2cnack");
+ DIFF_ST(obst1->intstat, obst0->intstat, 3, 1,
+ "lostarbitration");
+ DIFF_ST(obst1->intstat, obst0->intstat, 2, 1,
+ "keepouterrorint");
+ DIFF_ST(obst1->intstat, obst0->intstat, 1, 1, "KSVsha1calcint");
+ }
+}
+
static void _hdcp_do_work(struct work_struct *work)
{
+ int ret = 0;
struct hdmitx_dev *hdev =
container_of(work, struct hdmitx_dev, work_do_hdcp.work);
- if (hdev->hdcp_mode == 2) {
- /* hdev->hwop.cntlmisc(hdev, MISC_HDCP_CLKDIS, 1); */
+ switch (hdev->hdcp_mode) {
+ case 2:
+ /* hdev->HWOp.CntlMisc(hdev, MISC_HDCP_CLKDIS, 1); */
/* schedule_delayed_work(&hdev->work_do_hdcp, HZ / 50); */
- } else
+ break;
+ case 1:
+ mutex_lock(&mutex);
+ ret = save_obs_val(hdev, &obs_cur);
+ /* ret is NZ, then update obs_last */
+ if (ret) {
+ pr_obs(&obs_last, &obs_cur, ret);
+ obs_last = obs_cur;
+ }
+ mutex_unlock(&mutex);
+ /* log time frequency */
+ schedule_delayed_work(&hdev->work_do_hdcp, HZ / 20);
+ break;
+ case 0:
+ default:
+ mutex_lock(&mutex);
+ memset(&obs_cur, 0, sizeof(obs_cur));
+ memset(&obs_last, 0, sizeof(obs_last));
+ mutex_unlock(&mutex);
hdev->hwop.cntlmisc(hdev, MISC_HDCP_CLKDIS, 0);
+ break;
+ }
}
void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev)
return 0;
}
+static int read_buff(char *p)
+{
+ if (hdcplog_buf.rd_pos == hdcplog_buf.wr_pos)
+ return 0;
+
+ *p = hdcplog_buf.buf[hdcplog_buf.rd_pos];
+ hdcplog_buf.rd_pos = (hdcplog_buf.rd_pos + 1) % HDCP_LOG_SIZE;
+ return 1;
+}
+
+static void _write_buff(char c)
+{
+ hdcplog_buf.buf[hdcplog_buf.wr_pos] = c;
+ hdcplog_buf.wr_pos = (hdcplog_buf.wr_pos + 1) % HDCP_LOG_SIZE;
+ if (hdcplog_buf.wr_pos == hdcplog_buf.rd_pos)
+ hdcplog_buf.rd_pos = (hdcplog_buf.rd_pos + 1) % HDCP_LOG_SIZE;
+ wake_up_interruptible(&hdcplog_buf.wait);
+}
+
+static int write_buff(const char *fmt, ...)
+{
+ va_list args;
+ int i, len;
+ static char temp[64];
+
+ va_start(args, fmt);
+ len = vsnprintf(temp, sizeof(temp), fmt, args);
+ va_end(args);
+
+ for (i = 0; i < len; i++)
+ _write_buff(temp[i]);
+
+ return len;
+}
+
+static int hdcplog_open(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static ssize_t hdcplog_read(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ ssize_t error = -EINVAL;
+ int i = 0;
+ char c;
+
+ if ((file->f_flags & O_NONBLOCK) &&
+ (hdcplog_buf.rd_pos == hdcplog_buf.wr_pos))
+ return -EAGAIN;
+
+ if (!buf || !count)
+ goto out;
+
+ error = wait_event_interruptible(hdcplog_buf.wait,
+ (hdcplog_buf.wr_pos != hdcplog_buf.rd_pos));
+ if (error)
+ goto out;
+ while (!error && (read_buff(&c)) && i < count) {
+ error = __put_user(c, buf);
+ buf++;
+ i++;
+ }
+
+ if (!error)
+ error = i;
+out:
+ return error;
+}
+
+const struct file_operations hdcplog_ops = {
+ .read = hdcplog_read,
+ .open = hdcplog_open,
+};
+
+static struct dentry *hdmitx_dbgfs;
+
static int __init hdmitx_hdcp_init(void)
{
struct hdmitx_dev *hdev = get_hdmitx_device();
+ struct dentry *entry;
pr_info(HDCP "hdmitx_hdcp_init\n");
if (hdev->hdtx_dev == NULL) {
return -ENODEV;
}
+ memset(&hdcplog_buf, 0, sizeof(hdcplog_buf));
+ init_waitqueue_head(&hdcplog_buf.wait);
+
hdev->task_hdcp = kthread_run(hdmitx_hdcp_task, (void *)hdev,
"kthread_hdcp");
+ hdmitx_dbgfs = hdmitx_get_dbgfsdentry();
+ if (!hdmitx_dbgfs)
+ hdmitx_dbgfs = debugfs_create_dir(DEVICE_NAME, NULL);
+ if (!hdmitx_dbgfs) {
+ pr_err("can't create %s debugfs dir\n", DEVICE_NAME);
+ return 0;
+ }
+ entry = debugfs_create_file("hdcp_log", S_IFREG | 0444,
+ hdmitx_dbgfs, NULL,
+ &hdcplog_ops);
+ if (!entry)
+ pr_err("debugfs create file %s failed\n", "hdcp_log");
return 0;
}
static const struct dv_info dv_dummy;
static int log_level;
-static int hdr_mute_frame = 3;
+/* for SONY-KD-55A8F TV, need to mute more frames
+ * when switch DV(LL)->HLG
+ */
+static int hdr_mute_frame = 20;
struct vout_device_s hdmitx_vdev = {
.dv_info = &hdmitx_device.rxcap.dv_info,
return;
hdrinfo_to_vinfo(info, hdev);
+ if (hdev->para->cd == COLORDEPTH_24B)
+ memset(&info->hdr_info, 0, sizeof(struct hdr_info));
rxlatency_to_vinfo(info, &hdev->rxcap);
hdmitx_vdev.dv_info = &hdmitx_device.rxcap.dv_info;
}
hdev->output_blank_flag = 1;
hdev->ready = 1;
edidinfo_attach_to_vinfo(hdev);
+ /* backup values need to be updated to latest values */
+ memcpy(hdev->backup_fmt_attr, hdev->fmt_attr, 16);
+ hdev->backup_frac_rate_policy = hdev->frac_rate_policy;
+ hdev->backup_phy_idx = hdev->phy_idx;
return ret;
}
void hdmitx_video_mute_op(unsigned int flag)
{
- if (flag == 0)
- hdmitx_device.hwop.cntlconfig(&hdmitx_device,
- CONF_VIDEO_MUTE_OP, VIDEO_MUTE);
- else
- hdmitx_device.hwop.cntlconfig(&hdmitx_device,
- CONF_VIDEO_MUTE_OP, VIDEO_UNMUTE);
+ if (flag == 0) {
+ /* hdmitx_device.hwop.cntlconfig(&hdmitx_device, */
+ /* CONF_VIDEO_MUTE_OP, VIDEO_MUTE); */
+ hdmitx_device.vid_mute_op = VIDEO_MUTE;
+ } else {
+ /* hdmitx_device.hwop.cntlconfig(&hdmitx_device, */
+ /* CONF_VIDEO_MUTE_OP, VIDEO_UNMUTE); */
+ hdmitx_device.vid_mute_op = VIDEO_UNMUTE;
+ }
}
EXPORT_SYMBOL(hdmitx_video_mute_op);
struct hdmitx_dev *hdev = &hdmitx_device;
unsigned char DRM_HB[3] = {0x87, 0x1, 26};
static unsigned char DRM_DB[26] = {0x0};
+ unsigned long flags = 0;
hdmi_debug();
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
if (data)
memcpy(&drm_config_data, data,
sizeof(struct master_display_info_s));
hdmitx_device.hwop.setpacket(HDMI_PACKET_DRM, NULL, NULL);
hdmitx_device.hwop.cntlconfig(&hdmitx_device,
CONF_AVI_BT2020, hdev->colormetry);
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
schedule_work(&hdev->work_hdr);
DRM_DB[0] = 0;
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
hdmitx_device.hwop.cntlconfig(&hdmitx_device,
CONF_AVI_BT2020, SET_AVI_BT2020);
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
}
schedule_work(&hdev->work_hdr);
}
-
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
}
void update_current_para(struct hdmitx_dev *hdev)
static enum eotf_type ltype = EOTF_T_NULL;
static uint8_t ltmode = -1;
enum hdmi_tf_type hdr_type = HDMI_NONE;
+ unsigned long flags = 0;
hdmi_debug();
- if (hdev->bist_lock)
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
+ if (hdev->bist_lock) {
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
-
+ }
if (data == NULL)
memcpy(&vsif_debug_info.data, ¶,
sizeof(struct dv_vsif_para));
if (hdev->ready == 0) {
ltype = EOTF_T_NULL;
ltmode = -1;
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
if (hdev->rxcap.dv_info.ieeeoui != DV_IEEE_OUI) {
}
if ((hdev->chip_type) < MESON_CPU_ID_GXL) {
pr_info("hdmitx: not support DolbyVision\n");
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
}
if (type == EOTF_T_DV_AHEAD) {
hdev->hwop.setpacket(HDMI_PACKET_VEND, VEN_DB1, VEN_HB);
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
if (type == EOTF_T_DOLBYVISION) {
}
if (type == EOTF_T_DV_AHEAD) {
hdev->hwop.setpacket(HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
/*Dolby Vision standard case*/
}
}
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
}
struct hdr10plus_para hdr10p_config_data;
"1680x1050p60hz",
"1920x1200p60hz",
"2160x1200p90hz",
- "2560x1080p60hz",
"2560x1440p60hz",
"2560x1600p60hz",
"3440x1440p60hz",
*ppos += snprintf(buf + *ppos, PAGE_SIZE, "%s/",
aud_sample_size[j+1]);
}
- *ppos += snprintf(buf + *ppos - 1, PAGE_SIZE, " bit\n");
+ *ppos += snprintf(buf + *ppos - 1, PAGE_SIZE, " bit\n") - 1;
}
/**/
pos += snprintf(buf + pos, PAGE_SIZE, "%s/",
aud_sampling_frequency[j+1]);
}
- pos += snprintf(buf + pos - 1, PAGE_SIZE, " kHz, ");
+ pos += snprintf(buf + pos - 1, PAGE_SIZE, " kHz, ") - 1;
switch (prxcap->RxAudioCap[i].audio_format_code) {
case CT_PCM:
_show_pcm_ch(prxcap, i, &pos, buf);
}
}
next444:
- if (prxcap->dc_y444) {
- if ((prxcap->dc_36bit) || (dv->sup_10b_12b_444 == 0x2) ||
- (dv2->sup_10b_12b_444 == 0x2)) {
- if (!hdev->vend_id_hit)
- pos += snprintf(buf + pos,
- PAGE_SIZE, "444,12bit\n");
- }
- if ((prxcap->dc_30bit) || (dv->sup_10b_12b_444 == 0x1) ||
- (dv2->sup_10b_12b_444 == 0x1)) {
- if (!hdev->vend_id_hit)
- pos += snprintf(buf + pos,
- PAGE_SIZE, "444,10bit\n");
- pos += snprintf(buf + pos, PAGE_SIZE, "444,8bit\n");
- }
-#if 0
- if (prxcap->dc_48bit)
- pos += snprintf(buf + pos, PAGE_SIZE, "444,16bit\n");
-#endif
- if ((prxcap->dc_36bit) || (dv->sup_yuv422_12bit) ||
- (dv2->sup_yuv422_12bit)) {
- if (!hdev->vend_id_hit)
- pos += snprintf(buf + pos,
- PAGE_SIZE, "422,12bit\n");
- }
- if (prxcap->dc_30bit) {
- if (!hdev->vend_id_hit)
- pos += snprintf(buf + pos,
- PAGE_SIZE, "422,10bit\n");
- pos += snprintf(buf + pos, PAGE_SIZE, "422,8bit\n");
- goto nextrgb;
+ if (prxcap->native_Mode & (1 << 5)) {
+ if (prxcap->dc_y444) {
+ if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2 ||
+ dv2->sup_10b_12b_444 == 0x2)
+ if (!hdev->vend_id_hit)
+ pos += snprintf(buf + pos, PAGE_SIZE,
+ "444,12bit\n");
+ if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1 ||
+ dv2->sup_10b_12b_444 == 0x1) {
+ if (!hdev->vend_id_hit)
+ pos += snprintf(buf + pos, PAGE_SIZE,
+ "444,10bit\n");
+ }
}
- } else {
- if (prxcap->native_Mode & (1 << 5))
- pos += snprintf(buf + pos, PAGE_SIZE, "444,8bit\n");
- if (prxcap->native_Mode & (1 << 4))
- pos += snprintf(buf + pos, PAGE_SIZE, "422,8bit\n");
+ pos += snprintf(buf + pos, PAGE_SIZE, "444,8bit\n");
+ }
+ /* y422, not check dc */
+ if (prxcap->native_Mode & (1 << 4)) {
+ pos += snprintf(buf + pos, PAGE_SIZE, "422,12bit\n");
+ pos += snprintf(buf + pos, PAGE_SIZE, "422,10bit\n");
+ pos += snprintf(buf + pos, PAGE_SIZE, "422,8bit\n");
}
-nextrgb:
#if 0
if (prxcap->dc_48bit)
pos += snprintf(buf + pos, PAGE_SIZE, "rgb,16bit\n");
int pos = 0;
struct hdmi_format_para *para = NULL;
+ pr_info("%s[%d] %s\n", __func__, __LINE__, cvalid_mode);
if (cvalid_mode[0]) {
valid_mode = pre_process_str(cvalid_mode);
if (valid_mode == 0) {
para = hdmi_tst_fmt_name(cvalid_mode, cvalid_mode);
}
if (para) {
- pr_info(SYS "sname = %s\n", para->sname);
+ if (para->sname)
+ pr_info(SYS "sname = %s\n", para->sname);
+ else
+ pr_info(SYS "name = %s\n", para->name);
pr_info(SYS "char_clk = %d\n", para->tmds_clk);
pr_info(SYS "cd = %d\n", para->cd);
pr_info(SYS "cs = %d\n", para->cs);
memset(cvalid_mode, 0, sizeof(cvalid_mode));
strncpy(cvalid_mode, buf, sizeof(cvalid_mode));
cvalid_mode[31] = '\0';
+ pr_info("%s[%d] %s\n", __func__, __LINE__, cvalid_mode);
return count;
}
return 0;
}
-static bool mode_is_sd(const char *mode)
+static enum vmode_e hdmitx_validate_vmode(char *mode, unsigned int frac)
{
- if (strncmp(mode, "480i", 4) == 0)
- return 1;
- if (strncmp(mode, "480p", 4) == 0)
- return 1;
- if (strncmp(mode, "576i", 4) == 0)
- return 1;
- if (strncmp(mode, "576p", 4) == 0)
- return 1;
- return 0;
-}
-
-static enum vmode_e hdmitx_validate_vmode(char *_mode, unsigned int frac)
-{
- struct vinfo_s *info = NULL;
- char mode[32] = {0};
- struct rx_cap *prxcap = &hdmitx_device.rxcap;
- unsigned int hort_size = 0;
- unsigned int vert_size = 0;
-
- strncpy(mode, _mode, sizeof(mode));
- mode[31] = 0;
-
-/* if the EDID horizontal size / vertical size equals to 4:3,
- * then consider the SD formats as 4:3
- */
- hort_size = prxcap->physcial_weight;
- vert_size = prxcap->physcial_height;
- if (vert_size && (hort_size * 3 / vert_size) == 4) {
- if (mode_is_sd(_mode)) {
- pr_info("%s[%d]\n", __func__, __LINE__);
- strcat(mode, "_4x3");
- mode[31] = 0;
- }
- }
-
- info = hdmi_get_valid_vinfo(mode);
+ struct vinfo_s *info = hdmi_get_valid_vinfo(mode);
if (info) {
/* //remove frac support for vout api
(hdev->backup_frac_rate_policy == hdev->frac_rate_policy) &&
(hdev->backup_phy_idx == hdev->phy_idx))
return 1;
- memcpy(hdev->backup_fmt_attr, hdev->fmt_attr, 16);
- hdev->backup_frac_rate_policy = hdev->frac_rate_policy;
- hdev->backup_phy_idx = hdev->phy_idx;
return 0;
}
static void hdmitx_get_edid(struct hdmitx_dev *hdev)
{
+ unsigned long flags = 0;
+
mutex_lock(&getedid_mutex);
/* TODO hdmitx_edid_ram_buffer_clear(hdev); */
hdev->hwop.cntlddc(hdev, DDC_RESET_EDID, 0);
hdev->hwop.cntlddc(hdev, DDC_EDID_GET_DATA, 1);
}
}
-
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
hdmitx_edid_clear(hdev);
hdmitx_edid_parse(hdev);
- hdmitx_edid_buf_compare_print(hdev);
if (hdev->hdr_priority) { /* clear dv_info */
struct dv_info *dv = &hdev->rxcap.dv_info;
memset(dv, 0, sizeof(struct dv_info));
pr_info("clear dv_info\n");
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
+ hdmitx_edid_buf_compare_print(hdev);
mutex_unlock(&getedid_mutex);
}
info->hw_sha_calculator_flag = 1;
}
+static void hdmitx_hdr_state_init(struct hdmitx_dev *hdev)
+{
+ enum hdmi_tf_type hdr_type = HDMI_NONE;
+ unsigned int colorimetry = 0;
+ unsigned int hdr_mode = 0;
+
+ hdr_type = hdmitx_get_cur_hdr_st();
+ colorimetry = hdev->hwop.cntlconfig(hdev, CONF_GET_AVI_BT2020, 0);
+ /* 1:standard HDR, 2:non-standard, 3:HLG, 0:other */
+ if (hdr_type == HDMI_HDR_SMPTE_2084) {
+ if (colorimetry == 1)
+ hdr_mode = 1;
+ else
+ hdr_mode = 2;
+ } else if (hdr_type == HDMI_HDR_HLG) {
+ if (colorimetry == 1)
+ hdr_mode = 3;
+ } else {
+ hdr_mode = 0;
+ }
+
+ hdev->hdmi_last_hdr_mode = hdr_mode;
+ hdev->hdmi_current_hdr_mode = hdr_mode;
+}
+
static int amhdmitx_device_init(struct hdmitx_dev *hdmi_dev)
{
if (hdmi_dev == NULL)
hdmitx_device.fmt_attr);
hdmitx_device.hdmi_last_hdr_mode = 0;
hdmitx_device.hdmi_current_hdr_mode = 0;
+ /* hdr/vsif packet status init, no need to get actual status,
+ * force to print function callback for confirmation.
+ */
hdmitx_device.hdr_transfer_feature = T_UNKNOWN;
hdmitx_device.hdr_color_feature = C_UNKNOWN;
hdmitx_device.colormetry = 0;
if (!hdmitx_device.topo_info)
pr_info("failed to alloc hdcp topo info\n");
hdmitx_init_parameters(&hdmitx_device.hdmi_info);
-
+ hdmitx_device.vid_mute_op = VIDEO_NONE_OP;
+ spin_lock_init(&hdmitx_device.edid_spinlock);
return 0;
}
hdmi_pdata = pdev->dev.platform_data;
#endif
hdmitx_device.irq_hpd = platform_get_irq_byname(pdev, "hdmitx_hpd");
-
- pr_info(SYS "hpd irq = %d\n", hdmitx_device.irq_hpd);
+ hdmitx_device.irq_viu1_vsync =
+ platform_get_irq_byname(pdev, "viu1_vsync");
+ pr_info(SYS "hpd irq = %d, viu1_vsync = %d\n",
+ hdmitx_device.irq_hpd, hdmitx_device.irq_viu1_vsync);
return ret;
}
vsem_init_cfg(&hdmitx_device);
HDMITX_Meson_Init(&hdmitx_device);
-
+ hdmitx_hdr_state_init(&hdmitx_device);
/* When init hdmi, clear the hdmitx module edid ram and edid buffer. */
hdmitx_edid_clear(&hdmitx_device);
hdmitx_edid_ram_buffer_clear(&hdmitx_device);
unsigned int hdmi_vic_4k_flag = 0;
static enum eotf_type ltype = EOTF_T_NULL;
static unsigned char ltmode = -1;
+ unsigned long flags = 0;
hdmi_debug();
- if (hdev->bist_lock)
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
+ if (hdev->bist_lock) {
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
+ }
if (!data)
memcpy(&vsif_debug_info.data, ¶,
!= DV_IEEE_OUI)) {
ltype = EOTF_T_NULL;
ltmode = -1;
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
if ((hdev->chip_type) < MESON_CPU_ID_GXL) {
pr_info("hdmitx: not support DolbyVision\n");
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
}
}
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
}
struct vout_device_s hdmitx_vdev = {
struct hdmitx_dev *hdev = &hdmitx_device;
unsigned char DRM_HB[3] = {0x87, 0x1, 26};
static unsigned char DRM_DB[26] = {0x0};
+ unsigned long flags = 0;
hdmi_debug();
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
if (data)
memcpy(&drm_config_data, data,
sizeof(struct master_display_info_s));
hdmitx_device.hwop.setpacket(HDMI_PACKET_DRM, NULL, NULL);
hdmitx_device.hwop.cntlconfig(&hdmitx_device,
CONF_AVI_BT2020, hdev->colormetry);
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
schedule_work(&hdev->work_hdr);
DRM_DB[0] = 0;
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
hdmitx_device.hwop.cntlconfig(&hdmitx_device,
CONF_AVI_BT2020, SET_AVI_BT2020);
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
return;
}
/* if sdr/hdr mode change ,notify uevent to userspace*/
if (hdev->hdmi_current_hdr_mode != hdev->hdmi_last_hdr_mode)
schedule_work(&hdev->work_hdr);
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
}
struct hdr10plus_para hdr10p_config_data;
para = hdmi_tst_fmt_name(cvalid_mode, cvalid_mode);
}
if (para) {
- pr_info(SYS "sname = %s\n", para->sname);
+ if (para->sname)
+ pr_info(SYS "sname = %s\n", para->sname);
+ else
+ pr_info(SYS "name = %s\n", para->name);
pr_info(SYS "char_clk = %d\n", para->tmds_clk);
pr_info(SYS "cd = %d\n", para->cd);
pr_info(SYS "cs = %d\n", para->cs);
static void hdmitx_get_edid(struct hdmitx_dev *hdev)
{
unsigned int num;
+ unsigned long flags = 0;
mutex_lock(&getedid_mutex);
/* TODO hdmitx_edid_ram_buffer_clear(hdev); */
hdev->hwop.cntlddc(hdev, DDC_EDID_GET_DATA, 1);
}
}
-
+ spin_lock_irqsave(&hdev->edid_spinlock, flags);
hdmitx_edid_clear(hdev);
hdmitx_edid_parse(hdev);
- hdmitx_edid_buf_compare_print(hdev);
if (hdev->hdr_priority) { /* clear dv_info */
struct dv_info *dv = &hdev->rxcap.dv_info;
memset(dv, 0, sizeof(struct dv_info));
}
+ spin_unlock_irqrestore(&hdev->edid_spinlock, flags);
+ hdmitx_edid_buf_compare_print(hdev);
mutex_unlock(&getedid_mutex);
}
void hdmitx_debugfs_init(void);
+struct dentry *hdmitx_get_dbgfsdentry(void);
+
#endif
hdmitx_dbg_files[i].name);
}
}
+
+struct dentry *hdmitx_get_dbgfsdentry(void)
+{
+ return hdmitx_dbgfs;
+}
hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG1, 0x67);
hdmitx_wr_reg(HDMITX_TOP_DISABLE_NULL, 0x7); /* disable NULL pkt */
hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG0, 0x13);
+ hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 1, 1, 1);
/* Enable skpclk to HDCP2.2 IP */
hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 7, 1);
/* Enable esmclk to HDCP2.2 IP */
return IRQ_HANDLED;
}
+static irqreturn_t vsync_intr_handler(int irq, void *dev)
+{
+ struct hdmitx_dev *hdev = (struct hdmitx_dev *)dev;
+
+ if (hdev->vid_mute_op != VIDEO_NONE_OP) {
+ hdev->hwop.cntlconfig(hdev,
+ CONF_VIDEO_MUTE_OP, hdev->vid_mute_op);
+ hdev->vid_mute_op = VIDEO_NONE_OP;
+ }
+
+ return IRQ_HANDLED;
+}
+
static unsigned long modulo(unsigned long a, unsigned long b)
{
if (a >= b)
r = request_irq(phdev->irq_hpd, &intr_handler,
IRQF_SHARED, "hdmitx",
(void *)phdev);
+ if (r != 0)
+ pr_info(SYS "can't request hdmitx irq\n");
+ r = request_irq(phdev->irq_viu1_vsync, &vsync_intr_handler,
+ IRQF_SHARED, "hdmi_vsync",
+ (void *)phdev);
+ if (r != 0)
+ pr_info(SYS "can't request viu1_vsync irq\n");
}
static void hdmitx_uninit(struct hdmitx_dev *phdev)
static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
unsigned long argv)
{
+ struct hdcp_obs_val *obs;
int i = 0;
+ int ret = 0;
unsigned char *tmp_char = NULL;
struct hdcprp14_topo *topo14 = NULL;
unsigned int val;
+ unsigned char tmp[5];
if ((cmd & CMD_DDC_OFFSET) != CMD_DDC_OFFSET) {
pr_err(HW "ddc: invalid cmd 0x%x\n", cmd);
}
switch (cmd) {
+ case DDC_HDCP14_SAVE_OBS:
+ obs = (struct hdcp_obs_val *)hdev;
+ ret = 0;
+ tmp[0] = hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS0) & 0xff;
+ tmp[1] = hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS1) & 0xff;
+ tmp[2] = hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS2) & 0xff;
+ tmp[3] = hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3) & 0xff;
+ tmp[4] = hdmitx_rd_reg(HDMITX_DWC_A_APIINTSTAT) & 0xff;
+ /* if current status is not equal last obs, then return 1 */
+ if (obs->obs0 != tmp[0]) {
+ obs->obs0 = tmp[0];
+ ret |= (1 << 0);
+ }
+ if (obs->obs1 != tmp[1]) {
+ obs->obs1 = tmp[1];
+ ret |= (1 << 1);
+ }
+ if (obs->obs2 != tmp[2]) {
+ obs->obs2 = tmp[2];
+ ret |= (1 << 2);
+ }
+ if (obs->obs3 != tmp[3]) {
+ obs->obs3 = tmp[3];
+ ret |= (1 << 3);
+ }
+ if (obs->intstat != tmp[4]) {
+ obs->intstat = tmp[4];
+ ret |= (1 << 4);
+ }
+ return ret;
case DDC_RESET_EDID:
hdmitx_wr_reg(HDMITX_DWC_I2CM_SOFTRSTZ, 0);
memset(hdev->tmp_edid_buf, 0, ARRAY_SIZE(hdev->tmp_edid_buf));
if (argv == CLR_AVI_BT2020)
hdmitx_set_avi_colorimetry(hdev->para);
break;
+ case CONF_GET_AVI_BT2020:
+ if (((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF1) & 0xC0) == 0xC0) &&
+ ((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF2) & 0x70) == 0x60))
+ ret = 1;
+ else
+ ret = 0;
+ break;
case CONF_CLR_DV_VS10_SIG:
/* if current is DV/VSIF.DOVI, next will swith to HDR, need set
* Dolby_Vision_VS10_Signal_Type as 0
data32 |= (0 << 0);
hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF3, data32);
- hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, (para->vic & HDMITX_VIC_MASK));
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, vic & HDMITX_VIC_MASK);
/* For VESA modes, set VIC as 0 */
if (para->vic >= HDMITX_VESA_OFFSET) {
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __TXLX_REG_H__
-#define __TXLX_REG_H__
-#include "reg_ops.h"
-
-#define RESET0_REGISTER 0x401
-#define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER)
-#define RESET2_REGISTER 0x403
-#define P_RESET2_REGISTER RESET_CBUS_REG_ADDR(RESET2_REGISTER)
-
-#define ISA_DEBUG_REG0 0x3c00
-#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
-
-#endif
unsigned int vid_clk_div_reg;
unsigned int vid2_clk_ctrl_reg;
unsigned int vid2_clk_div_reg;
+ unsigned int vid_clk_mux;
+ unsigned int vid2_clk_mux;
void (*clktree_probe)(struct device *dev);
void (*clktree_remove)(struct device *dev);
}
if (dummy_encp_index == 0) {
+ if (dummy_venc_data->vid2_clk_mux == 0xff) {
+ VOUTERR("%s: invalid vid2_clk, unsupport dummy_panel\n",
+ __func__);
+ return;
+ }
if (flag) {
temp = vout_hiu_getb(dummy_venc_data->vid2_clk_div_reg,
ENCL_CLK_SEL, 4);
0xf, VCLK_XD0, 8);
udelay(5);
vout_hiu_setb(dummy_venc_data->vid_clk_ctrl_reg,
- 6, VCLK_CLK_IN_SEL, 3);
+ dummy_venc_data->vid_clk_mux,
+ VCLK_CLK_IN_SEL, 3);
vout_hiu_setb(dummy_venc_data->vid_clk_ctrl_reg,
1, VCLK_EN0, 1);
udelay(5);
static void dummy_enci_clk_ctrl(int flag)
{
+ unsigned int reg_ctrl, reg_div, reg_ctrl2;
+ unsigned int clk_mux, clk_sel;
+
if (!dummy_venc_data) {
VOUTERR("%s: no dummy_venc_data\n", __func__);
return;
}
+ if (dummy_venc_data->vid2_clk_mux == 0xff) {
+ reg_ctrl = dummy_venc_data->vid_clk_ctrl_reg;
+ reg_div = dummy_venc_data->vid_clk_div_reg;
+ clk_mux = dummy_venc_data->vid_clk_mux;
+ clk_sel = 0;
+ } else {
+ reg_ctrl = dummy_venc_data->vid2_clk_ctrl_reg;
+ reg_div = dummy_venc_data->vid2_clk_div_reg;
+ clk_mux = dummy_venc_data->vid2_clk_mux;
+ clk_sel = 8;
+ }
+ reg_ctrl2 = dummy_venc_data->vid_clk_ctrl2_reg;
if (flag) {
/* clk source sel: fckl_div5 */
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 0xf, VCLK2_XD, 8);
+ vout_hiu_setb(reg_div, 0xf, VCLK2_XD, 8);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 6, VCLK2_CLK_IN_SEL, 3);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_EN, 1);
+ vout_hiu_setb(reg_ctrl, clk_mux, VCLK2_CLK_IN_SEL, 3);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_EN, 1);
udelay(5);
vout_hiu_setb(dummy_venc_data->vid_clk_div_reg,
- 8, ENCI_CLK_SEL, 4);
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 1, VCLK2_XD_EN, 1);
+ clk_sel, ENCI_CLK_SEL, 4);
+ vout_hiu_setb(reg_div, 1, VCLK2_XD_EN, 1);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_DIV1_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_SOFT_RST, 1);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_DIV1_EN, 1);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_SOFT_RST, 1);
udelay(10);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_SOFT_RST, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_SOFT_RST, 1);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid_clk_ctrl2_reg,
- 1, ENCI_GATE_VCLK, 1);
+ vout_hiu_setb(reg_ctrl2, 1, ENCI_GATE_VCLK, 1);
} else {
- vout_hiu_setb(dummy_venc_data->vid_clk_ctrl2_reg,
- 0, ENCI_GATE_VCLK, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_DIV1_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 0, VCLK2_XD_EN, 1);
+ vout_hiu_setb(reg_ctrl2, 0, ENCI_GATE_VCLK, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_DIV1_EN, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_EN, 1);
+ vout_hiu_setb(reg_div, 0, VCLK2_XD_EN, 1);
}
}
static void dummy_encl_clk_ctrl(int flag)
{
+ unsigned int reg_ctrl, reg_div, reg_ctrl2;
+ unsigned int clk_mux, clk_sel;
+
if (!dummy_venc_data) {
VOUTERR("%s: no dummy_venc_data\n", __func__);
return;
}
+ if (dummy_venc_data->vid2_clk_mux == 0xff) {
+ reg_ctrl = dummy_venc_data->vid_clk_ctrl_reg;
+ reg_div = dummy_venc_data->vid_clk_div_reg;
+ clk_mux = dummy_venc_data->vid_clk_mux;
+ clk_sel = 0;
+ } else {
+ reg_ctrl = dummy_venc_data->vid2_clk_ctrl_reg;
+ reg_div = dummy_venc_data->vid2_clk_div_reg;
+ clk_mux = dummy_venc_data->vid2_clk_mux;
+ clk_sel = 8;
+ }
+ reg_ctrl2 = dummy_venc_data->vid_clk_ctrl2_reg;
if (flag) {
/* clk source sel: fckl_div5 */
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 0xf, VCLK2_XD, 8);
+ vout_hiu_setb(reg_div, 0xf, VCLK2_XD, 8);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 6, VCLK2_CLK_IN_SEL, 3);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_EN, 1);
+ vout_hiu_setb(reg_ctrl, clk_mux, VCLK2_CLK_IN_SEL, 3);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_EN, 1);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 8, ENCL_CLK_SEL, 4);
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 1, VCLK2_XD_EN, 1);
+ vout_hiu_setb(dummy_venc_data->vid_clk_div_reg,
+ clk_sel, ENCL_CLK_SEL, 4);
+ vout_hiu_setb(reg_div, 1, VCLK2_XD_EN, 1);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_DIV1_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 1, VCLK2_SOFT_RST, 1);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_DIV1_EN, 1);
+ vout_hiu_setb(reg_ctrl, 1, VCLK2_SOFT_RST, 1);
udelay(10);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_SOFT_RST, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_SOFT_RST, 1);
udelay(5);
- vout_hiu_setb(dummy_venc_data->vid_clk_ctrl2_reg,
- 1, ENCL_GATE_VCLK, 1);
+ vout_hiu_setb(reg_ctrl2, 1, ENCL_GATE_VCLK, 1);
} else {
- vout_hiu_setb(dummy_venc_data->vid_clk_ctrl2_reg,
- 0, ENCL_GATE_VCLK, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_DIV1_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_ctrl_reg,
- 0, VCLK2_EN, 1);
- vout_hiu_setb(dummy_venc_data->vid2_clk_div_reg,
- 0, VCLK2_XD_EN, 1);
+ vout_hiu_setb(reg_ctrl2, 0, ENCL_GATE_VCLK, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_DIV1_EN, 1);
+ vout_hiu_setb(reg_ctrl, 0, VCLK2_EN, 1);
+ vout_hiu_setb(reg_div, 0, VCLK2_XD_EN, 1);
}
}
.vid_clk_div_reg = HHI_VID_CLK_DIV,
.vid2_clk_ctrl_reg = HHI_VIID_CLK_CNTL,
.vid2_clk_div_reg = HHI_VIID_CLK_DIV,
+ .vid_clk_mux = 6, /* fckl_div5 */
+ .vid2_clk_mux = 6, /* fckl_div5 */
+
+ .clktree_probe = dummy_venc_clktree_probe,
+ .clktree_remove = dummy_venc_clktree_remove,
+ .encp_clk_gate_switch = dummy_encp_clk_gate_switch,
+ .enci_clk_gate_switch = dummy_enci_clk_gate_switch,
+ .encl_clk_gate_switch = dummy_encl_clk_gate_switch,
+};
+
+static struct dummy_venc_data_s dummy_venc_match_data_gxl = {
+ .vid_clk_ctrl_reg = HHI_VID_CLK_CNTL,
+ .vid_clk_ctrl2_reg = HHI_VID_CLK_CNTL2,
+ .vid_clk_div_reg = HHI_VID_CLK_DIV,
+ .vid2_clk_ctrl_reg = HHI_VIID_CLK_CNTL,
+ .vid2_clk_div_reg = HHI_VIID_CLK_DIV,
+ .vid_clk_mux = 3, /* fckl_div5 */
+ .vid2_clk_mux = 0xff, /* invalid */
.clktree_probe = dummy_venc_clktree_probe,
.clktree_remove = dummy_venc_clktree_remove,
.vid_clk_div_reg = CLKCTRL_VID_CLK_DIV,
.vid2_clk_ctrl_reg = CLKCTRL_VIID_CLK_CTRL,
.vid2_clk_div_reg = CLKCTRL_VIID_CLK_DIV,
+ .vid_clk_mux = 6, /* fckl_div5 */
+ .vid2_clk_mux = 6, /* fckl_div5 */
.clktree_probe = NULL,
.clktree_remove = NULL,
.compatible = "amlogic, dummy_venc",
.data = &dummy_venc_match_data,
},
+ {
+ .compatible = "amlogic, dummy_venc-gxl",
+ .data = &dummy_venc_match_data_gxl,
+ },
+ {
+ .compatible = "amlogic, dummy_venc-gxlx",
+ .data = &dummy_venc_match_data_gxl,
+ },
{
.compatible = "amlogic, dummy_venc_sc2",
.data = &dummy_venc_match_data_new,
pdata->para.hs4[temp_index].delay1 = delay1;
pdata->para.hs4[temp_index].delay2 = delay2;
pdata->para.hs4[temp_index].intf3 = intf3;
- pdata->para.hs4[temp_index].flag = 1;
- pdata->para.magic = 0x00487e44; /*E~K\0*/
- pdata->para.version = 1;
+ pdata->para.hs4[temp_index].flag = TUNED_FLAG;
+ pdata->para.magic = TUNED_MAGIC; /*E~K\0*/
+ pdata->para.version = TUNED_VERSION;
checksum = _para_checksum_calc(para);
pdata->para.checksum = checksum;
return 0;
}
- if (para->hs4[temp_index].flag == 0) {
+ if (para->magic != TUNED_MAGIC) {
+ pr_warn("[%s] magic is not match\n", __func__);
+ return 0;
+ }
+
+ if (para->version != TUNED_VERSION) {
+ pr_warn("[%s] VERSION is not match\n", __func__);
+ return 0;
+ }
+
+ if (para->hs4[temp_index].flag != TUNED_FLAG) {
pr_info("current temperature %d degree not tuning yet\n",
temperature / 1000);
return 0;
struct amlsd_host *host = pdata->host;
struct sd_emmc_status *ista = (struct sd_emmc_status *)&vstat;
- if (host->data->chip_type == MMC_CHIP_SC2)
- return 0;
if (pdata->no_sduart)
return 0;
};
struct amlsd_host *host = pdata->host;
- if (host->data->chip_type == MMC_CHIP_SC2)
- return 0;
pdata->is_sduart = on;
mutex_lock(&host->pinmux_lock);
pc = aml_devm_pinctrl_get_select(host, name[on]);
int i;
struct amlsd_host *host = pdata->host;
- if (host->data->chip_type == MMC_CHIP_SC2)
- return;
for (i = 0; i < 100; i++) {
mutex_lock(&host->pinmux_lock);
pc = aml_devm_pinctrl_get_select(host,
if (aml_chip) {
mtd = aml_chip->mtd;
if (mtd) {
- nand_release(mtd);
+ nand_release(mtd_to_nand(mtd));
kfree(mtd);
}
kfree(aml_chip);
struct clk *clk;
struct clk *phy_clk;
struct clk *bus_clk;
+ struct clk *dev_clk;
int pcie_num;
int gpio_type;
u32 port_num;
writel(val, amlogic_pcie->phy->reset_base);
}
}
+
+ amlogic_pcie->dev_clk = devm_clk_get(dev, "pcie_hcsl");
+ if (IS_ERR(amlogic_pcie->dev_clk)) {
+ dev_err(dev, "Failed to get pcie pcie_hcsl clock\n");
+ ret = PTR_ERR(amlogic_pcie->dev_clk);
+ goto fail_pcie_phy;
+ }
+
+ ret = clk_prepare_enable(amlogic_pcie->dev_clk);
+ if (ret)
+ goto fail_pcie_phy;
+
amlogic_pcie->phy_clk = devm_clk_get(dev, "pcie_phy");
if (IS_ERR(amlogic_pcie->phy_clk)) {
dev_err(dev, "Failed to get pcie pcie_phy clock\n");
ret = PTR_ERR(amlogic_pcie->phy_clk);
- goto fail_pcie;
+ goto fail_pcie_hcsl;
}
ret = clk_prepare_enable(amlogic_pcie->phy_clk);
if (ret)
- goto fail_pcie_phy;
+ goto fail_pcie_hcsl;
amlogic_pcie->bus_clk = devm_clk_get(dev, "pcie_refpll");
if (IS_ERR(amlogic_pcie->bus_clk)) {
dev_err(dev, "Failed to get pcie pcie_refpll clock\n");
clk_disable_unprepare(amlogic_pcie->bus_clk);
fail_pcie:
clk_disable_unprepare(amlogic_pcie->phy_clk);
+fail_pcie_hcsl:
+ clk_disable_unprepare(amlogic_pcie->dev_clk);
port_num--;
fail_pcie_phy:
return ret;
usleep_range(500, 510);
+ clk_disable_unprepare(amlogic_pcie->dev_clk);
clk_disable_unprepare(amlogic_pcie->clk);
clk_disable_unprepare(amlogic_pcie->phy_clk);
usleep_range(500, 510);
clk_prepare_enable(amlogic_pcie->phy_clk);
clk_prepare_enable(amlogic_pcie->clk);
+ clk_prepare_enable(amlogic_pcie->dev_clk);
usleep_range(500, 510);
if (amlogic_pcie->pcie_num == 1) {
else if (strcmp(cmd, "uboot_suspend") == 0)
reboot_reason = MESON_UBOOT_SUSPEND;
else if (strcmp(cmd, "quiescent") == 0 ||
- strcmp(cmd, ",quiescent") == 0)
+ strcmp(cmd, "userrequested,recovery,quiescent") == 0 ||
+ strcmp(cmd, ",quiescent") == 0)
reboot_reason = MESON_QUIESCENT_REBOOT;
else if (strcmp(cmd, "recovery,quiescent") == 0 ||
strcmp(cmd, "factory_reset,quiescent") == 0 ||
static long phy_in_base;
static long phy_out_base;
static unsigned long secmon_start_virt;
+static unsigned int mem_size;
#ifdef CONFIG_ARM64
#define IN_SIZE 0x1000
return 0;
if ((addr >= secmon_start_virt) &&
- (addr <= (secmon_start_virt + RESERVE_MEM_SIZE)))
+ (addr <= (secmon_start_virt + mem_size)))
return 1;
return 0;
struct device_node *np = pdev->dev.of_node;
unsigned int id;
int ret;
- int mem_size;
struct page *page;
if (!of_property_read_u32(np, "in_base_func", &id))
// unsigned long freq_cpu = clk_get_rate(aml_smartcard_clk)/1000*DIV_SMC;
pr_error("hw set param\n");
+ clk_set_rate(aml_smartcard_clk, smc->param.freq * 1000);
v = SMC_READ_REG(REG0);
reg0 = (struct smccard_hw_reg0 *)&v;
- reg0->etu_divider = smc->param.f / smc->param.d - 1;
+ reg0->etu_divider = ETU_DIVIDER_CLOCK_HZ * smc->param.f /
+ (smc->param.d * smc->param.freq) - 1;
SMC_WRITE_REG(REG0, v);
pr_error("REG0: 0x%08lx\n", v);
pr_error("f :%d\n", smc->param.f);
reg0->rst_level = RESET_ENABLE;
// reg0->io_level = 0;
reg0->recv_fifo_threshold = FIFO_THRESHOLD_DEFAULT;
- reg0->etu_divider = smc->param.f / smc->param.d - 1;
+ reg0->etu_divider = ETU_DIVIDER_CLOCK_HZ * smc->param.f
+ / (smc->param.d * smc->param.freq) - 1;
reg0->first_etu_offset = 5;
SMC_WRITE_REG(REG0, v);
smc_clk_enable(reg0->clk_en);
sc_reg0_reg->rst_level = RESET_ENABLE;
sc_reg0_reg->clk_en = 1;
- sc_reg0_reg->etu_divider =
- smc->param.f / smc->param.d - 1;
+ sc_reg0_reg->etu_divider = ETU_DIVIDER_CLOCK_HZ *
+ smc->param.f / (smc->param.d * smc->param.freq) - 1;
SMC_WRITE_REG(REG0, sc_reg0);
smc_clk_enable(sc_reg0_reg->clk_en);
// sc_reg0_reg->start_atr_en = 1;
sc_reg0_reg->start_atr = 1;
sc_reg0_reg->enable = 1;
- sc_reg0_reg->etu_divider =
- smc->param.f / smc->param.d - 1;
+ sc_reg0_reg->etu_divider = ETU_DIVIDER_CLOCK_HZ *
+ smc->param.f / (smc->param.d * smc->param.freq) - 1;
SMC_WRITE_REG(REG0, sc_reg0);
#ifdef RST_FROM_PIO
long cr;
pr_dbg("read %d bytes\n", ret);
+ spin_unlock_irqrestore(&smc->slock, flags);
if (cnt >= ret) {
cr = copy_to_user(buff, smc->recv_buf + start, ret);
} else {
cr = copy_to_user(buff, smc->recv_buf + start, cnt);
cr = copy_to_user(buff + cnt, smc->recv_buf, cnt1);
}
+ spin_lock_irqsave(&smc->slock, flags);
_atomic_wrap_add(&smc->recv_start, ret, RECV_BUF_SIZE);
}
spin_unlock_irqrestore(&smc->slock, flags);
int cnt = SEND_BUF_SIZE - start;
long cr;
+ spin_unlock_irqrestore(&smc->slock, flags);
if (cnt >= ret) {
cr = copy_from_user(smc->send_buf + start, buff, ret);
} else {
cr = copy_from_user(smc->send_buf + start, buff, cnt);
cr = copy_from_user(smc->send_buf, buff + cnt, cnt1);
}
+ spin_lock_irqsave(&smc->slock, flags);
_atomic_wrap_add(&smc->send_start, ret, SEND_BUF_SIZE);
}
/*01: clk input from pad*/
/*10: smc clk generated internally and sent to the smartcard pad*/
/*11: no clock*/
-#define ETU_CLK_SEL 2
+#define ETU_CLK_SEL 0
#define ATR_HOLDOFF_EN 1
#define ATR_CLK_MUX_DEFAULT 4
#define ATR_HOLDOFF_TCNT_DEFAULT 255
--- /dev/null
+config AMLOGIC_SOC_INFO
+ bool "Amlogic soc"
+ default n
+ help
+ say y to enable Amlogic chipid driver.
+
--- /dev/null
+obj-$(CONFIG_AMLOGIC_SOC_INFO) += socdata.o nocsdata.o
+
--- /dev/null
+/*
+ * drivers/amlogic/soc_info/nocsdata.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/cdev.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/scatterlist.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/ioctl.h>
+#include <linux/of.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/cma.h>
+#include <linux/sysfs.h>
+#include <linux/random.h>
+#include <linux/amlogic/secmon.h>
+#include <linux/arm-smccc.h>
+#include "soc_info.h"
+
+void __iomem *socinfo_sharemem_base;
+static long meson64_efuse_fn_smc(struct efuse_hal_api_arg *arg)
+{
+ long ret;
+ unsigned int cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt);
+ struct arm_smccc_res res;
+
+ switch (arg->cmd) {
+ case EFUSE_HAL_NOCS_API_READ:
+ cmd = read_nocsdata_cmd;
+ socinfo_sharemem_base = get_secmon_sharemem_output_base();
+ if (!socinfo_sharemem_base)
+ return -1;
+ break;
+ case EFUSE_HAL_NOCS_API_WRITE:
+ cmd = write_nocsdata_cmd;
+ socinfo_sharemem_base = get_secmon_sharemem_input_base();
+ if (!socinfo_sharemem_base)
+ return -1;
+ break;
+ default:
+ return -1;
+ }
+ offset = arg->offset;
+ size = arg->size;
+ sharemem_mutex_lock();
+ if (arg->cmd == EFUSE_HAL_NOCS_API_WRITE)
+ memcpy((void *)socinfo_sharemem_base,
+ (const void *)arg->buffer, size);
+
+ asm __volatile__("" : : : "memory");
+
+ arm_smccc_smc(cmd, offset, size, 0, 0, 0, 0, 0, &res);
+ ret = res.a0;
+ *retcnt = res.a0;
+ if ((arg->cmd == EFUSE_HAL_NOCS_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer,
+ (const void *)socinfo_sharemem_base, ret);
+ sharemem_mutex_unlock();
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+static int meson64_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ struct cpumask org_cpumask;
+
+ if (!arg)
+ return -1;
+
+ cpumask_copy(&org_cpumask, ¤t->cpus_allowed);
+ set_cpus_allowed_ptr(current, cpumask_of(0));
+ ret = meson64_efuse_fn_smc(arg);
+ set_cpus_allowed_ptr(current, &org_cpumask);
+ return ret;
+}
+
+ssize_t nocsdata_read(char *buf, size_t count, loff_t *ppos)
+{
+ unsigned int pos = *ppos;
+
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+ int ret;
+
+ arg.cmd = EFUSE_HAL_NOCS_API_READ;
+ arg.offset = pos;
+ arg.size = count;
+ arg.buffer = (unsigned long)buf;
+ arg.retcnt = (unsigned long)&retcnt;
+ ret = meson64_trustzone_efuse(&arg);
+ if (ret == 0) {
+ *ppos += retcnt;
+ return retcnt;
+ }
+ pr_debug("%s:%s:%d: read error!!!\n",
+ __FILE__, __func__, __LINE__);
+ return ret;
+}
+
+ssize_t nocsdata_write(const char *buf, size_t count, loff_t *ppos)
+{
+ unsigned int pos = *ppos;
+
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+ int ret;
+
+ arg.cmd = EFUSE_HAL_NOCS_API_WRITE;
+ arg.offset = pos;
+ arg.size = count;
+ arg.buffer = (unsigned long)buf;
+ arg.retcnt = (unsigned long)&retcnt;
+
+ ret = meson64_trustzone_efuse(&arg);
+ if (ret == 0) {
+ *ppos = retcnt;
+ return retcnt;
+ }
+ pr_debug("%s:%s:%d: write error!!!\n",
+ __FILE__, __func__, __LINE__);
+ return ret;
+}
--- /dev/null
+/*
+ * drivers/amlogic/soc_info/soc_info.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __SOC_INFO_H
+#define __SOC_INFO_H
+
+#define SOCDATA_DEVICE_NAME "socdata"
+#define SOCDATA_CLASS_NAME "socdata"
+#define NOCS_DATA_LENGTH (48)
+#define CMD_SOCVER1_DATA _IO('s', 0x01)
+#define CMD_SOCVER2_DATA _IO('s', 0x02)
+#define CMD_POC_DATA _IO('s', 0x03)
+#define CMD_NOCSDATA_READ _IO('s', 0x04)
+#define CMD_NOCSDATA_WRITE _IO('s', 0x05)
+
+#define EFUSE_HAL_NOCS_API_READ 4
+#define EFUSE_HAL_NOCS_API_WRITE 5
+
+extern unsigned int read_nocsdata_cmd;
+extern unsigned int write_nocsdata_cmd;
+ssize_t nocsdata_read(char *buf, size_t count, loff_t *ppos);
+ssize_t nocsdata_write(const char *buf, size_t count, loff_t *ppos);
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer;
+ unsigned long retcnt;
+};
+#endif
--- /dev/null
+/*
+ * drivers/amlogic/soc_info/socdata.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/cdev.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/scatterlist.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/ioctl.h>
+#include <linux/of.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/of_address.h>
+#include <linux/cma.h>
+#include <linux/sysfs.h>
+#include <linux/random.h>
+#include <linux/amlogic/secmon.h>
+#include "soc_info.h"
+
+unsigned int read_nocsdata_cmd;
+unsigned int write_nocsdata_cmd;
+static void __iomem *soc_ver1_addr, *soc_poc_addr;
+
+struct socdata_dev_t {
+ struct cdev cdev;
+ dev_t devno;
+};
+
+static struct socdata_dev_t *socdata_devp;
+
+static int socdata_open(struct inode *inode, struct file *file)
+{
+ struct socdata_dev_t *devp;
+
+ devp = container_of(inode->i_cdev, struct socdata_dev_t, cdev);
+ file->private_data = devp;
+ return 0;
+}
+
+static long socdata_unlocked_ioctl(struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ unsigned long ret = 0;
+ void __user *argp = (void __user *)arg;
+ unsigned long __user *soc_info = argp;
+ unsigned char info[NOCS_DATA_LENGTH];
+ long long int offset = 0;
+
+ switch (cmd) {
+ case CMD_POC_DATA:
+ if (put_user(readl(soc_poc_addr), soc_info))
+ return -EFAULT;
+ break;
+ case CMD_SOCVER1_DATA:
+ if (put_user(readl(soc_ver1_addr), soc_info))
+ return -EFAULT;
+ break;
+ case CMD_SOCVER2_DATA:
+ if (put_user(readl(soc_ver1_addr + 4), soc_info))
+ return -EFAULT;
+ break;
+ case CMD_NOCSDATA_READ:
+ nocsdata_read(info, NOCS_DATA_LENGTH, &offset);
+ ret = copy_to_user(argp, info, sizeof(info));
+ if (ret != 0) {
+ pr_debug("%s:%d,copy_to_user fail\n",
+ __func__, __LINE__);
+ return ret;
+ }
+ break;
+ case CMD_NOCSDATA_WRITE:
+ ret = copy_from_user(info, argp, (NOCS_DATA_LENGTH - 28));
+ if (ret != 0) {
+ pr_debug("%s:%d,copy_from_user fail\n",
+ __func__, __LINE__);
+ return ret;
+ }
+ if (nocsdata_write(info, (NOCS_DATA_LENGTH - 28), &offset))
+ return -EFAULT;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return ret;
+}
+
+#ifdef CONFIG_COMPAT
+static long socdata_compat_ioctl(struct file *filp,
+ unsigned int cmd, unsigned long args)
+{
+ unsigned long ret;
+
+ args = (unsigned long)compat_ptr(args);
+ ret = socdata_unlocked_ioctl(filp, cmd, args);
+
+ return ret;
+}
+#endif
+
+static const struct file_operations socdata_fops = {
+ .owner = THIS_MODULE,
+ .open = socdata_open,
+ .unlocked_ioctl = socdata_unlocked_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = socdata_compat_ioctl,
+#endif
+};
+
+static struct class socdata_class = {
+ .name = SOCDATA_CLASS_NAME,
+};
+
+static int aml_socdata_probe(struct platform_device *pdev)
+{
+ int ret = -1;
+ struct device *devp;
+
+ socdata_devp = devm_kzalloc(&pdev->dev,
+ sizeof(struct socdata_dev_t), GFP_KERNEL);
+ if (!socdata_devp) {
+ ret = -ENOMEM;
+ dev_err(&pdev->dev, "socdata: failed to allocate memory\n ");
+ goto out;
+ }
+
+ soc_ver1_addr = of_iomap(pdev->dev.of_node, 0);
+ soc_poc_addr = of_iomap(pdev->dev.of_node, 1);
+
+ if (of_property_read_u32(pdev->dev.of_node, "read_nocsdata_cmd",
+ &read_nocsdata_cmd)) {
+ dev_err(&pdev->dev, "please config read nocsdata cmd\n");
+ return -1;
+ }
+ if (of_property_read_u32(pdev->dev.of_node, "write_nocsdata_cmd",
+ &write_nocsdata_cmd)) {
+ dev_err(&pdev->dev, "please config write nocsdata cmd\n");
+ return -1;
+ }
+
+ ret = alloc_chrdev_region(&socdata_devp->devno, 0, 1,
+ SOCDATA_DEVICE_NAME);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "socdata: failed to allocate major number\n ");
+ ret = -ENODEV;
+ goto error1;
+ }
+ dev_info(&pdev->dev, "socdata_devno:%x\n", socdata_devp->devno);
+ ret = class_register(&socdata_class);
+ if (ret) {
+ dev_err(&pdev->dev, "socdata: failed to register class\n ");
+ goto error2;
+ }
+
+ /* connect the file operations with cdev */
+ cdev_init(&socdata_devp->cdev, &socdata_fops);
+ socdata_devp->cdev.owner = THIS_MODULE;
+ /* connect the major/minor number to the cdev */
+ ret = cdev_add(&socdata_devp->cdev, socdata_devp->devno, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "socdata: failed to add device\n");
+ goto error3;
+ }
+ devp = device_create(&socdata_class, NULL, socdata_devp->devno,
+ NULL, SOCDATA_DEVICE_NAME);
+ if (IS_ERR(devp)) {
+ dev_err(&pdev->dev, "socdata: failed to create device node\n");
+ ret = PTR_ERR(devp);
+ goto error4;
+ }
+ return 0;
+
+error4:
+ cdev_del(&socdata_devp->cdev);
+error3:
+ class_unregister(&socdata_class);
+error2:
+ unregister_chrdev_region(socdata_devp->devno, 1);
+error1:
+// devm_kfree(&(pdev->dev), socdata_devp);
+out:
+ return ret;
+}
+
+static int aml_socdata_remove(struct platform_device *pdev)
+{
+ unregister_chrdev_region(socdata_devp->devno, 1);
+ device_destroy(&socdata_class, socdata_devp->devno);
+ cdev_del(&socdata_devp->cdev);
+ class_unregister(&socdata_class);
+ return 0;
+}
+
+static const struct of_device_id meson_socdata_dt_match[] = {
+ { .compatible = "amlogic, socdata",
+ },
+ {},
+};
+
+static struct platform_driver aml_socdata_driver = {
+ .probe = aml_socdata_probe,
+ .remove = aml_socdata_remove,
+ .driver = {
+ .name = SOCDATA_DEVICE_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = meson_socdata_dt_match,
+ },
+};
+
+module_platform_driver(aml_socdata_driver);
+
+MODULE_DESCRIPTION("AMLOGIC socdata driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("<huaihong.lei@amlogic.com>");
-obj-$(CONFIG_AMLOGIC_TEE) += tee.o
+obj-$(CONFIG_AMLOGIC_TEE) += tee.o tee_demux.o
--- /dev/null
+/*
+ * drivers/amlogic/tee/tee_demux.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/arm-smccc.h>
+#include <linux/platform_device.h>
+
+#include <linux/amlogic/secmon.h>
+#include <linux/amlogic/tee.h>
+#include <linux/amlogic/tee_demux.h>
+#include <asm/cputype.h>
+#include <linux/printk.h>
+
+static void __iomem *dmx_shm_input;
+static void __iomem *dmx_shm_output;
+
+static int get_share_memory(void)
+{
+ if (!dmx_shm_input)
+ dmx_shm_input = get_secmon_sharemem_input_base();
+
+ if (!dmx_shm_output)
+ dmx_shm_output = get_secmon_sharemem_output_base();
+
+ if (dmx_shm_input && dmx_shm_output)
+ return 0;
+
+ return -1;
+}
+
+int tee_demux_set(enum tee_dmx_cmd cmd, void *data, u32 len)
+{
+ struct arm_smccc_res res;
+
+ if (!data || !len || get_share_memory())
+ return -1;
+
+ sharemem_mutex_lock();
+ memcpy((void *)dmx_shm_input, (const void *)data, len);
+ arm_smccc_smc(0x82000076, cmd, len, 0, 0, 0, 0, 0, &res);
+ sharemem_mutex_unlock();
+
+ return res.a0;
+}
+EXPORT_SYMBOL(tee_demux_set);
+
+int tee_demux_get(enum tee_dmx_cmd cmd,
+ void *in, u32 in_len, void *out, u32 out_len)
+{
+ struct arm_smccc_res res;
+
+ if (!out || !out_len || get_share_memory())
+ return -1;
+
+ sharemem_mutex_lock();
+ if (in && in_len)
+ memcpy((void *)dmx_shm_input, (const void *)in, in_len);
+ arm_smccc_smc(0x82000076, cmd, in_len, out_len, 0, 0, 0, 0, &res);
+ if (!res.a0)
+ memcpy((void *)out, (void *)dmx_shm_output, out_len);
+ sharemem_mutex_unlock();
+
+ return res.a0;
+}
+EXPORT_SYMBOL(tee_demux_get);
uByte bDescriptorType;
uWord bString[127];
} UPACKED usb_string_descriptor_t;
+#ifdef CONFIG_AMLOGIC_SYNC_20210524
+#undef USB_MAX_STRING_LEN
+#endif
#define USB_MAX_STRING_LEN 128
#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
if (!usb_power) {
set_wifi_power(is_power);
WIFI_INFO("Set %s power on !\n", (shift ? "WiFi":"BT"));
+ msleep(200);
sdio_notify(1);
sdio_reinit();
}
usb_power &= ~(1 << shift);
if (!usb_power) {
set_wifi_power(is_power);
+ msleep(200);
WIFI_INFO("Set %s power down\n", (shift ? "WiFi":"BT"));
sdio_notify(0);
}
unsigned int blklen;
/* the actual rbtree node holding this block */
struct rb_node node;
-} __attribute__ ((packed));
+};
struct regcache_rbtree_ctx {
struct rb_root root;
struct ion_codec_mm_heap {
struct ion_heap heap;
- int max_can_alloc_size;
- int alloced_size;
+ unsigned long max_can_alloc_size;
+ unsigned long alloced_size;
+ /* protect size account */
+ struct mutex mutex;
};
#define CODEC_MM_ION "ION"
unsigned long offset;
if (codec_heap->alloced_size + size > codec_heap->max_can_alloc_size) {
- pr_debug(
- "ion_codec_mm_allocate failed out size %ld,alloced %d\n",
+ pr_err(
+ "ion_codec_mm_allocate failed out size %lu,alloced %lu\n",
size,
codec_heap->alloced_size);
+ return ION_CODEC_MM_ALLOCATE_FAIL;
}
offset = codec_mm_alloc_for_dma(
pr_err("ion_codec_mm_allocate failed out size %d\n", (int)size);
return ION_CODEC_MM_ALLOCATE_FAIL;
}
+ mutex_lock(&codec_heap->mutex);
codec_heap->alloced_size += size;
+ mutex_unlock(&codec_heap->mutex);
return offset;
}
if (addr == ION_CODEC_MM_ALLOCATE_FAIL)
return;
- codec_mm_free_for_dma(CODEC_MM_ION, addr);
- codec_heap->alloced_size -= size;
+ mutex_lock(&codec_heap->mutex);
+ if (!codec_mm_free_for_dma(CODEC_MM_ION, addr))
+ codec_heap->alloced_size -= size;
+ mutex_unlock(&codec_heap->mutex);
}
static int ion_codec_mm_heap_allocate(struct ion_heap *heap,
codec_heap->heap.ops = &codec_mm_heap_ops;
codec_heap->heap.type = ION_HEAP_TYPE_CUSTOM;
codec_heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE;
+ mutex_init(&codec_heap->mutex);
return &codec_heap->heap;
}
int ret = 0;
size_t len = 0;
+#ifdef CONFIG_AMLOGIC_USB
+ if (!cdev)
+ return -EINVAL;
+#endif
DBG(cdev, "mtp_read(%zu)\n", count);
/* we will block until we're online */
pstore_ftrace_dump_old(cxt->fprz);
#endif
+#ifdef CONFIG_AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS
+ scrambler_ramoops_init();
+#endif
return 0;
fail_buf:
#define CLKID_MIPI_ENABLE_GATE 30
#define CLKID_MIPI_BANDGAP_GATE 31
#define CLKID_FCLK_DIV2P5 32
+#define CLKID_PCIE_HCSL 33
/*HHI_GCLK_MPEG0: 0x50*/
-#define GATE_BASE0 33
+#define GATE_BASE0 34
#define CLKID_DDR (GATE_BASE0 + 0)
#define CLKID_DOS (GATE_BASE0 + 1)
#define CLKID_AUDIO_LOCKER (GATE_BASE0 + 2)
#define CLKID_MPLL1 (CLKID_PLL_BASE + 13)
#define CLKID_MPLL2 (CLKID_PLL_BASE + 14)
#define CLKID_MPLL3 (CLKID_PLL_BASE + 15)
+#define CLKID_PCIE_HCSL (CLKID_PLL_BASE + 16)
-#define CLKID_XATL_BASE (CLKID_PLL_BASE + 16)
+#define CLKID_XATL_BASE (CLKID_PLL_BASE + 17)
#define CLKID_XTAL_DDR_PLL (CLKID_XATL_BASE + 0)
#define CLKID_XTAL_PLL_TOP (CLKID_XATL_BASE + 1)
#define CLKID_XTAL_USB_PLL0 (CLKID_XATL_BASE + 2)
--- /dev/null
+/*
+ * include/linux/amlogic/aml_crypto.h
+ *
+ * Copyright (C) 2021 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef _AML_CRYPTO_H_
+#define _AML_CRYPTO_H_
+
+#include <linux/types.h>
+
+#ifndef __KERNEL__
+#define __user
+#endif
+
+#define CRYPTO_OP_ENCRYPT 0
+#define CRYPTO_OP_DECRYPT 1
+
+#define MAX_CRYPTO_BUFFERS (32)
+
+struct session_op {
+ __u32 cipher; /* aml_crypto_op_t */
+ __u16 keylen;
+ __u16 kte; /* key table entry */
+ __u32 ses; /* session identifier */
+};
+
+struct crypt_mem {
+ __u32 length;
+ __u8 __user *addr;
+};
+
+struct crypt_op {
+ __u32 ses; /* session identifier */
+ __u8 op; /* OP_ENCRYPT or OP_DECRYPT */
+ __u8 src_phys; /* set if src is in physical addr */
+ __u8 dst_phys; /* set if dst is in physical addr */
+ __u8 ivlen; /* length of IV */
+ __u8 __user *iv; /* Notice: iv returned from physical is invalid */
+ __u8 num_src_bufs;
+ __u8 num_dst_bufs;
+ __u16 reserved; /* reserved */
+ struct crypt_mem src[MAX_CRYPTO_BUFFERS]; /* source data */
+ struct crypt_mem dst[MAX_CRYPTO_BUFFERS]; /* output data */
+};
+
+enum aml_crypto_op_t {
+ CRYPTO_OP_INVALID = 0,
+ CRYPTO_OP_DES_ECB = 1,
+ CRYPTO_OP_DES_CBC = 2,
+ CRYPTO_OP_TDES_ECB = 3,
+ CRYPTO_OP_TDES_CBC = 4,
+ CRYPTO_OP_AES_ECB = 5,
+ CRYPTO_OP_AES_CBC = 6,
+ CRYPTO_OP_AES_CTR = 7,
+
+ CRYPTO_OP_MAX
+};
+
+#define CREATE_SESSION _IOWR('a', 0, struct session_op)
+#define CLOSE_SESSION _IOW('a', 1, __u32)
+#define DO_CRYPTO _IOWR('a', 2, struct crypt_op)
+
+#endif
struct tuner_ops {
bool attached;
bool valid; /* There is hardware exist. */
+ bool pre_inited;
int refcount;
int index;
int type; /* The tuner's current FE type. */
const struct tuner_module *module;
- struct dvb_frontend fe;
+ struct dvb_frontend fe; /* Used to attach tuner. */
+ struct dvb_frontend *user; /* The current tuner user. */
struct tuner_config cfg;
struct list_head list;
};
int (*attach)(struct dvb_tuner *tuner, bool attach);
struct tuner_ops *(*match)(struct dvb_tuner *tuner, int std);
int (*detect)(struct dvb_tuner *tuner);
+ int (*pre_init)(struct dvb_tuner *tuner);
};
struct demod_ops {
bool attached;
bool registered;
bool valid; /* There is hardware. */
+ bool pre_inited;
+ bool external; /* external demod. */
int refcount;
int index;
struct demod_ops *(*match)(struct dvb_demod *demod, int std);
int (*detect)(struct dvb_demod *demod);
int (*register_frontend)(struct dvb_demod *demod, bool regist);
+ int (*pre_init)(struct dvb_demod *demod);
};
#if (defined CONFIG_AMLOGIC_DVB_EXTERN)
DSC_LOC_ENC,
CRYPTO_T0 = 0x100,
+ CRYPTO_T1 = 0x101,
+ CRYPTO_T2 = 0x102,
+ CRYPTO_T3 = 0x103,
+ CRYPTO_T4 = 0x104,
+ CRYPTO_T5 = 0x105,
};
enum key_algo {
#define MESON_CPU_MAJOR_ID_TL1 0x2E
#define MESON_CPU_MAJOR_ID_TM2 0x2F
#define MESON_CPU_MAJOR_ID_SC2 0x32
+#define MESON_CPU_MAJOR_ID_T7 0x36
+#define MESON_CPU_MAJOR_ID_S4 0x37
+
#define MESON_CPU_VERSION_LVL_MAJOR 0
#define MESON_CPU_VERSION_LVL_MINOR 1
#define VIDEO_COMPOSER_MAJOR (19 + (AML_BASE))
#define TSYNC_MAJOR (20 + (AML_BASE))
#define MEDIASYNC_MAJOR (21 + (AML_BASE))
+#define AMSYNC_MAJOR (24 + (AML_BASE))
+#define AMSYNC_SESSION_MAJOR (25 + (AML_BASE))
/*
*#define UIO_MAJOR 4+(AML_BASE)
*#define USB_DEV_EP_MAJOR 5+(AML_BASE)
#define MD_BUF_SIZE 1024
#define COMP_BUF_SIZE 8196
+#define DV_SEI 0x01000000
+#define DV_AV1_SEI 0x14000000
+#define HDR10P 0x02000000
+
void enable_dolby_vision(int enable);
bool is_dolby_vision_enable(void);
bool is_dolby_vision_on(void);
void di_api_post_disable(void);
+/**************************************************
+ * function:
+ * get report information from di;
+ * version:
+ *
+ * spt_bits: bit 0 for decontour,
+ * is 1 when there are decontour information;
+ * is 0 when there are no decontour information;
+ * dct_map_0: DCTR_MAP_HIST_0
+ * dct_sta_0: DCTR_STA_HIST_0
+ * dct_sta_1: DCTR_STA_HIST_1
+ **************************************************/
+struct dim_rpt_s {
+ unsigned int version;
+ unsigned int spt_bits;/*bit 0: dct*/
+ unsigned int dct_map_0;
+ unsigned int dct_map_1;
+ unsigned int dct_map_2;
+ unsigned int dct_map_3;
+ unsigned int dct_map_15;
+ unsigned int dct_bld_2;
+};
+
+enum DIM_DB_SV {
+ DIM_DB_SV_DCT_BL2, /* DCTR_BLENDING2 */
+};
+
+#define DIM_DB_SAVE_NUB 1
+
+/**************************************************
+ * function:
+ * get report information from di;
+ * vfm:
+ * input vframe;
+ * return:
+ * NULL: there is no report information from vfm;
+ * other: refer to struct dim_rpt_s
+ **************************************************/
+struct dim_rpt_s *dim_api_getrpt(struct vframe_s *vfm);
+
+/**************************************************
+ * function:
+ * select db value or pq value;
+ * idx:
+ * ref to DIM_DB_SV's define
+ * mode:
+ * 0: db value;
+ * 1: value from pdate;
+ * pdate: only useful when mode is 1.
+ * value / mask
+ **************************************************/
+bool dim_pq_db_sel(unsigned int idx, unsigned int mode, unsigned int *pdate);
+void dim_pq_db_setreg(unsigned int nub, unsigned int *preg);
+
#endif /* VIDEO_H */
struct vframe_s *vf;
void *caller_data; /*from di_init_parm.caller_data*/
u32 flag;
+ unsigned int crcout;
};
enum DI_FLAG {
DI_OUTPUT_422 = 0,
DI_OUTPUT_NV12 = 1,
DI_OUTPUT_NV21 = 2,
+ DI_OUTPUT_TVP = 0x20000000, /*21-03-02*/
+ DI_OUTPUT_LINEAR = 0x40000000,
+ /*1:di output must linear, 0: determined by di,may be linear or block*/
+ DI_OUTPUT_AFBC_BEST = 0x80000000,
+ /*if di support afbc, use afbc is the best choice*/
DI_OUTPUT_MAX = 0x7FFFFFFF,
};
*
* @return 0 for success, or fail type if < 0
*/
-//int di_release_keep_buf(struct di_buffer *buffer);
+int di_release_keep_buf(struct di_buffer *buffer);
+
+/**
+ * @brief di_get_buffer_num get output buffer num
+ *
+ * @param[in] index instance index
+ * @param[in] buffer Pointer of buffer structure
+ *
+ * @return number or fail type
+ */
+int di_get_buffer_num(int index);
#endif /*__DI_INTERLACE_H__*/
#define AMSTREAM_SET_AUDIO_DELAY_LIMIT_MS 0x11B
#define AMSTREAM_SET_DRMMODE 0x11C
#define AMSTREAM_SET_WORKMODE 0x11D
+#define AMSTREAM_SET_VIDEO_ID 0x11E
/* video set cmd */
#define AMSTREAM_SET_OMX_VPTS 0x160
#define AMSTREAM_SET_NO_POWERDOWN 0x178
#define AMSTREAM_SET_DV_META_WITH_EL 0x179
#define AMSTREAM_SET_FCC_MODE 0x180
+#define AMSTREAM_SET_DMC_URGENT 0x17a
/* video set ex cmd */
#define AMSTREAM_SET_EX_VIDEO_AXIS 0x260
#define AMSTREAM_GET_EX_VDECSTAT 0x902
#define AMSTREAM_GET_EX_ADECSTAT 0x903
#define AMSTREAM_GET_EX_UD_POC 0x904
+#define AMSTREAM_GET_EX_WR_COUNT 0x905
/* video get ex cmd */
#define AMSTREAM_GET_EX_VF_STATUS 0x960
struct adec_status astatus;
struct userdata_poc_info_t data_userdata_info;
- char data[24];
+ u32 wr_count;
+ char data[20];
};
u32 cmd;
#define VFRAME_FLAG_EMPTY_FRAME_V4L 0x800
#define VFRAME_FLAG_FAKE_FRAME 0x1000
#define VFRAME_FLAG_DOUBLE_FRAM 0x2000
-#define VFRAME_FLAG_VIDEO_DRM 0x4000
-#define VFRAME_FLAG_VIDEO_SECURE 0x20000
+#define VFRAME_FLAG_VIDEO_DRM 0x4000
+#define VFRAME_FLAG_VIDEO_VDETECT 0x8000
+#define VFRAME_FLAG_VIDEO_VDETECT_PUT 0x10000
+#define VFRAME_FLAG_VIDEO_SECURE 0x20000
+#define VFRAME_FLAG_DI_P_ONLY 0x40000 /* ary */
+#define VFRAME_FLAG_CONTAIN_POST_FRAME 0x80000
+#define VFRAME_FLAG_DI_PW_VFM 0x100000
+#define VFRAME_FLAG_DI_PW_N_LOCAL 0x200000
+#define VFRAME_FLAG_DI_PW_N_EXT 0x400000
enum pixel_aspect_ratio_e {
PIXEL_ASPECT_RATIO_1_1,
VIDEO_WIDEOPTION_16_9_COMBINED = 13,
VIDEO_WIDEOPTION_CUSTOM = 14,
VIDEO_WIDEOPTION_AFD = 15,
- VIDEO_WIDEOPTION_MAX = 16
+ VIDEO_WIDEOPTION_NONLINEAR_T = 16,
+ VIDEO_WIDEOPTION_MAX = 17
};
/* TODO: move to register headers */
extern bool super_scaler;
extern struct sr_info_s sr_info;
-#define VPP_FLAG_WIDEMODE_MASK 0x0000000F
+#define VPP_FLAG_WIDEMODE_MASK 0x1F000000
+#define VPP_WIDEMODE_BITS 24
#define VPP_FLAG_INTERLACE_OUT 0x00000010
#define VPP_FLAG_INTERLACE_IN 0x00000020
#define VPP_FLAG_CBCR_SEPARATE 0x00000040
u32 proc_3d_type;
bool vpp_3d_scale;
u32 nonlinear_factor;
+ u32 nonlinear_t_factor;
u32 wide_mode;
u32 zoom_ratio;
extern s32 vpp_set_nonlinear_factor(
struct disp_info_s *info, u32 f);
-
extern u32 vpp_get_nonlinear_factor(
struct disp_info_s *info);
+s32 vpp_set_nonlinear_t_factor(struct disp_info_s *info, u32 f);
+u32 vpp_get_nonlinear_t_factor(struct disp_info_s *info);
extern void vpp_disp_info_init(
struct disp_info_s *info, u8 id);
unsigned short h_sync;
unsigned short v_sync_offset;
unsigned short v_sync;
- unsigned char h_image_size;
- unsigned char v_image_size;
+ unsigned short h_image_size;
+ unsigned short v_image_size;
unsigned char h_border;
unsigned char v_border;
unsigned char flags;
unsigned short vactive;
unsigned short hblank;
unsigned short vblank;
- unsigned short hsync;
+ unsigned short vsync;
unsigned short tmds_clk; /* Value = Pixel clock ?? 10,000 */
enum hdmi_vic vesa_timing;
};
--- /dev/null
+/*
+ * include/linux/amlogic/media/vout/hdmi_tx/hdmi_hdcp.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __HDMI_HDCP_H__
+#define __HDMI_HDCP_H__
+#include <linux/wait.h>
+
+enum hdcp_ver_e {
+ HDCPVER_NONE = 0,
+ HDCPVER_14,
+ HDCPVER_22,
+};
+
+#define MAX_KSV_LISTS 127
+struct hdcprp14_topo {
+ unsigned char max_cascade_exceeded:1;
+ unsigned char depth:3;
+ unsigned char rsvd : 4;
+ unsigned char max_devs_exceeded:1;
+ unsigned char device_count:7; /* 1 ~ 127 */
+ unsigned char ksv_list[MAX_KSV_LISTS * 5];
+} __packed;
+
+struct hdcprp22_topo {
+ unsigned int depth;
+ unsigned int device_count;
+ unsigned int v1_X_device_down;
+ unsigned int v2_0_repeater_down;
+ unsigned int max_devs_exceeded;
+ unsigned int max_cascade_exceeded;
+ unsigned char id_num;
+ unsigned char id_lists[MAX_KSV_LISTS * 5];
+};
+
+struct hdcprp_topo {
+ /* hdcp_ver currently used */
+ enum hdcp_ver_e hdcp_ver;
+ union {
+ struct hdcprp14_topo topo14;
+ struct hdcprp22_topo topo22;
+ } topo;
+};
+
+struct hdcp_obs_val {
+ unsigned char obs0;
+ unsigned char obs1;
+ unsigned char obs2;
+ unsigned char obs3;
+ unsigned char intstat;
+};
+
+#define HDCP_LOG_SIZE 4096 /* 4KB */
+struct hdcplog_buf {
+ unsigned int wr_pos;
+ unsigned int rd_pos;
+ wait_queue_head_t wait;
+ unsigned char buf[HDCP_LOG_SIZE];
+};
+
+#endif
#define _HDMI_TX_MODULE_H
#include "hdmi_info_global.h"
#include "hdmi_config.h"
+#include "hdmi_hdcp.h"
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/cdev.h>
#include <linux/device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/amlogic/media/vout/vout_notify.h>
+#include <linux/spinlock.h>
#define DEVICE_NAME "amhdmitx"
struct clk *venci_1_gate;
};
-/* 2kB should be enough to record */
-#define HDCP_LOG_SIZE (1024 * 2)
-struct hdcplog_buf {
- int idx;
- unsigned char buf[HDCP_LOG_SIZE + 64]; /* padding 8 bytes */
-};
-
-enum hdcp_ver_e {
- HDCPVER_NONE = 0,
- HDCPVER_14,
- HDCPVER_22,
-};
-
-#define MAX_KSV_LISTS 127
-struct hdcprp14_topo {
- unsigned char max_cascade_exceeded:1;
- unsigned char depth:3;
- unsigned char max_devs_exceeded:1;
- unsigned char device_count:7; /* 1 ~ 127 */
- unsigned char ksv_list[MAX_KSV_LISTS * 5];
-};
-
-struct hdcprp22_topo {
- unsigned int depth;
- unsigned int device_count;
- unsigned int v1_X_device_down;
- unsigned int v2_0_repeater_down;
- unsigned int max_devs_exceeded;
- unsigned int max_cascade_exceeded;
- unsigned char id_num;
- unsigned char id_lists[MAX_KSV_LISTS * 5];
-};
-
-struct hdcprp_topo {
- /* hdcp_ver currently used */
- enum hdcp_ver_e hdcp_ver;
- union {
- struct hdcprp14_topo topo14;
- struct hdcprp22_topo topo22;
- } topo;
-};
-
#define EDID_MAX_BLOCK 4
-#define HDMI_TMP_BUF_SIZE 1024
struct hdmitx_dev {
struct cdev cdev; /* The cdev structure */
dev_t hdmitx_id;
struct hdmi_config_platform_data config_data;
enum hdmi_event_t hdmitx_event;
unsigned int irq_hpd;
+ unsigned int irq_viu1_vsync;
/*EDID*/
unsigned int cur_edid_block;
unsigned int cur_phy_block_ptr;
unsigned char mux_hpd_if_pin_high_flag;
int auth_process_timer;
struct hdmitx_info hdmi_info;
- unsigned char tmp_buf[HDMI_TMP_BUF_SIZE];
unsigned int log;
unsigned int tx_aud_cfg; /* 0, off; 1, on */
/* For some un-well-known TVs, no edid at all */
unsigned int drm_feature;/*Direct Rander Management*/
unsigned int vend_id_hit:1;
bool systemcontrol_on;
+ unsigned char vid_mute_op;
+ spinlock_t edid_spinlock; /* edid hdr/dv cap lock */
};
#define CMD_DDC_OFFSET (0x10 << 24)
#define SET_CT_GRAPHICS 2
#define SET_CT_PHOTO 3
#define SET_CT_CINEMA 4
+#define CONF_GET_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x05)
#define CONF_VIDEO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x04)
+#define VIDEO_NONE_OP 0x0
#define VIDEO_MUTE 0x1
#define VIDEO_UNMUTE 0x2
#define CONF_EMP_NUMBER (CMD_CONF_OFFSET + 0x3000 + 0x00)
+++ /dev/null
-/*
- * include/uapi/drm/meson_drm.h
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _MESON_DRM_H
-#define _MESON_DRM_H
-
-#include <drm/drm.h>
-
-/* memory type definitions. */
-enum drm_meson_gem_mem_type {
- /* Physically Continuous memory. */
- MESON_BO_CONTIG = 1 << 0,
- /* cachable mapping. */
- MESON_BO_CACHABLE = 1 << 1,
- /* write-combine mapping. */
- MESON_BO_WC = 1 << 2,
- MESON_BO_SECURE = 1 << 3,
- MESON_BO_MASK = MESON_BO_CONTIG | MESON_BO_CACHABLE |
- MESON_BO_WC
-};
-
-/* Use flags */
-#define BO_USE_NONE 0
-#define BO_USE_SCANOUT (1ull << 0)
-#define BO_USE_CURSOR (1ull << 1)
-#define BO_USE_CURSOR_64X64 BO_USE_CURSOR
-#define BO_USE_RENDERING (1ull << 2)
-#define BO_USE_LINEAR (1ull << 3)
-#define BO_USE_SW_READ_NEVER (1ull << 4)
-#define BO_USE_SW_READ_RARELY (1ull << 5)
-#define BO_USE_SW_READ_OFTEN (1ull << 6)
-#define BO_USE_SW_WRITE_NEVER (1ull << 7)
-#define BO_USE_SW_WRITE_RARELY (1ull << 8)
-#define BO_USE_SW_WRITE_OFTEN (1ull << 9)
-#define BO_USE_EXTERNAL_DISP (1ull << 10)
-#define BO_USE_PROTECTED (1ull << 11)
-#define BO_USE_HW_VIDEO_ENCODER (1ull << 12)
-#define BO_USE_CAMERA_WRITE (1ull << 13)
-#define BO_USE_CAMERA_READ (1ull << 14)
-#define BO_USE_RENDERSCRIPT (1ull << 16)
-#define BO_USE_TEXTURE (1ull << 17)
-
-
-/**
- * User-desired buffer creation information structure.
- *
- * @size: user-desired memory allocation size.
- * @flags: user request for setting memory type or cache attributes.
- * @handle: returned a handle to created gem object.
- * - this handle will be set by gem module of kernel side.
- */
-struct drm_meson_gem_create {
- uint64_t size;
- uint32_t flags;
- uint32_t handle;
-};
-
-#define DRM_MESON_GEM_CREATE 0x00
-
-#define DRM_IOCTL_MESON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
- DRM_MESON_GEM_CREATE, struct drm_meson_gem_create)
-
-#endif /* _MESON_DRM_H */
-
struct scpi_dvfs_info *scpi_dvfs_get_opps(u8 domain);
int scpi_get_sensor(char *name);
int scpi_get_sensor_value(u16 sensor, u32 *val);
-int scpi_send_usr_data(u32 client_id, u32 *val, u32 size);
+int scpi_send_usr_data(u32 client_id, void *val, u32 size);
int scpi_get_vrtc(u32 *p_vrtc);
int scpi_set_vrtc(u32 vrtc_val);
int scpi_get_ring_value(unsigned char *val);
int scpi_get_wakeup_reason(u32 *wakeup_reason);
int scpi_clr_wakeup_reason(void);
int scpi_get_cec_val(enum scpi_std_cmd index, u32 *p_cec);
-int scpi_send_cec_data(u32 cmd_id, u32 *val, u32 size);
+int scpi_send_cec_data(u32 cmd_id, void *val, u32 size);
u8 scpi_get_ethernet_calc(void);
int scpi_get_cpuinfo(enum scpi_get_pfm_type type, u32 *freq, u32 *vol);
int scpi_init_dsp_cfg0(u32 id, u32 addr, u32 cfg0);
long long checksum;
};
+/* flag is "@ML" */
+#define TUNED_FLAG 0x004C4D40
+/* version is "V1" */
+#define TUNED_VERSION 0x00003156
+/* magic is 0x00487e44 */
+#define TUNED_MAGIC 0x00487e44
+
struct amlsd_platform {
struct amlsd_host *host;
struct mmc_host *mmc;
#define DMC_DEV_ID_GE2D 15
#define DMC_DEV_ID_DI_PRE 16
#define DMC_DEV_ID_DI_POST 17
+#define DMC_DEV_ID_GDC 18
/*
* Desc: tee enabled state
--- /dev/null
+/*
+ * include/linux/amlogic/tee_demux.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __TEE_DEMUX_H__
+#define __TEE_DEMUX_H__
+
+#define TEE_DMX_ENABLE 1
+
+enum tee_dmx_cmd {
+ TEE_DMX_SET_SID_TABLE,
+ TEE_DMX_SET_TS_TABLE,
+ TEE_DMX_SET_ES_TABLE,
+ TEE_DMX_SET_PCR_TABLE,
+ TEE_DMX_SET_PID_TABLE,
+ TEE_DMX_SET_DMA_DESC,
+ TEE_DMX_GET_SECURITY_ENABLE = 0x1000,
+ TEE_DMX_GET_PCR,
+ TEE_DMX_GET_TSX_STATUS,
+};
+
+struct tee_dmx_ts_table_param {
+ int pid;
+ u32 pid_mask;
+ u32 pid_entry;
+ u32 buffer_id;
+};
+
+struct tee_dmx_sid_table_param {
+ u32 sid;
+ u32 begin;
+ u32 length;
+};
+
+union tee_dsc_pid_table {
+ u64 data;
+ struct {
+ u64 valid:1;
+ u64 resv0:7;
+ u64 resv1:1;
+ u64 scb00:1;
+ u64 scb_out:2;
+ u64 scb_as_is:1;
+ u64 odd_iv:6;
+ u64 even_00_iv:6;
+ u64 sid:6;
+ u64 pid:13;
+ u64 algo:4;
+ u64 kte_odd:8;
+ u64 kte_even_00:8;
+ } bits;
+};
+
+struct tee_dmx_pid_table_param {
+ u32 type;
+ u32 id;
+ union tee_dsc_pid_table table;
+};
+
+struct tee_dmx_es_table_param {
+ u32 es_entry;
+ int pid;
+ u32 sid;
+ u32 reset;
+ u32 dup_ok;
+ u8 fmt;
+};
+
+struct tee_dmx_pcr_table_param {
+ u32 pcr_entry;
+ u32 pcr_pid;
+ u32 sid;
+};
+
+struct tee_dmx_dma_desc_param {
+ u32 len;
+ u32 address;
+ u32 buffer_id;
+};
+
+int tee_demux_set(enum tee_dmx_cmd cmd, void *data, u32 len);
+
+int tee_demux_get(enum tee_dmx_cmd cmd,
+ void *in, u32 in_len, void *out, u32 out_len);
+
+#endif /* __TEE_DEMUX_H__ */
+
extern void key_invalidate(struct key *key);
extern void key_put(struct key *key);
+#ifdef CONFIG_AMLOGIC_MODIFY
+#include <asm/memory.h>
+#endif
+
static inline struct key *__key_get(struct key *key)
{
+#ifdef CONFIG_AMLOGIC_MODIFY
+ if (key < (struct key *)PAGE_OFFSET) {
+ WARN(1, "INVALID__x2__KEY:%p\n", key);
+ return NULL;
+ }
+#endif
atomic_inc(&key->usage);
return key;
}
extern void pstore_unregister(struct pstore_info *);
extern bool pstore_cannot_block_path(enum kmsg_dump_reason reason);
+#ifdef CONFIG_AMLOGIC_DEBUG_SCRAMBLER_RAMOOPS
+int scrambler_ramoops_init(void);
+#endif
+
#endif /*_LINUX_PSTORE_H*/
#endif
#define VERMAGIC_STRING \
- UTS_RELEASEY " " \
+ UTS_RELEASE " " \
MODULE_VERMAGIC_SMP MODULE_VERMAGIC_PREEMPT \
MODULE_VERMAGIC_MODULE_UNLOAD MODULE_VERMAGIC_MODVERSIONS \
MODULE_ARCH_VERMAGIC
header-y += netfilter_ipv6/
header-y += usb/
header-y += wimax/
+header-y += amlogic/
genhdr-y += version.h
--- /dev/null
+# amlogic Header export list
+header-y += msync.h
--- /dev/null
+/*
+ * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#ifndef AML_MSYNC_H
+#define AML_MSYNC_H
+
+#ifndef __KERNEL__
+#include <stdint.h>
+#endif
+
+struct pts_tri {
+ uint32_t wall_clock;
+ uint32_t pts;
+ uint32_t delay;
+};
+
+struct pcr_pair {
+ uint32_t pts;
+ uint64_t mono_clock;
+};
+
+struct pts_wall {
+ uint32_t wall_clock;
+ uint32_t interval;
+};
+
+enum av_sync_mode {
+ AVS_MODE_A_MASTER,
+ AVS_MODE_V_MASTER,
+ AVS_MODE_PCR_MASTER,
+ AVS_MODE_IPTV,
+ AVS_MODE_FREE_RUN
+};
+
+struct session_sync_stat {
+ uint32_t v_active;
+ uint32_t a_active;
+ /* enum av_sync_mode */
+ uint32_t mode;
+ /* valid in aligned sync */
+ uint32_t v_timeout;
+ /* in audio switching process */
+ uint32_t audio_switch;
+};
+
+enum avs_event {
+ AVS_VIDEO_START,
+ AVS_PAUSE,
+ AVS_RESUME,
+ AVS_VIDEO_STOP,
+ AVS_AUDIO_STOP,
+ AVS_VIDEO_TSTAMP_DISCONTINUITY,
+ AVS_AUDIO_TSTAMP_DISCONTINUITY,
+ AVS_AUDIO_SWITCH,
+ AVS_EVENT_MAX,
+};
+
+enum avs_astart_mode {
+ AVS_START_SYNC = 0,
+ AVS_START_ASYNC,
+ AVS_START_AGAIN,
+ AVS_START_MAX
+};
+
+struct audio_start {
+ /* in first audio pts */
+ uint32_t pts;
+ /* in render delay */
+ uint32_t delay;
+ /* out enum avs_astart_mode */
+ uint32_t mode;
+};
+
+struct session_event {
+ /* enum avs_event */
+ uint32_t event;
+ uint32_t value;
+};
+
+struct session_debug {
+ uint32_t debug_freerun;
+ uint32_t pcr_init_flag;
+ uint32_t pcr_init_mode;
+};
+
+#define AVS_INVALID_PTS 0xFFFFFFFFUL
+
+#define AMSYNC_START_V_FIRST 0x1
+#define AMSYNC_START_A_FIRST 0x2
+#define AMSYNC_START_ASAP 0x3
+#define AMSYNC_START_ALIGN 0x4
+
+/* msync ioctl */
+#define _A_M_S 'M'
+#define AMSYNC_IOC_ALLOC_SESSION _IOW((_A_M_S), 0x00, int)
+#define AMSYNC_IOC_REMOVE_SESSION _IOR((_A_M_S), 0x01, int)
+
+/* session ioctl */
+#define _A_M_SS 'S'
+#define AMSYNCS_IOC_SET_MODE _IOW((_A_M_SS), 0x00, unsigned int)
+#define AMSYNCS_IOC_GET_MODE _IOR((_A_M_SS), 0x01, unsigned int)
+#define AMSYNCS_IOC_SET_START_POLICY _IOW((_A_M_SS), 0x02, unsigned int)
+#define AMSYNCS_IOC_GET_START_POLICY _IOR((_A_M_SS), 0x03, unsigned int)
+#define AMSYNCS_IOC_SET_V_TS _IOW((_A_M_SS), 0x04, struct pts_tri)
+#define AMSYNCS_IOC_GET_V_TS _IOWR((_A_M_SS), 0x05, struct pts_tri)
+#define AMSYNCS_IOC_SET_A_TS _IOW((_A_M_SS), 0x06, struct pts_tri)
+#define AMSYNCS_IOC_GET_A_TS _IOWR((_A_M_SS), 0x07, struct pts_tri)
+#define AMSYNCS_IOC_SEND_EVENT _IOWR((_A_M_SS), 0x08, struct session_event)
+//For PCR/IPTV mode only
+#define AMSYNCS_IOC_GET_SYNC_STAT _IOWR((_A_M_SS), 0x09, struct session_sync_stat)
+#define AMSYNCS_IOC_SET_PCR _IOW((_A_M_SS), 0x0a, struct pcr_pair)
+#define AMSYNCS_IOC_GET_PCR _IOWR((_A_M_SS), 0x0b, struct pcr_pair)
+#define AMSYNCS_IOC_GET_WALL _IOR((_A_M_SS), 0x0c, struct pts_wall)
+#define AMSYNCS_IOC_SET_RATE _IOW((_A_M_SS), 0x0d, unsigned int)
+#define AMSYNCS_IOC_GET_RATE _IOR((_A_M_SS), 0x0e, unsigned int)
+#define AMSYNCS_IOC_SET_NAME _IOR((_A_M_SS), 0x0f, char *)
+#define AMSYNCS_IOC_SET_WALL_ADJ_THRES _IOW((_A_M_SS), 0x10, unsigned int)
+#define AMSYNCS_IOC_GET_WALL_ADJ_THRES _IOR((_A_M_SS), 0x11, unsigned int)
+#define AMSYNCS_IOC_GET_CLOCK_START _IOR((_A_M_SS), 0x12, unsigned int)
+#define AMSYNCS_IOC_AUDIO_START _IOW((_A_M_SS), 0x13, struct audio_start)
+#define AMSYNCS_IOC_SET_CLK_DEV _IOW((_A_M_SS), 0x14, int)
+#define AMSYNCS_IOC_GET_CLK_DEV _IOR((_A_M_SS), 0x15, int)
+
+//For debuging
+#define AMSYNCS_IOC_GET_DEBUG_MODE _IOR((_A_M_SS), 0x100, struct session_debug)
+
+int msync_vsync_update(void);
+
+#endif
if (!*fmt)
return 0;
-
+#ifdef CONFIG_AMLOGIC_MODIFY
+ seq_printf(m, "0x%pK : \"", *fmt);
+#else
seq_printf(m, "0x%lx : \"", *(unsigned long *)fmt);
+#endif
/*
* Tabs and new lines need to be converted.
return;
mapping = page_mapping(page);
+ if (mapping == TAIL_MAPPING) {
+ cc->forbid_to_cma = true;
+ return;
+ }
+
if ((unsigned long)mapping & PAGE_MAPPING_ANON)
mapping = NULL;
if ((unsigned long)mapping & PAGE_MAPPING_ANON)
mapping = NULL;
+ if (mapping == TAIL_MAPPING)
+ return 0;
+
if (PageKsm(page) && !PageSlab(page))
return 0;
--- /dev/null
+#! /bin/bash
+#
+# author: yao.zhang1@amlogic.com
+# 2021.05.20
+
+MAIN_FOLDER=`pwd`
+CONFIG_COVERITY_ALL="0"
+CC64="/opt/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-"
+CC32="/opt/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-"
+CONFIG_GKI_MODULE="arch/arm64/configs/meson64_gki_module_config"
+CONFIG_A64_R="arch/arm64/configs/meson64_a64_R_defconfig"
+
+function usage() {
+ cat << EOF
+ Usage:
+ ./$(basename $0) --help
+
+ code check kernel build script.
+ This script will coverity the latest code commit or all code coverity locally.
+
+ command list:
+ ./$(basename $0) [CONFIG_COVERITY_ALL]
+
+ Example:
+ 1) ./scripts/amlogic/code_check.sh --all //kernel 5.4 or kernel 4.9, then coverity all
+
+ 2) ./scripts/amlogic/code_check.sh //kernel 5.4 or kernel 4.9, then coverity own local last commit
+
+EOF
+ exit 1
+}
+
+function build_kernel() {
+ #echo "=====build kernel======"
+ if [ "$CONFIG_KERNEL_VERSION" = "4.9" ]; then
+ if [ "$CONFIG_ARCH" = "arm64" ]; then
+ echo "===========CONFIG_ARCH $CONFIG_ARCH ==========="
+ make ARCH=arm64 O=../kernel-output distclean
+ make ARCH=arm64 CROSS_COMPILE=$CC64 O=../kernel-output meson64_defconfig
+ make ARCH=arm64 mrproper
+ cov-build --dir ../im-dir/ make ARCH=arm64 CROSS_COMPILE=$CC64 O=../kernel-output Image -j32
+ elif [ "$CONFIG_ARCH" = "arm32" ]; then
+ echo "===========CONFIG_ARCH $CONFIG_ARCH ==========="
+ make ARCH=arm O=../kernel-output distclean
+ make ARCH=arm CROSS_COMPILE=$CC32 O=../kernel_output/ meson64_a32_defconfig
+ make ARCH=arm mrproper
+ cov-build --dir ../im-dir/ make ARCH=arm CROSS_COMPILE=$CC32 O=../kernel_output uImage -j32
+ else
+ echo "===========CONFIG_ARCH ? ==========="
+ usage
+ fi
+ elif [ "$CONFIG_KERNEL_VERSION" = "5.4" ]; then
+ #rm -rf ../im-dir/ ../html-result/ ../kernel-output*
+ git checkout scripts/kconfig/merge_config.sh
+ make ARCH=arm64 O=../kernel-output distclean
+ cat $CONFIG_GKI_MODULE $CONFIG_A64_R > arch/arm64/configs/meson64_gki.fragment.y
+ sed -i 's/=m/=y/' arch/arm64/configs/meson64_gki.fragment.y
+ sed -i 's/OUTPUT=\./OUTPUT=..\/kernel-output/' ./scripts/kconfig/merge_config.sh
+ ARCH=arm64 ./scripts/kconfig/merge_config.sh arch/arm64/configs/meson64_gki.fragment.y
+ rm arch/arm64/configs/meson64_gki.fragment.y
+ git checkout scripts/kconfig/merge_config.sh
+ #git checkout .
+ make ARCH=arm64 mrproper
+ cov-build --dir ../im-dir/ make ARCH=arm64 CROSS_COMPILE=$CC64 O=../kernel-output Image -j32
+ else
+ usage
+ fi
+}
+
+function build() {
+ WORKSPACE=`pwd`
+ #echo "===========WORKSPACE $WORKSPACE==========="
+
+ #git diff HEAD@{1} --name-only | grep -e '\.c$' -e '\.h$' > file.list
+ #git diff HEAD@{0} --name-only | grep -v -e '\.dtsi$' -e '\.dts$' > file.list
+ #git diff HEAD~1 HEAD~0 --name-only | grep -e '\.c$' -e '\.h$' > file.list
+ git diff HEAD^ --name-only | grep -e '\.c$' -e '\.h$' > file.list
+
+ tupattern="0"
+ firstline="0"
+ while read line
+ do
+ if [ "$firstline" = "0" ]; then
+ filelist="$line"
+ tupattern="file('/$line')"
+ firstline="1"
+ else
+ filelist="$line|$filelist"
+ tupattern="file('/$line')||$tupattern"
+ fi
+ done < file.list
+
+ echo "===========filelist $filelist==========="
+ result1=`echo $filelist |grep "arch/arm/"`
+ result2=`echo $filelist |grep "arch/arm64/"`
+ if [ "$result1" != "" ]&&[ "$result2" != "" ]; then
+ CONFIG_ARCH="arm64"
+ elif [ "$result1" != "" ]; then
+ CONFIG_ARCH="arm32"
+ else
+ CONFIG_ARCH="arm64"
+ fi
+
+ sleep 1
+
+ build_kernel
+
+ sleep 1
+
+ if [ "$CONFIG_COVERITY_ALL" = "1" ]; then
+ echo "===========CONFIG_COVERITY_ALL==========="
+ cov-analyze --dir ../im-dir/ --strip-path $WORKSPACE/ --all
+ sleep 1
+ cov-format-errors --dir ../im-dir/ --html-output ../html-result --filesort --strip-path $WORKSPACE/ -x
+ else
+ #echo "===========filelist ${filelist}"
+ #echo "===========tupattern ${tupattern}"
+ if [ "$filelist" = "" ]; then
+ echo "===========only coverity .c and .h !!!================="
+ fi
+ cov-analyze --dir ../im-dir/ --strip-path $WORKSPACE/ --tu-pattern "${tupattern}" --all
+ sleep 1
+ cov-format-errors --dir ../im-dir/ --include-files "${filelist}" --html-output ../html-result
+ fi
+}
+
+function parser() {
+ local i=0
+ local j=0
+ local argv=()
+ for arg in "$@" ; do
+ argv[$i]="$arg"
+ i=$((i + 1))
+ done
+ i=0
+ j=0
+ while [ $i -lt $# ]; do
+ arg="${argv[$i]}"
+ i=$((i + 1)) # must place here
+ case "$arg" in
+ -h|--help|help)
+ usage
+ exit ;;
+ #-a)
+ # CONFIG_ARCH="${argv[$i]}"
+ # echo "CONFIG_ARCH: ${CONFIG_ARCH}"
+ # continue ;;
+ #-v)
+ # CONFIG_KERNEL_VERSION="${argv[$i]}"
+ # echo "CONFIG_KERNEL_VERSION: ${CONFIG_KERNEL_VERSION}"
+ # continue ;;
+ --all)
+ CONFIG_COVERITY_ALL="1"
+ continue ;;
+ *)
+ esac
+ done
+
+ CONFIG_ARCH="arm64"
+ cat Makefile |grep "VERSION " > version_cat
+ cat Makefile |grep "PATCHLEVEL " > patchlevel_cat
+ VERSION=`sed -n '1p' version_cat | cut -d ' ' -f 3`
+ PATCHLEVEL=`sed -n '1p' patchlevel_cat | cut -d ' ' -f 3`
+ rm version_cat patchlevel_cat
+ CONFIG_KERNEL_VERSION=$VERSION.$PATCHLEVEL
+
+ echo "===========CONFIG_KERNEL_VERSION $CONFIG_KERNEL_VERSION==========="
+ #if [ "$j" == "0" ]; then
+ #usage
+ #exit
+ #fi
+}
+
+function main() {
+ if [ -z $0 ]
+ then
+ usage
+ return
+ fi
+ parser $@
+ build $@
+}
+
+main $@
* schedule the cleanup task to come and pull it out of the tree in process
* context at some later time.
*/
+
+#ifdef CONFIG_AMLOGIC_MODIFY
+#include <linux/memory.h>
+int is_key_invalid(struct key *key)
+{
+ if (key && key < (struct key *)PAGE_OFFSET)
+ return 1;
+ return 0;
+}
+EXPORT_SYMBOL(is_key_invalid);
+#endif
+
void key_put(struct key *key)
{
+#ifdef CONFIG_AMLOGIC_MODIFY
+ if (is_key_invalid(key)) {
+ WARN(1, "INVALID__x2__KEY:%p\n", key);
+ return;
+ }
+#endif
if (key) {
key_check(key);
int id;
id = (ucontrol->value.enumerated.item[0] >> 16) & 0xffff;
+ if (id > 2) {
+ pr_warn("%s(), invalid id = %d\n", __func__, id);
+ return 0;
+ }
+
inskew = (int)(ucontrol->value.enumerated.item[0] & 0xffff);
+ if (inskew > 7) {
+ pr_warn("%s(), invalid inskew = %d\n", __func__, inskew);
+ return 0;
+ }
+
audio_inskew = inskew;
off_set = EE_AUDIO_TDMIN_B_CTRL - EE_AUDIO_TDMIN_A_CTRL;
reg_in = EE_AUDIO_TDMIN_A_CTRL + off_set * id;
return 0;
}
+int pdm_get_chnum_flag(void)
+{
+ struct aml_pdm *p_pdm = get_pdm();
+
+ if (p_pdm && p_pdm->chipinfo)
+ return p_pdm->chipinfo->chnum_flag;
+
+ return 0;
+}
+
static int aml_pdm_filter_mode_get_enum(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
bool truncate_data;
/* train */
bool train;
+ bool chnum_flag;
int train_version;
};
int pdm_get_train_sample_count_from_dts(void);
int pdm_get_train_version(void);
+int pdm_get_chnum_flag(void);
+
#endif /*__AML_PDM_H__*/
spin_lock_irqsave(&pdm_lock, flags);
if (is_enable) {
/* en chnum sync default */
- if (pdm_enable_cnt == 0)
- aml_pdm_update_bits(
- PDM_CTRL,
- 0x1 << 31 | 1 << 17,
- is_enable << 31 | 1 << 17);
+ if (pdm_enable_cnt == 0) {
+ aml_pdm_update_bits(PDM_CTRL,
+ 0x1 << 31,
+ is_enable << 31);
+ if (pdm_get_chnum_flag())
+ aml_pdm_update_bits(PDM_CTRL,
+ 0x1 << 17,
+ 0x1 << 17);
+ }
pdm_enable_cnt++;
} else {
if (WARN_ON(pdm_enable_cnt == 0))
goto exit;
if (--pdm_enable_cnt == 0)
- aml_pdm_update_bits(
- PDM_CTRL,
+ aml_pdm_update_bits(PDM_CTRL,
0x1 << 31 | 0x1 << 16,
0 << 31 | 0 << 16);
}
/* PDM Asynchronous FIFO soft reset.
* write 1 to soft reset AFIFO
*/
- aml_pdm_update_bits(
- PDM_CTRL,
- 0x1 << 16,
- 0 << 16);
-
- aml_pdm_update_bits(
- PDM_CTRL,
- 0x1 << 16,
- 0x1 << 16);
+ aml_pdm_update_bits(PDM_CTRL,
+ 0x1 << 16,
+ 0 << 16);
+
+ aml_pdm_update_bits(PDM_CTRL,
+ 0x1 << 16,
+ 0x1 << 16);
}
void pdm_force_sysclk_to_oscin(bool force)
+++ /dev/null
-/*
- * sound/soc/amlogic/auge/pdm_hw_coeff.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/* LPF coefficent
- * For filter 1 and filter 3, it's only relative with coefficent mode
- * For filter 2, it's only relative with osr and hcic stage number
- */
-
-static const int lpf2_osr64[] = {
- 0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818,
- 0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41,
- 0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0,
- 0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000,
- 0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93,
- 0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12,
- 0x0002c1, 0xfff004, 0x00050a,
-};
-
-static const int lpf2_osr96[] = {
- 0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818,
- 0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41,
- 0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0,
- 0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000,
- 0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93,
- 0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12,
- 0x0002c1, 0xfff004, 0x00050a
-};
-
-static const int lpf2_osr128[] = {
- 0x00050b, 0xfff002, 0x0002c6, 0x003c15, 0xffa7fc,
- 0xffc899, 0x010b29, 0xff518f, 0xfebd98, 0x02909c,
- 0xff5ab8, 0xfc6254, 0x0563b2, 0x000000, 0xf46f16,
- 0x11c6a2, 0x2eb45a, 0x11c6a2, 0xf46f16, 0x000000,
- 0x0563b2, 0xfc6254, 0xff5ab8, 0x02909c, 0xfebd98,
- 0xff518f, 0x010b29, 0xffc899, 0xffa7fc, 0x003c15,
- 0x0002c6, 0xfff002, 0x00050b
-};
-
-static const int lpf2_osr192[] = {
- 0x00050b, 0xfff002, 0x0002c7, 0x003c16, 0xffa7f7,
- 0xffc89f, 0x010b35, 0xff516f, 0xfebd9a, 0x0290e8,
- 0xff5a6d, 0xfc61f8, 0x05649b, 0x000000, 0xf46d02,
- 0x11c6cc, 0x2eb731, 0x11c6cc, 0xf46d02, 0x000000,
- 0x05649b, 0xfc61f8, 0xff5a6d, 0x0290e8, 0xfebd9a,
- 0xff516f, 0x010b35, 0xffc89f, 0xffa7f7, 0x003c16,
- 0x0002c7, 0xfff002, 0x00050b
-};
-
-static const int lpf2_osr256[] = {
- 0x00050b, 0xfff002, 0x0002c7, 0x003c16, 0xffa7f6,
- 0xffc8a0, 0x010b37, 0xff516a, 0xfebd9a, 0x0290f4,
- 0xff5a62, 0xfc61ea, 0x0564bf, 0x000000, 0xf46cb0,
- 0x11c6d2, 0x2eb7a1, 0x11c6d2, 0xf46cb0, 0x000000,
- 0x0564bf, 0xfc61ea, 0xff5a62, 0x0290f4, 0xfebd9a,
- 0xff516a, 0x010b37, 0xffc8a0, 0xffa7f6, 0x003c16,
- 0x0002c7, 0xfff002, 0x00050b
-};
-
-static const int lpf2_osr384[] = {
- 0x00050b, 0xfff002, 0x0002c7, 0x003c16, 0xffa7f6,
- 0xffc8a0, 0x010b37, 0xff516a, 0xfebd9a, 0x0290f4,
- 0xff5a62, 0xfc61ea, 0x0564bf, 0x000000, 0xf46cb0,
- 0x11c6d2, 0x2eb7a1, 0x11c6d2, 0xf46cb0, 0x000000,
- 0x0564bf, 0xfc61ea, 0xff5a62, 0x0290f4, 0xfebd9a,
- 0xff516a, 0x010b37, 0xffc8a0, 0xffa7f6, 0x003c16,
- 0x0002c7, 0xfff002, 0x00050b
-};
-
-static const int lpf1_mode0[] = {
- 0x000006, 0x000002, 0xffffeb, 0xffffbe, 0xffff8a,
- 0xffff76, 0xffffb4, 0x00006b, 0x000187, 0x0002a7,
- 0x00031d, 0x00022c, 0xffff6b, 0xfffb35, 0xfff6e7,
- 0xfff4aa, 0xfff6b8, 0xfffe3f, 0x000a43, 0x00172a,
- 0x001f54, 0x001cfd, 0x000ce4, 0xfff0d0, 0xffd098,
- 0xffb8cd, 0xffb6b8, 0xffd2b1, 0x000adb, 0x0050ad,
- 0x008b46, 0x009ee9, 0x0077e0, 0x001506, 0xff8d7a,
- 0xff0dc4, 0xfecb6c, 0xfef1b8, 0xff8da0, 0x0080db,
- 0x0182b7, 0x0231a8, 0x023283, 0x0154bd, 0xffaf64,
- 0xfdab1a, 0xfbf20a, 0xfb46e9, 0xfc4cb4, 0xff4f72,
- 0x041fa5, 0x0a0e12, 0x100c37, 0x14eab3, 0x17a4fe,
- 0x17a4fe, 0x14eab3, 0x100c37, 0x0a0e12, 0x041fa5,
- 0xff4f72, 0xfc4cb4, 0xfb46e9, 0xfbf20a, 0xfdab1a,
- 0xffaf64, 0x0154bd, 0x023283, 0x0231a8, 0x0182b7,
- 0x0080db, 0xff8da0, 0xfef1b8, 0xfecb6c, 0xff0dc4,
- 0xff8d7a, 0x001506, 0x0077e0, 0x009ee9, 0x008b46,
- 0x0050ad, 0x000adb, 0xffd2b1, 0xffb6b8, 0xffb8cd,
- 0xffd098, 0xfff0d0, 0x000ce4, 0x001cfd, 0x001f54,
- 0x00172a, 0x000a43, 0xfffe3f, 0xfff6b8, 0xfff4aa,
- 0xfff6e7, 0xfffb35, 0xffff6b, 0x00022c, 0x00031d,
- 0x0002a7, 0x000187, 0x00006b, 0xffffb4, 0xffff76,
- 0xffff8a, 0xffffbe, 0xffffeb, 0x000002, 0x000006,
-};
-
-static const int lpf3_mode0[] = {
- 0x000007, 0x000000, 0xffffe8, 0x000000, 0x000038,
- 0x000000, 0xffff94, 0x000000, 0x0000c0, 0x000000,
- 0xfffec1, 0x000000, 0x0001f7, 0x000000, 0xfffd05,
- 0x000000, 0x000460, 0x000000, 0xfff9c1, 0x000000,
- 0x0008b7, 0x000000, 0xfff416, 0x000000, 0x000fff,
- 0x000000, 0xffeadc, 0x000000, 0x001b8a, 0x000000,
- 0xffdc97, 0x000000, 0x002d01, 0x000000, 0xffc767,
- 0x000000, 0x00467f, 0x000000, 0xffa8f1, 0x000000,
- 0x006ab0, 0x000000, 0xff7e26, 0x000000, 0x009d20,
- 0x000000, 0xff42ce, 0x000000, 0x00e2f1, 0x000000,
- 0xfef07e, 0x000000, 0x014470, 0x000000, 0xfe7c1b,
- 0x000000, 0x01d10f, 0x000000, 0xfdcf39, 0x000000,
- 0x02aaeb, 0x000000, 0xfcb2e7, 0x000000, 0x04311d,
- 0x000000, 0xfa719c, 0x000000, 0x07f53f, 0x000000,
- 0xf288b5, 0x000000, 0x28b482, 0x3fffff, 0x28b482,
- 0x000000, 0xf288b5, 0x000000, 0x07f53f, 0x000000,
- 0xfa719c, 0x000000, 0x04311d, 0x000000, 0xfcb2e7,
- 0x000000, 0x02aaeb, 0x000000, 0xfdcf39, 0x000000,
- 0x01d10f, 0x000000, 0xfe7c1b, 0x000000, 0x014470,
- 0x000000, 0xfef07e, 0x000000, 0x00e2f1, 0x000000,
- 0xff42ce, 0x000000, 0x009d20, 0x000000, 0xff7e26,
- 0x000000, 0x006ab0, 0x000000, 0xffa8f1, 0x000000,
- 0x00467f, 0x000000, 0xffc767, 0x000000, 0x002d01,
- 0x000000, 0xffdc97, 0x000000, 0x001b8a, 0x000000,
- 0xffeadc, 0x000000, 0x000fff, 0x000000, 0xfff416,
- 0x000000, 0x0008b7, 0x000000, 0xfff9c1, 0x000000,
- 0x000460, 0x000000, 0xfffd05, 0x000000, 0x0001f7,
- 0x000000, 0xfffec1, 0x000000, 0x0000c0, 0x000000,
- 0xffff94, 0x000000, 0x000038, 0x000000, 0xffffe8,
- 0x000000, 0x000007
-};
-
-static const int lpf1_mode1[] = {
- 0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45,
- 0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21,
- 0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212,
- 0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa,
- 0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef,
- 0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077,
- 0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690,
- 0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3,
- 0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686,
- 0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812,
- 0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60,
- 0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000,
- 0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e,
- 0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c,
- 0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece,
- 0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645,
- 0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9,
- 0xffffb2, 0x000014,
-};
-
-static const int lpf3_mode1[] = {
- 0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000,
- 0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7,
- 0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000,
- 0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0,
- 0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000,
- 0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7,
- 0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000,
- 0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45,
- 0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000,
- 0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c,
- 0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000,
- 0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216,
- 0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000,
- 0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d,
- 0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000,
- 0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368,
- 0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000,
- 0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb,
- 0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000,
- 0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c,
- 0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000,
- 0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46,
- 0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000,
- 0x000081, 0x000000,
-};
-
-static const int lpf1_mode2[] = {
- 0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45,
- 0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21,
- 0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212,
- 0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa,
- 0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef,
- 0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077,
- 0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690,
- 0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3,
- 0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686,
- 0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812,
- 0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60,
- 0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000,
- 0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e,
- 0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c,
- 0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece,
- 0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645,
- 0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9,
- 0xffffb2, 0x000014
-};
-
-static const int lpf3_mode2[] = {
- 0x00005e, 0xffff19, 0xfffe3e, 0x00030a, 0x0004de,
- 0xfff899, 0xfff531, 0x000f4a, 0x001510, 0xffe39e,
- 0xffda78, 0x0030d1, 0x003e97, 0xffb0c5, 0xff9cd2,
- 0x007aec, 0x009706, 0xff47dd, 0xff20f2, 0x010cbd,
- 0x01426b, 0xfe7e4e, 0xfe3340, 0x0226a1, 0x0293d1,
- 0xfce4d3, 0xfc382d, 0x04ad05, 0x05ef42, 0xf82315,
- 0xf4bde1, 0x130bdd, 0x399128, 0x399128, 0x130bdd,
- 0xf4bde1, 0xf82315, 0x05ef42, 0x04ad05, 0xfc382d,
- 0xfce4d3, 0x0293d1, 0x0226a1, 0xfe3340, 0xfe7e4e,
- 0x01426b, 0x010cbd, 0xff20f2, 0xff47dd, 0x009706,
- 0x007aec, 0xff9cd2, 0xffb0c5, 0x003e97, 0x0030d1,
- 0xffda78, 0xffe39e, 0x001510, 0x000f4a, 0xfff531,
- 0xfff899, 0x0004de, 0x00030a, 0xfffe3e, 0xffff19,
- 0x00005e
-};
-
-static const int lpf1_mode3[] = {
- 0x000000, 0xfffc12, 0xfff5cb, 0xfff022, 0xffeffa,
- 0xfffa03, 0x000f84, 0x002b96, 0x00429d, 0x00455c,
- 0x00277a, 0xffe762, 0xff93e1, 0xff4bc4, 0xff3567,
- 0xff6f81, 0x000000, 0x00c850, 0x018619, 0x01e3e3,
- 0x01972b, 0x008323, 0xfed332, 0xfd00e8, 0xfbbe66,
- 0xfbc791, 0xfda631, 0x017bb2, 0x06e40b, 0x0cfe8e,
- 0x129dfd, 0x1693d6, 0x18011b, 0x1693d6, 0x129dfd,
- 0x0cfe8e, 0x06e40b, 0x017bb2, 0xfda631, 0xfbc791,
- 0xfbbe66, 0xfd00e8, 0xfed332, 0x008323, 0x01972b,
- 0x01e3e3, 0x018619, 0x00c850, 0x000000, 0xff6f81,
- 0xff3567, 0xff4bc4, 0xff93e1, 0xffe762, 0x00277a,
- 0x00455c, 0x00429d, 0x002b96, 0x000f84, 0xfffa03,
- 0xffeffa, 0xfff022, 0xfff5cb, 0xfffc12, 0x000000,
-};
-
-static const int lpf3_mode3[] = {
- 0x000000, 0xfff4f6, 0x000000, 0x001e36, 0x000000,
- 0xffbfb6, 0x000000, 0x007789, 0x000000, 0xff3423,
- 0x000000, 0x0147cc, 0x000000, 0xfe0523, 0x000000,
- 0x02ffbb, 0x000000, 0xfb728b, 0x000000, 0x0732af,
- 0x000000, 0xf301d5, 0x000000, 0x288c99, 0x40023d,
- 0x288c99, 0x000000, 0xf301d5, 0x000000, 0x0732af,
- 0x000000, 0xfb728b, 0x000000, 0x02ffbb, 0x000000,
- 0xfe0523, 0x000000, 0x0147cc, 0x000000, 0xff3423,
- 0x000000, 0x007789, 0x000000, 0xffbfb6, 0x000000,
- 0x001e36, 0x000000, 0xfff4f6, 0x000000
-};
-
-static const int lpf1_mode4[] = {
- 0xfff71d, 0xffd0ad, 0xffa4b6, 0xff8cdb, 0xffa5d4,
- 0x000000, 0x009021, 0x012899, 0x0181ac, 0x0151f3,
- 0x0070b6, 0xfef591, 0xfd46bc, 0xfc0b63, 0xfc00d4,
- 0xfdbd02, 0x017215, 0x06c95c, 0x0ce665, 0x1295f9,
- 0x169d63, 0x181214, 0x169d63, 0x1295f9, 0x0ce665,
- 0x06c95c, 0x017215, 0xfdbd02, 0xfc00d4, 0xfc0b63,
- 0xfd46bc, 0xfef591, 0x0070b6, 0x0151f3, 0x0181ac,
- 0x012899, 0x009021, 0x000000, 0xffa5d4, 0xff8cdb,
- 0xffa4b6, 0xffd0ad, 0xfff71d
-};
-
-static const int lpf3_mode4[] = {
- 0xffd46b, 0xffb7a1, 0x006ded, 0x009ddb, 0xff25e9,
- 0xfedaef, 0x018208, 0x01f591, 0xfd7972, 0xfcbff4,
- 0x043527, 0x058a27, 0xf872cb, 0xf4f5a2, 0x12ef7c,
- 0x399f1f, 0x399f1f, 0x12ef7c, 0xf4f5a2, 0xf872cb,
- 0x058a27, 0x043527, 0xfcbff4, 0xfd7972, 0x01f591,
- 0x018208, 0xfedaef, 0xff25e9, 0x009ddb, 0x006ded,
- 0xffb7a1, 0xffd46b
-};
static struct pdm_chipinfo g12a_pdm_chipinfo = {
.mute_fn = true,
.truncate_data = false,
+ .chnum_flag = true,
};
static struct pdm_chipinfo tl1_pdm_chipinfo = {
+++ /dev/null
-/*
- * sound/soc/amlogic/auge/vad_hw_coeff.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
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projects / GitHub / LineageOS / G12 / android_kernel_amlogic_linux-4.9.git / commitdiff