drm/i915: Move common engine setup into intel_engine_cs.c

Common code deserves to be put in a separate file from legacy and
execlists implementation for clarity and ease of maintenance.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 684fc1cd08fa90260529ca558b18118d118c8f9c..75318ebb8d25bda319216e717fd13ef88117743f 100644 (file)
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -40,6 +40,7 @@ i915-y += i915_cmd_parser.o \
          i915_gpu_error.o \
          i915_trace_points.o \
          intel_breadcrumbs.o \
+         intel_engine_cs.o \
          intel_lrc.o \
          intel_mocs.o \
          intel_ringbuffer.o \

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
new file mode 100644 (file)
index 0000000..80117b4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_ringbuffer.h"
+#include "intel_lrc.h"
+
+static const struct engine_info {
+       const char *name;
+       unsigned exec_id;
+       unsigned guc_id;
+       u32 mmio_base;
+       unsigned irq_shift;
+       int (*init_legacy)(struct intel_engine_cs *engine);
+       int (*init_execlists)(struct intel_engine_cs *engine);
+} intel_engines[] = {
+       [RCS] = {
+               .name = "render ring",
+               .exec_id = I915_EXEC_RENDER,
+               .guc_id = GUC_RENDER_ENGINE,
+               .mmio_base = RENDER_RING_BASE,
+               .irq_shift = GEN8_RCS_IRQ_SHIFT,
+               .init_execlists = logical_render_ring_init,
+               .init_legacy = intel_init_render_ring_buffer,
+       },
+       [BCS] = {
+               .name = "blitter ring",
+               .exec_id = I915_EXEC_BLT,
+               .guc_id = GUC_BLITTER_ENGINE,
+               .mmio_base = BLT_RING_BASE,
+               .irq_shift = GEN8_BCS_IRQ_SHIFT,
+               .init_execlists = logical_xcs_ring_init,
+               .init_legacy = intel_init_blt_ring_buffer,
+       },
+       [VCS] = {
+               .name = "bsd ring",
+               .exec_id = I915_EXEC_BSD,
+               .guc_id = GUC_VIDEO_ENGINE,
+               .mmio_base = GEN6_BSD_RING_BASE,
+               .irq_shift = GEN8_VCS1_IRQ_SHIFT,
+               .init_execlists = logical_xcs_ring_init,
+               .init_legacy = intel_init_bsd_ring_buffer,
+       },
+       [VCS2] = {
+               .name = "bsd2 ring",
+               .exec_id = I915_EXEC_BSD,
+               .guc_id = GUC_VIDEO_ENGINE2,
+               .mmio_base = GEN8_BSD2_RING_BASE,
+               .irq_shift = GEN8_VCS2_IRQ_SHIFT,
+               .init_execlists = logical_xcs_ring_init,
+               .init_legacy = intel_init_bsd2_ring_buffer,
+       },
+       [VECS] = {
+               .name = "video enhancement ring",
+               .exec_id = I915_EXEC_VEBOX,
+               .guc_id = GUC_VIDEOENHANCE_ENGINE,
+               .mmio_base = VEBOX_RING_BASE,
+               .irq_shift = GEN8_VECS_IRQ_SHIFT,
+               .init_execlists = logical_xcs_ring_init,
+               .init_legacy = intel_init_vebox_ring_buffer,
+       },
+};
+
+static struct intel_engine_cs *
+intel_engine_setup(struct drm_i915_private *dev_priv,
+                  enum intel_engine_id id)
+{
+       const struct engine_info *info = &intel_engines[id];
+       struct intel_engine_cs *engine = &dev_priv->engine[id];
+
+       engine->id = id;
+       engine->i915 = dev_priv;
+       engine->name = info->name;
+       engine->exec_id = info->exec_id;
+       engine->hw_id = engine->guc_id = info->guc_id;
+       engine->mmio_base = info->mmio_base;
+       engine->irq_shift = info->irq_shift;
+
+       return engine;
+}
+
+/**
+ * intel_engines_init() - allocate, populate and init the Engine Command Streamers
+ * @dev: DRM device.
+ *
+ * Return: non-zero if the initialization failed.
+ */
+int intel_engines_init(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       unsigned int mask = 0;
+       int (*init)(struct intel_engine_cs *engine);
+       unsigned int i;
+       int ret;
+
+       WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
+               GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
+
+       for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
+               if (!HAS_ENGINE(dev_priv, i))
+                       continue;
+
+               if (i915.enable_execlists)
+                       init = intel_engines[i].init_execlists;
+               else
+                       init = intel_engines[i].init_legacy;
+
+               if (!init)
+                       continue;
+
+               ret = init(intel_engine_setup(dev_priv, i));
+               if (ret)
+                       goto cleanup;
+
+               mask |= ENGINE_MASK(i);
+       }
+
+       /*
+        * Catch failures to update intel_engines table when the new engines
+        * are added to the driver by a warning and disabling the forgotten
+        * engines.
+        */
+       if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask)) {
+               struct intel_device_info *info =
+                       (struct intel_device_info *)&dev_priv->info;
+               info->ring_mask = mask;
+       }
+
+       return 0;
+
+cleanup:
+       for (i = 0; i < I915_NUM_ENGINES; i++) {
+               if (i915.enable_execlists)
+                       intel_logical_ring_cleanup(&dev_priv->engine[i]);
+               else
+                       intel_cleanup_engine(&dev_priv->engine[i]);
+       }
+
+       return ret;
+}
+

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2e13a3a26245eb19f75a8606164af9b1c40521c0..6e88d9af93282270ef19116e92dab7b2085bbd04 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2083,7 +2083,7 @@ error:
        return ret;
 }
 
-static int logical_render_ring_init(struct intel_engine_cs *engine)
+int logical_render_ring_init(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
        int ret;
@@ -2126,147 +2126,13 @@ static int logical_render_ring_init(struct intel_engine_cs *engine)
        return ret;
 }
 
-static int logical_xcs_ring_init(struct intel_engine_cs *engine)
+int logical_xcs_ring_init(struct intel_engine_cs *engine)
 {
        logical_ring_setup(engine);
 
        return logical_ring_init(engine);
 }
 
-static const struct engine_info {
-       const char *name;
-       unsigned exec_id;
-       unsigned guc_id;
-       u32 mmio_base;
-       unsigned irq_shift;
-       int (*init_legacy)(struct intel_engine_cs *engine);
-       int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
-       [RCS] = {
-               .name = "render ring",
-               .exec_id = I915_EXEC_RENDER,
-               .guc_id = GUC_RENDER_ENGINE,
-               .mmio_base = RENDER_RING_BASE,
-               .irq_shift = GEN8_RCS_IRQ_SHIFT,
-               .init_execlists = logical_render_ring_init,
-               .init_legacy = intel_init_render_ring_buffer,
-       },
-       [BCS] = {
-               .name = "blitter ring",
-               .exec_id = I915_EXEC_BLT,
-               .guc_id = GUC_BLITTER_ENGINE,
-               .mmio_base = BLT_RING_BASE,
-               .irq_shift = GEN8_BCS_IRQ_SHIFT,
-               .init_execlists = logical_xcs_ring_init,
-               .init_legacy = intel_init_blt_ring_buffer,
-       },
-       [VCS] = {
-               .name = "bsd ring",
-               .exec_id = I915_EXEC_BSD,
-               .guc_id = GUC_VIDEO_ENGINE,
-               .mmio_base = GEN6_BSD_RING_BASE,
-               .irq_shift = GEN8_VCS1_IRQ_SHIFT,
-               .init_execlists = logical_xcs_ring_init,
-               .init_legacy = intel_init_bsd_ring_buffer,
-       },
-       [VCS2] = {
-               .name = "bsd2 ring",
-               .exec_id = I915_EXEC_BSD,
-               .guc_id = GUC_VIDEO_ENGINE2,
-               .mmio_base = GEN8_BSD2_RING_BASE,
-               .irq_shift = GEN8_VCS2_IRQ_SHIFT,
-               .init_execlists = logical_xcs_ring_init,
-               .init_legacy = intel_init_bsd2_ring_buffer,
-       },
-       [VECS] = {
-               .name = "video enhancement ring",
-               .exec_id = I915_EXEC_VEBOX,
-               .guc_id = GUC_VIDEOENHANCE_ENGINE,
-               .mmio_base = VEBOX_RING_BASE,
-               .irq_shift = GEN8_VECS_IRQ_SHIFT,
-               .init_execlists = logical_xcs_ring_init,
-               .init_legacy = intel_init_vebox_ring_buffer,
-       },
-};
-
-struct intel_engine_cs *
-intel_engine_setup(struct drm_i915_private *dev_priv,
-                  enum intel_engine_id id)
-{
-       const struct engine_info *info = &intel_engines[id];
-       struct intel_engine_cs *engine = &dev_priv->engine[id];
-
-       engine->id = id;
-       engine->i915 = dev_priv;
-       engine->name = info->name;
-       engine->exec_id = info->exec_id;
-       engine->hw_id = engine->guc_id = info->guc_id;
-       engine->mmio_base = info->mmio_base;
-       engine->irq_shift = info->irq_shift;
-
-       return engine;
-}
-
-/**
- * intel_engines_init() - allocate, populate and init the Engine Command Streamers
- * @dev: DRM device.
- *
- * Return: non-zero if the initialization failed.
- */
-int intel_engines_init(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       unsigned int mask = 0;
-       int (*init)(struct intel_engine_cs *engine);
-       unsigned int i;
-       int ret;
-
-       WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
-               GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
-
-       for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
-               if (!HAS_ENGINE(dev_priv, i))
-                       continue;
-
-               if (i915.enable_execlists)
-                       init = intel_engines[i].init_execlists;
-               else
-                       init = intel_engines[i].init_legacy;
-
-               if (!init)
-                       continue;
-
-               ret = init(intel_engine_setup(dev_priv, i));
-               if (ret)
-                       goto cleanup;
-
-               mask |= ENGINE_MASK(i);
-       }
-
-       /*
-        * Catch failures to update intel_engines table when the new engines
-        * are added to the driver by a warning and disabling the forgotten
-        * engines.
-        */
-       if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask)) {
-               struct intel_device_info *info =
-                       (struct intel_device_info *)&dev_priv->info;
-               info->ring_mask = mask;
-       }
-
-       return 0;
-
-cleanup:
-       for (i = 0; i < I915_NUM_ENGINES; i++) {
-               if (i915.enable_execlists)
-                       intel_logical_ring_cleanup(&dev_priv->engine[i]);
-               else
-                       intel_cleanup_engine(&dev_priv->engine[i]);
-       }
-
-       return ret;
-}
-
 static u32
 make_rpcs(struct drm_i915_private *dev_priv)
 {

diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index aa8905c42de790756b6fad128bd8e09bc9dfa68f..938e3eec06cfbdbaec76af9407872e178afb8ab5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -67,6 +67,9 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
 void intel_logical_ring_stop(struct intel_engine_cs *engine);
 void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
+int logical_render_ring_init(struct intel_engine_cs *engine);
+int logical_xcs_ring_init(struct intel_engine_cs *engine);
+
 int intel_engines_init(struct drm_device *dev);
 
 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a25eac17efcd12036b83c5d4ccf7b38edcbebb19..db7613e8d585ee97e64d5fcef227ece433d00a40 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -362,10 +362,6 @@ struct intel_engine_cs {
        u32 (*get_cmd_length_mask)(u32 cmd_header);
 };
 
-struct intel_engine_cs *
-intel_engine_setup(struct drm_i915_private *dev_priv,
-                  enum intel_engine_id id);
-
 static inline bool
 intel_engine_initialized(const struct intel_engine_cs *engine)
 {