}
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
- if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) {
- rbo->placements[c].fpfn = 0;
- rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT;
- } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
+ if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
TTM_PL_FLAG_UNCACHED;
}
if (domain & AMDGPU_GEM_DOMAIN_CPU) {
- if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) {
- rbo->placements[c].fpfn = 0;
- rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM;
- } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
+ if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
rbo->placements[c].fpfn = 0;
rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
TTM_PL_FLAG_UNCACHED;
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
/* Flag that CPU access will not work, this VRAM domain is invisible */
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
-/* Flag that un-cached attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2)
/* Flag that USWC attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3)
+#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag mask for GTT domain_flags */
#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
- (AMDGPU_GEM_CREATE_CPU_GTT_WC | \
- AMDGPU_GEM_CREATE_CPU_GTT_UC | \
+ (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
AMDGPU_GEM_CREATE_NO_CPU_ACCESS)