atl1c: clear WoL status when reset pcie

WoL status is read-clear and should be cleared when in S0
status.
putting it in atl1c_reset_pcie is more suitable than
in atl1c_get_permanent_address.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 209c1791531c3843d0df6e438f0b87c37a8dd77d..49f433e688c76463538a47c977d056b2fe4591a1 100644 (file)
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -73,7 +73,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
        u32 otp_ctrl_data;
        u32 twsi_ctrl_data;
        u32 ltssm_ctrl_data;
-       u32 wol_data;
        u8  eth_addr[ETH_ALEN];
        u16 phy_data;
        bool raise_vol = false;
@@ -114,10 +113,6 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
                ltssm_ctrl_data &= ~LTSSM_ID_EN_WRO;
                AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
 
-               /* clear any WOL settings */
-               AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
-               AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
-
 
                AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
                twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 6d5b37479ec4083f5696d3ad7f6183cb91390c08..63da1d8c54c50ac0043cdc0b81efa970fd80b05a 100644 (file)
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -133,6 +133,9 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
         */
        pci_enable_wake(pdev, PCI_D3hot, 0);
        pci_enable_wake(pdev, PCI_D3cold, 0);
+       /* wol sts read-clear */
+       AT_READ_REG(hw, REG_WOL_CTRL, &data);
+       AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
 
        /*
         * Mask some pcie error bits