rt2800: move RFCSR6_R2 & LDO_CFG0 setup to 3572 specific rfcsr init
authorStanislaw Gruszka <stf_xl@wp.pl>
Wed, 17 Apr 2013 12:08:15 +0000 (14:08 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 22 Apr 2013 19:20:17 +0000 (15:20 -0400)
Acked-by: Gertjan van Wingerde <gwingerde@gmail.com>
Signed-off-by: Stanislaw Gruszka <stf_xl@wp.pl>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/rt2x00/rt2800lib.c

index 102e50c383ad42e56e4f86e9806c19d7879482aa..6907cd313477e295e12b5fdcba8a39db45b33bb1 100644 (file)
@@ -4709,6 +4709,9 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
 
 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
 {
+       u8 rfcsr;
+       u32 reg;
+
        rt2800_rf_init_calibration(rt2x00dev, 30);
 
        rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
@@ -4742,6 +4745,20 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
        rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
        rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
        rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
+
+       rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
+       rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
+
+       rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
+       rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
+       rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
+       rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
+       msleep(1);
+       rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
+       rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
+       rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
+       rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 }
 
 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
@@ -4994,23 +5011,6 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                return 0;
        }
 
-
-       if (rt2x00_rt(rt2x00dev, RT3572)) {
-               rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
-               rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
-               rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
-
-               rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
-               rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
-               rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
-               rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
-               msleep(1);
-               rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
-               rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
-               rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
-               rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
-       }
-
        /*
         * Set RX Filter calibration for 20MHz and 40MHz
         */