#define S3C2410_WTCLRINT 0x0c
#define S3C2410_WTCNT_MAXCNT 0xffff
+#define S3C2410_WTCLRINT 0x0C
#define S3C2410_WTCON_RSTEN (1 << 0)
#define S3C2410_WTCON_INTEN (1 << 2)
return 0;
}
+static int s3c2410wdt_stop_intclear(struct s3c2410_wdt *wdt)
+{
+ spin_lock(&wdt->lock);
+ __s3c2410wdt_stop(wdt);
+ writel(1, wdt->reg_base + S3C2410_WTCLRINT);
+ spin_unlock(&wdt->lock);
+
+ return 0;
+}
+
static int s3c2410wdt_start(struct watchdog_device *wdd)
{
unsigned long wtcon;
dev_err(dev, "cannot register watchdog (%d)\n", ret);
goto err_cpufreq;
}
-
+ /* Prevent watchdog reset while setting */
+ s3c2410wdt_stop_intclear(wdt);
+ /* Enable pmu watchdog reset control */
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
if (ret < 0)
goto err_unregister;
}
#ifdef CONFIG_PM_SLEEP
-
static int s3c2410wdt_suspend(struct device *dev)
{
- int ret;
+ int ret = 0;
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
/* Save watchdog state, and turn it off. */
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
- ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
- if (ret < 0)
- return ret;
-
/* Note that WTCNT doesn't need to be saved. */
s3c2410wdt_stop(&wdt->wdt_device);
- return 0;
+ ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
+
+ return ret;
}
static int s3c2410wdt_resume(struct device *dev)
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
+ s3c2410wdt_stop_intclear(wdt);
+ /* Enable pmu watchdog reset control */
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
if (ret < 0)
return ret;