gpu: duplicate the max freq for S805Y [1/1]

PD#SWPL-940

Problem:
S805Y only max support freq is 666M.
if dts was wrong, kernel panic.

Solution:
limit the freq to 666M

Verify:
s805y_p215

Change-Id: Id4f3c243041febfc0939d22705e749b70d41b551
Signed-off-by: Jiyu Yang <jiyu.yang@amlogic.com>

diff --git a/utgard/platform/meson_bu/mali_clock.c b/utgard/platform/meson_bu/mali_clock.c
index e477f3eaa49da4e99dbaa69fa6ce4dace96b5516..ffe6680b9b1616f33cd5b408235d08c8094b176a 100644 (file)
--- a/utgard/platform/meson_bu/mali_clock.c
+++ b/utgard/platform/meson_bu/mali_clock.c
@@ -285,10 +285,6 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
                        dev_notice(&pdev->dev, "read clk_freq failed\n");
                }
 
-               if (is_meson_gxl_package_805Y()) {
-                       if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ)
-                               continue;
-               }
                ret = of_property_read_string(gpu_clk_dn,"clk_parent",
                                                                                &dvfs_tbl->clk_parent);
                if (ret) {
@@ -483,6 +479,7 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
        struct mali_gpu_clk_item *clk_item;
        phandle dvfs_clk_hdl;
        mali_dvfs_threshold_table *dvfs_tbl = NULL;
+       mali_dvfs_threshold_table *last_dvfs_tbl = NULL;
        uint32_t *clk_sample = NULL;
 
        struct property *prop;
@@ -572,6 +569,11 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
                if (ret) {
                        dev_notice(&pdev->dev, "read clk_freq failed\n");
                }
+               if (is_meson_gxl_package_805Y()) {
+                       if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ) {
+                               continue;
+                       }
+               }
 
                ret = of_property_read_string(gpu_clk_dn,"clk_parent",
                                &dvfs_tbl->clk_parent);
@@ -608,6 +610,7 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
 
                *clk_sample = dvfs_tbl->clk_freq / 1000000;
 
+               last_dvfs_tbl = dvfs_tbl;
                dvfs_tbl ++;
                clk_item ++;
                clk_sample ++;
@@ -615,6 +618,19 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
                mpdata->dvfs_table_size ++;
        }
 
+       if ((is_meson_gxl_package_805Y()) && (length > mpdata->dvfs_table_size)) {
+               dvfs_tbl = last_dvfs_tbl;
+               last_dvfs_tbl = dvfs_tbl - 1;
+               if (dvfs_tbl->clk_freq != last_dvfs_tbl->clk_freq) {
+                       dvfs_tbl ++;
+                       last_dvfs_tbl ++;
+                       memcpy(dvfs_tbl, last_dvfs_tbl, sizeof(*dvfs_tbl));
+                       *clk_sample = dvfs_tbl->clk_freq / 1000000;
+                       dvfs_tbl->freq_index = i;
+                       mpdata->dvfs_table_size ++;
+               }
+       }
+
        ret = of_property_read_u32(gpu_dn,"max_clk",
                        &mpdata->cfg_clock);
        if (ret) {