drm/amdgpu/gfx8: fix spelling typo in mqd allocation
authorAlex Deucher <alexander.deucher@amd.com>
Sat, 19 Aug 2017 03:39:52 +0000 (23:39 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 24 Aug 2017 15:48:40 +0000 (11:48 -0400)
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/include/vi_structs.h

index 832e592fcd0725b0f32406aec57d2fc466fe1179..fc260c13b1da4938443a972aecea21c2250d7e40 100644 (file)
@@ -4579,9 +4579,9 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
        mqd->compute_misc_reserved = 0x00000003;
        if (!(adev->flags & AMD_IS_APU)) {
                mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
-                                            + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
+                                            + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
                mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
-                                            + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
+                                            + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
        }
        eop_base_addr = ring->eop_gpu_addr >> 8;
        mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
@@ -4768,8 +4768,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
                mutex_unlock(&adev->srbm_mutex);
        } else {
                memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-               ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
-               ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
                mutex_lock(&adev->srbm_mutex);
                vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
                gfx_v8_0_mqd_init(ring);
@@ -4792,8 +4792,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
 
        if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
                memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-               ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
-               ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+               ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
                mutex_lock(&adev->srbm_mutex);
                vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
                gfx_v8_0_mqd_init(ring);
index ca93b5160ba6cfb34b5cc4cc4f409bda66ba0a35..3e606a761d0e6466be9e40002e4fab09f2ca4a5c 100644 (file)
@@ -419,8 +419,8 @@ struct vi_mqd_allocation {
        struct vi_mqd mqd;
        uint32_t wptr_poll_mem;
        uint32_t rptr_report_mem;
-       uint32_t dyamic_cu_mask;
-       uint32_t dyamic_rb_mask;
+       uint32_t dynamic_cu_mask;
+       uint32_t dynamic_rb_mask;
 };
 
 struct cz_mqd {