drm/i915: Move HAS_RC6 definition to platform definition

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80ca60d5ac16e1ea6cd4301966c5e59552ae4cdf..c16e9cbeabc7dd7e100d19ca5dd2b707a1fe3360 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -658,6 +658,7 @@ struct intel_csr {
        func(has_runtime_pm) sep \
        func(has_csr) sep \
        func(has_resource_streamer) sep \
+       func(has_rc6) sep \
        func(has_pipe_cxsr) sep \
        func(has_hotplug) sep \
        func(cursor_needs_physical) sep \
@@ -2790,7 +2791,7 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)           (INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)    (INTEL_INFO(dev)->has_runtime_pm)
-#define HAS_RC6(dev)           (INTEL_INFO(dev)->gen >= 6)
+#define HAS_RC6(dev)           (INTEL_INFO(dev)->has_rc6)
 #define HAS_RC6p(dev)          (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
 #define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 46c48eda23f61eb6dc990fd4d4aefd679319b5c5..42108dcaba17c01343ae4f08a3b40204c140d946 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_fbc = 1, \
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
        .has_llc = 1, \
+       .has_rc6 = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
        CURSOR_OFFSETS
 
@@ -219,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
        .has_fbc = 1, \
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
        .has_llc = 1, \
+       .has_rc6 = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
        IVB_CURSOR_OFFSETS
 
@@ -243,6 +245,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
        .gen = 7, .num_pipes = 2, \
        .has_psr = 1, \
        .has_runtime_pm = 1, \
+       .has_rc6 = 1, \
        .need_gfx_hws = 1, .has_hotplug = 1, \
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
        .display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_psr = 1,
        .has_runtime_pm = 1,
        .has_resource_streamer = 1,
+       .has_rc6 = 1,
        .display_mmio_offset = VLV_DISPLAY_BASE,
        GEN_CHV_PIPEOFFSETS,
        CURSOR_OFFSETS,
@@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = {
        .has_pooled_eu = 0,
        .has_csr = 1,
        .has_resource_streamer = 1,
+       .has_rc6 = 1,
        GEN_DEFAULT_PIPEOFFSETS,
        IVB_CURSOR_OFFSETS,
        BDW_COLORS,