[COMMON] spi: s3c64xx: Add return value check after clk_set_rate

CID: 197154

After clk_set_rate we need to check the return value is fine.

Change-Id: I66526a3d180626e9c8bedb7094f325e0044e5975
Signed-off-by: Kyungwoo Kang <kwoo.kang@samsung.com>

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index e893912152b3c8ef12f8c247d3873865c1a0423f..d8023ea69af4a67c8c19e97626d5f4826850312e 100644 (file)
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -740,6 +740,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
        struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
        void __iomem *regs = sdd->regs;
        u32 val;
+       int ret;
 
        /* Disable Clock */
        if (!sdd->port_conf->clk_from_cmu) {
@@ -809,7 +810,10 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 
        if (sdd->port_conf->clk_from_cmu) {
                /* There is a quarter-multiplier before the SPI */
-               clk_set_rate(sdd->src_clk, sdd->cur_speed * 4);
+               ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 4);
+               if (ret < 0)
+                       dev_err(&sdd->pdev->dev, "SPI clk set failed\n");
+
        } else {
                /* Configure Clock */
                val = readl(regs + S3C64XX_SPI_CLK_CFG);