KVM: MIPS/T&E: Report correct dcache line size

Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL,
so encode the correct value for the guest CP0_Config1.DL based on
cpu_dcache_line_size().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c
index 75ba3c4b7cd57fab0d8934f8a5b25459cb5b530f..a563759fd142c6b18ca2fd3b06a8a7703d8714d3 100644 (file)
--- a/arch/mips/kvm/trap_emul.c
+++ b/arch/mips/kvm/trap_emul.c
@@ -12,6 +12,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
+#include <linux/log2.h>
 #include <linux/uaccess.h>
 #include <linux/vmalloc.h>
 #include <asm/mmu_context.h>
@@ -644,6 +645,13 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
        /* Read the cache characteristics from the host Config1 Register */
        config1 = (read_c0_config1() & ~0x7f);
 
+       /* DCache line size not correctly reported in Config1 on Octeon CPUs */
+       if (cpu_dcache_line_size()) {
+               config1 &= ~MIPS_CONF1_DL;
+               config1 |= ((ilog2(cpu_dcache_line_size()) - 1) <<
+                           MIPS_CONF1_DL_SHF) & MIPS_CONF1_DL;
+       }
+
        /* Set up MMU size */
        config1 &= ~(0x3f << 25);
        config1 |= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25);