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DaVinci: DM365: Fix Compilation issue due to PINMUX entry
authorSandeep Paulraj <s-paulraj@ti.com>
Mon, 3 Aug 2009 17:58:24 +0000 (13:58 -0400)
committerKevin Hilman <khilman@deeprootsystems.com>
Wed, 26 Aug 2009 08:55:50 +0000 (11:55 +0300)
The mask can hold only 8 bit values. This gave a
compilation warning. This patch rectifies the warning.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
arch/arm/mach-davinci/dm365.c patch | blob | blame | history
arch/arm/mach-davinci/include/mach/mux.h patch | blob | blame | history

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index aa3b0bbdda7339f0398ca9f28ac1ad982ca75fe4..0a33e128f3f7ed41584151f5b89e9613f01c3395 100644 (file)
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -582,7 +582,8 @@ MUX_CFG(DM365,      VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 MUX_CFG(DM365, VIN_CAM_WEN,    0,   14,    3,    0,     false)
 MUX_CFG(DM365, VIN_CAM_VD,     0,   13,    1,    0,     false)
 MUX_CFG(DM365, VIN_CAM_HD,     0,   12,    1,    0,     false)
-MUX_CFG(DM365, VIN_YIN_EN,     0,   0,     0xfff, 0,    false)
+MUX_CFG(DM365, VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
+MUX_CFG(DM365, VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 
 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 368fca69197d18cbcb3fe7b152aeb801905b5eb0..a676b2f47aab053d4558bb004329bc331252f9d7 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -280,7 +280,8 @@ enum davinci_dm365_index {
        DM365_VIN_CAM_WEN,
        DM365_VIN_CAM_VD,
        DM365_VIN_CAM_HD,
-       DM365_VIN_YIN_EN,
+       DM365_VIN_YIN4_7_EN,
+       DM365_VIN_YIN0_3_EN,
 
        /* IRQ muxing */
        DM365_INT_EDMA_CC,