drm/radeon/cayman: add some missing regs to the VM reg checker
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 8 Nov 2012 15:08:04 +0000 (10:08 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 8 Nov 2012 15:24:07 +0000 (10:24 -0500)
These regs were being wronly rejected leading to rendering
issues.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=56876

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
drivers/gpu/drm/radeon/evergreen_cs.c
drivers/gpu/drm/radeon/evergreend.h

index 95e6318b62680652a2b600982dda4d7a39368292..c042e497e4507eaebfd91bb477acbc7520f0143d 100644 (file)
@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg)
        /* check config regs */
        switch (reg) {
        case GRBM_GFX_INDEX:
+       case CP_STRMOUT_CNTL:
+       case CP_COHER_CNTL:
+       case CP_COHER_SIZE:
        case VGT_VTX_VECT_EJECT_REG:
        case VGT_CACHE_INVALIDATION:
        case VGT_GS_VERTEX_REUSE:
index df542f1a5dfbf38198d6bfbe329fd6964eacf352..2bc0f6a1b428ab8151b2a7fa57d5f7848ab0dda6 100644 (file)
 #define                FB_READ_EN                                      (1 << 0)
 #define                FB_WRITE_EN                                     (1 << 1)
 
+#define        CP_STRMOUT_CNTL                                 0x84FC
+
+#define        CP_COHER_CNTL                                   0x85F0
+#define        CP_COHER_SIZE                                   0x85F4
 #define        CP_COHER_BASE                                   0x85F8
 #define        CP_STALLED_STAT1                        0x8674
 #define        CP_STALLED_STAT2                        0x8678