"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
+ /*set dynamic gp1 clk to val * 1000 *1000*/
+ dynamic_gp1_clk = <1000>;
cpu-supply = <&vddcpu0>;
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
#include <linux/delay.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/driver.h>
-
+#include <linux/amlogic/pm.h>
#include "../../regulator/internal.h"
#include <linux/amlogic/scpi_protocol.h>
#include "../../base/power/opp/opp.h"
if (__clk_get_enable_count(high_freq_clk_p) >= 1)
clk_disable_unprepare(high_freq_clk_p);
}
-
if (!ret) {
/*
* FIXME: clk_set_rate hasn't returned an error here however it
volt_tol = DEF_VOLT_TOL;
pr_info("value of voltage_tolerance %u\n", volt_tol);
+ if (of_property_read_u32(np, "dynamic_gp1_clk",
+ &gp1_clk_target)) {
+ pr_err("%s:don't find the node <dynamic_gp1_clk>\n",
+ __func__);
+ gp1_clk_target = 0;
+ }
+ pr_info("value of gp1_clk_target %u\n", gp1_clk_target);
+
if (cur_cluster < MAX_CLUSTERS)
cpumask_copy(policy->cpus, topology_core_cpumask(policy->cpu));
static int meson_cpufreq_suspend(struct cpufreq_policy *policy)
{
+ struct clk *dsu_pre_parent;
+ struct meson_cpufreq_driver_data *cpufreq_data;
+ int ret = 0;
- return cpufreq_generic_suspend(policy);
+ cpufreq_data = policy->driver_data;
+ dsu_pre_parent = cpufreq_data->clk_dsu_pre;
+
+ if (is_pm_freeze_mode() && gp1_clk_target) {
+ ret = __cpufreq_driver_target(policy, gp1_clk_target
+ * 1000, CPUFREQ_RELATION_H);
+ if (__clk_get_enable_count(dsu_pre_parent) == 0) {
+ ret = clk_prepare_enable(dsu_pre_parent);
+ if (ret) {
+ pr_err("%s: CPU%d gp1 pll enable failed,ret = %d\n",
+ __func__, policy->cpu, ret);
+ return ret;
+ }
+ }
+ /*set gp1 pll to 1.2G*/
+ clk_set_rate(dsu_pre_parent, 1200 * 1000 * 1000);
+ pr_info("gp1 pll =%lu!\n", clk_get_rate(dsu_pre_parent));
+ return ret;
+ } else
+ return cpufreq_generic_suspend(policy);
+ return 0;
}
static int meson_cpufreq_resume(struct cpufreq_policy *policy)
#define DSU_HIGH_RATE (1500 * 1000)
#define CPU_CMP_RATE (1800 * 1000)
+unsigned int gp1_clk_target;
/*whether use different tables or not*/
bool cpufreq_tables_supply;
static unsigned int hispeed_cpufreq_max;