* ata_generic.c - Generic PATA/SATA controller driver.
* Copyright 2005 Red Hat Inc <alan@redhat.com>, all rights reserved.
*
- * Elements from ide/pci/generic.c
+ * Elements from ide/pci/generic.c
* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
* Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
*
* May be copied or modified under the terms of the GNU General Public License
- *
+ *
* Driver for PCI IDE interfaces implementing the standard bus mastering
* interface functionality. This assumes the BIOS did the drive set up and
* tuning for us. By default we do not grab all IDE class devices as they
* may have other drivers or need fixups to avoid problems. Instead we keep
* a default list of stuff without documentation/driver that appears to
- * work.
+ * work.
*/
#include <linux/kernel.h>
*
* Set up cable type and use generic probe init
*/
-
+
static int generic_pre_reset(struct ata_port *ap)
{
ap->cbl = ATA_CBL_PATA80;
* None (inherited from caller).
*/
-
+
static void generic_error_handler(struct ata_port *ap)
{
ata_bmdma_drive_eh(ap, generic_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
* Use a non standard set_mode function. We don't want to be tuned.
* The BIOS configured everything. Our job is not to fiddle. We
* read the dma enabled bits from the PCI configuration of the device
- * and respect them.
+ * and respect them.
*/
-
+
static void generic_set_mode(struct ata_port *ap)
{
int dma_enabled = 0;
/* Bits 5 and 6 indicate if DMA is active on master/slave */
if (ap->ioaddr.bmdma_addr)
dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-
+
for (i = 0; i < ATA_MAX_DEVICES; i++) {
struct ata_device *dev = &ap->device[i];
if (ata_dev_enabled(dev)) {
/* We don't really care */
dev->pio_mode = XFER_PIO_0;
dev->dma_mode = XFER_MW_DMA_0;
- /* We do need the right mode information for DMA or PIO
+ /* We do need the right mode information for DMA or PIO
and this comes from the current configuration flags */
if (dma_enabled & (1 << (5 + i))) {
dev->xfer_mode = XFER_MW_DMA_0;
static struct ata_port_operations generic_port_ops = {
.set_mode = generic_set_mode,
-
+
.port_disable = ata_port_disable,
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.bmdma_start = ata_bmdma_start,
.bmdma_stop = ata_bmdma_stop,
.bmdma_status = ata_bmdma_status,
-
+
.data_xfer = ata_pio_data_xfer,
.freeze = ata_bmdma_freeze,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
-
+};
+
static int all_generic_ide; /* Set to claim all devices */
/**
* @id: match entry
*
* Called each time a matching IDE interface is found. We check if the
- * interface is one we wish to claim and if so we perform any chip
+ * interface is one we wish to claim and if so we perform any chip
* specific hacks then let the ATA layer do the heavy lifting.
*/
-
+
static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
u16 command;
.port_ops = &generic_port_ops
};
static struct ata_port_info *port_info[2] = { &info, &info };
-
+
/* Don't use the generic entry unless instructed to do so */
if (id->driver_data == 1 && all_generic_ide == 0)
return -ENODEV;
pci_read_config_word(dev, PCI_COMMAND, &command);
if (!(command & PCI_COMMAND_IO))
return -ENODEV;
-
+
if (dev->vendor == PCI_VENDOR_ID_AL)
ata_pci_clear_simplex(dev);
static struct pci_device_id ata_generic[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
- { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
+ { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
{ PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), },
{ PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), },
{ PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), },
ich6_sata_ahci = 8,
ich6m_sata_ahci = 9,
ich8_sata_ahci = 10,
-
+
/* constants for mapping table */
P0 = 0, /* port 0 */
P1 = 1, /* port 1 */
{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
/* C-ICH (i810E2) */
{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
- /* ESB (855GME/875P + 6300ESB) UDMA 100 */
+ /* ESB (855GME/875P + 6300ESB) UDMA 100 */
{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
/* ICH6 (and 6) (i915) UDMA 100 */
{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
.udma_mask = ATA_UDMA4,
.port_ops = &ich_pata_ops,
},
-
+
/* ich_pata_100: 3 */
{
.sht = &piix_sht,
u8 slave_data;
u8 udma_enable;
int control = 0;
-
+
/*
* See Intel Document 298600-004 for the timing programing rules
* for ICH controllers.
if (ata_pio_need_iordy(adev))
control |= 2; /* IE enable */
- /* Intel specifies that the PPE functionality is for disk only */
+ /* Intel specifies that the PPE functionality is for disk only */
if (adev->class == ATA_DEV_ATA)
control |= 4; /* PPE enable */
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
-
+
if (ap->udma_mask) {
pci_read_config_byte(dev, 0x48, &udma_enable);
udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
u8 speed = adev->dma_mode;
int devid = adev->devno + 2 * ap->port_no;
u8 udma_enable;
-
+
static const /* ISP RTC */
u8 timings[][2] = { { 0, 0 },
{ 0, 0 },
u16 udma_timing;
u16 ideconf;
int u_clock, u_speed;
-
+
/*
* UDMA is handled by a combination of clock switching and
- * selection of dividers
- *
+ * selection of dividers
+ *
* Handy rule: Odd modes are UDMATIMx 01, even are 02
- * except UDMA0 which is 00
+ * except UDMA0 which is 00
*/
u_speed = min(2 - (udma & 1), udma);
if (udma == 5)
u_clock = 1; /* 66Mhz */
else
u_clock = 0; /* 33Mhz */
-
+
udma_enable |= (1 << devid);
-
+
/* Load the CT/RP selection */
pci_read_config_word(dev, 0x4A, &udma_timing);
udma_timing &= ~(3 << (4 * devid));
udma_timing |= u_speed << (4 * devid);
pci_write_config_word(dev, 0x4A, udma_timing);
- if (isich) {
+ if (isich) {
/* Select a 33/66/100Mhz clock */
pci_read_config_word(dev, 0x54, &ideconf);
ideconf &= ~(0x1001 << devid);
XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
};
int pio = needed_pio[mwdma] - XFER_PIO_0;
-
+
control = 3; /* IORDY|TIME1 */
-
+
/* If the drive MWDMA is faster than it can do PIO then
we must force PIO into PIO0 */
-
+
if (adev->pio_mode < needed_pio[mwdma])
/* Enable DMA timing only */
control |= 8; /* PIO cycles in PIO0 */
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
pci_write_config_byte(dev, 0x44, slave_data);
} else { /* Master */
- master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
+ master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
and master timing bits */
master_data |= control;
master_data |=
/* ATA - FIFO on set nibble to 0x05, ATAPI - FIFO off, set nibble to
0x00. Not all the docs agree but the behaviour we now use is the
one stated in the BIOS Programming Guide */
-
+
pci_read_config_byte(pdev, pio_fifo, &fifo);
fifo &= ~(0x0F << shift);
if (on)
.sht = &ali_sht,
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_PIO_LBA48,
.pio_mask = 0x1f,
- .mwdma_mask = 0x07,
+ .mwdma_mask = 0x07,
.udma_mask = 0x07, /* UDMA33 */
.port_ops = &ali_20_port_ops
};
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 ata66;
-
+
if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
* TODO
* Testing work
*/
-
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
/*
* CMD64x specific registers definition.
*/
-
+
enum {
CFR = 0x50,
CFR_INTR_CH0 = 0x02,
pci_read_config_byte(pdev, BMIDECSR, &r);
if (r & (1 << ap->port_no))
ap->cbl = ATA_CBL_PATA80;
- else
+ else
ap->cbl = ATA_CBL_PATA40;
-
+
return ata_std_prereset(ap);
}
*
* Called to do the PIO mode setup.
*/
-
+
static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
struct ata_timing t;
const unsigned long T = 1000000 / 33;
const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
-
+
u8 reg;
-
+
/* Port layout is not logical so use a table */
- const u8 arttim_port[2][2] = {
+ const u8 arttim_port[2][2] = {
{ ARTTIM0, ARTTIM1 },
{ ARTTIM23, ARTTIM23 }
};
{ DRWTIM0, DRWTIM1 },
{ DRWTIM2, DRWTIM3 }
};
-
+
int arttim = arttim_port[ap->port_no][adev->devno];
int drwtim = drwtim_port[ap->port_no][adev->devno];
-
-
+
+
if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
return;
if (ap->port_no) {
/* Slave has shared address setup */
struct ata_device *pair = ata_dev_pair(adev);
-
+
if (pair) {
struct ata_timing tp;
ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
}
}
-
+
printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
t.active, t.recover, t.setup);
if (t.recover > 16) {
}
if (t.active > 16)
t.active = 16;
-
+
/* Now convert the clocks into values we can actually stuff into
the chip */
-
+
if (t.recover > 1)
t.recover--;
else
t.recover = 15;
-
+
if (t.setup > 4)
t.setup = 0xC0;
else
t.setup = setup_data[t.setup];
-
+
t.active &= 0x0F; /* 0 = 16 */
-
+
/* Load setup timing */
pci_read_config_byte(pdev, arttim, ®);
reg &= 0x3F;
reg |= t.setup;
pci_write_config_byte(pdev, arttim, reg);
-
+
/* Load active/recovery */
- pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
+ pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}
/**
*
* Called to do the DMA mode setup.
*/
-
+
static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
static const u8 udma_data[] = {
0x31, 0x21, 0x11, 0x25, 0x15, 0x05
};
- static const u8 mwdma_data[] = {
+ static const u8 mwdma_data[] = {
0x30, 0x20, 0x10
};
-
+
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 regU, regD;
int pciU = UDIDETCR0 + 8 * ap->port_no;
int pciD = BMIDESR0 + 8 * ap->port_no;
int shift = 2 * adev->devno;
-
+
pci_read_config_byte(pdev, pciD, ®D);
pci_read_config_byte(pdev, pciU, ®U);
regD &= ~(0x20 << shift);
regU &= ~(0x35 << shift);
-
+
if (adev->dma_mode >= XFER_UDMA_0)
regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
else
u8 dma_intr;
int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
int dma_mask = ap->port_no ? ARTTIM2 : CFR;
-
+
ata_bmdma_stop(qc);
-
+
pci_read_config_byte(pdev, dma_reg, &dma_intr);
pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}
-
+
/**
* cmd646r1_dma_stop - DMA stop callback
* @qc: Command in progress
{
ata_bmdma_stop(qc);
}
-
+
static struct scsi_host_template cmd64x_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations cmd646r1_port_ops = {
.port_disable = ata_port_disable,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations cmd648_port_ops = {
.port_disable = ata_port_disable,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
-
+};
+
static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
u32 class_rev;
-
+
static struct ata_port_info cmd_info[6] = {
{ /* CMD 643 - no UDMA */
.sht = &cmd64x_sht,
};
static struct ata_port_info *port_info[2], *info;
u8 mrdmode;
-
+
info = &cmd_info[id->driver_data];
-
+
pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xFF;
-
+
if (id->driver_data == 0) /* 643 */
ata_pci_clear_simplex(pdev);
-
+
if (pdev->device == PCI_DEVICE_ID_CMD_646) {
/* Does UDMA work ? */
if (class_rev > 4)
mrdmode &= ~ 0x30; /* IRQ set up */
mrdmode |= 0x02; /* Memory read line enable */
pci_write_config_byte(pdev, MRDMODE, mrdmode);
-
+
/* Force PIO 0 here.. */
-
+
/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
-
+
port_info[0] = port_info[1] = info;
return ata_pci_init_one(pdev, port_info, 2);
}
* linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
*
*/
-
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
*
* Called to do the PIO mode setup.
*/
-
+
static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
const unsigned long T = 1000000 / 33;
short time_16, time_8;
u32 addr;
-
+
if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) {
printk(KERN_ERR DRV_NAME ": mome computation failed.\n");
return;
time_16 = FIT(t.recover, 0, 15) | (FIT(t.active, 0, 15) << 4);
time_8 = FIT(t.act8b, 0, 15) | (FIT(t.rec8b, 0, 15) << 4);
-
+
if (adev->devno == 0) {
pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
-
+
addr &= ~0x0F; /* Mask bits */
addr |= FIT(t.setup, 0, 15);
-
+
pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16);
pci_write_config_byte(pdev, CY82_IDE_MASTER_IOW, time_16);
pci_write_config_byte(pdev, CY82_IDE_MASTER_8BIT, time_8);
} else {
pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
-
+
addr &= ~0xF0; /* Mask bits */
addr |= (FIT(t.setup, 0, 15) << 4);
*
* Called to do the DMA mode setup.
*/
-
+
static void cy82c693_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
int reg = CY82_INDEX_CHANNEL0 + ap->port_no;
-
+
/* Be afraid, be very afraid. Magic registers in low I/O space */
outb(reg, 0x22);
outb(adev->dma_mode - XFER_MW_DMA_0, 0x23);
-
+
/* 0x50 gives the best behaviour on the Alpha's using this chip */
outb(CY82_INDEX_TIMEOUT, 0x22);
outb(0x50, 0x23);
.set_piomode = cy82c693_set_piomode,
.set_dmamode = cy82c693_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
.port_ops = &cy82c693_port_ops
};
static struct ata_port_info *port_info[1] = { &info };
-
+
/* Devfn 1 is the ATA primary. The secondary is magic and on devfn2. For the
moment we don't handle the secondary. FIXME */
-
+
if (PCI_FUNC(pdev->devfn) != 1)
return -ENODEV;
-
+
return ata_pci_init_one(pdev, port_info, 1);
}
while(list[i] != NULL) {
if (!strncmp(list[i], s, len)) {
- printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
+ printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
modestr, list[i]);
return 1;
}
*
* Block UDMA on devices that cause trouble with this controller.
*/
-
+
static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
{
if (adev->class == ATA_DEV_ATA) {
* Return the 32bit register programming information for this channel
* that matches the speed provided.
*/
-
+
static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
{
struct hpt_clock *clocks = ap->host->private_data;
-
+
while(clocks->xfer_speed) {
if (clocks->xfer_speed == speed)
return clocks->timing;
BUG();
return 0xffffffffU; /* silence compiler warning */
}
-
+
static int hpt36x_pre_reset(struct ata_port *ap)
{
u8 ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
pci_read_config_byte(pdev, 0x5A, &ata66);
if (ata66 & (1 << ap->port_no))
ap->cbl = ATA_CBL_PATA40;
*
* Perform the reset handling for the 366/368
*/
-
+
static void hpt36x_error_handler(struct ata_port *ap)
{
ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
* @ap: ATA interface
* @adev: device on the interface
*
- * Perform PIO mode setup.
+ * Perform PIO mode setup.
*/
-
+
static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
if (fast & 0x80) {
fast &= ~0x80;
pci_write_config_byte(pdev, addr2, fast);
}
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt36x_find_mode(ap, adev->pio_mode);
mode &= ~0x8000000; /* No FIFO in PIO */
* Set up the channel for MWDMA or UDMA modes. Much the same as with
* PIO, load the mode number and then set MWDMA or UDMA flag.
*/
-
+
static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
if (fast & 0x80) {
fast &= ~0x80;
pci_write_config_byte(pdev, addr2, fast);
}
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt36x_find_mode(ap, adev->dma_mode);
mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
/*
* Configuration for HPT366/68
*/
-
+
static struct ata_port_operations hpt366_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt366_set_piomode,
.set_dmamode = hpt366_set_dmamode,
.mode_filter = hpt366_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* hpt36x_init_one - Initialise an HPT366/368
* HPT37x/30x 4 (HPT366) 3+ Other driver
*
*/
-
+
static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
static struct ata_port_info info_hpt366 = {
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xFF;
-
+
/* May be a later chip in disguise. Check */
/* Newer chips are not in the HPT36x driver. Ignore them */
if (class_rev > 2)
pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
pci_read_config_dword(dev, 0x40, ®1);
-
+
/* PCI clocking determines the ATA timing values to use */
/* info_hpt366 is safe against re-entry so we can scribble on it */
switch(reg1 & 0x700) {
{ XFER_UDMA_0, 0x14a0e73f },
{ XFER_MW_DMA_2, 0x2480fa73 },
- { XFER_MW_DMA_1, 0x2480fa77 },
+ { XFER_MW_DMA_1, 0x2480fa77 },
{ XFER_MW_DMA_0, 0x2480fb3f },
{ XFER_PIO_4, 0x0c82be73 },
* Return the 32bit register programming information for this channel
* that matches the speed provided.
*/
-
+
static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
{
struct hpt_clock *clocks = ap->host->private_data;
-
+
while(clocks->xfer_speed) {
if (clocks->xfer_speed == speed)
return clocks->timing;
while(list[i] != NULL) {
if (!strncmp(list[i], s, len)) {
- printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
+ printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
modestr, list[i]);
return 1;
}
*
* Block UDMA on devices that cause trouble with this controller.
*/
-
+
static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
{
if (adev->class != ATA_DEV_ATA) {
*
* Block UDMA on devices that cause trouble with this controller.
*/
-
+
static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
{
if (adev->class != ATA_DEV_ATA) {
}
return ata_pci_default_filter(ap, adev, mask);
}
-
+
/**
* hpt37x_pre_reset - reset the hpt37x bus
* @ap: ATA port to reset
*
* Perform the initial reset handling for the 370/372 and 374 func 0
*/
-
+
static int hpt37x_pre_reset(struct ata_port *ap)
{
u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
pci_read_config_byte(pdev, 0x5B, &scr2);
pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
/* Cable register now active */
pci_read_config_byte(pdev, 0x5A, &ata66);
/* Restore state */
pci_write_config_byte(pdev, 0x5B, scr2);
-
+
if (ata66 & (1 << ap->port_no))
ap->cbl = ATA_CBL_PATA40;
else
ap->cbl = ATA_CBL_PATA80;
/* Reset the state machine */
- pci_write_config_byte(pdev, 0x50, 0x37);
- pci_write_config_byte(pdev, 0x54, 0x37);
+ pci_write_config_byte(pdev, 0x50, 0x37);
+ pci_write_config_byte(pdev, 0x54, 0x37);
udelay(100);
-
+
return ata_std_prereset(ap);
}
*
* Perform probe for HPT37x, except for HPT374 channel 2
*/
-
+
static void hpt37x_error_handler(struct ata_port *ap)
{
ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
{
u16 mcr3, mcr6;
u8 ata66;
-
+
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
/* Do the extra channel work */
pci_read_config_word(pdev, 0x52, &mcr3);
/* Reset TCBLID/FCBLID to output */
pci_write_config_word(pdev, 0x52, mcr3);
pci_write_config_word(pdev, 0x56, mcr6);
-
+
if (ata66 & (1 << ap->port_no))
ap->cbl = ATA_CBL_PATA40;
else
ap->cbl = ATA_CBL_PATA80;
/* Reset the state machine */
- pci_write_config_byte(pdev, 0x50, 0x37);
- pci_write_config_byte(pdev, 0x54, 0x37);
+ pci_write_config_byte(pdev, 0x50, 0x37);
+ pci_write_config_byte(pdev, 0x54, 0x37);
udelay(100);
-
+
return ata_std_prereset(ap);
}
* channels. The function 0 channels work like usual but function 1
* is special
*/
-
+
static void hpt374_error_handler(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (!(PCI_FUNC(pdev->devfn) & 1))
hpt37x_error_handler(ap);
else
* @ap: ATA interface
* @adev: device on the interface
*
- * Perform PIO mode setup.
+ * Perform PIO mode setup.
*/
-
+
static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x02;
fast |= 0x01;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt37x_find_mode(ap, adev->pio_mode);
mode &= ~0x8000000; /* No FIFO in PIO */
* Set up the channel for MWDMA or UDMA modes. Much the same as with
* PIO, load the mode number and then set MWDMA or UDMA flag.
*/
-
+
static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x02;
fast |= 0x01;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt37x_find_mode(ap, adev->dma_mode);
mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
* The 370 and 370A want us to reset the DMA engine each time we
* use it. The 372 and later are fine.
*/
-
+
static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
*
* Work around the HPT370 DMA engine.
*/
-
+
static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2);
u8 dma_cmd;
unsigned long bmdma = ap->ioaddr.bmdma_addr;
-
+
if (dma_stat & 0x01) {
udelay(20);
dma_stat = inb(bmdma + 2);
* @ap: ATA interface
* @adev: device on the interface
*
- * Perform PIO mode setup.
+ * Perform PIO mode setup.
*/
-
+
static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x07;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt37x_find_mode(ap, adev->pio_mode);
-
+
printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
mode &= ~0x80000000; /* No FIFO in PIO */
mode &= ~0x30070000; /* Leave config bits alone */
* Set up the channel for MWDMA or UDMA modes. Much the same as with
* PIO, load the mode number and then set MWDMA or UDMA flag.
*/
-
+
static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x07;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt37x_find_mode(ap, adev->dma_mode);
printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
*
* Clean up after the HPT372 and later DMA engine
*/
-
+
static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int mscreg = 0x50 + 2 * ap->port_no;
u8 bwsr_stat, msc_stat;
-
+
pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
pci_read_config_byte(pdev, mscreg, &msc_stat);
if (bwsr_stat & (1 << ap->port_no))
/*
* Configuration for HPT370
*/
-
+
static struct ata_port_operations hpt370_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt370_set_piomode,
.set_dmamode = hpt370_set_dmamode,
.mode_filter = hpt370_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/*
* Configuration for HPT370A. Close to 370 but less filters
*/
-
+
static struct ata_port_operations hpt370a_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt370_set_piomode,
.set_dmamode = hpt370_set_dmamode,
.mode_filter = hpt370a_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/*
* Configuration for HPT372, HPT371, HPT302. Slightly different PIO
* and DMA mode setting functionality.
*/
-
+
static struct ata_port_operations hpt372_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt372_set_piomode,
.set_dmamode = hpt372_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/*
* Configuration for HPT374. Mode setting works like 372 and friends
* but we have a different cable detection procedure.
*/
-
+
static struct ata_port_operations hpt374_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt372_set_piomode,
.set_dmamode = hpt372_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* htp37x_clock_slot - Turn timing to PC clock entry
* Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
* and 3 for 66Mhz)
*/
-
+
static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
{
unsigned int f = (base * freq) / 192; /* Mhz */
/**
* hpt37x_calibrate_dpll - Calibrate the DPLL loop
- * @dev: PCI device
+ * @dev: PCI device
*
* Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
* succeeds
u8 reg5b;
u32 reg5c;
int tries;
-
+
for(tries = 0; tries < 0x5000; tries++) {
udelay(50);
pci_read_config_byte(dev, 0x5b, ®5b);
*
* (1) UDMA133 support depends on the bus clock
*/
-
+
static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
/* HPT370 - UDMA100 */
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xFF;
-
+
if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
/* May be a later chip in disguise. Check */
/* Older chips are in the HPT366 driver. Ignore them */
if (class_rev == 6)
return -ENODEV;
- switch(class_rev) {
+ switch(class_rev) {
case 3:
port = &info_hpt370;
chip_table = &hpt370;
* state on reset when PDIAG is a input.
*/
- pci_write_config_byte(dev, 0x5b, 0x23);
-
+ pci_write_config_byte(dev, 0x5b, 0x23);
+
pci_read_config_dword(dev, 0x70, &freq);
if ((freq >> 12) != 0xABCDE) {
int i;
u8 sr;
u32 total = 0;
-
+
printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
-
+
/* This is the process the HPT371 BIOS is reported to use */
for(i = 0; i < 128; i++) {
pci_read_config_byte(dev, 0x78, &sr);
freq = total / 128;
}
freq &= 0x1FF;
-
+
/*
* Turn the frequency check into a band and then find a timing
* table to match it.
*/
-
+
clock_slot = hpt37x_clock_slot(freq, chip_table->base);
if (chip_table->clocks[clock_slot] == NULL) {
/*
unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192;
unsigned int f_high = f_low + 2;
int adjust;
-
+
for(adjust = 0; adjust < 8; adjust++) {
if (hpt37x_calibrate_dpll(dev))
break;
}
/* Check if this works for all cases */
port->private_data = (void *)hpt370_timings_66;
-
+
printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
} else {
port->private_data = (void *)chip_table->clocks[clock_slot];
* Perform a final fixup. The 371 and 372 clock determines
* if UDMA133 is available.
*/
-
+
if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
if (port == &info_hpt372)
}
printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
}
- port_info[0] = port_info[1] = port;
+ port_info[0] = port_info[1] = port;
/* Now kick off ATA set up */
return ata_pci_init_one(dev, port_info, 2);
}
* PIO.
* 31 FIFO enable.
*/
-
+
/* 66MHz DPLL clocks */
static struct hpt_clock hpt3x2n_clocks[] = {
* is hard coded but easy to change. This will be needed if we use
* different DPLLs
*/
-
+
static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
{
struct hpt_clock *clocks = hpt3x2n_clocks;
-
+
while(clocks->xfer_speed) {
if (clocks->xfer_speed == speed)
return clocks->timing;
* Perform the initial reset handling for the 3x2n series controllers.
* Reset the hardware and state machine, obtain the cable type.
*/
-
+
static int hpt3xn_pre_reset(struct ata_port *ap)
{
u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
pci_read_config_byte(pdev, 0x5B, &scr2);
pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
/* Cable register now active */
pci_read_config_byte(pdev, 0x5A, &ata66);
/* Restore state */
pci_write_config_byte(pdev, 0x5B, scr2);
-
+
if (ata66 & (1 << ap->port_no))
ap->cbl = ATA_CBL_PATA40;
else
ap->cbl = ATA_CBL_PATA80;
/* Reset the state machine */
- pci_write_config_byte(pdev, 0x50, 0x37);
- pci_write_config_byte(pdev, 0x54, 0x37);
+ pci_write_config_byte(pdev, 0x50, 0x37);
+ pci_write_config_byte(pdev, 0x54, 0x37);
udelay(100);
return ata_std_prereset(ap);
}
-
+
/**
* hpt3x2n_error_handler - probe the hpt3x2n bus
* @ap: ATA port to reset
*
* Perform the probe reset handling for the 3x2N
*/
-
+
static void hpt3x2n_error_handler(struct ata_port *ap)
{
ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}
-
+
/**
* hpt3x2n_set_piomode - PIO setup
* @ap: ATA interface
* @adev: device on the interface
*
- * Perform PIO mode setup.
+ * Perform PIO mode setup.
*/
-
+
static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x07;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt3x2n_find_mode(ap, adev->pio_mode);
mode &= ~0x8000000; /* No FIFO in PIO */
* Set up the channel for MWDMA or UDMA modes. Much the same as with
* PIO, load the mode number and then set MWDMA or UDMA flag.
*/
-
+
static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
addr2 = 0x51 + 4 * ap->port_no;
-
+
/* Fast interrupt prediction disable, hold off interrupt disable */
pci_read_config_byte(pdev, addr2, &fast);
fast &= ~0x07;
pci_write_config_byte(pdev, addr2, fast);
-
+
pci_read_config_dword(pdev, addr1, ®);
mode = hpt3x2n_find_mode(ap, adev->dma_mode);
mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
*
* Clean up after the HPT3x2n and later DMA engine
*/
-
+
static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int mscreg = 0x50 + 2 * ap->port_no;
u8 bwsr_stat, msc_stat;
-
+
pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
pci_read_config_byte(pdev, mscreg, &msc_stat);
if (bwsr_stat & (1 << ap->port_no))
* - writing
* - second channel UDMA7 (SATA ports) or higher
* - 66MHz PCI
- *
+ *
* or we will underclock the device and get reduced performance.
*/
-
+
static void hpt3x2n_set_clock(struct ata_port *ap, int source)
{
unsigned long bmdma = ap->ioaddr.bmdma_addr;
-
+
/* Tristate the bus */
outb(0x80, bmdma+0x73);
outb(0x80, bmdma+0x77);
-
+
/* Switch clock and reset channels */
outb(source, bmdma+0x7B);
outb(0xC0, bmdma+0x79);
-
+
/* Reset state machines */
outb(0x37, bmdma+0x70);
outb(0x37, bmdma+0x74);
-
+
/* Complete reset */
outb(0x00, bmdma+0x79);
-
+
/* Reconnect channels to bus */
outb(0x00, bmdma+0x73);
outb(0x00, bmdma+0x77);
{
struct ata_host *host = ap->host;
struct ata_port *pair = host->ports[ap->port_no ^ 1];
-
+
if (pair->hsm_task_state == HSM_ST_IDLE)
return 1;
return 0;
return USE_DPLL; /* Needed for write */
if (flags & PCI66)
return USE_DPLL; /* Needed at 66Mhz */
- return 0;
+ return 0;
}
static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
struct ata_taskfile *tf = &qc->tf;
struct ata_port *ap = qc->ap;
int flags = (long)ap->host->private_data;
-
+
if (hpt3x2n_pair_idle(ap)) {
int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
if ((flags & USE_DPLL) != dpll) {
/*
* Configuration for HPT3x2n.
*/
-
+
static struct ata_port_operations hpt3x2n_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = hpt3x2n_set_piomode,
.set_dmamode = hpt3x2n_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* hpt3xn_calibrate_dpll - Calibrate the DPLL loop
- * @dev: PCI device
+ * @dev: PCI device
*
* Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
* succeeds
u8 reg5b;
u32 reg5c;
int tries;
-
+
for(tries = 0; tries < 0x5000; tries++) {
udelay(50);
pci_read_config_byte(dev, 0x5b, ®5b);
{
unsigned long freq;
u32 fcnt;
-
+
pci_read_config_dword(pdev, 0x70/*CHECKME*/, &fcnt);
if ((fcnt >> 12) != 0xABCDE) {
printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
return 33; /* Not BIOS set */
}
fcnt &= 0x1FF;
-
+
freq = (fcnt * 77) / 192;
-
+
/* Clamp to bands */
if (freq < 40)
return 33;
*
* To pin down HPT371N
*/
-
+
static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
/* HPT372N and friends - UDMA133 */
u8 irqmask;
u32 class_rev;
-
+
unsigned int pci_mhz;
unsigned int f_low, f_high;
int adjust;
-
+
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xFF;
-
+
switch(dev->device) {
case PCI_DEVICE_ID_TTI_HPT366:
if (class_rev < 6)
/* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
50 for UDMA100. Right now we always use 66 */
-
+
pci_mhz = hpt3x2n_pci_clock(dev);
-
+
f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
f_high = f_low + 2; /* Tolerance */
-
+
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
/* PLL clock */
pci_write_config_byte(dev, 0x5B, 0x21);
-
+
/* Unlike the 37x we don't try jiggling the frequency */
for(adjust = 0; adjust < 8; adjust++) {
if (hpt3xn_calibrate_dpll(dev))
port->private_data = NULL;
if (pci_mhz > 60)
port->private_data = (void *)PCI66;
-
+
/* Now kick off ATA set up */
port_info[0] = port_info[1] = port;
return ata_pci_init_one(dev, port_info, 2);
* May be copied or modified under the terms of the GNU General Public
* License
*/
-
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
};
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (ap->port_no && !pci_test_config_bits(pdev, &it8172_enable_bits[ap->port_no])) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
* based upon
*
* it821x.c
- *
+ *
* linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
*
* Copyright (C) 2004 Red Hat <alan@redhat.com>
*
* Set the cable type
*/
-
+
static int it821x_pre_reset(struct ata_port *ap)
{
ap->cbl = ATA_CBL_PATA80;
*
* Set the cable type and trigger a probe
*/
-
+
static void it821x_error_handler(struct ata_port *ap)
{
return ata_bmdma_drive_eh(ap, it821x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
struct it821x_dev *itdev = ap->private_data;
int unit = adev->devno;
int mode_wanted = adev->pio_mode - XFER_PIO_0;
-
+
/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
itdev->want[unit][1] = pio_want[mode_wanted];
itdev->want[unit][0] = 1; /* PIO is lowest priority */
* @adev: ATA device
*
* Set up the DMA modes. The actions taken depend heavily on the mode
- * to use. If UDMA is used as is hopefully the usual case then the
+ * to use. If UDMA is used as is hopefully the usual case then the
* timing register is private and we need only consider the clock. If
* we are using MWDMA then we have to manage the setting ourself as
* we switch devices and mode.
if (adev->dma_mode >= XFER_UDMA_0) {
int mode_wanted = adev->dma_mode - XFER_UDMA_0;
-
+
itdev->want[unit][1] = udma_want[mode_wanted];
itdev->want[unit][0] = 3; /* UDMA is high priority */
itdev->mwdma[unit] = MWDMA_OFF;
it821x_program_udma(ap, adev, itdev->udma[unit]);
} else {
int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
-
+
itdev->want[unit][1] = mwdma_want[mode_wanted];
itdev->want[unit][0] = 2; /* MWDMA is low priority */
itdev->mwdma[unit] = dma[mode_wanted];
* @qc: Command in progress
*
* Usually drivers set the DMA timing at the point the set_dmamode call
- * is made. IT821x however requires we load new timings on the
+ * is made. IT821x however requires we load new timings on the
* transitions in some cases.
*/
*
* Device selection hook. If neccessary perform clock switching
*/
-
+
static void it821x_passthru_dev_select(struct ata_port *ap,
unsigned int device)
{
* perform out own device selection timing loads before the
* usual happenings kick off
*/
-
+
static unsigned int it821x_smart_qc_issue_prot(struct ata_queued_cmd *qc)
{
switch(qc->tf.command)
* perform out own device selection timing loads before the
* usual happenings kick off
*/
-
+
static unsigned int it821x_passthru_qc_issue_prot(struct ata_queued_cmd *qc)
{
it821x_passthru_dev_select(qc->ap, qc->dev->devno);
* Use a non standard set_mode function. We don't want to be tuned.
* The BIOS configured everything. Our job is not to fiddle. We
* read the dma enabled bits from the PCI configuration of the device
- * and respect them.
+ * and respect them.
*/
-
+
static void it821x_smart_set_mode(struct ata_port *ap)
{
int dma_enabled = 0;
/* It is possible that BMDMA isn't allocated */
if (ap->ioaddr.bmdma_addr)
dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
-
+
for (i = 0; i < ATA_MAX_DEVICES; i++) {
struct ata_device *dev = &ap->device[i];
if (ata_dev_enabled(dev)) {
/* We don't really care */
dev->pio_mode = XFER_PIO_0;
dev->dma_mode = XFER_MW_DMA_0;
- /* We do need the right mode information for DMA or PIO
+ /* We do need the right mode information for DMA or PIO
and this comes from the current configuration flags */
if (dma_enabled & (1 << (5 + i))) {
dev->xfer_mode = XFER_MW_DMA_0;
* FIXME: When FUA appears we need to block FUA too. And SMART and
* basically we need to filter commands for this chip.
*/
-
+
static void it821x_dev_config(struct ata_port *ap, struct ata_device *adev)
{
unsigned char model_num[40];
/* This block ought to be a library routine as it is in several
drivers now */
-
+
ata_id_string(adev->id, model_num, ATA_ID_PROD_OFS,
sizeof(model_num));
s = &model_num[0];
if (adev->max_sectors > 255)
adev->max_sectors = 255;
-
+
if (strstr(model_num, "Integrated Technology Express")) {
/* RAID mode */
printk(KERN_INFO "IT821x %sRAID%d volume",
* Decide if this ATAPI command can be issued by DMA on this
* controller. Return 0 if it can be.
*/
-
+
static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct it821x_dev *itdev = ap->private_data;
-
+
/* No ATAPI DMA in smart mode */
if (itdev->smart)
return -EOPNOTSUPP;
/* Cool */
return 0;
}
-
+
/**
* it821x_port_start - port setup
*
* The it821x needs to maintain private data structures and also to
* use the standard PCI interface which lacks support for this
- * functionality. We instead set up the private data on the port
+ * functionality. We instead set up the private data on the port
* start hook, and tear it down on port stop
*/
-
+
static int it821x_port_start(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int ret = ata_port_start(ap);
if (ret < 0)
return ret;
-
+
ap->private_data = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
if (ap->private_data == NULL) {
ata_port_stop(ap);
return -ENOMEM;
}
-
+
itdev = ap->private_data;
memset(itdev, 0, sizeof(struct it821x_dev));
*
* Release the private objects we added in it821x_port_start
*/
-
+
static void it821x_port_stop(struct ata_port *ap) {
kfree(ap->private_data);
ap->private_data = NULL; /* We want an OOPS if we reuse this
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.mode_filter = ata_pci_default_filter,
-
+
.check_status = ata_check_status,
.check_atapi_dma= it821x_check_atapi_dma,
.exec_command = ata_exec_command,
.port_start = it821x_port_start,
.port_stop = it821x_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations it821x_passthru_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = it821x_passthru_set_piomode,
.set_dmamode = it821x_passthru_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = it821x_port_start,
.port_stop = it821x_port_stop,
.host_stop = ata_host_stop
-};
+};
static void __devinit it821x_disable_raid(struct pci_dev *pdev)
{
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
}
-
+
static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
u8 conf;
-
+
static struct ata_port_info info_smart = {
.sht = &it821x_sht,
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
.port_ops = &it821x_passthru_port_ops
};
static struct ata_port_info *port_info[2];
-
+
static char *mode[2] = { "pass through", "smart" };
/* Force the card into bypass mode if so requested */
}
pci_read_config_byte(pdev, 0x50, &conf);
conf &= 1;
-
+
printk(KERN_INFO DRV_NAME ": controller in %s mode.\n", mode[conf]);
if (conf == 0)
port_info[0] = port_info[1] = &info_passthru;
else
port_info[0] = port_info[1] = &info_smart;
-
+
return ata_pci_init_one(pdev, port_info, 2);
}
int pio = adev->pio_mode - XFER_PIO_0;
u8 rt;
unsigned long flags;
-
+
/* Safe as UP only. Force I/Os to occur together */
-
+
local_irq_save(flags);
-
+
/* Unlock the control interface */
do
{
while((inb(0x1F2) & 0x80) && --tries);
local_irq_restore(flags);
-
+
outb(inb(0x1F4) & 0x07, 0x1F4);
rt = inb(0x1F3);
/*
* Opti core chipset helpers
*/
-
+
/**
* opti_syscfg - read OPTI chipset configuration
* @reg: Configuration register to read
{
unsigned long flags;
u8 r;
-
+
/* Uniprocessor chipset and must force cycles adjancent */
local_irq_save(flags);
outb(reg, 0x22);
}
/* Probe for automatically detectable controllers */
-
+
if (io == 0x1F0 && ops == &legacy_port_ops) {
unsigned long flags;
last_port = 2;
}
- /* If an OPTI 82C46X is present find out where the channels are */
+ /* If an OPTI 82C46X is present find out where the channels are */
if (opti82c46x) {
static const char *optis[4] = {
"3/463MV", "5MV",
};
u8 chans = 1;
u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
-
+
opti82c46x = 3; /* Assume master and slave first */
printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
if (ctrl == 3)
*
* Cables are handled by the RAID controller. Report 80 pin.
*/
-
+
static int netcell_pre_reset(struct ata_port *ap)
{
ap->cbl = ATA_CBL_PATA80;
/* Any chip specific setup/optimisation/messages here */
ata_pci_clear_simplex(pdev);
-
+
/* And let the library code do the work */
return ata_pci_init_one(pdev, port_info, 2);
}
*
* Set up cable type and use generic probe init
*/
-
+
static int optidma_pre_reset(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
- static const struct pci_bits optidma_enable_bits = {
+ static const struct pci_bits optidma_enable_bits = {
0x40, 1, 0x08, 0x00
};
* Unlock the control register block for this adapter. Registers must not
* be unlocked in a situation where libata might look at them.
*/
-
+
static void optidma_unlock(struct ata_port *ap)
{
unsigned long regio = ap->ioaddr.cmd_addr;
-
+
/* These 3 unlock the control register access */
inw(regio + 1);
inw(regio + 1);
*
* Re-lock the configuration register settings.
*/
-
+
static void optidma_lock(struct ata_port *ap)
{
unsigned long regio = ap->ioaddr.cmd_addr;
-
+
/* Relock */
outb(0x83, regio + 2);
}
/* Switch from IDE to control mode */
optidma_unlock(ap);
-
+
/*
* As with many controllers the address setup time is shared
addr = 0;
else
addr = addr_timing[pci_clock][pio];
-
+
if (pair) {
u8 pair_addr;
/* Hardware constraint */
if (pair_addr > addr)
addr = pair_addr;
}
-
+
/* Commence primary programming sequence */
/* First we load the device number into the timing select */
outb(adev->devno, regio + MISC_REG);
/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
outb(0x85, regio + CNTRL_REG);
-
+
/* Switch back to IDE mode */
optidma_lock(ap);
-
+
/* Note: at this point our programming is incomplete. We are
not supposed to program PCI 0x43 "things we hacked onto the chip"
until we've done both sets of PIO/DMA timings */
int dev2 = 2 * adev->devno;
int unit = 2 * ap->port_no + adev->devno;
int udma = mode - XFER_UDMA_0;
-
+
pci_read_config_byte(pdev, 0x44, &udcfg);
if (mode <= XFER_UDMA_0) {
udcfg &= ~(1 << unit);
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
optidma_set_mode(ap, adev, adev->pio_mode);
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
optidma_set_mode(ap, adev, adev->dma_mode);
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
optiplus_set_mode(ap, adev, adev->pio_mode);
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
optiplus_set_mode(ap, adev, adev->dma_mode);
* Turn the ATA device setup into PCI configuration bits
* for register 0x43 and return the two bits needed.
*/
-
+
static u8 optidma_make_bits43(struct ata_device *adev)
{
static const u8 bits43[5] = {
* Finalise the configuration by writing the nibble of extra bits
* of data into the chip.
*/
-
+
static void optidma_post_set_mode(struct ata_port *ap)
{
u8 r;
int nybble = 4 * ap->port_no;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
pci_read_config_byte(pdev, 0x43, &r);
-
+
r &= (0x0F << nybble);
- r |= (optidma_make_bits43(&ap->device[0]) +
+ r |= (optidma_make_bits43(&ap->device[0]) +
(optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
pci_write_config_byte(pdev, 0x43, r);
* optiplus_with_udma - Look for UDMA capable setup
* @pdev; ATA controller
*/
-
+
static int optiplus_with_udma(struct pci_dev *pdev)
{
u8 r;
int ret = 0;
int ioport = 0x22;
struct pci_dev *dev1;
-
+
/* Find function 1 */
dev1 = pci_get_device(0x1045, 0xC701, NULL);
if(dev1 == NULL)
return 0;
-
+
/* Rev must be >= 0x10 */
pci_read_config_byte(dev1, 0x08, &r);
if (r < 0x10)
pci_read_config_byte(dev1, 0x52, &r);
if (r & 0x80) /* IDEDIR disabled */
ret = 1;
-done:
+done:
printk(KERN_WARNING "UDMA not supported in this configuration.\n");
done_nomsg: /* Wrong chip revision */
pci_dev_put(dev1);
inw(0x1F1);
inw(0x1F1);
pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
-
+
if (optiplus_with_udma(dev))
info = &info_82c700_udma;
/*
* pata_pcmcia.c - PCMCIA PATA controller driver.
* Copyright 2005-2006 Red Hat Inc <alan@redhat.com>, all rights reserved.
- * PCMCIA ident update Copyright 2006 Marcin Juszkiewicz
+ * PCMCIA ident update Copyright 2006 Marcin Juszkiewicz
* <openembedded@hrw.one.pl>
*
* This program is free software; you can redistribute it and/or modify
* TODO:
* Channel interlock/reset on both required ?
*/
-
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
*
* Set up cable type and use generic probe init
*/
-
+
static int pdc2024x_pre_reset(struct ata_port *ap)
{
ap->cbl = ATA_CBL_PATA40;
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u16 cis;
-
+
pci_read_config_word(pdev, 0x50, &cis);
if (cis & (1 << (10 + ap->port_no)))
ap->cbl = ATA_CBL_PATA80;
* so a configure_dmamode call will undo any work we do here and vice
* versa
*/
-
+
static void pdc_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
r_bp &= ~0x07;
r_ap |= (pio_timing[pio] >> 8);
r_bp |= (pio_timing[pio] & 0xFF);
-
+
if (ata_pio_need_iordy(adev))
r_ap |= 0x20; /* IORDY enable */
if (adev->class == ATA_DEV_ATA)
* Called to do the PIO mode setup. Our timing registers are shared
* but we want to set the PIO timing by default.
*/
-
+
static void pdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
pdc_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
* Load DMA cycle times into the chip ready for a DMA transfer
* to occur.
*/
-
+
static void pdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
{ 0x20, 0x01 },
{ 0x40, 0x02 }, /* 66 Mhz Clock */
{ 0x20, 0x01 },
- { 0x20, 0x01 }
+ { 0x20, 0x01 }
};
u8 r_bp, r_cp;
-
+
pci_read_config_byte(pdev, port + 1, &r_bp);
pci_read_config_byte(pdev, port + 2, &r_cp);
-
+
r_bp &= ~0xF0;
r_cp &= ~0x0F;
-
+
if (adev->dma_mode >= XFER_UDMA_0) {
int speed = adev->dma_mode - XFER_UDMA_0;
r_bp |= udma_timing[speed][0];
r_cp |= udma_timing[speed][1];
-
+
} else {
int speed = adev->dma_mode - XFER_MW_DMA_0;
r_bp |= 0x60;
}
pci_write_config_byte(pdev, port + 1, r_bp);
pci_write_config_byte(pdev, port + 2, r_cp);
-
+
}
/**
* In UDMA3 or higher we have to clock switch for the duration of the
* DMA transfer sequence.
*/
-
+
static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
unsigned long clock = master + 0x11;
unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
-
+
u32 len;
-
+
/* Check we keep host level locking here */
if (adev->dma_mode >= XFER_UDMA_2)
outb(inb(clock) | sel66, clock);
else
outb(inb(clock) & ~sel66, clock);
- /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
+ /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
and move to qc_issue ? */
pdc_set_dmamode(ap, qc->dev);
len = qc->nsect * 512;
else
len = qc->nbytes;
-
+
if (tf->flags & ATA_TFLAG_WRITE)
len |= 0x06000000;
else
len |= 0x05000000;
-
+
outl(len, atapi_reg);
}
-
- /* Activate DMA */
+
+ /* Activate DMA */
ata_bmdma_start(qc);
}
* After a DMA completes we need to put the clock back to 33MHz for
* PIO timings.
*/
-
+
static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct ata_device *adev = qc->dev;
struct ata_taskfile *tf = &qc->tf;
-
+
int sel66 = ap->port_no ? 0x08: 0x02;
/* The clock bits are in the same register for both channels */
unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
unsigned long clock = master + 0x11;
unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
-
+
/* Cases the state machine will not complete correctly */
if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
outl(0, atapi_reg);
* sizes to 8bit to avoid making the state engine on the 2026x cards
* barf.
*/
-
+
static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
{
adev->max_sectors = 256;
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations pdc2026x_port_ops = {
.port_disable = ata_port_disable,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static int pdc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
.mwdma_mask = 0x07,
.udma_mask = ATA_UDMA2,
.port_ops = &pdc2024x_port_ops
- },
+ },
{
.sht = &pdc_sht,
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
.udma_mask = ATA_UDMA5,
.port_ops = &pdc2026x_port_ops
}
-
+
};
static struct ata_port_info *port_info[2];
port_info[0] = port_info[1] = &info[id->driver_data];
-
+
if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
struct pci_dev *bridge = dev->bus->self;
/* Don't grab anything behind a Promise I2O RAID */
u8 last;
int fast;
struct platform_device *platform_dev;
-
+
};
static struct ata_host *qdi_host[NR_HOST];
/* Get the timing data in cycles */
ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
-
+
if (qdi->fast) {
active = 8 - FIT(t.active, 1, 8);
recovery = 18 - FIT(t.recover, 3, 18);
recovery = 15 - FIT(t.recover, 0, 15);
}
timing = (recovery << 4) | active | 0x08;
-
+
qdi->clock[adev->devno] = timing;
- outb(timing, qdi->timing);
+ outb(timing, qdi->timing);
}
static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
/* Get the timing data in cycles */
ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
-
+
if (qdi->fast) {
active = 8 - FIT(t.active, 1, 8);
recovery = 18 - FIT(t.recover, 3, 18);
recovery = 15 - FIT(t.recover, 0, 15);
}
timing = (recovery << 4) | active | 0x08;
-
+
qdi->clock[adev->devno] = timing;
outb(timing, qdi->timing);
-
+
/* Clear the FIFO */
if (adev->class != ATA_DEV_ATA)
outb(0x5F, (qdi->timing & 0xFFF0) + 3);
{
struct ata_port *ap = adev->ap;
int slop = buflen & 3;
-
+
if (ata_id_has_dword_io(adev->id)) {
if (write_data)
outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
else
insl(ap->ioaddr.data_addr, buf, buflen >> 2);
-
+
if (unlikely(slop)) {
u32 pad;
if (write_data) {
.thaw = ata_bmdma_thaw,
.error_handler = ata_bmdma_error_handler,
.post_internal_cmd = ata_bmdma_post_internal_cmd,
-
+
.qc_prep = ata_qc_prep,
.qc_issue = qdi_qc_issue_prot,
.eng_timeout = ata_eng_timeout,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations qdi6580_port_ops = {
.port_disable = ata_port_disable,
.thaw = ata_bmdma_thaw,
.error_handler = ata_bmdma_error_handler,
.post_internal_cmd = ata_bmdma_post_internal_cmd,
-
+
.qc_prep = ata_qc_prep,
.qc_issue = qdi_qc_issue_prot,
.eng_timeout = ata_eng_timeout,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* qdi_init_one - attach a qdi interface
* Register an ISA bus IDE interface. Such interfaces are PIO and we
* assume do not support IRQ sharing.
*/
-
+
static __init int qdi_init_one(unsigned long port, int type, unsigned long io, int irq, int fast)
{
struct ata_probe_ent ae;
pdev = platform_device_register_simple(DRV_NAME, nr_qdi_host, NULL, 0);
if (pdev == NULL)
return -ENOMEM;
-
+
memset(&ae, 0, sizeof(struct ata_probe_ent));
INIT_LIST_HEAD(&ae.node);
ae.dev = &pdev->dev;
-
+
if (type == 6580) {
ae.port_ops = &qdi6580_port_ops;
ae.pio_mask = 0x1F;
ae.port_ops = &qdi6500_port_ops;
ae.pio_mask = 0x07; /* Actually PIO3 !IORDY is possible */
}
-
+
ae.sht = &qdi_sht;
ae.n_ports = 1;
ae.irq = irq;
platform_device_unregister(pdev);
return -ENODEV;
}
-
+
qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev);
- return 0;
+ return 0;
}
/**
*
* Attach qdi IDE interfaces by scanning the ports it may occupy.
*/
-
+
static __init int qdi_init(void)
{
unsigned long flags;
static const unsigned long qd_port[2] = { 0x30, 0xB0 };
static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
static const int ide_irq[2] = { 14, 15 };
-
+
int ct = 0;
int i;
-
+
if (probe_qdi == 0)
return -ENODEV;
-
+
/*
* Check each possible QD65xx base address
*/
-
+
for (i = 0; i < 2; i++) {
unsigned long port = qd_port[i];
u8 r, res;
-
-
+
+
if (request_region(port, 2, "pata_qdi")) {
/* Check for a card */
local_irq_save(flags);
res = inb_p(port);
outb_p(r, port);
local_irq_restore(flags);
-
+
/* Fail */
if (res == 0x19)
{
release_region(port, 2);
continue;
}
-
+
/* Passes the presence test */
r = inb_p(port + 1); /* Check port agrees with port set */
if ((r & 2) >> 1 != i) {
continue;
}
- /* Check card type */
+ /* Check card type */
if ((r & 0xF0) == 0xC0) {
/* QD6500: single channel */
if (r & 8) {
*/
release_region(qdi_data[i].timing, 2);
platform_device_unregister(qdi_data[i].platform_dev);
- }
+ }
}
MODULE_AUTHOR("Alan Cox");
*
* Set up cable type and use generic probe init
*/
-
+
static int radisys_pre_reset(struct ata_port *ap)
{
ap->cbl = ATA_CBL_PATA80;
struct pci_dev *dev = to_pci_dev(ap->host->dev);
u16 idetm_data;
u8 udma_enable;
-
+
static const /* ISP RTC */
u8 timings[][2] = { { 0, 0 },
{ 0, 0 },
/* Mask out the relevant control and timing bits we will load. Also
clear the other drive TIME register as a precaution */
-
+
idetm_data &= 0xCCCC;
idetm_data |= control << (4 * adev->devno);
idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
udma_enable &= ~(1 << adev->devno);
} else {
u8 udma_mode;
-
+
/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */
-
+
pci_read_config_byte(dev, 0x4A, &udma_mode);
-
+
if (adev->xfer_mode == XFER_UDMA_2)
udma_mode &= ~ (1 << adev->devno);
else /* UDMA 4 */
udma_mode |= (1 << adev->devno);
-
+
pci_write_config_byte(dev, 0x4A, udma_mode);
-
+
udma_enable |= (1 << adev->devno);
}
pci_write_config_word(dev, 0x40, idetm_data);
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
+ *
*/
#include <linux/kernel.h>
* Return the PCI bus clocking for the SC1200 chipset configuration
* in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
*/
-
+
static int sc1200_clock(void)
{
/* Magic registers that give us the chipset data */
u8 chip_id = inb(0x903C);
u8 silicon_rev = inb(0x903D);
u16 pci_clock;
-
+
if (chip_id == 0x04 && silicon_rev < SC1200_REV_B1)
return 0; /* 33 MHz mode */
*
* Set our PIO requirements. This is fairly simple on the SC1200
*/
-
+
static void sc1200_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
static const u32 pio_timings[4][5] = {
u32 format;
unsigned int reg = 0x40 + 0x10 * ap->port_no;
int mode = adev->pio_mode - XFER_PIO_0;
-
+
pci_read_config_dword(pdev, reg + 4, &format);
format >>= 31;
format += sc1200_clock();
- pci_write_config_dword(pdev, reg + 8 * adev->devno,
+ pci_write_config_dword(pdev, reg + 8 * adev->devno,
pio_timings[format][mode]);
}
* We cannot mix MWDMA and UDMA without reloading timings each switch
* master to slave.
*/
-
+
static void sc1200_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
static const u32 udma_timing[3][3] = {
{ 0x00932470, 0x00922260, 0x00922140 },
{ 0x009436A1, 0x00933481, 0x00923261 }
};
-
+
static const u32 mwdma_timing[3][3] = {
{ 0x00077771, 0x00012121, 0x00002020 },
{ 0x000BBBB2, 0x00024241, 0x00013131 },
{ 0x000FFFF3, 0x00035352, 0x00015151 }
};
-
+
int clock = sc1200_clock();
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
unsigned int reg = 0x40 + 0x10 * ap->port_no;
format = udma_timing[clock][mode - XFER_UDMA_0];
else
format = mwdma_timing[clock][mode - XFER_MW_DMA_0];
-
+
if (adev->devno == 0) {
u32 timings;
-
+
pci_read_config_dword(pdev, reg + 4, &timings);
timings &= 0x80000000UL;
timings |= format;
.set_piomode = sc1200_set_piomode,
.set_dmamode = sc1200_set_dmamode,
.mode_filter = ata_pci_default_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* sc1200_init_one - Initialise an SC1200
* Just throw the needed data at the libata helper and it does all
* our work.
*/
-
+
static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
static struct ata_port_info info = {
.port_ops = &sc1200_port_ops
};
static struct ata_port_info *port_info[2] = { &info, &info };
-
+
/* Can't enable port 2 yet, see top comments */
return ata_pci_init_one(dev, port_info, 1);
}
* based upon
*
* serverworks.c
- *
+ *
* Copyright (C) 1998-2000 Michel Aubry
* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
* @ap: ATA port to do cable detect
*
* Dell hide the 40/80 pin select for their interfaces in the top two
- * bits of the subsystem ID.
+ * bits of the subsystem ID.
*/
-
+
static int dell_cable(struct ata_port *ap) {
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
return ATA_CBL_PATA80;
return ATA_CBL_PATA40;
* subsystem ID the same as dell. We could use one function but we may
* need to extend the Dell one in future
*/
-
+
static int sun_cable(struct ata_port *ap) {
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
return ATA_CBL_PATA80;
return ATA_CBL_PATA40;
* Note that we don't copy the old serverworks code because the old
* code contains obvious mistakes
*/
-
+
static struct sv_cable_table cable_detect[] = {
{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
* serverworks_pre_reset - cable detection
* @ap: ATA port
*
- * Perform cable detection according to the device and subvendor
+ * Perform cable detection according to the device and subvendor
* identifications
*/
-
+
static int serverworks_pre_reset(struct ata_port *ap) {
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
struct sv_cable_table *cb = cable_detect;
while(cb->device) {
- if (cb->device == pdev->device &&
+ if (cb->device == pdev->device &&
(cb->subvendor == pdev->subsystem_vendor ||
cb->subvendor == PCI_ANY_ID)) {
ap->cbl = cb->cable_detect(ap);
* Returns true if the device being checked is known to be a CSB
* series device.
*/
-
+
static u8 serverworks_is_csb(struct pci_dev *pdev)
{
switch (pdev->device) {
* specific rules. OSB4 requires no UDMA for disks due to a FIFO
* bug we hit.
*/
-
+
static unsigned long serverworks_osb4_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
{
if (adev->class == ATA_DEV_ATA)
char model_num[40];
int len, i;
- /* Disk, UDMA */
+ /* Disk, UDMA */
if (adev->class != ATA_DEV_ATA)
return ata_pci_default_filter(ap, adev, mask);
/* Actually do need to check */
ata_id_string(adev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
/* Precuationary - why not do this in the libata core ?? */
-
+
len = strlen(model_num);
while ((len > 0) && (model_num[len - 1] == ' ')) {
len--;
int pio = adev->pio_mode - XFER_PIO_0;
pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
-
+
/* The OSB4 just requires the timing but the CSB series want the
mode number as well */
if (serverworks_is_csb(pdev)) {
ultra_cfg |= (1 << devbits);
} else {
- pci_write_config_byte(pdev, 0x44 + offset,
+ pci_write_config_byte(pdev, 0x44 + offset,
dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
ultra_cfg &= ~(1 << devbits);
}
.set_piomode = serverworks_set_piomode,
.set_dmamode = serverworks_set_dmamode,
.mode_filter = serverworks_osb4_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.qc_issue = ata_qc_issue_prot,
.eng_timeout = ata_eng_timeout,
.data_xfer = ata_pio_data_xfer,
-
+
.irq_handler = ata_interrupt,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static struct ata_port_operations serverworks_csb_port_ops = {
.port_disable = ata_port_disable,
.set_piomode = serverworks_set_piomode,
.set_dmamode = serverworks_set_dmamode,
.mode_filter = serverworks_csb_filter,
-
+
.tf_load = ata_tf_load,
.tf_read = ata_tf_read,
.check_status = ata_check_status,
.qc_issue = ata_qc_issue_prot,
.eng_timeout = ata_eng_timeout,
.data_xfer = ata_pio_data_xfer,
-
+
.irq_handler = ata_interrupt,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
static int serverworks_fixup_osb4(struct pci_dev *pdev)
{
{
u8 rev;
u8 btr;
-
+
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
/* Third Channel Test */
else
btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
pci_write_config_byte(pdev, 0x5A, btr);
-
+
return btr;
}
};
static struct ata_port_info *port_info[2];
struct ata_port_info *devinfo = &info[id->driver_data];
-
+
/* Force master latency timer to 64 PCI clocks */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
-
+
/* If the returned btr is the newer revision then
select the right info block */
if (serverworks_fixup_csb(pdev) == 3)
devinfo = &info[3];
-
+
/* Is this the 3rd channel CSB6 IDE ? */
if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
ports = 1;
/* setup HT1000E */
else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
serverworks_fixup_ht1000(pdev);
-
+
if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
ata_pci_clear_simplex(pdev);
-
+
port_info[0] = port_info[1] = devinfo;
return ata_pci_init_one(pdev, port_info, ports);
}
{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
{ 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
};
-
+
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u16 tmp;
{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
{ 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
};
-
+
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
.thaw = ata_bmdma_thaw,
.error_handler = sis_66_error_handler,
.post_internal_cmd = ata_bmdma_post_internal_cmd,
-
+
.bmdma_setup = ata_bmdma_setup,
.bmdma_start = ata_bmdma_start,
.bmdma_stop = ata_bmdma_stop,
.thaw = ata_bmdma_thaw,
.error_handler = sis_66_error_handler,
.post_internal_cmd = ata_bmdma_post_internal_cmd,
-
+
.bmdma_setup = ata_bmdma_setup,
.bmdma_start = ata_bmdma_start,
*
* and in part on the documentation and errata sheet
*/
-
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
*
* Set up cable type and use generic probe init
*/
-
+
static int sl82c105_pre_reset(struct ata_port *ap)
{
static const struct pci_bits sl82c105_enable_bits[] = {
* so a configure_dmamode call will undo any work we do here and vice
* versa
*/
-
+
static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
};
u16 dummy;
int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
-
+
pci_write_config_word(pdev, timing, pio_timing[pio]);
/* Can we lose this oddity of the old driver */
pci_read_config_word(pdev, timing, &dummy);
* Called to do the PIO mode setup. Our timing registers are shared
* but we want to set the PIO timing by default.
*/
-
+
static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
* Load DMA cycle times into the chip ready for a DMA transfer
* to occur.
*/
-
+
static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u16 dummy;
int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
int dma = adev->dma_mode - XFER_MW_DMA_0;
-
+
pci_write_config_word(pdev, timing, dma_timing[dma]);
/* Can we lose this oddity of the old driver */
pci_read_config_word(pdev, timing, &dummy);
* for the device in question. Set appropriate PIO timings not DMA
* timings at this point.
*/
-
+
static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
switch(adev->dma_mode) {
break;
default:
BUG();
- }
+ }
}
/**
* @ap: ATA interface
*
* The sl82c105 has some serious problems with the DMA engine
- * when transfers don't run as expected or ATAPI is used. The
+ * when transfers don't run as expected or ATAPI is used. The
* recommended fix is to reset the engine each use using a chip
* test register.
*/
-
+
static void sl82c105_reset_engine(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u16 val;
-
+
pci_read_config_word(pdev, 0x7E, &val);
pci_write_config_word(pdev, 0x7E, val | 4);
pci_write_config_word(pdev, 0x7E, val & ~4);
* @qc: ATA command
*
* Reset the DMA engine each use as recommended by the errata
- * document.
+ * document.
*
* FIXME: if we switch clock at BMDMA start/end we might get better
* PIO performance on DMA capable devices.
*/
-
+
static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
sl82c105_reset_engine(ap);
-
+
/* Set the clocks for DMA */
sl82c105_configure_dmamode(ap, qc->dev);
- /* Activate DMA */
+ /* Activate DMA */
ata_bmdma_start(qc);
}
* We assume bmdma_stop is always called if bmdma_start as called. If
* not then we may need to wrap qc_issue.
*/
-
+
static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
ata_bmdma_stop(qc);
sl82c105_reset_engine(ap);
-
+
/* This will redo the initial setup of the DMA device to matching
PIO timings */
sl82c105_set_dmamode(ap, qc->dev);
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
-
+
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.host_stop = ata_host_stop
-};
+};
/**
* sl82c105_bridge_revision - find bridge version
* providing it is a Winbond 553 reports the revision. If it cannot
* find a revision or the right device it returns -1
*/
-
+
static int sl82c105_bridge_revision(struct pci_dev *pdev)
{
struct pci_dev *bridge;
return rev;
}
-
+
static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
static struct ata_port_info info_dma = {
int rev;
rev = sl82c105_bridge_revision(dev);
-
+
if (rev == -1)
dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
else if (rev <= 5)
port_info[0] = &info_dma;
port_info[1] = &info_dma;
}
-
+
pci_read_config_dword(dev, 0x40, &val);
val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
pci_write_config_dword(dev, 0x40, val);
};
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
};
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
+
if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff