projects
/
GitHub
/
exynos8895
/
android_kernel_samsung_universal8895.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
878a3c3
)
agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
author
Chris Wilson
<chris@chris-wilson.co.uk>
Fri, 22 Oct 2010 13:59:29 +0000
(14:59 +0100)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Fri, 22 Oct 2010 14:04:09 +0000
(15:04 +0100)
In cleaning up the mask functions in
bdd3072
, the setting of the PTE
valid bit was dropped for Sandybridge.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/char/agp/intel-gtt.c
patch
|
blob
|
blame
|
history
diff --git
a/drivers/char/agp/intel-gtt.c
b/drivers/char/agp/intel-gtt.c
index 0c8ff6d8824bdbe3e37e9d7e337a23735b4227b8..6b6760ea2435bac1865325aec74d579f9687f87e 100644
(file)
--- a/
drivers/char/agp/intel-gtt.c
+++ b/
drivers/char/agp/intel-gtt.c
@@
-1211,13
+1211,13
@@
static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
u32 pte_flags;
if (type_mask == AGP_USER_UNCACHED_MEMORY)
- pte_flags = GEN6_PTE_UNCACHED;
+ pte_flags = GEN6_PTE_UNCACHED
| I810_PTE_VALID
;
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
- pte_flags = GEN6_PTE_LLC;
+ pte_flags = GEN6_PTE_LLC
| I810_PTE_VALID
;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
} else { /* set 'normal'/'cached' to LLC by default */
- pte_flags = GEN6_PTE_LLC_MLC;
+ pte_flags = GEN6_PTE_LLC_MLC
| I810_PTE_VALID
;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
}