ARM: dts: r8a7791: Add SYSC PM Domains

Add a device node for the System Controller.
Hook up the Cortex-A15 CPU cores and the Cortex-A15 L2 cache/SCU to
their respective PM Domains.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 6d4a0b6e4df9d7b822f8129149fb69101a50657a..e30200c9476a8c942b335ff0e69c536d9b36f3a8 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/clock/r8a7791-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7791-sysc.h>
 
 / {
        compatible = "renesas,r8a7791";
@@ -51,6 +52,7 @@
                        voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg_clocks R8A7791_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
+                       power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */
@@ -67,6 +69,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <1>;
                        clock-frequency = <1500000000>;
+                       power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
                };
        };
@@ -92,6 +95,7 @@
 
        L2_CA15: cache-controller@0 {
                compatible = "cache";
+               power-domains = <&sysc R8A7791_PD_CA15_SCU>;
                cache-unified;
                cache-level = <2>;
        };
@@ -1466,6 +1470,12 @@
                };
        };
 
+       sysc: system-controller@e6180000 {
+               compatible = "renesas,r8a7791-sysc";
+               reg = <0 0xe6180000 0 0x0200>;
+               #power-domain-cells = <1>;
+       };
+
        qspi: spi@e6b10000 {
                compatible = "renesas,qspi-r8a7791", "renesas,qspi";
                reg = <0 0xe6b10000 0 0x2c>;