ath9k_hw: Program correct PLL value for AR9565
authorSujith Manoharan <c_manoha@qualcomm.com>
Mon, 10 Sep 2012 03:50:29 +0000 (09:20 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 11 Sep 2012 19:31:41 +0000 (15:31 -0400)
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/hw.c

index 063d724bba126805cd996443b216d980204e7d47..47de1a92bfe47010f29b1dccca318a17640d70fb 100644 (file)
@@ -918,7 +918,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
        }
 
        pll = ath9k_hw_compute_pll_control(ah, chan);
-
+       if (AR_SREV_9565(ah))
+               pll |= 0x40000;
        REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
        if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||