x86/tsc: Remove the TSC_ADJUST clamp

Now that all affected platforms have a microcode update; and we check
this and disable TSC_DEADLINE and print a microcode revision update
error if its too old, we can remove the TSC_ADJUST clamp.

This should help with systems where the second socket runs ahead of
the first socket and needs a negative adjustment. In this case we'd
hit the 0 clamp and give up for not achieving synchronization.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: kevin.b.stanton@intel.com
Link: http://lkml.kernel.org/r/20170531155306.100950003@infradead.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 728f7537847583108075d91ad4aa75edfd86f077..7842371bc9e47179dba5c104fadddcb9d6b184c8 100644 (file)
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -71,13 +71,8 @@ static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
         * non zero. We don't do that on non boot cpus because physical
         * hotplug should have set the ADJUST register to a value > 0 so
         * the TSC is in sync with the already running cpus.
-        *
-        * But we always force positive ADJUST values. Otherwise the TSC
-        * deadline timer creates an interrupt storm. We also have to
-        * prevent values > 0x7FFFFFFF as those wreckage the timer as well.
         */
-       if ((bootcpu && bootval != 0) || (!bootcpu && bootval < 0) ||
-           (bootval > 0x7FFFFFFF)) {
+       if (bootcpu && bootval != 0) {
                pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,
                        bootval);
                wrmsrl(MSR_IA32_TSC_ADJUST, 0);
@@ -451,20 +446,6 @@ retry:
         */
        cur->adjusted += cur_max_warp;
 
-       /*
-        * TSC deadline timer stops working or creates an interrupt storm
-        * with adjust values < 0 and > x07ffffff.
-        *
-        * To allow adjust values > 0x7FFFFFFF we need to disable the
-        * deadline timer and use the local APIC timer, but that requires
-        * more intrusive changes and we do not have any useful information
-        * from Intel about the underlying HW wreckage yet.
-        */
-       if (cur->adjusted < 0)
-               cur->adjusted = 0;
-       if (cur->adjusted > 0x7FFFFFFF)
-               cur->adjusted = 0x7FFFFFFF;
-
        pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
                cpu, cur_max_warp, cur->adjusted);