mac_cb->max_frm = MAC_DEFAULT_MTU;
mac_cb->tx_pause_frm_time = MAC_DEFAULT_PAUSE_TIME;
+ mac_cb->port_rst_off = mac_cb->mac_id;
/* if the dsaf node doesn't contain a port subnode, get phy-handle
* from dsaf node
}
mac_cb->serdes_ctrl = syscon;
+ ret = fwnode_property_read_u32(mac_cb->fw_port,
+ "port-rst-offset",
+ &mac_cb->port_rst_off);
+ if (ret) {
+ dev_dbg(mac_cb->dev,
+ "mac%d port-rst-offset not found, use default value.\n",
+ mac_cb->mac_id);
+ }
+
syscon = syscon_node_to_regmap(
of_parse_phandle(to_of_node(mac_cb->fw_port),
"cpld-syscon", 0));
return;
reg_val |= RESET_REQ_OR_DREQ;
-
- if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
- reg_val |= 0x2082082 << port;
- else
- reg_val |= 0x2082082 << (dsaf_dev->reset_offset + 6);
+ reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
if (val == 0)
reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
if (port >= DSAF_XGE_NUM)
return;
- if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
- reg_val |= XGMAC_TRX_CORE_SRST_M << port;
- else
- reg_val |= XGMAC_TRX_CORE_SRST_M <<
- (dsaf_dev->reset_offset + 6);
+ reg_val |= XGMAC_TRX_CORE_SRST_M
+ << dsaf_dev->mac_cb[port]->port_rst_off;
if (val == 0)
reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
{
u32 reg_val_1;
u32 reg_val_2;
+ u32 port_rst_off;
if (port >= DSAF_GE_NUM)
return;
if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
reg_val_1 = 0x1 << port;
+ port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
/* there is difference between V1 and V2 in register.*/
if (AE_IS_VER1(dsaf_dev->dsaf_ver))
- reg_val_2 = 0x1041041 << port;
+ reg_val_2 = 0x1041041 << port_rst_off;
else
- reg_val_2 = 0x2082082 << port;
+ reg_val_2 = 0x2082082 << port_rst_off;
if (val == 0) {
dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
u32 reg_val = 0;
u32 reg_addr;
- if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
- reg_val |= RESET_REQ_OR_DREQ << port;
- else
- reg_val |= RESET_REQ_OR_DREQ <<
- (dsaf_dev->reset_offset + 6);
+ reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
if (val == 0)
reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;