ARM: dts: omap5.dtsi: add DSS RFBI node

The RFBI node for OMAP DSS was left out when adding the rest of the DSS
nodes, because it was not clear how to set up the clocks for the RFBI.

However, it seems that if there is a HWMOD for a device, we also need a
DT node for it. Otherwise, at boot, we get:

WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0()
omap_hwmod: dss_rfbi: doesn't have mpu register target base

Now that v3.17-rc3 contains a fix 8fd46439e1f5 ("ARM: dts:
omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK
required by the RFBI, let's add the RFBI node to get rid of the
warning.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
[tony@atomide.com: updated description per comments from Nishant]
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc8df1739f393657e9040e67e486e08a47e04648..1e6ff61a7f12851026c139930ee3636be36bad1d 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -945,6 +945,15 @@
                                clock-names = "fck";
                        };
 
+                       rfbi: encoder@58002000  {
+                               compatible = "ti,omap5-rfbi";
+                               reg = <0x58002000 0x100>;
+                               status = "disabled";
+                               ti,hwmods = "dss_rfbi";
+                               clocks = <&dss_dss_clk>, <&l3_iclk_div>;
+                               clock-names = "fck", "ick";
+                       };
+
                        dsi1: encoder@58004000 {
                                compatible = "ti,omap5-dsi";
                                reg = <0x58004000 0x200>,