drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disabling

Bspec requires a 10 us delay after disabling power well 1 and - if not
toggled on-demand - the AUX IO power wells during display uninit.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1498750622-14023-2-git-send-email-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index efe80ed5fd4d062f1999bfafc19670293d5a3dea..fd59016191ff2f96f52cfd892b69ac7260f6b816 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2701,6 +2701,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_power_well_disable(dev_priv, well);
 
        mutex_unlock(&power_domains->lock);
+
+       usleep_range(10, 30);           /* 10 us delay per Bspec */
 }
 
 void bxt_display_core_init(struct drm_i915_private *dev_priv,
@@ -2758,6 +2760,8 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_power_well_disable(dev_priv, well);
 
        mutex_unlock(&power_domains->lock);
+
+       usleep_range(10, 30);           /* 10 us delay per Bspec */
 }
 
 #define CNL_PROCMON_IDX(val) \
@@ -2859,6 +2863,8 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
        intel_power_well_disable(dev_priv, well);
        mutex_unlock(&power_domains->lock);
 
+       usleep_range(10, 30);           /* 10 us delay per Bspec */
+
        /* 5. Disable Comp */
        val = I915_READ(CHICKEN_MISC_2);
        val |= COMP_PWR_DOWN;