platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len
authorRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Fri, 7 Oct 2016 10:31:12 +0000 (16:01 +0530)
committerDarren Hart <dvhart@linux.intel.com>
Tue, 13 Dec 2016 17:28:54 +0000 (09:28 -0800)
On Sunrise Point PCH, the Power Management Controller provides 4K bytes of
memory space for various power management and debug registers. This fix is
needed to access power management & debug registers that are mapped at a
higher offset.

Also, this provides a fix for correctly masking the PWRMBASE as the initial
bits (0-11) are reserved.

Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
drivers/platform/x86/intel_pmc_core.c
drivers/platform/x86/intel_pmc_core.h

index e8b1b836ca2d3cd04e884e26a1916bc8a450daec..5774882a530093cbdf645d843a45918052349b6e 100644 (file)
@@ -149,6 +149,7 @@ static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
                dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
                return err;
        }
+       pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
        dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
 
        pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
index e3f671f4d12228e8ee9a11c471c5f8d68dc1a549..cde31ec02266c396efe260b538d3894ed08374ba 100644 (file)
@@ -26,8 +26,9 @@
 
 #define SPT_PMC_BASE_ADDR_OFFSET               0x48
 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET      0x13c
-#define SPT_PMC_MMIO_REG_LEN                   0x100
+#define SPT_PMC_MMIO_REG_LEN                   0x1000
 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP                0x64
+#define PMC_BASE_ADDR_MASK                     ~(SPT_PMC_MMIO_REG_LEN - 1)
 
 /**
  * struct pmc_dev - pmc device structure