drm/i915: scramble reset support for DP port CRC on g4x

We need to reset the DP scrambler on every vsync to get stable CRCs.
And since we can't use the normal pipe CRC on DP ports on g4x we
really need them to be able to test modesetting issues on (e)DP
outputs.

Note that the DC balance reset is for SDVO port CRCs so we don't
strictly need it. But better safe than sorry (and it's a nice template
in case we ever want to grab port CRCs for e.g. audio checking).

v2: Apply the suggestions from Damien's review.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7c29a88271779c000d83a6ac41a9d4db7b4734d6..8812516115125bd14b60f7070f8bf4ca2d053f26 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2057,6 +2057,9 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
                                 enum intel_pipe_crc_source *source,
                                 uint32_t *val)
 {
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       bool need_stable_symbols = false;
+
        if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
                int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
                if (ret)
@@ -2076,16 +2079,19 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
                if (!IS_G4X(dev))
                        return -EINVAL;
                *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
+               need_stable_symbols = true;
                break;
        case INTEL_PIPE_CRC_SOURCE_DP_C:
                if (!IS_G4X(dev))
                        return -EINVAL;
                *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
+               need_stable_symbols = true;
                break;
        case INTEL_PIPE_CRC_SOURCE_DP_D:
                if (!IS_G4X(dev))
                        return -EINVAL;
                *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
+               need_stable_symbols = true;
                break;
        case INTEL_PIPE_CRC_SOURCE_NONE:
                *val = 0;
@@ -2094,9 +2100,52 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
                return -EINVAL;
        }
 
+       /*
+        * When the pipe CRC tap point is after the transcoders we need
+        * to tweak symbol-level features to produce a deterministic series of
+        * symbols for a given frame. We need to reset those features only once
+        * a frame (instead of every nth symbol):
+        *   - DC-balance: used to ensure a better clock recovery from the data
+        *     link (SDVO)
+        *   - DisplayPort scrambling: used for EMI reduction
+        */
+       if (need_stable_symbols) {
+               uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+
+               WARN_ON(!IS_G4X(dev));
+
+               I915_WRITE(PORT_DFT_I9XX,
+                          I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
+
+               if (pipe == PIPE_A)
+                       tmp |= PIPE_A_SCRAMBLE_RESET;
+               else
+                       tmp |= PIPE_B_SCRAMBLE_RESET;
+
+               I915_WRITE(PORT_DFT2_G4X, tmp);
+       }
+
        return 0;
 }
 
+static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
+                                        enum pipe pipe)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       uint32_t tmp = I915_READ(PORT_DFT2_G4X);
+
+       if (pipe == PIPE_A)
+               tmp &= ~PIPE_A_SCRAMBLE_RESET;
+       else
+               tmp &= ~PIPE_B_SCRAMBLE_RESET;
+       I915_WRITE(PORT_DFT2_G4X, tmp);
+
+       if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
+               I915_WRITE(PORT_DFT_I9XX,
+                          I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
+       }
+}
+
 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
                                uint32_t *val)
 {
@@ -2215,6 +2264,9 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
                spin_unlock_irq(&pipe_crc->lock);
 
                kfree(entries);
+
+               if (IS_G4X(dev))
+                       g4x_undo_pipe_scramble_reset(dev, pipe);
        }
 
        return 0;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3dfcac7ef3c4bca3cc38bf7336e28bcdc1ccdc71..4328e3bd63b22ad4b5fcfaf2174f94754a9b5c56 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2150,6 +2150,14 @@
 #define PCH_HDMIC      0xe1150
 #define PCH_HDMID      0xe1160
 
+#define PORT_DFT_I9XX                          0x61150
+#define   DC_BALANCE_RESET                     (1 << 25)
+#define PORT_DFT2_G4X                          0x61154
+#define   DC_BALANCE_RESET_VLV                 (1 << 31)
+#define   PIPE_SCRAMBLE_RESET_MASK             (0x3 << 0)
+#define   PIPE_B_SCRAMBLE_RESET                        (1 << 1)
+#define   PIPE_A_SCRAMBLE_RESET                        (1 << 0)
+
 /* Gen 3 SDVO bits: */
 #define   SDVO_ENABLE                          (1 << 31)
 #define   SDVO_PIPE_SEL(pipe)                  ((pipe) << 30)