#define FRAME_RATE_RESOLUTION 1000
#define DEFAULT_TAG (0xE05)
+#define IGNORE_TAG (0xD5C) /* ex) encoder DRC */
+#define HEADER_TAG (0xC5D)
#define MFC_NO_INSTANCE_SET -1
mfc_debug(5, "[CTRLS] Control value "
"is not up to date: "
"0x%08x\n", ctrl->id);
- return -EINVAL;
+ if (ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG)
+ ctrl->value = IGNORE_TAG;
+ else
+ return -EINVAL;
}
found = 1;
mfc_change_state(ctx, MFCINST_FINISHING);
mfc_set_bit(ctx->num, &dev->work_bits);
- while (mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED)) {
+ while (ctx->state != MFCINST_FINISHED) {
ret = mfc_just_run(dev, ctx->num);
if (ret) {
mfc_err_ctx("Failed to run MFC\n");
mfc_err_ctx("Waiting for LAST_SEQ timed out\n");
break;
}
- if (ctx->state == MFCINST_FINISHED) {
- mfc_debug(2, "all encoded buffers out\n");
- break;
- }
}
}
struct mfc_enc *enc = ctx->enc_priv;
struct mfc_enc_params *p = &enc->params;
struct mfc_buf *dst_mb;
- int ret;
+ int ret, index;
enc->header_size = mfc_get_enc_strm_size();
mfc_debug(2, "[STREAM] encoded slice type: %d, header size: %d, display order: %d\n",
}
vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, mfc_get_enc_strm_size());
+
+ index = dst_mb->vb.vb2_buf.index;
+ if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->dst_ctrls[index]) < 0)
+ mfc_err_ctx("failed in get_buf_ctrls_val\n");
+ call_cop(ctx, get_buf_update_val, ctx, &ctx->dst_ctrls[index],
+ V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, HEADER_TAG);
+
vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE);
/* encoder dst buffer CFW UNPROT */
struct mfc_buf *mfc_buf)
{
struct mfc_dev *dev = ctx->dev;
- dma_addr_t addr;
- unsigned int size, offset, index;
+ dma_addr_t addr = 0;
+ unsigned int size = 0, offset = 0, index = -1;
- index = mfc_buf->vb.vb2_buf.index;
- addr = mfc_buf->addr[0][0];
- offset = mfc_buf->vb.vb2_buf.planes[0].data_offset;
- size = (unsigned int)vb2_plane_size(&mfc_buf->vb.vb2_buf, 0);
- size = ALIGN(size, 512);
+ if (mfc_buf) {
+ index = mfc_buf->vb.vb2_buf.index;
+ addr = mfc_buf->addr[0][0];
+ offset = mfc_buf->vb.vb2_buf.planes[0].data_offset;
+ size = (unsigned int)vb2_plane_size(&mfc_buf->vb.vb2_buf, 0);
+ size = ALIGN(size, 512);
+ }
MFC_WRITEL(addr, MFC_REG_E_STREAM_BUFFER_ADDR); /* 16B align */
MFC_WRITEL(size, MFC_REG_E_STREAM_BUFFER_SIZE);
int mfc_run_enc_last_frames(struct mfc_ctx *ctx)
{
- struct mfc_buf *dst_mb;
+ struct mfc_buf *dst_mb = NULL;
struct mfc_raw_info *raw;
raw = &ctx->raw_buf;
dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_SET_USED);
- if (!dst_mb) {
- mfc_debug(2, "no dst buffers\n");
- return -EAGAIN;
- }
+ if (!dst_mb)
+ mfc_debug(2, "no dst buffers set to zero\n");
mfc_debug(2, "Set address zero for all planes\n");
mfc_set_enc_frame_buffer(ctx, 0, raw->num_planes);