vpp: sr: disable more latch ctrl for SR0 [1/1]

PD#TV-7673

Problem:
SR0 register enabled the latch function, it will cause
frame size setting out of sync when bypass sr0.

Solution:
Disable the latch option.

Verify:
Verified with X301

Change-Id: Ibfc4c5f8f695757ddd7d7d9e50e4b5be23268388
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>

diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c
index b7b319019317d401b1dcc7b2eb5d2e3f39622575..421b50b543833838fbdc22777e292e8aab1d988d 100644 (file)
--- a/drivers/amlogic/media/video_sink/video.c
+++ b/drivers/amlogic/media/video_sink/video.c
@@ -13504,11 +13504,17 @@ static int __init video_early_init(void)
                /* disable latch for sr core0/1 scaler */
                WRITE_VCBUS_REG_BITS(
                        SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
+               WRITE_VCBUS_REG_BITS(
+                       SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
                WRITE_VCBUS_REG_BITS(
                        SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1);
-       } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B))
+       } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
                WRITE_VCBUS_REG_BITS(
                        SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
+               /* TODO: check if the bit8 is available */
+               /* WRITE_VCBUS_REG_BITS( */
+               /*      SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1); */
+       }
        return 0;
 }