arm64: Add ARCH_WORKAROUND_2 probing

commit a725e3dda1813ed306734823ac4c65ca04e38500 upstream.

As for Spectre variant-2, we rely on SMCCC 1.1 to provide the
discovery mechanism for detecting the SSBD mitigation.

A new capability is also allocated for that purpose, and a
config option.

Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 2d5f7aca156dd1c3f1603605e1535d9fadc2b72b..1bbb89d37f5724b71bf8aaa6bf05a9ee36ecc3f5 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -849,6 +849,15 @@ config HARDEN_BRANCH_PREDICTOR
 
          If unsure, say Y.
 
+config ARM64_SSBD
+       bool "Speculative Store Bypass Disable" if EXPERT
+       default y
+       help
+         This enables mitigation of the bypassing of previous stores
+         by speculative loads.
+
+         If unsure, say Y.
+
 menuconfig ARMV8_DEPRECATED
        bool "Emulate deprecated/obsolete ARMv8 instructions"
        depends on COMPAT

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 2e7b236bc596204724d7f5b04d9c6eb6ada744e0..76c0d23ca161fb8a02f05b4ef47d088c2e1e4726 100644 (file)
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -43,7 +43,8 @@
 #define ARM64_UNMAP_KERNEL_AT_EL0              23
 #define ARM64_HARDEN_BRANCH_PREDICTOR          24
 #define ARM64_HARDEN_BP_POST_GUEST_EXIT                25
+#define ARM64_SSBD                             26
 
-#define ARM64_NCAPS                            26
+#define ARM64_NCAPS                            27
 
 #endif /* __ASM_CPUCAPS_H */

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 62530ba60497e465299ebf9e91272c044aa0a1ee..86cd3b690f3512d050f77e5d2820cd868f391f63 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -252,6 +252,67 @@ void __init arm64_update_smccc_conduit(struct alt_instr *alt,
 
        *updptr = cpu_to_le32(insn);
 }
+
+static void arm64_set_ssbd_mitigation(bool state)
+{
+       switch (psci_ops.conduit) {
+       case PSCI_CONDUIT_HVC:
+               arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
+               break;
+
+       case PSCI_CONDUIT_SMC:
+               arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
+               break;
+
+       default:
+               WARN_ON_ONCE(1);
+               break;
+       }
+}
+
+static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
+                                   int scope)
+{
+       struct arm_smccc_res res;
+       bool supported = true;
+
+       WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
+
+       if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
+               return false;
+
+       /*
+        * The probe function return value is either negative
+        * (unsupported or mitigated), positive (unaffected), or zero
+        * (requires mitigation). We only need to do anything in the
+        * last case.
+        */
+       switch (psci_ops.conduit) {
+       case PSCI_CONDUIT_HVC:
+               arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
+                                 ARM_SMCCC_ARCH_WORKAROUND_2, &res);
+               if ((int)res.a0 != 0)
+                       supported = false;
+               break;
+
+       case PSCI_CONDUIT_SMC:
+               arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
+                                 ARM_SMCCC_ARCH_WORKAROUND_2, &res);
+               if ((int)res.a0 != 0)
+                       supported = false;
+               break;
+
+       default:
+               supported = false;
+       }
+
+       if (supported) {
+               __this_cpu_write(arm64_ssbd_callback_required, 1);
+               arm64_set_ssbd_mitigation(true);
+       }
+
+       return supported;
+}
 #endif /* CONFIG_ARM64_SSBD */
 
 #define MIDR_RANGE(model, min, max) \
@@ -451,6 +512,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
                .enable = enable_smccc_arch_workaround_1,
        },
+#endif
+#ifdef CONFIG_ARM64_SSBD
+       {
+               .desc = "Speculative Store Bypass Disable",
+               .def_scope = SCOPE_LOCAL_CPU,
+               .capability = ARM64_SSBD,
+               .matches = has_ssbd_mitigation,
+       },
 #endif
        {
        }