drm/i915/skl: Expose DC5/DC6 entry counts

The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

v2: Rebase
v3: Take RPM ref before reading (Imre)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446220412-32574-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 847753dd47ab4c3dbfcabaada6a092d4e8cbb27a..bf04f5bda32462b23cb9d5729642363e37e7b2d6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2811,6 +2811,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
        seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
                   CSR_VERSION_MINOR(csr->version));
 
+       intel_runtime_pm_get(dev_priv);
+
+       if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+               seq_printf(m, "DC3 -> DC5 count: %d\n",
+                          I915_READ(SKL_CSR_DC3_DC5_COUNT));
+               seq_printf(m, "DC5 -> DC6 count: %d\n",
+                          I915_READ(SKL_CSR_DC5_DC6_COUNT));
+       }
+
+       intel_runtime_pm_put(dev_priv);
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8f1d42063265109a466baf0e347d858b4325292..bbfc9d9a5b495f6fcaeb0f89837e90ce43714e2a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5697,6 +5697,10 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_12BIT  (2 << 0)
 #define GAMMA_MODE_MODE_SPLIT  (3 << 0)
 
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT  0x80030
+#define SKL_CSR_DC5_DC6_COUNT  0x8002C
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)