};
/* HT cap appropriate for wide channels */
-static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
+static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap = {
.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
.ht_supported = true,
},
};
+/* HT cap appropriate for SISO 20 */
+static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
+ .cap = IEEE80211_HT_CAP_SGI_20,
+ .ht_supported = true,
+ .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
+ .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
+ .mcs = {
+ .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ .rx_highest = cpu_to_le16(72),
+ .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
+ },
+};
+
/* HT cap appropriate for MIMO rates in 20mhz channel */
static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
.cap = IEEE80211_HT_CAP_SGI_20,
wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
- memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
- if (!strcmp(ht_mode_param, "mimo"))
+
+ if (!strcmp(ht_mode_param, "wide")) {
+ memcpy(&wl->ht_cap, &wl18xx_siso40_ht_cap,
+ sizeof(wl18xx_siso40_ht_cap));
+ } else if (!strcmp(ht_mode_param, "mimo")) {
memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
sizeof(wl18xx_mimo_ht_cap));
+ } else if (!strcmp(ht_mode_param, "siso20")) {
+ memcpy(&wl->ht_cap, &wl18xx_siso20_ht_cap,
+ sizeof(wl18xx_siso20_ht_cap));
+ } else {
+ wl1271_error("invalid ht_mode '%s'", ht_mode_param);
+ goto out_free;
+ }
wl18xx_conf_init(wl);
priv->conf.phy.low_band_component_type = 0x06;
} else {
wl1271_error("invalid board type '%s'", board_type_param);
- wlcore_free_hw(wl);
- return -EINVAL;
+ goto out_free;
}
if (!checksum_param) {
wl->enable_11a = enable_11a_param;
return wlcore_probe(wl, pdev);
+
+out_free:
+ wlcore_free_hw(wl);
+ return -EINVAL;
}
static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
module_exit(wl18xx_exit);
module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
-MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
+MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20");
module_param_named(board_type, board_type_param, charp, S_IRUSR);
MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "