return ring->adev->wb.wb[ring->rptr_offs];
}
-static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
+static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- return RREG32(CP_RB0_WPTR);
+ if (ring == &adev->gfx.gfx_ring[0])
+ return RREG32(CP_RB0_WPTR);
+ else if (ring == &adev->gfx.compute_ring[0])
+ return RREG32(CP_RB1_WPTR);
+ else if (ring == &adev->gfx.compute_ring[1])
+ return RREG32(CP_RB2_WPTR);
+ else
+ BUG();
}
static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
(void)RREG32(CP_RB0_WPTR);
}
-static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- u32 wptr;
-
- if (ring == &adev->gfx.compute_ring[0]) {
- wptr = RREG32(CP_RB1_WPTR);
- } else if (ring == &adev->gfx.compute_ring[1]) {
- wptr = RREG32(CP_RB2_WPTR);
- } else {
- BUG();
- }
-
- return wptr;
-}
-
static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
.get_rptr = gfx_v6_0_ring_get_rptr,
- .get_wptr = gfx_v6_0_ring_get_wptr_gfx,
+ .get_wptr = gfx_v6_0_ring_get_wptr,
.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
.parse_cs = NULL,
.emit_ib = gfx_v6_0_ring_emit_ib_gfx,
static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
.get_rptr = gfx_v6_0_ring_get_rptr,
- .get_wptr = gfx_v6_0_ring_get_wptr_compute,
+ .get_wptr = gfx_v6_0_ring_get_wptr,
.set_wptr = gfx_v6_0_ring_set_wptr_compute,
.parse_cs = NULL,
.emit_ib = gfx_v6_0_ring_emit_ib_compute,