ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
authorKukjin Kim <kgene.kim@samsung.com>
Sun, 6 Nov 2011 04:54:56 +0000 (13:54 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Sun, 6 Nov 2011 04:54:56 +0000 (13:54 +0900)
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
made for plaforms based on EXYNOS4 SoCs. But since upcoming
Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
codes in current mach-exynos4, one mach-exynos directory will
be used for them.

This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
avoid changing in driver side.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
146 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/configs/exynos4_defconfig
arch/arm/mach-exynos/Kconfig [new file with mode: 0644]
arch/arm/mach-exynos/Makefile [new file with mode: 0644]
arch/arm/mach-exynos/Makefile.boot [new file with mode: 0644]
arch/arm/mach-exynos/clock-exynos4210.c [new file with mode: 0644]
arch/arm/mach-exynos/clock-exynos4212.c [new file with mode: 0644]
arch/arm/mach-exynos/clock.c [new file with mode: 0644]
arch/arm/mach-exynos/cpu.c [new file with mode: 0644]
arch/arm/mach-exynos/cpuidle.c [new file with mode: 0644]
arch/arm/mach-exynos/dev-ahci.c [new file with mode: 0644]
arch/arm/mach-exynos/dev-audio.c [new file with mode: 0644]
arch/arm/mach-exynos/dev-dwmci.c [new file with mode: 0644]
arch/arm/mach-exynos/dev-pd.c [new file with mode: 0644]
arch/arm/mach-exynos/dev-sysmmu.c [new file with mode: 0644]
arch/arm/mach-exynos/dma.c [new file with mode: 0644]
arch/arm/mach-exynos/headsmp.S [new file with mode: 0644]
arch/arm/mach-exynos/hotplug.c [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/debug-macro.S [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/dma.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/dwmci.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/entry-macro.S [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/exynos4-clock.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/gpio.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/hardware.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/io.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/irqs.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/map.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/memory.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/pm-core.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/pmu.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-audss.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-clock.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-gpio.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-irq.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-mct.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-mem.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-pmu.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-sysmmu.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/regs-usb-phy.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/sysmmu.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/system.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/timex.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/uncompress.h [new file with mode: 0644]
arch/arm/mach-exynos/include/mach/vmalloc.h [new file with mode: 0644]
arch/arm/mach-exynos/init.c [new file with mode: 0644]
arch/arm/mach-exynos/irq-combiner.c [new file with mode: 0644]
arch/arm/mach-exynos/irq-eint.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-armlex4210.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-nuri.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-origen.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-smdk4x12.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-smdkv310.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-universal_c210.c [new file with mode: 0644]
arch/arm/mach-exynos/mct.c [new file with mode: 0644]
arch/arm/mach-exynos/platsmp.c [new file with mode: 0644]
arch/arm/mach-exynos/pm.c [new file with mode: 0644]
arch/arm/mach-exynos/pmu.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-fimc.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-fimd0.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c0.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c1.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c2.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c3.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c4.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c5.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c6.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-i2c7.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-keypad.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-sdhci-gpio.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-sdhci.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-usb-phy.c [new file with mode: 0644]
arch/arm/mach-exynos4/Kconfig [deleted file]
arch/arm/mach-exynos4/Makefile [deleted file]
arch/arm/mach-exynos4/Makefile.boot [deleted file]
arch/arm/mach-exynos4/clock-exynos4210.c [deleted file]
arch/arm/mach-exynos4/clock-exynos4212.c [deleted file]
arch/arm/mach-exynos4/clock.c [deleted file]
arch/arm/mach-exynos4/cpu.c [deleted file]
arch/arm/mach-exynos4/cpuidle.c [deleted file]
arch/arm/mach-exynos4/dev-ahci.c [deleted file]
arch/arm/mach-exynos4/dev-audio.c [deleted file]
arch/arm/mach-exynos4/dev-dwmci.c [deleted file]
arch/arm/mach-exynos4/dev-pd.c [deleted file]
arch/arm/mach-exynos4/dev-sysmmu.c [deleted file]
arch/arm/mach-exynos4/dma.c [deleted file]
arch/arm/mach-exynos4/headsmp.S [deleted file]
arch/arm/mach-exynos4/hotplug.c [deleted file]
arch/arm/mach-exynos4/include/mach/debug-macro.S [deleted file]
arch/arm/mach-exynos4/include/mach/dma.h [deleted file]
arch/arm/mach-exynos4/include/mach/dwmci.h [deleted file]
arch/arm/mach-exynos4/include/mach/entry-macro.S [deleted file]
arch/arm/mach-exynos4/include/mach/exynos4-clock.h [deleted file]
arch/arm/mach-exynos4/include/mach/gpio.h [deleted file]
arch/arm/mach-exynos4/include/mach/hardware.h [deleted file]
arch/arm/mach-exynos4/include/mach/io.h [deleted file]
arch/arm/mach-exynos4/include/mach/irqs.h [deleted file]
arch/arm/mach-exynos4/include/mach/map.h [deleted file]
arch/arm/mach-exynos4/include/mach/memory.h [deleted file]
arch/arm/mach-exynos4/include/mach/pm-core.h [deleted file]
arch/arm/mach-exynos4/include/mach/pmu.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-audss.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-clock.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-gpio.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-irq.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-mct.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-mem.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-pmu.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-sysmmu.h [deleted file]
arch/arm/mach-exynos4/include/mach/regs-usb-phy.h [deleted file]
arch/arm/mach-exynos4/include/mach/sysmmu.h [deleted file]
arch/arm/mach-exynos4/include/mach/system.h [deleted file]
arch/arm/mach-exynos4/include/mach/timex.h [deleted file]
arch/arm/mach-exynos4/include/mach/uncompress.h [deleted file]
arch/arm/mach-exynos4/include/mach/vmalloc.h [deleted file]
arch/arm/mach-exynos4/init.c [deleted file]
arch/arm/mach-exynos4/irq-combiner.c [deleted file]
arch/arm/mach-exynos4/irq-eint.c [deleted file]
arch/arm/mach-exynos4/mach-armlex4210.c [deleted file]
arch/arm/mach-exynos4/mach-nuri.c [deleted file]
arch/arm/mach-exynos4/mach-origen.c [deleted file]
arch/arm/mach-exynos4/mach-smdk4x12.c [deleted file]
arch/arm/mach-exynos4/mach-smdkv310.c [deleted file]
arch/arm/mach-exynos4/mach-universal_c210.c [deleted file]
arch/arm/mach-exynos4/mct.c [deleted file]
arch/arm/mach-exynos4/platsmp.c [deleted file]
arch/arm/mach-exynos4/pm.c [deleted file]
arch/arm/mach-exynos4/pmu.c [deleted file]
arch/arm/mach-exynos4/setup-fimc.c [deleted file]
arch/arm/mach-exynos4/setup-fimd0.c [deleted file]
arch/arm/mach-exynos4/setup-i2c0.c [deleted file]
arch/arm/mach-exynos4/setup-i2c1.c [deleted file]
arch/arm/mach-exynos4/setup-i2c2.c [deleted file]
arch/arm/mach-exynos4/setup-i2c3.c [deleted file]
arch/arm/mach-exynos4/setup-i2c4.c [deleted file]
arch/arm/mach-exynos4/setup-i2c5.c [deleted file]
arch/arm/mach-exynos4/setup-i2c6.c [deleted file]
arch/arm/mach-exynos4/setup-i2c7.c [deleted file]
arch/arm/mach-exynos4/setup-keypad.c [deleted file]
arch/arm/mach-exynos4/setup-sdhci-gpio.c [deleted file]
arch/arm/mach-exynos4/setup-sdhci.c [deleted file]
arch/arm/mach-exynos4/setup-usb-phy.c [deleted file]
arch/arm/plat-s5p/Kconfig
arch/arm/plat-s5p/cpu.c
arch/arm/plat-samsung/include/plat/exynos4.h

index 2bda424c1b2bb4b0ef7a74d63fe027d718e1c3b7..44789eff983f444c22cd967cbe418f7e50159358 100644 (file)
@@ -837,8 +837,8 @@ config ARCH_S5PV210
        help
          Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_EXYNOS4
-       bool "Samsung EXYNOS4"
+config ARCH_EXYNOS
+       bool "SAMSUNG EXYNOS"
        select CPU_V7
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_HAS_HOLES_MEMORYMODEL
@@ -852,7 +852,7 @@ config ARCH_EXYNOS4
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select NEED_MACH_MEMORY_H
        help
-         Samsung EXYNOS4 series based systems
+         Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 
 config ARCH_SHARK
        bool "Shark"
@@ -1079,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
 
 source "arch/arm/mach-s5pv210/Kconfig"
 
-source "arch/arm/mach-exynos4/Kconfig"
+source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
index b7c2d377a6c2330ed194ff931f0a91ec33b0fce8..dfcf3b033e10b465ff44107c43cfa1141fd989f4 100644 (file)
@@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX)              := s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)         := s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)         := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)         := s5pv210
-machine-$(CONFIG_ARCH_EXYNOS4)         := exynos4
+machine-$(CONFIG_ARCH_EXYNOS4)         := exynos
 machine-$(CONFIG_ARCH_SA1100)          := sa1100
 machine-$(CONFIG_ARCH_SHARK)           := shark
 machine-$(CONFIG_ARCH_SHMOBILE)        := shmobile
index cd40bb56e5686c58b5c2ad7beab4a2105842d897..bffe68e190a3d93157886557e1958bde59798648 100644 (file)
@@ -4,19 +4,18 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_EXYNOS4=y
+CONFIG_ARCH_EXYNOS=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDKC210=y
-CONFIG_MACH_SMDKV310=y
 CONFIG_MACH_ARMLEX4210=y
 CONFIG_MACH_UNIVERSAL_C210=y
 CONFIG_MACH_NURI=y
 CONFIG_MACH_ORIGEN=y
+CONFIG_MACH_SMDK4412=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
@@ -61,13 +60,9 @@ CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_RT_MUTEXES=y
 CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_DEBUG_S3C_UART=1
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
new file mode 100644 (file)
index 0000000..724ec0f
--- /dev/null
@@ -0,0 +1,349 @@
+# arch/arm/mach-exynos/Kconfig
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#              http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+# Configuration options for the EXYNOS4
+
+if ARCH_EXYNOS
+
+menu "SAMSUNG EXYNOS SoCs Support"
+
+choice
+       prompt "EXYNOS System Type"
+       default ARCH_EXYNOS4
+
+config ARCH_EXYNOS4
+       bool "SAMSUNG EXYNOS4"
+       help
+         Samsung EXYNOS4 SoCs based systems
+
+endchoice
+
+comment "EXYNOS SoCs"
+
+config CPU_EXYNOS4210
+       bool "SAMSUNG EXYNOS4210"
+       default y
+       depends on ARCH_EXYNOS4
+       select SAMSUNG_DMADEV
+       select ARM_CPU_SUSPEND if PM
+       select S5P_PM if PM
+       select S5P_SLEEP if PM
+       help
+         Enable EXYNOS4210 CPU support
+
+config SOC_EXYNOS4212
+       bool "SAMSUNG EXYNOS4212"
+       default y
+       depends on ARCH_EXYNOS4
+       select S5P_PM if PM
+       select S5P_SLEEP if PM
+       help
+         Enable EXYNOS4212 SoC support
+
+config SOC_EXYNOS4412
+       bool "SAMSUNG EXYNOS4412"
+       default y
+       depends on ARCH_EXYNOS4
+       help
+         Enable EXYNOS4412 SoC support
+
+config EXYNOS4_MCT
+       bool
+       default y
+       help
+         Use MCT (Multi Core Timer) as kernel timers
+
+config EXYNOS4_DEV_AHCI
+       bool
+       help
+         Compile in platform device definitions for AHCI
+
+config EXYNOS4_SETUP_FIMD0
+       bool
+       help
+         Common setup code for FIMD0.
+
+config EXYNOS4_DEV_PD
+       bool
+       help
+         Compile in platform device definitions for Power Domain
+
+config EXYNOS4_DEV_SYSMMU
+       bool
+       help
+         Common setup code for SYSTEM MMU in EXYNOS4
+
+config EXYNOS4_DEV_DWMCI
+       bool
+       help
+         Compile in platform device definitions for DWMCI
+
+config EXYNOS4_SETUP_I2C1
+       bool
+       help
+         Common setup code for i2c bus 1.
+
+config EXYNOS4_SETUP_I2C2
+       bool
+       help
+         Common setup code for i2c bus 2.
+
+config EXYNOS4_SETUP_I2C3
+       bool
+       help
+         Common setup code for i2c bus 3.
+
+config EXYNOS4_SETUP_I2C4
+       bool
+       help
+         Common setup code for i2c bus 4.
+
+config EXYNOS4_SETUP_I2C5
+       bool
+       help
+         Common setup code for i2c bus 5.
+
+config EXYNOS4_SETUP_I2C6
+       bool
+       help
+         Common setup code for i2c bus 6.
+
+config EXYNOS4_SETUP_I2C7
+       bool
+       help
+         Common setup code for i2c bus 7.
+
+config EXYNOS4_SETUP_KEYPAD
+       bool
+       help
+         Common setup code for keypad.
+
+config EXYNOS4_SETUP_SDHCI
+       bool
+       select EXYNOS4_SETUP_SDHCI_GPIO
+       help
+         Internal helper functions for EXYNOS4 based SDHCI systems.
+
+config EXYNOS4_SETUP_SDHCI_GPIO
+       bool
+       help
+         Common setup code for SDHCI gpio.
+
+config EXYNOS4_SETUP_FIMC
+       bool
+       help
+         Common setup code for the camera interfaces.
+
+config EXYNOS4_SETUP_USB_PHY
+       bool
+       help
+         Common setup code for USB PHY controller
+
+# machine support
+
+if ARCH_EXYNOS4
+
+comment "EXYNOS4210 Boards"
+
+config MACH_SMDKC210
+       bool "SMDKC210"
+       select MACH_SMDKV310
+       help
+         Machine support for Samsung SMDKC210
+
+config MACH_SMDKV310
+       bool "SMDKV310"
+       select CPU_EXYNOS4210
+       select S5P_DEV_FIMD0
+       select S3C_DEV_RTC
+       select S3C_DEV_WDT
+       select S3C_DEV_I2C1
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_I2C_HDMIPHY
+       select S5P_DEV_MFC
+       select S5P_DEV_TV
+       select S5P_DEV_USB_EHCI
+       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC1
+       select S3C_DEV_HSMMC2
+       select S3C_DEV_HSMMC3
+       select SAMSUNG_DEV_BACKLIGHT
+       select EXYNOS4_DEV_AHCI
+       select SAMSUNG_DEV_KEYPAD
+       select EXYNOS4_DEV_PD
+       select SAMSUNG_DEV_PWM
+       select EXYNOS4_DEV_SYSMMU
+       select EXYNOS4_SETUP_FIMD0
+       select EXYNOS4_SETUP_I2C1
+       select EXYNOS4_SETUP_KEYPAD
+       select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_USB_PHY
+       help
+         Machine support for Samsung SMDKV310
+
+config MACH_ARMLEX4210
+       bool "ARMLEX4210"
+       select CPU_EXYNOS4210
+       select S3C_DEV_RTC
+       select S3C_DEV_WDT
+       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC2
+       select S3C_DEV_HSMMC3
+       select EXYNOS4_DEV_AHCI
+       select EXYNOS4_DEV_SYSMMU
+       select EXYNOS4_SETUP_SDHCI
+       help
+         Machine support for Samsung ARMLEX4210 based on EXYNOS4210
+
+config MACH_UNIVERSAL_C210
+       bool "Mobile UNIVERSAL_C210 Board"
+       select CPU_EXYNOS4210
+       select S5P_GPIO_INT
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_CSIS0
+       select S5P_DEV_FIMD0
+       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC2
+       select S3C_DEV_HSMMC3
+       select S3C_DEV_I2C1
+       select S3C_DEV_I2C3
+       select S3C_DEV_I2C5
+       select S5P_DEV_I2C_HDMIPHY
+       select S5P_DEV_MFC
+       select S5P_DEV_ONENAND
+       select S5P_DEV_TV
+       select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMD0
+       select EXYNOS4_SETUP_I2C1
+       select EXYNOS4_SETUP_I2C3
+       select EXYNOS4_SETUP_I2C5
+       select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_FIMC
+       select S5P_SETUP_MIPIPHY
+       help
+         Machine support for Samsung Mobile Universal S5PC210 Reference
+         Board.
+
+config MACH_NURI
+       bool "Mobile NURI Board"
+       select CPU_EXYNOS4210
+       select S5P_GPIO_INT
+       select S3C_DEV_WDT
+       select S3C_DEV_RTC
+       select S5P_DEV_FIMD0
+       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC2
+       select S3C_DEV_HSMMC3
+       select S3C_DEV_I2C1
+       select S3C_DEV_I2C3
+       select S3C_DEV_I2C5
+       select S5P_DEV_CSIS0
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_MFC
+       select S5P_DEV_USB_EHCI
+       select S5P_SETUP_MIPIPHY
+       select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMC
+       select EXYNOS4_SETUP_FIMD0
+       select EXYNOS4_SETUP_I2C1
+       select EXYNOS4_SETUP_I2C3
+       select EXYNOS4_SETUP_I2C5
+       select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_USB_PHY
+       select S5P_SETUP_MIPIPHY
+       select SAMSUNG_DEV_PWM
+       select SAMSUNG_DEV_ADC
+       help
+         Machine support for Samsung Mobile NURI Board.
+
+config MACH_ORIGEN
+       bool "ORIGEN"
+       select CPU_EXYNOS4210
+       select S3C_DEV_RTC
+       select S3C_DEV_WDT
+       select S3C_DEV_HSMMC
+       select S3C_DEV_HSMMC2
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_FIMD0
+       select S5P_DEV_I2C_HDMIPHY
+       select S5P_DEV_MFC
+       select S5P_DEV_TV
+       select S5P_DEV_USB_EHCI
+       select SAMSUNG_DEV_BACKLIGHT
+       select SAMSUNG_DEV_PWM
+       select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMD0
+       select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_USB_PHY
+       help
+         Machine support for ORIGEN based on Samsung EXYNOS4210
+
+comment "EXYNOS4212 Boards"
+
+config MACH_SMDK4212
+       bool "SMDK4212"
+       select SOC_EXYNOS4212
+       select S3C_DEV_HSMMC2
+       select S3C_DEV_HSMMC3
+       select S3C_DEV_I2C1
+       select S3C_DEV_I2C3
+       select S3C_DEV_I2C7
+       select S3C_DEV_RTC
+       select S3C_DEV_WDT
+       select SAMSUNG_DEV_BACKLIGHT
+       select SAMSUNG_DEV_KEYPAD
+       select SAMSUNG_DEV_PWM
+       select EXYNOS4_SETUP_I2C1
+       select EXYNOS4_SETUP_I2C3
+       select EXYNOS4_SETUP_I2C7
+       select EXYNOS4_SETUP_KEYPAD
+       select EXYNOS4_SETUP_SDHCI
+       help
+         Machine support for Samsung SMDK4212
+
+comment "EXYNOS4412 Boards"
+
+config MACH_SMDK4412
+       bool "SMDK4412"
+       select SOC_EXYNOS4412
+       select MACH_SMDK4212
+       help
+         Machine support for Samsung SMDK4412
+endif
+
+if ARCH_EXYNOS4
+
+comment "Configuration for HSMMC 8-bit bus width"
+
+config EXYNOS4_SDHCI_CH0_8BIT
+       bool "Channel 0 with 8-bit bus"
+       help
+         Support HSMMC Channel 0 8-bit bus.
+         If selected, Channel 1 is disabled.
+
+config EXYNOS4_SDHCI_CH2_8BIT
+       bool "Channel 2 with 8-bit bus"
+       help
+         Support HSMMC Channel 2 8-bit bus.
+         If selected, Channel 3 is disabled.
+endif
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
new file mode 100644 (file)
index 0000000..59069a3
--- /dev/null
@@ -0,0 +1,60 @@
+# arch/arm/mach-exynos/Makefile
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#              http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y                          :=
+obj-m                          :=
+obj-n                          :=
+obj-                           :=
+
+# Core support for EXYNOS4 system
+
+obj-$(CONFIG_ARCH_EXYNOS4)     += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS4)     += irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
+obj-$(CONFIG_PM)               += pm.o
+obj-$(CONFIG_CPU_IDLE)         += cpuidle.o
+
+obj-$(CONFIG_SMP)              += platsmp.o headsmp.o
+
+obj-$(CONFIG_EXYNOS4_MCT)      += mct.o
+
+obj-$(CONFIG_HOTPLUG_CPU)      += hotplug.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDKC210)            += mach-smdkv310.o
+obj-$(CONFIG_MACH_SMDKV310)            += mach-smdkv310.o
+obj-$(CONFIG_MACH_ARMLEX4210)          += mach-armlex4210.o
+obj-$(CONFIG_MACH_UNIVERSAL_C210)      += mach-universal_c210.o
+obj-$(CONFIG_MACH_NURI)                        += mach-nuri.o
+obj-$(CONFIG_MACH_ORIGEN)              += mach-origen.o
+
+obj-$(CONFIG_MACH_SMDK4212)            += mach-smdk4x12.o
+obj-$(CONFIG_MACH_SMDK4412)            += mach-smdk4x12.o
+
+# device support
+
+obj-$(CONFIG_ARCH_EXYNOS4)             += dev-audio.o
+obj-$(CONFIG_EXYNOS4_DEV_AHCI)         += dev-ahci.o
+obj-$(CONFIG_EXYNOS4_DEV_PD)           += dev-pd.o
+obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)       += dev-sysmmu.o
+obj-$(CONFIG_EXYNOS4_DEV_DWMCI)                += dev-dwmci.o
+
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC)       += setup-fimc.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)      += setup-fimd0.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C1)       += setup-i2c1.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C2)       += setup-i2c2.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C3)       += setup-i2c3.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C4)       += setup-i2c4.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C5)       += setup-i2c5.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C6)       += setup-i2c6.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C7)       += setup-i2c7.o
+obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)     += setup-keypad.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)      += setup-sdhci.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)    += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
new file mode 100644 (file)
index 0000000..b9862e2
--- /dev/null
@@ -0,0 +1,2 @@
+   zreladdr-y  += 0x40008000
+params_phys-y  := 0x40000100
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
new file mode 100644 (file)
index 0000000..b9d5ef6
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4210_clock_save[] = {
+       SAVE_ITEM(S5P_CLKSRC_IMAGE),
+       SAVE_ITEM(S5P_CLKSRC_LCD1),
+       SAVE_ITEM(S5P_CLKDIV_IMAGE),
+       SAVE_ITEM(S5P_CLKDIV_LCD1),
+       SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+       SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+};
+
+static struct clksrc_clk *sysclks[] = {
+       /* nothing here yet */
+};
+
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static struct clksrc_clk clksrcs[] = {
+       {
+               .clk            = {
+                       .name           = "sclk_sata",
+                       .id             = -1,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &clkset_mout_corebus,
+               .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimd",
+                       .devname        = "exynos4-fb.1",
+                       .enable         = exynos4_clksrc_mask_lcd1_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+       },
+};
+
+static struct clk init_clocks_off[] = {
+       {
+               .name           = "sataphy",
+               .id             = -1,
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "sata",
+               .id             = -1,
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "fimd",
+               .devname        = "exynos4-fb.1",
+               .enable         = exynos4_clk_ip_lcd1_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4210_clock_suspend(void)
+{
+       s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+
+       return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+       s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4210_clock_syscore_ops = {
+       .suspend        = exynos4210_clock_suspend,
+       .resume         = exynos4210_clock_resume,
+};
+
+void __init exynos4210_register_clocks(void)
+{
+       int ptr;
+
+       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+       clk_mout_mpll.reg_src.shift = 8;
+       clk_mout_mpll.reg_src.size = 1;
+
+       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+               s3c_register_clksrc(sysclks[ptr], 1);
+
+       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+       register_syscore_ops(&exynos4210_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
new file mode 100644 (file)
index 0000000..77d5dec
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4212_clock_save[] = {
+       SAVE_ITEM(S5P_CLKSRC_IMAGE),
+       SAVE_ITEM(S5P_CLKDIV_IMAGE),
+       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+};
+
+static struct clk *clk_src_mpll_user_list[] = {
+       [0] = &clk_fin_mpll,
+       [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clk_src_mpll_user = {
+       .sources        = clk_src_mpll_user_list,
+       .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk clk_mout_mpll_user = {
+       .clk = {
+               .name           = "mout_mpll_user",
+       },
+       .sources        = &clk_src_mpll_user,
+       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk *sysclks[] = {
+       &clk_mout_mpll_user,
+};
+
+static struct clksrc_clk clksrcs[] = {
+       /* nothing here yet */
+};
+
+static struct clk init_clocks_off[] = {
+       /* nothing here yet */
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4212_clock_suspend(void)
+{
+       s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+
+       return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+       s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4212_clock_syscore_ops = {
+       .suspend        = exynos4212_clock_suspend,
+       .resume         = exynos4212_clock_resume,
+};
+
+void __init exynos4212_register_clocks(void)
+{
+       int ptr;
+
+       /* usbphy1 is removed */
+       clkset_group_list[4] = NULL;
+
+       /* mout_mpll_user is used */
+       clkset_group_list[6] = &clk_mout_mpll_user.clk;
+       clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+
+       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+       clk_mout_mpll.reg_src.shift = 12;
+       clk_mout_mpll.reg_src.size = 1;
+
+       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+               s3c_register_clksrc(sysclks[ptr], 1);
+
+       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+       register_syscore_ops(&exynos4212_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
new file mode 100644 (file)
index 0000000..2894f0a
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+/* linux/arch/arm/mach-exynos4/clock.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4_clock_save[] = {
+       SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+       SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+       SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+       SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+       SAVE_ITEM(S5P_CLKSRC_TOP0),
+       SAVE_ITEM(S5P_CLKSRC_TOP1),
+       SAVE_ITEM(S5P_CLKSRC_CAM),
+       SAVE_ITEM(S5P_CLKSRC_TV),
+       SAVE_ITEM(S5P_CLKSRC_MFC),
+       SAVE_ITEM(S5P_CLKSRC_G3D),
+       SAVE_ITEM(S5P_CLKSRC_LCD0),
+       SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+       SAVE_ITEM(S5P_CLKSRC_FSYS),
+       SAVE_ITEM(S5P_CLKSRC_PERIL0),
+       SAVE_ITEM(S5P_CLKSRC_PERIL1),
+       SAVE_ITEM(S5P_CLKDIV_CAM),
+       SAVE_ITEM(S5P_CLKDIV_TV),
+       SAVE_ITEM(S5P_CLKDIV_MFC),
+       SAVE_ITEM(S5P_CLKDIV_G3D),
+       SAVE_ITEM(S5P_CLKDIV_LCD0),
+       SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+       SAVE_ITEM(S5P_CLKDIV_FSYS0),
+       SAVE_ITEM(S5P_CLKDIV_FSYS1),
+       SAVE_ITEM(S5P_CLKDIV_FSYS2),
+       SAVE_ITEM(S5P_CLKDIV_FSYS3),
+       SAVE_ITEM(S5P_CLKDIV_PERIL0),
+       SAVE_ITEM(S5P_CLKDIV_PERIL1),
+       SAVE_ITEM(S5P_CLKDIV_PERIL2),
+       SAVE_ITEM(S5P_CLKDIV_PERIL3),
+       SAVE_ITEM(S5P_CLKDIV_PERIL4),
+       SAVE_ITEM(S5P_CLKDIV_PERIL5),
+       SAVE_ITEM(S5P_CLKDIV_TOP),
+       SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+       SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+       SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+       SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+       SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+       SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+       SAVE_ITEM(S5P_CLKDIV2_RATIO),
+       SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+       SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+       SAVE_ITEM(S5P_CLKGATE_IP_TV),
+       SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+       SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+       SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+       SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+       SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+       SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+       SAVE_ITEM(S5P_CLKGATE_BLOCK),
+       SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+       SAVE_ITEM(S5P_CLKSRC_DMC),
+       SAVE_ITEM(S5P_CLKDIV_DMC0),
+       SAVE_ITEM(S5P_CLKDIV_DMC1),
+       SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+       SAVE_ITEM(S5P_CLKSRC_CPU),
+       SAVE_ITEM(S5P_CLKDIV_CPU),
+       SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+       SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+       SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+
+struct clk clk_sclk_hdmi27m = {
+       .name           = "sclk_hdmi27m",
+       .rate           = 27000000,
+};
+
+struct clk clk_sclk_hdmiphy = {
+       .name           = "sclk_hdmiphy",
+};
+
+struct clk clk_sclk_usbphy0 = {
+       .name           = "sclk_usbphy0",
+       .rate           = 27000000,
+};
+
+struct clk clk_sclk_usbphy1 = {
+       .name           = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+       .name           = "apb_pclk",
+       .id             = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk clk_mout_apll = {
+       .clk    = {
+               .name           = "mout_apll",
+       },
+       .sources        = &clk_src_apll,
+       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+struct clksrc_clk clk_sclk_apll = {
+       .clk    = {
+               .name           = "sclk_apll",
+               .parent         = &clk_mout_apll.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+struct clksrc_clk clk_mout_epll = {
+       .clk    = {
+               .name           = "mout_epll",
+       },
+       .sources        = &clk_src_epll,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_mpll = {
+       .clk = {
+               .name           = "mout_mpll",
+       },
+       .sources        = &clk_src_mpll,
+
+       /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *clkset_moutcore_list[] = {
+       [0] = &clk_mout_apll.clk,
+       [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_moutcore = {
+       .sources        = clkset_moutcore_list,
+       .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
+};
+
+static struct clksrc_clk clk_moutcore = {
+       .clk    = {
+               .name           = "moutcore",
+       },
+       .sources        = &clkset_moutcore,
+       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_coreclk = {
+       .clk    = {
+               .name           = "core_clk",
+               .parent         = &clk_moutcore.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_armclk = {
+       .clk    = {
+               .name           = "armclk",
+               .parent         = &clk_coreclk.clk,
+       },
+};
+
+static struct clksrc_clk clk_aclk_corem0 = {
+       .clk    = {
+               .name           = "aclk_corem0",
+               .parent         = &clk_coreclk.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cores = {
+       .clk    = {
+               .name           = "aclk_cores",
+               .parent         = &clk_coreclk.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_corem1 = {
+       .clk    = {
+               .name           = "aclk_corem1",
+               .parent         = &clk_coreclk.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_periphclk = {
+       .clk    = {
+               .name           = "periphclk",
+               .parent         = &clk_coreclk.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+struct clk *clkset_corebus_list[] = {
+       [0] = &clk_mout_mpll.clk,
+       [1] = &clk_sclk_apll.clk,
+};
+
+struct clksrc_sources clkset_mout_corebus = {
+       .sources        = clkset_corebus_list,
+       .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
+};
+
+static struct clksrc_clk clk_mout_corebus = {
+       .clk    = {
+               .name           = "mout_corebus",
+       },
+       .sources        = &clkset_mout_corebus,
+       .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_dmc = {
+       .clk    = {
+               .name           = "sclk_dmc",
+               .parent         = &clk_mout_corebus.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cored = {
+       .clk    = {
+               .name           = "aclk_cored",
+               .parent         = &clk_sclk_dmc.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_corep = {
+       .clk    = {
+               .name           = "aclk_corep",
+               .parent         = &clk_aclk_cored.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_acp = {
+       .clk    = {
+               .name           = "aclk_acp",
+               .parent         = &clk_mout_corebus.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_pclk_acp = {
+       .clk    = {
+               .name           = "pclk_acp",
+               .parent         = &clk_aclk_acp.clk,
+       },
+       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *clkset_aclk_top_list[] = {
+       [0] = &clk_mout_mpll.clk,
+       [1] = &clk_sclk_apll.clk,
+};
+
+struct clksrc_sources clkset_aclk = {
+       .sources        = clkset_aclk_top_list,
+       .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
+};
+
+static struct clksrc_clk clk_aclk_200 = {
+       .clk    = {
+               .name           = "aclk_200",
+       },
+       .sources        = &clkset_aclk,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
+       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_100 = {
+       .clk    = {
+               .name           = "aclk_100",
+       },
+       .sources        = &clkset_aclk,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
+       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_aclk_160 = {
+       .clk    = {
+               .name           = "aclk_160",
+       },
+       .sources        = &clkset_aclk,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
+       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk clk_aclk_133 = {
+       .clk    = {
+               .name           = "aclk_133",
+       },
+       .sources        = &clkset_aclk,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
+       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *clkset_vpllsrc_list[] = {
+       [0] = &clk_fin_vpll,
+       [1] = &clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources clkset_vpllsrc = {
+       .sources        = clkset_vpllsrc_list,
+       .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk clk_vpllsrc = {
+       .clk    = {
+               .name           = "vpll_src",
+               .enable         = exynos4_clksrc_mask_top_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources        = &clkset_vpllsrc,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_vpll_list[] = {
+       [0] = &clk_vpllsrc.clk,
+       [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources clkset_sclk_vpll = {
+       .sources        = clkset_sclk_vpll_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
+};
+
+struct clksrc_clk clk_sclk_vpll = {
+       .clk    = {
+               .name           = "sclk_vpll",
+       },
+       .sources        = &clkset_sclk_vpll,
+       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk init_clocks_off[] = {
+       {
+               .name           = "timers",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1<<24),
+       }, {
+               .name           = "csis",
+               .devname        = "s5p-mipi-csis.0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "csis",
+               .devname        = "s5p-mipi-csis.1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.2",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.3",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "fimd",
+               .devname        = "exynos4-fb.0",
+               .enable         = exynos4_clk_ip_lcd0_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "dwmmc",
+               .parent         = &clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "dac",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "mixer",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "vp",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "hdmi",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "hdmiphy",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_hdmiphy_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "dacphy",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_dac_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "dma",
+               .devname        = "dma-pl330.0",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "dma",
+               .devname        = "dma-pl330.1",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "adc",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "keypad",
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 16),
+       }, {
+               .name           = "rtc",
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "watchdog",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
+               .name           = "usbhost",
+               .enable         = exynos4_clk_ip_fsys_ctrl ,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "otg",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 16),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 17),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 19),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 21),
+       }, {
+               .name           = "ac97",
+               .devname        = "samsung-ac97",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 27),
+       }, {
+               .name           = "fimg2d",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "mfc",
+               .devname        = "s5p-mfc",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.0",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.1",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.2",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.3",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.4",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.5",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 11),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.6",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.7",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-hdmiphy-i2c",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
+               .name           = "SYSMMU_MDMA",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "SYSMMU_FIMC0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "SYSMMU_FIMC1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "SYSMMU_FIMC2",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "SYSMMU_FIMC3",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "SYSMMU_JPEG",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 11),
+       }, {
+               .name           = "SYSMMU_FIMD0",
+               .enable         = exynos4_clk_ip_lcd0_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_FIMD1",
+               .enable         = exynos4_clk_ip_lcd1_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_PCIe",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "SYSMMU_G2D",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "SYSMMU_ROTATOR",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_TV",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_MFC_L",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "SYSMMU_MFC_R",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 2),
+       }
+};
+
+static struct clk init_clocks[] = {
+       {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.3",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.4",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.5",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 5),
+       }
+};
+
+struct clk *clkset_group_list[] = {
+       [0] = &clk_ext_xtal_mux,
+       [1] = &clk_xusbxti,
+       [2] = &clk_sclk_hdmi27m,
+       [3] = &clk_sclk_usbphy0,
+       [4] = &clk_sclk_usbphy1,
+       [5] = &clk_sclk_hdmiphy,
+       [6] = &clk_mout_mpll.clk,
+       [7] = &clk_mout_epll.clk,
+       [8] = &clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources clkset_group = {
+       .sources        = clkset_group_list,
+       .nr_sources     = ARRAY_SIZE(clkset_group_list),
+};
+
+static struct clk *clkset_mout_g2d0_list[] = {
+       [0] = &clk_mout_mpll.clk,
+       [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d0 = {
+       .sources        = clkset_mout_g2d0_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk clk_mout_g2d0 = {
+       .clk    = {
+               .name           = "mout_g2d0",
+       },
+       .sources        = &clkset_mout_g2d0,
+       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d1_list[] = {
+       [0] = &clk_mout_epll.clk,
+       [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d1 = {
+       .sources        = clkset_mout_g2d1_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk clk_mout_g2d1 = {
+       .clk    = {
+               .name           = "mout_g2d1",
+       },
+       .sources        = &clkset_mout_g2d1,
+       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d_list[] = {
+       [0] = &clk_mout_g2d0.clk,
+       [1] = &clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d = {
+       .sources        = clkset_mout_g2d_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
+};
+
+static struct clk *clkset_mout_mfc0_list[] = {
+       [0] = &clk_mout_mpll.clk,
+       [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc0 = {
+       .sources        = clkset_mout_mfc0_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk clk_mout_mfc0 = {
+       .clk    = {
+               .name           = "mout_mfc0",
+       },
+       .sources        = &clkset_mout_mfc0,
+       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc1_list[] = {
+       [0] = &clk_mout_epll.clk,
+       [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc1 = {
+       .sources        = clkset_mout_mfc1_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk clk_mout_mfc1 = {
+       .clk    = {
+               .name           = "mout_mfc1",
+       },
+       .sources        = &clkset_mout_mfc1,
+       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc_list[] = {
+       [0] = &clk_mout_mfc0.clk,
+       [1] = &clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc = {
+       .sources        = clkset_mout_mfc_list,
+       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
+};
+
+static struct clk *clkset_sclk_dac_list[] = {
+       [0] = &clk_sclk_vpll.clk,
+       [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+       .sources        = clkset_sclk_dac_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+       .clk            = {
+               .name           = "sclk_dac",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &clkset_sclk_dac,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_pixel = {
+       .clk            = {
+               .name           = "sclk_pixel",
+               .parent = &clk_sclk_vpll.clk,
+       },
+       .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_hdmi_list[] = {
+       [0] = &clk_sclk_pixel.clk,
+       [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+       .sources        = clkset_sclk_hdmi_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+       .clk            = {
+               .name           = "sclk_hdmi",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &clkset_sclk_hdmi,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_mixer_list[] = {
+       [0] = &clk_sclk_dac.clk,
+       [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+       .sources        = clkset_sclk_mixer_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk clk_sclk_mixer = {
+       .clk            = {
+               .name           = "sclk_mixer",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .sources = &clkset_sclk_mixer,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+       &clk_sclk_dac,
+       &clk_sclk_pixel,
+       &clk_sclk_hdmi,
+       &clk_sclk_mixer,
+};
+
+static struct clksrc_clk clk_dout_mmc0 = {
+       .clk            = {
+               .name           = "dout_mmc0",
+       },
+       .sources = &clkset_group,
+       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc1 = {
+       .clk            = {
+               .name           = "dout_mmc1",
+       },
+       .sources = &clkset_group,
+       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc2 = {
+       .clk            = {
+               .name           = "dout_mmc2",
+       },
+       .sources = &clkset_group,
+       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc3 = {
+       .clk            = {
+               .name           = "dout_mmc3",
+       },
+       .sources = &clkset_group,
+       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc4 = {
+       .clk            = {
+               .name           = "dout_mmc4",
+       },
+       .sources = &clkset_group,
+       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clksrcs[] = {
+       {
+               .clk    = {
+                       .name           = "uclk1",
+                       .devname        = "s5pv210-uart.0",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "uclk1",
+                       .devname        = "s5pv210-uart.1",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 4),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "uclk1",
+                       .devname        = "s5pv210-uart.2",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 8),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "uclk1",
+                       .devname        = "s5pv210-uart.3",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 12),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_pwm",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_csis",
+                       .devname        = "s5p-mipi-csis.0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_csis",
+                       .devname        = "s5p-mipi-csis.1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 28),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_cam0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_cam1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 20),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 4),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.2",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 8),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.3",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 12),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimd",
+                       .devname        = "exynos4-fb.0",
+                       .enable         = exynos4_clksrc_mask_lcd0_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_spi",
+                       .devname        = "s3c64xx-spi.0",
+                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_spi",
+                       .devname        = "s3c64xx-spi.1",
+                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                       .ctrlbit        = (1 << 20),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_spi",
+                       .devname        = "s3c64xx-spi.2",
+                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &clkset_group,
+               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+               .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_fimg2d",
+               },
+               .sources = &clkset_mout_g2d,
+               .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+               .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_mfc",
+                       .devname        = "s5p-mfc",
+               },
+               .sources = &clkset_mout_mfc,
+               .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
+               .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_mmc",
+                       .devname        = "s3c-sdhci.0",
+                       .parent         = &clk_dout_mmc0.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_mmc",
+                       .devname        = "s3c-sdhci.1",
+                       .parent         = &clk_dout_mmc1.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 4),
+               },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_mmc",
+                       .devname        = "s3c-sdhci.2",
+                       .parent         = &clk_dout_mmc2.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 8),
+               },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_mmc",
+                       .devname        = "s3c-sdhci.3",
+                       .parent         = &clk_dout_mmc3.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 12),
+               },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+       }, {
+               .clk            = {
+                       .name           = "sclk_dwmmc",
+                       .parent         = &clk_dout_mmc4.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+       }
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+       &clk_mout_apll,
+       &clk_sclk_apll,
+       &clk_mout_epll,
+       &clk_mout_mpll,
+       &clk_moutcore,
+       &clk_coreclk,
+       &clk_armclk,
+       &clk_aclk_corem0,
+       &clk_aclk_cores,
+       &clk_aclk_corem1,
+       &clk_periphclk,
+       &clk_mout_corebus,
+       &clk_sclk_dmc,
+       &clk_aclk_cored,
+       &clk_aclk_corep,
+       &clk_aclk_acp,
+       &clk_pclk_acp,
+       &clk_vpllsrc,
+       &clk_sclk_vpll,
+       &clk_aclk_200,
+       &clk_aclk_100,
+       &clk_aclk_160,
+       &clk_aclk_133,
+       &clk_dout_mmc0,
+       &clk_dout_mmc1,
+       &clk_dout_mmc2,
+       &clk_dout_mmc3,
+       &clk_dout_mmc4,
+       &clk_mout_mfc0,
+       &clk_mout_mfc1,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+       if (soc_is_exynos4210())
+               return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+                                       pll_4508);
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+       else
+               return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+       .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 vpll_div[][8] = {
+       {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+       { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned int vpll_con0, vpll_con1 = 0;
+       unsigned int i;
+
+       /* Return if nothing changed */
+       if (clk->rate == rate)
+               return 0;
+
+       vpll_con0 = __raw_readl(S5P_VPLL_CON0);
+       vpll_con0 &= ~(0x1 << 27 |                                      \
+                       PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                       PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                       PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+       vpll_con1 = __raw_readl(S5P_VPLL_CON1);
+       vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                       PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                       PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
+               if (vpll_div[i][0] == rate) {
+                       vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                       vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                       vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                       vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                       vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                       vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                       vpll_con0 |= vpll_div[i][7] << 27;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(vpll_div)) {
+               printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                               __func__);
+               return -EINVAL;
+       }
+
+       __raw_writel(vpll_con0, S5P_VPLL_CON0);
+       __raw_writel(vpll_con1, S5P_VPLL_CON1);
+
+       /* Wait for VPLL lock */
+       while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+               continue;
+
+       clk->rate = rate;
+       return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+       .get_rate = exynos4_vpll_get_rate,
+       .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+       struct clk *xtal_clk;
+       unsigned long apll = 0;
+       unsigned long mpll = 0;
+       unsigned long epll = 0;
+       unsigned long vpll = 0;
+       unsigned long vpllsrc;
+       unsigned long xtal;
+       unsigned long armclk;
+       unsigned long sclk_dmc;
+       unsigned long aclk_200;
+       unsigned long aclk_100;
+       unsigned long aclk_160;
+       unsigned long aclk_133;
+       unsigned int ptr;
+
+       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+       xtal_clk = clk_get(NULL, "xtal");
+       BUG_ON(IS_ERR(xtal_clk));
+
+       xtal = clk_get_rate(xtal_clk);
+
+       xtal_rate = xtal;
+
+       clk_put(xtal_clk);
+
+       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+       if (soc_is_exynos4210()) {
+               apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+                                       pll_4508);
+               mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+                                       pll_4508);
+               epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                       __raw_readl(S5P_EPLL_CON1), pll_4600);
+
+               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+               vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                       __raw_readl(S5P_VPLL_CON1), pll_4650c);
+       } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+               apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+               mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+               epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                       __raw_readl(S5P_EPLL_CON1));
+
+               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+               vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                       __raw_readl(S5P_VPLL_CON1));
+       } else {
+               /* nothing */
+       }
+
+       clk_fout_apll.ops = &exynos4_fout_apll_ops;
+       clk_fout_mpll.rate = mpll;
+       clk_fout_epll.rate = epll;
+       clk_fout_vpll.ops = &exynos4_vpll_ops;
+       clk_fout_vpll.rate = vpll;
+
+       printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                       apll, mpll, epll, vpll);
+
+       armclk = clk_get_rate(&clk_armclk.clk);
+       sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
+
+       aclk_200 = clk_get_rate(&clk_aclk_200.clk);
+       aclk_100 = clk_get_rate(&clk_aclk_100.clk);
+       aclk_160 = clk_get_rate(&clk_aclk_160.clk);
+       aclk_133 = clk_get_rate(&clk_aclk_133.clk);
+
+       printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                        "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                       armclk, sclk_dmc, aclk_200,
+                       aclk_100, aclk_160, aclk_133);
+
+       clk_f.rate = armclk;
+       clk_h.rate = sclk_dmc;
+       clk_p.rate = aclk_100;
+
+       for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+               s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+static struct clk *clks[] __initdata = {
+       &clk_sclk_hdmi27m,
+       &clk_sclk_hdmiphy,
+       &clk_sclk_usbphy0,
+       &clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+       s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+       return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+       s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+       .suspend        = exynos4_clock_suspend,
+       .resume         = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+       int ptr;
+
+       s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+               s3c_register_clksrc(sysclks[ptr], 1);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
+               s3c_register_clksrc(sclk_tv[ptr], 1);
+
+       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+       s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+       register_syscore_ops(&exynos4_clock_syscore_ops);
+       s3c24xx_register_clock(&dummy_apb_pclk);
+
+       s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
new file mode 100644 (file)
index 0000000..90ec247
--- /dev/null
@@ -0,0 +1,298 @@
+/* linux/arch/arm/mach-exynos/cpu.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/proc-fns.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/adc-core.h>
+#include <plat/sdhci.h>
+#include <plat/fb-core.h>
+#include <plat/fimc-core.h>
+#include <plat/iic-core.h>
+#include <plat/reset.h>
+#include <plat/tv-core.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-pmu.h>
+
+unsigned int gic_bank_offset __read_mostly;
+
+extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
+                        unsigned int irq_start);
+extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+
+/* Initial IO mappings */
+static struct map_desc exynos_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_COMBINER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(S3C_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
+               .length         = SZ_8K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_L2CC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO1,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO2,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO3,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
+               .length         = SZ_256,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_DMC0,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos4_iodesc0[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos4_iodesc1[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static void exynos_idle(void)
+{
+       if (!need_resched())
+               cpu_do_idle();
+
+       local_irq_enable();
+}
+
+static void exynos4_sw_reset(void)
+{
+       __raw_writel(0x1, S5P_SWRESET);
+}
+
+/*
+ * exynos_map_io
+ *
+ * register the standard cpu IO areas
+ */
+void __init exynos4_map_io(void)
+{
+       iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+       iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+
+       if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+               iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+       else
+               iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+
+       /* initialize device information early */
+       exynos4_default_sdhci0();
+       exynos4_default_sdhci1();
+       exynos4_default_sdhci2();
+       exynos4_default_sdhci3();
+
+       s3c_adc_setname("samsung-adc-v3");
+
+       s3c_fimc_setname(0, "exynos4-fimc");
+       s3c_fimc_setname(1, "exynos4-fimc");
+       s3c_fimc_setname(2, "exynos4-fimc");
+       s3c_fimc_setname(3, "exynos4-fimc");
+
+       /* The I2C bus controllers are directly compatible with s3c2440 */
+       s3c_i2c0_setname("s3c2440-i2c");
+       s3c_i2c1_setname("s3c2440-i2c");
+       s3c_i2c2_setname("s3c2440-i2c");
+
+       s5p_fb_setname(0, "exynos4-fb");
+       s5p_hdmi_setname("exynos4-hdmi");
+}
+
+void __init exynos4_init_clocks(int xtal)
+{
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+
+       if (soc_is_exynos4210())
+               exynos4210_register_clocks();
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               exynos4212_register_clocks();
+
+       exynos4_register_clocks();
+       exynos4_setup_clocks();
+}
+
+static void exynos4_gic_irq_fix_base(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+
+       gic_data->cpu_base = S5P_VA_GIC_CPU +
+                           (gic_bank_offset * smp_processor_id());
+
+       gic_data->dist_base = S5P_VA_GIC_DIST +
+                           (gic_bank_offset * smp_processor_id());
+}
+
+void __init exynos4_init_irq(void)
+{
+       int irq;
+
+       gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+
+       gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+       gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
+       gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
+       gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
+
+       for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+
+               combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                               COMBINER_IRQ(irq, 0));
+               combiner_cascade_irq(irq, IRQ_SPI(irq));
+       }
+
+       /* The parameters of s5p_init_irq() are for VIC init.
+        * Theses parameters should be NULL and 0 because EXYNOS4
+        * uses GIC instead of VIC.
+        */
+       s5p_init_irq(NULL, 0);
+}
+
+struct sysdev_class exynos4_sysclass = {
+       .name   = "exynos4-core",
+};
+
+static struct sys_device exynos4_sysdev = {
+       .cls    = &exynos4_sysclass,
+};
+
+static int __init exynos4_core_init(void)
+{
+       return sysdev_class_register(&exynos4_sysclass);
+}
+core_initcall(exynos4_core_init);
+
+#ifdef CONFIG_CACHE_L2X0
+static int __init exynos4_l2x0_cache_init(void)
+{
+       /* TAG, Data Latency Control: 2cycle */
+       __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+
+       if (soc_is_exynos4210())
+               __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+       /* L2X0 Prefetch Control */
+       __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+       /* L2X0 Power Control */
+       __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+                    S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+
+       return 0;
+}
+
+early_initcall(exynos4_l2x0_cache_init);
+#endif
+
+int __init exynos_init(void)
+{
+       printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+
+       /* set idle function */
+       pm_idle = exynos_idle;
+
+       /* set sw_reset function */
+       if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+               s5p_reset_hook = exynos4_sw_reset;
+
+       return sysdev_register(&exynos4_sysdev);
+}
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
new file mode 100644 (file)
index 0000000..bf7e96f
--- /dev/null
@@ -0,0 +1,86 @@
+/* linux/arch/arm/mach-exynos4/cpuidle.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+
+#include <asm/proc-fns.h>
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+                             struct cpuidle_state *state);
+
+static struct cpuidle_state exynos4_cpuidle_set[] = {
+       [0] = {
+               .enter                  = exynos4_enter_idle,
+               .exit_latency           = 1,
+               .target_residency       = 100000,
+               .flags                  = CPUIDLE_FLAG_TIME_VALID,
+               .name                   = "IDLE",
+               .desc                   = "ARM clock gating(WFI)",
+       },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
+
+static struct cpuidle_driver exynos4_idle_driver = {
+       .name           = "exynos4_idle",
+       .owner          = THIS_MODULE,
+};
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+                             struct cpuidle_state *state)
+{
+       struct timeval before, after;
+       int idle_time;
+
+       local_irq_disable();
+       do_gettimeofday(&before);
+
+       cpu_do_idle();
+
+       do_gettimeofday(&after);
+       local_irq_enable();
+       idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                   (after.tv_usec - before.tv_usec);
+
+       return idle_time;
+}
+
+static int __init exynos4_init_cpuidle(void)
+{
+       int i, max_cpuidle_state, cpu_id;
+       struct cpuidle_device *device;
+
+       cpuidle_register_driver(&exynos4_idle_driver);
+
+       for_each_cpu(cpu_id, cpu_online_mask) {
+               device = &per_cpu(exynos4_cpuidle_device, cpu_id);
+               device->cpu = cpu_id;
+
+               device->state_count = (sizeof(exynos4_cpuidle_set) /
+                                              sizeof(struct cpuidle_state));
+
+               max_cpuidle_state = device->state_count;
+
+               for (i = 0; i < max_cpuidle_state; i++) {
+                       memcpy(&device->states[i], &exynos4_cpuidle_set[i],
+                                       sizeof(struct cpuidle_state));
+               }
+
+               if (cpuidle_register_device(device)) {
+                       printk(KERN_ERR "CPUidle register device failed\n,");
+                       return -EIO;
+               }
+       }
+       return 0;
+}
+device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
new file mode 100644 (file)
index 0000000..f57a3de
--- /dev/null
@@ -0,0 +1,263 @@
+/* linux/arch/arm/mach-exynos4/dev-ahci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - AHCI support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+
+#include <plat/cpu.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+
+/* PHY Control Register */
+#define SATA_CTRL0             0x0
+/* PHY Link Control Register */
+#define SATA_CTRL1             0x4
+/* PHY Status Register */
+#define SATA_PHY_STATUS                0x8
+
+#define SATA_CTRL0_RX_DATA_VALID(x)    (x << 27)
+#define SATA_CTRL0_SPEED_MODE          (1 << 26)
+#define SATA_CTRL0_M_PHY_CAL           (1 << 19)
+#define SATA_CTRL0_PHY_CMU_RST_N       (1 << 10)
+#define SATA_CTRL0_M_PHY_LN_RST_N      (1 << 9)
+#define SATA_CTRL0_PHY_POR_N           (1 << 8)
+
+#define SATA_CTRL1_RST_PMALIVE_N       (1 << 8)
+#define SATA_CTRL1_RST_RXOOB_N         (1 << 7)
+#define SATA_CTRL1_RST_RX_N            (1 << 6)
+#define SATA_CTRL1_RST_TX_N            (1 << 5)
+
+#define SATA_PHY_STATUS_CMU_OK         (1 << 18)
+#define SATA_PHY_STATUS_LANE_OK                (1 << 16)
+
+#define LANE0          0x200
+#define COM_LANE       0xA00
+
+#define HOST_PORTS_IMPL        0xC
+#define SCLK_SATA_FREQ (67 * MHZ)
+
+static void __iomem *phy_base, *phy_ctrl;
+
+struct phy_reg {
+       u8      reg;
+       u8      val;
+};
+
+/* SATA PHY setup */
+static const struct phy_reg exynos4_sataphy_cmu[] = {
+       { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
+       { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
+       { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
+       { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
+       { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
+       { 0x6b, 0xc8 }, { 0x6c, 0x06 },
+};
+
+static const struct phy_reg exynos4_sataphy_lane[] = {
+       { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
+       { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
+       { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
+       { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
+       { 0x51, 0x0f },
+};
+
+static const struct phy_reg exynos4_sataphy_comlane[] = {
+       { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
+       { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
+       { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
+       { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
+       { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
+       { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
+       { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
+       { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
+       { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
+       { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
+       { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
+       { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
+       { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
+       { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
+};
+
+static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
+{
+       unsigned long timeout;
+
+       /* wait for maximum of 3 sec */
+       timeout = jiffies + msecs_to_jiffies(3000);
+       while (!(__raw_readl(reg) & bit)) {
+               if (time_after(jiffies, timeout))
+                       return -1;
+               cpu_relax();
+       }
+       return 0;
+}
+
+static int ahci_phy_init(void __iomem *mmio)
+{
+       int i, ctrl0;
+
+       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
+               __raw_writeb(exynos4_sataphy_cmu[i].val,
+               phy_base + (exynos4_sataphy_cmu[i].reg * 4));
+
+       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
+               __raw_writeb(exynos4_sataphy_lane[i].val,
+               phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
+
+       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
+               __raw_writeb(exynos4_sataphy_comlane[i].val,
+               phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
+
+       __raw_writeb(0x07, phy_base);
+
+       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+       ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
+       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+       if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+                               SATA_PHY_STATUS_CMU_OK) < 0) {
+               printk(KERN_ERR "PHY CMU not ready\n");
+               return -EBUSY;
+       }
+
+       __raw_writeb(0x03, phy_base + (COM_LANE * 4));
+
+       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+       ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
+       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+       if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+                               SATA_PHY_STATUS_LANE_OK) < 0) {
+               printk(KERN_ERR "PHY LANE not ready\n");
+               return -EBUSY;
+       }
+
+       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+       ctrl0 |= SATA_CTRL0_M_PHY_CAL;
+       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+       return 0;
+}
+
+static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
+{
+       struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
+       int val, ret;
+
+       phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
+       if (!phy_base) {
+               dev_err(dev, "failed to allocate memory for SATA PHY\n");
+               return -ENOMEM;
+       }
+
+       phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
+       if (!phy_ctrl) {
+               dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
+               ret = -ENOMEM;
+               goto err1;
+       }
+
+       clk_sata = clk_get(dev, "sata");
+       if (IS_ERR(clk_sata)) {
+               dev_err(dev, "failed to get sata clock\n");
+               ret = PTR_ERR(clk_sata);
+               clk_sata = NULL;
+               goto err2;
+
+       }
+       clk_enable(clk_sata);
+
+       clk_sataphy = clk_get(dev, "sataphy");
+       if (IS_ERR(clk_sataphy)) {
+               dev_err(dev, "failed to get sataphy clock\n");
+               ret = PTR_ERR(clk_sataphy);
+               clk_sataphy = NULL;
+               goto err3;
+       }
+       clk_enable(clk_sataphy);
+
+       clk_sclk_sata = clk_get(dev, "sclk_sata");
+       if (IS_ERR(clk_sclk_sata)) {
+               dev_err(dev, "failed to get sclk_sata\n");
+               ret = PTR_ERR(clk_sclk_sata);
+               clk_sclk_sata = NULL;
+               goto err4;
+       }
+       clk_enable(clk_sclk_sata);
+       clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
+
+       __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
+
+       /* Enable PHY link control */
+       val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
+                       SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
+       __raw_writel(val, phy_ctrl + SATA_CTRL1);
+
+       /* Set communication speed as 3Gbps and enable PHY power */
+       val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
+                       SATA_CTRL0_PHY_POR_N;
+       __raw_writel(val, phy_ctrl + SATA_CTRL0);
+
+       /* Port0 is available */
+       __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
+
+       return ahci_phy_init(mmio);
+
+err4:
+       clk_disable(clk_sataphy);
+       clk_put(clk_sataphy);
+err3:
+       clk_disable(clk_sata);
+       clk_put(clk_sata);
+err2:
+       iounmap(phy_ctrl);
+err1:
+       iounmap(phy_base);
+
+       return ret;
+}
+
+static struct ahci_platform_data exynos4_ahci_pdata = {
+       .init = exynos4_ahci_init,
+};
+
+static struct resource exynos4_ahci_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_SATA,
+               .end    = EXYNOS4_PA_SATA + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_SATA,
+               .end    = IRQ_SATA,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_ahci = {
+       .name           = "ahci",
+       .id             = -1,
+       .resource       = exynos4_ahci_resource,
+       .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
+       .dev            = {
+               .platform_data          = &exynos4_ahci_pdata,
+               .dma_mask               = &exynos4_ahci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
new file mode 100644 (file)
index 0000000..5a9f9c2
--- /dev/null
@@ -0,0 +1,369 @@
+/* linux/arch/arm/mach-exynos4/dev-audio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+#include <mach/regs-audss.h>
+
+static const char *rclksrc[] = {
+       [0] = "busclk",
+       [1] = "i2sclk",
+};
+
+static int exynos4_cfg_i2s(struct platform_device *pdev)
+{
+       /* configure GPIO for i2s port */
+       switch (pdev->id) {
+       case 0:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
+               break;
+       case 1:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
+               break;
+       case 2:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
+               break;
+       default:
+               printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct s3c_audio_pdata i2sv5_pdata = {
+       .cfg_gpio = exynos4_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
+                                        | QUIRK_NEED_RSTCLR,
+                       .src_clk = rclksrc,
+                       .idma_addr = EXYNOS4_AUDSS_INT_MEM,
+               },
+       },
+};
+
+static struct resource exynos4_i2s0_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_I2S0,
+               .end    = EXYNOS4_PA_I2S0 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S0_TX,
+               .end    = DMACH_I2S0_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S0_RX,
+               .end    = DMACH_I2S0_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [3] = {
+               .start  = DMACH_I2S0S_TX,
+               .end    = DMACH_I2S0S_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_i2s0 = {
+       .name = "samsung-i2s",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
+       .resource = exynos4_i2s0_resource,
+       .dev = {
+               .platform_data = &i2sv5_pdata,
+       },
+};
+
+static const char *rclksrc_v3[] = {
+       [0] = "sclk_i2s",
+       [1] = "no_such_clock",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = exynos4_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_NO_MUXPSR,
+                       .src_clk = rclksrc_v3,
+               },
+       },
+};
+
+static struct resource exynos4_i2s1_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_I2S1,
+               .end    = EXYNOS4_PA_I2S1 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S1_TX,
+               .end    = DMACH_I2S1_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S1_RX,
+               .end    = DMACH_I2S1_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_i2s1 = {
+       .name = "samsung-i2s",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
+       .resource = exynos4_i2s1_resource,
+       .dev = {
+               .platform_data = &i2sv3_pdata,
+       },
+};
+
+static struct resource exynos4_i2s2_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_I2S2,
+               .end    = EXYNOS4_PA_I2S2 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S2_TX,
+               .end    = DMACH_I2S2_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S2_RX,
+               .end    = DMACH_I2S2_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_i2s2 = {
+       .name = "samsung-i2s",
+       .id = 2,
+       .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
+       .resource = exynos4_i2s2_resource,
+       .dev = {
+               .platform_data = &i2sv3_pdata,
+       },
+};
+
+/* PCM Controller platform_devices */
+
+static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
+{
+       switch (pdev->id) {
+       case 0:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
+               break;
+       case 1:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
+               break;
+       case 2:
+               s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
+               break;
+       default:
+               printk(KERN_DEBUG "Invalid PCM Controller number!");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+       .cfg_gpio = exynos4_pcm_cfg_gpio,
+};
+
+static struct resource exynos4_pcm0_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_PCM0,
+               .end    = EXYNOS4_PA_PCM0 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM0_TX,
+               .end    = DMACH_PCM0_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM0_RX,
+               .end    = DMACH_PCM0_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_pcm0 = {
+       .name = "samsung-pcm",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
+       .resource = exynos4_pcm0_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+static struct resource exynos4_pcm1_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_PCM1,
+               .end    = EXYNOS4_PA_PCM1 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM1_TX,
+               .end    = DMACH_PCM1_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM1_RX,
+               .end    = DMACH_PCM1_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_pcm1 = {
+       .name = "samsung-pcm",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
+       .resource = exynos4_pcm1_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+static struct resource exynos4_pcm2_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_PCM2,
+               .end    = EXYNOS4_PA_PCM2 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM2_TX,
+               .end    = DMACH_PCM2_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM2_RX,
+               .end    = DMACH_PCM2_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device exynos4_device_pcm2 = {
+       .name = "samsung-pcm",
+       .id = 2,
+       .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
+       .resource = exynos4_pcm2_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+/* AC97 Controller platform devices */
+
+static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
+{
+       return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
+}
+
+static struct resource exynos4_ac97_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_AC97,
+               .end    = EXYNOS4_PA_AC97 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_AC97_PCMOUT,
+               .end    = DMACH_AC97_PCMOUT,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_AC97_PCMIN,
+               .end    = DMACH_AC97_PCMIN,
+               .flags  = IORESOURCE_DMA,
+       },
+       [3] = {
+               .start  = DMACH_AC97_MICIN,
+               .end    = DMACH_AC97_MICIN,
+               .flags  = IORESOURCE_DMA,
+       },
+       [4] = {
+               .start  = IRQ_AC97,
+               .end    = IRQ_AC97,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct s3c_audio_pdata s3c_ac97_pdata = {
+       .cfg_gpio = exynos4_ac97_cfg_gpio,
+};
+
+static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_ac97 = {
+       .name = "samsung-ac97",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
+       .resource = exynos4_ac97_resource,
+       .dev = {
+               .platform_data = &s3c_ac97_pdata,
+               .dma_mask = &exynos4_ac97_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+       },
+};
+
+/* S/PDIF Controller platform_device */
+
+static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
+{
+       s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
+
+       return 0;
+}
+
+static struct resource exynos4_spdif_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_SPDIF,
+               .end    = EXYNOS4_PA_SPDIF + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_SPDIF,
+               .end    = DMACH_SPDIF,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+static struct s3c_audio_pdata samsung_spdif_pdata = {
+       .cfg_gpio = exynos4_spdif_cfg_gpio,
+};
+
+static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_spdif = {
+       .name = "samsung-spdif",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
+       .resource = exynos4_spdif_resource,
+       .dev = {
+               .platform_data = &samsung_spdif_pdata,
+               .dma_mask = &exynos4_spdif_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+       },
+};
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
new file mode 100644 (file)
index 0000000..b025db4
--- /dev/null
@@ -0,0 +1,82 @@
+/*
+ * linux/arch/arm/mach-exynos4/dev-dwmci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Platform device for Synopsys DesignWare Mobile Storage IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/dw_mmc.h>
+
+#include <plat/devs.h>
+
+#include <mach/map.h>
+
+static int exynos4_dwmci_get_bus_wd(u32 slot_id)
+{
+       return 4;
+}
+
+static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
+{
+       return 0;
+}
+
+static struct resource exynos4_dwmci_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_DWMCI,
+               .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_DWMCI,
+               .end    = IRQ_DWMCI,
+               .flags  = IORESOURCE_IRQ,
+       }
+};
+
+static struct dw_mci_board exynos4_dwci_pdata = {
+       .num_slots                      = 1,
+       .quirks                         = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+       .bus_hz                         = 80 * 1000 * 1000,
+       .detect_delay_ms        = 200,
+       .init                           = exynos4_dwmci_init,
+       .get_bus_wd                     = exynos4_dwmci_get_bus_wd,
+};
+
+static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_dwmci = {
+       .name           = "dw_mmc",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(exynos4_dwmci_resource),
+       .resource       = exynos4_dwmci_resource,
+       .dev            = {
+               .dma_mask               = &exynos4_dwmci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+               .platform_data  = &exynos4_dwci_pdata,
+       },
+};
+
+void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
+{
+       struct dw_mci_board *npd;
+
+       npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+                       &exynos4_device_dwmci);
+
+       if (!npd->init)
+               npd->init = exynos4_dwmci_init;
+       if (!npd->get_bus_wd)
+               npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
+}
diff --git a/arch/arm/mach-exynos/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
new file mode 100644 (file)
index 0000000..3273f25
--- /dev/null
@@ -0,0 +1,139 @@
+/* linux/arch/arm/mach-exynos4/dev-pd.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Power Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/regs-pmu.h>
+
+#include <plat/pd.h>
+
+static int exynos4_pd_enable(struct device *dev)
+{
+       struct samsung_pd_info *pdata =  dev->platform_data;
+       u32 timeout;
+
+       __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
+
+       /* Wait max 1ms */
+       timeout = 10;
+       while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
+               != S5P_INT_LOCAL_PWR_EN) {
+               if (timeout == 0) {
+                       printk(KERN_ERR "Power domain %s enable failed.\n",
+                               dev_name(dev));
+                       return -ETIMEDOUT;
+               }
+               timeout--;
+               udelay(100);
+       }
+
+       return 0;
+}
+
+static int exynos4_pd_disable(struct device *dev)
+{
+       struct samsung_pd_info *pdata =  dev->platform_data;
+       u32 timeout;
+
+       __raw_writel(0, pdata->base);
+
+       /* Wait max 1ms */
+       timeout = 10;
+       while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
+               if (timeout == 0) {
+                       printk(KERN_ERR "Power domain %s disable failed.\n",
+                               dev_name(dev));
+                       return -ETIMEDOUT;
+               }
+               timeout--;
+               udelay(100);
+       }
+
+       return 0;
+}
+
+struct platform_device exynos4_device_pd[] = {
+       {
+               .name           = "samsung-pd",
+               .id             = 0,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_MFC_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 1,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_G3D_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 2,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_LCD0_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 3,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_LCD1_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 4,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_TV_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 5,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_CAM_CONF,
+                       },
+               },
+       }, {
+               .name           = "samsung-pd",
+               .id             = 6,
+               .dev = {
+                       .platform_data = &(struct samsung_pd_info) {
+                               .enable         = exynos4_pd_enable,
+                               .disable        = exynos4_pd_disable,
+                               .base           = S5P_PMU_GPS_CONF,
+                       },
+               },
+       },
+};
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
new file mode 100644 (file)
index 0000000..3b7cae0
--- /dev/null
@@ -0,0 +1,232 @@
+/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - System MMU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/sysmmu.h>
+#include <plat/s5p-clock.h>
+
+/* These names must be equal to the clock names in mach-exynos4/clock.c */
+const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
+       "SYSMMU_MDMA"   ,
+       "SYSMMU_SSS"    ,
+       "SYSMMU_FIMC0"  ,
+       "SYSMMU_FIMC1"  ,
+       "SYSMMU_FIMC2"  ,
+       "SYSMMU_FIMC3"  ,
+       "SYSMMU_JPEG"   ,
+       "SYSMMU_FIMD0"  ,
+       "SYSMMU_FIMD1"  ,
+       "SYSMMU_PCIe"   ,
+       "SYSMMU_G2D"    ,
+       "SYSMMU_ROTATOR",
+       "SYSMMU_MDMA2"  ,
+       "SYSMMU_TV"     ,
+       "SYSMMU_MFC_L"  ,
+       "SYSMMU_MFC_R"  ,
+};
+
+static struct resource exynos4_sysmmu_resource[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_SYSMMU_MDMA,
+               .end    = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_SYSMMU_MDMA0_0,
+               .end    = IRQ_SYSMMU_MDMA0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = EXYNOS4_PA_SYSMMU_SSS,
+               .end    = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [3] = {
+               .start  = IRQ_SYSMMU_SSS_0,
+               .end    = IRQ_SYSMMU_SSS_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [4] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMC0,
+               .end    = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [5] = {
+               .start  = IRQ_SYSMMU_FIMC0_0,
+               .end    = IRQ_SYSMMU_FIMC0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [6] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMC1,
+               .end    = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [7] = {
+               .start  = IRQ_SYSMMU_FIMC1_0,
+               .end    = IRQ_SYSMMU_FIMC1_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [8] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMC2,
+               .end    = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [9] = {
+               .start  = IRQ_SYSMMU_FIMC2_0,
+               .end    = IRQ_SYSMMU_FIMC2_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [10] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMC3,
+               .end    = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [11] = {
+               .start  = IRQ_SYSMMU_FIMC3_0,
+               .end    = IRQ_SYSMMU_FIMC3_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [12] = {
+               .start  = EXYNOS4_PA_SYSMMU_JPEG,
+               .end    = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [13] = {
+               .start  = IRQ_SYSMMU_JPEG_0,
+               .end    = IRQ_SYSMMU_JPEG_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [14] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMD0,
+               .end    = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [15] = {
+               .start  = IRQ_SYSMMU_LCD0_M0_0,
+               .end    = IRQ_SYSMMU_LCD0_M0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [16] = {
+               .start  = EXYNOS4_PA_SYSMMU_FIMD1,
+               .end    = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [17] = {
+               .start  = IRQ_SYSMMU_LCD1_M1_0,
+               .end    = IRQ_SYSMMU_LCD1_M1_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [18] = {
+               .start  = EXYNOS4_PA_SYSMMU_PCIe,
+               .end    = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [19] = {
+               .start  = IRQ_SYSMMU_PCIE_0,
+               .end    = IRQ_SYSMMU_PCIE_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [20] = {
+               .start  = EXYNOS4_PA_SYSMMU_G2D,
+               .end    = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [21] = {
+               .start  = IRQ_SYSMMU_2D_0,
+               .end    = IRQ_SYSMMU_2D_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [22] = {
+               .start  = EXYNOS4_PA_SYSMMU_ROTATOR,
+               .end    = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [23] = {
+               .start  = IRQ_SYSMMU_ROTATOR_0,
+               .end    = IRQ_SYSMMU_ROTATOR_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [24] = {
+               .start  = EXYNOS4_PA_SYSMMU_MDMA2,
+               .end    = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [25] = {
+               .start  = IRQ_SYSMMU_MDMA1_0,
+               .end    = IRQ_SYSMMU_MDMA1_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [26] = {
+               .start  = EXYNOS4_PA_SYSMMU_TV,
+               .end    = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [27] = {
+               .start  = IRQ_SYSMMU_TV_M0_0,
+               .end    = IRQ_SYSMMU_TV_M0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [28] = {
+               .start  = EXYNOS4_PA_SYSMMU_MFC_L,
+               .end    = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [29] = {
+               .start  = IRQ_SYSMMU_MFC_M0_0,
+               .end    = IRQ_SYSMMU_MFC_M0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [30] = {
+               .start  = EXYNOS4_PA_SYSMMU_MFC_R,
+               .end    = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [31] = {
+               .start  = IRQ_SYSMMU_MFC_M1_0,
+               .end    = IRQ_SYSMMU_MFC_M1_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device exynos4_device_sysmmu = {
+       .name           = "s5p-sysmmu",
+       .id             = 32,
+       .num_resources  = ARRAY_SIZE(exynos4_sysmmu_resource),
+       .resource       = exynos4_sysmmu_resource,
+};
+EXPORT_SYMBOL(exynos4_device_sysmmu);
+
+static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
+void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
+{
+       sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
+       if (IS_ERR(sysmmu_clk[ips]))
+               sysmmu_clk[ips] = NULL;
+       else
+               clk_put(sysmmu_clk[ips]);
+}
+
+void sysmmu_clk_enable(sysmmu_ips ips)
+{
+       if (sysmmu_clk[ips])
+               clk_enable(sysmmu_clk[ips]);
+}
+
+void sysmmu_clk_disable(sysmmu_ips ips)
+{
+       if (sysmmu_clk[ips])
+               clk_disable(sysmmu_clk[ips]);
+}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
new file mode 100644 (file)
index 0000000..9667c61
--- /dev/null
@@ -0,0 +1,250 @@
+/* linux/arch/arm/mach-exynos4/dma.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl330.h>
+
+#include <asm/irq.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/dma.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+struct dma_pl330_peri pdma0_peri[28] = {
+       {
+               .peri_id = (u8)DMACH_PCM0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_PCM0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_PCM2_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_PCM2_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_MSM_REQ0,
+       }, {
+               .peri_id = (u8)DMACH_MSM_REQ2,
+       }, {
+               .peri_id = (u8)DMACH_SPI0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SPI0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SPI2_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SPI2_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_I2S0S_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_I2S0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_I2S0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART2_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART2_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART4_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART4_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS2_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS2_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS4_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS4_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_AC97_MICIN,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_AC97_PCMIN,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_AC97_PCMOUT,
+               .rqtype = MEMTODEV,
+       },
+};
+
+struct dma_pl330_platdata exynos4_pdma0_pdata = {
+       .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
+       .peri = pdma0_peri,
+};
+
+struct amba_device exynos4_device_pdma0 = {
+       .dev = {
+               .init_name = "dma-pl330.0",
+               .dma_mask = &dma_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+               .platform_data = &exynos4_pdma0_pdata,
+       },
+       .res = {
+               .start = EXYNOS4_PA_PDMA0,
+               .end = EXYNOS4_PA_PDMA0 + SZ_4K,
+               .flags = IORESOURCE_MEM,
+       },
+       .irq = {IRQ_PDMA0, NO_IRQ},
+       .periphid = 0x00041330,
+};
+
+struct dma_pl330_peri pdma1_peri[25] = {
+       {
+               .peri_id = (u8)DMACH_PCM0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_PCM0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_PCM1_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_PCM1_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_MSM_REQ1,
+       }, {
+               .peri_id = (u8)DMACH_MSM_REQ3,
+       }, {
+               .peri_id = (u8)DMACH_SPI1_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SPI1_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_I2S0S_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_I2S0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_I2S0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_I2S1_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_I2S1_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART0_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART0_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART1_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART1_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_UART3_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_UART3_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS1_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS1_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS3_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS3_TX,
+               .rqtype = MEMTODEV,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS5_RX,
+               .rqtype = DEVTOMEM,
+       }, {
+               .peri_id = (u8)DMACH_SLIMBUS5_TX,
+               .rqtype = MEMTODEV,
+       },
+};
+
+struct dma_pl330_platdata exynos4_pdma1_pdata = {
+       .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
+       .peri = pdma1_peri,
+};
+
+struct amba_device exynos4_device_pdma1 = {
+       .dev = {
+               .init_name = "dma-pl330.1",
+               .dma_mask = &dma_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+               .platform_data = &exynos4_pdma1_pdata,
+       },
+       .res = {
+               .start = EXYNOS4_PA_PDMA1,
+               .end = EXYNOS4_PA_PDMA1 + SZ_4K,
+               .flags = IORESOURCE_MEM,
+       },
+       .irq = {IRQ_PDMA1, NO_IRQ},
+       .periphid = 0x00041330,
+};
+
+static int __init exynos4_dma_init(void)
+{
+       amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+       amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+
+       return 0;
+}
+arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
new file mode 100644 (file)
index 0000000..3cdeb36
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ *  linux/arch/arm/mach-exynos4/headsmp.S
+ *
+ *  Cloned from linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+       __CPUINIT
+
+/*
+ * exynos4 specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(exynos4_secondary_startup)
+       mrc     p15, 0, r0, c0, c0, 5
+       and     r0, r0, #15
+       adr     r4, 1f
+       ldmia   r4, {r5, r6}
+       sub     r4, r4, r5
+       add     r6, r6, r4
+pen:   ldr     r7, [r6]
+       cmp     r7, r0
+       bne     pen
+
+       /*
+        * we've been released from the holding pen: secondary_stack
+        * should now contain the SVC stack for this core
+        */
+       b       secondary_startup
+
+1:     .long   .
+       .long   pen_release
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
new file mode 100644 (file)
index 0000000..da70e7e
--- /dev/null
@@ -0,0 +1,133 @@
+/* linux arch/arm/mach-exynos4/hotplug.c
+ *
+ *  Cloned from linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/regs-pmu.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+       unsigned int v;
+
+       flush_cache_all();
+       asm volatile(
+       "       mcr     p15, 0, %1, c7, c5, 0\n"
+       "       mcr     p15, 0, %1, c7, c10, 4\n"
+       /*
+        * Turn off coherency
+        */
+       "       mrc     p15, 0, %0, c1, c0, 1\n"
+       "       bic     %0, %0, %3\n"
+       "       mcr     p15, 0, %0, c1, c0, 1\n"
+       "       mrc     p15, 0, %0, c1, c0, 0\n"
+       "       bic     %0, %0, %2\n"
+       "       mcr     p15, 0, %0, c1, c0, 0\n"
+         : "=&r" (v)
+         : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+         : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+       unsigned int v;
+
+       asm volatile(
+       "mrc    p15, 0, %0, c1, c0, 0\n"
+       "       orr     %0, %0, %1\n"
+       "       mcr     p15, 0, %0, c1, c0, 0\n"
+       "       mrc     p15, 0, %0, c1, c0, 1\n"
+       "       orr     %0, %0, %2\n"
+       "       mcr     p15, 0, %0, c1, c0, 1\n"
+         : "=&r" (v)
+         : "Ir" (CR_C), "Ir" (0x40)
+         : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+       for (;;) {
+
+               /* make cpu1 to be turned off at next WFI command */
+               if (cpu == 1)
+                       __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+
+               /*
+                * here's the WFI
+                */
+               asm(".word      0xe320f003\n"
+                   :
+                   :
+                   : "memory", "cc");
+
+               if (pen_release == cpu_logical_map(cpu)) {
+                       /*
+                        * OK, proper wakeup, we're done
+                        */
+                       break;
+               }
+
+               /*
+                * Getting here, means that we have come out of WFI without
+                * having been woken up - this shouldn't happen
+                *
+                * Just note it happening - when we're woken, we can report
+                * its occurrence.
+                */
+               (*spurious)++;
+       }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+       return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+       int spurious = 0;
+
+       /*
+        * we're ready for shutdown now, so do it
+        */
+       cpu_enter_lowpower();
+       platform_do_lowpower(cpu, &spurious);
+
+       /*
+        * bring this CPU back into the world of cache
+        * coherency, and then restore interrupts
+        */
+       cpu_leave_lowpower();
+
+       if (spurious)
+               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+       /*
+        * we don't allow CPU 0 to be shutdown (it is still too special
+        * e.g. clock tick interrupts)
+        */
+       return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
new file mode 100644 (file)
index 0000000..6cacf16
--- /dev/null
@@ -0,0 +1,35 @@
+/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+
+       /* note, for the boot process to work we have to keep the UART
+        * virtual address aligned to an 1MiB boundary for the L1
+        * mapping the head code makes. We keep the UART virtual address
+        * aligned and add in the offset when we load the value here.
+        */
+
+       .macro addruart, rp, rv, tmp
+               ldr     \rp, = S3C_PA_UART
+               ldr     \rv, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+               add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+               add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+#endif
+       .endm
+
+#define fifo_full fifo_full_s5pv210
+#define fifo_level fifo_level_s5pv210
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-exynos/include/mach/dma.h b/arch/arm/mach-exynos/include/mach/dma.h
new file mode 100644 (file)
index 0000000..201842a
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos/include/mach/dwmci.h b/arch/arm/mach-exynos/include/mach/dwmci.h
new file mode 100644 (file)
index 0000000..7ce6574
--- /dev/null
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * Synopsys DesignWare Mobile Storage for EXYNOS4210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_DWMCI_H
+#define __ASM_ARM_ARCH_DWMCI_H __FILE__
+
+#include <linux/mmc/dw_mmc.h>
+
+extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
+
+#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
new file mode 100644 (file)
index 0000000..f5e9fd8
--- /dev/null
@@ -0,0 +1,91 @@
+/* arch/arm/mach-exynos4/include/mach/entry-macro.S
+ *
+ * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for EXYNOS4 platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/hardware/gic.h>
+
+               .macro  disable_fiq
+               .endm
+
+               .macro  get_irqnr_preamble, base, tmp
+               mov     \tmp, #0
+
+               mrc     p15, 0, \base, c0, c0, 5
+               and     \base, \base, #3
+               cmp     \base, #0
+               beq     1f
+
+               ldr     \tmp, =gic_bank_offset
+               ldr     \tmp, [\tmp]
+               cmp     \base, #1
+               beq     1f
+
+               cmp     \base, #2
+               addeq   \tmp, \tmp, \tmp
+               addne   \tmp, \tmp, \tmp, LSL #1
+
+1:             ldr     \base, =gic_cpu_base_addr
+               ldr     \base, [\base]
+               add     \base, \base, \tmp
+               .endm
+
+               .macro  arch_ret_to_user, tmp1, tmp2
+               .endm
+
+               /*
+                * The interrupt numbering scheme is defined in the
+                * interrupt controller spec.  To wit:
+                *
+                * Interrupts 0-15 are IPI
+                * 16-28 are reserved
+                * 29-31 are local.  We allow 30 to be used for the watchdog.
+                * 32-1020 are global
+                * 1021-1022 are reserved
+                * 1023 is "spurious" (no interrupt)
+                *
+                * For now, we ignore all local interrupts so only return an interrupt if it's
+                * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                *
+                * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                * valid range for an IRQ (30-1020 inclusive).
+                */
+
+               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+               ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+
+               ldr     \tmp, =1021
+
+               bic     \irqnr, \irqstat, #0x1c00
+
+               cmp     \irqnr, #15
+               cmpcc   \irqnr, \irqnr
+               cmpne   \irqnr, \tmp
+               cmpcs   \irqnr, \irqnr
+               addne   \irqnr, \irqnr, #32
+
+               .endm
+
+               /* We assume that irqstat (the raw value of the IRQ acknowledge
+                * register) is preserved from the macro above.
+                * If there is an IPI, we immediately signal end of interrupt on the
+                * controller, since this requires the original irqstat value which
+                * we won't easily be able to recreate later.
+                */
+
+               .macro test_for_ipi, irqnr, irqstat, base, tmp
+               bic     \irqnr, \irqstat, #0x1c00
+               cmp     \irqnr, #16
+               strcc   \irqstat, [\base, #GIC_CPU_EOI]
+               cmpcs   \irqnr, \irqnr
+               .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
new file mode 100644 (file)
index 0000000..a07fcbf
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clk clk_sclk_hdmi27m;
+extern struct clk clk_sclk_usbphy0;
+extern struct clk clk_sclk_usbphy1;
+extern struct clk clk_sclk_hdmiphy;
+
+extern struct clksrc_clk clk_sclk_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk clk_mout_epll;
+extern struct clksrc_clk clk_sclk_vpll;
+
+extern struct clk *clkset_corebus_list[];
+extern struct clksrc_sources clkset_mout_corebus;
+
+extern struct clk *clkset_aclk_top_list[];
+extern struct clksrc_sources clkset_aclk;
+
+extern struct clk *clkset_group_list[];
+extern struct clksrc_sources clkset_group;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
new file mode 100644 (file)
index 0000000..80523ca
--- /dev/null
@@ -0,0 +1,149 @@
+/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
+
+/* GPIO bank sizes */
+#define EXYNOS4_GPIO_A0_NR     (8)
+#define EXYNOS4_GPIO_A1_NR     (6)
+#define EXYNOS4_GPIO_B_NR      (8)
+#define EXYNOS4_GPIO_C0_NR     (5)
+#define EXYNOS4_GPIO_C1_NR     (5)
+#define EXYNOS4_GPIO_D0_NR     (4)
+#define EXYNOS4_GPIO_D1_NR     (4)
+#define EXYNOS4_GPIO_E0_NR     (5)
+#define EXYNOS4_GPIO_E1_NR     (8)
+#define EXYNOS4_GPIO_E2_NR     (6)
+#define EXYNOS4_GPIO_E3_NR     (8)
+#define EXYNOS4_GPIO_E4_NR     (8)
+#define EXYNOS4_GPIO_F0_NR     (8)
+#define EXYNOS4_GPIO_F1_NR     (8)
+#define EXYNOS4_GPIO_F2_NR     (8)
+#define EXYNOS4_GPIO_F3_NR     (6)
+#define EXYNOS4_GPIO_J0_NR     (8)
+#define EXYNOS4_GPIO_J1_NR     (5)
+#define EXYNOS4_GPIO_K0_NR     (7)
+#define EXYNOS4_GPIO_K1_NR     (7)
+#define EXYNOS4_GPIO_K2_NR     (7)
+#define EXYNOS4_GPIO_K3_NR     (7)
+#define EXYNOS4_GPIO_L0_NR     (8)
+#define EXYNOS4_GPIO_L1_NR     (3)
+#define EXYNOS4_GPIO_L2_NR     (8)
+#define EXYNOS4_GPIO_X0_NR     (8)
+#define EXYNOS4_GPIO_X1_NR     (8)
+#define EXYNOS4_GPIO_X2_NR     (8)
+#define EXYNOS4_GPIO_X3_NR     (8)
+#define EXYNOS4_GPIO_Y0_NR     (6)
+#define EXYNOS4_GPIO_Y1_NR     (4)
+#define EXYNOS4_GPIO_Y2_NR     (6)
+#define EXYNOS4_GPIO_Y3_NR     (8)
+#define EXYNOS4_GPIO_Y4_NR     (8)
+#define EXYNOS4_GPIO_Y5_NR     (8)
+#define EXYNOS4_GPIO_Y6_NR     (8)
+#define EXYNOS4_GPIO_Z_NR      (7)
+
+/* GPIO bank numbers */
+
+#define EXYNOS4_GPIO_NEXT(__gpio) \
+       ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p_gpio_number {
+       EXYNOS4_GPIO_A0_START   = 0,
+       EXYNOS4_GPIO_A1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
+       EXYNOS4_GPIO_B_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
+       EXYNOS4_GPIO_C0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
+       EXYNOS4_GPIO_C1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
+       EXYNOS4_GPIO_D0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
+       EXYNOS4_GPIO_D1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
+       EXYNOS4_GPIO_E0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
+       EXYNOS4_GPIO_E1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
+       EXYNOS4_GPIO_E2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
+       EXYNOS4_GPIO_E3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
+       EXYNOS4_GPIO_E4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
+       EXYNOS4_GPIO_F0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
+       EXYNOS4_GPIO_F1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
+       EXYNOS4_GPIO_F2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
+       EXYNOS4_GPIO_F3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
+       EXYNOS4_GPIO_J0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
+       EXYNOS4_GPIO_J1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
+       EXYNOS4_GPIO_K0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
+       EXYNOS4_GPIO_K1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
+       EXYNOS4_GPIO_K2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
+       EXYNOS4_GPIO_K3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
+       EXYNOS4_GPIO_L0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
+       EXYNOS4_GPIO_L1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
+       EXYNOS4_GPIO_L2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
+       EXYNOS4_GPIO_X0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
+       EXYNOS4_GPIO_X1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
+       EXYNOS4_GPIO_X2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
+       EXYNOS4_GPIO_X3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
+       EXYNOS4_GPIO_Y0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
+       EXYNOS4_GPIO_Y1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
+       EXYNOS4_GPIO_Y2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
+       EXYNOS4_GPIO_Y3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
+       EXYNOS4_GPIO_Y4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
+       EXYNOS4_GPIO_Y5_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
+       EXYNOS4_GPIO_Y6_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
+       EXYNOS4_GPIO_Z_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
+};
+
+/* EXYNOS4 GPIO number definitions */
+#define EXYNOS4_GPA0(_nr)      (EXYNOS4_GPIO_A0_START + (_nr))
+#define EXYNOS4_GPA1(_nr)      (EXYNOS4_GPIO_A1_START + (_nr))
+#define EXYNOS4_GPB(_nr)       (EXYNOS4_GPIO_B_START + (_nr))
+#define EXYNOS4_GPC0(_nr)      (EXYNOS4_GPIO_C0_START + (_nr))
+#define EXYNOS4_GPC1(_nr)      (EXYNOS4_GPIO_C1_START + (_nr))
+#define EXYNOS4_GPD0(_nr)      (EXYNOS4_GPIO_D0_START + (_nr))
+#define EXYNOS4_GPD1(_nr)      (EXYNOS4_GPIO_D1_START + (_nr))
+#define EXYNOS4_GPE0(_nr)      (EXYNOS4_GPIO_E0_START + (_nr))
+#define EXYNOS4_GPE1(_nr)      (EXYNOS4_GPIO_E1_START + (_nr))
+#define EXYNOS4_GPE2(_nr)      (EXYNOS4_GPIO_E2_START + (_nr))
+#define EXYNOS4_GPE3(_nr)      (EXYNOS4_GPIO_E3_START + (_nr))
+#define EXYNOS4_GPE4(_nr)      (EXYNOS4_GPIO_E4_START + (_nr))
+#define EXYNOS4_GPF0(_nr)      (EXYNOS4_GPIO_F0_START + (_nr))
+#define EXYNOS4_GPF1(_nr)      (EXYNOS4_GPIO_F1_START + (_nr))
+#define EXYNOS4_GPF2(_nr)      (EXYNOS4_GPIO_F2_START + (_nr))
+#define EXYNOS4_GPF3(_nr)      (EXYNOS4_GPIO_F3_START + (_nr))
+#define EXYNOS4_GPJ0(_nr)      (EXYNOS4_GPIO_J0_START + (_nr))
+#define EXYNOS4_GPJ1(_nr)      (EXYNOS4_GPIO_J1_START + (_nr))
+#define EXYNOS4_GPK0(_nr)      (EXYNOS4_GPIO_K0_START + (_nr))
+#define EXYNOS4_GPK1(_nr)      (EXYNOS4_GPIO_K1_START + (_nr))
+#define EXYNOS4_GPK2(_nr)      (EXYNOS4_GPIO_K2_START + (_nr))
+#define EXYNOS4_GPK3(_nr)      (EXYNOS4_GPIO_K3_START + (_nr))
+#define EXYNOS4_GPL0(_nr)      (EXYNOS4_GPIO_L0_START + (_nr))
+#define EXYNOS4_GPL1(_nr)      (EXYNOS4_GPIO_L1_START + (_nr))
+#define EXYNOS4_GPL2(_nr)      (EXYNOS4_GPIO_L2_START + (_nr))
+#define EXYNOS4_GPX0(_nr)      (EXYNOS4_GPIO_X0_START + (_nr))
+#define EXYNOS4_GPX1(_nr)      (EXYNOS4_GPIO_X1_START + (_nr))
+#define EXYNOS4_GPX2(_nr)      (EXYNOS4_GPIO_X2_START + (_nr))
+#define EXYNOS4_GPX3(_nr)      (EXYNOS4_GPIO_X3_START + (_nr))
+#define EXYNOS4_GPY0(_nr)      (EXYNOS4_GPIO_Y0_START + (_nr))
+#define EXYNOS4_GPY1(_nr)      (EXYNOS4_GPIO_Y1_START + (_nr))
+#define EXYNOS4_GPY2(_nr)      (EXYNOS4_GPIO_Y2_START + (_nr))
+#define EXYNOS4_GPY3(_nr)      (EXYNOS4_GPIO_Y3_START + (_nr))
+#define EXYNOS4_GPY4(_nr)      (EXYNOS4_GPIO_Y4_START + (_nr))
+#define EXYNOS4_GPY5(_nr)      (EXYNOS4_GPIO_Y5_START + (_nr))
+#define EXYNOS4_GPY6(_nr)      (EXYNOS4_GPIO_Y6_START + (_nr))
+#define EXYNOS4_GPZ(_nr)       (EXYNOS4_GPIO_Z_START + (_nr))
+
+/* the end of the EXYNOS4 specific gpios */
+#define EXYNOS4_GPIO_END       (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
+#define S3C_GPIO_END           EXYNOS4_GPIO_END
+
+/* define the number of gpios we need to the one after the GPZ() range */
+#define ARCH_NR_GPIOS          (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +       \
+                                CONFIG_SAMSUNG_GPIO_EXTRA + 1)
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
new file mode 100644 (file)
index 0000000..5109eb2
--- /dev/null
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Hardware support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
new file mode 100644 (file)
index 0000000..d5478d2
--- /dev/null
@@ -0,0 +1,26 @@
+/* linux/arch/arm/mach-exynos4/include/mach/io.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/io.h
+ *
+ * Default IO routines for EXYNOS4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H __FILE__
+
+/* No current ISA/PCI bus support. */
+#define __io(a)                __typesafe_io(a)
+#define __mem_pci(a)   (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
new file mode 100644 (file)
index 0000000..dfd4b7e
--- /dev/null
@@ -0,0 +1,169 @@
+/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#include <plat/irqs.h>
+
+/* PPI: Private Peripheral Interrupt */
+
+#define IRQ_PPI(x)             S5P_IRQ(x+16)
+
+#define IRQ_MCT_LOCALTIMER     IRQ_PPI(12)
+
+/* SPI: Shared Peripheral Interrupt */
+
+#define IRQ_SPI(x)             S5P_IRQ(x+32)
+
+#define IRQ_EINT0              IRQ_SPI(16)
+#define IRQ_EINT1              IRQ_SPI(17)
+#define IRQ_EINT2              IRQ_SPI(18)
+#define IRQ_EINT3              IRQ_SPI(19)
+#define IRQ_EINT4              IRQ_SPI(20)
+#define IRQ_EINT5              IRQ_SPI(21)
+#define IRQ_EINT6              IRQ_SPI(22)
+#define IRQ_EINT7              IRQ_SPI(23)
+#define IRQ_EINT8              IRQ_SPI(24)
+#define IRQ_EINT9              IRQ_SPI(25)
+#define IRQ_EINT10             IRQ_SPI(26)
+#define IRQ_EINT11             IRQ_SPI(27)
+#define IRQ_EINT12             IRQ_SPI(28)
+#define IRQ_EINT13             IRQ_SPI(29)
+#define IRQ_EINT14             IRQ_SPI(30)
+#define IRQ_EINT15             IRQ_SPI(31)
+#define IRQ_EINT16_31          IRQ_SPI(32)
+
+#define IRQ_PDMA0              IRQ_SPI(35)
+#define IRQ_PDMA1              IRQ_SPI(36)
+#define IRQ_TIMER0_VIC         IRQ_SPI(37)
+#define IRQ_TIMER1_VIC         IRQ_SPI(38)
+#define IRQ_TIMER2_VIC         IRQ_SPI(39)
+#define IRQ_TIMER3_VIC         IRQ_SPI(40)
+#define IRQ_TIMER4_VIC         IRQ_SPI(41)
+#define IRQ_MCT_L0             IRQ_SPI(42)
+#define IRQ_WDT                        IRQ_SPI(43)
+#define IRQ_RTC_ALARM          IRQ_SPI(44)
+#define IRQ_RTC_TIC            IRQ_SPI(45)
+#define IRQ_GPIO_XB            IRQ_SPI(46)
+#define IRQ_GPIO_XA            IRQ_SPI(47)
+#define IRQ_MCT_L1             IRQ_SPI(48)
+
+#define IRQ_UART0              IRQ_SPI(52)
+#define IRQ_UART1              IRQ_SPI(53)
+#define IRQ_UART2              IRQ_SPI(54)
+#define IRQ_UART3              IRQ_SPI(55)
+#define IRQ_UART4              IRQ_SPI(56)
+#define IRQ_MCT_G0             IRQ_SPI(57)
+#define IRQ_IIC                        IRQ_SPI(58)
+#define IRQ_IIC1               IRQ_SPI(59)
+#define IRQ_IIC2               IRQ_SPI(60)
+#define IRQ_IIC3               IRQ_SPI(61)
+#define IRQ_IIC4               IRQ_SPI(62)
+#define IRQ_IIC5               IRQ_SPI(63)
+#define IRQ_IIC6               IRQ_SPI(64)
+#define IRQ_IIC7               IRQ_SPI(65)
+
+#define IRQ_USB_HOST           IRQ_SPI(70)
+#define IRQ_USB_HSOTG          IRQ_SPI(71)
+#define IRQ_MODEM_IF           IRQ_SPI(72)
+#define IRQ_HSMMC0             IRQ_SPI(73)
+#define IRQ_HSMMC1             IRQ_SPI(74)
+#define IRQ_HSMMC2             IRQ_SPI(75)
+#define IRQ_HSMMC3             IRQ_SPI(76)
+#define IRQ_DWMCI              IRQ_SPI(77)
+
+#define IRQ_MIPI_CSIS0         IRQ_SPI(78)
+#define IRQ_MIPI_CSIS1         IRQ_SPI(80)
+
+#define IRQ_ONENAND_AUDI       IRQ_SPI(82)
+#define IRQ_ROTATOR            IRQ_SPI(83)
+#define IRQ_FIMC0              IRQ_SPI(84)
+#define IRQ_FIMC1              IRQ_SPI(85)
+#define IRQ_FIMC2              IRQ_SPI(86)
+#define IRQ_FIMC3              IRQ_SPI(87)
+#define IRQ_JPEG               IRQ_SPI(88)
+#define IRQ_2D                 IRQ_SPI(89)
+#define IRQ_PCIE               IRQ_SPI(90)
+
+#define IRQ_MIXER              IRQ_SPI(91)
+#define IRQ_HDMI               IRQ_SPI(92)
+#define IRQ_IIC_HDMIPHY                IRQ_SPI(93)
+#define IRQ_MFC                        IRQ_SPI(94)
+#define IRQ_SDO                        IRQ_SPI(95)
+
+#define IRQ_AUDIO_SS           IRQ_SPI(96)
+#define IRQ_I2S0               IRQ_SPI(97)
+#define IRQ_I2S1               IRQ_SPI(98)
+#define IRQ_I2S2               IRQ_SPI(99)
+#define IRQ_AC97               IRQ_SPI(100)
+
+#define IRQ_SPDIF              IRQ_SPI(104)
+#define IRQ_ADC0               IRQ_SPI(105)
+#define IRQ_PEN0               IRQ_SPI(106)
+#define IRQ_ADC1               IRQ_SPI(107)
+#define IRQ_PEN1               IRQ_SPI(108)
+#define IRQ_KEYPAD             IRQ_SPI(109)
+#define IRQ_PMU                        IRQ_SPI(110)
+#define IRQ_GPS                        IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
+#define IRQ_SLIMBUS            IRQ_SPI(113)
+
+#define IRQ_TSI                        IRQ_SPI(115)
+#define IRQ_SATA               IRQ_SPI(116)
+
+#define MAX_IRQ_IN_COMBINER    8
+#define COMBINER_GROUP(x)      ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)     (COMBINER_GROUP(x) + y)
+
+#define IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
+#define IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
+#define IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
+#define IRQ_SYSMMU_FIMC1_0     COMBINER_IRQ(4, 3)
+#define IRQ_SYSMMU_FIMC2_0     COMBINER_IRQ(4, 4)
+#define IRQ_SYSMMU_FIMC3_0     COMBINER_IRQ(4, 5)
+#define IRQ_SYSMMU_JPEG_0      COMBINER_IRQ(4, 6)
+#define IRQ_SYSMMU_2D_0                COMBINER_IRQ(4, 7)
+
+#define IRQ_SYSMMU_ROTATOR_0   COMBINER_IRQ(5, 0)
+#define IRQ_SYSMMU_MDMA1_0     COMBINER_IRQ(5, 1)
+#define IRQ_SYSMMU_LCD0_M0_0   COMBINER_IRQ(5, 2)
+#define IRQ_SYSMMU_LCD1_M1_0   COMBINER_IRQ(5, 3)
+#define IRQ_SYSMMU_TV_M0_0     COMBINER_IRQ(5, 4)
+#define IRQ_SYSMMU_MFC_M0_0    COMBINER_IRQ(5, 5)
+#define IRQ_SYSMMU_MFC_M1_0    COMBINER_IRQ(5, 6)
+#define IRQ_SYSMMU_PCIE_0      COMBINER_IRQ(5, 7)
+
+#define IRQ_FIMD0_FIFO         COMBINER_IRQ(11, 0)
+#define IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
+#define IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
+
+#define MAX_COMBINER_NR                16
+
+#define IRQ_ADC                        IRQ_ADC0
+#define IRQ_TC                 IRQ_PEN0
+
+#define S5P_IRQ_EINT_BASE      COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1         (S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2         (S5P_IRQ_EINT_BASE + 16)
+
+/* optional GPIO interrupts */
+#define S5P_GPIOINT_BASE       (S5P_IRQ_EINT_BASE + 32)
+#define IRQ_GPIO1_NR_GROUPS    16
+#define IRQ_GPIO2_NR_GROUPS    9
+#define IRQ_GPIO_END           (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+
+/* Set the default NR_IRQS */
+#define NR_IRQS                        (IRQ_GPIO_END + 64)
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
new file mode 100644 (file)
index 0000000..058541d
--- /dev/null
@@ -0,0 +1,197 @@
+/* linux/arch/arm/mach-exynos/include/mach/map.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * EXYNOS4 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET                        (0x10000)
+
+#include <plat/map-s5p.h>
+
+#define EXYNOS4_PA_SYSRAM0             0x02025000
+#define EXYNOS4_PA_SYSRAM1             0x02020000
+
+#define EXYNOS4_PA_FIMC0               0x11800000
+#define EXYNOS4_PA_FIMC1               0x11810000
+#define EXYNOS4_PA_FIMC2               0x11820000
+#define EXYNOS4_PA_FIMC3               0x11830000
+
+#define EXYNOS4_PA_I2S0                        0x03830000
+#define EXYNOS4_PA_I2S1                        0xE3100000
+#define EXYNOS4_PA_I2S2                        0xE2A00000
+
+#define EXYNOS4_PA_PCM0                        0x03840000
+#define EXYNOS4_PA_PCM1                        0x13980000
+#define EXYNOS4_PA_PCM2                        0x13990000
+
+#define EXYNOS4_PA_SROM_BANK(x)                (0x04000000 + ((x) * 0x01000000))
+
+#define EXYNOS4_PA_ONENAND             0x0C000000
+#define EXYNOS4_PA_ONENAND_DMA         0x0C600000
+
+#define EXYNOS4_PA_CHIPID              0x10000000
+
+#define EXYNOS4_PA_SYSCON              0x10010000
+#define EXYNOS4_PA_PMU                 0x10020000
+#define EXYNOS4_PA_CMU                 0x10030000
+
+#define EXYNOS4_PA_SYSTIMER            0x10050000
+#define EXYNOS4_PA_WATCHDOG            0x10060000
+#define EXYNOS4_PA_RTC                 0x10070000
+
+#define EXYNOS4_PA_KEYPAD              0x100A0000
+
+#define EXYNOS4_PA_DMC0                        0x10400000
+
+#define EXYNOS4_PA_COMBINER            0x10440000
+
+#define EXYNOS4_PA_GIC_CPU             0x10480000
+#define EXYNOS4_PA_GIC_DIST            0x10490000
+
+#define EXYNOS4_PA_COREPERI            0x10500000
+#define EXYNOS4_PA_TWD                 0x10500600
+#define EXYNOS4_PA_L2CC                        0x10502000
+
+#define EXYNOS4_PA_MDMA                        0x10810000
+#define EXYNOS4_PA_PDMA0               0x12680000
+#define EXYNOS4_PA_PDMA1               0x12690000
+
+#define EXYNOS4_PA_SYSMMU_MDMA         0x10A40000
+#define EXYNOS4_PA_SYSMMU_SSS          0x10A50000
+#define EXYNOS4_PA_SYSMMU_FIMC0                0x11A20000
+#define EXYNOS4_PA_SYSMMU_FIMC1                0x11A30000
+#define EXYNOS4_PA_SYSMMU_FIMC2                0x11A40000
+#define EXYNOS4_PA_SYSMMU_FIMC3                0x11A50000
+#define EXYNOS4_PA_SYSMMU_JPEG         0x11A60000
+#define EXYNOS4_PA_SYSMMU_FIMD0                0x11E20000
+#define EXYNOS4_PA_SYSMMU_FIMD1                0x12220000
+#define EXYNOS4_PA_SYSMMU_PCIe         0x12620000
+#define EXYNOS4_PA_SYSMMU_G2D          0x12A20000
+#define EXYNOS4_PA_SYSMMU_ROTATOR      0x12A30000
+#define EXYNOS4_PA_SYSMMU_MDMA2                0x12A40000
+#define EXYNOS4_PA_SYSMMU_TV           0x12E20000
+#define EXYNOS4_PA_SYSMMU_MFC_L                0x13620000
+#define EXYNOS4_PA_SYSMMU_MFC_R                0x13630000
+
+#define EXYNOS4_PA_GPIO1               0x11400000
+#define EXYNOS4_PA_GPIO2               0x11000000
+#define EXYNOS4_PA_GPIO3               0x03860000
+
+#define EXYNOS4_PA_MIPI_CSIS0          0x11880000
+#define EXYNOS4_PA_MIPI_CSIS1          0x11890000
+
+#define EXYNOS4_PA_FIMD0               0x11C00000
+
+#define EXYNOS4_PA_HSMMC(x)            (0x12510000 + ((x) * 0x10000))
+#define EXYNOS4_PA_DWMCI               0x12550000
+
+#define EXYNOS4_PA_SATA                        0x12560000
+#define EXYNOS4_PA_SATAPHY             0x125D0000
+#define EXYNOS4_PA_SATAPHY_CTRL                0x126B0000
+
+#define EXYNOS4_PA_SROMC               0x12570000
+
+#define EXYNOS4_PA_EHCI                        0x12580000
+#define EXYNOS4_PA_HSPHY               0x125B0000
+#define EXYNOS4_PA_MFC                 0x13400000
+
+#define EXYNOS4_PA_UART                        0x13800000
+
+#define EXYNOS4_PA_VP                  0x12C00000
+#define EXYNOS4_PA_MIXER               0x12C10000
+#define EXYNOS4_PA_SDO                 0x12C20000
+#define EXYNOS4_PA_HDMI                        0x12D00000
+#define EXYNOS4_PA_IIC_HDMIPHY         0x138E0000
+
+#define EXYNOS4_PA_IIC(x)              (0x13860000 + ((x) * 0x10000))
+
+#define EXYNOS4_PA_ADC                 0x13910000
+#define EXYNOS4_PA_ADC1                        0x13911000
+
+#define EXYNOS4_PA_AC97                        0x139A0000
+
+#define EXYNOS4_PA_SPDIF               0x139B0000
+
+#define EXYNOS4_PA_TIMER               0x139D0000
+
+#define EXYNOS4_PA_SDRAM               0x40000000
+
+/* Compatibiltiy Defines */
+
+#define S3C_PA_HSMMC0                  EXYNOS4_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                  EXYNOS4_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                  EXYNOS4_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                  EXYNOS4_PA_HSMMC(3)
+#define S3C_PA_IIC                     EXYNOS4_PA_IIC(0)
+#define S3C_PA_IIC1                    EXYNOS4_PA_IIC(1)
+#define S3C_PA_IIC2                    EXYNOS4_PA_IIC(2)
+#define S3C_PA_IIC3                    EXYNOS4_PA_IIC(3)
+#define S3C_PA_IIC4                    EXYNOS4_PA_IIC(4)
+#define S3C_PA_IIC5                    EXYNOS4_PA_IIC(5)
+#define S3C_PA_IIC6                    EXYNOS4_PA_IIC(6)
+#define S3C_PA_IIC7                    EXYNOS4_PA_IIC(7)
+#define S3C_PA_RTC                     EXYNOS4_PA_RTC
+#define S3C_PA_WDT                     EXYNOS4_PA_WATCHDOG
+#define S3C_PA_UART                    EXYNOS4_PA_UART
+
+#define S5P_PA_CHIPID                  EXYNOS4_PA_CHIPID
+#define S5P_PA_EHCI                    EXYNOS4_PA_EHCI
+#define S5P_PA_FIMC0                   EXYNOS4_PA_FIMC0
+#define S5P_PA_FIMC1                   EXYNOS4_PA_FIMC1
+#define S5P_PA_FIMC2                   EXYNOS4_PA_FIMC2
+#define S5P_PA_FIMC3                   EXYNOS4_PA_FIMC3
+#define S5P_PA_FIMD0                   EXYNOS4_PA_FIMD0
+#define S5P_PA_HDMI                    EXYNOS4_PA_HDMI
+#define S5P_PA_IIC_HDMIPHY             EXYNOS4_PA_IIC_HDMIPHY
+#define S5P_PA_MFC                     EXYNOS4_PA_MFC
+#define S5P_PA_MIPI_CSIS0              EXYNOS4_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1              EXYNOS4_PA_MIPI_CSIS1
+#define S5P_PA_MIXER                   EXYNOS4_PA_MIXER
+#define S5P_PA_ONENAND                 EXYNOS4_PA_ONENAND
+#define S5P_PA_ONENAND_DMA             EXYNOS4_PA_ONENAND_DMA
+#define S5P_PA_SDO                     EXYNOS4_PA_SDO
+#define S5P_PA_SDRAM                   EXYNOS4_PA_SDRAM
+#define S5P_PA_SROMC                   EXYNOS4_PA_SROMC
+#define S5P_PA_SYSCON                  EXYNOS4_PA_SYSCON
+#define S5P_PA_TIMER                   EXYNOS4_PA_TIMER
+#define S5P_PA_VP                      EXYNOS4_PA_VP
+
+#define SAMSUNG_PA_ADC                 EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1                        EXYNOS4_PA_ADC1
+#define SAMSUNG_PA_KEYPAD              EXYNOS4_PA_KEYPAD
+
+#define EXYNOS_PA_COMBINER             EXYNOS4_PA_COMBINER
+#define EXYNOS_PA_GIC_CPU              EXYNOS4_PA_GIC_CPU
+#define EXYNOS_PA_GIC_DIST             EXYNOS4_PA_GIC_DIST
+#define EXYNOS_PA_PMU                  EXYNOS4_PA_PMU
+#define EXYNOS_PA_SYSTIMER             EXYNOS4_PA_SYSTIMER
+
+/* Compatibility UART */
+
+#define S3C_VA_UARTx(x)                        (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
+#define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                   S5P_PA_UART(0)
+#define S5P_PA_UART1                   S5P_PA_UART(1)
+#define S5P_PA_UART2                   S5P_PA_UART(2)
+#define S5P_PA_UART3                   S5P_PA_UART(3)
+#define S5P_PA_UART4                   S5P_PA_UART(4)
+
+#define S5P_SZ_UART                    SZ_256
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
new file mode 100644 (file)
index 0000000..374ef2c
--- /dev/null
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos4/include/mach/memory.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Memory definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
+
+#define PLAT_PHYS_OFFSET               UL(0x40000000)
+
+/* Maximum of 256MiB in one bank */
+#define MAX_PHYSMEM_BITS       32
+#define SECTION_SIZE_BITS      28
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
new file mode 100644 (file)
index 0000000..9d8da51
--- /dev/null
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PM_CORE_H
+#define __ASM_ARCH_PM_CORE_H __FILE__
+
+#include <mach/regs-pmu.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+       /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+       unsigned int tmp;
+       tmp = __raw_readl(S5P_WAKEUP_MASK);
+       tmp &= ~(1 << 31);
+       __raw_writel(tmp, S5P_WAKEUP_MASK);
+
+       __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
+       __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+       /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+       /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                          struct pm_uart_save *save)
+{
+       /* nothing here yet */
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+       /* nothing here yet */
+}
+
+static inline void samsung_pm_saved_gpios(void)
+{
+       /* nothing here yet */
+}
+
+#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
new file mode 100644 (file)
index 0000000..632dd56
--- /dev/null
@@ -0,0 +1,32 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+#define PMU_TABLE_END  NULL
+
+enum sys_powerdown {
+       SYS_AFTR,
+       SYS_LPA,
+       SYS_SLEEP,
+       NUM_SYS_POWERDOWN,
+};
+
+struct exynos4_pmu_conf {
+       void __iomem *reg;
+       unsigned int val[NUM_SYS_POWERDOWN];
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
new file mode 100644 (file)
index 0000000..ca5a8b6
--- /dev/null
@@ -0,0 +1,18 @@
+/* arch/arm/mach-exynos4/include/mach/regs-audss.h
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *             http://www.samsung.com
+ *
+ * Exynos4 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define EXYNOS4_AUDSS_INT_MEM  (0x03000000)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
new file mode 100644 (file)
index 0000000..6c37ebe
--- /dev/null
@@ -0,0 +1,210 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <plat/cpu.h>
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)                  (S5P_VA_CMU + (x))
+
+#define S5P_CLKDIV_LEFTBUS             S5P_CLKREG(0x04500)
+#define S5P_CLKDIV_STAT_LEFTBUS                S5P_CLKREG(0x04600)
+#define S5P_CLKGATE_IP_LEFTBUS         S5P_CLKREG(0x04800)
+
+#define S5P_CLKDIV_RIGHTBUS            S5P_CLKREG(0x08500)
+#define S5P_CLKDIV_STAT_RIGHTBUS       S5P_CLKREG(0x08600)
+#define S5P_CLKGATE_IP_RIGHTBUS                S5P_CLKREG(0x08800)
+
+#define S5P_EPLL_LOCK                  S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK                  S5P_CLKREG(0x0C020)
+
+#define S5P_EPLL_CON0                  S5P_CLKREG(0x0C110)
+#define S5P_EPLL_CON1                  S5P_CLKREG(0x0C114)
+#define S5P_VPLL_CON0                  S5P_CLKREG(0x0C120)
+#define S5P_VPLL_CON1                  S5P_CLKREG(0x0C124)
+
+#define S5P_CLKSRC_TOP0                        S5P_CLKREG(0x0C210)
+#define S5P_CLKSRC_TOP1                        S5P_CLKREG(0x0C214)
+#define S5P_CLKSRC_CAM                 S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_TV                  S5P_CLKREG(0x0C224)
+#define S5P_CLKSRC_MFC                 S5P_CLKREG(0x0C228)
+#define S5P_CLKSRC_G3D                 S5P_CLKREG(0x0C22C)
+#define S5P_CLKSRC_IMAGE               S5P_CLKREG(0x0C230)
+#define S5P_CLKSRC_LCD0                        S5P_CLKREG(0x0C234)
+#define S5P_CLKSRC_MAUDIO              S5P_CLKREG(0x0C23C)
+#define S5P_CLKSRC_FSYS                        S5P_CLKREG(0x0C240)
+#define S5P_CLKSRC_PERIL0              S5P_CLKREG(0x0C250)
+#define S5P_CLKSRC_PERIL1              S5P_CLKREG(0x0C254)
+
+#define S5P_CLKSRC_MASK_TOP            S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM            S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV             S5P_CLKREG(0x0C324)
+#define S5P_CLKSRC_MASK_LCD0           S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_MAUDIO         S5P_CLKREG(0x0C33C)
+#define S5P_CLKSRC_MASK_FSYS           S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0         S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1         S5P_CLKREG(0x0C354)
+
+#define S5P_CLKDIV_TOP                 S5P_CLKREG(0x0C510)
+#define S5P_CLKDIV_CAM                 S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_TV                  S5P_CLKREG(0x0C524)
+#define S5P_CLKDIV_MFC                 S5P_CLKREG(0x0C528)
+#define S5P_CLKDIV_G3D                 S5P_CLKREG(0x0C52C)
+#define S5P_CLKDIV_IMAGE               S5P_CLKREG(0x0C530)
+#define S5P_CLKDIV_LCD0                        S5P_CLKREG(0x0C534)
+#define S5P_CLKDIV_MAUDIO              S5P_CLKREG(0x0C53C)
+#define S5P_CLKDIV_FSYS0               S5P_CLKREG(0x0C540)
+#define S5P_CLKDIV_FSYS1               S5P_CLKREG(0x0C544)
+#define S5P_CLKDIV_FSYS2               S5P_CLKREG(0x0C548)
+#define S5P_CLKDIV_FSYS3               S5P_CLKREG(0x0C54C)
+#define S5P_CLKDIV_PERIL0              S5P_CLKREG(0x0C550)
+#define S5P_CLKDIV_PERIL1              S5P_CLKREG(0x0C554)
+#define S5P_CLKDIV_PERIL2              S5P_CLKREG(0x0C558)
+#define S5P_CLKDIV_PERIL3              S5P_CLKREG(0x0C55C)
+#define S5P_CLKDIV_PERIL4              S5P_CLKREG(0x0C560)
+#define S5P_CLKDIV_PERIL5              S5P_CLKREG(0x0C564)
+#define S5P_CLKDIV2_RATIO              S5P_CLKREG(0x0C580)
+
+#define S5P_CLKDIV_STAT_TOP            S5P_CLKREG(0x0C610)
+
+#define S5P_CLKGATE_SCLKCAM            S5P_CLKREG(0x0C820)
+#define S5P_CLKGATE_IP_CAM             S5P_CLKREG(0x0C920)
+#define S5P_CLKGATE_IP_TV              S5P_CLKREG(0x0C924)
+#define S5P_CLKGATE_IP_MFC             S5P_CLKREG(0x0C928)
+#define S5P_CLKGATE_IP_G3D             S5P_CLKREG(0x0C92C)
+#define S5P_CLKGATE_IP_IMAGE           (soc_is_exynos4210() ? \
+                                       S5P_CLKREG(0x0C930) : \
+                                       S5P_CLKREG(0x04930))
+#define S5P_CLKGATE_IP_IMAGE_4210      S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE_4212      S5P_CLKREG(0x04930)
+#define S5P_CLKGATE_IP_LCD0            S5P_CLKREG(0x0C934)
+#define S5P_CLKGATE_IP_FSYS            S5P_CLKREG(0x0C940)
+#define S5P_CLKGATE_IP_GPS             S5P_CLKREG(0x0C94C)
+#define S5P_CLKGATE_IP_PERIL           S5P_CLKREG(0x0C950)
+#define S5P_CLKGATE_IP_PERIR           (soc_is_exynos4210() ? \
+                                       S5P_CLKREG(0x0C960) : \
+                                       S5P_CLKREG(0x08960))
+#define S5P_CLKGATE_IP_PERIR_4210      S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR_4212      S5P_CLKREG(0x08960)
+#define S5P_CLKGATE_BLOCK              S5P_CLKREG(0x0C970)
+
+#define S5P_CLKSRC_MASK_DMC            S5P_CLKREG(0x10300)
+#define S5P_CLKSRC_DMC                 S5P_CLKREG(0x10200)
+#define S5P_CLKDIV_DMC0                        S5P_CLKREG(0x10500)
+#define S5P_CLKDIV_DMC1                        S5P_CLKREG(0x10504)
+#define S5P_CLKDIV_STAT_DMC0           S5P_CLKREG(0x10600)
+#define S5P_CLKGATE_IP_DMC             S5P_CLKREG(0x10900)
+
+#define S5P_APLL_LOCK                  S5P_CLKREG(0x14000)
+#define S5P_MPLL_LOCK                  (soc_is_exynos4210() ? \
+                                       S5P_CLKREG(0x14004) :  \
+                                       S5P_CLKREG(0x10008))
+#define S5P_APLL_CON0                  S5P_CLKREG(0x14100)
+#define S5P_APLL_CON1                  S5P_CLKREG(0x14104)
+#define S5P_MPLL_CON0                  (soc_is_exynos4210() ? \
+                                       S5P_CLKREG(0x14108) : \
+                                       S5P_CLKREG(0x10108))
+#define S5P_MPLL_CON1                  (soc_is_exynos4210() ? \
+                                       S5P_CLKREG(0x1410C) : \
+                                       S5P_CLKREG(0x1010C))
+
+#define S5P_CLKSRC_CPU                 S5P_CLKREG(0x14200)
+#define S5P_CLKMUX_STATCPU             S5P_CLKREG(0x14400)
+
+#define S5P_CLKDIV_CPU                 S5P_CLKREG(0x14500)
+#define S5P_CLKDIV_CPU1                        S5P_CLKREG(0x14504)
+#define S5P_CLKDIV_STATCPU             S5P_CLKREG(0x14600)
+#define S5P_CLKDIV_STATCPU1            S5P_CLKREG(0x14604)
+
+#define S5P_CLKGATE_SCLKCPU            S5P_CLKREG(0x14800)
+#define S5P_CLKGATE_IP_CPU             S5P_CLKREG(0x14900)
+
+#define S5P_APLL_LOCKTIME              (0x1C20)        /* 300us */
+
+#define S5P_APLLCON0_ENABLE_SHIFT      (31)
+#define S5P_APLLCON0_LOCKED_SHIFT      (29)
+#define S5P_APLL_VAL_1000              ((250 << 16) | (6 << 8) | 1)
+#define S5P_APLL_VAL_800               ((200 << 16) | (6 << 8) | 1)
+
+#define S5P_EPLLCON0_ENABLE_SHIFT      (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT      (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT      (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT      (29)
+
+#define S5P_CLKSRC_CPU_MUXCORE_SHIFT   (16)
+#define S5P_CLKMUX_STATCPU_MUXCORE_MASK        (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define S5P_CLKDIV_CPU0_CORE_SHIFT     (0)
+#define S5P_CLKDIV_CPU0_CORE_MASK      (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
+#define S5P_CLKDIV_CPU0_COREM0_SHIFT   (4)
+#define S5P_CLKDIV_CPU0_COREM0_MASK    (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
+#define S5P_CLKDIV_CPU0_COREM1_SHIFT   (8)
+#define S5P_CLKDIV_CPU0_COREM1_MASK    (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
+#define S5P_CLKDIV_CPU0_PERIPH_SHIFT   (12)
+#define S5P_CLKDIV_CPU0_PERIPH_MASK    (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
+#define S5P_CLKDIV_CPU0_ATB_SHIFT      (16)
+#define S5P_CLKDIV_CPU0_ATB_MASK       (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
+#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT  (20)
+#define S5P_CLKDIV_CPU0_PCLKDBG_MASK   (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define S5P_CLKDIV_CPU0_APLL_SHIFT     (24)
+#define S5P_CLKDIV_CPU0_APLL_MASK      (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
+
+#define S5P_CLKDIV_DMC0_ACP_SHIFT      (0)
+#define S5P_CLKDIV_DMC0_ACP_MASK       (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
+#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT  (4)
+#define S5P_CLKDIV_DMC0_ACPPCLK_MASK   (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define S5P_CLKDIV_DMC0_DPHY_SHIFT     (8)
+#define S5P_CLKDIV_DMC0_DPHY_MASK      (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
+#define S5P_CLKDIV_DMC0_DMC_SHIFT      (12)
+#define S5P_CLKDIV_DMC0_DMC_MASK       (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
+#define S5P_CLKDIV_DMC0_DMCD_SHIFT     (16)
+#define S5P_CLKDIV_DMC0_DMCD_MASK      (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
+#define S5P_CLKDIV_DMC0_DMCP_SHIFT     (20)
+#define S5P_CLKDIV_DMC0_DMCP_MASK      (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
+#define S5P_CLKDIV_DMC0_COPY2_SHIFT    (24)
+#define S5P_CLKDIV_DMC0_COPY2_MASK     (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
+#define S5P_CLKDIV_DMC0_CORETI_SHIFT   (28)
+#define S5P_CLKDIV_DMC0_CORETI_MASK    (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define S5P_CLKDIV_TOP_ACLK200_SHIFT   (0)
+#define S5P_CLKDIV_TOP_ACLK200_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK100_SHIFT   (4)
+#define S5P_CLKDIV_TOP_ACLK100_MASK    (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK160_SHIFT   (8)
+#define S5P_CLKDIV_TOP_ACLK160_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK133_SHIFT   (12)
+#define S5P_CLKDIV_TOP_ACLK133_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
+#define S5P_CLKDIV_TOP_ONENAND_SHIFT   (16)
+#define S5P_CLKDIV_TOP_ONENAND_MASK    (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
+
+#define S5P_CLKDIV_BUS_GDLR_SHIFT      (0)
+#define S5P_CLKDIV_BUS_GDLR_MASK       (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
+#define S5P_CLKDIV_BUS_GPLR_SHIFT      (4)
+#define S5P_CLKDIV_BUS_GPLR_MASK       (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+
+/* Only for EXYNOS4210 */
+
+#define S5P_CLKSRC_LCD1                        S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MASK_LCD1           S5P_CLKREG(0x0C338)
+#define S5P_CLKDIV_LCD1                        S5P_CLKREG(0x0C538)
+#define S5P_CLKGATE_IP_LCD1            S5P_CLKREG(0x0C938)
+
+/* Compatibility defines and inclusion */
+
+#include <mach/regs-pmu.h>
+
+#define S5P_EPLL_CON                   S5P_EPLL_CON0
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
new file mode 100644 (file)
index 0000000..1401b21
--- /dev/null
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#define EXYNOS4_EINT40CON              (S5P_VA_GPIO2 + 0xE00)
+#define S5P_EINT_CON(x)                        (EXYNOS4_EINT40CON + ((x) * 0x4))
+
+#define EXYNOS4_EINT40FLTCON0          (S5P_VA_GPIO2 + 0xE80)
+#define S5P_EINT_FLTCON(x)             (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
+
+#define EXYNOS4_EINT40MASK             (S5P_VA_GPIO2 + 0xF00)
+#define S5P_EINT_MASK(x)               (EXYNOS4_EINT40MASK + ((x) * 0x4))
+
+#define EXYNOS4_EINT40PEND             (S5P_VA_GPIO2 + 0xF40)
+#define S5P_EINT_PEND(x)               (EXYNOS4_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)                 (EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)           (1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE                      S3C_GPIO_SFN(0xf)
+
+#define EINT_GPIO_0(x)                 EXYNOS4_GPX0(x)
+#define EINT_GPIO_1(x)                 EXYNOS4_GPX1(x)
+#define EINT_GPIO_2(x)                 EXYNOS4_GPX2(x)
+#define EINT_GPIO_3(x)                 EXYNOS4_GPX3(x)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
new file mode 100644 (file)
index 0000000..9c7b4bf
--- /dev/null
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
new file mode 100644 (file)
index 0000000..80dd02a
--- /dev/null
@@ -0,0 +1,53 @@
+/* arch/arm/mach-exynos4/include/mach/regs-mct.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 MCT configutation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MCT_H
+#define __ASM_ARCH_REGS_MCT_H __FILE__
+
+#include <mach/map.h>
+
+#define EXYNOS4_MCTREG(x)              (S5P_VA_SYSTIMER + (x))
+
+#define EXYNOS4_MCT_G_CNT_L            EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U            EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT                EXYNOS4_MCTREG(0x110)
+
+#define EXYNOS4_MCT_G_COMP0_L          EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U          EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR   EXYNOS4_MCTREG(0x208)
+
+#define EXYNOS4_MCT_G_TCON             EXYNOS4_MCTREG(0x240)
+
+#define EXYNOS4_MCT_G_INT_CSTAT                EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB          EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT            EXYNOS4_MCTREG(0x24C)
+
+#define _EXYNOS4_MCT_L_BASE            EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)          (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK             (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET             (0x00)
+#define MCT_L_ICNTB_OFFSET             (0x08)
+#define MCT_L_TCON_OFFSET              (0x20)
+#define MCT_L_INT_CSTAT_OFFSET         (0x30)
+#define MCT_L_INT_ENB_OFFSET           (0x34)
+#define MCT_L_WSTAT_OFFSET             (0x40)
+
+#define MCT_G_TCON_START               (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC      (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE                (1 << 0)
+
+#define MCT_L_TCON_INTERVAL_MODE       (1 << 2)
+#define MCT_L_TCON_INT_START           (1 << 1)
+#define MCT_L_TCON_TIMER_START         (1 << 0)
+
+#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-mem.h b/arch/arm/mach-exynos/include/mach/regs-mem.h
new file mode 100644 (file)
index 0000000..0368b5a
--- /dev/null
@@ -0,0 +1,23 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - SROMC and DMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MEM_H
+#define __ASM_ARCH_REGS_MEM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_DMC0_MEMCON_OFFSET         0x04
+
+#define S5P_DMC0_MEMTYPE_SHIFT         8
+#define S5P_DMC0_MEMTYPE_MASK          0xF
+
+#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
new file mode 100644 (file)
index 0000000..4fff8e9
--- /dev/null
@@ -0,0 +1,220 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_H
+#define __ASM_ARCH_REGS_PMU_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_PMUREG(x)                          (S5P_VA_PMU + (x))
+
+#define S5P_CENTRAL_SEQ_CONFIGURATION          S5P_PMUREG(0x0200)
+
+#define S5P_CENTRAL_LOWPWR_CFG                 (1 << 16)
+
+#define S5P_CENTRAL_SEQ_OPTION                 S5P_PMUREG(0x0208)
+
+#define S5P_USE_STANDBY_WFI0                   (1 << 16)
+#define S5P_USE_STANDBY_WFI1                   (1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM             (1 << 18)
+#define S5P_USE_STANDBY_WFE0                   (1 << 24)
+#define S5P_USE_STANDBY_WFE1                   (1 << 25)
+#define S5P_USE_STANDBYWFE_ISP_ARM             (1 << 26)
+
+#define S5P_SWRESET                            S5P_PMUREG(0x0400)
+
+#define S5P_WAKEUP_STAT                                S5P_PMUREG(0x0600)
+#define S5P_EINT_WAKEUP_MASK                   S5P_PMUREG(0x0604)
+#define S5P_WAKEUP_MASK                                S5P_PMUREG(0x0608)
+
+#define S5P_HDMI_PHY_CONTROL                   S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE                    (1 << 0)
+
+#define S5P_DAC_PHY_CONTROL                    S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE                     (1 << 0)
+
+#define S5P_MIPI_DPHY_CONTROL(n)               S5P_PMUREG(0x0710 + (n) * 4)
+#define S5P_MIPI_DPHY_ENABLE                   (1 << 0)
+#define S5P_MIPI_DPHY_SRESETN                  (1 << 1)
+#define S5P_MIPI_DPHY_MRESETN                  (1 << 2)
+
+#define S5P_INFORM0                            S5P_PMUREG(0x0800)
+#define S5P_INFORM1                            S5P_PMUREG(0x0804)
+#define S5P_INFORM2                            S5P_PMUREG(0x0808)
+#define S5P_INFORM3                            S5P_PMUREG(0x080C)
+#define S5P_INFORM4                            S5P_PMUREG(0x0810)
+#define S5P_INFORM5                            S5P_PMUREG(0x0814)
+#define S5P_INFORM6                            S5P_PMUREG(0x0818)
+#define S5P_INFORM7                            S5P_PMUREG(0x081C)
+
+#define S5P_ARM_CORE0_LOWPWR                   S5P_PMUREG(0x1000)
+#define S5P_DIS_IRQ_CORE0                      S5P_PMUREG(0x1004)
+#define S5P_DIS_IRQ_CENTRAL0                   S5P_PMUREG(0x1008)
+#define S5P_ARM_CORE1_LOWPWR                   S5P_PMUREG(0x1010)
+#define S5P_DIS_IRQ_CORE1                      S5P_PMUREG(0x1014)
+#define S5P_DIS_IRQ_CENTRAL1                   S5P_PMUREG(0x1018)
+#define S5P_ARM_COMMON_LOWPWR                  S5P_PMUREG(0x1080)
+#define S5P_L2_0_LOWPWR                                S5P_PMUREG(0x10C0)
+#define S5P_L2_1_LOWPWR                                S5P_PMUREG(0x10C4)
+#define S5P_CMU_ACLKSTOP_LOWPWR                        S5P_PMUREG(0x1100)
+#define S5P_CMU_SCLKSTOP_LOWPWR                        S5P_PMUREG(0x1104)
+#define S5P_CMU_RESET_LOWPWR                   S5P_PMUREG(0x110C)
+#define S5P_APLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1120)
+#define S5P_MPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1124)
+#define S5P_VPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1128)
+#define S5P_EPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x112C)
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR       S5P_PMUREG(0x1138)
+#define S5P_CMU_RESET_GPSALIVE_LOWPWR          S5P_PMUREG(0x113C)
+#define S5P_CMU_CLKSTOP_CAM_LOWPWR             S5P_PMUREG(0x1140)
+#define S5P_CMU_CLKSTOP_TV_LOWPWR              S5P_PMUREG(0x1144)
+#define S5P_CMU_CLKSTOP_MFC_LOWPWR             S5P_PMUREG(0x1148)
+#define S5P_CMU_CLKSTOP_G3D_LOWPWR             S5P_PMUREG(0x114C)
+#define S5P_CMU_CLKSTOP_LCD0_LOWPWR            S5P_PMUREG(0x1150)
+#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          S5P_PMUREG(0x1158)
+#define S5P_CMU_CLKSTOP_GPS_LOWPWR             S5P_PMUREG(0x115C)
+#define S5P_CMU_RESET_CAM_LOWPWR               S5P_PMUREG(0x1160)
+#define S5P_CMU_RESET_TV_LOWPWR                        S5P_PMUREG(0x1164)
+#define S5P_CMU_RESET_MFC_LOWPWR               S5P_PMUREG(0x1168)
+#define S5P_CMU_RESET_G3D_LOWPWR               S5P_PMUREG(0x116C)
+#define S5P_CMU_RESET_LCD0_LOWPWR              S5P_PMUREG(0x1170)
+#define S5P_CMU_RESET_MAUDIO_LOWPWR            S5P_PMUREG(0x1178)
+#define S5P_CMU_RESET_GPS_LOWPWR               S5P_PMUREG(0x117C)
+#define S5P_TOP_BUS_LOWPWR                     S5P_PMUREG(0x1180)
+#define S5P_TOP_RETENTION_LOWPWR               S5P_PMUREG(0x1184)
+#define S5P_TOP_PWR_LOWPWR                     S5P_PMUREG(0x1188)
+#define S5P_LOGIC_RESET_LOWPWR                 S5P_PMUREG(0x11A0)
+#define S5P_ONENAND_MEM_LOWPWR                 S5P_PMUREG(0x11C0)
+#define S5P_G2D_ACP_MEM_LOWPWR                 S5P_PMUREG(0x11C8)
+#define S5P_USBOTG_MEM_LOWPWR                  S5P_PMUREG(0x11CC)
+#define S5P_HSMMC_MEM_LOWPWR                   S5P_PMUREG(0x11D0)
+#define S5P_CSSYS_MEM_LOWPWR                   S5P_PMUREG(0x11D4)
+#define S5P_SECSS_MEM_LOWPWR                   S5P_PMUREG(0x11D8)
+#define S5P_PAD_RETENTION_DRAM_LOWPWR          S5P_PMUREG(0x1200)
+#define S5P_PAD_RETENTION_MAUDIO_LOWPWR                S5P_PMUREG(0x1204)
+#define S5P_PAD_RETENTION_GPIO_LOWPWR          S5P_PMUREG(0x1220)
+#define S5P_PAD_RETENTION_UART_LOWPWR          S5P_PMUREG(0x1224)
+#define S5P_PAD_RETENTION_MMCA_LOWPWR          S5P_PMUREG(0x1228)
+#define S5P_PAD_RETENTION_MMCB_LOWPWR          S5P_PMUREG(0x122C)
+#define S5P_PAD_RETENTION_EBIA_LOWPWR          S5P_PMUREG(0x1230)
+#define S5P_PAD_RETENTION_EBIB_LOWPWR          S5P_PMUREG(0x1234)
+#define S5P_PAD_RETENTION_ISOLATION_LOWPWR     S5P_PMUREG(0x1240)
+#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR       S5P_PMUREG(0x1260)
+#define S5P_XUSBXTI_LOWPWR                     S5P_PMUREG(0x1280)
+#define S5P_XXTI_LOWPWR                                S5P_PMUREG(0x1284)
+#define S5P_EXT_REGULATOR_LOWPWR               S5P_PMUREG(0x12C0)
+#define S5P_GPIO_MODE_LOWPWR                   S5P_PMUREG(0x1300)
+#define S5P_GPIO_MODE_MAUDIO_LOWPWR            S5P_PMUREG(0x1340)
+#define S5P_CAM_LOWPWR                         S5P_PMUREG(0x1380)
+#define S5P_TV_LOWPWR                          S5P_PMUREG(0x1384)
+#define S5P_MFC_LOWPWR                         S5P_PMUREG(0x1388)
+#define S5P_G3D_LOWPWR                         S5P_PMUREG(0x138C)
+#define S5P_LCD0_LOWPWR                                S5P_PMUREG(0x1390)
+#define S5P_MAUDIO_LOWPWR                      S5P_PMUREG(0x1398)
+#define S5P_GPS_LOWPWR                         S5P_PMUREG(0x139C)
+#define S5P_GPS_ALIVE_LOWPWR                   S5P_PMUREG(0x13A0)
+
+#define S5P_ARM_CORE0_CONFIGURATION            S5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_OPTION                   S5P_PMUREG(0x2008)
+#define S5P_ARM_CORE1_CONFIGURATION            S5P_PMUREG(0x2080)
+#define S5P_ARM_CORE1_STATUS                   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE1_OPTION                   S5P_PMUREG(0x2088)
+
+#define S5P_ARM_COMMON_OPTION                  S5P_PMUREG(0x2408)
+#define S5P_TOP_PWR_OPTION                     S5P_PMUREG(0x2C48)
+#define S5P_CAM_OPTION                         S5P_PMUREG(0x3C08)
+#define S5P_TV_OPTION                          S5P_PMUREG(0x3C28)
+#define S5P_MFC_OPTION                         S5P_PMUREG(0x3C48)
+#define S5P_G3D_OPTION                         S5P_PMUREG(0x3C68)
+#define S5P_LCD0_OPTION                                S5P_PMUREG(0x3C88)
+#define S5P_LCD1_OPTION                                S5P_PMUREG(0x3CA8)
+#define S5P_MAUDIO_OPTION                      S5P_PMUREG(0x3CC8)
+#define S5P_GPS_OPTION                         S5P_PMUREG(0x3CE8)
+#define S5P_GPS_ALIVE_OPTION                   S5P_PMUREG(0x3D08)
+
+#define S5P_PAD_RET_MAUDIO_OPTION              S5P_PMUREG(0x3028)
+#define S5P_PAD_RET_GPIO_OPTION                        S5P_PMUREG(0x3108)
+#define S5P_PAD_RET_UART_OPTION                        S5P_PMUREG(0x3128)
+#define S5P_PAD_RET_MMCA_OPTION                        S5P_PMUREG(0x3148)
+#define S5P_PAD_RET_MMCB_OPTION                        S5P_PMUREG(0x3168)
+#define S5P_PAD_RET_EBIA_OPTION                        S5P_PMUREG(0x3188)
+#define S5P_PAD_RET_EBIB_OPTION                        S5P_PMUREG(0x31A8)
+
+#define S5P_PMU_CAM_CONF                       S5P_PMUREG(0x3C00)
+#define S5P_PMU_TV_CONF                                S5P_PMUREG(0x3C20)
+#define S5P_PMU_MFC_CONF                       S5P_PMUREG(0x3C40)
+#define S5P_PMU_G3D_CONF                       S5P_PMUREG(0x3C60)
+#define S5P_PMU_LCD0_CONF                      S5P_PMUREG(0x3C80)
+#define S5P_PMU_GPS_CONF                       S5P_PMUREG(0x3CE0)
+
+#define S5P_PMU_SATA_PHY_CONTROL_EN            0x1
+#define S5P_CORE_LOCAL_PWR_EN                  0x3
+#define S5P_INT_LOCAL_PWR_EN                   0x7
+
+#define S5P_CHECK_SLEEP                                0x00000BAD
+
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL                S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE         (1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL       S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR    S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR      S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR         S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR            S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR            S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR                        S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF              S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR                     S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR       S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR     S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR           S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR             S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR             S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR               S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR             S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR       S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR             S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR                 S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR         S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR         S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR                     S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR                 S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR  S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR       S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR           S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR               S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR           S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR                         S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR              S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR               S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR              S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR              S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR          S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION                    S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION                    S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION                 S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION                     S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION                 S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION                  S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION                   S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION                   S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION                   S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION                 S5P_PMUREG(0x2F48)
+
+#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
new file mode 100644 (file)
index 0000000..68ff6ad
--- /dev/null
@@ -0,0 +1,28 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - System MMU register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SYSMMU_H
+#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
+
+#define S5P_MMU_CTRL                   0x000
+#define S5P_MMU_CFG                    0x004
+#define S5P_MMU_STATUS                 0x008
+#define S5P_MMU_FLUSH                  0x00C
+#define S5P_PT_BASE_ADDR               0x014
+#define S5P_INT_STATUS                 0x018
+#define S5P_INT_CLEAR                  0x01C
+#define S5P_PAGE_FAULT_ADDR            0x024
+#define S5P_AW_FAULT_ADDR              0x028
+#define S5P_AR_FAULT_ADDR              0x02C
+#define S5P_DEFAULT_SLAVE_ADDR         0x030
+
+#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
new file mode 100644 (file)
index 0000000..c337cf3
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_REGS_USB_PHY_H
+#define __PLAT_S5P_REGS_USB_PHY_H
+
+#define EXYNOS4_HSOTG_PHYREG(x)                ((x) + S3C_VA_USB_HSPHY)
+
+#define EXYNOS4_PHYPWR                 EXYNOS4_HSOTG_PHYREG(0x00)
+#define PHY1_HSIC_NORMAL_MASK          (0xf << 9)
+#define PHY1_HSIC1_SLEEP               (1 << 12)
+#define PHY1_HSIC1_FORCE_SUSPEND       (1 << 11)
+#define PHY1_HSIC0_SLEEP               (1 << 10)
+#define PHY1_HSIC0_FORCE_SUSPEND       (1 << 9)
+
+#define PHY1_STD_NORMAL_MASK           (0x7 << 6)
+#define PHY1_STD_SLEEP                 (1 << 8)
+#define PHY1_STD_ANALOG_POWERDOWN      (1 << 7)
+#define PHY1_STD_FORCE_SUSPEND         (1 << 6)
+
+#define PHY0_NORMAL_MASK               (0x39 << 0)
+#define PHY0_SLEEP                     (1 << 5)
+#define PHY0_OTG_DISABLE               (1 << 4)
+#define PHY0_ANALOG_POWERDOWN          (1 << 3)
+#define PHY0_FORCE_SUSPEND             (1 << 0)
+
+#define EXYNOS4_PHYCLK                 EXYNOS4_HSOTG_PHYREG(0x04)
+#define PHY1_COMMON_ON_N               (1 << 7)
+#define PHY0_COMMON_ON_N               (1 << 4)
+#define PHY0_ID_PULLUP                 (1 << 2)
+#define CLKSEL_MASK                    (0x3 << 0)
+#define CLKSEL_SHIFT                   (0)
+#define CLKSEL_48M                     (0x0 << 0)
+#define CLKSEL_12M                     (0x2 << 0)
+#define CLKSEL_24M                     (0x3 << 0)
+
+#define EXYNOS4_RSTCON                 EXYNOS4_HSOTG_PHYREG(0x08)
+#define HOST_LINK_PORT_SWRST_MASK      (0xf << 6)
+#define HOST_LINK_PORT2_SWRST          (1 << 9)
+#define HOST_LINK_PORT1_SWRST          (1 << 8)
+#define HOST_LINK_PORT0_SWRST          (1 << 7)
+#define HOST_LINK_ALL_SWRST            (1 << 6)
+
+#define PHY1_SWRST_MASK                        (0x7 << 3)
+#define PHY1_HSIC_SWRST                        (1 << 5)
+#define PHY1_STD_SWRST                 (1 << 4)
+#define PHY1_ALL_SWRST                 (1 << 3)
+
+#define PHY0_SWRST_MASK                        (0x7 << 0)
+#define PHY0_PHYLINK_SWRST             (1 << 2)
+#define PHY0_HLINK_SWRST               (1 << 1)
+#define PHY0_SWRST                     (1 << 0)
+
+#define EXYNOS4_PHY1CON                        EXYNOS4_HSOTG_PHYREG(0x34)
+#define FPENABLEN                      (1 << 0)
+
+#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
new file mode 100644 (file)
index 0000000..6a5fbb5
--- /dev/null
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung sysmmu driver for EXYNOS4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_SYSMMU_H
+#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
+
+enum exynos4_sysmmu_ips {
+       SYSMMU_MDMA,
+       SYSMMU_SSS,
+       SYSMMU_FIMC0,
+       SYSMMU_FIMC1,
+       SYSMMU_FIMC2,
+       SYSMMU_FIMC3,
+       SYSMMU_JPEG,
+       SYSMMU_FIMD0,
+       SYSMMU_FIMD1,
+       SYSMMU_PCIe,
+       SYSMMU_G2D,
+       SYSMMU_ROTATOR,
+       SYSMMU_MDMA2,
+       SYSMMU_TV,
+       SYSMMU_MFC_L,
+       SYSMMU_MFC_R,
+       EXYNOS4_SYSMMU_TOTAL_IPNUM,
+};
+
+#define S5P_SYSMMU_TOTAL_IPNUM         EXYNOS4_SYSMMU_TOTAL_IPNUM
+
+extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+
+typedef enum exynos4_sysmmu_ips sysmmu_ips;
+
+void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
+void sysmmu_clk_enable(sysmmu_ips ips);
+void sysmmu_clk_disable(sysmmu_ips ips);
+
+#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
new file mode 100644 (file)
index 0000000..5e3220c
--- /dev/null
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos4/include/mach/system.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - system support header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <plat/system-reset.h>
+
+static void arch_idle(void)
+{
+       /* nothing here yet */
+}
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h
new file mode 100644 (file)
index 0000000..6d13875
--- /dev/null
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-exynos4/include/mach/timex.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Copyright (c) 2003-2010 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/timex.h
+ *
+ * EXYNOS4 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H __FILE__
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
new file mode 100644 (file)
index 0000000..21d97bc
--- /dev/null
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H __FILE__
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+       /* we do not need to do any cpu detection here at the moment. */
+
+       /*
+        * For preventing FIFO overrun or infinite loop of UART console,
+        * fifo_max should be the minimum fifo size of all of the UART channels
+        */
+       fifo_mask = S5PV210_UFSTAT_TXMASK;
+       fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
+}
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
new file mode 100644 (file)
index 0000000..284330e
--- /dev/null
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EXYNOS4 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H __FILE__
+
+#define VMALLOC_END    0xF6000000UL
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
new file mode 100644 (file)
index 0000000..a8a83e3
--- /dev/null
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos4/init.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
+       [0] = {
+               .name           = "uclk1",
+               .divisor        = 1,
+               .min_baud       = 0,
+               .max_baud       = 0,
+       },
+};
+
+/* uart registration process */
+void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+       struct s3c2410_uartcfg *tcfg = cfg;
+       u32 ucnt;
+
+       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+               if (!tcfg->clocks) {
+                       tcfg->has_fracval = 1;
+                       tcfg->clocks = exynos4_serial_clocks;
+                       tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
+               }
+               tcfg->flags |= NO_NEED_CHECK_CLKSRC;
+       }
+
+       s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
new file mode 100644 (file)
index 0000000..5a2758a
--- /dev/null
@@ -0,0 +1,124 @@
+/* linux/arch/arm/mach-exynos4/irq-combiner.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Based on arch/arm/common/gic.c
+ *
+ * IRQ COMBINER support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+
+#include <asm/mach/irq.h>
+
+#define COMBINER_ENABLE_SET    0x0
+#define COMBINER_ENABLE_CLEAR  0x4
+#define COMBINER_INT_STATUS    0xC
+
+static DEFINE_SPINLOCK(irq_controller_lock);
+
+struct combiner_chip_data {
+       unsigned int irq_offset;
+       unsigned int irq_mask;
+       void __iomem *base;
+};
+
+static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+
+static inline void __iomem *combiner_base(struct irq_data *data)
+{
+       struct combiner_chip_data *combiner_data =
+               irq_data_get_irq_chip_data(data);
+
+       return combiner_data->base;
+}
+
+static void combiner_mask_irq(struct irq_data *data)
+{
+       u32 mask = 1 << (data->irq % 32);
+
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+}
+
+static void combiner_unmask_irq(struct irq_data *data)
+{
+       u32 mask = 1 << (data->irq % 32);
+
+       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+}
+
+static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+       struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       unsigned int cascade_irq, combiner_irq;
+       unsigned long status;
+
+       chained_irq_enter(chip, desc);
+
+       spin_lock(&irq_controller_lock);
+       status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+       spin_unlock(&irq_controller_lock);
+       status &= chip_data->irq_mask;
+
+       if (status == 0)
+               goto out;
+
+       combiner_irq = __ffs(status);
+
+       cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+       if (unlikely(cascade_irq >= NR_IRQS))
+               do_bad_IRQ(cascade_irq, desc);
+       else
+               generic_handle_irq(cascade_irq);
+
+ out:
+       chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip combiner_chip = {
+       .name           = "COMBINER",
+       .irq_mask       = combiner_mask_irq,
+       .irq_unmask     = combiner_unmask_irq,
+};
+
+void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+{
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+       if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+               BUG();
+       irq_set_chained_handler(irq, combiner_handle_cascade_irq);
+}
+
+void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+                         unsigned int irq_start)
+{
+       unsigned int i;
+
+       if (combiner_nr >= MAX_COMBINER_NR)
+               BUG();
+
+       combiner_data[combiner_nr].base = base;
+       combiner_data[combiner_nr].irq_offset = irq_start;
+       combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+
+       /* Disable all interrupts */
+
+       __raw_writel(combiner_data[combiner_nr].irq_mask,
+                    base + COMBINER_ENABLE_CLEAR);
+
+       /* Setup the Linux IRQ subsystem */
+
+       for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+                               + MAX_IRQ_IN_COMBINER; i++) {
+               irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+               irq_set_chip_data(i, &combiner_data[combiner_nr]);
+               set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+       }
+}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
new file mode 100644 (file)
index 0000000..badb8c6
--- /dev/null
@@ -0,0 +1,237 @@
+/* linux/arch/arm/mach-exynos4/irq-eint.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <plat/pm.h>
+#include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+
+#include <asm/mach/irq.h>
+
+static DEFINE_SPINLOCK(eint_lock);
+
+static unsigned int eint0_15_data[16];
+
+static unsigned int exynos4_get_irq_nr(unsigned int number)
+{
+       u32 ret = 0;
+
+       switch (number) {
+       case 0 ... 3:
+               ret = (number + IRQ_EINT0);
+               break;
+       case 4 ... 7:
+               ret = (number + (IRQ_EINT4 - 4));
+               break;
+       case 8 ... 15:
+               ret = (number + (IRQ_EINT8 - 8));
+               break;
+       default:
+               printk(KERN_ERR "number available : %d\n", number);
+       }
+
+       return ret;
+}
+
+static inline void exynos4_irq_eint_mask(struct irq_data *data)
+{
+       u32 mask;
+
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask |= eint_irq_to_bit(data->irq);
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+}
+
+static void exynos4_irq_eint_unmask(struct irq_data *data)
+{
+       u32 mask;
+
+       spin_lock(&eint_lock);
+       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask &= ~(eint_irq_to_bit(data->irq));
+       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+}
+
+static inline void exynos4_irq_eint_ack(struct irq_data *data)
+{
+       __raw_writel(eint_irq_to_bit(data->irq),
+                    S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+}
+
+static void exynos4_irq_eint_maskack(struct irq_data *data)
+{
+       exynos4_irq_eint_mask(data);
+       exynos4_irq_eint_ack(data);
+}
+
+static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+       int offs = EINT_OFFSET(data->irq);
+       int shift;
+       u32 ctrl, mask;
+       u32 newvalue = 0;
+
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+               break;
+
+       case IRQ_TYPE_EDGE_FALLING:
+               newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+               break;
+
+       case IRQ_TYPE_EDGE_BOTH:
+               newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+               break;
+
+       case IRQ_TYPE_LEVEL_LOW:
+               newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+               break;
+
+       case IRQ_TYPE_LEVEL_HIGH:
+               newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+               break;
+
+       default:
+               printk(KERN_ERR "No such irq type %d", type);
+               return -EINVAL;
+       }
+
+       shift = (offs & 0x7) * 4;
+       mask = 0x7 << shift;
+
+       spin_lock(&eint_lock);
+       ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       ctrl &= ~mask;
+       ctrl |= newvalue << shift;
+       __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       spin_unlock(&eint_lock);
+
+       switch (offs) {
+       case 0 ... 7:
+               s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+               break;
+       case 8 ... 15:
+               s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+               break;
+       case 16 ... 23:
+               s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+               break;
+       case 24 ... 31:
+               s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+               break;
+       default:
+               printk(KERN_ERR "No such irq number %d", offs);
+       }
+
+       return 0;
+}
+
+static struct irq_chip exynos4_irq_eint = {
+       .name           = "exynos4-eint",
+       .irq_mask       = exynos4_irq_eint_mask,
+       .irq_unmask     = exynos4_irq_eint_unmask,
+       .irq_mask_ack   = exynos4_irq_eint_maskack,
+       .irq_ack        = exynos4_irq_eint_ack,
+       .irq_set_type   = exynos4_irq_eint_set_type,
+#ifdef CONFIG_PM
+       .irq_set_wake   = s3c_irqext_wake,
+#endif
+};
+
+/* exynos4_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void exynos4_irq_demux_eint(unsigned int start)
+{
+       unsigned int irq;
+
+       u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+       u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+
+       status &= ~mask;
+       status &= 0xff;
+
+       while (status) {
+               irq = fls(status) - 1;
+               generic_handle_irq(irq + start);
+               status &= ~(1 << irq);
+       }
+}
+
+static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+       struct irq_chip *chip = irq_get_chip(irq);
+       chained_irq_enter(chip, desc);
+       exynos4_irq_demux_eint(IRQ_EINT(16));
+       exynos4_irq_demux_eint(IRQ_EINT(24));
+       chained_irq_exit(chip, desc);
+}
+
+static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+       u32 *irq_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+
+       chained_irq_enter(chip, desc);
+       chip->irq_mask(&desc->irq_data);
+
+       if (chip->irq_ack)
+               chip->irq_ack(&desc->irq_data);
+
+       generic_handle_irq(*irq_data);
+
+       chip->irq_unmask(&desc->irq_data);
+       chained_irq_exit(chip, desc);
+}
+
+int __init exynos4_init_irq_eint(void)
+{
+       int irq;
+
+       for (irq = 0 ; irq <= 31 ; irq++) {
+               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                                        handle_level_irq);
+               set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+       }
+
+       irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+
+       for (irq = 0 ; irq <= 15 ; irq++) {
+               eint0_15_data[irq] = IRQ_EINT(irq);
+
+               irq_set_handler_data(exynos4_get_irq_nr(irq),
+                                    &eint0_15_data[irq]);
+               irq_set_chained_handler(exynos4_get_irq_nr(irq),
+                                       exynos4_irq_eint0_15);
+       }
+
+       return 0;
+}
+
+arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
new file mode 100644 (file)
index 0000000..f0ca6c1
--- /dev/null
@@ -0,0 +1,215 @@
+/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ARMLEX4210_UCON_DEFAULT        (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define ARMLEX4210_ULCON_DEFAULT       S3C2410_LCON_CS8
+
+#define ARMLEX4210_UFCON_DEFAULT       (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG4 |        \
+                                S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .flags          = 0,
+               .ucon           = ARMLEX4210_UCON_DEFAULT,
+               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .flags          = 0,
+               .ucon           = ARMLEX4210_UCON_DEFAULT,
+               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .flags          = 0,
+               .ucon           = ARMLEX4210_UCON_DEFAULT,
+               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .flags          = 0,
+               .ucon           = ARMLEX4210_UCON_DEFAULT,
+               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+       },
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_PERMANENT,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+       .max_width              = 8,
+       .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_GPIO,
+       .ext_cd_gpio            = EXYNOS4_GPX2(5),
+       .ext_cd_gpio_invert     = 1,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+       .max_width              = 4,
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_PERMANENT,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+       .max_width              = 4,
+};
+
+static void __init armlex4210_sdhci_init(void)
+{
+       s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
+       s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
+       s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
+}
+
+static void __init armlex4210_wlan_init(void)
+{
+       /* enable */
+       s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
+
+       /* reset */
+       s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
+
+       /* wakeup */
+       s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
+}
+
+static struct resource armlex4210_smsc911x_resources[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_SROM_BANK(3),
+               .end    = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_EINT(27),
+               .end    = IRQ_EINT(27),
+               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+       },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+       .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+       .phy_interface  = PHY_INTERFACE_MODE_MII,
+       .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device armlex4210_smsc911x = {
+       .name           = "smsc911x",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
+       .resource       = armlex4210_smsc911x_resources,
+       .dev            = {
+               .platform_data  = &smsc9215_config,
+       },
+};
+
+static struct platform_device *armlex4210_devices[] __initdata = {
+       &s3c_device_hsmmc0,
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc3,
+       &s3c_device_rtc,
+       &s3c_device_wdt,
+       &exynos4_device_sysmmu,
+       &samsung_asoc_dma,
+       &armlex4210_smsc911x,
+       &exynos4_device_ahci,
+};
+
+static void __init armlex4210_smsc911x_init(void)
+{
+       u32 cs1;
+
+       /* configure nCS1 width to 16 bits */
+       cs1 = __raw_readl(S5P_SROM_BW) &
+               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+               (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+               (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
+               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+               S5P_SROM_BW__NCS1__SHIFT;
+       __raw_writel(cs1, S5P_SROM_BW);
+
+       /* set timing for nCS1 suitable for ethernet chip */
+       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+static void __init armlex4210_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(armlex4210_uartcfgs,
+                          ARRAY_SIZE(armlex4210_uartcfgs));
+}
+
+static void __init armlex4210_machine_init(void)
+{
+       armlex4210_smsc911x_init();
+
+       armlex4210_sdhci_init();
+
+       armlex4210_wlan_init();
+
+       platform_add_devices(armlex4210_devices,
+                            ARRAY_SIZE(armlex4210_devices));
+}
+
+MACHINE_START(ARMLEX4210, "ARMLEX4210")
+       /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = armlex4210_map_io,
+       .init_machine   = armlex4210_machine_init,
+       .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
new file mode 100644 (file)
index 0000000..236bbe1
--- /dev/null
@@ -0,0 +1,1339 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-nuri.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/i2c-gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/power/max8903_charger.h>
+#include <linux/power/max17042_battery.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
+#include <linux/mmc/host.h>
+#include <linux/fb.h>
+#include <linux/pwm_backlight.h>
+
+#include <video/platform_lcd.h>
+#include <media/m5mols.h>
+#include <media/s5p_fimc.h>
+#include <media/v4l2-mediabus.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/adc.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/sdhci.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/mfc.h>
+#include <plat/pd.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define NURI_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define NURI_ULCON_DEFAULT     S3C2410_LCON_CS8
+
+#define NURI_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG256 |      \
+                                S5PV210_UFCON_RXTRIG256)
+
+enum fixed_regulator_id {
+       FIXED_REG_ID_MMC = 0,
+       FIXED_REG_ID_MAX8903,
+       FIXED_REG_ID_CAM_A28V,
+       FIXED_REG_ID_CAM_12V,
+};
+
+static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
+       {
+               .hwport         = 0,
+               .ucon           = NURI_UCON_DEFAULT,
+               .ulcon          = NURI_ULCON_DEFAULT,
+               .ufcon          = NURI_UFCON_DEFAULT,
+       },
+       {
+               .hwport         = 1,
+               .ucon           = NURI_UCON_DEFAULT,
+               .ulcon          = NURI_ULCON_DEFAULT,
+               .ufcon          = NURI_UFCON_DEFAULT,
+       },
+       {
+               .hwport         = 2,
+               .ucon           = NURI_UCON_DEFAULT,
+               .ulcon          = NURI_ULCON_DEFAULT,
+               .ufcon          = NURI_UFCON_DEFAULT,
+       },
+       {
+               .hwport         = 3,
+               .ucon           = NURI_UCON_DEFAULT,
+               .ulcon          = NURI_ULCON_DEFAULT,
+               .ufcon          = NURI_UFCON_DEFAULT,
+       },
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
+       .max_width              = 8,
+       .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                               MMC_CAP_DISABLE | MMC_CAP_ERASE),
+       .cd_type                = S3C_SDHCI_CD_PERMANENT,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply emmc_supplies[] = {
+       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+       REGULATOR_SUPPLY("vmmc", "dw_mmc"),
+};
+
+static struct regulator_init_data emmc_fixed_voltage_init_data = {
+       .constraints            = {
+               .name           = "VMEM_VDD_2.8V",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
+       .consumer_supplies      = emmc_supplies,
+};
+
+static struct fixed_voltage_config emmc_fixed_voltage_config = {
+       .supply_name            = "MASSMEMORY_EN (inverted)",
+       .microvolts             = 2800000,
+       .gpio                   = EXYNOS4_GPL1(1),
+       .enable_high            = false,
+       .init_data              = &emmc_fixed_voltage_init_data,
+};
+
+static struct platform_device emmc_fixed_voltage = {
+       .name                   = "reg-fixed-voltage",
+       .id                     = FIXED_REG_ID_MMC,
+       .dev                    = {
+               .platform_data  = &emmc_fixed_voltage_config,
+       },
+};
+
+/* SD */
+static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
+       .max_width              = 4,
+       .host_caps              = MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                               MMC_CAP_DISABLE,
+       .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
+       .ext_cd_gpio_invert     = 1,
+       .cd_type                = S3C_SDHCI_CD_GPIO,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WLAN */
+static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
+       .max_width              = 4,
+       .host_caps              = MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+       .cd_type                = S3C_SDHCI_CD_EXTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static void __init nuri_sdhci_init(void)
+{
+       s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
+       s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
+       s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
+}
+
+/* GPIO KEYS */
+static struct gpio_keys_button nuri_gpio_keys_tables[] = {
+       {
+               .code                   = KEY_VOLUMEUP,
+               .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
+               .desc                   = "gpio-keys: KEY_VOLUMEUP",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_VOLUMEDOWN,
+               .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
+               .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_POWER,
+               .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
+               .desc                   = "gpio-keys: KEY_POWER",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       },
+};
+
+static struct gpio_keys_platform_data nuri_gpio_keys_data = {
+       .buttons                = nuri_gpio_keys_tables,
+       .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
+};
+
+static struct platform_device nuri_gpio_keys = {
+       .name                   = "gpio-keys",
+       .dev                    = {
+               .platform_data  = &nuri_gpio_keys_data,
+       },
+};
+
+/* Frame Buffer */
+static struct s3c_fb_pd_win nuri_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 64,
+               .right_margin   = 16,
+               .upper_margin   = 64,
+               .lower_margin   = 1,
+               .hsync_len      = 48,
+               .vsync_len      = 3,
+               .xres           = 1280,
+               .yres           = 800,
+               .refresh        = 60,
+       },
+       .max_bpp        = 24,
+       .default_bpp    = 16,
+       .virtual_x      = 1280,
+       .virtual_y      = 800,
+};
+
+static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
+       .win[0]         = &nuri_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                         VIDCON0_CLKSEL_LCD,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
+{
+       int gpio = EXYNOS4_GPE1(5);
+
+       gpio_request(gpio, "LVDS_nSHDN");
+       gpio_direction_output(gpio, power);
+       gpio_free(gpio);
+}
+
+static int nuri_bl_init(struct device *dev)
+{
+       int ret, gpio = EXYNOS4_GPE2(3);
+
+       ret = gpio_request(gpio, "LCD_LDO_EN");
+       if (!ret)
+               gpio_direction_output(gpio, 0);
+
+       return ret;
+}
+
+static int nuri_bl_notify(struct device *dev, int brightness)
+{
+       if (brightness < 1)
+               brightness = 0;
+
+       gpio_set_value(EXYNOS4_GPE2(3), 1);
+
+       return brightness;
+}
+
+static void nuri_bl_exit(struct device *dev)
+{
+       gpio_free(EXYNOS4_GPE2(3));
+}
+
+/* nuri pwm backlight */
+static struct platform_pwm_backlight_data nuri_backlight_data = {
+       .pwm_id                 = 0,
+       .pwm_period_ns          = 30000,
+       .max_brightness         = 100,
+       .dft_brightness         = 50,
+       .init                   = nuri_bl_init,
+       .notify                 = nuri_bl_notify,
+       .exit                   = nuri_bl_exit,
+};
+
+static struct platform_device nuri_backlight_device = {
+       .name                   = "pwm-backlight",
+       .id                     = -1,
+       .dev                    = {
+               .parent         = &s3c_device_timer[0].dev,
+               .platform_data  = &nuri_backlight_data,
+       },
+};
+
+static struct plat_lcd_data nuri_lcd_platform_data = {
+       .set_power              = nuri_lcd_power_on,
+};
+
+static struct platform_device nuri_lcd_device = {
+       .name                   = "platform-lcd",
+       .id                     = -1,
+       .dev                    = {
+               .platform_data  = &nuri_lcd_platform_data,
+       },
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+       /* Gyro, To be updated */
+};
+
+/* TSP */
+static u8 mxt_init_vals[] = {
+       /* MXT_GEN_COMMAND(6) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       /* MXT_GEN_POWER(7) */
+       0x20, 0xff, 0x32,
+       /* MXT_GEN_ACQUIRE(8) */
+       0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
+       /* MXT_TOUCH_MULTI(9) */
+       0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
+       0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00,
+       /* MXT_TOUCH_KEYARRAY(15) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+       0x00,
+       /* MXT_SPT_GPIOPWM(19) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       /* MXT_PROCI_GRIPFACE(20) */
+       0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
+       0x0f, 0x0a,
+       /* MXT_PROCG_NOISE(22) */
+       0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
+       0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
+       /* MXT_TOUCH_PROXIMITY(23) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00,
+       /* MXT_PROCI_ONETOUCH(24) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       /* MXT_SPT_SELFTEST(25) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00,
+       /* MXT_PROCI_TWOTOUCH(27) */
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       /* MXT_SPT_CTECONFIG(28) */
+       0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
+};
+
+static struct mxt_platform_data mxt_platform_data = {
+       .config                 = mxt_init_vals,
+       .config_length          = ARRAY_SIZE(mxt_init_vals),
+
+       .x_line                 = 18,
+       .y_line                 = 11,
+       .x_size                 = 1024,
+       .y_size                 = 600,
+       .blen                   = 0x1,
+       .threshold              = 0x28,
+       .voltage                = 2800000,              /* 2.8V */
+       .orient                 = MXT_DIAGONAL_COUNTER,
+       .irqflags               = IRQF_TRIGGER_FALLING,
+};
+
+static struct s3c2410_platform_i2c i2c3_data __initdata = {
+       .flags          = 0,
+       .bus_num        = 3,
+       .slave_addr     = 0x10,
+       .frequency      = 400 * 1000,
+       .sda_delay      = 100,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
+               .platform_data  = &mxt_platform_data,
+               .irq            = IRQ_EINT(4),
+       },
+};
+
+static void __init nuri_tsp_init(void)
+{
+       int gpio;
+
+       /* TOUCH_INT: XEINT_4 */
+       gpio = EXYNOS4_GPX0(4);
+       gpio_request(gpio, "TOUCH_INT");
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+}
+
+static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
+       REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
+       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
+       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
+       REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
+       REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
+       REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
+       REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
+       REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
+       REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
+       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
+       REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
+};
+static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
+       REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
+       REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
+       REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
+       REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
+       REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
+       REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
+       REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
+       REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
+       REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
+       REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
+};
+
+static struct regulator_consumer_supply __initdata max8997_charger_[] = {
+       REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+};
+static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
+       REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
+};
+
+static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
+       REGULATOR_SUPPLY("gps_clk", "bcm4751"),
+       REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
+       REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+       .constraints    = {
+               .name           = "VADC_3.3V_C210",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
+       .consumer_supplies      = max8997_ldo1_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+       .constraints    = {
+               .name           = "VALIVE_1.1V_C210",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+       .constraints    = {
+               .name           = "VUSB_1.1V_C210",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
+       .consumer_supplies      = max8997_ldo3_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+       .constraints    = {
+               .name           = "VMIPI_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
+       .consumer_supplies      = max8997_ldo4_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo5_data = {
+       .constraints    = {
+               .name           = "VHSIC_1.2V_C210",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
+       .consumer_supplies      = max8997_ldo5_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+       .constraints    = {
+               .name           = "VCC_1.8V_PDA",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+       .constraints    = {
+               .name           = "CAM_ISP_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
+       .consumer_supplies      = max8997_ldo7_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+       .constraints    = {
+               .name           = "VUSB/VDAC_3.3V_C210",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
+       .consumer_supplies      = max8997_ldo8_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+       .constraints    = {
+               .name           = "VCC_2.8V_PDA",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+       .constraints    = {
+               .name           = "VPLL_1.1V_C210",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+       .constraints    = {
+               .name           = "LVDS_VDD3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .boot_on        = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
+       .consumer_supplies      = max8997_ldo11_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo12_data = {
+       .constraints    = {
+               .name           = "VT_CAM_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
+       .consumer_supplies      = max8997_ldo12_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo13_data = {
+       .constraints    = {
+               .name           = "VTF_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
+       .consumer_supplies      = max8997_ldo13_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+       .constraints    = {
+               .name           = "VCC_3.0V_MOTOR",
+               .min_uV         = 3000000,
+               .max_uV         = 3000000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
+       .consumer_supplies      = max8997_ldo14_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo15_data = {
+       .constraints    = {
+               .name           = "VTOUCH_ADVV2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
+       .consumer_supplies      = max8997_ldo15_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo16_data = {
+       .constraints    = {
+               .name           = "CAM_SENSOR_IO_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
+       .consumer_supplies      = max8997_ldo16_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo18_data = {
+       .constraints    = {
+               .name           = "VTOUCH_VDD2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
+       .consumer_supplies      = max8997_ldo18_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+       .constraints    = {
+               .name           = "VDDQ_M1M2_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+       .constraints    = {
+               .name           = "VARM_1.2V_C210",
+               .min_uV         = 900000,
+               .max_uV         = 1350000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
+       .consumer_supplies = max8997_buck1_,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+       .constraints    = {
+               .name           = "VINT_1.1V_C210",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
+       .consumer_supplies = max8997_buck2_,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+       .constraints    = {
+               .name           = "VG3D_1.1V_C210",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                 REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
+       .consumer_supplies = max8997_buck3_,
+};
+
+static struct regulator_init_data __initdata max8997_buck4_data = {
+       .constraints    = {
+               .name           = "CAM_ISP_CORE_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
+       .consumer_supplies = max8997_buck4_,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+       .constraints    = {
+               .name           = "VMEM_1.2V_C210",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck6_data = {
+       .constraints    = {
+               .name           = "CAM_AF_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
+       .consumer_supplies = max8997_buck6_,
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+       .constraints    = {
+               .name           = "VCC_SUB_2.0V",
+               .min_uV         = 2000000,
+               .max_uV         = 2000000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_32khz_ap_data = {
+       .constraints    = {
+               .name           = "32KHz AP",
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
+       .consumer_supplies = max8997_32khz_ap_,
+};
+
+static struct regulator_init_data __initdata max8997_32khz_cp_data = {
+       .constraints    = {
+               .name           = "32KHz CP",
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_vichg_data = {
+       .constraints    = {
+               .name           = "VICHG",
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_esafeout1_data = {
+       .constraints    = {
+               .name           = "SAFEOUT1",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
+       .consumer_supplies      = max8997_esafeout1_,
+};
+
+static struct regulator_init_data __initdata max8997_esafeout2_data = {
+       .constraints    = {
+               .name           = "SAFEOUT2",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
+       .consumer_supplies      = max8997_esafeout2_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_cv_data = {
+       .constraints    = {
+               .name           = "CHARGER_CV",
+               .min_uV         = 4200000,
+               .max_uV         = 4200000,
+               .apply_uV       = 1,
+       },
+};
+
+static struct regulator_init_data __initdata max8997_charger_data = {
+       .constraints    = {
+               .name           = "CHARGER",
+               .min_uA         = 200000,
+               .max_uA         = 950000,
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+                               REGULATOR_CHANGE_CURRENT,
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
+       .consumer_supplies      = max8997_charger_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_topoff_data = {
+       .constraints    = {
+               .name           = "CHARGER TOPOFF",
+               .min_uA         = 50000,
+               .max_uA         = 200000,
+               .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
+       .consumer_supplies      = max8997_chg_toff_,
+};
+
+static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
+       { MAX8997_LDO1, &max8997_ldo1_data },
+       { MAX8997_LDO2, &max8997_ldo2_data },
+       { MAX8997_LDO3, &max8997_ldo3_data },
+       { MAX8997_LDO4, &max8997_ldo4_data },
+       { MAX8997_LDO5, &max8997_ldo5_data },
+       { MAX8997_LDO6, &max8997_ldo6_data },
+       { MAX8997_LDO7, &max8997_ldo7_data },
+       { MAX8997_LDO8, &max8997_ldo8_data },
+       { MAX8997_LDO9, &max8997_ldo9_data },
+       { MAX8997_LDO10, &max8997_ldo10_data },
+       { MAX8997_LDO11, &max8997_ldo11_data },
+       { MAX8997_LDO12, &max8997_ldo12_data },
+       { MAX8997_LDO13, &max8997_ldo13_data },
+       { MAX8997_LDO14, &max8997_ldo14_data },
+       { MAX8997_LDO15, &max8997_ldo15_data },
+       { MAX8997_LDO16, &max8997_ldo16_data },
+
+       { MAX8997_LDO18, &max8997_ldo18_data },
+       { MAX8997_LDO21, &max8997_ldo21_data },
+
+       { MAX8997_BUCK1, &max8997_buck1_data },
+       { MAX8997_BUCK2, &max8997_buck2_data },
+       { MAX8997_BUCK3, &max8997_buck3_data },
+       { MAX8997_BUCK4, &max8997_buck4_data },
+       { MAX8997_BUCK5, &max8997_buck5_data },
+       { MAX8997_BUCK6, &max8997_buck6_data },
+       { MAX8997_BUCK7, &max8997_buck7_data },
+
+       { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
+       { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
+
+       { MAX8997_ENVICHG, &max8997_vichg_data },
+       { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
+       { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
+       { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
+       { MAX8997_CHARGER, &max8997_charger_data },
+       { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
+};
+
+static struct max8997_platform_data __initdata nuri_max8997_pdata = {
+       .wakeup                 = 1,
+
+       .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
+       .regulators             = nuri_max8997_regulators,
+
+       .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
+       .buck2_gpiodvs = true,
+
+       .buck1_voltage[0] = 1350000, /* 1.35V */
+       .buck1_voltage[1] = 1300000, /* 1.3V */
+       .buck1_voltage[2] = 1250000, /* 1.25V */
+       .buck1_voltage[3] = 1200000, /* 1.2V */
+       .buck1_voltage[4] = 1150000, /* 1.15V */
+       .buck1_voltage[5] = 1100000, /* 1.1V */
+       .buck1_voltage[6] = 1000000, /* 1.0V */
+       .buck1_voltage[7] = 950000, /* 0.95V */
+
+       .buck2_voltage[0] = 1100000, /* 1.1V */
+       .buck2_voltage[1] = 1000000, /* 1.0V */
+       .buck2_voltage[2] = 950000, /* 0.95V */
+       .buck2_voltage[3] = 900000, /* 0.9V */
+       .buck2_voltage[4] = 1100000, /* 1.1V */
+       .buck2_voltage[5] = 1000000, /* 1.0V */
+       .buck2_voltage[6] = 950000, /* 0.95V */
+       .buck2_voltage[7] = 900000, /* 0.9V */
+
+       .buck5_voltage[0] = 1200000, /* 1.2V */
+       .buck5_voltage[1] = 1200000, /* 1.2V */
+       .buck5_voltage[2] = 1200000, /* 1.2V */
+       .buck5_voltage[3] = 1200000, /* 1.2V */
+       .buck5_voltage[4] = 1200000, /* 1.2V */
+       .buck5_voltage[5] = 1200000, /* 1.2V */
+       .buck5_voltage[6] = 1200000, /* 1.2V */
+       .buck5_voltage[7] = 1200000, /* 1.2V */
+};
+
+/* GPIO I2C 5 (PMIC) */
+enum { I2C5_MAX8997 };
+static struct i2c_board_info i2c5_devs[] __initdata = {
+       [I2C5_MAX8997] = {
+               I2C_BOARD_INFO("max8997", 0xCC >> 1),
+               .platform_data  = &nuri_max8997_pdata,
+       },
+};
+
+static struct max17042_platform_data nuri_battery_platform_data = {
+};
+
+/* GPIO I2C 9 (Fuel Gauge) */
+static struct i2c_gpio_platform_data i2c9_gpio_data = {
+       .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
+       .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
+};
+static struct platform_device i2c9_gpio = {
+       .name                   = "i2c-gpio",
+       .id                     = 9,
+       .dev                    = {
+               .platform_data  = &i2c9_gpio_data,
+       },
+};
+enum { I2C9_MAX17042};
+static struct i2c_board_info i2c9_devs[] __initdata = {
+       [I2C9_MAX17042] = {
+               I2C_BOARD_INFO("max17042", 0x36),
+               .platform_data = &nuri_battery_platform_data,
+       },
+};
+
+/* MAX8903 Secondary Charger */
+static struct regulator_consumer_supply supplies_max8903[] = {
+       REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
+};
+
+static struct regulator_init_data max8903_charger_en_data = {
+       .constraints = {
+               .name           = "VOUT_CHARGER",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
+       .consumer_supplies = supplies_max8903,
+};
+
+static struct fixed_voltage_config max8903_charger_en = {
+       .supply_name = "VOUT_CHARGER",
+       .microvolts = 5000000, /* Assume 5VDC */
+       .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
+       .enable_high = 0, /* Enable = Low */
+       .enabled_at_boot = 1,
+       .init_data = &max8903_charger_en_data,
+};
+
+static struct platform_device max8903_fixed_reg_dev = {
+       .name = "reg-fixed-voltage",
+       .id = FIXED_REG_ID_MAX8903,
+       .dev = { .platform_data = &max8903_charger_en },
+};
+
+static struct max8903_pdata nuri_max8903 = {
+       /*
+        * cen: don't control with the driver, let it be
+        * controlled by regulator above
+        */
+       .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
+       /* uok, usus: not connected */
+       .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+       /* flt: vcc_1.8V_pda */
+       .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
+
+       .dc_valid = true,
+       .usb_valid = false, /* USB is not wired to MAX8903 */
+};
+
+static struct platform_device nuri_max8903_device = {
+       .name                   = "max8903-charger",
+       .dev                    = {
+               .platform_data  = &nuri_max8903,
+       },
+};
+
+static void __init nuri_power_init(void)
+{
+       int gpio;
+       int irq_base = IRQ_GPIO_END + 1;
+       int ta_en = 0;
+
+       nuri_max8997_pdata.irq_base = irq_base;
+       irq_base += MAX8997_IRQ_NR;
+
+       gpio = EXYNOS4_GPX0(7);
+       gpio_request(gpio, "AP_PMIC_IRQ");
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+       gpio = EXYNOS4_GPX2(3);
+       gpio_request(gpio, "FUEL_ALERT");
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+       gpio = nuri_max8903.dok;
+       gpio_request(gpio, "TA_nCONNECTED");
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+       ta_en = gpio_get_value(gpio) ? 0 : 1;
+
+       gpio = nuri_max8903.chg;
+       gpio_request(gpio, "TA_nCHG");
+       gpio_direction_input(gpio);
+
+       gpio = nuri_max8903.dcm;
+       gpio_request(gpio, "CURR_ADJ");
+       gpio_direction_output(gpio, ta_en);
+}
+
+/* USB EHCI */
+static struct s5p_ehci_platdata nuri_ehci_pdata;
+
+static void __init nuri_ehci_init(void)
+{
+       struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
+
+       s5p_ehci_set_platdata(pdata);
+}
+
+/* CAMERA */
+static struct regulator_consumer_supply cam_vdda_supply[] = {
+       REGULATOR_SUPPLY("a_sensor", "0-001f"),
+};
+
+static struct regulator_init_data cam_vdda_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
+       .consumer_supplies = cam_vdda_supply,
+};
+
+static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
+       .supply_name    = "CAM_IO_EN",
+       .microvolts     = 2800000,
+       .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_vdda_reg_init_data,
+};
+
+static struct platform_device cam_vdda_fixed_rdev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
+       .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply camera_8m_12v_supply =
+       REGULATOR_SUPPLY("dig_12", "0-001f");
+
+static struct regulator_init_data cam_8m_12v_reg_init_data = {
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &camera_8m_12v_supply,
+       .constraints = {
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS
+       },
+};
+
+static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
+       .supply_name    = "8M_1.2V",
+       .microvolts     = 1200000,
+       .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_8m_12v_reg_init_data,
+};
+
+static struct platform_device cam_8m_12v_fixed_rdev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
+       .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+       .clk_rate       = 166000000UL,
+       .lanes          = 2,
+       .alignment      = 32,
+       .hs_settle      = 12,
+       .phy_enable     = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_MEGA_RST      EXYNOS4_GPY3(7) /* ISP_RESET */
+#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPL2(5)
+
+static struct m5mols_platform_data m5mols_platdata = {
+       .gpio_reset = GPIO_CAM_MEGA_RST,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+       I2C_BOARD_INFO("M5MOLS", 0x1F),
+       .platform_data  = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
+       {
+               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
+               .bus_type       = FIMC_MIPI_CSI2,
+               .board_info     = &m5mols_board_info,
+               .clk_frequency  = 24000000UL,
+               .csi_data_align = 32,
+       },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+       .isp_info       = nuri_camera_sensors,
+       .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
+};
+
+static struct gpio nuri_camera_gpios[] = {
+       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
+       { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+};
+
+static void nuri_camera_init(void)
+{
+       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+                        &s5p_device_mipi_csis0);
+       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
+                        &s5p_device_fimc_md);
+
+       if (gpio_request_array(nuri_camera_gpios,
+                              ARRAY_SIZE(nuri_camera_gpios))) {
+               pr_err("%s: GPIO request failed\n", __func__);
+               return;
+       }
+
+       m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
+       if (!IS_ERR_VALUE(m5mols_board_info.irq))
+               s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
+       else
+               pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
+
+       /* Free GPIOs controlled directly by the sensor drivers. */
+       gpio_free(GPIO_CAM_MEGA_RST);
+
+       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
+               pr_err("%s: Camera port A setup failed\n", __func__);
+               return;
+       }
+       /* Increase drive strength of the sensor clock output */
+       s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
+}
+
+static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
+       .frequency      = 400000U,
+       .sda_delay      = 200,
+};
+
+static struct platform_device *nuri_devices[] __initdata = {
+       /* Samsung Platform Devices */
+       &s3c_device_i2c5, /* PMIC should initialize first */
+       &s3c_device_i2c0,
+       &emmc_fixed_voltage,
+       &s5p_device_mipi_csis0,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &s5p_device_fimd0,
+       &s3c_device_hsmmc0,
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc3,
+       &s3c_device_wdt,
+       &s3c_device_timer[0],
+       &s5p_device_ehci,
+       &s3c_device_i2c3,
+       &i2c9_gpio,
+       &s3c_device_adc,
+       &s3c_device_rtc,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
+       &exynos4_device_pd[PD_MFC],
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_CAM],
+       &s5p_device_fimc_md,
+
+       /* NURI Devices */
+       &nuri_gpio_keys,
+       &nuri_lcd_device,
+       &nuri_backlight_device,
+       &max8903_fixed_reg_dev,
+       &nuri_max8903_device,
+       &cam_vdda_fixed_rdev,
+       &cam_8m_12v_fixed_rdev,
+};
+
+static void __init nuri_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+}
+
+static void __init nuri_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init nuri_machine_init(void)
+{
+       nuri_sdhci_init();
+       nuri_tsp_init();
+       nuri_power_init();
+
+       s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
+       i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+       s3c_i2c3_set_platdata(&i2c3_data);
+       i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+       s3c_i2c5_set_platdata(NULL);
+       i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
+       i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+       i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
+       i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
+
+       s5p_fimd0_set_platdata(&nuri_fb_pdata);
+
+       nuri_camera_init();
+
+       nuri_ehci_init();
+       clk_xusbxti.rate = 24000000;
+
+       /* Last */
+       platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+}
+
+MACHINE_START(NURI, "NURI")
+       /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = nuri_map_io,
+       .init_machine   = nuri_machine_init,
+       .timer          = &exynos4_timer,
+       .reserve        = &nuri_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
new file mode 100644 (file)
index 0000000..f80b563
--- /dev/null
@@ -0,0 +1,700 @@
+/* linux/arch/arm/mach-exynos4/mach-origen.c
+ *
+ * Copyright (c) 2011 Insignal Co., Ltd.
+ *             http://www.insignal.co.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8997.h>
+#include <linux/lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+#include <plat/pd.h>
+#include <plat/fb.h>
+#include <plat/mfc.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ORIGEN_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define ORIGEN_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define ORIGEN_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG4 |        \
+                                S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+};
+
+static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
+       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
+       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
+};
+static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
+       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
+       REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
+       REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
+       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
+};
+static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
+       REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
+       REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
+       REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
+       REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata buck1_consumer[] = {
+       REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck2_consumer[] = {
+       REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck3_consumer[] = {
+       REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
+};
+static struct regulator_consumer_supply __initdata buck7_consumer[] = {
+       REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+       .constraints    = {
+               .name           = "VDD_ABB_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+       .constraints    = {
+               .name           = "VDD_ALIVE_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+       .constraints    = {
+               .name           = "VMIPI_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
+       .consumer_supplies      = ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+       .constraints    = {
+               .name           = "VDD_RTC_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+       .constraints    = {
+               .name           = "VMIPI_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
+       .consumer_supplies      = ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+       .constraints    = {
+               .name           = "VDD_AUD_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
+       .consumer_supplies      = ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+       .constraints    = {
+               .name           = "VADC_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
+       .consumer_supplies      = ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+       .constraints    = {
+               .name           = "DVDD_SWB_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
+       .consumer_supplies      = ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+       .constraints    = {
+               .name           = "VDD_PLL_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+       .constraints    = {
+               .name           = "VDD_AUD_3V",
+               .min_uV         = 3000000,
+               .max_uV         = 3000000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
+       .consumer_supplies      = ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+       .constraints    = {
+               .name           = "AVDD18_SWB_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
+       .consumer_supplies      = ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo17_data = {
+       .constraints    = {
+               .name           = "VDD_SWB_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
+       .consumer_supplies      = ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+       .constraints    = {
+               .name           = "VDD_MIF_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+       .constraints    = {
+               .name           = "VDD_ARM_1.2V",
+               .min_uV         = 950000,
+               .max_uV         = 1350000,
+               .always_on      = 1,
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
+       .consumer_supplies      = buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+       .constraints    = {
+               .name           = "VDD_INT_1.1V",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .always_on      = 1,
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
+       .consumer_supplies      = buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+       .constraints    = {
+               .name           = "VDD_G3D_1.1V",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                       REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
+       .consumer_supplies      = buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+       .constraints    = {
+               .name           = "VDDQ_M1M2_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+       .constraints    = {
+               .name           = "VDD_LCD_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .boot_on        = 1,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
+       .consumer_supplies      = buck7_consumer,
+};
+
+static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
+       { MAX8997_LDO1,         &max8997_ldo1_data },
+       { MAX8997_LDO2,         &max8997_ldo2_data },
+       { MAX8997_LDO3,         &max8997_ldo3_data },
+       { MAX8997_LDO4,         &max8997_ldo4_data },
+       { MAX8997_LDO6,         &max8997_ldo6_data },
+       { MAX8997_LDO7,         &max8997_ldo7_data },
+       { MAX8997_LDO8,         &max8997_ldo8_data },
+       { MAX8997_LDO9,         &max8997_ldo9_data },
+       { MAX8997_LDO10,        &max8997_ldo10_data },
+       { MAX8997_LDO11,        &max8997_ldo11_data },
+       { MAX8997_LDO14,        &max8997_ldo14_data },
+       { MAX8997_LDO17,        &max8997_ldo17_data },
+       { MAX8997_LDO21,        &max8997_ldo21_data },
+       { MAX8997_BUCK1,        &max8997_buck1_data },
+       { MAX8997_BUCK2,        &max8997_buck2_data },
+       { MAX8997_BUCK3,        &max8997_buck3_data },
+       { MAX8997_BUCK5,        &max8997_buck5_data },
+       { MAX8997_BUCK7,        &max8997_buck7_data },
+};
+
+struct max8997_platform_data __initdata origen_max8997_pdata = {
+       .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
+       .regulators     = origen_max8997_regulators,
+
+       .wakeup = true,
+       .buck1_gpiodvs  = false,
+       .buck2_gpiodvs  = false,
+       .buck5_gpiodvs  = false,
+       .irq_base       = IRQ_GPIO_END + 1,
+
+       .ignore_gpiodvs_side_effect = true,
+       .buck125_default_idx = 0x0,
+
+       .buck125_gpios[0]       = EXYNOS4_GPX0(0),
+       .buck125_gpios[1]       = EXYNOS4_GPX0(1),
+       .buck125_gpios[2]       = EXYNOS4_GPX0(2),
+
+       .buck1_voltage[0]       = 1350000,
+       .buck1_voltage[1]       = 1300000,
+       .buck1_voltage[2]       = 1250000,
+       .buck1_voltage[3]       = 1200000,
+       .buck1_voltage[4]       = 1150000,
+       .buck1_voltage[5]       = 1100000,
+       .buck1_voltage[6]       = 1000000,
+       .buck1_voltage[7]       = 950000,
+
+       .buck2_voltage[0]       = 1100000,
+       .buck2_voltage[1]       = 1100000,
+       .buck2_voltage[2]       = 1100000,
+       .buck2_voltage[3]       = 1100000,
+       .buck2_voltage[4]       = 1000000,
+       .buck2_voltage[5]       = 1000000,
+       .buck2_voltage[6]       = 1000000,
+       .buck2_voltage[7]       = 1000000,
+
+       .buck5_voltage[0]       = 1200000,
+       .buck5_voltage[1]       = 1200000,
+       .buck5_voltage[2]       = 1200000,
+       .buck5_voltage[3]       = 1200000,
+       .buck5_voltage[4]       = 1200000,
+       .buck5_voltage[5]       = 1200000,
+       .buck5_voltage[6]       = 1200000,
+       .buck5_voltage[7]       = 1200000,
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("max8997", (0xCC >> 1)),
+               .platform_data  = &origen_max8997_pdata,
+               .irq            = IRQ_EINT(4),
+       },
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata origen_ehci_pdata;
+
+static void __init origen_ehci_init(void)
+{
+       struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
+
+       s5p_ehci_set_platdata(pdata);
+}
+
+static struct gpio_keys_button origen_gpio_keys_table[] = {
+       {
+               .code                   = KEY_MENU,
+               .gpio                   = EXYNOS4_GPX1(5),
+               .desc                   = "gpio-keys: KEY_MENU",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_HOME,
+               .gpio                   = EXYNOS4_GPX1(6),
+               .desc                   = "gpio-keys: KEY_HOME",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_BACK,
+               .gpio                   = EXYNOS4_GPX1(7),
+               .desc                   = "gpio-keys: KEY_BACK",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_UP,
+               .gpio                   = EXYNOS4_GPX2(0),
+               .desc                   = "gpio-keys: KEY_UP",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_DOWN,
+               .gpio                   = EXYNOS4_GPX2(1),
+               .desc                   = "gpio-keys: KEY_DOWN",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       },
+};
+
+static struct gpio_keys_platform_data origen_gpio_keys_data = {
+       .buttons        = origen_gpio_keys_table,
+       .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
+};
+
+static struct platform_device origen_device_gpiokeys = {
+       .name           = "gpio-keys",
+       .dev            = {
+               .platform_data  = &origen_gpio_keys_data,
+       },
+};
+
+static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+       int ret;
+
+       if (power)
+               ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                       GPIOF_OUT_INIT_HIGH, "GPE3_4");
+       else
+               ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                       GPIOF_OUT_INIT_LOW, "GPE3_4");
+
+       gpio_free(EXYNOS4_GPE3(4));
+
+       if (ret)
+               pr_err("failed to request gpio for LCD power: %d\n", ret);
+}
+
+static struct plat_lcd_data origen_lcd_hv070wsa_data = {
+       .set_power = lcd_hv070wsa_set_power,
+};
+
+static struct platform_device origen_lcd_hv070wsa = {
+       .name                   = "platform-lcd",
+       .dev.parent             = &s5p_device_fimd0.dev,
+       .dev.platform_data      = &origen_lcd_hv070wsa_data,
+};
+
+static struct s3c_fb_pd_win origen_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 64,
+               .right_margin   = 16,
+               .upper_margin   = 64,
+               .lower_margin   = 16,
+               .hsync_len      = 48,
+               .vsync_len      = 3,
+               .xres           = 1024,
+               .yres           = 600,
+       },
+       .max_bpp                = 32,
+       .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
+       .win[0]         = &origen_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct platform_device *origen_devices[] __initdata = {
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc0,
+       &s3c_device_i2c0,
+       &s3c_device_rtc,
+       &s3c_device_wdt,
+       &s5p_device_ehci,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &s5p_device_fimd0,
+       &s5p_device_hdmi,
+       &s5p_device_i2c_hdmiphy,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
+       &s5p_device_mixer,
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_TV],
+       &exynos4_device_pd[PD_G3D],
+       &exynos4_device_pd[PD_LCD1],
+       &exynos4_device_pd[PD_CAM],
+       &exynos4_device_pd[PD_GPS],
+       &exynos4_device_pd[PD_MFC],
+       &origen_device_gpiokeys,
+       &origen_lcd_hv070wsa,
+};
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info origen_bl_gpio_info = {
+       .no             = EXYNOS4_GPD0(0),
+       .func           = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data origen_bl_data = {
+       .pwm_id         = 0,
+       .pwm_period_ns  = 1000,
+};
+
+static void s5p_tv_setup(void)
+{
+       /* Direct HPD to HDMI chip */
+       gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+}
+
+static void __init origen_power_init(void)
+{
+       gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
+       s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init origen_machine_init(void)
+{
+       origen_power_init();
+
+       s3c_i2c0_set_platdata(NULL);
+       i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+
+       /*
+        * Since sdhci instance 2 can contain a bootable media,
+        * sdhci instance 0 is registered after instance 2.
+        */
+       s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
+       s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
+
+       origen_ehci_init();
+       clk_xusbxti.rate = 24000000;
+
+       s5p_tv_setup();
+       s5p_i2c_hdmiphy_set_platdata(NULL);
+
+       s5p_fimd0_set_platdata(&origen_lcd_pdata);
+
+       platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+
+       samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+}
+
+MACHINE_START(ORIGEN, "ORIGEN")
+       /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = origen_map_io,
+       .init_machine   = origen_machine_init,
+       .timer          = &exynos4_timer,
+       .reserve        = &origen_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
new file mode 100644 (file)
index 0000000..fcf2e0e
--- /dev/null
@@ -0,0 +1,302 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4X12_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG4 |        \
+                                S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .flags          = 0,
+               .ucon           = SMDK4X12_UCON_DEFAULT,
+               .ulcon          = SMDK4X12_ULCON_DEFAULT,
+               .ufcon          = SMDK4X12_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .flags          = 0,
+               .ucon           = SMDK4X12_UCON_DEFAULT,
+               .ulcon          = SMDK4X12_ULCON_DEFAULT,
+               .ufcon          = SMDK4X12_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .flags          = 0,
+               .ucon           = SMDK4X12_UCON_DEFAULT,
+               .ulcon          = SMDK4X12_ULCON_DEFAULT,
+               .ufcon          = SMDK4X12_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .flags          = 0,
+               .ucon           = SMDK4X12_UCON_DEFAULT,
+               .ulcon          = SMDK4X12_ULCON_DEFAULT,
+               .ufcon          = SMDK4X12_UFCON_DEFAULT,
+       },
+};
+
+static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+       .max_width              = 8,
+       .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+       REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+       REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+       REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8997_buck1_data = {
+       .constraints    = {
+               .name           = "VDD_ARM_SMDK4X12",
+               .min_uV         = 925000,
+               .max_uV         = 1350000,
+               .always_on      = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+       .constraints    = {
+               .name           = "VDD_INT_SMDK4X12",
+               .min_uV         = 950000,
+               .max_uV         = 1150000,
+               .always_on      = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+       .constraints    = {
+               .name           = "VDD_G3D_SMDK4X12",
+               .min_uV         = 950000,
+               .max_uV         = 1150000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                 REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &max8997_buck3,
+};
+
+static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
+       { MAX8997_BUCK1, &max8997_buck1_data },
+       { MAX8997_BUCK2, &max8997_buck2_data },
+       { MAX8997_BUCK3, &max8997_buck3_data },
+};
+
+static struct max8997_platform_data smdk4x12_max8997_pdata = {
+       .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
+       .regulators     = smdk4x12_max8997_regulators,
+
+       .buck1_voltage[0] = 1100000,    /* 1.1V */
+       .buck1_voltage[1] = 1100000,    /* 1.1V */
+       .buck1_voltage[2] = 1100000,    /* 1.1V */
+       .buck1_voltage[3] = 1100000,    /* 1.1V */
+       .buck1_voltage[4] = 1100000,    /* 1.1V */
+       .buck1_voltage[5] = 1100000,    /* 1.1V */
+       .buck1_voltage[6] = 1000000,    /* 1.0V */
+       .buck1_voltage[7] = 950000,     /* 0.95V */
+
+       .buck2_voltage[0] = 1100000,    /* 1.1V */
+       .buck2_voltage[1] = 1000000,    /* 1.0V */
+       .buck2_voltage[2] = 950000,     /* 0.95V */
+       .buck2_voltage[3] = 900000,     /* 0.9V */
+       .buck2_voltage[4] = 1100000,    /* 1.1V */
+       .buck2_voltage[5] = 1000000,    /* 1.0V */
+       .buck2_voltage[6] = 950000,     /* 0.95V */
+       .buck2_voltage[7] = 900000,     /* 0.9V */
+
+       .buck5_voltage[0] = 1100000,    /* 1.1V */
+       .buck5_voltage[1] = 1100000,    /* 1.1V */
+       .buck5_voltage[2] = 1100000,    /* 1.1V */
+       .buck5_voltage[3] = 1100000,    /* 1.1V */
+       .buck5_voltage[4] = 1100000,    /* 1.1V */
+       .buck5_voltage[5] = 1100000,    /* 1.1V */
+       .buck5_voltage[6] = 1100000,    /* 1.1V */
+       .buck5_voltage[7] = 1100000,    /* 1.1V */
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
+       {
+               I2C_BOARD_INFO("max8997", 0x66),
+               .platform_data  = &smdk4x12_max8997_pdata,
+       }
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
+       { I2C_BOARD_INFO("wm8994", 0x1a), }
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
+       /* nothing here yet */
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
+       /* nothing here yet */
+};
+
+static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
+       .no = EXYNOS4_GPD0(1),
+       .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4x12_bl_data = {
+       .pwm_id = 1,
+       .pwm_period_ns  = 1000,
+};
+
+static uint32_t smdk4x12_keymap[] __initdata = {
+       /* KEY(row, col, keycode) */
+       KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+       KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
+       .keymap         = smdk4x12_keymap,
+       .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
+};
+
+static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
+       .keymap_data    = &smdk4x12_keymap_data,
+       .rows           = 2,
+       .cols           = 5,
+};
+
+static struct platform_device *smdk4x12_devices[] __initdata = {
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc3,
+       &s3c_device_i2c0,
+       &s3c_device_i2c1,
+       &s3c_device_i2c3,
+       &s3c_device_i2c7,
+       &s3c_device_rtc,
+       &s3c_device_wdt,
+       &samsung_device_keypad,
+};
+
+static void __init smdk4x12_map_io(void)
+{
+       clk_xusbxti.rate = 24000000;
+
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(clk_xusbxti.rate);
+       s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
+}
+
+static void __init smdk4x12_machine_init(void)
+{
+       s3c_i2c0_set_platdata(NULL);
+       i2c_register_board_info(0, smdk4x12_i2c_devs0,
+                               ARRAY_SIZE(smdk4x12_i2c_devs0));
+
+       s3c_i2c1_set_platdata(NULL);
+       i2c_register_board_info(1, smdk4x12_i2c_devs1,
+                               ARRAY_SIZE(smdk4x12_i2c_devs1));
+
+       s3c_i2c3_set_platdata(NULL);
+       i2c_register_board_info(3, smdk4x12_i2c_devs3,
+                               ARRAY_SIZE(smdk4x12_i2c_devs3));
+
+       s3c_i2c7_set_platdata(NULL);
+       i2c_register_board_info(7, smdk4x12_i2c_devs7,
+                               ARRAY_SIZE(smdk4x12_i2c_devs7));
+
+       samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+
+       samsung_keypad_set_platdata(&smdk4x12_keypad_data);
+
+       s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
+       s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
+
+       platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
+}
+
+MACHINE_START(SMDK4212, "SMDK4212")
+       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = smdk4x12_map_io,
+       .init_machine   = smdk4x12_machine_init,
+       .timer          = &exynos4_timer,
+MACHINE_END
+
+MACHINE_START(SMDK4412, "SMDK4412")
+       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+       /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = smdk4x12_map_io,
+       .init_machine   = smdk4x12_machine_init,
+       .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
new file mode 100644 (file)
index 0000000..cec2afa
--- /dev/null
@@ -0,0 +1,390 @@
+/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/lcd.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/pwm_backlight.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/keypad.h>
+#include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+#include <plat/mfc.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKV310_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG4 |        \
+                                S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .flags          = 0,
+               .ucon           = SMDKV310_UCON_DEFAULT,
+               .ulcon          = SMDKV310_ULCON_DEFAULT,
+               .ufcon          = SMDKV310_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .flags          = 0,
+               .ucon           = SMDKV310_UCON_DEFAULT,
+               .ulcon          = SMDKV310_ULCON_DEFAULT,
+               .ufcon          = SMDKV310_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .flags          = 0,
+               .ucon           = SMDKV310_UCON_DEFAULT,
+               .ulcon          = SMDKV310_ULCON_DEFAULT,
+               .ufcon          = SMDKV310_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .flags          = 0,
+               .ucon           = SMDKV310_UCON_DEFAULT,
+               .ulcon          = SMDKV310_ULCON_DEFAULT,
+               .ufcon          = SMDKV310_UFCON_DEFAULT,
+       },
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+       .max_width              = 8,
+       .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_GPIO,
+       .ext_cd_gpio            = EXYNOS4_GPK0(2),
+       .ext_cd_gpio_invert     = 1,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+       .max_width              = 8,
+       .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_GPIO,
+       .ext_cd_gpio            = EXYNOS4_GPK2(2),
+       .ext_cd_gpio_invert     = 1,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+                                  unsigned int power)
+{
+       if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+               gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+               gpio_free(EXYNOS4_GPD0(1));
+#endif
+               /* fire nRESET on power up */
+               gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+               gpio_direction_output(EXYNOS4_GPX0(6), 1);
+               mdelay(100);
+
+               gpio_set_value(EXYNOS4_GPX0(6), 0);
+               mdelay(10);
+
+               gpio_set_value(EXYNOS4_GPX0(6), 1);
+               mdelay(10);
+
+               gpio_free(EXYNOS4_GPX0(6));
+       } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+               gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+               gpio_free(EXYNOS4_GPD0(1));
+#endif
+       }
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+       .set_power              = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+       .name                   = "platform-lcd",
+       .dev.parent             = &s5p_device_fimd0.dev,
+       .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 13,
+               .right_margin   = 8,
+               .upper_margin   = 7,
+               .lower_margin   = 5,
+               .hsync_len      = 3,
+               .vsync_len      = 1,
+               .xres           = 800,
+               .yres           = 480,
+       },
+       .max_bpp                = 32,
+       .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+       .win[0]         = &smdkv310_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct resource smdkv310_smsc911x_resources[] = {
+       [0] = {
+               .start  = EXYNOS4_PA_SROM_BANK(1),
+               .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_EINT(5),
+               .end    = IRQ_EINT(5),
+               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+       },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+       .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+       .phy_interface  = PHY_INTERFACE_MODE_MII,
+       .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkv310_smsc911x = {
+       .name           = "smsc911x",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
+       .resource       = smdkv310_smsc911x_resources,
+       .dev            = {
+               .platform_data  = &smsc9215_config,
+       },
+};
+
+static uint32_t smdkv310_keymap[] __initdata = {
+       /* KEY(row, col, keycode) */
+       KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+       KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+       KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+       KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
+       .keymap         = smdkv310_keymap,
+       .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
+};
+
+static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
+       .keymap_data    = &smdkv310_keymap_data,
+       .rows           = 2,
+       .cols           = 8,
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+       {I2C_BOARD_INFO("wm8994", 0x1a),},
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata smdkv310_ehci_pdata;
+
+static void __init smdkv310_ehci_init(void)
+{
+       struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
+
+       s5p_ehci_set_platdata(pdata);
+}
+
+static struct platform_device *smdkv310_devices[] __initdata = {
+       &s3c_device_hsmmc0,
+       &s3c_device_hsmmc1,
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc3,
+       &s3c_device_i2c1,
+       &s5p_device_i2c_hdmiphy,
+       &s3c_device_rtc,
+       &s3c_device_wdt,
+       &s5p_device_ehci,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &exynos4_device_ac97,
+       &exynos4_device_i2s0,
+       &samsung_device_keypad,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
+       &exynos4_device_pd[PD_MFC],
+       &exynos4_device_pd[PD_G3D],
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_LCD1],
+       &exynos4_device_pd[PD_CAM],
+       &exynos4_device_pd[PD_TV],
+       &exynos4_device_pd[PD_GPS],
+       &exynos4_device_spdif,
+       &exynos4_device_sysmmu,
+       &samsung_asoc_dma,
+       &samsung_asoc_idma,
+       &s5p_device_fimd0,
+       &smdkv310_lcd_lte480wv,
+       &smdkv310_smsc911x,
+       &exynos4_device_ahci,
+       &s5p_device_hdmi,
+       &s5p_device_mixer,
+};
+
+static void __init smdkv310_smsc911x_init(void)
+{
+       u32 cs1;
+
+       /* configure nCS1 width to 16 bits */
+       cs1 = __raw_readl(S5P_SROM_BW) &
+               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+               (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+               S5P_SROM_BW__NCS1__SHIFT;
+       __raw_writel(cs1, S5P_SROM_BW);
+
+       /* set timing for nCS1 suitable for ethernet chip */
+       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
+       .no = EXYNOS4_GPD0(1),
+       .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkv310_bl_data = {
+       .pwm_id = 1,
+       .pwm_period_ns  = 1000,
+};
+
+static void s5p_tv_setup(void)
+{
+       /* direct HPD to HDMI chip */
+       WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+       /* setup dependencies between TV devices */
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
+static void __init smdkv310_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+}
+
+static void __init smdkv310_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init smdkv310_machine_init(void)
+{
+       s3c_i2c1_set_platdata(NULL);
+       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+       smdkv310_smsc911x_init();
+
+       s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
+       s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
+       s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
+       s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+
+       s5p_tv_setup();
+       s5p_i2c_hdmiphy_set_platdata(NULL);
+
+       samsung_keypad_set_platdata(&smdkv310_keypad_data);
+
+       samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+       s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+
+       smdkv310_ehci_init();
+       clk_xusbxti.rate = 24000000;
+
+       platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+}
+
+MACHINE_START(SMDKV310, "SMDKV310")
+       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+       /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = smdkv310_map_io,
+       .init_machine   = smdkv310_machine_init,
+       .timer          = &exynos4_timer,
+       .reserve        = &smdkv310_reserve,
+MACHINE_END
+
+MACHINE_START(SMDKC210, "SMDKC210")
+       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = smdkv310_map_io,
+       .init_machine   = smdkv310_machine_init,
+       .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
new file mode 100644 (file)
index 0000000..a2a177f
--- /dev/null
@@ -0,0 +1,1064 @@
+/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/fb.h>
+#include <linux/mfd/max8998.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/max8952.h>
+#include <linux/mmc/host.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/mcs.h>
+#include <linux/i2c/atmel_mxt_ts.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/fb.h>
+#include <plat/mfc.h>
+#include <plat/sdhci.h>
+#include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
+
+#include <mach/map.h>
+
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+#include <media/m5mols.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define UNIVERSAL_ULCON_DEFAULT        S3C2410_LCON_CS8
+
+#define UNIVERSAL_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG256 |      \
+                                S5PV210_UFCON_RXTRIG256)
+
+static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .ucon           = UNIVERSAL_UCON_DEFAULT,
+               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .ucon           = UNIVERSAL_UCON_DEFAULT,
+               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .ucon           = UNIVERSAL_UCON_DEFAULT,
+               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .ucon           = UNIVERSAL_UCON_DEFAULT,
+               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+       },
+};
+
+static struct regulator_consumer_supply max8952_consumer =
+       REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct max8952_platform_data universal_max8952_pdata __initdata = {
+       .gpio_vid0      = EXYNOS4_GPX0(3),
+       .gpio_vid1      = EXYNOS4_GPX0(4),
+       .gpio_en        = -1, /* Not controllable, set "Always High" */
+       .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
+       .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
+       .sync_freq      = 0, /* default: fastest */
+       .ramp_speed     = 0, /* default: fastest */
+
+       .reg_data       = {
+               .constraints    = {
+                       .name           = "VARM_1.2V",
+                       .min_uV         = 770000,
+                       .max_uV         = 1400000,
+                       .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                       .always_on      = 1,
+                       .boot_on        = 1,
+               },
+               .num_consumer_supplies  = 1,
+               .consumer_supplies      = &max8952_consumer,
+       },
+};
+
+static struct regulator_consumer_supply lp3974_buck1_consumer =
+       REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply lp3974_buck2_consumer =
+       REGULATOR_SUPPLY("vddg3d", NULL);
+
+static struct regulator_consumer_supply lp3974_buck3_consumer =
+       REGULATOR_SUPPLY("vdet", "s5p-sdo");
+
+static struct regulator_init_data lp3974_buck1_data = {
+       .constraints    = {
+               .name           = "VINT_1.1V",
+               .min_uV         = 750000,
+               .max_uV         = 1500000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                       REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &lp3974_buck1_consumer,
+};
+
+static struct regulator_init_data lp3974_buck2_data = {
+       .constraints    = {
+               .name           = "VG3D_1.1V",
+               .min_uV         = 750000,
+               .max_uV         = 1500000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                       REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &lp3974_buck2_consumer,
+};
+
+static struct regulator_init_data lp3974_buck3_data = {
+       .constraints    = {
+               .name           = "VCC_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &lp3974_buck3_consumer,
+};
+
+static struct regulator_init_data lp3974_buck4_data = {
+       .constraints    = {
+               .name           = "VMEM_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_ldo2_data = {
+       .constraints    = {
+               .name           = "VALIVE_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
+       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
+};
+
+static struct regulator_init_data lp3974_ldo3_data = {
+       .constraints    = {
+               .name           = "VUSB+MIPI_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
+       .consumer_supplies = lp3974_ldo3_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
+       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
+};
+
+static struct regulator_init_data lp3974_ldo4_data = {
+       .constraints    = {
+               .name           = "VADC_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
+       .consumer_supplies = lp3974_ldo4_consumer,
+};
+
+static struct regulator_init_data lp3974_ldo5_data = {
+       .constraints    = {
+               .name           = "VTF_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_ldo6_data = {
+       .constraints    = {
+               .name           = "LDO6",
+               .min_uV         = 2000000,
+               .max_uV         = 2000000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
+       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
+};
+
+static struct regulator_init_data lp3974_ldo7_data = {
+       .constraints    = {
+               .name           = "VLCD+VMIPI_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
+       .consumer_supplies      = lp3974_ldo7_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
+       REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
+};
+
+static struct regulator_init_data lp3974_ldo8_data = {
+       .constraints    = {
+               .name           = "VUSB+VDAC_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
+       .consumer_supplies = lp3974_ldo8_consumer,
+};
+
+static struct regulator_init_data lp3974_ldo9_data = {
+       .constraints    = {
+               .name           = "VCC_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_ldo10_data = {
+       .constraints    = {
+               .name           = "VPLL_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .boot_on        = 1,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_consumer_supply lp3974_ldo11_consumer =
+       REGULATOR_SUPPLY("dig_28", "0-001f");
+
+static struct regulator_init_data lp3974_ldo11_data = {
+       .constraints    = {
+               .name           = "CAM_AF_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo11_consumer,
+};
+
+static struct regulator_init_data lp3974_ldo12_data = {
+       .constraints    = {
+               .name           = "PS_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_ldo13_data = {
+       .constraints    = {
+               .name           = "VHIC_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_consumer_supply lp3974_ldo14_consumer =
+       REGULATOR_SUPPLY("dig_18", "0-001f");
+
+static struct regulator_init_data lp3974_ldo14_data = {
+       .constraints    = {
+               .name           = "CAM_I_HOST_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo14_consumer,
+};
+
+
+static struct regulator_consumer_supply lp3974_ldo15_consumer =
+       REGULATOR_SUPPLY("dig_12", "0-001f");
+
+static struct regulator_init_data lp3974_ldo15_data = {
+       .constraints    = {
+               .name           = "CAM_S_DIG+FM33_CORE_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo15_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+       REGULATOR_SUPPLY("a_sensor", "0-001f"),
+};
+
+static struct regulator_init_data lp3974_ldo16_data = {
+       .constraints    = {
+               .name           = "CAM_S_ANA_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
+       .consumer_supplies      = lp3974_ldo16_consumer,
+};
+
+static struct regulator_init_data lp3974_ldo17_data = {
+       .constraints    = {
+               .name           = "VCC_3.0V_LCD",
+               .min_uV         = 3000000,
+               .max_uV         = 3000000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_32khz_ap_data = {
+       .constraints    = {
+               .name           = "32KHz AP",
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_32khz_cp_data = {
+       .constraints    = {
+               .name           = "32KHz CP",
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_vichg_data = {
+       .constraints    = {
+               .name           = "VICHG",
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_esafeout1_data = {
+       .constraints    = {
+               .name           = "SAFEOUT1",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data lp3974_esafeout2_data = {
+       .constraints    = {
+               .name           = "SAFEOUT2",
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct max8998_regulator_data lp3974_regulators[] = {
+       { MAX8998_LDO2,  &lp3974_ldo2_data },
+       { MAX8998_LDO3,  &lp3974_ldo3_data },
+       { MAX8998_LDO4,  &lp3974_ldo4_data },
+       { MAX8998_LDO5,  &lp3974_ldo5_data },
+       { MAX8998_LDO6,  &lp3974_ldo6_data },
+       { MAX8998_LDO7,  &lp3974_ldo7_data },
+       { MAX8998_LDO8,  &lp3974_ldo8_data },
+       { MAX8998_LDO9,  &lp3974_ldo9_data },
+       { MAX8998_LDO10, &lp3974_ldo10_data },
+       { MAX8998_LDO11, &lp3974_ldo11_data },
+       { MAX8998_LDO12, &lp3974_ldo12_data },
+       { MAX8998_LDO13, &lp3974_ldo13_data },
+       { MAX8998_LDO14, &lp3974_ldo14_data },
+       { MAX8998_LDO15, &lp3974_ldo15_data },
+       { MAX8998_LDO16, &lp3974_ldo16_data },
+       { MAX8998_LDO17, &lp3974_ldo17_data },
+       { MAX8998_BUCK1, &lp3974_buck1_data },
+       { MAX8998_BUCK2, &lp3974_buck2_data },
+       { MAX8998_BUCK3, &lp3974_buck3_data },
+       { MAX8998_BUCK4, &lp3974_buck4_data },
+       { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
+       { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
+       { MAX8998_ENVICHG, &lp3974_vichg_data },
+       { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
+       { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
+};
+
+static struct max8998_platform_data universal_lp3974_pdata = {
+       .num_regulators         = ARRAY_SIZE(lp3974_regulators),
+       .regulators             = lp3974_regulators,
+       .buck1_voltage1         = 1100000,      /* INT */
+       .buck1_voltage2         = 1000000,
+       .buck1_voltage3         = 1100000,
+       .buck1_voltage4         = 1000000,
+       .buck1_set1             = EXYNOS4_GPX0(5),
+       .buck1_set2             = EXYNOS4_GPX0(6),
+       .buck2_voltage1         = 1200000,      /* G3D */
+       .buck2_voltage2         = 1100000,
+       .buck1_default_idx      = 0,
+       .buck2_set3             = EXYNOS4_GPE2(0),
+       .buck2_default_idx      = 0,
+       .wakeup                 = true,
+};
+
+
+enum fixed_regulator_id {
+       FIXED_REG_ID_MMC0,
+       FIXED_REG_ID_HDMI_5V,
+       FIXED_REG_ID_CAM_S_IF,
+       FIXED_REG_ID_CAM_I_CORE,
+       FIXED_REG_ID_CAM_VT_DIO,
+};
+
+static struct regulator_consumer_supply hdmi_fixed_consumer =
+       REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
+
+static struct regulator_init_data hdmi_fixed_voltage_init_data = {
+       .constraints            = {
+               .name           = "HDMI_5V",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &hdmi_fixed_consumer,
+};
+
+static struct fixed_voltage_config hdmi_fixed_voltage_config = {
+       .supply_name            = "HDMI_EN1",
+       .microvolts             = 5000000,
+       .gpio                   = EXYNOS4_GPE0(1),
+       .enable_high            = true,
+       .init_data              = &hdmi_fixed_voltage_init_data,
+};
+
+static struct platform_device hdmi_fixed_voltage = {
+       .name                   = "reg-fixed-voltage",
+       .id                     = FIXED_REG_ID_HDMI_5V,
+       .dev                    = {
+               .platform_data  = &hdmi_fixed_voltage_config,
+       },
+};
+
+/* GPIO I2C 5 (PMIC) */
+static struct i2c_board_info i2c5_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("max8952", 0xC0 >> 1),
+               .platform_data  = &universal_max8952_pdata,
+       }, {
+               I2C_BOARD_INFO("lp3974", 0xCC >> 1),
+               .platform_data  = &universal_lp3974_pdata,
+       },
+};
+
+/* I2C3 (TSP) */
+static struct mxt_platform_data qt602240_platform_data = {
+       .x_line         = 19,
+       .y_line         = 11,
+       .x_size         = 800,
+       .y_size         = 480,
+       .blen           = 0x11,
+       .threshold      = 0x28,
+       .voltage        = 2800000,              /* 2.8V */
+       .orient         = MXT_DIAGONAL,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("qt602240_ts", 0x4a),
+               .platform_data = &qt602240_platform_data,
+       },
+};
+
+static void __init universal_tsp_init(void)
+{
+       int gpio;
+
+       /* TSP_LDO_ON: XMDMADDR_11 */
+       gpio = EXYNOS4_GPE2(3);
+       gpio_request(gpio, "TSP_LDO_ON");
+       gpio_direction_output(gpio, 1);
+       gpio_export(gpio, 0);
+
+       /* TSP_INT: XMDMADDR_7 */
+       gpio = EXYNOS4_GPE1(7);
+       gpio_request(gpio, "TSP_INT");
+
+       s5p_register_gpio_interrupt(gpio);
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+       i2c3_devs[0].irq = gpio_to_irq(gpio);
+}
+
+
+/* GPIO I2C 12 (3 Touchkey) */
+static uint32_t touchkey_keymap[] = {
+       /* MCS_KEY_MAP(value, keycode) */
+       MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
+       MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
+};
+
+static struct mcs_platform_data touchkey_data = {
+       .keymap         = touchkey_keymap,
+       .keymap_size    = ARRAY_SIZE(touchkey_keymap),
+       .key_maxval     = 2,
+};
+
+/* GPIO I2C 3_TOUCH 2.8V */
+#define I2C_GPIO_BUS_12                12
+static struct i2c_gpio_platform_data i2c_gpio12_data = {
+       .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
+       .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
+};
+
+static struct platform_device i2c_gpio12 = {
+       .name           = "i2c-gpio",
+       .id             = I2C_GPIO_BUS_12,
+       .dev            = {
+               .platform_data  = &i2c_gpio12_data,
+       },
+};
+
+static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
+               .platform_data = &touchkey_data,
+       },
+};
+
+static void __init universal_touchkey_init(void)
+{
+       int gpio;
+
+       gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
+       gpio_request(gpio, "3_TOUCH_INT");
+       s5p_register_gpio_interrupt(gpio);
+       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+       i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
+
+       gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
+       gpio_request(gpio, "3_TOUCH_EN");
+       gpio_direction_output(gpio, 1);
+}
+
+static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
+       .frequency      = 300 * 1000,
+       .sda_delay      = 200,
+};
+
+/* GPIO KEYS */
+static struct gpio_keys_button universal_gpio_keys_tables[] = {
+       {
+               .code                   = KEY_VOLUMEUP,
+               .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
+               .desc                   = "gpio-keys: KEY_VOLUMEUP",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_VOLUMEDOWN,
+               .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
+               .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_CONFIG,
+               .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
+               .desc                   = "gpio-keys: KEY_CONFIG",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_CAMERA,
+               .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
+               .desc                   = "gpio-keys: KEY_CAMERA",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_OK,
+               .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
+               .desc                   = "gpio-keys: KEY_OK",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .debounce_interval      = 1,
+       },
+};
+
+static struct gpio_keys_platform_data universal_gpio_keys_data = {
+       .buttons        = universal_gpio_keys_tables,
+       .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
+};
+
+static struct platform_device universal_gpio_keys = {
+       .name                   = "gpio-keys",
+       .dev                    = {
+               .platform_data  = &universal_gpio_keys_data,
+       },
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
+       .max_width              = 8,
+       .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                               MMC_CAP_DISABLE),
+       .cd_type                = S3C_SDHCI_CD_PERMANENT,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply mmc0_supplies[] = {
+       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
+static struct regulator_init_data mmc0_fixed_voltage_init_data = {
+       .constraints            = {
+               .name           = "VMEM_VDD_2.8V",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
+       .consumer_supplies      = mmc0_supplies,
+};
+
+static struct fixed_voltage_config mmc0_fixed_voltage_config = {
+       .supply_name            = "MASSMEMORY_EN",
+       .microvolts             = 2800000,
+       .gpio                   = EXYNOS4_GPE1(3),
+       .enable_high            = true,
+       .init_data              = &mmc0_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc0_fixed_voltage = {
+       .name                   = "reg-fixed-voltage",
+       .id                     = FIXED_REG_ID_MMC0,
+       .dev                    = {
+               .platform_data  = &mmc0_fixed_voltage_config,
+       },
+};
+
+/* SD */
+static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
+       .max_width              = 4,
+       .host_caps              = MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                               MMC_CAP_DISABLE,
+       .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
+       .ext_cd_gpio_invert     = 1,
+       .cd_type                = S3C_SDHCI_CD_GPIO,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WiFi */
+static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
+       .max_width              = 4,
+       .host_caps              = MMC_CAP_4_BIT_DATA |
+                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                               MMC_CAP_DISABLE,
+       .cd_type                = S3C_SDHCI_CD_EXTERNAL,
+};
+
+static void __init universal_sdhci_init(void)
+{
+       s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
+       s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
+       s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
+}
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+       /* Gyro, To be updated */
+};
+
+/* Frame Buffer */
+static struct s3c_fb_pd_win universal_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 16,
+               .right_margin   = 16,
+               .upper_margin   = 2,
+               .lower_margin   = 28,
+               .hsync_len      = 2,
+               .vsync_len      = 1,
+               .xres           = 480,
+               .yres           = 800,
+               .refresh        = 55,
+       },
+       .max_bpp        = 32,
+       .default_bpp    = 16,
+};
+
+static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
+       .win[0]         = &universal_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                         VIDCON0_CLKSEL_LCD,
+       .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+                         | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct regulator_consumer_supply cam_i_core_supply =
+       REGULATOR_SUPPLY("core", "0-001f");
+
+static struct regulator_init_data cam_i_core_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &cam_i_core_supply,
+};
+
+static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
+       .supply_name    = "CAM_I_CORE_1.2V",
+       .microvolts     = 1200000,
+       .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_i_core_reg_init_data,
+};
+
+static struct platform_device cam_i_core_fixed_reg_dev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
+       .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply cam_s_if_supply =
+       REGULATOR_SUPPLY("d_sensor", "0-001f");
+
+static struct regulator_init_data cam_s_if_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &cam_s_if_supply,
+};
+
+static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
+       .supply_name    = "CAM_S_IF_1.8V",
+       .microvolts     = 1800000,
+       .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
+       .enable_high    = 1,
+       .init_data      = &cam_s_if_reg_init_data,
+};
+
+static struct platform_device cam_s_if_fixed_reg_dev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
+       .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+       .clk_rate       = 166000000UL,
+       .lanes          = 2,
+       .alignment      = 32,
+       .hs_settle      = 12,
+       .phy_enable     = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_LEVEL_EN(n)   EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPX1(5) /* XEINT_13 */
+#define GPIO_CAM_MEGA_nRST     EXYNOS4_GPE2(5)
+
+static int m5mols_set_power(struct device *dev, int on)
+{
+       gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
+       gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+       return 0;
+}
+
+static struct m5mols_platform_data m5mols_platdata = {
+       .gpio_reset     = GPIO_CAM_MEGA_nRST,
+       .reset_polarity = 0,
+       .set_power      = m5mols_set_power,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+       I2C_BOARD_INFO("M5MOLS", 0x1F),
+       .platform_data = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info universal_camera_sensors[] = {
+       {
+               .mux_id         = 0,
+               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
+               .bus_type       = FIMC_MIPI_CSI2,
+               .board_info     = &m5mols_board_info,
+               .i2c_bus_num    = 0,
+               .clk_frequency  = 21600000UL,
+               .csi_data_align = 32,
+       },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+       .isp_info       = universal_camera_sensors,
+       .num_clients    = ARRAY_SIZE(universal_camera_sensors),
+};
+
+static struct gpio universal_camera_gpios[] = {
+       { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
+       { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
+       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
+       { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
+};
+
+static void universal_camera_init(void)
+{
+       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+                        &s5p_device_mipi_csis0);
+       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
+                        &s5p_device_fimc_md);
+
+       if (gpio_request_array(universal_camera_gpios,
+                              ARRAY_SIZE(universal_camera_gpios))) {
+               pr_err("%s: GPIO request failed\n", __func__);
+               return;
+       }
+
+       if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
+               m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
+       else
+               pr_err("Failed to configure 8M_ISP_INT GPIO\n");
+
+       /* Free GPIOs controlled directly by the sensor drivers. */
+       gpio_free(GPIO_CAM_MEGA_nRST);
+       gpio_free(GPIO_CAM_8M_ISP_INT);
+
+       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
+               pr_err("Camera port A setup failed\n");
+}
+
+static struct platform_device *universal_devices[] __initdata = {
+       /* Samsung Platform Devices */
+       &s5p_device_mipi_csis0,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &mmc0_fixed_voltage,
+       &s3c_device_hsmmc0,
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc3,
+       &s3c_device_i2c0,
+       &s3c_device_i2c3,
+       &s3c_device_i2c5,
+       &s5p_device_i2c_hdmiphy,
+       &hdmi_fixed_voltage,
+       &exynos4_device_pd[PD_TV],
+       &s5p_device_hdmi,
+       &s5p_device_sdo,
+       &s5p_device_mixer,
+
+       /* Universal Devices */
+       &i2c_gpio12,
+       &universal_gpio_keys,
+       &s5p_device_onenand,
+       &s5p_device_fimd0,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
+       &exynos4_device_pd[PD_MFC],
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_CAM],
+       &cam_i_core_fixed_reg_dev,
+       &cam_s_if_fixed_reg_dev,
+       &s5p_device_fimc_md,
+};
+
+static void __init universal_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+}
+
+void s5p_tv_setup(void)
+{
+       /* direct HPD to HDMI chip */
+       gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
+
+       gpio_direction_input(EXYNOS4_GPX3(7));
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+       /* setup dependencies between TV devices */
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
+static void __init universal_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init universal_machine_init(void)
+{
+       universal_sdhci_init();
+       s5p_tv_setup();
+
+       s3c_i2c0_set_platdata(&universal_i2c0_platdata);
+       i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+       universal_tsp_init();
+       s3c_i2c3_set_platdata(NULL);
+       i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+
+       s3c_i2c5_set_platdata(NULL);
+       s5p_i2c_hdmiphy_set_platdata(NULL);
+       i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+
+       s5p_fimd0_set_platdata(&universal_lcd_pdata);
+
+       universal_touchkey_init();
+       i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
+                       ARRAY_SIZE(i2c_gpio12_devs));
+
+       universal_camera_init();
+
+       /* Last */
+       platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+}
+
+MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
+       /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = universal_map_io,
+       .init_machine   = universal_machine_init,
+       .timer          = &exynos4_timer,
+       .reserve        = &universal_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
new file mode 100644 (file)
index 0000000..97343df
--- /dev/null
@@ -0,0 +1,471 @@
+/* linux/arch/arm/mach-exynos4/mct.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 MCT(Multi-Core Timer) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/percpu.h>
+
+#include <asm/hardware/gic.h>
+
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/regs-mct.h>
+#include <asm/mach/time.h>
+
+enum {
+       MCT_INT_SPI,
+       MCT_INT_PPI
+};
+
+static unsigned long clk_cnt_per_tick;
+static unsigned long clk_rate;
+static unsigned int mct_int_type;
+
+struct mct_clock_event_device {
+       struct clock_event_device *evt;
+       void __iomem *base;
+       char name[10];
+};
+
+static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
+
+static void exynos4_mct_write(unsigned int value, void *addr)
+{
+       void __iomem *stat_addr;
+       u32 mask;
+       u32 i;
+
+       __raw_writel(value, addr);
+
+       if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+               u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+               switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+               case (u32) MCT_L_TCON_OFFSET:
+                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                       mask = 1 << 3;          /* L_TCON write status */
+                       break;
+               case (u32) MCT_L_ICNTB_OFFSET:
+                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                       mask = 1 << 1;          /* L_ICNTB write status */
+                       break;
+               case (u32) MCT_L_TCNTB_OFFSET:
+                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                       mask = 1 << 0;          /* L_TCNTB write status */
+                       break;
+               default:
+                       return;
+               }
+       } else {
+               switch ((u32) addr) {
+               case (u32) EXYNOS4_MCT_G_TCON:
+                       stat_addr = EXYNOS4_MCT_G_WSTAT;
+                       mask = 1 << 16;         /* G_TCON write status */
+                       break;
+               case (u32) EXYNOS4_MCT_G_COMP0_L:
+                       stat_addr = EXYNOS4_MCT_G_WSTAT;
+                       mask = 1 << 0;          /* G_COMP0_L write status */
+                       break;
+               case (u32) EXYNOS4_MCT_G_COMP0_U:
+                       stat_addr = EXYNOS4_MCT_G_WSTAT;
+                       mask = 1 << 1;          /* G_COMP0_U write status */
+                       break;
+               case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                       stat_addr = EXYNOS4_MCT_G_WSTAT;
+                       mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
+                       break;
+               case (u32) EXYNOS4_MCT_G_CNT_L:
+                       stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                       mask = 1 << 0;          /* G_CNT_L write status */
+                       break;
+               case (u32) EXYNOS4_MCT_G_CNT_U:
+                       stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                       mask = 1 << 1;          /* G_CNT_U write status */
+                       break;
+               default:
+                       return;
+               }
+       }
+
+       /* Wait maximum 1 ms until written values are applied */
+       for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
+               if (__raw_readl(stat_addr) & mask) {
+                       __raw_writel(mask, stat_addr);
+                       return;
+               }
+
+       panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+}
+
+/* Clocksource handling */
+static void exynos4_mct_frc_start(u32 hi, u32 lo)
+{
+       u32 reg;
+
+       exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
+       exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
+
+       reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+       reg |= MCT_G_TCON_START;
+       exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
+}
+
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+       unsigned int lo, hi;
+       u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+
+       do {
+               hi = hi2;
+               lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
+               hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+       } while (hi != hi2);
+
+       return ((cycle_t)hi << 32) | lo;
+}
+
+static void exynos4_frc_resume(struct clocksource *cs)
+{
+       exynos4_mct_frc_start(0, 0);
+}
+
+struct clocksource mct_frc = {
+       .name           = "mct-frc",
+       .rating         = 400,
+       .read           = exynos4_frc_read,
+       .mask           = CLOCKSOURCE_MASK(64),
+       .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+       .resume         = exynos4_frc_resume,
+};
+
+static void __init exynos4_clocksource_init(void)
+{
+       exynos4_mct_frc_start(0, 0);
+
+       if (clocksource_register_hz(&mct_frc, clk_rate))
+               panic("%s: can't register clocksource\n", mct_frc.name);
+}
+
+static void exynos4_mct_comp0_stop(void)
+{
+       unsigned int tcon;
+
+       tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+       tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
+
+       exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
+       exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
+}
+
+static void exynos4_mct_comp0_start(enum clock_event_mode mode,
+                                   unsigned long cycles)
+{
+       unsigned int tcon;
+       cycle_t comp_cycle;
+
+       tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+
+       if (mode == CLOCK_EVT_MODE_PERIODIC) {
+               tcon |= MCT_G_TCON_COMP0_AUTO_INC;
+               exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
+       }
+
+       comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
+       exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
+       exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
+
+       exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
+
+       tcon |= MCT_G_TCON_COMP0_ENABLE;
+       exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
+}
+
+static int exynos4_comp_set_next_event(unsigned long cycles,
+                                      struct clock_event_device *evt)
+{
+       exynos4_mct_comp0_start(evt->mode, cycles);
+
+       return 0;
+}
+
+static void exynos4_comp_set_mode(enum clock_event_mode mode,
+                                 struct clock_event_device *evt)
+{
+       exynos4_mct_comp0_stop();
+
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+       case CLOCK_EVT_MODE_RESUME:
+               break;
+       }
+}
+
+static struct clock_event_device mct_comp_device = {
+       .name           = "mct-comp",
+       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+       .rating         = 250,
+       .set_next_event = exynos4_comp_set_next_event,
+       .set_mode       = exynos4_comp_set_mode,
+};
+
+static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
+{
+       struct clock_event_device *evt = dev_id;
+
+       exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
+
+       evt->event_handler(evt);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction mct_comp_event_irq = {
+       .name           = "mct_comp_irq",
+       .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+       .handler        = exynos4_mct_comp_isr,
+       .dev_id         = &mct_comp_device,
+};
+
+static void exynos4_clockevent_init(void)
+{
+       clk_cnt_per_tick = clk_rate / 2 / HZ;
+
+       clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+       mct_comp_device.max_delta_ns =
+               clockevent_delta2ns(0xffffffff, &mct_comp_device);
+       mct_comp_device.min_delta_ns =
+               clockevent_delta2ns(0xf, &mct_comp_device);
+       mct_comp_device.cpumask = cpumask_of(0);
+       clockevents_register_device(&mct_comp_device);
+
+       setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+}
+
+#ifdef CONFIG_LOCAL_TIMERS
+/* Clock event handling */
+static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
+{
+       unsigned long tmp;
+       unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
+       void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+
+       tmp = __raw_readl(addr);
+       if (tmp & mask) {
+               tmp &= ~mask;
+               exynos4_mct_write(tmp, addr);
+       }
+}
+
+static void exynos4_mct_tick_start(unsigned long cycles,
+                                  struct mct_clock_event_device *mevt)
+{
+       unsigned long tmp;
+
+       exynos4_mct_tick_stop(mevt);
+
+       tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
+
+       /* update interrupt count buffer */
+       exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
+
+       /* enable MCT tick interrupt */
+       exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
+
+       tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+       tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
+              MCT_L_TCON_INTERVAL_MODE;
+       exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
+}
+
+static int exynos4_tick_set_next_event(unsigned long cycles,
+                                      struct clock_event_device *evt)
+{
+       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+
+       exynos4_mct_tick_start(cycles, mevt);
+
+       return 0;
+}
+
+static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
+                                        struct clock_event_device *evt)
+{
+       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+
+       exynos4_mct_tick_stop(mevt);
+
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+       case CLOCK_EVT_MODE_RESUME:
+               break;
+       }
+}
+
+static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+{
+       struct clock_event_device *evt = mevt->evt;
+
+       /*
+        * This is for supporting oneshot mode.
+        * Mct would generate interrupt periodically
+        * without explicit stopping.
+        */
+       if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
+               exynos4_mct_tick_stop(mevt);
+
+       /* Clear the MCT tick interrupt */
+       if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+               exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+               return 1;
+       } else {
+               return 0;
+       }
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+       struct mct_clock_event_device *mevt = dev_id;
+       struct clock_event_device *evt = mevt->evt;
+
+       exynos4_mct_tick_clear(mevt);
+
+       evt->event_handler(evt);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction mct_tick0_event_irq = {
+       .name           = "mct_tick0_irq",
+       .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+       .handler        = exynos4_mct_tick_isr,
+};
+
+static struct irqaction mct_tick1_event_irq = {
+       .name           = "mct_tick1_irq",
+       .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+       .handler        = exynos4_mct_tick_isr,
+};
+
+static void exynos4_mct_tick_init(struct clock_event_device *evt)
+{
+       struct mct_clock_event_device *mevt;
+       unsigned int cpu = smp_processor_id();
+
+       mevt = this_cpu_ptr(&percpu_mct_tick);
+       mevt->evt = evt;
+
+       mevt->base = EXYNOS4_MCT_L_BASE(cpu);
+       sprintf(mevt->name, "mct_tick%d", cpu);
+
+       evt->name = mevt->name;
+       evt->cpumask = cpumask_of(cpu);
+       evt->set_next_event = exynos4_tick_set_next_event;
+       evt->set_mode = exynos4_tick_set_mode;
+       evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+       evt->rating = 450;
+
+       clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+       evt->max_delta_ns =
+               clockevent_delta2ns(0x7fffffff, evt);
+       evt->min_delta_ns =
+               clockevent_delta2ns(0xf, evt);
+
+       clockevents_register_device(evt);
+
+       exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
+
+       if (mct_int_type == MCT_INT_SPI) {
+               if (cpu == 0) {
+                       mct_tick0_event_irq.dev_id = mevt;
+                       evt->irq = IRQ_MCT_L0;
+                       setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+               } else {
+                       mct_tick1_event_irq.dev_id = mevt;
+                       evt->irq = IRQ_MCT_L1;
+                       setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                       irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+               }
+       } else {
+               enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
+       }
+}
+
+/* Setup the local clock events for a CPU */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+       exynos4_mct_tick_init(evt);
+
+       return 0;
+}
+
+void local_timer_stop(struct clock_event_device *evt)
+{
+       evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+       if (mct_int_type == MCT_INT_SPI)
+               disable_irq(evt->irq);
+       else
+               disable_percpu_irq(IRQ_MCT_LOCALTIMER);
+}
+#endif /* CONFIG_LOCAL_TIMERS */
+
+static void __init exynos4_timer_resources(void)
+{
+       struct clk *mct_clk;
+       mct_clk = clk_get(NULL, "xtal");
+
+       clk_rate = clk_get_rate(mct_clk);
+
+       if (mct_int_type == MCT_INT_PPI) {
+               int err;
+
+               err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+                                        exynos4_mct_tick_isr, "MCT",
+                                        &percpu_mct_tick);
+               WARN(err, "MCT: can't request IRQ %d (%d)\n",
+                    IRQ_MCT_LOCALTIMER, err);
+       }
+}
+
+static void __init exynos4_timer_init(void)
+{
+       if (soc_is_exynos4210())
+               mct_int_type = MCT_INT_SPI;
+       else
+               mct_int_type = MCT_INT_PPI;
+
+       exynos4_timer_resources();
+       exynos4_clocksource_init();
+       exynos4_clockevent_init();
+}
+
+struct sys_timer exynos4_timer = {
+       .init           = exynos4_timer_init,
+};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
new file mode 100644 (file)
index 0000000..0559540
--- /dev/null
@@ -0,0 +1,225 @@
+/* linux/arch/arm/mach-exynos4/platsmp.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/unified.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+
+#include <plat/cpu.h>
+
+extern unsigned int gic_bank_offset;
+extern void exynos4_secondary_startup(void);
+
+#define CPU1_BOOT_REG          (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                               S5P_INFORM5 : S5P_VA_SYSRAM)
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+
+volatile int __cpuinitdata pen_release = -1;
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+       pen_release = val;
+       smp_wmb();
+       __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+       outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+       return (void __iomem *)(S5P_VA_SCU);
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit exynos4_gic_secondary_init(void)
+{
+       void __iomem *dist_base = S5P_VA_GIC_DIST +
+                               (gic_bank_offset * smp_processor_id());
+       void __iomem *cpu_base = S5P_VA_GIC_CPU +
+                               (gic_bank_offset * smp_processor_id());
+       int i;
+
+       /*
+        * Deal with the banked PPI and SGI interrupts - disable all
+        * PPI interrupts, ensure all SGI interrupts are enabled.
+        */
+       __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+       __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+       /*
+        * Set priority on PPI and SGI interrupts
+        */
+       for (i = 0; i < 32; i += 4)
+               __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
+       __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
+       __raw_writel(1, cpu_base + GIC_CPU_CTRL);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+       /*
+        * if any interrupts are already enabled for the primary
+        * core (e.g. timer irq), then they will not have been enabled
+        * for us: do so
+        */
+       exynos4_gic_secondary_init();
+
+       /*
+        * let the primary processor know we're out of the
+        * pen, then head off into the C entry point
+        */
+       write_pen_release(-1);
+
+       /*
+        * Synchronise with the boot thread.
+        */
+       spin_lock(&boot_lock);
+       spin_unlock(&boot_lock);
+
+       set_cpu_online(cpu, true);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+       unsigned long timeout;
+
+       /*
+        * Set synchronisation state between this boot processor
+        * and the secondary one
+        */
+       spin_lock(&boot_lock);
+
+       /*
+        * The secondary processor is waiting to be released from
+        * the holding pen - release it, then wait for it to flag
+        * that it has been released by resetting pen_release.
+        *
+        * Note that "pen_release" is the hardware CPU ID, whereas
+        * "cpu" is Linux's internal ID.
+        */
+       write_pen_release(cpu_logical_map(cpu));
+
+       if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+               __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                            S5P_ARM_CORE1_CONFIGURATION);
+
+               timeout = 10;
+
+               /* wait max 10 ms until cpu1 is on */
+               while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                       & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+                       if (timeout-- == 0)
+                               break;
+
+                       mdelay(1);
+               }
+
+               if (timeout == 0) {
+                       printk(KERN_ERR "cpu1 power enable failed");
+                       spin_unlock(&boot_lock);
+                       return -ETIMEDOUT;
+               }
+       }
+       /*
+        * Send the secondary CPU a soft interrupt, thereby causing
+        * the boot monitor to read the system wide flags register,
+        * and branch to the address found there.
+        */
+
+       timeout = jiffies + (1 * HZ);
+       while (time_before(jiffies, timeout)) {
+               smp_rmb();
+
+               __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                       CPU1_BOOT_REG);
+               gic_raise_softirq(cpumask_of(cpu), 1);
+
+               if (pen_release == -1)
+                       break;
+
+               udelay(10);
+       }
+
+       /*
+        * now the secondary core is starting up let it run its
+        * calibrations, then wait for it to finish
+        */
+       spin_unlock(&boot_lock);
+
+       return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+
+void __init smp_init_cpus(void)
+{
+       void __iomem *scu_base = scu_base_addr();
+       unsigned int i, ncores;
+
+       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+       /* sanity check */
+       if (ncores > nr_cpu_ids) {
+               pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                       ncores, nr_cpu_ids);
+               ncores = nr_cpu_ids;
+       }
+
+       for (i = 0; i < ncores; i++)
+               set_cpu_possible(i, true);
+
+       set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+
+       scu_enable(scu_base_addr());
+
+       /*
+        * Write the address of secondary startup into the
+        * system-wide flags register. The boot monitor waits
+        * until it receives a soft interrupt, and then the
+        * secondary CPU branches to this address.
+        */
+       __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                       CPU1_BOOT_REG);
+}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
new file mode 100644 (file)
index 0000000..509a435
--- /dev/null
@@ -0,0 +1,428 @@
+/* linux/arch/arm/mach-exynos4/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4210 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/pll.h>
+#include <plat/regs-srom.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/pm-core.h>
+#include <mach/pmu.h>
+
+static struct sleep_save exynos4_set_clksrc[] = {
+       { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
+       { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
+       { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
+       { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
+       { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
+       { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
+       { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
+       { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
+       { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
+};
+
+static struct sleep_save exynos4210_set_clksrc[] = {
+       { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+};
+
+static struct sleep_save exynos4_epll_save[] = {
+       SAVE_ITEM(S5P_EPLL_CON0),
+       SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+       SAVE_ITEM(S5P_VPLL_CON0),
+       SAVE_ITEM(S5P_VPLL_CON1),
+};
+
+static struct sleep_save exynos4_core_save[] = {
+       /* GIC side */
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
+       SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
+       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
+       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+
+       /* SROM side */
+       SAVE_ITEM(S5P_SROM_BW),
+       SAVE_ITEM(S5P_SROM_BC0),
+       SAVE_ITEM(S5P_SROM_BC1),
+       SAVE_ITEM(S5P_SROM_BC2),
+       SAVE_ITEM(S5P_SROM_BC3),
+};
+
+static struct sleep_save exynos4_l2cc_save[] = {
+       SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
+       SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
+       SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
+       SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
+       SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
+};
+
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
+static int exynos4_cpu_suspend(unsigned long arg)
+{
+       outer_flush_all();
+
+       /* issue the standby signal into the pm unit. */
+       cpu_do_idle();
+
+       /* we should never get past here */
+       panic("sleep resumed to originator?");
+}
+
+static void exynos4_pm_prepare(void)
+{
+       u32 tmp;
+
+       s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+       s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+       s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+       s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
+
+       tmp = __raw_readl(S5P_INFORM1);
+
+       /* Set value of power down register for sleep mode */
+
+       exynos4_sys_powerdown_conf(SYS_SLEEP);
+       __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+
+       /* ensure at least INFORM0 has the resume address */
+
+       __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+
+       /* Before enter central sequence mode, clock src register have to set */
+
+       s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+
+       if (soc_is_exynos4210())
+               s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
+}
+
+static int exynos4_pm_add(struct sys_device *sysdev)
+{
+       pm_cpu_prep = exynos4_pm_prepare;
+       pm_cpu_sleep = exynos4_cpu_suspend;
+
+       return 0;
+}
+
+/* This function copy from linux/arch/arm/kernel/smp_scu.c */
+
+void exynos4_scu_enable(void __iomem *scu_base)
+{
+       u32 scu_ctrl;
+
+       scu_ctrl = __raw_readl(scu_base);
+       /* already enabled? */
+       if (scu_ctrl & 1)
+               return;
+
+       scu_ctrl |= 1;
+       __raw_writel(scu_ctrl, scu_base);
+
+       /*
+        * Ensure that the data accessed by CPU0 before the SCU was
+        * initialised is visible to the other CPUs.
+        */
+       flush_cache_all();
+}
+
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+       unsigned long pll_con, locktime, lockcnt;
+       unsigned long pll_in_rate;
+       unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+       if (pll_base_rate == 0)
+               return;
+
+       pll_in_rate = pll_base_rate;
+
+       /* EPLL */
+       pll_con = exynos4_epll_save[0].val;
+
+       if (pll_con & (1 << 31)) {
+               pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+               p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+               pll_in_rate /= 1000000;
+
+               locktime = (3000 / pll_in_rate) * p_div;
+               lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+               __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+               s3c_pm_do_restore_core(exynos4_epll_save,
+                                       ARRAY_SIZE(exynos4_epll_save));
+               epll_wait = 1;
+       }
+
+       pll_in_rate = pll_base_rate;
+
+       /* VPLL */
+       pll_con = exynos4_vpll_save[0].val;
+
+       if (pll_con & (1 << 31)) {
+               pll_in_rate /= 1000000;
+               /* 750us */
+               locktime = 750;
+               lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+               __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+               s3c_pm_do_restore_core(exynos4_vpll_save,
+                                       ARRAY_SIZE(exynos4_vpll_save));
+               vpll_wait = 1;
+       }
+
+       /* Wait PLL locking */
+
+       do {
+               if (epll_wait) {
+                       pll_con = __raw_readl(S5P_EPLL_CON0);
+                       if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                               epll_wait = 0;
+               }
+
+               if (vpll_wait) {
+                       pll_con = __raw_readl(S5P_VPLL_CON0);
+                       if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                               vpll_wait = 0;
+               }
+       } while (epll_wait || vpll_wait);
+}
+
+static struct sysdev_driver exynos4_pm_driver = {
+       .add            = exynos4_pm_add,
+};
+
+static __init int exynos4_pm_drvinit(void)
+{
+       struct clk *pll_base;
+       unsigned int tmp;
+
+       s3c_pm_init();
+
+       /* All wakeup disable */
+
+       tmp = __raw_readl(S5P_WAKEUP_MASK);
+       tmp |= ((0xFF << 8) | (0x1F << 1));
+       __raw_writel(tmp, S5P_WAKEUP_MASK);
+
+       pll_base = clk_get(NULL, "xtal");
+
+       if (!IS_ERR(pll_base)) {
+               pll_base_rate = clk_get_rate(pll_base);
+               clk_put(pll_base);
+       }
+
+       return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
+}
+arch_initcall(exynos4_pm_drvinit);
+
+static int exynos4_pm_suspend(void)
+{
+       unsigned long tmp;
+
+       /* Setting Central Sequence Register for power down mode */
+
+       tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+       tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+       __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+       if (soc_is_exynos4212()) {
+               tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+               tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
+                        S5P_USE_STANDBYWFE_ISP_ARM);
+               __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+       }
+
+       /* Save Power control register */
+       asm ("mrc p15, 0, %0, c15, c0, 0"
+            : "=r" (tmp) : : "cc");
+       save_arm_register[0] = tmp;
+
+       /* Save Diagnostic register */
+       asm ("mrc p15, 0, %0, c15, c0, 1"
+            : "=r" (tmp) : : "cc");
+       save_arm_register[1] = tmp;
+
+       return 0;
+}
+
+static void exynos4_pm_resume(void)
+{
+       unsigned long tmp;
+
+       /*
+        * If PMU failed while entering sleep mode, WFI will be
+        * ignored by PMU and then exiting cpu_do_idle().
+        * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+        * in this situation.
+        */
+       tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+       if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+               tmp |= S5P_CENTRAL_LOWPWR_CFG;
+               __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+               /* No need to perform below restore code */
+               goto early_wakeup;
+       }
+       /* Restore Power control register */
+       tmp = save_arm_register[0];
+       asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+                     : : "r" (tmp)
+                     : "cc");
+
+       /* Restore Diagnostic register */
+       tmp = save_arm_register[1];
+       asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+                     : : "r" (tmp)
+                     : "cc");
+
+       /* For release retention */
+
+       __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+       __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+
+       s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+
+       exynos4_restore_pll();
+
+       exynos4_scu_enable(S5P_VA_SCU);
+
+#ifdef CONFIG_CACHE_L2X0
+       s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+       outer_inv_all();
+       /* enable L2X0*/
+       writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
+#endif
+
+early_wakeup:
+       return;
+}
+
+static struct syscore_ops exynos4_pm_syscore_ops = {
+       .suspend        = exynos4_pm_suspend,
+       .resume         = exynos4_pm_resume,
+};
+
+static __init int exynos4_pm_syscore_init(void)
+{
+       register_syscore_ops(&exynos4_pm_syscore_ops);
+       return 0;
+}
+arch_initcall(exynos4_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
new file mode 100644 (file)
index 0000000..bba48f5
--- /dev/null
@@ -0,0 +1,230 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+       /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+       { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+       { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+       { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+       { PMU_TABLE_END,},
+};
+
+static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ISP_ARM_LOWPWR,                   { 0x1, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,     { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,   { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+       { S5P_L2_0_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+       /* XXX_OPTION register should be set other field */
+       { S5P_ARM_L2_0_OPTION,                  { 0x10, 0x10, 0x0 } },
+       { S5P_L2_1_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+       { S5P_ARM_L2_1_OPTION,                  { 0x10, 0x10, 0x0 } },
+       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+       { S5P_DRAM_FREQ_DOWN_LOWPWR,            { 0x1, 0x1, 0x1 } },
+       { S5P_DDRPHY_DLLOFF_LOWPWR,             { 0x1, 0x1, 0x1 } },
+       { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,        { 0x1, 0x1, 0x1 } },
+       { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_COREBLK_LOWPWR,         { 0x1, 0x1, 0x0 } },
+       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_MPLLUSER_SYSCLK_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_ISP_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_ISP_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+       { S5P_TOP_BUS_COREBLK_LOWPWR,           { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_COREBLK_LOWPWR,           { 0x3, 0x0, 0x3 } },
+       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_OSCCLK_GATE_LOWPWR,               { 0x1, 0x0, 0x1 } },
+       { S5P_LOGIC_RESET_COREBLK_LOWPWR,       { 0x1, 0x1, 0x0 } },
+       { S5P_OSCCLK_GATE_COREBLK_LOWPWR,       { 0x1, 0x0, 0x1 } },
+       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_ONENAND_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_HSI_MEM_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_HSI_MEM_OPTION,                   { 0x10, 0x10, 0x0 } },
+       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_G2D_ACP_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+       { S5P_USBOTG_MEM_OPTION,                { 0x10, 0x10, 0x0 } },
+       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_HSMMC_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_CSSYS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_SECSS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_ROTATOR_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_ROTATOR_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_ISOLATION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_COREBLK_LOWPWR,         { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_TOP_ASB_RESET_LOWPWR,             { 0x1, 0x1, 0x1 } },
+       { S5P_TOP_ASB_ISOLATION_LOWPWR,         { 0x1, 0x0, 0x1 } },
+       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_ISP_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+       { S5P_CMU_SYSCLK_ISP_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SYSCLK_GPS_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { PMU_TABLE_END,},
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+       unsigned int i;
+
+       for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
+               __raw_writel(exynos4_pmu_config[i].val[mode],
+                               exynos4_pmu_config[i].reg);
+}
+
+static int __init exynos4_pmu_init(void)
+{
+       exynos4_pmu_config = exynos4210_pmu_config;
+
+       if (soc_is_exynos4210()) {
+               exynos4_pmu_config = exynos4210_pmu_config;
+               pr_info("EXYNOS4210 PMU Initialize\n");
+       } else if (soc_is_exynos4212()) {
+               exynos4_pmu_config = exynos4212_pmu_config;
+               pr_info("EXYNOS4212 PMU Initialize\n");
+       } else {
+               pr_info("EXYNOS4: PMU not supported\n");
+       }
+
+       return 0;
+}
+arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
new file mode 100644 (file)
index 0000000..6a45078
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * Exynos4 camera interface GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/camport.h>
+
+int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
+{
+       u32 gpio8, gpio5;
+       u32 sfn;
+       int ret;
+
+       switch (id) {
+       case S5P_CAMPORT_A:
+               gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
+               gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
+               sfn = S3C_GPIO_SFN(2);
+               break;
+
+       case S5P_CAMPORT_B:
+               gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
+               gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
+               sfn = S3C_GPIO_SFN(3);
+               break;
+
+       default:
+               WARN(1, "Wrong camport id: %d\n", id);
+               return -EINVAL;
+       }
+
+       ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
+       if (ret)
+               return ret;
+
+       return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
new file mode 100644 (file)
index 0000000..07a6dbe
--- /dev/null
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos4/setup-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 FIMD 0 configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
+
+#include <mach/map.h>
+
+void exynos4_fimd0_gpio_setup_24bpp(void)
+{
+       unsigned int reg;
+
+       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
+       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
+       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
+       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
+
+       /*
+        * Set DISPLAY_CONTROL register for Display path selection.
+        *
+        * DISPLAY_CONTROL[1:0]
+        * ---------------------
+        *  00 | MIE
+        *  01 | MDINE
+        *  10 | FIMD : selected
+        *  11 | FIMD
+        */
+       reg = __raw_readl(S3C_VA_SYS + 0x0210);
+       reg |= (1 << 1);
+       __raw_writel(reg, S3C_VA_SYS + 0x0210);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
new file mode 100644 (file)
index 0000000..d395bd1
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c0.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * I2C0 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
+                             S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
new file mode 100644 (file)
index 0000000..fd7235a
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c1.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C1 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
+                             S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
new file mode 100644 (file)
index 0000000..2694b19
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c2.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C2 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c2_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
+                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
new file mode 100644 (file)
index 0000000..379bd30
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C3 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c3_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
+                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
new file mode 100644 (file)
index 0000000..9f3c048
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C4 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c4_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
new file mode 100644 (file)
index 0000000..77e1a1e
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c5.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C5 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c5_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
+                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
new file mode 100644 (file)
index 0000000..284d12b
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C6 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c6_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
+                             S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
new file mode 100644 (file)
index 0000000..b7611ee
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-exynos4/setup-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C7 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c7_cfg_gpio(struct platform_device *dev)
+{
+       s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
+                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
new file mode 100644 (file)
index 0000000..7862bfb
--- /dev/null
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-exynos4/setup-keypad.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * GPIO configuration for Exynos4 KeyPad device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+       /* Keypads can be of various combinations, Just making sure */
+
+       if (rows > 8) {
+               /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
+               s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
+                                       S3C_GPIO_PULL_UP);
+
+               /* Set all the necessary GPX3 pins: KP_ROW[8~] */
+               s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
+                                        S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+       } else {
+               /* Set all the necessary GPX2 pins: KP_ROW[x] */
+               s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
+                                       S3C_GPIO_PULL_UP);
+       }
+
+       /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
+       s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
new file mode 100644 (file)
index 0000000..e8d08bf
--- /dev/null
@@ -0,0 +1,152 @@
+/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+       unsigned int gpio;
+
+       /* Set all the necessary GPK0[0:1] pins to special-function 2 */
+       for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       switch (width) {
+       case 8:
+               for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+                       /* Data pin GPK1[3:6] to special-function 3 */
+                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+               }
+       case 4:
+               for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
+                       /* Data pin GPK0[3:6] to special-function 2 */
+                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+               }
+       default:
+               break;
+       }
+
+       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+               s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+}
+
+void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+       unsigned int gpio;
+
+       /* Set all the necessary GPK1[0:1] pins to special-function 2 */
+       for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
+               /* Data pin GPK1[3:6] to special-function 2 */
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+               s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+}
+
+void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+       unsigned int gpio;
+
+       /* Set all the necessary GPK2[0:1] pins to special-function 2 */
+       for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       switch (width) {
+       case 8:
+               for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
+                       /* Data pin GPK3[3:6] to special-function 3 */
+                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+               }
+       case 4:
+               for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
+                       /* Data pin GPK2[3:6] to special-function 2 */
+                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+               }
+       default:
+               break;
+       }
+
+       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+               s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+}
+
+void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+       unsigned int gpio;
+
+       /* Set all the necessary GPK3[0:1] pins to special-function 2 */
+       for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
+               /* Data pin GPK3[3:6] to special-function 2 */
+               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+
+       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+               s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
+               s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
+               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+       }
+}
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
new file mode 100644 (file)
index 0000000..92937b4
--- /dev/null
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos4/setup-sdhci.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *exynos4_hsmmc_clksrcs[4] = {
+       [0] = NULL,
+       [1] = NULL,
+       [2] = "sclk_mmc",       /* mmc_bus */
+       [3] = NULL,
+};
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
new file mode 100644 (file)
index 0000000..39aca04
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-usb-phy.h>
+#include <plat/cpu.h>
+#include <plat/usb-phy.h>
+
+static int exynos4_usb_phy1_init(struct platform_device *pdev)
+{
+       struct clk *otg_clk;
+       struct clk *xusbxti_clk;
+       u32 phyclk;
+       u32 rstcon;
+       int err;
+
+       otg_clk = clk_get(&pdev->dev, "otg");
+       if (IS_ERR(otg_clk)) {
+               dev_err(&pdev->dev, "Failed to get otg clock\n");
+               return PTR_ERR(otg_clk);
+       }
+
+       err = clk_enable(otg_clk);
+       if (err) {
+               clk_put(otg_clk);
+               return err;
+       }
+
+       writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
+                       S5P_USBHOST_PHY_CONTROL);
+
+       /* set clock frequency for PLL */
+       phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
+
+       xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+       if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
+               switch (clk_get_rate(xusbxti_clk)) {
+               case 12 * MHZ:
+                       phyclk |= CLKSEL_12M;
+                       break;
+               case 24 * MHZ:
+                       phyclk |= CLKSEL_24M;
+                       break;
+               default:
+               case 48 * MHZ:
+                       /* default reference clock */
+                       break;
+               }
+               clk_put(xusbxti_clk);
+       }
+
+       writel(phyclk, EXYNOS4_PHYCLK);
+
+       /* floating prevention logic: disable */
+       writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
+
+       /* set to normal HSIC 0 and 1 of PHY1 */
+       writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
+                       EXYNOS4_PHYPWR);
+
+       /* set to normal standard USB of PHY1 */
+       writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
+
+       /* reset all ports of both PHY and Link */
+       rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
+               PHY1_SWRST_MASK;
+       writel(rstcon, EXYNOS4_RSTCON);
+       udelay(10);
+
+       rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
+       writel(rstcon, EXYNOS4_RSTCON);
+       udelay(80);
+
+       clk_disable(otg_clk);
+       clk_put(otg_clk);
+
+       return 0;
+}
+
+static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+{
+       struct clk *otg_clk;
+       int err;
+
+       otg_clk = clk_get(&pdev->dev, "otg");
+       if (IS_ERR(otg_clk)) {
+               dev_err(&pdev->dev, "Failed to get otg clock\n");
+               return PTR_ERR(otg_clk);
+       }
+
+       err = clk_enable(otg_clk);
+       if (err) {
+               clk_put(otg_clk);
+               return err;
+       }
+
+       writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
+                       EXYNOS4_PHYPWR);
+
+       writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
+                       S5P_USBHOST_PHY_CONTROL);
+
+       clk_disable(otg_clk);
+       clk_put(otg_clk);
+
+       return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+       if (type == S5P_USB_PHY_HOST)
+               return exynos4_usb_phy1_init(pdev);
+
+       return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+       if (type == S5P_USB_PHY_HOST)
+               return exynos4_usb_phy1_exit(pdev);
+
+       return -EINVAL;
+}
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
deleted file mode 100644 (file)
index 51cff04..0000000
+++ /dev/null
@@ -1,329 +0,0 @@
-# arch/arm/mach-exynos4/Kconfig
-#
-# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
-#              http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-# Configuration options for the EXYNOS4
-
-if ARCH_EXYNOS4
-
-config CPU_EXYNOS4210
-       bool
-       select SAMSUNG_DMADEV
-       select ARM_CPU_SUSPEND if PM
-       select S5P_PM if PM
-       select S5P_SLEEP if PM
-       help
-         Enable EXYNOS4210 CPU support
-
-config SOC_EXYNOS4212
-       bool
-       select ARM_CPU_SUSPEND if PM
-       select S5P_PM if PM
-       select S5P_SLEEP if PM
-       help
-         Enable EXYNOS4212 SoC support
-
-config SOC_EXYNOS4412
-       bool
-       help
-         Enable EXYNOS4412 SoC support
-
-config EXYNOS4_MCT
-       bool
-       default y
-       help
-         Use MCT (Multi Core Timer) as kernel timers
-
-config EXYNOS4_DEV_AHCI
-       bool
-       help
-         Compile in platform device definitions for AHCI
-
-config EXYNOS4_SETUP_FIMD0
-       bool
-       help
-         Common setup code for FIMD0.
-
-config EXYNOS4_DEV_PD
-       bool
-       help
-         Compile in platform device definitions for Power Domain
-
-config EXYNOS4_DEV_SYSMMU
-       bool
-       help
-         Common setup code for SYSTEM MMU in EXYNOS4
-
-config EXYNOS4_DEV_DWMCI
-       bool
-       help
-         Compile in platform device definitions for DWMCI
-
-config EXYNOS4_SETUP_I2C1
-       bool
-       help
-         Common setup code for i2c bus 1.
-
-config EXYNOS4_SETUP_I2C2
-       bool
-       help
-         Common setup code for i2c bus 2.
-
-config EXYNOS4_SETUP_I2C3
-       bool
-       help
-         Common setup code for i2c bus 3.
-
-config EXYNOS4_SETUP_I2C4
-       bool
-       help
-         Common setup code for i2c bus 4.
-
-config EXYNOS4_SETUP_I2C5
-       bool
-       help
-         Common setup code for i2c bus 5.
-
-config EXYNOS4_SETUP_I2C6
-       bool
-       help
-         Common setup code for i2c bus 6.
-
-config EXYNOS4_SETUP_I2C7
-       bool
-       help
-         Common setup code for i2c bus 7.
-
-config EXYNOS4_SETUP_KEYPAD
-       bool
-       help
-         Common setup code for keypad.
-
-config EXYNOS4_SETUP_SDHCI
-       bool
-       select EXYNOS4_SETUP_SDHCI_GPIO
-       help
-         Internal helper functions for EXYNOS4 based SDHCI systems.
-
-config EXYNOS4_SETUP_SDHCI_GPIO
-       bool
-       help
-         Common setup code for SDHCI gpio.
-
-config EXYNOS4_SETUP_FIMC
-       bool
-       help
-         Common setup code for the camera interfaces.
-
-config EXYNOS4_SETUP_USB_PHY
-       bool
-       help
-         Common setup code for USB PHY controller
-
-# machine support
-
-menu "EXYNOS4 Machines"
-
-comment "EXYNOS4210 Boards"
-
-config MACH_SMDKC210
-       bool "SMDKC210"
-       select MACH_SMDKV310
-       help
-         Machine support for Samsung SMDKC210
-
-config MACH_SMDKV310
-       bool "SMDKV310"
-       select CPU_EXYNOS4210
-       select S5P_DEV_FIMD0
-       select S3C_DEV_RTC
-       select S3C_DEV_WDT
-       select S3C_DEV_I2C1
-       select S5P_DEV_FIMC0
-       select S5P_DEV_FIMC1
-       select S5P_DEV_FIMC2
-       select S5P_DEV_FIMC3
-       select S5P_DEV_I2C_HDMIPHY
-       select S5P_DEV_MFC
-       select S5P_DEV_TV
-       select S5P_DEV_USB_EHCI
-       select S3C_DEV_HSMMC
-       select S3C_DEV_HSMMC1
-       select S3C_DEV_HSMMC2
-       select S3C_DEV_HSMMC3
-       select SAMSUNG_DEV_BACKLIGHT
-       select EXYNOS4_DEV_AHCI
-       select SAMSUNG_DEV_KEYPAD
-       select EXYNOS4_DEV_PD
-       select SAMSUNG_DEV_PWM
-       select EXYNOS4_DEV_SYSMMU
-       select EXYNOS4_SETUP_FIMD0
-       select EXYNOS4_SETUP_I2C1
-       select EXYNOS4_SETUP_KEYPAD
-       select EXYNOS4_SETUP_SDHCI
-       select EXYNOS4_SETUP_USB_PHY
-       help
-         Machine support for Samsung SMDKV310
-
-config MACH_ARMLEX4210
-       bool "ARMLEX4210"
-       select CPU_EXYNOS4210
-       select S3C_DEV_RTC
-       select S3C_DEV_WDT
-       select S3C_DEV_HSMMC
-       select S3C_DEV_HSMMC2
-       select S3C_DEV_HSMMC3
-       select EXYNOS4_DEV_AHCI
-       select EXYNOS4_DEV_SYSMMU
-       select EXYNOS4_SETUP_SDHCI
-       help
-         Machine support for Samsung ARMLEX4210 based on EXYNOS4210
-
-config MACH_UNIVERSAL_C210
-       bool "Mobile UNIVERSAL_C210 Board"
-       select CPU_EXYNOS4210
-       select S5P_GPIO_INT
-       select S5P_DEV_FIMC0
-       select S5P_DEV_FIMC1
-       select S5P_DEV_FIMC2
-       select S5P_DEV_FIMC3
-       select S5P_DEV_CSIS0
-       select S5P_DEV_FIMD0
-       select S3C_DEV_HSMMC
-       select S3C_DEV_HSMMC2
-       select S3C_DEV_HSMMC3
-       select S3C_DEV_I2C1
-       select S3C_DEV_I2C3
-       select S3C_DEV_I2C5
-       select S5P_DEV_I2C_HDMIPHY
-       select S5P_DEV_MFC
-       select S5P_DEV_ONENAND
-       select S5P_DEV_TV
-       select EXYNOS4_DEV_PD
-       select EXYNOS4_SETUP_FIMD0
-       select EXYNOS4_SETUP_I2C1
-       select EXYNOS4_SETUP_I2C3
-       select EXYNOS4_SETUP_I2C5
-       select EXYNOS4_SETUP_SDHCI
-       select EXYNOS4_SETUP_FIMC
-       select S5P_SETUP_MIPIPHY
-       help
-         Machine support for Samsung Mobile Universal S5PC210 Reference
-         Board.
-
-config MACH_NURI
-       bool "Mobile NURI Board"
-       select CPU_EXYNOS4210
-       select S5P_GPIO_INT
-       select S3C_DEV_WDT
-       select S3C_DEV_RTC
-       select S5P_DEV_FIMD0
-       select S3C_DEV_HSMMC
-       select S3C_DEV_HSMMC2
-       select S3C_DEV_HSMMC3
-       select S3C_DEV_I2C1
-       select S3C_DEV_I2C3
-       select S3C_DEV_I2C5
-       select S5P_DEV_CSIS0
-       select S5P_DEV_FIMC0
-       select S5P_DEV_FIMC1
-       select S5P_DEV_FIMC2
-       select S5P_DEV_FIMC3
-       select S5P_DEV_MFC
-       select S5P_DEV_USB_EHCI
-       select S5P_SETUP_MIPIPHY
-       select EXYNOS4_DEV_PD
-       select EXYNOS4_SETUP_FIMC
-       select EXYNOS4_SETUP_FIMD0
-       select EXYNOS4_SETUP_I2C1
-       select EXYNOS4_SETUP_I2C3
-       select EXYNOS4_SETUP_I2C5
-       select EXYNOS4_SETUP_SDHCI
-       select EXYNOS4_SETUP_USB_PHY
-       select S5P_SETUP_MIPIPHY
-       select SAMSUNG_DEV_PWM
-       select SAMSUNG_DEV_ADC
-       help
-         Machine support for Samsung Mobile NURI Board.
-
-config MACH_ORIGEN
-       bool "ORIGEN"
-       select CPU_EXYNOS4210
-       select S3C_DEV_RTC
-       select S3C_DEV_WDT
-       select S3C_DEV_HSMMC
-       select S3C_DEV_HSMMC2
-       select S5P_DEV_FIMC0
-       select S5P_DEV_FIMC1
-       select S5P_DEV_FIMC2
-       select S5P_DEV_FIMC3
-       select S5P_DEV_FIMD0
-       select S5P_DEV_I2C_HDMIPHY
-       select S5P_DEV_MFC
-       select S5P_DEV_TV
-       select S5P_DEV_USB_EHCI
-       select SAMSUNG_DEV_BACKLIGHT
-       select SAMSUNG_DEV_PWM
-       select EXYNOS4_DEV_PD
-       select EXYNOS4_SETUP_FIMD0
-       select EXYNOS4_SETUP_SDHCI
-       select EXYNOS4_SETUP_USB_PHY
-       help
-         Machine support for ORIGEN based on Samsung EXYNOS4210
-
-comment "EXYNOS4212 Boards"
-
-config MACH_SMDK4212
-       bool "SMDK4212"
-       select SOC_EXYNOS4212
-       select S3C_DEV_HSMMC2
-       select S3C_DEV_HSMMC3
-       select S3C_DEV_I2C1
-       select S3C_DEV_I2C3
-       select S3C_DEV_I2C7
-       select S3C_DEV_RTC
-       select S3C_DEV_WDT
-       select SAMSUNG_DEV_BACKLIGHT
-       select SAMSUNG_DEV_KEYPAD
-       select SAMSUNG_DEV_PWM
-       select EXYNOS4_SETUP_I2C1
-       select EXYNOS4_SETUP_I2C3
-       select EXYNOS4_SETUP_I2C7
-       select EXYNOS4_SETUP_KEYPAD
-       select EXYNOS4_SETUP_SDHCI
-       help
-         Machine support for Samsung SMDK4212
-
-comment "EXYNOS4412 Boards"
-
-config MACH_SMDK4412
-       bool "SMDK4412"
-       select SOC_EXYNOS4412
-       select MACH_SMDK4212
-       help
-         Machine support for Samsung SMDK4412
-
-endmenu
-
-comment "Configuration for HSMMC bus width"
-
-menu "Use 8-bit bus width"
-
-config EXYNOS4_SDHCI_CH0_8BIT
-       bool "Channel 0 with 8-bit bus"
-       help
-         Support HSMMC Channel 0 8-bit bus.
-         If selected, Channel 1 is disabled.
-
-config EXYNOS4_SDHCI_CH2_8BIT
-       bool "Channel 2 with 8-bit bus"
-       help
-         Support HSMMC Channel 2 8-bit bus.
-         If selected, Channel 3 is disabled.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
deleted file mode 100644 (file)
index 2bb18f4..0000000
+++ /dev/null
@@ -1,61 +0,0 @@
-# arch/arm/mach-exynos4/Makefile
-#
-# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
-#              http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-obj-y                          :=
-obj-m                          :=
-obj-n                          :=
-obj-                           :=
-
-# Core support for EXYNOS4 system
-
-obj-$(CONFIG_ARCH_EXYNOS4)     += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_ARCH_EXYNOS4)     += setup-i2c0.o irq-eint.o dma.o pmu.o
-obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
-obj-$(CONFIG_PM)               += pm.o
-obj-$(CONFIG_CPU_IDLE)         += cpuidle.o
-
-obj-$(CONFIG_SMP)              += platsmp.o headsmp.o
-
-obj-$(CONFIG_EXYNOS4_MCT)      += mct.o
-
-obj-$(CONFIG_HOTPLUG_CPU)      += hotplug.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDKC210)            += mach-smdkv310.o
-obj-$(CONFIG_MACH_SMDKV310)            += mach-smdkv310.o
-obj-$(CONFIG_MACH_ARMLEX4210)          += mach-armlex4210.o
-obj-$(CONFIG_MACH_UNIVERSAL_C210)      += mach-universal_c210.o
-obj-$(CONFIG_MACH_NURI)                        += mach-nuri.o
-obj-$(CONFIG_MACH_ORIGEN)              += mach-origen.o
-
-obj-$(CONFIG_MACH_SMDK4212)            += mach-smdk4x12.o
-obj-$(CONFIG_MACH_SMDK4412)            += mach-smdk4x12.o
-
-# device support
-
-obj-y                                  += dev-audio.o
-obj-$(CONFIG_EXYNOS4_DEV_AHCI)         += dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_PD)           += dev-pd.o
-obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)       += dev-sysmmu.o
-obj-$(CONFIG_EXYNOS4_DEV_DWMCI)        += dev-dwmci.o
-
-obj-$(CONFIG_EXYNOS4_SETUP_FIMC)       += setup-fimc.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)      += setup-fimd0.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C1)       += setup-i2c1.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C2)       += setup-i2c2.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C3)       += setup-i2c3.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C4)       += setup-i2c4.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C5)       += setup-i2c5.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C6)       += setup-i2c6.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C7)       += setup-i2c7.o
-obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)     += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)      += setup-sdhci.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-
-obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)    += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos4/Makefile.boot b/arch/arm/mach-exynos4/Makefile.boot
deleted file mode 100644 (file)
index b9862e2..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y  += 0x40008000
-params_phys-y  := 0x40000100
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
deleted file mode 100644 (file)
index b9d5ef6..0000000
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
-
-static struct sleep_save exynos4210_clock_save[] = {
-       SAVE_ITEM(S5P_CLKSRC_IMAGE),
-       SAVE_ITEM(S5P_CLKSRC_LCD1),
-       SAVE_ITEM(S5P_CLKDIV_IMAGE),
-       SAVE_ITEM(S5P_CLKDIV_LCD1),
-       SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-       SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
-};
-
-static struct clksrc_clk *sysclks[] = {
-       /* nothing here yet */
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-       {
-               .clk            = {
-                       .name           = "sclk_sata",
-                       .id             = -1,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_mout_corebus,
-               .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimd",
-                       .devname        = "exynos4-fb.1",
-                       .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
-       },
-};
-
-static struct clk init_clocks_off[] = {
-       {
-               .name           = "sataphy",
-               .id             = -1,
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "sata",
-               .id             = -1,
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "fimd",
-               .devname        = "exynos4-fb.1",
-               .enable         = exynos4_clk_ip_lcd1_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-       s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-       return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-       s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4210_clock_syscore_ops = {
-       .suspend        = exynos4210_clock_suspend,
-       .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-       int ptr;
-
-       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-       clk_mout_mpll.reg_src.shift = 8;
-       clk_mout_mpll.reg_src.size = 1;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-               s3c_register_clksrc(sysclks[ptr], 1);
-
-       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-       register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
deleted file mode 100644 (file)
index 77d5dec..0000000
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
-
-static struct sleep_save exynos4212_clock_save[] = {
-       SAVE_ITEM(S5P_CLKSRC_IMAGE),
-       SAVE_ITEM(S5P_CLKDIV_IMAGE),
-       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
-};
-
-static struct clk *clk_src_mpll_user_list[] = {
-       [0] = &clk_fin_mpll,
-       [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-       .sources        = clk_src_mpll_user_list,
-       .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-       .clk = {
-               .name           = "mout_mpll_user",
-       },
-       .sources        = &clk_src_mpll_user,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk *sysclks[] = {
-       &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-       /* nothing here yet */
-};
-
-static struct clk init_clocks_off[] = {
-       /* nothing here yet */
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-       s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-       return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-       s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4212_clock_syscore_ops = {
-       .suspend        = exynos4212_clock_suspend,
-       .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-       int ptr;
-
-       /* usbphy1 is removed */
-       clkset_group_list[4] = NULL;
-
-       /* mout_mpll_user is used */
-       clkset_group_list[6] = &clk_mout_mpll_user.clk;
-       clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
-       clk_mout_mpll.reg_src.shift = 12;
-       clk_mout_mpll.reg_src.size = 1;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-               s3c_register_clksrc(sysclks[ptr], 1);
-
-       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-       register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
deleted file mode 100644 (file)
index 2894f0a..0000000
+++ /dev/null
@@ -1,1491 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-
-static struct sleep_save exynos4_clock_save[] = {
-       SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-       SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-       SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-       SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-       SAVE_ITEM(S5P_CLKSRC_TOP0),
-       SAVE_ITEM(S5P_CLKSRC_TOP1),
-       SAVE_ITEM(S5P_CLKSRC_CAM),
-       SAVE_ITEM(S5P_CLKSRC_TV),
-       SAVE_ITEM(S5P_CLKSRC_MFC),
-       SAVE_ITEM(S5P_CLKSRC_G3D),
-       SAVE_ITEM(S5P_CLKSRC_LCD0),
-       SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-       SAVE_ITEM(S5P_CLKSRC_FSYS),
-       SAVE_ITEM(S5P_CLKSRC_PERIL0),
-       SAVE_ITEM(S5P_CLKSRC_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV_CAM),
-       SAVE_ITEM(S5P_CLKDIV_TV),
-       SAVE_ITEM(S5P_CLKDIV_MFC),
-       SAVE_ITEM(S5P_CLKDIV_G3D),
-       SAVE_ITEM(S5P_CLKDIV_LCD0),
-       SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-       SAVE_ITEM(S5P_CLKDIV_FSYS0),
-       SAVE_ITEM(S5P_CLKDIV_FSYS1),
-       SAVE_ITEM(S5P_CLKDIV_FSYS2),
-       SAVE_ITEM(S5P_CLKDIV_FSYS3),
-       SAVE_ITEM(S5P_CLKDIV_PERIL0),
-       SAVE_ITEM(S5P_CLKDIV_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV_PERIL2),
-       SAVE_ITEM(S5P_CLKDIV_PERIL3),
-       SAVE_ITEM(S5P_CLKDIV_PERIL4),
-       SAVE_ITEM(S5P_CLKDIV_PERIL5),
-       SAVE_ITEM(S5P_CLKDIV_TOP),
-       SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-       SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-       SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-       SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-       SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-       SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV2_RATIO),
-       SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-       SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-       SAVE_ITEM(S5P_CLKGATE_IP_TV),
-       SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-       SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-       SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-       SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-       SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-       SAVE_ITEM(S5P_CLKGATE_BLOCK),
-       SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-       SAVE_ITEM(S5P_CLKSRC_DMC),
-       SAVE_ITEM(S5P_CLKDIV_DMC0),
-       SAVE_ITEM(S5P_CLKDIV_DMC1),
-       SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-       SAVE_ITEM(S5P_CLKSRC_CPU),
-       SAVE_ITEM(S5P_CLKDIV_CPU),
-       SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-       SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-       SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-
-struct clk clk_sclk_hdmi27m = {
-       .name           = "sclk_hdmi27m",
-       .rate           = 27000000,
-};
-
-struct clk clk_sclk_hdmiphy = {
-       .name           = "sclk_hdmiphy",
-};
-
-struct clk clk_sclk_usbphy0 = {
-       .name           = "sclk_usbphy0",
-       .rate           = 27000000,
-};
-
-struct clk clk_sclk_usbphy1 = {
-       .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-       .name           = "apb_pclk",
-       .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk clk_mout_apll = {
-       .clk    = {
-               .name           = "mout_apll",
-       },
-       .sources        = &clk_src_apll,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_sclk_apll = {
-       .clk    = {
-               .name           = "sclk_apll",
-               .parent         = &clk_mout_apll.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-struct clksrc_clk clk_mout_epll = {
-       .clk    = {
-               .name           = "mout_epll",
-       },
-       .sources        = &clk_src_epll,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
-       .clk = {
-               .name           = "mout_mpll",
-       },
-       .sources        = &clk_src_mpll,
-
-       /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *clkset_moutcore_list[] = {
-       [0] = &clk_mout_apll.clk,
-       [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_moutcore = {
-       .sources        = clkset_moutcore_list,
-       .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
-};
-
-static struct clksrc_clk clk_moutcore = {
-       .clk    = {
-               .name           = "moutcore",
-       },
-       .sources        = &clkset_moutcore,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_coreclk = {
-       .clk    = {
-               .name           = "core_clk",
-               .parent         = &clk_moutcore.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_armclk = {
-       .clk    = {
-               .name           = "armclk",
-               .parent         = &clk_coreclk.clk,
-       },
-};
-
-static struct clksrc_clk clk_aclk_corem0 = {
-       .clk    = {
-               .name           = "aclk_corem0",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
-       .clk    = {
-               .name           = "aclk_cores",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
-       .clk    = {
-               .name           = "aclk_corem1",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
-       .clk    = {
-               .name           = "periphclk",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-struct clk *clkset_corebus_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_mout_corebus = {
-       .sources        = clkset_corebus_list,
-       .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
-};
-
-static struct clksrc_clk clk_mout_corebus = {
-       .clk    = {
-               .name           = "mout_corebus",
-       },
-       .sources        = &clkset_mout_corebus,
-       .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_dmc = {
-       .clk    = {
-               .name           = "sclk_dmc",
-               .parent         = &clk_mout_corebus.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cored = {
-       .clk    = {
-               .name           = "aclk_cored",
-               .parent         = &clk_sclk_dmc.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
-       .clk    = {
-               .name           = "aclk_corep",
-               .parent         = &clk_aclk_cored.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
-       .clk    = {
-               .name           = "aclk_acp",
-               .parent         = &clk_mout_corebus.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
-       .clk    = {
-               .name           = "pclk_acp",
-               .parent         = &clk_aclk_acp.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *clkset_aclk_top_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_aclk = {
-       .sources        = clkset_aclk_top_list,
-       .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
-static struct clksrc_clk clk_aclk_200 = {
-       .clk    = {
-               .name           = "aclk_200",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_100 = {
-       .clk    = {
-               .name           = "aclk_100",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_aclk_160 = {
-       .clk    = {
-               .name           = "aclk_160",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk clk_aclk_133 = {
-       .clk    = {
-               .name           = "aclk_133",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
-       [0] = &clk_fin_vpll,
-       [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
-       .sources        = clkset_vpllsrc_list,
-       .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
-       .clk    = {
-               .name           = "vpll_src",
-               .enable         = exynos4_clksrc_mask_top_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .sources        = &clkset_vpllsrc,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
-       [0] = &clk_vpllsrc.clk,
-       [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
-       .sources        = clkset_sclk_vpll_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-struct clksrc_clk clk_sclk_vpll = {
-       .clk    = {
-               .name           = "sclk_vpll",
-       },
-       .sources        = &clkset_sclk_vpll,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk init_clocks_off[] = {
-       {
-               .name           = "timers",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1<<24),
-       }, {
-               .name           = "csis",
-               .devname        = "s5p-mipi-csis.0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "csis",
-               .devname        = "s5p-mipi-csis.1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.2",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.3",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "fimd",
-               .devname        = "exynos4-fb.0",
-               .enable         = exynos4_clk_ip_lcd0_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 6),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.3",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "dwmmc",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "dac",
-               .devname        = "s5p-sdo",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "mixer",
-               .devname        = "s5p-mixer",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "vp",
-               .devname        = "s5p-mixer",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "hdmi",
-               .devname        = "exynos4-hdmi",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "hdmiphy",
-               .devname        = "exynos4-hdmi",
-               .enable         = exynos4_clk_hdmiphy_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "dacphy",
-               .devname        = "s5p-sdo",
-               .enable         = exynos4_clk_dac_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "dma",
-               .devname        = "dma-pl330.0",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "dma",
-               .devname        = "dma-pl330.1",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "adc",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 15),
-       }, {
-               .name           = "keypad",
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 16),
-       }, {
-               .name           = "rtc",
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 15),
-       }, {
-               .name           = "watchdog",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 14),
-       }, {
-               .name           = "usbhost",
-               .enable         = exynos4_clk_ip_fsys_ctrl ,
-               .ctrlbit        = (1 << 12),
-       }, {
-               .name           = "otg",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 13),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 16),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 17),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 18),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 19),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 20),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 21),
-       }, {
-               .name           = "ac97",
-               .devname        = "samsung-ac97",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 27),
-       }, {
-               .name           = "fimg2d",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "mfc",
-               .devname        = "s5p-mfc",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.0",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 6),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.1",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.2",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.3",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.4",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.5",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 11),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.6",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 12),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.7",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 13),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-hdmiphy-i2c",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 14),
-       }, {
-               .name           = "SYSMMU_MDMA",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "SYSMMU_FIMC0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "SYSMMU_FIMC1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "SYSMMU_FIMC2",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "SYSMMU_FIMC3",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "SYSMMU_JPEG",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 11),
-       }, {
-               .name           = "SYSMMU_FIMD0",
-               .enable         = exynos4_clk_ip_lcd0_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_FIMD1",
-               .enable         = exynos4_clk_ip_lcd1_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_PCIe",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 18),
-       }, {
-               .name           = "SYSMMU_G2D",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "SYSMMU_ROTATOR",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_TV",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_MFC_L",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "SYSMMU_MFC_R",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 2),
-       }
-};
-
-static struct clk init_clocks[] = {
-       {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.3",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.4",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.5",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 5),
-       }
-};
-
-struct clk *clkset_group_list[] = {
-       [0] = &clk_ext_xtal_mux,
-       [1] = &clk_xusbxti,
-       [2] = &clk_sclk_hdmi27m,
-       [3] = &clk_sclk_usbphy0,
-       [4] = &clk_sclk_usbphy1,
-       [5] = &clk_sclk_hdmiphy,
-       [6] = &clk_mout_mpll.clk,
-       [7] = &clk_mout_epll.clk,
-       [8] = &clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources clkset_group = {
-       .sources        = clkset_group_list,
-       .nr_sources     = ARRAY_SIZE(clkset_group_list),
-};
-
-static struct clk *clkset_mout_g2d0_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d0 = {
-       .sources        = clkset_mout_g2d0_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-
-static struct clksrc_clk clk_mout_g2d0 = {
-       .clk    = {
-               .name           = "mout_g2d0",
-       },
-       .sources        = &clkset_mout_g2d0,
-       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d1_list[] = {
-       [0] = &clk_mout_epll.clk,
-       [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d1 = {
-       .sources        = clkset_mout_g2d1_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-
-static struct clksrc_clk clk_mout_g2d1 = {
-       .clk    = {
-               .name           = "mout_g2d1",
-       },
-       .sources        = &clkset_mout_g2d1,
-       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d_list[] = {
-       [0] = &clk_mout_g2d0.clk,
-       [1] = &clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d = {
-       .sources        = clkset_mout_g2d_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-
-static struct clk *clkset_mout_mfc0_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc0 = {
-       .sources        = clkset_mout_mfc0_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk clk_mout_mfc0 = {
-       .clk    = {
-               .name           = "mout_mfc0",
-       },
-       .sources        = &clkset_mout_mfc0,
-       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc1_list[] = {
-       [0] = &clk_mout_epll.clk,
-       [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc1 = {
-       .sources        = clkset_mout_mfc1_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk clk_mout_mfc1 = {
-       .clk    = {
-               .name           = "mout_mfc1",
-       },
-       .sources        = &clkset_mout_mfc1,
-       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc_list[] = {
-       [0] = &clk_mout_mfc0.clk,
-       [1] = &clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc = {
-       .sources        = clkset_mout_mfc_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
-       [0] = &clk_sclk_vpll.clk,
-       [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
-       .sources        = clkset_sclk_dac_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
-       .clk            = {
-               .name           = "sclk_dac",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 8),
-       },
-       .sources = &clkset_sclk_dac,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
-       .clk            = {
-               .name           = "sclk_pixel",
-               .parent = &clk_sclk_vpll.clk,
-       },
-       .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
-       [0] = &clk_sclk_pixel.clk,
-       [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
-       .sources        = clkset_sclk_hdmi_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
-       .clk            = {
-               .name           = "sclk_hdmi",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .sources = &clkset_sclk_hdmi,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
-       [0] = &clk_sclk_dac.clk,
-       [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
-       .sources        = clkset_sclk_mixer_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
-       .clk            = {
-               .name           = "sclk_mixer",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 4),
-       },
-       .sources = &clkset_sclk_mixer,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
-       &clk_sclk_dac,
-       &clk_sclk_pixel,
-       &clk_sclk_hdmi,
-       &clk_sclk_mixer,
-};
-
-static struct clksrc_clk clk_dout_mmc0 = {
-       .clk            = {
-               .name           = "dout_mmc0",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc1 = {
-       .clk            = {
-               .name           = "dout_mmc1",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc2 = {
-       .clk            = {
-               .name           = "dout_mmc2",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc3 = {
-       .clk            = {
-               .name           = "dout_mmc3",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc4 = {
-       .clk            = {
-               .name           = "dout_mmc4",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-       {
-               .clk    = {
-                       .name           = "uclk1",
-                       .devname        = "s5pv210-uart.0",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "uclk1",
-                       .devname        = "s5pv210-uart.1",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 4),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "uclk1",
-                       .devname        = "s5pv210-uart.2",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "uclk1",
-                       .devname        = "s5pv210-uart.3",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 12),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_pwm",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_csis",
-                       .devname        = "s5p-mipi-csis.0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_csis",
-                       .devname        = "s5p-mipi-csis.1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 28),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_cam0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 16),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_cam1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 20),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 4),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.2",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.3",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 12),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimd",
-                       .devname        = "exynos4-fb.0",
-                       .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_spi",
-                       .devname        = "s3c64xx-spi.0",
-                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                       .ctrlbit        = (1 << 16),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_spi",
-                       .devname        = "s3c64xx-spi.1",
-                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                       .ctrlbit        = (1 << 20),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_spi",
-                       .devname        = "s3c64xx-spi.2",
-                       .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimg2d",
-               },
-               .sources = &clkset_mout_g2d,
-               .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mfc",
-                       .devname        = "s5p-mfc",
-               },
-               .sources = &clkset_mout_mfc,
-               .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .parent         = &clk_dout_mmc0.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .parent         = &clk_dout_mmc1.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 4),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .parent         = &clk_dout_mmc2.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.3",
-                       .parent         = &clk_dout_mmc3.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 12),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_dwmmc",
-                       .parent         = &clk_dout_mmc4.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 16),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-       }
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-       &clk_mout_apll,
-       &clk_sclk_apll,
-       &clk_mout_epll,
-       &clk_mout_mpll,
-       &clk_moutcore,
-       &clk_coreclk,
-       &clk_armclk,
-       &clk_aclk_corem0,
-       &clk_aclk_cores,
-       &clk_aclk_corem1,
-       &clk_periphclk,
-       &clk_mout_corebus,
-       &clk_sclk_dmc,
-       &clk_aclk_cored,
-       &clk_aclk_corep,
-       &clk_aclk_acp,
-       &clk_pclk_acp,
-       &clk_vpllsrc,
-       &clk_sclk_vpll,
-       &clk_aclk_200,
-       &clk_aclk_100,
-       &clk_aclk_160,
-       &clk_aclk_133,
-       &clk_dout_mmc0,
-       &clk_dout_mmc1,
-       &clk_dout_mmc2,
-       &clk_dout_mmc3,
-       &clk_dout_mmc4,
-       &clk_mout_mfc0,
-       &clk_mout_mfc1,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-       if (soc_is_exynos4210())
-               return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
-                                       pll_4508);
-       else if (soc_is_exynos4212() || soc_is_exynos4412())
-               return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
-       else
-               return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-       .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 vpll_div[][8] = {
-       {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-       { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-       return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int vpll_con0, vpll_con1 = 0;
-       unsigned int i;
-
-       /* Return if nothing changed */
-       if (clk->rate == rate)
-               return 0;
-
-       vpll_con0 = __raw_readl(S5P_VPLL_CON0);
-       vpll_con0 &= ~(0x1 << 27 |                                      \
-                       PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                       PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                       PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-       vpll_con1 = __raw_readl(S5P_VPLL_CON1);
-       vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                       PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                       PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-       for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-               if (vpll_div[i][0] == rate) {
-                       vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                       vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                       vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                       vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                       vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                       vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                       vpll_con0 |= vpll_div[i][7] << 27;
-                       break;
-               }
-       }
-
-       if (i == ARRAY_SIZE(vpll_div)) {
-               printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                               __func__);
-               return -EINVAL;
-       }
-
-       __raw_writel(vpll_con0, S5P_VPLL_CON0);
-       __raw_writel(vpll_con1, S5P_VPLL_CON1);
-
-       /* Wait for VPLL lock */
-       while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-               continue;
-
-       clk->rate = rate;
-       return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-       .get_rate = exynos4_vpll_get_rate,
-       .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-       struct clk *xtal_clk;
-       unsigned long apll = 0;
-       unsigned long mpll = 0;
-       unsigned long epll = 0;
-       unsigned long vpll = 0;
-       unsigned long vpllsrc;
-       unsigned long xtal;
-       unsigned long armclk;
-       unsigned long sclk_dmc;
-       unsigned long aclk_200;
-       unsigned long aclk_100;
-       unsigned long aclk_160;
-       unsigned long aclk_133;
-       unsigned int ptr;
-
-       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-       xtal_clk = clk_get(NULL, "xtal");
-       BUG_ON(IS_ERR(xtal_clk));
-
-       xtal = clk_get_rate(xtal_clk);
-
-       xtal_rate = xtal;
-
-       clk_put(xtal_clk);
-
-       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-       if (soc_is_exynos4210()) {
-               apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-                                       pll_4508);
-               mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
-                                       pll_4508);
-               epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                       __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-               vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                       __raw_readl(S5P_VPLL_CON1), pll_4650c);
-       } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-               apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-               mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-               epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                       __raw_readl(S5P_EPLL_CON1));
-
-               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-               vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                       __raw_readl(S5P_VPLL_CON1));
-       } else {
-               /* nothing */
-       }
-
-       clk_fout_apll.ops = &exynos4_fout_apll_ops;
-       clk_fout_mpll.rate = mpll;
-       clk_fout_epll.rate = epll;
-       clk_fout_vpll.ops = &exynos4_vpll_ops;
-       clk_fout_vpll.rate = vpll;
-
-       printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                       apll, mpll, epll, vpll);
-
-       armclk = clk_get_rate(&clk_armclk.clk);
-       sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-
-       aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-       aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-       aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-       aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-
-       printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                        "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                       armclk, sclk_dmc, aclk_200,
-                       aclk_100, aclk_160, aclk_133);
-
-       clk_f.rate = armclk;
-       clk_h.rate = sclk_dmc;
-       clk_p.rate = aclk_100;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-               s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-       &clk_sclk_hdmi27m,
-       &clk_sclk_hdmiphy,
-       &clk_sclk_usbphy0,
-       &clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-       s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-       return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-       s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4_clock_syscore_ops = {
-       .suspend        = exynos4_clock_suspend,
-       .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-       int ptr;
-
-       s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-               s3c_register_clksrc(sysclks[ptr], 1);
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-               s3c_register_clksrc(sclk_tv[ptr], 1);
-
-       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-       s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-       register_syscore_ops(&exynos4_clock_syscore_ops);
-       s3c24xx_register_clock(&dummy_apb_pclk);
-
-       s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
deleted file mode 100644 (file)
index 5b1765b..0000000
+++ /dev/null
@@ -1,293 +0,0 @@
-/* linux/arch/arm/mach-exynos4/cpu.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/sysdev.h>
-
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/proc-fns.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/exynos4.h>
-#include <plat/adc-core.h>
-#include <plat/sdhci.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/reset.h>
-#include <plat/tv-core.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-pmu.h>
-
-unsigned int gic_bank_offset __read_mostly;
-
-extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
-                        unsigned int irq_start);
-extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
-
-/* Initial IO mappings */
-static struct map_desc exynos4_iodesc[] __initdata = {
-       {
-               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_CMU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
-               .length         = SZ_128K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_PMU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
-               .length         = SZ_8K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_L2CC,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO1,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO2,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GPIO3,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
-               .length         = SZ_256,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_DMC0,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S3C_VA_UART,
-               .pfn            = __phys_to_pfn(S3C_PA_UART),
-               .length         = SZ_512K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_SROMC,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
-       },
-};
-
-static struct map_desc exynos4_iodesc0[] __initdata = {
-       {
-               .virtual        = (unsigned long)S5P_VA_SYSRAM,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       },
-};
-
-static struct map_desc exynos4_iodesc1[] __initdata = {
-       {
-               .virtual        = (unsigned long)S5P_VA_SYSRAM,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       },
-};
-
-static void exynos4_idle(void)
-{
-       if (!need_resched())
-               cpu_do_idle();
-
-       local_irq_enable();
-}
-
-static void exynos4_sw_reset(void)
-{
-       __raw_writel(0x1, S5P_SWRESET);
-}
-
-/*
- * exynos4_map_io
- *
- * register the standard cpu IO areas
- */
-void __init exynos4_map_io(void)
-{
-       iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-
-       if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-               iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
-       else
-               iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
-
-       /* initialize device information early */
-       exynos4_default_sdhci0();
-       exynos4_default_sdhci1();
-       exynos4_default_sdhci2();
-       exynos4_default_sdhci3();
-
-       s3c_adc_setname("samsung-adc-v3");
-
-       s3c_fimc_setname(0, "exynos4-fimc");
-       s3c_fimc_setname(1, "exynos4-fimc");
-       s3c_fimc_setname(2, "exynos4-fimc");
-       s3c_fimc_setname(3, "exynos4-fimc");
-
-       /* The I2C bus controllers are directly compatible with s3c2440 */
-       s3c_i2c0_setname("s3c2440-i2c");
-       s3c_i2c1_setname("s3c2440-i2c");
-       s3c_i2c2_setname("s3c2440-i2c");
-
-       s5p_fb_setname(0, "exynos4-fb");
-       s5p_hdmi_setname("exynos4-hdmi");
-}
-
-void __init exynos4_init_clocks(int xtal)
-{
-       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-       s3c24xx_register_baseclocks(xtal);
-       s5p_register_clocks(xtal);
-
-       if (soc_is_exynos4210())
-               exynos4210_register_clocks();
-       else if (soc_is_exynos4212() || soc_is_exynos4412())
-               exynos4212_register_clocks();
-
-       exynos4_register_clocks();
-       exynos4_setup_clocks();
-}
-
-static void exynos4_gic_irq_fix_base(struct irq_data *d)
-{
-       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-
-       gic_data->cpu_base = S5P_VA_GIC_CPU +
-                           (gic_bank_offset * smp_processor_id());
-
-       gic_data->dist_base = S5P_VA_GIC_DIST +
-                           (gic_bank_offset * smp_processor_id());
-}
-
-void __init exynos4_init_irq(void)
-{
-       int irq;
-
-       gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-
-       gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-       gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
-       gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
-       gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
-
-       for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
-
-               combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                               COMBINER_IRQ(irq, 0));
-               combiner_cascade_irq(irq, IRQ_SPI(irq));
-       }
-
-       /* The parameters of s5p_init_irq() are for VIC init.
-        * Theses parameters should be NULL and 0 because EXYNOS4
-        * uses GIC instead of VIC.
-        */
-       s5p_init_irq(NULL, 0);
-}
-
-struct sysdev_class exynos4_sysclass = {
-       .name   = "exynos4-core",
-};
-
-static struct sys_device exynos4_sysdev = {
-       .cls    = &exynos4_sysclass,
-};
-
-static int __init exynos4_core_init(void)
-{
-       return sysdev_class_register(&exynos4_sysclass);
-}
-
-core_initcall(exynos4_core_init);
-
-#ifdef CONFIG_CACHE_L2X0
-static int __init exynos4_l2x0_cache_init(void)
-{
-       /* TAG, Data Latency Control: 2cycle */
-       __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-
-       if (soc_is_exynos4210())
-               __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-       else if (soc_is_exynos4212() || soc_is_exynos4412())
-               __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-
-       /* L2X0 Prefetch Control */
-       __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
-
-       /* L2X0 Power Control */
-       __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
-                    S5P_VA_L2CC + L2X0_POWER_CTRL);
-
-       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
-
-       return 0;
-}
-
-early_initcall(exynos4_l2x0_cache_init);
-#endif
-
-int __init exynos4_init(void)
-{
-       printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
-
-       /* set idle function */
-       pm_idle = exynos4_idle;
-
-       /* set sw_reset function */
-       s5p_reset_hook = exynos4_sw_reset;
-
-       return sysdev_register(&exynos4_sysdev);
-}
diff --git a/arch/arm/mach-exynos4/cpuidle.c b/arch/arm/mach-exynos4/cpuidle.c
deleted file mode 100644 (file)
index bf7e96f..0000000
+++ /dev/null
@@ -1,86 +0,0 @@
-/* linux/arch/arm/mach-exynos4/cpuidle.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/cpuidle.h>
-#include <linux/io.h>
-
-#include <asm/proc-fns.h>
-
-static int exynos4_enter_idle(struct cpuidle_device *dev,
-                             struct cpuidle_state *state);
-
-static struct cpuidle_state exynos4_cpuidle_set[] = {
-       [0] = {
-               .enter                  = exynos4_enter_idle,
-               .exit_latency           = 1,
-               .target_residency       = 100000,
-               .flags                  = CPUIDLE_FLAG_TIME_VALID,
-               .name                   = "IDLE",
-               .desc                   = "ARM clock gating(WFI)",
-       },
-};
-
-static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
-
-static struct cpuidle_driver exynos4_idle_driver = {
-       .name           = "exynos4_idle",
-       .owner          = THIS_MODULE,
-};
-
-static int exynos4_enter_idle(struct cpuidle_device *dev,
-                             struct cpuidle_state *state)
-{
-       struct timeval before, after;
-       int idle_time;
-
-       local_irq_disable();
-       do_gettimeofday(&before);
-
-       cpu_do_idle();
-
-       do_gettimeofday(&after);
-       local_irq_enable();
-       idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-                   (after.tv_usec - before.tv_usec);
-
-       return idle_time;
-}
-
-static int __init exynos4_init_cpuidle(void)
-{
-       int i, max_cpuidle_state, cpu_id;
-       struct cpuidle_device *device;
-
-       cpuidle_register_driver(&exynos4_idle_driver);
-
-       for_each_cpu(cpu_id, cpu_online_mask) {
-               device = &per_cpu(exynos4_cpuidle_device, cpu_id);
-               device->cpu = cpu_id;
-
-               device->state_count = (sizeof(exynos4_cpuidle_set) /
-                                              sizeof(struct cpuidle_state));
-
-               max_cpuidle_state = device->state_count;
-
-               for (i = 0; i < max_cpuidle_state; i++) {
-                       memcpy(&device->states[i], &exynos4_cpuidle_set[i],
-                                       sizeof(struct cpuidle_state));
-               }
-
-               if (cpuidle_register_device(device)) {
-                       printk(KERN_ERR "CPUidle register device failed\n,");
-                       return -EIO;
-               }
-       }
-       return 0;
-}
-device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos4/dev-ahci.c b/arch/arm/mach-exynos4/dev-ahci.c
deleted file mode 100644 (file)
index f57a3de..0000000
+++ /dev/null
@@ -1,263 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-ahci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - AHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/ahci_platform.h>
-
-#include <plat/cpu.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-pmu.h>
-
-/* PHY Control Register */
-#define SATA_CTRL0             0x0
-/* PHY Link Control Register */
-#define SATA_CTRL1             0x4
-/* PHY Status Register */
-#define SATA_PHY_STATUS                0x8
-
-#define SATA_CTRL0_RX_DATA_VALID(x)    (x << 27)
-#define SATA_CTRL0_SPEED_MODE          (1 << 26)
-#define SATA_CTRL0_M_PHY_CAL           (1 << 19)
-#define SATA_CTRL0_PHY_CMU_RST_N       (1 << 10)
-#define SATA_CTRL0_M_PHY_LN_RST_N      (1 << 9)
-#define SATA_CTRL0_PHY_POR_N           (1 << 8)
-
-#define SATA_CTRL1_RST_PMALIVE_N       (1 << 8)
-#define SATA_CTRL1_RST_RXOOB_N         (1 << 7)
-#define SATA_CTRL1_RST_RX_N            (1 << 6)
-#define SATA_CTRL1_RST_TX_N            (1 << 5)
-
-#define SATA_PHY_STATUS_CMU_OK         (1 << 18)
-#define SATA_PHY_STATUS_LANE_OK                (1 << 16)
-
-#define LANE0          0x200
-#define COM_LANE       0xA00
-
-#define HOST_PORTS_IMPL        0xC
-#define SCLK_SATA_FREQ (67 * MHZ)
-
-static void __iomem *phy_base, *phy_ctrl;
-
-struct phy_reg {
-       u8      reg;
-       u8      val;
-};
-
-/* SATA PHY setup */
-static const struct phy_reg exynos4_sataphy_cmu[] = {
-       { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
-       { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
-       { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
-       { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
-       { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
-       { 0x6b, 0xc8 }, { 0x6c, 0x06 },
-};
-
-static const struct phy_reg exynos4_sataphy_lane[] = {
-       { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
-       { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
-       { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
-       { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
-       { 0x51, 0x0f },
-};
-
-static const struct phy_reg exynos4_sataphy_comlane[] = {
-       { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
-       { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
-       { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
-       { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
-       { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
-       { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
-       { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
-       { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
-       { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
-       { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
-       { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
-       { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
-       { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
-       { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
-};
-
-static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
-{
-       unsigned long timeout;
-
-       /* wait for maximum of 3 sec */
-       timeout = jiffies + msecs_to_jiffies(3000);
-       while (!(__raw_readl(reg) & bit)) {
-               if (time_after(jiffies, timeout))
-                       return -1;
-               cpu_relax();
-       }
-       return 0;
-}
-
-static int ahci_phy_init(void __iomem *mmio)
-{
-       int i, ctrl0;
-
-       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
-               __raw_writeb(exynos4_sataphy_cmu[i].val,
-               phy_base + (exynos4_sataphy_cmu[i].reg * 4));
-
-       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
-               __raw_writeb(exynos4_sataphy_lane[i].val,
-               phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
-
-       for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
-               __raw_writeb(exynos4_sataphy_comlane[i].val,
-               phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
-
-       __raw_writeb(0x07, phy_base);
-
-       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-       ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
-       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-       if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                               SATA_PHY_STATUS_CMU_OK) < 0) {
-               printk(KERN_ERR "PHY CMU not ready\n");
-               return -EBUSY;
-       }
-
-       __raw_writeb(0x03, phy_base + (COM_LANE * 4));
-
-       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-       ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
-       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-       if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                               SATA_PHY_STATUS_LANE_OK) < 0) {
-               printk(KERN_ERR "PHY LANE not ready\n");
-               return -EBUSY;
-       }
-
-       ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-       ctrl0 |= SATA_CTRL0_M_PHY_CAL;
-       __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-       return 0;
-}
-
-static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
-{
-       struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
-       int val, ret;
-
-       phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
-       if (!phy_base) {
-               dev_err(dev, "failed to allocate memory for SATA PHY\n");
-               return -ENOMEM;
-       }
-
-       phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
-       if (!phy_ctrl) {
-               dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
-               ret = -ENOMEM;
-               goto err1;
-       }
-
-       clk_sata = clk_get(dev, "sata");
-       if (IS_ERR(clk_sata)) {
-               dev_err(dev, "failed to get sata clock\n");
-               ret = PTR_ERR(clk_sata);
-               clk_sata = NULL;
-               goto err2;
-
-       }
-       clk_enable(clk_sata);
-
-       clk_sataphy = clk_get(dev, "sataphy");
-       if (IS_ERR(clk_sataphy)) {
-               dev_err(dev, "failed to get sataphy clock\n");
-               ret = PTR_ERR(clk_sataphy);
-               clk_sataphy = NULL;
-               goto err3;
-       }
-       clk_enable(clk_sataphy);
-
-       clk_sclk_sata = clk_get(dev, "sclk_sata");
-       if (IS_ERR(clk_sclk_sata)) {
-               dev_err(dev, "failed to get sclk_sata\n");
-               ret = PTR_ERR(clk_sclk_sata);
-               clk_sclk_sata = NULL;
-               goto err4;
-       }
-       clk_enable(clk_sclk_sata);
-       clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
-
-       __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
-
-       /* Enable PHY link control */
-       val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
-                       SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
-       __raw_writel(val, phy_ctrl + SATA_CTRL1);
-
-       /* Set communication speed as 3Gbps and enable PHY power */
-       val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
-                       SATA_CTRL0_PHY_POR_N;
-       __raw_writel(val, phy_ctrl + SATA_CTRL0);
-
-       /* Port0 is available */
-       __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
-
-       return ahci_phy_init(mmio);
-
-err4:
-       clk_disable(clk_sataphy);
-       clk_put(clk_sataphy);
-err3:
-       clk_disable(clk_sata);
-       clk_put(clk_sata);
-err2:
-       iounmap(phy_ctrl);
-err1:
-       iounmap(phy_base);
-
-       return ret;
-}
-
-static struct ahci_platform_data exynos4_ahci_pdata = {
-       .init = exynos4_ahci_init,
-};
-
-static struct resource exynos4_ahci_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_SATA,
-               .end    = EXYNOS4_PA_SATA + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_SATA,
-               .end    = IRQ_SATA,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ahci = {
-       .name           = "ahci",
-       .id             = -1,
-       .resource       = exynos4_ahci_resource,
-       .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
-       .dev            = {
-               .platform_data          = &exynos4_ahci_pdata,
-               .dma_mask               = &exynos4_ahci_dmamask,
-               .coherent_dma_mask      = DMA_BIT_MASK(32),
-       },
-};
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
deleted file mode 100644 (file)
index 5a9f9c2..0000000
+++ /dev/null
@@ -1,369 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-audio.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *     Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/audio.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/regs-audss.h>
-
-static const char *rclksrc[] = {
-       [0] = "busclk",
-       [1] = "i2sclk",
-};
-
-static int exynos4_cfg_i2s(struct platform_device *pdev)
-{
-       /* configure GPIO for i2s port */
-       switch (pdev->id) {
-       case 0:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
-               break;
-       case 1:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
-               break;
-       case 2:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
-               break;
-       default:
-               printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static struct s3c_audio_pdata i2sv5_pdata = {
-       .cfg_gpio = exynos4_cfg_i2s,
-       .type = {
-               .i2s = {
-                       .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                        | QUIRK_NEED_RSTCLR,
-                       .src_clk = rclksrc,
-                       .idma_addr = EXYNOS4_AUDSS_INT_MEM,
-               },
-       },
-};
-
-static struct resource exynos4_i2s0_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_I2S0,
-               .end    = EXYNOS4_PA_I2S0 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_I2S0_TX,
-               .end    = DMACH_I2S0_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_I2S0_RX,
-               .end    = DMACH_I2S0_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [3] = {
-               .start  = DMACH_I2S0S_TX,
-               .end    = DMACH_I2S0S_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_i2s0 = {
-       .name = "samsung-i2s",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
-       .resource = exynos4_i2s0_resource,
-       .dev = {
-               .platform_data = &i2sv5_pdata,
-       },
-};
-
-static const char *rclksrc_v3[] = {
-       [0] = "sclk_i2s",
-       [1] = "no_such_clock",
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-       .cfg_gpio = exynos4_cfg_i2s,
-       .type = {
-               .i2s = {
-                       .quirks = QUIRK_NO_MUXPSR,
-                       .src_clk = rclksrc_v3,
-               },
-       },
-};
-
-static struct resource exynos4_i2s1_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_I2S1,
-               .end    = EXYNOS4_PA_I2S1 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_I2S1_TX,
-               .end    = DMACH_I2S1_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_I2S1_RX,
-               .end    = DMACH_I2S1_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_i2s1 = {
-       .name = "samsung-i2s",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
-       .resource = exynos4_i2s1_resource,
-       .dev = {
-               .platform_data = &i2sv3_pdata,
-       },
-};
-
-static struct resource exynos4_i2s2_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_I2S2,
-               .end    = EXYNOS4_PA_I2S2 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_I2S2_TX,
-               .end    = DMACH_I2S2_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_I2S2_RX,
-               .end    = DMACH_I2S2_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_i2s2 = {
-       .name = "samsung-i2s",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
-       .resource = exynos4_i2s2_resource,
-       .dev = {
-               .platform_data = &i2sv3_pdata,
-       },
-};
-
-/* PCM Controller platform_devices */
-
-static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
-{
-       switch (pdev->id) {
-       case 0:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
-               break;
-       case 1:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
-               break;
-       case 2:
-               s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
-               break;
-       default:
-               printk(KERN_DEBUG "Invalid PCM Controller number!");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-       .cfg_gpio = exynos4_pcm_cfg_gpio,
-};
-
-static struct resource exynos4_pcm0_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_PCM0,
-               .end    = EXYNOS4_PA_PCM0 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_PCM0_TX,
-               .end    = DMACH_PCM0_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_PCM0_RX,
-               .end    = DMACH_PCM0_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_pcm0 = {
-       .name = "samsung-pcm",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
-       .resource = exynos4_pcm0_resource,
-       .dev = {
-               .platform_data = &s3c_pcm_pdata,
-       },
-};
-
-static struct resource exynos4_pcm1_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_PCM1,
-               .end    = EXYNOS4_PA_PCM1 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_PCM1_TX,
-               .end    = DMACH_PCM1_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_PCM1_RX,
-               .end    = DMACH_PCM1_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_pcm1 = {
-       .name = "samsung-pcm",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
-       .resource = exynos4_pcm1_resource,
-       .dev = {
-               .platform_data = &s3c_pcm_pdata,
-       },
-};
-
-static struct resource exynos4_pcm2_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_PCM2,
-               .end    = EXYNOS4_PA_PCM2 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_PCM2_TX,
-               .end    = DMACH_PCM2_TX,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_PCM2_RX,
-               .end    = DMACH_PCM2_RX,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-struct platform_device exynos4_device_pcm2 = {
-       .name = "samsung-pcm",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
-       .resource = exynos4_pcm2_resource,
-       .dev = {
-               .platform_data = &s3c_pcm_pdata,
-       },
-};
-
-/* AC97 Controller platform devices */
-
-static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
-{
-       return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource exynos4_ac97_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_AC97,
-               .end    = EXYNOS4_PA_AC97 + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_AC97_PCMOUT,
-               .end    = DMACH_AC97_PCMOUT,
-               .flags  = IORESOURCE_DMA,
-       },
-       [2] = {
-               .start  = DMACH_AC97_PCMIN,
-               .end    = DMACH_AC97_PCMIN,
-               .flags  = IORESOURCE_DMA,
-       },
-       [3] = {
-               .start  = DMACH_AC97_MICIN,
-               .end    = DMACH_AC97_MICIN,
-               .flags  = IORESOURCE_DMA,
-       },
-       [4] = {
-               .start  = IRQ_AC97,
-               .end    = IRQ_AC97,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-       .cfg_gpio = exynos4_ac97_cfg_gpio,
-};
-
-static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ac97 = {
-       .name = "samsung-ac97",
-       .id = -1,
-       .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
-       .resource = exynos4_ac97_resource,
-       .dev = {
-               .platform_data = &s3c_ac97_pdata,
-               .dma_mask = &exynos4_ac97_dmamask,
-               .coherent_dma_mask = DMA_BIT_MASK(32),
-       },
-};
-
-/* S/PDIF Controller platform_device */
-
-static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
-{
-       s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
-
-       return 0;
-}
-
-static struct resource exynos4_spdif_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_SPDIF,
-               .end    = EXYNOS4_PA_SPDIF + 0x100 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = DMACH_SPDIF,
-               .end    = DMACH_SPDIF,
-               .flags  = IORESOURCE_DMA,
-       },
-};
-
-static struct s3c_audio_pdata samsung_spdif_pdata = {
-       .cfg_gpio = exynos4_spdif_cfg_gpio,
-};
-
-static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_spdif = {
-       .name = "samsung-spdif",
-       .id = -1,
-       .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
-       .resource = exynos4_spdif_resource,
-       .dev = {
-               .platform_data = &samsung_spdif_pdata,
-               .dma_mask = &exynos4_spdif_dmamask,
-               .coherent_dma_mask = DMA_BIT_MASK(32),
-       },
-};
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c
deleted file mode 100644 (file)
index b025db4..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/dev-dwmci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Platform device for Synopsys DesignWare Mobile Storage IP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/mmc/dw_mmc.h>
-
-#include <plat/devs.h>
-
-#include <mach/map.h>
-
-static int exynos4_dwmci_get_bus_wd(u32 slot_id)
-{
-       return 4;
-}
-
-static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
-{
-       return 0;
-}
-
-static struct resource exynos4_dwmci_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_DWMCI,
-               .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_DWMCI,
-               .end    = IRQ_DWMCI,
-               .flags  = IORESOURCE_IRQ,
-       }
-};
-
-static struct dw_mci_board exynos4_dwci_pdata = {
-       .num_slots                      = 1,
-       .quirks                         = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
-       .bus_hz                         = 80 * 1000 * 1000,
-       .detect_delay_ms        = 200,
-       .init                           = exynos4_dwmci_init,
-       .get_bus_wd                     = exynos4_dwmci_get_bus_wd,
-};
-
-static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_dwmci = {
-       .name           = "dw_mmc",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(exynos4_dwmci_resource),
-       .resource       = exynos4_dwmci_resource,
-       .dev            = {
-               .dma_mask               = &exynos4_dwmci_dmamask,
-               .coherent_dma_mask      = DMA_BIT_MASK(32),
-               .platform_data  = &exynos4_dwci_pdata,
-       },
-};
-
-void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
-{
-       struct dw_mci_board *npd;
-
-       npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
-                       &exynos4_device_dwmci);
-
-       if (!npd->init)
-               npd->init = exynos4_dwmci_init;
-       if (!npd->get_bus_wd)
-               npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
-}
diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
deleted file mode 100644 (file)
index 3273f25..0000000
+++ /dev/null
@@ -1,139 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-pd.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Power Domain support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-
-#include <mach/regs-pmu.h>
-
-#include <plat/pd.h>
-
-static int exynos4_pd_enable(struct device *dev)
-{
-       struct samsung_pd_info *pdata =  dev->platform_data;
-       u32 timeout;
-
-       __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
-
-       /* Wait max 1ms */
-       timeout = 10;
-       while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
-               != S5P_INT_LOCAL_PWR_EN) {
-               if (timeout == 0) {
-                       printk(KERN_ERR "Power domain %s enable failed.\n",
-                               dev_name(dev));
-                       return -ETIMEDOUT;
-               }
-               timeout--;
-               udelay(100);
-       }
-
-       return 0;
-}
-
-static int exynos4_pd_disable(struct device *dev)
-{
-       struct samsung_pd_info *pdata =  dev->platform_data;
-       u32 timeout;
-
-       __raw_writel(0, pdata->base);
-
-       /* Wait max 1ms */
-       timeout = 10;
-       while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
-               if (timeout == 0) {
-                       printk(KERN_ERR "Power domain %s disable failed.\n",
-                               dev_name(dev));
-                       return -ETIMEDOUT;
-               }
-               timeout--;
-               udelay(100);
-       }
-
-       return 0;
-}
-
-struct platform_device exynos4_device_pd[] = {
-       {
-               .name           = "samsung-pd",
-               .id             = 0,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_MFC_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 1,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_G3D_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 2,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_LCD0_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 3,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_LCD1_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 4,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_TV_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 5,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_CAM_CONF,
-                       },
-               },
-       }, {
-               .name           = "samsung-pd",
-               .id             = 6,
-               .dev = {
-                       .platform_data = &(struct samsung_pd_info) {
-                               .enable         = exynos4_pd_enable,
-                               .disable        = exynos4_pd_disable,
-                               .base           = S5P_PMU_GPS_CONF,
-                       },
-               },
-       },
-};
diff --git a/arch/arm/mach-exynos4/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c
deleted file mode 100644 (file)
index 3b7cae0..0000000
+++ /dev/null
@@ -1,232 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - System MMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/sysmmu.h>
-#include <plat/s5p-clock.h>
-
-/* These names must be equal to the clock names in mach-exynos4/clock.c */
-const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
-       "SYSMMU_MDMA"   ,
-       "SYSMMU_SSS"    ,
-       "SYSMMU_FIMC0"  ,
-       "SYSMMU_FIMC1"  ,
-       "SYSMMU_FIMC2"  ,
-       "SYSMMU_FIMC3"  ,
-       "SYSMMU_JPEG"   ,
-       "SYSMMU_FIMD0"  ,
-       "SYSMMU_FIMD1"  ,
-       "SYSMMU_PCIe"   ,
-       "SYSMMU_G2D"    ,
-       "SYSMMU_ROTATOR",
-       "SYSMMU_MDMA2"  ,
-       "SYSMMU_TV"     ,
-       "SYSMMU_MFC_L"  ,
-       "SYSMMU_MFC_R"  ,
-};
-
-static struct resource exynos4_sysmmu_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_SYSMMU_MDMA,
-               .end    = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_SYSMMU_MDMA0_0,
-               .end    = IRQ_SYSMMU_MDMA0_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [2] = {
-               .start  = EXYNOS4_PA_SYSMMU_SSS,
-               .end    = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [3] = {
-               .start  = IRQ_SYSMMU_SSS_0,
-               .end    = IRQ_SYSMMU_SSS_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [4] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMC0,
-               .end    = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [5] = {
-               .start  = IRQ_SYSMMU_FIMC0_0,
-               .end    = IRQ_SYSMMU_FIMC0_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [6] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMC1,
-               .end    = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [7] = {
-               .start  = IRQ_SYSMMU_FIMC1_0,
-               .end    = IRQ_SYSMMU_FIMC1_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [8] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMC2,
-               .end    = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [9] = {
-               .start  = IRQ_SYSMMU_FIMC2_0,
-               .end    = IRQ_SYSMMU_FIMC2_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [10] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMC3,
-               .end    = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [11] = {
-               .start  = IRQ_SYSMMU_FIMC3_0,
-               .end    = IRQ_SYSMMU_FIMC3_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [12] = {
-               .start  = EXYNOS4_PA_SYSMMU_JPEG,
-               .end    = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [13] = {
-               .start  = IRQ_SYSMMU_JPEG_0,
-               .end    = IRQ_SYSMMU_JPEG_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [14] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMD0,
-               .end    = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [15] = {
-               .start  = IRQ_SYSMMU_LCD0_M0_0,
-               .end    = IRQ_SYSMMU_LCD0_M0_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [16] = {
-               .start  = EXYNOS4_PA_SYSMMU_FIMD1,
-               .end    = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [17] = {
-               .start  = IRQ_SYSMMU_LCD1_M1_0,
-               .end    = IRQ_SYSMMU_LCD1_M1_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [18] = {
-               .start  = EXYNOS4_PA_SYSMMU_PCIe,
-               .end    = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [19] = {
-               .start  = IRQ_SYSMMU_PCIE_0,
-               .end    = IRQ_SYSMMU_PCIE_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [20] = {
-               .start  = EXYNOS4_PA_SYSMMU_G2D,
-               .end    = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [21] = {
-               .start  = IRQ_SYSMMU_2D_0,
-               .end    = IRQ_SYSMMU_2D_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [22] = {
-               .start  = EXYNOS4_PA_SYSMMU_ROTATOR,
-               .end    = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [23] = {
-               .start  = IRQ_SYSMMU_ROTATOR_0,
-               .end    = IRQ_SYSMMU_ROTATOR_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [24] = {
-               .start  = EXYNOS4_PA_SYSMMU_MDMA2,
-               .end    = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [25] = {
-               .start  = IRQ_SYSMMU_MDMA1_0,
-               .end    = IRQ_SYSMMU_MDMA1_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [26] = {
-               .start  = EXYNOS4_PA_SYSMMU_TV,
-               .end    = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [27] = {
-               .start  = IRQ_SYSMMU_TV_M0_0,
-               .end    = IRQ_SYSMMU_TV_M0_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [28] = {
-               .start  = EXYNOS4_PA_SYSMMU_MFC_L,
-               .end    = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [29] = {
-               .start  = IRQ_SYSMMU_MFC_M0_0,
-               .end    = IRQ_SYSMMU_MFC_M0_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-       [30] = {
-               .start  = EXYNOS4_PA_SYSMMU_MFC_R,
-               .end    = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [31] = {
-               .start  = IRQ_SYSMMU_MFC_M1_0,
-               .end    = IRQ_SYSMMU_MFC_M1_0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device exynos4_device_sysmmu = {
-       .name           = "s5p-sysmmu",
-       .id             = 32,
-       .num_resources  = ARRAY_SIZE(exynos4_sysmmu_resource),
-       .resource       = exynos4_sysmmu_resource,
-};
-EXPORT_SYMBOL(exynos4_device_sysmmu);
-
-static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
-{
-       sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
-       if (IS_ERR(sysmmu_clk[ips]))
-               sysmmu_clk[ips] = NULL;
-       else
-               clk_put(sysmmu_clk[ips]);
-}
-
-void sysmmu_clk_enable(sysmmu_ips ips)
-{
-       if (sysmmu_clk[ips])
-               clk_enable(sysmmu_clk[ips]);
-}
-
-void sysmmu_clk_disable(sysmmu_ips ips)
-{
-       if (sysmmu_clk[ips])
-               clk_disable(sysmmu_clk[ips]);
-}
diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c
deleted file mode 100644 (file)
index 9667c61..0000000
+++ /dev/null
@@ -1,250 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *     Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-struct dma_pl330_peri pdma0_peri[28] = {
-       {
-               .peri_id = (u8)DMACH_PCM0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_PCM0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_PCM2_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_PCM2_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_MSM_REQ0,
-       }, {
-               .peri_id = (u8)DMACH_MSM_REQ2,
-       }, {
-               .peri_id = (u8)DMACH_SPI0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SPI0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SPI2_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SPI2_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_I2S0S_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_I2S0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_I2S0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART2_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART2_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART4_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART4_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS2_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS2_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS4_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS4_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_AC97_MICIN,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_AC97_PCMIN,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_AC97_PCMOUT,
-               .rqtype = MEMTODEV,
-       },
-};
-
-struct dma_pl330_platdata exynos4_pdma0_pdata = {
-       .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-       .peri = pdma0_peri,
-};
-
-struct amba_device exynos4_device_pdma0 = {
-       .dev = {
-               .init_name = "dma-pl330.0",
-               .dma_mask = &dma_dmamask,
-               .coherent_dma_mask = DMA_BIT_MASK(32),
-               .platform_data = &exynos4_pdma0_pdata,
-       },
-       .res = {
-               .start = EXYNOS4_PA_PDMA0,
-               .end = EXYNOS4_PA_PDMA0 + SZ_4K,
-               .flags = IORESOURCE_MEM,
-       },
-       .irq = {IRQ_PDMA0, NO_IRQ},
-       .periphid = 0x00041330,
-};
-
-struct dma_pl330_peri pdma1_peri[25] = {
-       {
-               .peri_id = (u8)DMACH_PCM0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_PCM0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_PCM1_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_PCM1_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_MSM_REQ1,
-       }, {
-               .peri_id = (u8)DMACH_MSM_REQ3,
-       }, {
-               .peri_id = (u8)DMACH_SPI1_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SPI1_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_I2S0S_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_I2S0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_I2S0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_I2S1_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_I2S1_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART0_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART0_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART1_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART1_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_UART3_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_UART3_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS1_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS1_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS3_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS3_TX,
-               .rqtype = MEMTODEV,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS5_RX,
-               .rqtype = DEVTOMEM,
-       }, {
-               .peri_id = (u8)DMACH_SLIMBUS5_TX,
-               .rqtype = MEMTODEV,
-       },
-};
-
-struct dma_pl330_platdata exynos4_pdma1_pdata = {
-       .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-       .peri = pdma1_peri,
-};
-
-struct amba_device exynos4_device_pdma1 = {
-       .dev = {
-               .init_name = "dma-pl330.1",
-               .dma_mask = &dma_dmamask,
-               .coherent_dma_mask = DMA_BIT_MASK(32),
-               .platform_data = &exynos4_pdma1_pdata,
-       },
-       .res = {
-               .start = EXYNOS4_PA_PDMA1,
-               .end = EXYNOS4_PA_PDMA1 + SZ_4K,
-               .flags = IORESOURCE_MEM,
-       },
-       .irq = {IRQ_PDMA1, NO_IRQ},
-       .periphid = 0x00041330,
-};
-
-static int __init exynos4_dma_init(void)
-{
-       amba_device_register(&exynos4_device_pdma0, &iomem_resource);
-       amba_device_register(&exynos4_device_pdma1, &iomem_resource);
-
-       return 0;
-}
-arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-exynos4/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
deleted file mode 100644 (file)
index 3cdeb36..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  linux/arch/arm/mach-exynos4/headsmp.S
- *
- *  Cloned from linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-       __CPUINIT
-
-/*
- * exynos4 specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(exynos4_secondary_startup)
-       mrc     p15, 0, r0, c0, c0, 5
-       and     r0, r0, #15
-       adr     r4, 1f
-       ldmia   r4, {r5, r6}
-       sub     r4, r4, r5
-       add     r6, r6, r4
-pen:   ldr     r7, [r6]
-       cmp     r7, r0
-       bne     pen
-
-       /*
-        * we've been released from the holding pen: secondary_stack
-        * should now contain the SVC stack for this core
-        */
-       b       secondary_startup
-
-1:     .long   .
-       .long   pen_release
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
deleted file mode 100644 (file)
index da70e7e..0000000
+++ /dev/null
@@ -1,133 +0,0 @@
-/* linux arch/arm/mach-exynos4/hotplug.c
- *
- *  Cloned from linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/regs-pmu.h>
-
-extern volatile int pen_release;
-
-static inline void cpu_enter_lowpower(void)
-{
-       unsigned int v;
-
-       flush_cache_all();
-       asm volatile(
-       "       mcr     p15, 0, %1, c7, c5, 0\n"
-       "       mcr     p15, 0, %1, c7, c10, 4\n"
-       /*
-        * Turn off coherency
-        */
-       "       mrc     p15, 0, %0, c1, c0, 1\n"
-       "       bic     %0, %0, %3\n"
-       "       mcr     p15, 0, %0, c1, c0, 1\n"
-       "       mrc     p15, 0, %0, c1, c0, 0\n"
-       "       bic     %0, %0, %2\n"
-       "       mcr     p15, 0, %0, c1, c0, 0\n"
-         : "=&r" (v)
-         : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-         : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-       unsigned int v;
-
-       asm volatile(
-       "mrc    p15, 0, %0, c1, c0, 0\n"
-       "       orr     %0, %0, %1\n"
-       "       mcr     p15, 0, %0, c1, c0, 0\n"
-       "       mrc     p15, 0, %0, c1, c0, 1\n"
-       "       orr     %0, %0, %2\n"
-       "       mcr     p15, 0, %0, c1, c0, 1\n"
-         : "=&r" (v)
-         : "Ir" (CR_C), "Ir" (0x40)
-         : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-       for (;;) {
-
-               /* make cpu1 to be turned off at next WFI command */
-               if (cpu == 1)
-                       __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
-
-               /*
-                * here's the WFI
-                */
-               asm(".word      0xe320f003\n"
-                   :
-                   :
-                   : "memory", "cc");
-
-               if (pen_release == cpu_logical_map(cpu)) {
-                       /*
-                        * OK, proper wakeup, we're done
-                        */
-                       break;
-               }
-
-               /*
-                * Getting here, means that we have come out of WFI without
-                * having been woken up - this shouldn't happen
-                *
-                * Just note it happening - when we're woken, we can report
-                * its occurrence.
-                */
-               (*spurious)++;
-       }
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
-       return 1;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-       int spurious = 0;
-
-       /*
-        * we're ready for shutdown now, so do it
-        */
-       cpu_enter_lowpower();
-       platform_do_lowpower(cpu, &spurious);
-
-       /*
-        * bring this CPU back into the world of cache
-        * coherency, and then restore interrupts
-        */
-       cpu_leave_lowpower();
-
-       if (spurious)
-               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
-       /*
-        * we don't allow CPU 0 to be shutdown (it is still too special
-        * e.g. clock tick interrupts)
-        */
-       return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
deleted file mode 100644 (file)
index 6cacf16..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-
-       /* note, for the boot process to work we have to keep the UART
-        * virtual address aligned to an 1MiB boundary for the L1
-        * mapping the head code makes. We keep the UART virtual address
-        * aligned and add in the offset when we load the value here.
-        */
-
-       .macro addruart, rp, rv, tmp
-               ldr     \rp, = S3C_PA_UART
-               ldr     \rv, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-               add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
-               add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
-#endif
-       .endm
-
-#define fifo_full fifo_full_s5pv210
-#define fifo_level fifo_level_s5pv210
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
deleted file mode 100644 (file)
index 201842a..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *     Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* This platform uses the common DMA API driver for PL330 */
-#include <plat/dma-pl330.h>
-
-#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
deleted file mode 100644 (file)
index 7ce6574..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * Synopsys DesignWare Mobile Storage for EXYNOS4210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_ARCH_DWMCI_H
-#define __ASM_ARM_ARCH_DWMCI_H __FILE__
-
-#include <linux/mmc/dw_mmc.h>
-
-extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
-
-#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
deleted file mode 100644 (file)
index f5e9fd8..0000000
+++ /dev/null
@@ -1,91 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/entry-macro.S
- *
- * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for EXYNOS4 platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
-
-               .macro  disable_fiq
-               .endm
-
-               .macro  get_irqnr_preamble, base, tmp
-               mov     \tmp, #0
-
-               mrc     p15, 0, \base, c0, c0, 5
-               and     \base, \base, #3
-               cmp     \base, #0
-               beq     1f
-
-               ldr     \tmp, =gic_bank_offset
-               ldr     \tmp, [\tmp]
-               cmp     \base, #1
-               beq     1f
-
-               cmp     \base, #2
-               addeq   \tmp, \tmp, \tmp
-               addne   \tmp, \tmp, \tmp, LSL #1
-
-1:             ldr     \base, =gic_cpu_base_addr
-               ldr     \base, [\base]
-               add     \base, \base, \tmp
-               .endm
-
-               .macro  arch_ret_to_user, tmp1, tmp2
-               .endm
-
-               /*
-                * The interrupt numbering scheme is defined in the
-                * interrupt controller spec.  To wit:
-                *
-                * Interrupts 0-15 are IPI
-                * 16-28 are reserved
-                * 29-31 are local.  We allow 30 to be used for the watchdog.
-                * 32-1020 are global
-                * 1021-1022 are reserved
-                * 1023 is "spurious" (no interrupt)
-                *
-                * For now, we ignore all local interrupts so only return an interrupt if it's
-                * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                *
-                * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                * valid range for an IRQ (30-1020 inclusive).
-                */
-
-               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-               ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-               ldr     \tmp, =1021
-
-               bic     \irqnr, \irqstat, #0x1c00
-
-               cmp     \irqnr, #15
-               cmpcc   \irqnr, \irqnr
-               cmpne   \irqnr, \tmp
-               cmpcs   \irqnr, \irqnr
-               addne   \irqnr, \irqnr, #32
-
-               .endm
-
-               /* We assume that irqstat (the raw value of the IRQ acknowledge
-                * register) is preserved from the macro above.
-                * If there is an IPI, we immediately signal end of interrupt on the
-                * controller, since this requires the original irqstat value which
-                * we won't easily be able to recreate later.
-                */
-
-               .macro test_for_ipi, irqnr, irqstat, base, tmp
-               bic     \irqnr, \irqstat, #0x1c00
-               cmp     \irqnr, #16
-               strcc   \irqstat, [\base, #GIC_CPU_EOI]
-               cmpcs   \irqnr, \irqnr
-               .endm
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
deleted file mode 100644 (file)
index a07fcbf..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
deleted file mode 100644 (file)
index 80523ca..0000000
+++ /dev/null
@@ -1,149 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
-
-/* GPIO bank sizes */
-#define EXYNOS4_GPIO_A0_NR     (8)
-#define EXYNOS4_GPIO_A1_NR     (6)
-#define EXYNOS4_GPIO_B_NR      (8)
-#define EXYNOS4_GPIO_C0_NR     (5)
-#define EXYNOS4_GPIO_C1_NR     (5)
-#define EXYNOS4_GPIO_D0_NR     (4)
-#define EXYNOS4_GPIO_D1_NR     (4)
-#define EXYNOS4_GPIO_E0_NR     (5)
-#define EXYNOS4_GPIO_E1_NR     (8)
-#define EXYNOS4_GPIO_E2_NR     (6)
-#define EXYNOS4_GPIO_E3_NR     (8)
-#define EXYNOS4_GPIO_E4_NR     (8)
-#define EXYNOS4_GPIO_F0_NR     (8)
-#define EXYNOS4_GPIO_F1_NR     (8)
-#define EXYNOS4_GPIO_F2_NR     (8)
-#define EXYNOS4_GPIO_F3_NR     (6)
-#define EXYNOS4_GPIO_J0_NR     (8)
-#define EXYNOS4_GPIO_J1_NR     (5)
-#define EXYNOS4_GPIO_K0_NR     (7)
-#define EXYNOS4_GPIO_K1_NR     (7)
-#define EXYNOS4_GPIO_K2_NR     (7)
-#define EXYNOS4_GPIO_K3_NR     (7)
-#define EXYNOS4_GPIO_L0_NR     (8)
-#define EXYNOS4_GPIO_L1_NR     (3)
-#define EXYNOS4_GPIO_L2_NR     (8)
-#define EXYNOS4_GPIO_X0_NR     (8)
-#define EXYNOS4_GPIO_X1_NR     (8)
-#define EXYNOS4_GPIO_X2_NR     (8)
-#define EXYNOS4_GPIO_X3_NR     (8)
-#define EXYNOS4_GPIO_Y0_NR     (6)
-#define EXYNOS4_GPIO_Y1_NR     (4)
-#define EXYNOS4_GPIO_Y2_NR     (6)
-#define EXYNOS4_GPIO_Y3_NR     (8)
-#define EXYNOS4_GPIO_Y4_NR     (8)
-#define EXYNOS4_GPIO_Y5_NR     (8)
-#define EXYNOS4_GPIO_Y6_NR     (8)
-#define EXYNOS4_GPIO_Z_NR      (7)
-
-/* GPIO bank numbers */
-
-#define EXYNOS4_GPIO_NEXT(__gpio) \
-       ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-       EXYNOS4_GPIO_A0_START   = 0,
-       EXYNOS4_GPIO_A1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
-       EXYNOS4_GPIO_B_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
-       EXYNOS4_GPIO_C0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
-       EXYNOS4_GPIO_C1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
-       EXYNOS4_GPIO_D0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
-       EXYNOS4_GPIO_D1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
-       EXYNOS4_GPIO_E0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
-       EXYNOS4_GPIO_E1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
-       EXYNOS4_GPIO_E2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
-       EXYNOS4_GPIO_E3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
-       EXYNOS4_GPIO_E4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
-       EXYNOS4_GPIO_F0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
-       EXYNOS4_GPIO_F1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
-       EXYNOS4_GPIO_F2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
-       EXYNOS4_GPIO_F3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
-       EXYNOS4_GPIO_J0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
-       EXYNOS4_GPIO_J1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
-       EXYNOS4_GPIO_K0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
-       EXYNOS4_GPIO_K1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
-       EXYNOS4_GPIO_K2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
-       EXYNOS4_GPIO_K3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
-       EXYNOS4_GPIO_L0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
-       EXYNOS4_GPIO_L1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
-       EXYNOS4_GPIO_L2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
-       EXYNOS4_GPIO_X0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
-       EXYNOS4_GPIO_X1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
-       EXYNOS4_GPIO_X2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
-       EXYNOS4_GPIO_X3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
-       EXYNOS4_GPIO_Y0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
-       EXYNOS4_GPIO_Y1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
-       EXYNOS4_GPIO_Y2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
-       EXYNOS4_GPIO_Y3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
-       EXYNOS4_GPIO_Y4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
-       EXYNOS4_GPIO_Y5_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
-       EXYNOS4_GPIO_Y6_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
-       EXYNOS4_GPIO_Z_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
-};
-
-/* EXYNOS4 GPIO number definitions */
-#define EXYNOS4_GPA0(_nr)      (EXYNOS4_GPIO_A0_START + (_nr))
-#define EXYNOS4_GPA1(_nr)      (EXYNOS4_GPIO_A1_START + (_nr))
-#define EXYNOS4_GPB(_nr)       (EXYNOS4_GPIO_B_START + (_nr))
-#define EXYNOS4_GPC0(_nr)      (EXYNOS4_GPIO_C0_START + (_nr))
-#define EXYNOS4_GPC1(_nr)      (EXYNOS4_GPIO_C1_START + (_nr))
-#define EXYNOS4_GPD0(_nr)      (EXYNOS4_GPIO_D0_START + (_nr))
-#define EXYNOS4_GPD1(_nr)      (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr)      (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr)      (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr)      (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr)      (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr)      (EXYNOS4_GPIO_E4_START + (_nr))
-#define EXYNOS4_GPF0(_nr)      (EXYNOS4_GPIO_F0_START + (_nr))
-#define EXYNOS4_GPF1(_nr)      (EXYNOS4_GPIO_F1_START + (_nr))
-#define EXYNOS4_GPF2(_nr)      (EXYNOS4_GPIO_F2_START + (_nr))
-#define EXYNOS4_GPF3(_nr)      (EXYNOS4_GPIO_F3_START + (_nr))
-#define EXYNOS4_GPJ0(_nr)      (EXYNOS4_GPIO_J0_START + (_nr))
-#define EXYNOS4_GPJ1(_nr)      (EXYNOS4_GPIO_J1_START + (_nr))
-#define EXYNOS4_GPK0(_nr)      (EXYNOS4_GPIO_K0_START + (_nr))
-#define EXYNOS4_GPK1(_nr)      (EXYNOS4_GPIO_K1_START + (_nr))
-#define EXYNOS4_GPK2(_nr)      (EXYNOS4_GPIO_K2_START + (_nr))
-#define EXYNOS4_GPK3(_nr)      (EXYNOS4_GPIO_K3_START + (_nr))
-#define EXYNOS4_GPL0(_nr)      (EXYNOS4_GPIO_L0_START + (_nr))
-#define EXYNOS4_GPL1(_nr)      (EXYNOS4_GPIO_L1_START + (_nr))
-#define EXYNOS4_GPL2(_nr)      (EXYNOS4_GPIO_L2_START + (_nr))
-#define EXYNOS4_GPX0(_nr)      (EXYNOS4_GPIO_X0_START + (_nr))
-#define EXYNOS4_GPX1(_nr)      (EXYNOS4_GPIO_X1_START + (_nr))
-#define EXYNOS4_GPX2(_nr)      (EXYNOS4_GPIO_X2_START + (_nr))
-#define EXYNOS4_GPX3(_nr)      (EXYNOS4_GPIO_X3_START + (_nr))
-#define EXYNOS4_GPY0(_nr)      (EXYNOS4_GPIO_Y0_START + (_nr))
-#define EXYNOS4_GPY1(_nr)      (EXYNOS4_GPIO_Y1_START + (_nr))
-#define EXYNOS4_GPY2(_nr)      (EXYNOS4_GPIO_Y2_START + (_nr))
-#define EXYNOS4_GPY3(_nr)      (EXYNOS4_GPIO_Y3_START + (_nr))
-#define EXYNOS4_GPY4(_nr)      (EXYNOS4_GPIO_Y4_START + (_nr))
-#define EXYNOS4_GPY5(_nr)      (EXYNOS4_GPIO_Y5_START + (_nr))
-#define EXYNOS4_GPY6(_nr)      (EXYNOS4_GPIO_Y6_START + (_nr))
-#define EXYNOS4_GPZ(_nr)       (EXYNOS4_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS4 specific gpios */
-#define EXYNOS4_GPIO_END       (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-#define S3C_GPIO_END           EXYNOS4_GPIO_END
-
-/* define the number of gpios we need to the one after the GPZ() range */
-#define ARCH_NR_GPIOS          (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +       \
-                                CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos4/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h
deleted file mode 100644 (file)
index 5109eb2..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h
deleted file mode 100644 (file)
index d5478d2..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/io.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6442/include/mach/io.h
- *
- * Default IO routines for EXYNOS4
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H __FILE__
-
-/* No current ISA/PCI bus support. */
-#define __io(a)                __typesafe_io(a)
-#define __mem_pci(a)   (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
deleted file mode 100644 (file)
index dfd4b7e..0000000
+++ /dev/null
@@ -1,169 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* PPI: Private Peripheral Interrupt */
-
-#define IRQ_PPI(x)             S5P_IRQ(x+16)
-
-#define IRQ_MCT_LOCALTIMER     IRQ_PPI(12)
-
-/* SPI: Shared Peripheral Interrupt */
-
-#define IRQ_SPI(x)             S5P_IRQ(x+32)
-
-#define IRQ_EINT0              IRQ_SPI(16)
-#define IRQ_EINT1              IRQ_SPI(17)
-#define IRQ_EINT2              IRQ_SPI(18)
-#define IRQ_EINT3              IRQ_SPI(19)
-#define IRQ_EINT4              IRQ_SPI(20)
-#define IRQ_EINT5              IRQ_SPI(21)
-#define IRQ_EINT6              IRQ_SPI(22)
-#define IRQ_EINT7              IRQ_SPI(23)
-#define IRQ_EINT8              IRQ_SPI(24)
-#define IRQ_EINT9              IRQ_SPI(25)
-#define IRQ_EINT10             IRQ_SPI(26)
-#define IRQ_EINT11             IRQ_SPI(27)
-#define IRQ_EINT12             IRQ_SPI(28)
-#define IRQ_EINT13             IRQ_SPI(29)
-#define IRQ_EINT14             IRQ_SPI(30)
-#define IRQ_EINT15             IRQ_SPI(31)
-#define IRQ_EINT16_31          IRQ_SPI(32)
-
-#define IRQ_PDMA0              IRQ_SPI(35)
-#define IRQ_PDMA1              IRQ_SPI(36)
-#define IRQ_TIMER0_VIC         IRQ_SPI(37)
-#define IRQ_TIMER1_VIC         IRQ_SPI(38)
-#define IRQ_TIMER2_VIC         IRQ_SPI(39)
-#define IRQ_TIMER3_VIC         IRQ_SPI(40)
-#define IRQ_TIMER4_VIC         IRQ_SPI(41)
-#define IRQ_MCT_L0             IRQ_SPI(42)
-#define IRQ_WDT                        IRQ_SPI(43)
-#define IRQ_RTC_ALARM          IRQ_SPI(44)
-#define IRQ_RTC_TIC            IRQ_SPI(45)
-#define IRQ_GPIO_XB            IRQ_SPI(46)
-#define IRQ_GPIO_XA            IRQ_SPI(47)
-#define IRQ_MCT_L1             IRQ_SPI(48)
-
-#define IRQ_UART0              IRQ_SPI(52)
-#define IRQ_UART1              IRQ_SPI(53)
-#define IRQ_UART2              IRQ_SPI(54)
-#define IRQ_UART3              IRQ_SPI(55)
-#define IRQ_UART4              IRQ_SPI(56)
-#define IRQ_MCT_G0             IRQ_SPI(57)
-#define IRQ_IIC                        IRQ_SPI(58)
-#define IRQ_IIC1               IRQ_SPI(59)
-#define IRQ_IIC2               IRQ_SPI(60)
-#define IRQ_IIC3               IRQ_SPI(61)
-#define IRQ_IIC4               IRQ_SPI(62)
-#define IRQ_IIC5               IRQ_SPI(63)
-#define IRQ_IIC6               IRQ_SPI(64)
-#define IRQ_IIC7               IRQ_SPI(65)
-
-#define IRQ_USB_HOST           IRQ_SPI(70)
-#define IRQ_USB_HSOTG          IRQ_SPI(71)
-#define IRQ_MODEM_IF           IRQ_SPI(72)
-#define IRQ_HSMMC0             IRQ_SPI(73)
-#define IRQ_HSMMC1             IRQ_SPI(74)
-#define IRQ_HSMMC2             IRQ_SPI(75)
-#define IRQ_HSMMC3             IRQ_SPI(76)
-#define IRQ_DWMCI              IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0         IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1         IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI       IRQ_SPI(82)
-#define IRQ_ROTATOR            IRQ_SPI(83)
-#define IRQ_FIMC0              IRQ_SPI(84)
-#define IRQ_FIMC1              IRQ_SPI(85)
-#define IRQ_FIMC2              IRQ_SPI(86)
-#define IRQ_FIMC3              IRQ_SPI(87)
-#define IRQ_JPEG               IRQ_SPI(88)
-#define IRQ_2D                 IRQ_SPI(89)
-#define IRQ_PCIE               IRQ_SPI(90)
-
-#define IRQ_MIXER              IRQ_SPI(91)
-#define IRQ_HDMI               IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY                IRQ_SPI(93)
-#define IRQ_MFC                        IRQ_SPI(94)
-#define IRQ_SDO                        IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS           IRQ_SPI(96)
-#define IRQ_I2S0               IRQ_SPI(97)
-#define IRQ_I2S1               IRQ_SPI(98)
-#define IRQ_I2S2               IRQ_SPI(99)
-#define IRQ_AC97               IRQ_SPI(100)
-
-#define IRQ_SPDIF              IRQ_SPI(104)
-#define IRQ_ADC0               IRQ_SPI(105)
-#define IRQ_PEN0               IRQ_SPI(106)
-#define IRQ_ADC1               IRQ_SPI(107)
-#define IRQ_PEN1               IRQ_SPI(108)
-#define IRQ_KEYPAD             IRQ_SPI(109)
-#define IRQ_PMU                        IRQ_SPI(110)
-#define IRQ_GPS                        IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
-#define IRQ_SLIMBUS            IRQ_SPI(113)
-
-#define IRQ_TSI                        IRQ_SPI(115)
-#define IRQ_SATA               IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER    8
-#define COMBINER_GROUP(x)      ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)     (COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0     COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0     COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0     COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0      COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0                COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0   COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0     COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0   COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0   COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0     COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0    COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0    COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0      COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO         COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR                16
-
-#define IRQ_ADC                        IRQ_ADC0
-#define IRQ_TC                 IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE      COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1         (S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2         (S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE       (S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS    16
-#define IRQ_GPIO2_NR_GROUPS    9
-#define IRQ_GPIO_END           (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-/* Set the default NR_IRQS */
-#define NR_IRQS                        (IRQ_GPIO_END + 64)
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
deleted file mode 100644 (file)
index 918a979..0000000
+++ /dev/null
@@ -1,191 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/map.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * EXYNOS4 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-
-/*
- * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
- * So need to define it, and here is to avoid redefinition warning.
- */
-#define S3C_UART_OFFSET                        (0x10000)
-
-#include <plat/map-s5p.h>
-
-#define EXYNOS4_PA_SYSRAM0             0x02025000
-#define EXYNOS4_PA_SYSRAM1             0x02020000
-
-#define EXYNOS4_PA_FIMC0               0x11800000
-#define EXYNOS4_PA_FIMC1               0x11810000
-#define EXYNOS4_PA_FIMC2               0x11820000
-#define EXYNOS4_PA_FIMC3               0x11830000
-
-#define EXYNOS4_PA_I2S0                        0x03830000
-#define EXYNOS4_PA_I2S1                        0xE3100000
-#define EXYNOS4_PA_I2S2                        0xE2A00000
-
-#define EXYNOS4_PA_PCM0                        0x03840000
-#define EXYNOS4_PA_PCM1                        0x13980000
-#define EXYNOS4_PA_PCM2                        0x13990000
-
-#define EXYNOS4_PA_SROM_BANK(x)                (0x04000000 + ((x) * 0x01000000))
-
-#define EXYNOS4_PA_ONENAND             0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA         0x0C600000
-
-#define EXYNOS4_PA_CHIPID              0x10000000
-
-#define EXYNOS4_PA_SYSCON              0x10010000
-#define EXYNOS4_PA_PMU                 0x10020000
-#define EXYNOS4_PA_CMU                 0x10030000
-
-#define EXYNOS4_PA_SYSTIMER            0x10050000
-#define EXYNOS4_PA_WATCHDOG            0x10060000
-#define EXYNOS4_PA_RTC                 0x10070000
-
-#define EXYNOS4_PA_KEYPAD              0x100A0000
-
-#define EXYNOS4_PA_DMC0                        0x10400000
-
-#define EXYNOS4_PA_COMBINER            0x10440000
-
-#define EXYNOS4_PA_GIC_CPU             0x10480000
-#define EXYNOS4_PA_GIC_DIST            0x10490000
-
-#define EXYNOS4_PA_COREPERI            0x10500000
-#define EXYNOS4_PA_TWD                 0x10500600
-#define EXYNOS4_PA_L2CC                        0x10502000
-
-#define EXYNOS4_PA_MDMA                        0x10810000
-#define EXYNOS4_PA_PDMA0               0x12680000
-#define EXYNOS4_PA_PDMA1               0x12690000
-
-#define EXYNOS4_PA_SYSMMU_MDMA         0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS          0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0                0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1                0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2                0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3                0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG         0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0                0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1                0x12220000
-#define EXYNOS4_PA_SYSMMU_PCIe         0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D          0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR      0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2                0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV           0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L                0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R                0x13630000
-
-#define EXYNOS4_PA_GPIO1               0x11400000
-#define EXYNOS4_PA_GPIO2               0x11000000
-#define EXYNOS4_PA_GPIO3               0x03860000
-
-#define EXYNOS4_PA_MIPI_CSIS0          0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1          0x11890000
-
-#define EXYNOS4_PA_FIMD0               0x11C00000
-
-#define EXYNOS4_PA_HSMMC(x)            (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI               0x12550000
-
-#define EXYNOS4_PA_SATA                        0x12560000
-#define EXYNOS4_PA_SATAPHY             0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL                0x126B0000
-
-#define EXYNOS4_PA_SROMC               0x12570000
-
-#define EXYNOS4_PA_EHCI                        0x12580000
-#define EXYNOS4_PA_HSPHY               0x125B0000
-#define EXYNOS4_PA_MFC                 0x13400000
-
-#define EXYNOS4_PA_UART                        0x13800000
-
-#define EXYNOS4_PA_VP                  0x12C00000
-#define EXYNOS4_PA_MIXER               0x12C10000
-#define EXYNOS4_PA_SDO                 0x12C20000
-#define EXYNOS4_PA_HDMI                        0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY         0x138E0000
-
-#define EXYNOS4_PA_IIC(x)              (0x13860000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_ADC                 0x13910000
-#define EXYNOS4_PA_ADC1                        0x13911000
-
-#define EXYNOS4_PA_AC97                        0x139A0000
-
-#define EXYNOS4_PA_SPDIF               0x139B0000
-
-#define EXYNOS4_PA_TIMER               0x139D0000
-
-#define EXYNOS4_PA_SDRAM               0x40000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0                  EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                  EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                  EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                  EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC                     EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1                    EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2                    EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3                    EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4                    EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5                    EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6                    EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7                    EXYNOS4_PA_IIC(7)
-#define SAMSUNG_PA_ADC                 EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1                        EXYNOS4_PA_ADC1
-#define S3C_PA_RTC                     EXYNOS4_PA_RTC
-#define S3C_PA_WDT                     EXYNOS4_PA_WATCHDOG
-
-#define S5P_PA_CHIPID                  EXYNOS4_PA_CHIPID
-#define S5P_PA_FIMC0                   EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1                   EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2                   EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3                   EXYNOS4_PA_FIMC3
-#define S5P_PA_MIPI_CSIS0              EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1              EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_FIMD0                   EXYNOS4_PA_FIMD0
-#define S5P_PA_ONENAND                 EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA             EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDRAM                   EXYNOS4_PA_SDRAM
-#define S5P_PA_SROMC                   EXYNOS4_PA_SROMC
-#define S5P_PA_MFC                     EXYNOS4_PA_MFC
-#define S5P_PA_SYSCON                  EXYNOS4_PA_SYSCON
-#define S5P_PA_TIMER                   EXYNOS4_PA_TIMER
-#define S5P_PA_EHCI                    EXYNOS4_PA_EHCI
-
-#define S5P_PA_SDO                     EXYNOS4_PA_SDO
-#define S5P_PA_VP                      EXYNOS4_PA_VP
-#define S5P_PA_MIXER                   EXYNOS4_PA_MIXER
-#define S5P_PA_HDMI                    EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY             EXYNOS4_PA_IIC_HDMIPHY
-
-#define SAMSUNG_PA_KEYPAD              EXYNOS4_PA_KEYPAD
-
-/* UART */
-
-#define S3C_PA_UART                    EXYNOS4_PA_UART
-
-#define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                   S5P_PA_UART(0)
-#define S5P_PA_UART1                   S5P_PA_UART(1)
-#define S5P_PA_UART2                   S5P_PA_UART(2)
-#define S5P_PA_UART3                   S5P_PA_UART(3)
-#define S5P_PA_UART4                   S5P_PA_UART(4)
-
-#define S5P_SZ_UART                    SZ_256
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos4/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h
deleted file mode 100644 (file)
index 374ef2c..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/memory.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Memory definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H __FILE__
-
-#define PLAT_PHYS_OFFSET               UL(0x40000000)
-
-/* Maximum of 256MiB in one bank */
-#define MAX_PHYSMEM_BITS       32
-#define SECTION_SIZE_BITS      28
-
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
deleted file mode 100644 (file)
index 9d8da51..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PM_CORE_H
-#define __ASM_ARCH_PM_CORE_H __FILE__
-
-#include <mach/regs-pmu.h>
-
-static inline void s3c_pm_debug_init_uart(void)
-{
-       /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-       unsigned int tmp;
-       tmp = __raw_readl(S5P_WAKEUP_MASK);
-       tmp &= ~(1 << 31);
-       __raw_writel(tmp, S5P_WAKEUP_MASK);
-
-       __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-       __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
-}
-
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-       /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-       /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
-                                          struct pm_uart_save *save)
-{
-       /* nothing here yet */
-}
-
-static inline void s3c_pm_restored_gpios(void)
-{
-       /* nothing here yet */
-}
-
-static inline void samsung_pm_saved_gpios(void)
-{
-       /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
deleted file mode 100644 (file)
index 632dd56..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * EXYNOS4210 - PMU(Power Management Unit) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PMU_H
-#define __ASM_ARCH_PMU_H __FILE__
-
-#define PMU_TABLE_END  NULL
-
-enum sys_powerdown {
-       SYS_AFTR,
-       SYS_LPA,
-       SYS_SLEEP,
-       NUM_SYS_POWERDOWN,
-};
-
-struct exynos4_pmu_conf {
-       void __iomem *reg;
-       unsigned int val[NUM_SYS_POWERDOWN];
-};
-
-extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
-
-#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
deleted file mode 100644 (file)
index ca5a8b6..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-audss.h
- *
- * Copyright (c) 2011 Samsung Electronics
- *             http://www.samsung.com
- *
- * Exynos4 Audio SubSystem clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_REGS_AUDSS_H
-#define __PLAT_REGS_AUDSS_H __FILE__
-
-#define EXYNOS4_AUDSS_INT_MEM  (0x03000000)
-
-#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
deleted file mode 100644 (file)
index 6c37ebe..0000000
+++ /dev/null
@@ -1,210 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <plat/cpu.h>
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)                  (S5P_VA_CMU + (x))
-
-#define S5P_CLKDIV_LEFTBUS             S5P_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS                S5P_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS         S5P_CLKREG(0x04800)
-
-#define S5P_CLKDIV_RIGHTBUS            S5P_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS       S5P_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS                S5P_CLKREG(0x08800)
-
-#define S5P_EPLL_LOCK                  S5P_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK                  S5P_CLKREG(0x0C020)
-
-#define S5P_EPLL_CON0                  S5P_CLKREG(0x0C110)
-#define S5P_EPLL_CON1                  S5P_CLKREG(0x0C114)
-#define S5P_VPLL_CON0                  S5P_CLKREG(0x0C120)
-#define S5P_VPLL_CON1                  S5P_CLKREG(0x0C124)
-
-#define S5P_CLKSRC_TOP0                        S5P_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1                        S5P_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM                 S5P_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV                  S5P_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC                 S5P_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D                 S5P_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE               S5P_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0                        S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO              S5P_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS                        S5P_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0              S5P_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1              S5P_CLKREG(0x0C254)
-
-#define S5P_CLKSRC_MASK_TOP            S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM            S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV             S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0           S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO         S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS           S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0         S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1         S5P_CLKREG(0x0C354)
-
-#define S5P_CLKDIV_TOP                 S5P_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM                 S5P_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV                  S5P_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC                 S5P_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D                 S5P_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE               S5P_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0                        S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO              S5P_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0               S5P_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1               S5P_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2               S5P_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3               S5P_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0              S5P_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1              S5P_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2              S5P_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3              S5P_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4              S5P_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5              S5P_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO              S5P_CLKREG(0x0C580)
-
-#define S5P_CLKDIV_STAT_TOP            S5P_CLKREG(0x0C610)
-
-#define S5P_CLKGATE_SCLKCAM            S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM             S5P_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_TV              S5P_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_MFC             S5P_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_G3D             S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE           (soc_is_exynos4210() ? \
-                                       S5P_CLKREG(0x0C930) : \
-                                       S5P_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4210      S5P_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_IMAGE_4212      S5P_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_LCD0            S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_FSYS            S5P_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_GPS             S5P_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIL           S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR           (soc_is_exynos4210() ? \
-                                       S5P_CLKREG(0x0C960) : \
-                                       S5P_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4210      S5P_CLKREG(0x0C960)
-#define S5P_CLKGATE_IP_PERIR_4212      S5P_CLKREG(0x08960)
-#define S5P_CLKGATE_BLOCK              S5P_CLKREG(0x0C970)
-
-#define S5P_CLKSRC_MASK_DMC            S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC                 S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC0                        S5P_CLKREG(0x10500)
-#define S5P_CLKDIV_DMC1                        S5P_CLKREG(0x10504)
-#define S5P_CLKDIV_STAT_DMC0           S5P_CLKREG(0x10600)
-#define S5P_CLKGATE_IP_DMC             S5P_CLKREG(0x10900)
-
-#define S5P_APLL_LOCK                  S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK                  (soc_is_exynos4210() ? \
-                                       S5P_CLKREG(0x14004) :  \
-                                       S5P_CLKREG(0x10008))
-#define S5P_APLL_CON0                  S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1                  S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0                  (soc_is_exynos4210() ? \
-                                       S5P_CLKREG(0x14108) : \
-                                       S5P_CLKREG(0x10108))
-#define S5P_MPLL_CON1                  (soc_is_exynos4210() ? \
-                                       S5P_CLKREG(0x1410C) : \
-                                       S5P_CLKREG(0x1010C))
-
-#define S5P_CLKSRC_CPU                 S5P_CLKREG(0x14200)
-#define S5P_CLKMUX_STATCPU             S5P_CLKREG(0x14400)
-
-#define S5P_CLKDIV_CPU                 S5P_CLKREG(0x14500)
-#define S5P_CLKDIV_CPU1                        S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU             S5P_CLKREG(0x14600)
-#define S5P_CLKDIV_STATCPU1            S5P_CLKREG(0x14604)
-
-#define S5P_CLKGATE_SCLKCPU            S5P_CLKREG(0x14800)
-#define S5P_CLKGATE_IP_CPU             S5P_CLKREG(0x14900)
-
-#define S5P_APLL_LOCKTIME              (0x1C20)        /* 300us */
-
-#define S5P_APLLCON0_ENABLE_SHIFT      (31)
-#define S5P_APLLCON0_LOCKED_SHIFT      (29)
-#define S5P_APLL_VAL_1000              ((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800               ((200 << 16) | (6 << 8) | 1)
-
-#define S5P_EPLLCON0_ENABLE_SHIFT      (31)
-#define S5P_EPLLCON0_LOCKED_SHIFT      (29)
-
-#define S5P_VPLLCON0_ENABLE_SHIFT      (31)
-#define S5P_VPLLCON0_LOCKED_SHIFT      (29)
-
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT   (16)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK        (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define S5P_CLKDIV_CPU0_CORE_SHIFT     (0)
-#define S5P_CLKDIV_CPU0_CORE_MASK      (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT   (4)
-#define S5P_CLKDIV_CPU0_COREM0_MASK    (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT   (8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK    (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT   (12)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK    (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT      (16)
-#define S5P_CLKDIV_CPU0_ATB_MASK       (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT  (20)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK   (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT     (24)
-#define S5P_CLKDIV_CPU0_APLL_MASK      (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
-
-#define S5P_CLKDIV_DMC0_ACP_SHIFT      (0)
-#define S5P_CLKDIV_DMC0_ACP_MASK       (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT  (4)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK   (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT     (8)
-#define S5P_CLKDIV_DMC0_DPHY_MASK      (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT      (12)
-#define S5P_CLKDIV_DMC0_DMC_MASK       (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT     (16)
-#define S5P_CLKDIV_DMC0_DMCD_MASK      (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT     (20)
-#define S5P_CLKDIV_DMC0_DMCP_MASK      (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT    (24)
-#define S5P_CLKDIV_DMC0_COPY2_MASK     (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT   (28)
-#define S5P_CLKDIV_DMC0_CORETI_MASK    (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT   (0)
-#define S5P_CLKDIV_TOP_ACLK200_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT   (4)
-#define S5P_CLKDIV_TOP_ACLK100_MASK    (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT   (8)
-#define S5P_CLKDIV_TOP_ACLK160_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT   (12)
-#define S5P_CLKDIV_TOP_ACLK133_MASK    (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT   (16)
-#define S5P_CLKDIV_TOP_ONENAND_MASK    (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
-
-#define S5P_CLKDIV_BUS_GDLR_SHIFT      (0)
-#define S5P_CLKDIV_BUS_GDLR_MASK       (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT      (4)
-#define S5P_CLKDIV_BUS_GPLR_MASK       (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
-
-/* Only for EXYNOS4210 */
-
-#define S5P_CLKSRC_LCD1                        S5P_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1           S5P_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1                        S5P_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1            S5P_CLKREG(0x0C938)
-
-/* Compatibility defines and inclusion */
-
-#include <mach/regs-pmu.h>
-
-#define S5P_EPLL_CON                   S5P_EPLL_CON0
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
deleted file mode 100644 (file)
index 1401b21..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#define EXYNOS4_EINT40CON              (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x)                        (EXYNOS4_EINT40CON + ((x) * 0x4))
-
-#define EXYNOS4_EINT40FLTCON0          (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x)             (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
-
-#define EXYNOS4_EINT40MASK             (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x)               (EXYNOS4_EINT40MASK + ((x) * 0x4))
-
-#define EXYNOS4_EINT40PEND             (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x)               (EXYNOS4_EINT40PEND + ((x) * 0x4))
-
-#define EINT_REG_NR(x)                 (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)           (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE                      S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)                 EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x)                 EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x)                 EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x)                 EXYNOS4_GPX3(x)
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-irq.h b/arch/arm/mach-exynos4/include/mach/regs-irq.h
deleted file mode 100644 (file)
index 9c7b4bf..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <asm/hardware/gic.h>
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
deleted file mode 100644 (file)
index 80dd02a..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)              (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L            EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U            EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT                EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L          EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U          EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR   EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON             EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT                EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB          EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT            EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE            EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)          (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK             (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET             (0x00)
-#define MCT_L_ICNTB_OFFSET             (0x08)
-#define MCT_L_TCON_OFFSET              (0x20)
-#define MCT_L_INT_CSTAT_OFFSET         (0x30)
-#define MCT_L_INT_ENB_OFFSET           (0x34)
-#define MCT_L_WSTAT_OFFSET             (0x40)
-
-#define MCT_G_TCON_START               (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC      (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE                (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE       (1 << 2)
-#define MCT_L_TCON_INT_START           (1 << 1)
-#define MCT_L_TCON_TIMER_START         (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h
deleted file mode 100644 (file)
index 0368b5a..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - SROMC and DMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MEM_H
-#define __ASM_ARCH_REGS_MEM_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_DMC0_MEMCON_OFFSET         0x04
-
-#define S5P_DMC0_MEMTYPE_SHIFT         8
-#define S5P_DMC0_MEMTYPE_MASK          0xF
-
-#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
deleted file mode 100644 (file)
index 4fff8e9..0000000
+++ /dev/null
@@ -1,220 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Power management unit definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_PMU_H
-#define __ASM_ARCH_REGS_PMU_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_PMUREG(x)                          (S5P_VA_PMU + (x))
-
-#define S5P_CENTRAL_SEQ_CONFIGURATION          S5P_PMUREG(0x0200)
-
-#define S5P_CENTRAL_LOWPWR_CFG                 (1 << 16)
-
-#define S5P_CENTRAL_SEQ_OPTION                 S5P_PMUREG(0x0208)
-
-#define S5P_USE_STANDBY_WFI0                   (1 << 16)
-#define S5P_USE_STANDBY_WFI1                   (1 << 17)
-#define S5P_USE_STANDBYWFI_ISP_ARM             (1 << 18)
-#define S5P_USE_STANDBY_WFE0                   (1 << 24)
-#define S5P_USE_STANDBY_WFE1                   (1 << 25)
-#define S5P_USE_STANDBYWFE_ISP_ARM             (1 << 26)
-
-#define S5P_SWRESET                            S5P_PMUREG(0x0400)
-
-#define S5P_WAKEUP_STAT                                S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK                   S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK                                S5P_PMUREG(0x0608)
-
-#define S5P_HDMI_PHY_CONTROL                   S5P_PMUREG(0x0700)
-#define S5P_HDMI_PHY_ENABLE                    (1 << 0)
-
-#define S5P_DAC_PHY_CONTROL                    S5P_PMUREG(0x070C)
-#define S5P_DAC_PHY_ENABLE                     (1 << 0)
-
-#define S5P_MIPI_DPHY_CONTROL(n)               S5P_PMUREG(0x0710 + (n) * 4)
-#define S5P_MIPI_DPHY_ENABLE                   (1 << 0)
-#define S5P_MIPI_DPHY_SRESETN                  (1 << 1)
-#define S5P_MIPI_DPHY_MRESETN                  (1 << 2)
-
-#define S5P_INFORM0                            S5P_PMUREG(0x0800)
-#define S5P_INFORM1                            S5P_PMUREG(0x0804)
-#define S5P_INFORM2                            S5P_PMUREG(0x0808)
-#define S5P_INFORM3                            S5P_PMUREG(0x080C)
-#define S5P_INFORM4                            S5P_PMUREG(0x0810)
-#define S5P_INFORM5                            S5P_PMUREG(0x0814)
-#define S5P_INFORM6                            S5P_PMUREG(0x0818)
-#define S5P_INFORM7                            S5P_PMUREG(0x081C)
-
-#define S5P_ARM_CORE0_LOWPWR                   S5P_PMUREG(0x1000)
-#define S5P_DIS_IRQ_CORE0                      S5P_PMUREG(0x1004)
-#define S5P_DIS_IRQ_CENTRAL0                   S5P_PMUREG(0x1008)
-#define S5P_ARM_CORE1_LOWPWR                   S5P_PMUREG(0x1010)
-#define S5P_DIS_IRQ_CORE1                      S5P_PMUREG(0x1014)
-#define S5P_DIS_IRQ_CENTRAL1                   S5P_PMUREG(0x1018)
-#define S5P_ARM_COMMON_LOWPWR                  S5P_PMUREG(0x1080)
-#define S5P_L2_0_LOWPWR                                S5P_PMUREG(0x10C0)
-#define S5P_L2_1_LOWPWR                                S5P_PMUREG(0x10C4)
-#define S5P_CMU_ACLKSTOP_LOWPWR                        S5P_PMUREG(0x1100)
-#define S5P_CMU_SCLKSTOP_LOWPWR                        S5P_PMUREG(0x1104)
-#define S5P_CMU_RESET_LOWPWR                   S5P_PMUREG(0x110C)
-#define S5P_APLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1120)
-#define S5P_MPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1124)
-#define S5P_VPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x1128)
-#define S5P_EPLL_SYSCLK_LOWPWR                 S5P_PMUREG(0x112C)
-#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR       S5P_PMUREG(0x1138)
-#define S5P_CMU_RESET_GPSALIVE_LOWPWR          S5P_PMUREG(0x113C)
-#define S5P_CMU_CLKSTOP_CAM_LOWPWR             S5P_PMUREG(0x1140)
-#define S5P_CMU_CLKSTOP_TV_LOWPWR              S5P_PMUREG(0x1144)
-#define S5P_CMU_CLKSTOP_MFC_LOWPWR             S5P_PMUREG(0x1148)
-#define S5P_CMU_CLKSTOP_G3D_LOWPWR             S5P_PMUREG(0x114C)
-#define S5P_CMU_CLKSTOP_LCD0_LOWPWR            S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          S5P_PMUREG(0x1158)
-#define S5P_CMU_CLKSTOP_GPS_LOWPWR             S5P_PMUREG(0x115C)
-#define S5P_CMU_RESET_CAM_LOWPWR               S5P_PMUREG(0x1160)
-#define S5P_CMU_RESET_TV_LOWPWR                        S5P_PMUREG(0x1164)
-#define S5P_CMU_RESET_MFC_LOWPWR               S5P_PMUREG(0x1168)
-#define S5P_CMU_RESET_G3D_LOWPWR               S5P_PMUREG(0x116C)
-#define S5P_CMU_RESET_LCD0_LOWPWR              S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_MAUDIO_LOWPWR            S5P_PMUREG(0x1178)
-#define S5P_CMU_RESET_GPS_LOWPWR               S5P_PMUREG(0x117C)
-#define S5P_TOP_BUS_LOWPWR                     S5P_PMUREG(0x1180)
-#define S5P_TOP_RETENTION_LOWPWR               S5P_PMUREG(0x1184)
-#define S5P_TOP_PWR_LOWPWR                     S5P_PMUREG(0x1188)
-#define S5P_LOGIC_RESET_LOWPWR                 S5P_PMUREG(0x11A0)
-#define S5P_ONENAND_MEM_LOWPWR                 S5P_PMUREG(0x11C0)
-#define S5P_G2D_ACP_MEM_LOWPWR                 S5P_PMUREG(0x11C8)
-#define S5P_USBOTG_MEM_LOWPWR                  S5P_PMUREG(0x11CC)
-#define S5P_HSMMC_MEM_LOWPWR                   S5P_PMUREG(0x11D0)
-#define S5P_CSSYS_MEM_LOWPWR                   S5P_PMUREG(0x11D4)
-#define S5P_SECSS_MEM_LOWPWR                   S5P_PMUREG(0x11D8)
-#define S5P_PAD_RETENTION_DRAM_LOWPWR          S5P_PMUREG(0x1200)
-#define S5P_PAD_RETENTION_MAUDIO_LOWPWR                S5P_PMUREG(0x1204)
-#define S5P_PAD_RETENTION_GPIO_LOWPWR          S5P_PMUREG(0x1220)
-#define S5P_PAD_RETENTION_UART_LOWPWR          S5P_PMUREG(0x1224)
-#define S5P_PAD_RETENTION_MMCA_LOWPWR          S5P_PMUREG(0x1228)
-#define S5P_PAD_RETENTION_MMCB_LOWPWR          S5P_PMUREG(0x122C)
-#define S5P_PAD_RETENTION_EBIA_LOWPWR          S5P_PMUREG(0x1230)
-#define S5P_PAD_RETENTION_EBIB_LOWPWR          S5P_PMUREG(0x1234)
-#define S5P_PAD_RETENTION_ISOLATION_LOWPWR     S5P_PMUREG(0x1240)
-#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR       S5P_PMUREG(0x1260)
-#define S5P_XUSBXTI_LOWPWR                     S5P_PMUREG(0x1280)
-#define S5P_XXTI_LOWPWR                                S5P_PMUREG(0x1284)
-#define S5P_EXT_REGULATOR_LOWPWR               S5P_PMUREG(0x12C0)
-#define S5P_GPIO_MODE_LOWPWR                   S5P_PMUREG(0x1300)
-#define S5P_GPIO_MODE_MAUDIO_LOWPWR            S5P_PMUREG(0x1340)
-#define S5P_CAM_LOWPWR                         S5P_PMUREG(0x1380)
-#define S5P_TV_LOWPWR                          S5P_PMUREG(0x1384)
-#define S5P_MFC_LOWPWR                         S5P_PMUREG(0x1388)
-#define S5P_G3D_LOWPWR                         S5P_PMUREG(0x138C)
-#define S5P_LCD0_LOWPWR                                S5P_PMUREG(0x1390)
-#define S5P_MAUDIO_LOWPWR                      S5P_PMUREG(0x1398)
-#define S5P_GPS_LOWPWR                         S5P_PMUREG(0x139C)
-#define S5P_GPS_ALIVE_LOWPWR                   S5P_PMUREG(0x13A0)
-
-#define S5P_ARM_CORE0_CONFIGURATION            S5P_PMUREG(0x2000)
-#define S5P_ARM_CORE0_OPTION                   S5P_PMUREG(0x2008)
-#define S5P_ARM_CORE1_CONFIGURATION            S5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS                   S5P_PMUREG(0x2084)
-#define S5P_ARM_CORE1_OPTION                   S5P_PMUREG(0x2088)
-
-#define S5P_ARM_COMMON_OPTION                  S5P_PMUREG(0x2408)
-#define S5P_TOP_PWR_OPTION                     S5P_PMUREG(0x2C48)
-#define S5P_CAM_OPTION                         S5P_PMUREG(0x3C08)
-#define S5P_TV_OPTION                          S5P_PMUREG(0x3C28)
-#define S5P_MFC_OPTION                         S5P_PMUREG(0x3C48)
-#define S5P_G3D_OPTION                         S5P_PMUREG(0x3C68)
-#define S5P_LCD0_OPTION                                S5P_PMUREG(0x3C88)
-#define S5P_LCD1_OPTION                                S5P_PMUREG(0x3CA8)
-#define S5P_MAUDIO_OPTION                      S5P_PMUREG(0x3CC8)
-#define S5P_GPS_OPTION                         S5P_PMUREG(0x3CE8)
-#define S5P_GPS_ALIVE_OPTION                   S5P_PMUREG(0x3D08)
-
-#define S5P_PAD_RET_MAUDIO_OPTION              S5P_PMUREG(0x3028)
-#define S5P_PAD_RET_GPIO_OPTION                        S5P_PMUREG(0x3108)
-#define S5P_PAD_RET_UART_OPTION                        S5P_PMUREG(0x3128)
-#define S5P_PAD_RET_MMCA_OPTION                        S5P_PMUREG(0x3148)
-#define S5P_PAD_RET_MMCB_OPTION                        S5P_PMUREG(0x3168)
-#define S5P_PAD_RET_EBIA_OPTION                        S5P_PMUREG(0x3188)
-#define S5P_PAD_RET_EBIB_OPTION                        S5P_PMUREG(0x31A8)
-
-#define S5P_PMU_CAM_CONF                       S5P_PMUREG(0x3C00)
-#define S5P_PMU_TV_CONF                                S5P_PMUREG(0x3C20)
-#define S5P_PMU_MFC_CONF                       S5P_PMUREG(0x3C40)
-#define S5P_PMU_G3D_CONF                       S5P_PMUREG(0x3C60)
-#define S5P_PMU_LCD0_CONF                      S5P_PMUREG(0x3C80)
-#define S5P_PMU_GPS_CONF                       S5P_PMUREG(0x3CE0)
-
-#define S5P_PMU_SATA_PHY_CONTROL_EN            0x1
-#define S5P_CORE_LOCAL_PWR_EN                  0x3
-#define S5P_INT_LOCAL_PWR_EN                   0x7
-
-#define S5P_CHECK_SLEEP                                0x00000BAD
-
-/* Only for EXYNOS4210 */
-#define S5P_USBHOST_PHY_CONTROL                S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE         (1 << 0)
-
-#define S5P_PMU_SATA_PHY_CONTROL       S5P_PMUREG(0x0720)
-
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR    S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_LCD1_LOWPWR      S5P_PMUREG(0x1174)
-#define S5P_MODIMIF_MEM_LOWPWR         S5P_PMUREG(0x11C4)
-#define S5P_PCIE_MEM_LOWPWR            S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR            S5P_PMUREG(0x11E4)
-#define S5P_LCD1_LOWPWR                        S5P_PMUREG(0x1394)
-
-#define S5P_PMU_LCD1_CONF              S5P_PMUREG(0x3CA0)
-
-/* Only for EXYNOS4212 */
-#define S5P_ISP_ARM_LOWPWR                     S5P_PMUREG(0x1050)
-#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR       S5P_PMUREG(0x1054)
-#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR     S5P_PMUREG(0x1058)
-#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1110)
-#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1114)
-#define S5P_CMU_RESET_COREBLK_LOWPWR           S5P_PMUREG(0x111C)
-#define S5P_MPLLUSER_SYSCLK_LOWPWR             S5P_PMUREG(0x1130)
-#define S5P_CMU_CLKSTOP_ISP_LOWPWR             S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_ISP_LOWPWR               S5P_PMUREG(0x1174)
-#define S5P_TOP_BUS_COREBLK_LOWPWR             S5P_PMUREG(0x1190)
-#define S5P_TOP_RETENTION_COREBLK_LOWPWR       S5P_PMUREG(0x1194)
-#define S5P_TOP_PWR_COREBLK_LOWPWR             S5P_PMUREG(0x1198)
-#define S5P_OSCCLK_GATE_LOWPWR                 S5P_PMUREG(0x11A4)
-#define S5P_LOGIC_RESET_COREBLK_LOWPWR         S5P_PMUREG(0x11B0)
-#define S5P_OSCCLK_GATE_COREBLK_LOWPWR         S5P_PMUREG(0x11B4)
-#define S5P_HSI_MEM_LOWPWR                     S5P_PMUREG(0x11C4)
-#define S5P_ROTATOR_MEM_LOWPWR                 S5P_PMUREG(0x11DC)
-#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR  S5P_PMUREG(0x123C)
-#define S5P_PAD_ISOLATION_COREBLK_LOWPWR       S5P_PMUREG(0x1250)
-#define S5P_GPIO_MODE_COREBLK_LOWPWR           S5P_PMUREG(0x1320)
-#define S5P_TOP_ASB_RESET_LOWPWR               S5P_PMUREG(0x1344)
-#define S5P_TOP_ASB_ISOLATION_LOWPWR           S5P_PMUREG(0x1348)
-#define S5P_ISP_LOWPWR                         S5P_PMUREG(0x1394)
-#define S5P_DRAM_FREQ_DOWN_LOWPWR              S5P_PMUREG(0x13B0)
-#define S5P_DDRPHY_DLLOFF_LOWPWR               S5P_PMUREG(0x13B4)
-#define S5P_CMU_SYSCLK_ISP_LOWPWR              S5P_PMUREG(0x13B8)
-#define S5P_CMU_SYSCLK_GPS_LOWPWR              S5P_PMUREG(0x13BC)
-#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR          S5P_PMUREG(0x13C0)
-
-#define S5P_ARM_L2_0_OPTION                    S5P_PMUREG(0x2608)
-#define S5P_ARM_L2_1_OPTION                    S5P_PMUREG(0x2628)
-#define S5P_ONENAND_MEM_OPTION                 S5P_PMUREG(0x2E08)
-#define S5P_HSI_MEM_OPTION                     S5P_PMUREG(0x2E28)
-#define S5P_G2D_ACP_MEM_OPTION                 S5P_PMUREG(0x2E48)
-#define S5P_USBOTG_MEM_OPTION                  S5P_PMUREG(0x2E68)
-#define S5P_HSMMC_MEM_OPTION                   S5P_PMUREG(0x2E88)
-#define S5P_CSSYS_MEM_OPTION                   S5P_PMUREG(0x2EA8)
-#define S5P_SECSS_MEM_OPTION                   S5P_PMUREG(0x2EC8)
-#define S5P_ROTATOR_MEM_OPTION                 S5P_PMUREG(0x2F48)
-
-#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
deleted file mode 100644 (file)
index 68ff6ad..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - System MMU register
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYSMMU_H
-#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
-
-#define S5P_MMU_CTRL                   0x000
-#define S5P_MMU_CFG                    0x004
-#define S5P_MMU_STATUS                 0x008
-#define S5P_MMU_FLUSH                  0x00C
-#define S5P_PT_BASE_ADDR               0x014
-#define S5P_INT_STATUS                 0x018
-#define S5P_INT_CLEAR                  0x01C
-#define S5P_PAGE_FAULT_ADDR            0x024
-#define S5P_AW_FAULT_ADDR              0x028
-#define S5P_AR_FAULT_ADDR              0x02C
-#define S5P_DEFAULT_SLAVE_ADDR         0x030
-
-#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
deleted file mode 100644 (file)
index c337cf3..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-
-#define EXYNOS4_HSOTG_PHYREG(x)                ((x) + S3C_VA_USB_HSPHY)
-
-#define EXYNOS4_PHYPWR                 EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK          (0xf << 9)
-#define PHY1_HSIC1_SLEEP               (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND       (1 << 11)
-#define PHY1_HSIC0_SLEEP               (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND       (1 << 9)
-
-#define PHY1_STD_NORMAL_MASK           (0x7 << 6)
-#define PHY1_STD_SLEEP                 (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN      (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND         (1 << 6)
-
-#define PHY0_NORMAL_MASK               (0x39 << 0)
-#define PHY0_SLEEP                     (1 << 5)
-#define PHY0_OTG_DISABLE               (1 << 4)
-#define PHY0_ANALOG_POWERDOWN          (1 << 3)
-#define PHY0_FORCE_SUSPEND             (1 << 0)
-
-#define EXYNOS4_PHYCLK                 EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N               (1 << 7)
-#define PHY0_COMMON_ON_N               (1 << 4)
-#define PHY0_ID_PULLUP                 (1 << 2)
-#define CLKSEL_MASK                    (0x3 << 0)
-#define CLKSEL_SHIFT                   (0)
-#define CLKSEL_48M                     (0x0 << 0)
-#define CLKSEL_12M                     (0x2 << 0)
-#define CLKSEL_24M                     (0x3 << 0)
-
-#define EXYNOS4_RSTCON                 EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK      (0xf << 6)
-#define HOST_LINK_PORT2_SWRST          (1 << 9)
-#define HOST_LINK_PORT1_SWRST          (1 << 8)
-#define HOST_LINK_PORT0_SWRST          (1 << 7)
-#define HOST_LINK_ALL_SWRST            (1 << 6)
-
-#define PHY1_SWRST_MASK                        (0x7 << 3)
-#define PHY1_HSIC_SWRST                        (1 << 5)
-#define PHY1_STD_SWRST                 (1 << 4)
-#define PHY1_ALL_SWRST                 (1 << 3)
-
-#define PHY0_SWRST_MASK                        (0x7 << 0)
-#define PHY0_PHYLINK_SWRST             (1 << 2)
-#define PHY0_HLINK_SWRST               (1 << 1)
-#define PHY0_SWRST                     (1 << 0)
-
-#define EXYNOS4_PHY1CON                        EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN                      (1 << 0)
-
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos4/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h
deleted file mode 100644 (file)
index 6a5fbb5..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Samsung sysmmu driver for EXYNOS4
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-enum exynos4_sysmmu_ips {
-       SYSMMU_MDMA,
-       SYSMMU_SSS,
-       SYSMMU_FIMC0,
-       SYSMMU_FIMC1,
-       SYSMMU_FIMC2,
-       SYSMMU_FIMC3,
-       SYSMMU_JPEG,
-       SYSMMU_FIMD0,
-       SYSMMU_FIMD1,
-       SYSMMU_PCIe,
-       SYSMMU_G2D,
-       SYSMMU_ROTATOR,
-       SYSMMU_MDMA2,
-       SYSMMU_TV,
-       SYSMMU_MFC_L,
-       SYSMMU_MFC_R,
-       EXYNOS4_SYSMMU_TOTAL_IPNUM,
-};
-
-#define S5P_SYSMMU_TOTAL_IPNUM         EXYNOS4_SYSMMU_TOTAL_IPNUM
-
-extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
-
-typedef enum exynos4_sysmmu_ips sysmmu_ips;
-
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
-void sysmmu_clk_enable(sysmmu_ips ips);
-void sysmmu_clk_disable(sysmmu_ips ips);
-
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h
deleted file mode 100644 (file)
index 5e3220c..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/system.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-#include <plat/system-reset.h>
-
-static void arch_idle(void)
-{
-       /* nothing here yet */
-}
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos4/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h
deleted file mode 100644 (file)
index 6d13875..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/timex.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Copyright (c) 2003-2010 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * Based on arch/arm/mach-s5p6442/include/mach/timex.h
- *
- * EXYNOS4 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H __FILE__
-
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-
-#define CLOCK_TICK_RATE 12000000
-
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-exynos4/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h
deleted file mode 100644 (file)
index 21d97bc..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H __FILE__
-
-#include <mach/map.h>
-#include <plat/uncompress.h>
-
-static void arch_detect_cpu(void)
-{
-       /* we do not need to do any cpu detection here at the moment. */
-
-       /*
-        * For preventing FIFO overrun or infinite loop of UART console,
-        * fifo_max should be the minimum fifo size of all of the UART channels
-        */
-       fifo_mask = S5PV210_UFSTAT_TXMASK;
-       fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h
deleted file mode 100644 (file)
index 284330e..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * EXYNOS4 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-
-#define VMALLOC_END    0xF6000000UL
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos4/init.c b/arch/arm/mach-exynos4/init.c
deleted file mode 100644 (file)
index a8a83e3..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-exynos4/init.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/regs-serial.h>
-
-static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk1",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-};
-
-/* uart registration process */
-void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-       struct s3c2410_uartcfg *tcfg = cfg;
-       u32 ucnt;
-
-       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-               if (!tcfg->clocks) {
-                       tcfg->has_fracval = 1;
-                       tcfg->clocks = exynos4_serial_clocks;
-                       tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
-               }
-               tcfg->flags |= NO_NEED_CHECK_CLKSRC;
-       }
-
-       s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
deleted file mode 100644 (file)
index 5a2758a..0000000
+++ /dev/null
@@ -1,124 +0,0 @@
-/* linux/arch/arm/mach-exynos4/irq-combiner.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Based on arch/arm/common/gic.c
- *
- * IRQ COMBINER support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-
-#include <asm/mach/irq.h>
-
-#define COMBINER_ENABLE_SET    0x0
-#define COMBINER_ENABLE_CLEAR  0x4
-#define COMBINER_INT_STATUS    0xC
-
-static DEFINE_SPINLOCK(irq_controller_lock);
-
-struct combiner_chip_data {
-       unsigned int irq_offset;
-       unsigned int irq_mask;
-       void __iomem *base;
-};
-
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-       struct combiner_chip_data *combiner_data =
-               irq_data_get_irq_chip_data(data);
-
-       return combiner_data->base;
-}
-
-static void combiner_mask_irq(struct irq_data *data)
-{
-       u32 mask = 1 << (data->irq % 32);
-
-       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-
-static void combiner_unmask_irq(struct irq_data *data)
-{
-       u32 mask = 1 << (data->irq % 32);
-
-       __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-       struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-       struct irq_chip *chip = irq_get_chip(irq);
-       unsigned int cascade_irq, combiner_irq;
-       unsigned long status;
-
-       chained_irq_enter(chip, desc);
-
-       spin_lock(&irq_controller_lock);
-       status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
-       spin_unlock(&irq_controller_lock);
-       status &= chip_data->irq_mask;
-
-       if (status == 0)
-               goto out;
-
-       combiner_irq = __ffs(status);
-
-       cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-       if (unlikely(cascade_irq >= NR_IRQS))
-               do_bad_IRQ(cascade_irq, desc);
-       else
-               generic_handle_irq(cascade_irq);
-
- out:
-       chained_irq_exit(chip, desc);
-}
-
-static struct irq_chip combiner_chip = {
-       .name           = "COMBINER",
-       .irq_mask       = combiner_mask_irq,
-       .irq_unmask     = combiner_unmask_irq,
-};
-
-void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
-{
-       if (combiner_nr >= MAX_COMBINER_NR)
-               BUG();
-       if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
-               BUG();
-       irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-
-void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-                         unsigned int irq_start)
-{
-       unsigned int i;
-
-       if (combiner_nr >= MAX_COMBINER_NR)
-               BUG();
-
-       combiner_data[combiner_nr].base = base;
-       combiner_data[combiner_nr].irq_offset = irq_start;
-       combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-
-       /* Disable all interrupts */
-
-       __raw_writel(combiner_data[combiner_nr].irq_mask,
-                    base + COMBINER_ENABLE_CLEAR);
-
-       /* Setup the Linux IRQ subsystem */
-
-       for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-                               + MAX_IRQ_IN_COMBINER; i++) {
-               irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-               irq_set_chip_data(i, &combiner_data[combiner_nr]);
-               set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-       }
-}
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
deleted file mode 100644 (file)
index badb8c6..0000000
+++ /dev/null
@@ -1,237 +0,0 @@
-/* linux/arch/arm/mach-exynos4/irq-eint.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - IRQ EINT support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/gpio.h>
-
-#include <plat/pm.h>
-#include <plat/cpu.h>
-#include <plat/gpio-cfg.h>
-
-#include <mach/regs-gpio.h>
-
-#include <asm/mach/irq.h>
-
-static DEFINE_SPINLOCK(eint_lock);
-
-static unsigned int eint0_15_data[16];
-
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-       u32 ret = 0;
-
-       switch (number) {
-       case 0 ... 3:
-               ret = (number + IRQ_EINT0);
-               break;
-       case 4 ... 7:
-               ret = (number + (IRQ_EINT4 - 4));
-               break;
-       case 8 ... 15:
-               ret = (number + (IRQ_EINT8 - 8));
-               break;
-       default:
-               printk(KERN_ERR "number available : %d\n", number);
-       }
-
-       return ret;
-}
-
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
-{
-       u32 mask;
-
-       spin_lock(&eint_lock);
-       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       mask |= eint_irq_to_bit(data->irq);
-       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       spin_unlock(&eint_lock);
-}
-
-static void exynos4_irq_eint_unmask(struct irq_data *data)
-{
-       u32 mask;
-
-       spin_lock(&eint_lock);
-       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       mask &= ~(eint_irq_to_bit(data->irq));
-       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       spin_unlock(&eint_lock);
-}
-
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
-{
-       __raw_writel(eint_irq_to_bit(data->irq),
-                    S5P_EINT_PEND(EINT_REG_NR(data->irq)));
-}
-
-static void exynos4_irq_eint_maskack(struct irq_data *data)
-{
-       exynos4_irq_eint_mask(data);
-       exynos4_irq_eint_ack(data);
-}
-
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-       int offs = EINT_OFFSET(data->irq);
-       int shift;
-       u32 ctrl, mask;
-       u32 newvalue = 0;
-
-       switch (type) {
-       case IRQ_TYPE_EDGE_RISING:
-               newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-               break;
-
-       case IRQ_TYPE_EDGE_FALLING:
-               newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-               break;
-
-       case IRQ_TYPE_EDGE_BOTH:
-               newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-               break;
-
-       case IRQ_TYPE_LEVEL_LOW:
-               newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-               break;
-
-       case IRQ_TYPE_LEVEL_HIGH:
-               newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-               break;
-
-       default:
-               printk(KERN_ERR "No such irq type %d", type);
-               return -EINVAL;
-       }
-
-       shift = (offs & 0x7) * 4;
-       mask = 0x7 << shift;
-
-       spin_lock(&eint_lock);
-       ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
-       ctrl &= ~mask;
-       ctrl |= newvalue << shift;
-       __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
-       spin_unlock(&eint_lock);
-
-       switch (offs) {
-       case 0 ... 7:
-               s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-               break;
-       case 8 ... 15:
-               s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-               break;
-       case 16 ... 23:
-               s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-               break;
-       case 24 ... 31:
-               s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-               break;
-       default:
-               printk(KERN_ERR "No such irq number %d", offs);
-       }
-
-       return 0;
-}
-
-static struct irq_chip exynos4_irq_eint = {
-       .name           = "exynos4-eint",
-       .irq_mask       = exynos4_irq_eint_mask,
-       .irq_unmask     = exynos4_irq_eint_unmask,
-       .irq_mask_ack   = exynos4_irq_eint_maskack,
-       .irq_ack        = exynos4_irq_eint_ack,
-       .irq_set_type   = exynos4_irq_eint_set_type,
-#ifdef CONFIG_PM
-       .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-
-/* exynos4_irq_demux_eint
- *
- * This function demuxes the IRQ from from EINTs 16 to 31.
- * It is designed to be inlined into the specific handler
- * s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void exynos4_irq_demux_eint(unsigned int start)
-{
-       unsigned int irq;
-
-       u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-       u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
-
-       status &= ~mask;
-       status &= 0xff;
-
-       while (status) {
-               irq = fls(status) - 1;
-               generic_handle_irq(irq + start);
-               status &= ~(1 << irq);
-       }
-}
-
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-       struct irq_chip *chip = irq_get_chip(irq);
-       chained_irq_enter(chip, desc);
-       exynos4_irq_demux_eint(IRQ_EINT(16));
-       exynos4_irq_demux_eint(IRQ_EINT(24));
-       chained_irq_exit(chip, desc);
-}
-
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
-{
-       u32 *irq_data = irq_get_handler_data(irq);
-       struct irq_chip *chip = irq_get_chip(irq);
-
-       chained_irq_enter(chip, desc);
-       chip->irq_mask(&desc->irq_data);
-
-       if (chip->irq_ack)
-               chip->irq_ack(&desc->irq_data);
-
-       generic_handle_irq(*irq_data);
-
-       chip->irq_unmask(&desc->irq_data);
-       chained_irq_exit(chip, desc);
-}
-
-int __init exynos4_init_irq_eint(void)
-{
-       int irq;
-
-       for (irq = 0 ; irq <= 31 ; irq++) {
-               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
-                                        handle_level_irq);
-               set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
-       }
-
-       irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
-
-       for (irq = 0 ; irq <= 15 ; irq++) {
-               eint0_15_data[irq] = IRQ_EINT(irq);
-
-               irq_set_handler_data(exynos4_get_irq_nr(irq),
-                                    &eint0_15_data[irq]);
-               irq_set_chained_handler(exynos4_get_irq_nr(irq),
-                                       exynos4_irq_eint0_15);
-       }
-
-       return 0;
-}
-
-arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
deleted file mode 100644 (file)
index f0ca6c1..0000000
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/smsc911x.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/exynos4.h>
-#include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/sdhci.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ARMLEX4210_UCON_DEFAULT        (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define ARMLEX4210_ULCON_DEFAULT       S3C2410_LCON_CS8
-
-#define ARMLEX4210_UFCON_DEFAULT       (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG4 |        \
-                                S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .flags          = 0,
-               .ucon           = ARMLEX4210_UCON_DEFAULT,
-               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .flags          = 0,
-               .ucon           = ARMLEX4210_UCON_DEFAULT,
-               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .flags          = 0,
-               .ucon           = ARMLEX4210_UCON_DEFAULT,
-               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .flags          = 0,
-               .ucon           = ARMLEX4210_UCON_DEFAULT,
-               .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-               .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-       },
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_PERMANENT,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-       .max_width              = 8,
-       .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .ext_cd_gpio            = EXYNOS4_GPX2(5),
-       .ext_cd_gpio_invert     = 1,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-       .max_width              = 4,
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_PERMANENT,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-       .max_width              = 4,
-};
-
-static void __init armlex4210_sdhci_init(void)
-{
-       s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
-       s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
-       s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
-}
-
-static void __init armlex4210_wlan_init(void)
-{
-       /* enable */
-       s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
-
-       /* reset */
-       s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
-
-       /* wakeup */
-       s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
-}
-
-static struct resource armlex4210_smsc911x_resources[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_SROM_BANK(3),
-               .end    = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_EINT(27),
-               .end    = IRQ_EINT(27),
-               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-       },
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-       .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-       .phy_interface  = PHY_INTERFACE_MODE_MII,
-       .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device armlex4210_smsc911x = {
-       .name           = "smsc911x",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
-       .resource       = armlex4210_smsc911x_resources,
-       .dev            = {
-               .platform_data  = &smsc9215_config,
-       },
-};
-
-static struct platform_device *armlex4210_devices[] __initdata = {
-       &s3c_device_hsmmc0,
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc3,
-       &s3c_device_rtc,
-       &s3c_device_wdt,
-       &exynos4_device_sysmmu,
-       &samsung_asoc_dma,
-       &armlex4210_smsc911x,
-       &exynos4_device_ahci,
-};
-
-static void __init armlex4210_smsc911x_init(void)
-{
-       u32 cs1;
-
-       /* configure nCS1 width to 16 bits */
-       cs1 = __raw_readl(S5P_SROM_BW) &
-               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-               (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-               (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
-               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-               S5P_SROM_BW__NCS1__SHIFT;
-       __raw_writel(cs1, S5P_SROM_BW);
-
-       /* set timing for nCS1 suitable for ethernet chip */
-       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-static void __init armlex4210_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(armlex4210_uartcfgs,
-                          ARRAY_SIZE(armlex4210_uartcfgs));
-}
-
-static void __init armlex4210_machine_init(void)
-{
-       armlex4210_smsc911x_init();
-
-       armlex4210_sdhci_init();
-
-       armlex4210_wlan_init();
-
-       platform_add_devices(armlex4210_devices,
-                            ARRAY_SIZE(armlex4210_devices));
-}
-
-MACHINE_START(ARMLEX4210, "ARMLEX4210")
-       /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = armlex4210_map_io,
-       .init_machine   = armlex4210_machine_init,
-       .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
deleted file mode 100644 (file)
index 236bbe1..0000000
+++ /dev/null
@@ -1,1339 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-nuri.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/i2c-gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/power/max8903_charger.h>
-#include <linux/power/max17042_battery.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mfd/max8997-private.h>
-#include <linux/mmc/host.h>
-#include <linux/fb.h>
-#include <linux/pwm_backlight.h>
-
-#include <video/platform_lcd.h>
-#include <media/m5mols.h>
-#include <media/s5p_fimc.h>
-#include <media/v4l2-mediabus.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/adc.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/regs-serial.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/ehci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/iic.h>
-#include <plat/mfc.h>
-#include <plat/pd.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-#include <plat/mipi_csis.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define NURI_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define NURI_ULCON_DEFAULT     S3C2410_LCON_CS8
-
-#define NURI_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG256 |      \
-                                S5PV210_UFCON_RXTRIG256)
-
-enum fixed_regulator_id {
-       FIXED_REG_ID_MMC = 0,
-       FIXED_REG_ID_MAX8903,
-       FIXED_REG_ID_CAM_A28V,
-       FIXED_REG_ID_CAM_12V,
-};
-
-static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
-       {
-               .hwport         = 0,
-               .ucon           = NURI_UCON_DEFAULT,
-               .ulcon          = NURI_ULCON_DEFAULT,
-               .ufcon          = NURI_UFCON_DEFAULT,
-       },
-       {
-               .hwport         = 1,
-               .ucon           = NURI_UCON_DEFAULT,
-               .ulcon          = NURI_ULCON_DEFAULT,
-               .ufcon          = NURI_UFCON_DEFAULT,
-       },
-       {
-               .hwport         = 2,
-               .ucon           = NURI_UCON_DEFAULT,
-               .ulcon          = NURI_ULCON_DEFAULT,
-               .ufcon          = NURI_UFCON_DEFAULT,
-       },
-       {
-               .hwport         = 3,
-               .ucon           = NURI_UCON_DEFAULT,
-               .ulcon          = NURI_ULCON_DEFAULT,
-               .ufcon          = NURI_UFCON_DEFAULT,
-       },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
-       .max_width              = 8,
-       .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                               MMC_CAP_DISABLE | MMC_CAP_ERASE),
-       .cd_type                = S3C_SDHCI_CD_PERMANENT,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct regulator_consumer_supply emmc_supplies[] = {
-       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
-       REGULATOR_SUPPLY("vmmc", "dw_mmc"),
-};
-
-static struct regulator_init_data emmc_fixed_voltage_init_data = {
-       .constraints            = {
-               .name           = "VMEM_VDD_2.8V",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
-       .consumer_supplies      = emmc_supplies,
-};
-
-static struct fixed_voltage_config emmc_fixed_voltage_config = {
-       .supply_name            = "MASSMEMORY_EN (inverted)",
-       .microvolts             = 2800000,
-       .gpio                   = EXYNOS4_GPL1(1),
-       .enable_high            = false,
-       .init_data              = &emmc_fixed_voltage_init_data,
-};
-
-static struct platform_device emmc_fixed_voltage = {
-       .name                   = "reg-fixed-voltage",
-       .id                     = FIXED_REG_ID_MMC,
-       .dev                    = {
-               .platform_data  = &emmc_fixed_voltage_config,
-       },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
-       .max_width              = 4,
-       .host_caps              = MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                               MMC_CAP_DISABLE,
-       .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
-       .ext_cd_gpio_invert     = 1,
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-/* WLAN */
-static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
-       .max_width              = 4,
-       .host_caps              = MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-       .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static void __init nuri_sdhci_init(void)
-{
-       s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
-       s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
-       s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
-}
-
-/* GPIO KEYS */
-static struct gpio_keys_button nuri_gpio_keys_tables[] = {
-       {
-               .code                   = KEY_VOLUMEUP,
-               .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-               .desc                   = "gpio-keys: KEY_VOLUMEUP",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_VOLUMEDOWN,
-               .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-               .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_POWER,
-               .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
-               .desc                   = "gpio-keys: KEY_POWER",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       },
-};
-
-static struct gpio_keys_platform_data nuri_gpio_keys_data = {
-       .buttons                = nuri_gpio_keys_tables,
-       .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
-};
-
-static struct platform_device nuri_gpio_keys = {
-       .name                   = "gpio-keys",
-       .dev                    = {
-               .platform_data  = &nuri_gpio_keys_data,
-       },
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win nuri_fb_win0 = {
-       .win_mode = {
-               .left_margin    = 64,
-               .right_margin   = 16,
-               .upper_margin   = 64,
-               .lower_margin   = 1,
-               .hsync_len      = 48,
-               .vsync_len      = 3,
-               .xres           = 1280,
-               .yres           = 800,
-               .refresh        = 60,
-       },
-       .max_bpp        = 24,
-       .default_bpp    = 16,
-       .virtual_x      = 1280,
-       .virtual_y      = 800,
-};
-
-static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
-       .win[0]         = &nuri_fb_win0,
-       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                         VIDCON0_CLKSEL_LCD,
-       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
-{
-       int gpio = EXYNOS4_GPE1(5);
-
-       gpio_request(gpio, "LVDS_nSHDN");
-       gpio_direction_output(gpio, power);
-       gpio_free(gpio);
-}
-
-static int nuri_bl_init(struct device *dev)
-{
-       int ret, gpio = EXYNOS4_GPE2(3);
-
-       ret = gpio_request(gpio, "LCD_LDO_EN");
-       if (!ret)
-               gpio_direction_output(gpio, 0);
-
-       return ret;
-}
-
-static int nuri_bl_notify(struct device *dev, int brightness)
-{
-       if (brightness < 1)
-               brightness = 0;
-
-       gpio_set_value(EXYNOS4_GPE2(3), 1);
-
-       return brightness;
-}
-
-static void nuri_bl_exit(struct device *dev)
-{
-       gpio_free(EXYNOS4_GPE2(3));
-}
-
-/* nuri pwm backlight */
-static struct platform_pwm_backlight_data nuri_backlight_data = {
-       .pwm_id                 = 0,
-       .pwm_period_ns          = 30000,
-       .max_brightness         = 100,
-       .dft_brightness         = 50,
-       .init                   = nuri_bl_init,
-       .notify                 = nuri_bl_notify,
-       .exit                   = nuri_bl_exit,
-};
-
-static struct platform_device nuri_backlight_device = {
-       .name                   = "pwm-backlight",
-       .id                     = -1,
-       .dev                    = {
-               .parent         = &s3c_device_timer[0].dev,
-               .platform_data  = &nuri_backlight_data,
-       },
-};
-
-static struct plat_lcd_data nuri_lcd_platform_data = {
-       .set_power              = nuri_lcd_power_on,
-};
-
-static struct platform_device nuri_lcd_device = {
-       .name                   = "platform-lcd",
-       .id                     = -1,
-       .dev                    = {
-               .platform_data  = &nuri_lcd_platform_data,
-       },
-};
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-       /* Gyro, To be updated */
-};
-
-/* TSP */
-static u8 mxt_init_vals[] = {
-       /* MXT_GEN_COMMAND(6) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       /* MXT_GEN_POWER(7) */
-       0x20, 0xff, 0x32,
-       /* MXT_GEN_ACQUIRE(8) */
-       0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
-       /* MXT_TOUCH_MULTI(9) */
-       0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
-       0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00,
-       /* MXT_TOUCH_KEYARRAY(15) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
-       0x00,
-       /* MXT_SPT_GPIOPWM(19) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       /* MXT_PROCI_GRIPFACE(20) */
-       0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
-       0x0f, 0x0a,
-       /* MXT_PROCG_NOISE(22) */
-       0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
-       0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
-       /* MXT_TOUCH_PROXIMITY(23) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00,
-       /* MXT_PROCI_ONETOUCH(24) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       /* MXT_SPT_SELFTEST(25) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00,
-       /* MXT_PROCI_TWOTOUCH(27) */
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       /* MXT_SPT_CTECONFIG(28) */
-       0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
-};
-
-static struct mxt_platform_data mxt_platform_data = {
-       .config                 = mxt_init_vals,
-       .config_length          = ARRAY_SIZE(mxt_init_vals),
-
-       .x_line                 = 18,
-       .y_line                 = 11,
-       .x_size                 = 1024,
-       .y_size                 = 600,
-       .blen                   = 0x1,
-       .threshold              = 0x28,
-       .voltage                = 2800000,              /* 2.8V */
-       .orient                 = MXT_DIAGONAL_COUNTER,
-       .irqflags               = IRQF_TRIGGER_FALLING,
-};
-
-static struct s3c2410_platform_i2c i2c3_data __initdata = {
-       .flags          = 0,
-       .bus_num        = 3,
-       .slave_addr     = 0x10,
-       .frequency      = 400 * 1000,
-       .sda_delay      = 100,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-       {
-               I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
-               .platform_data  = &mxt_platform_data,
-               .irq            = IRQ_EINT(4),
-       },
-};
-
-static void __init nuri_tsp_init(void)
-{
-       int gpio;
-
-       /* TOUCH_INT: XEINT_4 */
-       gpio = EXYNOS4_GPX0(4);
-       gpio_request(gpio, "TOUCH_INT");
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-}
-
-static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
-       REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
-       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
-       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
-       REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
-       REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
-       REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
-       REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
-       REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
-       REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
-       REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
-};
-static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
-       REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
-       REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
-       REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
-       REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-       REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
-       REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
-       REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
-       REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
-       REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
-       REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
-};
-
-static struct regulator_consumer_supply __initdata max8997_charger_[] = {
-       REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
-};
-static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
-       REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
-};
-
-static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
-       REGULATOR_SUPPLY("gps_clk", "bcm4751"),
-       REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
-       REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-       .constraints    = {
-               .name           = "VADC_3.3V_C210",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
-       .consumer_supplies      = max8997_ldo1_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data = {
-       .constraints    = {
-               .name           = "VALIVE_1.1V_C210",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-       .constraints    = {
-               .name           = "VUSB_1.1V_C210",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
-       .consumer_supplies      = max8997_ldo3_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-       .constraints    = {
-               .name           = "VMIPI_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
-       .consumer_supplies      = max8997_ldo4_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo5_data = {
-       .constraints    = {
-               .name           = "VHSIC_1.2V_C210",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
-       .consumer_supplies      = max8997_ldo5_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-       .constraints    = {
-               .name           = "VCC_1.8V_PDA",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-       .constraints    = {
-               .name           = "CAM_ISP_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
-       .consumer_supplies      = max8997_ldo7_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-       .constraints    = {
-               .name           = "VUSB/VDAC_3.3V_C210",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
-       .consumer_supplies      = max8997_ldo8_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-       .constraints    = {
-               .name           = "VCC_2.8V_PDA",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-       .constraints    = {
-               .name           = "VPLL_1.1V_C210",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-       .constraints    = {
-               .name           = "LVDS_VDD3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .boot_on        = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
-       .consumer_supplies      = max8997_ldo11_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo12_data = {
-       .constraints    = {
-               .name           = "VT_CAM_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
-       .consumer_supplies      = max8997_ldo12_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo13_data = {
-       .constraints    = {
-               .name           = "VTF_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
-       .consumer_supplies      = max8997_ldo13_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-       .constraints    = {
-               .name           = "VCC_3.0V_MOTOR",
-               .min_uV         = 3000000,
-               .max_uV         = 3000000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
-       .consumer_supplies      = max8997_ldo14_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo15_data = {
-       .constraints    = {
-               .name           = "VTOUCH_ADVV2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
-       .consumer_supplies      = max8997_ldo15_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo16_data = {
-       .constraints    = {
-               .name           = "CAM_SENSOR_IO_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
-       .consumer_supplies      = max8997_ldo16_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo18_data = {
-       .constraints    = {
-               .name           = "VTOUCH_VDD2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
-       .consumer_supplies      = max8997_ldo18_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-       .constraints    = {
-               .name           = "VDDQ_M1M2_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-       .constraints    = {
-               .name           = "VARM_1.2V_C210",
-               .min_uV         = 900000,
-               .max_uV         = 1350000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
-       .consumer_supplies = max8997_buck1_,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-       .constraints    = {
-               .name           = "VINT_1.1V_C210",
-               .min_uV         = 900000,
-               .max_uV         = 1100000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
-       .consumer_supplies = max8997_buck2_,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-       .constraints    = {
-               .name           = "VG3D_1.1V_C210",
-               .min_uV         = 900000,
-               .max_uV         = 1100000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                 REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
-       .consumer_supplies = max8997_buck3_,
-};
-
-static struct regulator_init_data __initdata max8997_buck4_data = {
-       .constraints    = {
-               .name           = "CAM_ISP_CORE_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
-       .consumer_supplies = max8997_buck4_,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-       .constraints    = {
-               .name           = "VMEM_1.2V_C210",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_buck6_data = {
-       .constraints    = {
-               .name           = "CAM_AF_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
-       .consumer_supplies = max8997_buck6_,
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-       .constraints    = {
-               .name           = "VCC_SUB_2.0V",
-               .min_uV         = 2000000,
-               .max_uV         = 2000000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_32khz_ap_data = {
-       .constraints    = {
-               .name           = "32KHz AP",
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
-       .consumer_supplies = max8997_32khz_ap_,
-};
-
-static struct regulator_init_data __initdata max8997_32khz_cp_data = {
-       .constraints    = {
-               .name           = "32KHz CP",
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_vichg_data = {
-       .constraints    = {
-               .name           = "VICHG",
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_esafeout1_data = {
-       .constraints    = {
-               .name           = "SAFEOUT1",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
-       .consumer_supplies      = max8997_esafeout1_,
-};
-
-static struct regulator_init_data __initdata max8997_esafeout2_data = {
-       .constraints    = {
-               .name           = "SAFEOUT2",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
-       .consumer_supplies      = max8997_esafeout2_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_cv_data = {
-       .constraints    = {
-               .name           = "CHARGER_CV",
-               .min_uV         = 4200000,
-               .max_uV         = 4200000,
-               .apply_uV       = 1,
-       },
-};
-
-static struct regulator_init_data __initdata max8997_charger_data = {
-       .constraints    = {
-               .name           = "CHARGER",
-               .min_uA         = 200000,
-               .max_uA         = 950000,
-               .boot_on        = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS |
-                               REGULATOR_CHANGE_CURRENT,
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
-       .consumer_supplies      = max8997_charger_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_topoff_data = {
-       .constraints    = {
-               .name           = "CHARGER TOPOFF",
-               .min_uA         = 50000,
-               .max_uA         = 200000,
-               .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
-       .consumer_supplies      = max8997_chg_toff_,
-};
-
-static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
-       { MAX8997_LDO1, &max8997_ldo1_data },
-       { MAX8997_LDO2, &max8997_ldo2_data },
-       { MAX8997_LDO3, &max8997_ldo3_data },
-       { MAX8997_LDO4, &max8997_ldo4_data },
-       { MAX8997_LDO5, &max8997_ldo5_data },
-       { MAX8997_LDO6, &max8997_ldo6_data },
-       { MAX8997_LDO7, &max8997_ldo7_data },
-       { MAX8997_LDO8, &max8997_ldo8_data },
-       { MAX8997_LDO9, &max8997_ldo9_data },
-       { MAX8997_LDO10, &max8997_ldo10_data },
-       { MAX8997_LDO11, &max8997_ldo11_data },
-       { MAX8997_LDO12, &max8997_ldo12_data },
-       { MAX8997_LDO13, &max8997_ldo13_data },
-       { MAX8997_LDO14, &max8997_ldo14_data },
-       { MAX8997_LDO15, &max8997_ldo15_data },
-       { MAX8997_LDO16, &max8997_ldo16_data },
-
-       { MAX8997_LDO18, &max8997_ldo18_data },
-       { MAX8997_LDO21, &max8997_ldo21_data },
-
-       { MAX8997_BUCK1, &max8997_buck1_data },
-       { MAX8997_BUCK2, &max8997_buck2_data },
-       { MAX8997_BUCK3, &max8997_buck3_data },
-       { MAX8997_BUCK4, &max8997_buck4_data },
-       { MAX8997_BUCK5, &max8997_buck5_data },
-       { MAX8997_BUCK6, &max8997_buck6_data },
-       { MAX8997_BUCK7, &max8997_buck7_data },
-
-       { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
-       { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
-
-       { MAX8997_ENVICHG, &max8997_vichg_data },
-       { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
-       { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
-       { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
-       { MAX8997_CHARGER, &max8997_charger_data },
-       { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
-};
-
-static struct max8997_platform_data __initdata nuri_max8997_pdata = {
-       .wakeup                 = 1,
-
-       .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
-       .regulators             = nuri_max8997_regulators,
-
-       .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-       .buck2_gpiodvs = true,
-
-       .buck1_voltage[0] = 1350000, /* 1.35V */
-       .buck1_voltage[1] = 1300000, /* 1.3V */
-       .buck1_voltage[2] = 1250000, /* 1.25V */
-       .buck1_voltage[3] = 1200000, /* 1.2V */
-       .buck1_voltage[4] = 1150000, /* 1.15V */
-       .buck1_voltage[5] = 1100000, /* 1.1V */
-       .buck1_voltage[6] = 1000000, /* 1.0V */
-       .buck1_voltage[7] = 950000, /* 0.95V */
-
-       .buck2_voltage[0] = 1100000, /* 1.1V */
-       .buck2_voltage[1] = 1000000, /* 1.0V */
-       .buck2_voltage[2] = 950000, /* 0.95V */
-       .buck2_voltage[3] = 900000, /* 0.9V */
-       .buck2_voltage[4] = 1100000, /* 1.1V */
-       .buck2_voltage[5] = 1000000, /* 1.0V */
-       .buck2_voltage[6] = 950000, /* 0.95V */
-       .buck2_voltage[7] = 900000, /* 0.9V */
-
-       .buck5_voltage[0] = 1200000, /* 1.2V */
-       .buck5_voltage[1] = 1200000, /* 1.2V */
-       .buck5_voltage[2] = 1200000, /* 1.2V */
-       .buck5_voltage[3] = 1200000, /* 1.2V */
-       .buck5_voltage[4] = 1200000, /* 1.2V */
-       .buck5_voltage[5] = 1200000, /* 1.2V */
-       .buck5_voltage[6] = 1200000, /* 1.2V */
-       .buck5_voltage[7] = 1200000, /* 1.2V */
-};
-
-/* GPIO I2C 5 (PMIC) */
-enum { I2C5_MAX8997 };
-static struct i2c_board_info i2c5_devs[] __initdata = {
-       [I2C5_MAX8997] = {
-               I2C_BOARD_INFO("max8997", 0xCC >> 1),
-               .platform_data  = &nuri_max8997_pdata,
-       },
-};
-
-static struct max17042_platform_data nuri_battery_platform_data = {
-};
-
-/* GPIO I2C 9 (Fuel Gauge) */
-static struct i2c_gpio_platform_data i2c9_gpio_data = {
-       .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
-       .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
-};
-static struct platform_device i2c9_gpio = {
-       .name                   = "i2c-gpio",
-       .id                     = 9,
-       .dev                    = {
-               .platform_data  = &i2c9_gpio_data,
-       },
-};
-enum { I2C9_MAX17042};
-static struct i2c_board_info i2c9_devs[] __initdata = {
-       [I2C9_MAX17042] = {
-               I2C_BOARD_INFO("max17042", 0x36),
-               .platform_data = &nuri_battery_platform_data,
-       },
-};
-
-/* MAX8903 Secondary Charger */
-static struct regulator_consumer_supply supplies_max8903[] = {
-       REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
-};
-
-static struct regulator_init_data max8903_charger_en_data = {
-       .constraints = {
-               .name           = "VOUT_CHARGER",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
-       .consumer_supplies = supplies_max8903,
-};
-
-static struct fixed_voltage_config max8903_charger_en = {
-       .supply_name = "VOUT_CHARGER",
-       .microvolts = 5000000, /* Assume 5VDC */
-       .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
-       .enable_high = 0, /* Enable = Low */
-       .enabled_at_boot = 1,
-       .init_data = &max8903_charger_en_data,
-};
-
-static struct platform_device max8903_fixed_reg_dev = {
-       .name = "reg-fixed-voltage",
-       .id = FIXED_REG_ID_MAX8903,
-       .dev = { .platform_data = &max8903_charger_en },
-};
-
-static struct max8903_pdata nuri_max8903 = {
-       /*
-        * cen: don't control with the driver, let it be
-        * controlled by regulator above
-        */
-       .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
-       /* uok, usus: not connected */
-       .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
-       /* flt: vcc_1.8V_pda */
-       .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
-
-       .dc_valid = true,
-       .usb_valid = false, /* USB is not wired to MAX8903 */
-};
-
-static struct platform_device nuri_max8903_device = {
-       .name                   = "max8903-charger",
-       .dev                    = {
-               .platform_data  = &nuri_max8903,
-       },
-};
-
-static void __init nuri_power_init(void)
-{
-       int gpio;
-       int irq_base = IRQ_GPIO_END + 1;
-       int ta_en = 0;
-
-       nuri_max8997_pdata.irq_base = irq_base;
-       irq_base += MAX8997_IRQ_NR;
-
-       gpio = EXYNOS4_GPX0(7);
-       gpio_request(gpio, "AP_PMIC_IRQ");
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-       gpio = EXYNOS4_GPX2(3);
-       gpio_request(gpio, "FUEL_ALERT");
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-       gpio = nuri_max8903.dok;
-       gpio_request(gpio, "TA_nCONNECTED");
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-       ta_en = gpio_get_value(gpio) ? 0 : 1;
-
-       gpio = nuri_max8903.chg;
-       gpio_request(gpio, "TA_nCHG");
-       gpio_direction_input(gpio);
-
-       gpio = nuri_max8903.dcm;
-       gpio_request(gpio, "CURR_ADJ");
-       gpio_direction_output(gpio, ta_en);
-}
-
-/* USB EHCI */
-static struct s5p_ehci_platdata nuri_ehci_pdata;
-
-static void __init nuri_ehci_init(void)
-{
-       struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
-
-       s5p_ehci_set_platdata(pdata);
-}
-
-/* CAMERA */
-static struct regulator_consumer_supply cam_vdda_supply[] = {
-       REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data cam_vdda_reg_init_data = {
-       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-       .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
-       .consumer_supplies = cam_vdda_supply,
-};
-
-static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
-       .supply_name    = "CAM_IO_EN",
-       .microvolts     = 2800000,
-       .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
-       .enable_high    = 1,
-       .init_data      = &cam_vdda_reg_init_data,
-};
-
-static struct platform_device cam_vdda_fixed_rdev = {
-       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
-       .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply camera_8m_12v_supply =
-       REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data cam_8m_12v_reg_init_data = {
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &camera_8m_12v_supply,
-       .constraints = {
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS
-       },
-};
-
-static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
-       .supply_name    = "8M_1.2V",
-       .microvolts     = 1200000,
-       .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
-       .enable_high    = 1,
-       .init_data      = &cam_8m_12v_reg_init_data,
-};
-
-static struct platform_device cam_8m_12v_fixed_rdev = {
-       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
-       .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-       .clk_rate       = 166000000UL,
-       .lanes          = 2,
-       .alignment      = 32,
-       .hs_settle      = 12,
-       .phy_enable     = s5p_csis_phy_enable,
-};
-
-#define GPIO_CAM_MEGA_RST      EXYNOS4_GPY3(7) /* ISP_RESET */
-#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPL2(5)
-
-static struct m5mols_platform_data m5mols_platdata = {
-       .gpio_reset = GPIO_CAM_MEGA_RST,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-       I2C_BOARD_INFO("M5MOLS", 0x1F),
-       .platform_data  = &m5mols_platdata,
-};
-
-static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
-       {
-               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
-               .bus_type       = FIMC_MIPI_CSI2,
-               .board_info     = &m5mols_board_info,
-               .clk_frequency  = 24000000UL,
-               .csi_data_align = 32,
-       },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-       .isp_info       = nuri_camera_sensors,
-       .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
-};
-
-static struct gpio nuri_camera_gpios[] = {
-       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
-       { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
-};
-
-static void nuri_camera_init(void)
-{
-       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                        &s5p_device_mipi_csis0);
-       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                        &s5p_device_fimc_md);
-
-       if (gpio_request_array(nuri_camera_gpios,
-                              ARRAY_SIZE(nuri_camera_gpios))) {
-               pr_err("%s: GPIO request failed\n", __func__);
-               return;
-       }
-
-       m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
-       if (!IS_ERR_VALUE(m5mols_board_info.irq))
-               s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
-       else
-               pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
-
-       /* Free GPIOs controlled directly by the sensor drivers. */
-       gpio_free(GPIO_CAM_MEGA_RST);
-
-       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
-               pr_err("%s: Camera port A setup failed\n", __func__);
-               return;
-       }
-       /* Increase drive strength of the sensor clock output */
-       s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
-}
-
-static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
-       .frequency      = 400000U,
-       .sda_delay      = 200,
-};
-
-static struct platform_device *nuri_devices[] __initdata = {
-       /* Samsung Platform Devices */
-       &s3c_device_i2c5, /* PMIC should initialize first */
-       &s3c_device_i2c0,
-       &emmc_fixed_voltage,
-       &s5p_device_mipi_csis0,
-       &s5p_device_fimc0,
-       &s5p_device_fimc1,
-       &s5p_device_fimc2,
-       &s5p_device_fimc3,
-       &s5p_device_fimd0,
-       &s3c_device_hsmmc0,
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc3,
-       &s3c_device_wdt,
-       &s3c_device_timer[0],
-       &s5p_device_ehci,
-       &s3c_device_i2c3,
-       &i2c9_gpio,
-       &s3c_device_adc,
-       &s3c_device_rtc,
-       &s5p_device_mfc,
-       &s5p_device_mfc_l,
-       &s5p_device_mfc_r,
-       &exynos4_device_pd[PD_MFC],
-       &exynos4_device_pd[PD_LCD0],
-       &exynos4_device_pd[PD_CAM],
-       &s5p_device_fimc_md,
-
-       /* NURI Devices */
-       &nuri_gpio_keys,
-       &nuri_lcd_device,
-       &nuri_backlight_device,
-       &max8903_fixed_reg_dev,
-       &nuri_max8903_device,
-       &cam_vdda_fixed_rdev,
-       &cam_8m_12v_fixed_rdev,
-};
-
-static void __init nuri_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
-}
-
-static void __init nuri_reserve(void)
-{
-       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init nuri_machine_init(void)
-{
-       nuri_sdhci_init();
-       nuri_tsp_init();
-       nuri_power_init();
-
-       s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
-       i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-       s3c_i2c3_set_platdata(&i2c3_data);
-       i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-       s3c_i2c5_set_platdata(NULL);
-       i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
-       i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-       i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
-       i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
-
-       s5p_fimd0_set_platdata(&nuri_fb_pdata);
-
-       nuri_camera_init();
-
-       nuri_ehci_init();
-       clk_xusbxti.rate = 24000000;
-
-       /* Last */
-       platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
-       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
-       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
-       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-}
-
-MACHINE_START(NURI, "NURI")
-       /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = nuri_map_io,
-       .init_machine   = nuri_machine_init,
-       .timer          = &exynos4_timer,
-       .reserve        = &nuri_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
deleted file mode 100644 (file)
index f80b563..0000000
+++ /dev/null
@@ -1,700 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-origen.c
- *
- * Copyright (c) 2011 Insignal Co., Ltd.
- *             http://www.insignal.co.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/max8997.h>
-#include <linux/lcd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-
-#include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/ehci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/pd.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ORIGEN_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define ORIGEN_ULCON_DEFAULT   S3C2410_LCON_CS8
-
-#define ORIGEN_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG4 |        \
-                                S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-};
-
-static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
-       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
-       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
-       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
-};
-static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
-       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
-       REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
-       REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
-       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
-};
-static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
-       REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
-       REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
-       REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
-       REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata buck1_consumer[] = {
-       REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck2_consumer[] = {
-       REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck3_consumer[] = {
-       REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
-};
-static struct regulator_consumer_supply __initdata buck7_consumer[] = {
-       REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-       .constraints    = {
-               .name           = "VDD_ABB_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data = {
-       .constraints    = {
-               .name           = "VDD_ALIVE_1.1V",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-       .constraints    = {
-               .name           = "VMIPI_1.1V",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
-       .consumer_supplies      = ldo3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-       .constraints    = {
-               .name           = "VDD_RTC_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-       .constraints    = {
-               .name           = "VMIPI_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
-       .consumer_supplies      = ldo6_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-       .constraints    = {
-               .name           = "VDD_AUD_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
-       .consumer_supplies      = ldo7_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-       .constraints    = {
-               .name           = "VADC_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
-       .consumer_supplies      = ldo8_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-       .constraints    = {
-               .name           = "DVDD_SWB_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
-       .consumer_supplies      = ldo9_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-       .constraints    = {
-               .name           = "VDD_PLL_1.1V",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-       .constraints    = {
-               .name           = "VDD_AUD_3V",
-               .min_uV         = 3000000,
-               .max_uV         = 3000000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
-       .consumer_supplies      = ldo11_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-       .constraints    = {
-               .name           = "AVDD18_SWB_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
-       .consumer_supplies      = ldo14_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo17_data = {
-       .constraints    = {
-               .name           = "VDD_SWB_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
-       .consumer_supplies      = ldo17_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-       .constraints    = {
-               .name           = "VDD_MIF_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-       .constraints    = {
-               .name           = "VDD_ARM_1.2V",
-               .min_uV         = 950000,
-               .max_uV         = 1350000,
-               .always_on      = 1,
-               .boot_on        = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-       .consumer_supplies      = buck1_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-       .constraints    = {
-               .name           = "VDD_INT_1.1V",
-               .min_uV         = 900000,
-               .max_uV         = 1100000,
-               .always_on      = 1,
-               .boot_on        = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-       .consumer_supplies      = buck2_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-       .constraints    = {
-               .name           = "VDD_G3D_1.1V",
-               .min_uV         = 900000,
-               .max_uV         = 1100000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                       REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
-       .consumer_supplies      = buck3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-       .constraints    = {
-               .name           = "VDDQ_M1M2_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-       .constraints    = {
-               .name           = "VDD_LCD_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .boot_on        = 1,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
-       .consumer_supplies      = buck7_consumer,
-};
-
-static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
-       { MAX8997_LDO1,         &max8997_ldo1_data },
-       { MAX8997_LDO2,         &max8997_ldo2_data },
-       { MAX8997_LDO3,         &max8997_ldo3_data },
-       { MAX8997_LDO4,         &max8997_ldo4_data },
-       { MAX8997_LDO6,         &max8997_ldo6_data },
-       { MAX8997_LDO7,         &max8997_ldo7_data },
-       { MAX8997_LDO8,         &max8997_ldo8_data },
-       { MAX8997_LDO9,         &max8997_ldo9_data },
-       { MAX8997_LDO10,        &max8997_ldo10_data },
-       { MAX8997_LDO11,        &max8997_ldo11_data },
-       { MAX8997_LDO14,        &max8997_ldo14_data },
-       { MAX8997_LDO17,        &max8997_ldo17_data },
-       { MAX8997_LDO21,        &max8997_ldo21_data },
-       { MAX8997_BUCK1,        &max8997_buck1_data },
-       { MAX8997_BUCK2,        &max8997_buck2_data },
-       { MAX8997_BUCK3,        &max8997_buck3_data },
-       { MAX8997_BUCK5,        &max8997_buck5_data },
-       { MAX8997_BUCK7,        &max8997_buck7_data },
-};
-
-struct max8997_platform_data __initdata origen_max8997_pdata = {
-       .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
-       .regulators     = origen_max8997_regulators,
-
-       .wakeup = true,
-       .buck1_gpiodvs  = false,
-       .buck2_gpiodvs  = false,
-       .buck5_gpiodvs  = false,
-       .irq_base       = IRQ_GPIO_END + 1,
-
-       .ignore_gpiodvs_side_effect = true,
-       .buck125_default_idx = 0x0,
-
-       .buck125_gpios[0]       = EXYNOS4_GPX0(0),
-       .buck125_gpios[1]       = EXYNOS4_GPX0(1),
-       .buck125_gpios[2]       = EXYNOS4_GPX0(2),
-
-       .buck1_voltage[0]       = 1350000,
-       .buck1_voltage[1]       = 1300000,
-       .buck1_voltage[2]       = 1250000,
-       .buck1_voltage[3]       = 1200000,
-       .buck1_voltage[4]       = 1150000,
-       .buck1_voltage[5]       = 1100000,
-       .buck1_voltage[6]       = 1000000,
-       .buck1_voltage[7]       = 950000,
-
-       .buck2_voltage[0]       = 1100000,
-       .buck2_voltage[1]       = 1100000,
-       .buck2_voltage[2]       = 1100000,
-       .buck2_voltage[3]       = 1100000,
-       .buck2_voltage[4]       = 1000000,
-       .buck2_voltage[5]       = 1000000,
-       .buck2_voltage[6]       = 1000000,
-       .buck2_voltage[7]       = 1000000,
-
-       .buck5_voltage[0]       = 1200000,
-       .buck5_voltage[1]       = 1200000,
-       .buck5_voltage[2]       = 1200000,
-       .buck5_voltage[3]       = 1200000,
-       .buck5_voltage[4]       = 1200000,
-       .buck5_voltage[5]       = 1200000,
-       .buck5_voltage[6]       = 1200000,
-       .buck5_voltage[7]       = 1200000,
-};
-
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-       {
-               I2C_BOARD_INFO("max8997", (0xCC >> 1)),
-               .platform_data  = &origen_max8997_pdata,
-               .irq            = IRQ_EINT(4),
-       },
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata origen_ehci_pdata;
-
-static void __init origen_ehci_init(void)
-{
-       struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
-
-       s5p_ehci_set_platdata(pdata);
-}
-
-static struct gpio_keys_button origen_gpio_keys_table[] = {
-       {
-               .code                   = KEY_MENU,
-               .gpio                   = EXYNOS4_GPX1(5),
-               .desc                   = "gpio-keys: KEY_MENU",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_HOME,
-               .gpio                   = EXYNOS4_GPX1(6),
-               .desc                   = "gpio-keys: KEY_HOME",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_BACK,
-               .gpio                   = EXYNOS4_GPX1(7),
-               .desc                   = "gpio-keys: KEY_BACK",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_UP,
-               .gpio                   = EXYNOS4_GPX2(0),
-               .desc                   = "gpio-keys: KEY_UP",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_DOWN,
-               .gpio                   = EXYNOS4_GPX2(1),
-               .desc                   = "gpio-keys: KEY_DOWN",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .wakeup                 = 1,
-               .debounce_interval      = 1,
-       },
-};
-
-static struct gpio_keys_platform_data origen_gpio_keys_data = {
-       .buttons        = origen_gpio_keys_table,
-       .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
-};
-
-static struct platform_device origen_device_gpiokeys = {
-       .name           = "gpio-keys",
-       .dev            = {
-               .platform_data  = &origen_gpio_keys_data,
-       },
-};
-
-static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
-       int ret;
-
-       if (power)
-               ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                       GPIOF_OUT_INIT_HIGH, "GPE3_4");
-       else
-               ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                       GPIOF_OUT_INIT_LOW, "GPE3_4");
-
-       gpio_free(EXYNOS4_GPE3(4));
-
-       if (ret)
-               pr_err("failed to request gpio for LCD power: %d\n", ret);
-}
-
-static struct plat_lcd_data origen_lcd_hv070wsa_data = {
-       .set_power = lcd_hv070wsa_set_power,
-};
-
-static struct platform_device origen_lcd_hv070wsa = {
-       .name                   = "platform-lcd",
-       .dev.parent             = &s5p_device_fimd0.dev,
-       .dev.platform_data      = &origen_lcd_hv070wsa_data,
-};
-
-static struct s3c_fb_pd_win origen_fb_win0 = {
-       .win_mode = {
-               .left_margin    = 64,
-               .right_margin   = 16,
-               .upper_margin   = 64,
-               .lower_margin   = 16,
-               .hsync_len      = 48,
-               .vsync_len      = 3,
-               .xres           = 1024,
-               .yres           = 600,
-       },
-       .max_bpp                = 32,
-       .default_bpp            = 24,
-};
-
-static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
-       .win[0]         = &origen_fb_win0,
-       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static struct platform_device *origen_devices[] __initdata = {
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc0,
-       &s3c_device_i2c0,
-       &s3c_device_rtc,
-       &s3c_device_wdt,
-       &s5p_device_ehci,
-       &s5p_device_fimc0,
-       &s5p_device_fimc1,
-       &s5p_device_fimc2,
-       &s5p_device_fimc3,
-       &s5p_device_fimd0,
-       &s5p_device_hdmi,
-       &s5p_device_i2c_hdmiphy,
-       &s5p_device_mfc,
-       &s5p_device_mfc_l,
-       &s5p_device_mfc_r,
-       &s5p_device_mixer,
-       &exynos4_device_pd[PD_LCD0],
-       &exynos4_device_pd[PD_TV],
-       &exynos4_device_pd[PD_G3D],
-       &exynos4_device_pd[PD_LCD1],
-       &exynos4_device_pd[PD_CAM],
-       &exynos4_device_pd[PD_GPS],
-       &exynos4_device_pd[PD_MFC],
-       &origen_device_gpiokeys,
-       &origen_lcd_hv070wsa,
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info origen_bl_gpio_info = {
-       .no             = EXYNOS4_GPD0(0),
-       .func           = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data origen_bl_data = {
-       .pwm_id         = 0,
-       .pwm_period_ns  = 1000,
-};
-
-static void s5p_tv_setup(void)
-{
-       /* Direct HPD to HDMI chip */
-       gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
-}
-
-static void __init origen_power_init(void)
-{
-       gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
-       s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_reserve(void)
-{
-       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init origen_machine_init(void)
-{
-       origen_power_init();
-
-       s3c_i2c0_set_platdata(NULL);
-       i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
-
-       /*
-        * Since sdhci instance 2 can contain a bootable media,
-        * sdhci instance 0 is registered after instance 2.
-        */
-       s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
-       s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
-
-       origen_ehci_init();
-       clk_xusbxti.rate = 24000000;
-
-       s5p_tv_setup();
-       s5p_i2c_hdmiphy_set_platdata(NULL);
-
-       s5p_fimd0_set_platdata(&origen_lcd_pdata);
-
-       platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
-
-       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
-       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
-       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
-
-       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
-
-       samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
-}
-
-MACHINE_START(ORIGEN, "ORIGEN")
-       /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = origen_map_io,
-       .init_machine   = origen_machine_init,
-       .timer          = &exynos4_timer,
-       .reserve        = &origen_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos4/mach-smdk4x12.c
deleted file mode 100644 (file)
index fcf2e0e..0000000
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/machine.h>
-#include <linux/serial_core.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/backlight.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/exynos4.h>
-#include <plat/gpio-cfg.h>
-#include <plat/iic.h>
-#include <plat/keypad.h>
-#include <plat/regs-serial.h>
-#include <plat/sdhci.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK4X12_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
-
-#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG4 |        \
-                                S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .flags          = 0,
-               .ucon           = SMDK4X12_UCON_DEFAULT,
-               .ulcon          = SMDK4X12_ULCON_DEFAULT,
-               .ufcon          = SMDK4X12_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .flags          = 0,
-               .ucon           = SMDK4X12_UCON_DEFAULT,
-               .ulcon          = SMDK4X12_ULCON_DEFAULT,
-               .ufcon          = SMDK4X12_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .flags          = 0,
-               .ucon           = SMDK4X12_UCON_DEFAULT,
-               .ulcon          = SMDK4X12_ULCON_DEFAULT,
-               .ufcon          = SMDK4X12_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .flags          = 0,
-               .ucon           = SMDK4X12_UCON_DEFAULT,
-               .ulcon          = SMDK4X12_ULCON_DEFAULT,
-               .ufcon          = SMDK4X12_UFCON_DEFAULT,
-       },
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-       .max_width              = 8,
-       .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct regulator_consumer_supply max8997_buck1 =
-       REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct regulator_consumer_supply max8997_buck2 =
-       REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply max8997_buck3 =
-       REGULATOR_SUPPLY("vdd_g3d", NULL);
-
-static struct regulator_init_data max8997_buck1_data = {
-       .constraints    = {
-               .name           = "VDD_ARM_SMDK4X12",
-               .min_uV         = 925000,
-               .max_uV         = 1350000,
-               .always_on      = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &max8997_buck1,
-};
-
-static struct regulator_init_data max8997_buck2_data = {
-       .constraints    = {
-               .name           = "VDD_INT_SMDK4X12",
-               .min_uV         = 950000,
-               .max_uV         = 1150000,
-               .always_on      = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &max8997_buck2,
-};
-
-static struct regulator_init_data max8997_buck3_data = {
-       .constraints    = {
-               .name           = "VDD_G3D_SMDK4X12",
-               .min_uV         = 950000,
-               .max_uV         = 1150000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                 REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &max8997_buck3,
-};
-
-static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
-       { MAX8997_BUCK1, &max8997_buck1_data },
-       { MAX8997_BUCK2, &max8997_buck2_data },
-       { MAX8997_BUCK3, &max8997_buck3_data },
-};
-
-static struct max8997_platform_data smdk4x12_max8997_pdata = {
-       .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
-       .regulators     = smdk4x12_max8997_regulators,
-
-       .buck1_voltage[0] = 1100000,    /* 1.1V */
-       .buck1_voltage[1] = 1100000,    /* 1.1V */
-       .buck1_voltage[2] = 1100000,    /* 1.1V */
-       .buck1_voltage[3] = 1100000,    /* 1.1V */
-       .buck1_voltage[4] = 1100000,    /* 1.1V */
-       .buck1_voltage[5] = 1100000,    /* 1.1V */
-       .buck1_voltage[6] = 1000000,    /* 1.0V */
-       .buck1_voltage[7] = 950000,     /* 0.95V */
-
-       .buck2_voltage[0] = 1100000,    /* 1.1V */
-       .buck2_voltage[1] = 1000000,    /* 1.0V */
-       .buck2_voltage[2] = 950000,     /* 0.95V */
-       .buck2_voltage[3] = 900000,     /* 0.9V */
-       .buck2_voltage[4] = 1100000,    /* 1.1V */
-       .buck2_voltage[5] = 1000000,    /* 1.0V */
-       .buck2_voltage[6] = 950000,     /* 0.95V */
-       .buck2_voltage[7] = 900000,     /* 0.9V */
-
-       .buck5_voltage[0] = 1100000,    /* 1.1V */
-       .buck5_voltage[1] = 1100000,    /* 1.1V */
-       .buck5_voltage[2] = 1100000,    /* 1.1V */
-       .buck5_voltage[3] = 1100000,    /* 1.1V */
-       .buck5_voltage[4] = 1100000,    /* 1.1V */
-       .buck5_voltage[5] = 1100000,    /* 1.1V */
-       .buck5_voltage[6] = 1100000,    /* 1.1V */
-       .buck5_voltage[7] = 1100000,    /* 1.1V */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
-       {
-               I2C_BOARD_INFO("max8997", 0x66),
-               .platform_data  = &smdk4x12_max8997_pdata,
-       }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
-       { I2C_BOARD_INFO("wm8994", 0x1a), }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
-       /* nothing here yet */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
-       /* nothing here yet */
-};
-
-static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
-       .no = EXYNOS4_GPD0(1),
-       .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdk4x12_bl_data = {
-       .pwm_id = 1,
-       .pwm_period_ns  = 1000,
-};
-
-static uint32_t smdk4x12_keymap[] __initdata = {
-       /* KEY(row, col, keycode) */
-       KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
-       KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
-};
-
-static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
-       .keymap         = smdk4x12_keymap,
-       .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
-};
-
-static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
-       .keymap_data    = &smdk4x12_keymap_data,
-       .rows           = 2,
-       .cols           = 5,
-};
-
-static struct platform_device *smdk4x12_devices[] __initdata = {
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc3,
-       &s3c_device_i2c0,
-       &s3c_device_i2c1,
-       &s3c_device_i2c3,
-       &s3c_device_i2c7,
-       &s3c_device_rtc,
-       &s3c_device_wdt,
-       &samsung_device_keypad,
-};
-
-static void __init smdk4x12_map_io(void)
-{
-       clk_xusbxti.rate = 24000000;
-
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(clk_xusbxti.rate);
-       s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
-}
-
-static void __init smdk4x12_machine_init(void)
-{
-       s3c_i2c0_set_platdata(NULL);
-       i2c_register_board_info(0, smdk4x12_i2c_devs0,
-                               ARRAY_SIZE(smdk4x12_i2c_devs0));
-
-       s3c_i2c1_set_platdata(NULL);
-       i2c_register_board_info(1, smdk4x12_i2c_devs1,
-                               ARRAY_SIZE(smdk4x12_i2c_devs1));
-
-       s3c_i2c3_set_platdata(NULL);
-       i2c_register_board_info(3, smdk4x12_i2c_devs3,
-                               ARRAY_SIZE(smdk4x12_i2c_devs3));
-
-       s3c_i2c7_set_platdata(NULL);
-       i2c_register_board_info(7, smdk4x12_i2c_devs7,
-                               ARRAY_SIZE(smdk4x12_i2c_devs7));
-
-       samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
-
-       samsung_keypad_set_platdata(&smdk4x12_keypad_data);
-
-       s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
-       s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
-
-       platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
-}
-
-MACHINE_START(SMDK4212, "SMDK4212")
-       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = smdk4x12_map_io,
-       .init_machine   = smdk4x12_machine_init,
-       .timer          = &exynos4_timer,
-MACHINE_END
-
-MACHINE_START(SMDK4412, "SMDK4412")
-       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-       /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = smdk4x12_map_io,
-       .init_machine   = smdk4x12_machine_init,
-       .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
deleted file mode 100644 (file)
index cec2afa..0000000
+++ /dev/null
@@ -1,390 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/keypad.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/pd.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/mfc.h>
-#include <plat/ehci.h>
-#include <plat/clock.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKV310_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
-
-#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG4 |        \
-                                S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .flags          = 0,
-               .ucon           = SMDKV310_UCON_DEFAULT,
-               .ulcon          = SMDKV310_ULCON_DEFAULT,
-               .ufcon          = SMDKV310_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .flags          = 0,
-               .ucon           = SMDKV310_UCON_DEFAULT,
-               .ulcon          = SMDKV310_ULCON_DEFAULT,
-               .ufcon          = SMDKV310_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .flags          = 0,
-               .ucon           = SMDKV310_UCON_DEFAULT,
-               .ulcon          = SMDKV310_ULCON_DEFAULT,
-               .ufcon          = SMDKV310_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .flags          = 0,
-               .ucon           = SMDKV310_UCON_DEFAULT,
-               .ulcon          = SMDKV310_ULCON_DEFAULT,
-               .ufcon          = SMDKV310_UFCON_DEFAULT,
-       },
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-       .max_width              = 8,
-       .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .ext_cd_gpio            = EXYNOS4_GPK0(2),
-       .ext_cd_gpio_invert     = 1,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_INTERNAL,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-       .max_width              = 8,
-       .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .ext_cd_gpio            = EXYNOS4_GPK2(2),
-       .ext_cd_gpio_invert     = 1,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                  unsigned int power)
-{
-       if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-               gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-               gpio_free(EXYNOS4_GPD0(1));
-#endif
-               /* fire nRESET on power up */
-               gpio_request(EXYNOS4_GPX0(6), "GPX0");
-
-               gpio_direction_output(EXYNOS4_GPX0(6), 1);
-               mdelay(100);
-
-               gpio_set_value(EXYNOS4_GPX0(6), 0);
-               mdelay(10);
-
-               gpio_set_value(EXYNOS4_GPX0(6), 1);
-               mdelay(10);
-
-               gpio_free(EXYNOS4_GPX0(6));
-       } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-               gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-               gpio_free(EXYNOS4_GPD0(1));
-#endif
-       }
-}
-
-static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
-       .set_power              = lcd_lte480wv_set_power,
-};
-
-static struct platform_device smdkv310_lcd_lte480wv = {
-       .name                   = "platform-lcd",
-       .dev.parent             = &s5p_device_fimd0.dev,
-       .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
-};
-
-static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-       .win_mode = {
-               .left_margin    = 13,
-               .right_margin   = 8,
-               .upper_margin   = 7,
-               .lower_margin   = 5,
-               .hsync_len      = 3,
-               .vsync_len      = 1,
-               .xres           = 800,
-               .yres           = 480,
-       },
-       .max_bpp                = 32,
-       .default_bpp            = 24,
-};
-
-static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
-       .win[0]         = &smdkv310_fb_win0,
-       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static struct resource smdkv310_smsc911x_resources[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_SROM_BANK(1),
-               .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_EINT(5),
-               .end    = IRQ_EINT(5),
-               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-       },
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-       .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-       .phy_interface  = PHY_INTERFACE_MODE_MII,
-       .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device smdkv310_smsc911x = {
-       .name           = "smsc911x",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
-       .resource       = smdkv310_smsc911x_resources,
-       .dev            = {
-               .platform_data  = &smsc9215_config,
-       },
-};
-
-static uint32_t smdkv310_keymap[] __initdata = {
-       /* KEY(row, col, keycode) */
-       KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-       KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-       KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-       KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-
-static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
-       .keymap         = smdkv310_keymap,
-       .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
-};
-
-static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
-       .keymap_data    = &smdkv310_keymap_data,
-       .rows           = 2,
-       .cols           = 8,
-};
-
-static struct i2c_board_info i2c_devs1[] __initdata = {
-       {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata smdkv310_ehci_pdata;
-
-static void __init smdkv310_ehci_init(void)
-{
-       struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
-
-       s5p_ehci_set_platdata(pdata);
-}
-
-static struct platform_device *smdkv310_devices[] __initdata = {
-       &s3c_device_hsmmc0,
-       &s3c_device_hsmmc1,
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc3,
-       &s3c_device_i2c1,
-       &s5p_device_i2c_hdmiphy,
-       &s3c_device_rtc,
-       &s3c_device_wdt,
-       &s5p_device_ehci,
-       &s5p_device_fimc0,
-       &s5p_device_fimc1,
-       &s5p_device_fimc2,
-       &s5p_device_fimc3,
-       &exynos4_device_ac97,
-       &exynos4_device_i2s0,
-       &samsung_device_keypad,
-       &s5p_device_mfc,
-       &s5p_device_mfc_l,
-       &s5p_device_mfc_r,
-       &exynos4_device_pd[PD_MFC],
-       &exynos4_device_pd[PD_G3D],
-       &exynos4_device_pd[PD_LCD0],
-       &exynos4_device_pd[PD_LCD1],
-       &exynos4_device_pd[PD_CAM],
-       &exynos4_device_pd[PD_TV],
-       &exynos4_device_pd[PD_GPS],
-       &exynos4_device_spdif,
-       &exynos4_device_sysmmu,
-       &samsung_asoc_dma,
-       &samsung_asoc_idma,
-       &s5p_device_fimd0,
-       &smdkv310_lcd_lte480wv,
-       &smdkv310_smsc911x,
-       &exynos4_device_ahci,
-       &s5p_device_hdmi,
-       &s5p_device_mixer,
-};
-
-static void __init smdkv310_smsc911x_init(void)
-{
-       u32 cs1;
-
-       /* configure nCS1 width to 16 bits */
-       cs1 = __raw_readl(S5P_SROM_BW) &
-               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-               (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-               S5P_SROM_BW__NCS1__SHIFT;
-       __raw_writel(cs1, S5P_SROM_BW);
-
-       /* set timing for nCS1 suitable for ethernet chip */
-       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
-       .no = EXYNOS4_GPD0(1),
-       .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkv310_bl_data = {
-       .pwm_id = 1,
-       .pwm_period_ns  = 1000,
-};
-
-static void s5p_tv_setup(void)
-{
-       /* direct HPD to HDMI chip */
-       WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
-       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-
-       /* setup dependencies between TV devices */
-       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
-       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
-}
-
-static void __init smdkv310_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
-}
-
-static void __init smdkv310_reserve(void)
-{
-       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdkv310_machine_init(void)
-{
-       s3c_i2c1_set_platdata(NULL);
-       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-       smdkv310_smsc911x_init();
-
-       s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
-       s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
-       s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
-       s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
-
-       s5p_tv_setup();
-       s5p_i2c_hdmiphy_set_platdata(NULL);
-
-       samsung_keypad_set_platdata(&smdkv310_keypad_data);
-
-       samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
-       s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
-
-       smdkv310_ehci_init();
-       clk_xusbxti.rate = 24000000;
-
-       platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
-       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
-}
-
-MACHINE_START(SMDKV310, "SMDKV310")
-       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-       /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = smdkv310_map_io,
-       .init_machine   = smdkv310_machine_init,
-       .timer          = &exynos4_timer,
-       .reserve        = &smdkv310_reserve,
-MACHINE_END
-
-MACHINE_START(SMDKC210, "SMDKC210")
-       /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = smdkv310_map_io,
-       .init_machine   = smdkv310_machine_init,
-       .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
deleted file mode 100644 (file)
index a2a177f..0000000
+++ /dev/null
@@ -1,1064 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/fb.h>
-#include <linux/mfd/max8998.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/max8952.h>
-#include <linux/mmc/host.h>
-#include <linux/i2c-gpio.h>
-#include <linux/i2c/mcs.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/sdhci.h>
-#include <plat/pd.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-#include <plat/mipi_csis.h>
-
-#include <mach/map.h>
-
-#include <media/v4l2-mediabus.h>
-#include <media/s5p_fimc.h>
-#include <media/m5mols.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define UNIVERSAL_ULCON_DEFAULT        S3C2410_LCON_CS8
-
-#define UNIVERSAL_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG256 |      \
-                                S5PV210_UFCON_RXTRIG256)
-
-static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .ucon           = UNIVERSAL_UCON_DEFAULT,
-               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .ucon           = UNIVERSAL_UCON_DEFAULT,
-               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .ucon           = UNIVERSAL_UCON_DEFAULT,
-               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .ucon           = UNIVERSAL_UCON_DEFAULT,
-               .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-               .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-       },
-};
-
-static struct regulator_consumer_supply max8952_consumer =
-       REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct max8952_platform_data universal_max8952_pdata __initdata = {
-       .gpio_vid0      = EXYNOS4_GPX0(3),
-       .gpio_vid1      = EXYNOS4_GPX0(4),
-       .gpio_en        = -1, /* Not controllable, set "Always High" */
-       .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
-       .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
-       .sync_freq      = 0, /* default: fastest */
-       .ramp_speed     = 0, /* default: fastest */
-
-       .reg_data       = {
-               .constraints    = {
-                       .name           = "VARM_1.2V",
-                       .min_uV         = 770000,
-                       .max_uV         = 1400000,
-                       .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                       .always_on      = 1,
-                       .boot_on        = 1,
-               },
-               .num_consumer_supplies  = 1,
-               .consumer_supplies      = &max8952_consumer,
-       },
-};
-
-static struct regulator_consumer_supply lp3974_buck1_consumer =
-       REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply lp3974_buck2_consumer =
-       REGULATOR_SUPPLY("vddg3d", NULL);
-
-static struct regulator_consumer_supply lp3974_buck3_consumer =
-       REGULATOR_SUPPLY("vdet", "s5p-sdo");
-
-static struct regulator_init_data lp3974_buck1_data = {
-       .constraints    = {
-               .name           = "VINT_1.1V",
-               .min_uV         = 750000,
-               .max_uV         = 1500000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                       REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = 1,
-       .consumer_supplies = &lp3974_buck1_consumer,
-};
-
-static struct regulator_init_data lp3974_buck2_data = {
-       .constraints    = {
-               .name           = "VG3D_1.1V",
-               .min_uV         = 750000,
-               .max_uV         = 1500000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                       REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = 1,
-       .consumer_supplies = &lp3974_buck2_consumer,
-};
-
-static struct regulator_init_data lp3974_buck3_data = {
-       .constraints    = {
-               .name           = "VCC_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-       .num_consumer_supplies = 1,
-       .consumer_supplies = &lp3974_buck3_consumer,
-};
-
-static struct regulator_init_data lp3974_buck4_data = {
-       .constraints    = {
-               .name           = "VMEM_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .apply_uV       = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_ldo2_data = {
-       .constraints    = {
-               .name           = "VALIVE_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
-       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
-       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
-       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo3_data = {
-       .constraints    = {
-               .name           = "VUSB+MIPI_1.1V",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
-       .consumer_supplies = lp3974_ldo3_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
-       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
-};
-
-static struct regulator_init_data lp3974_ldo4_data = {
-       .constraints    = {
-               .name           = "VADC_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
-       .consumer_supplies = lp3974_ldo4_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo5_data = {
-       .constraints    = {
-               .name           = "VTF_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_ldo6_data = {
-       .constraints    = {
-               .name           = "LDO6",
-               .min_uV         = 2000000,
-               .max_uV         = 2000000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
-       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo7_data = {
-       .constraints    = {
-               .name           = "VLCD+VMIPI_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
-       .consumer_supplies      = lp3974_ldo7_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
-       REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
-};
-
-static struct regulator_init_data lp3974_ldo8_data = {
-       .constraints    = {
-               .name           = "VUSB+VDAC_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
-       .consumer_supplies = lp3974_ldo8_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo9_data = {
-       .constraints    = {
-               .name           = "VCC_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_ldo10_data = {
-       .constraints    = {
-               .name           = "VPLL_1.1V",
-               .min_uV         = 1100000,
-               .max_uV         = 1100000,
-               .boot_on        = 1,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_consumer_supply lp3974_ldo11_consumer =
-       REGULATOR_SUPPLY("dig_28", "0-001f");
-
-static struct regulator_init_data lp3974_ldo11_data = {
-       .constraints    = {
-               .name           = "CAM_AF_3.3V",
-               .min_uV         = 3300000,
-               .max_uV         = 3300000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &lp3974_ldo11_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo12_data = {
-       .constraints    = {
-               .name           = "PS_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_ldo13_data = {
-       .constraints    = {
-               .name           = "VHIC_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_consumer_supply lp3974_ldo14_consumer =
-       REGULATOR_SUPPLY("dig_18", "0-001f");
-
-static struct regulator_init_data lp3974_ldo14_data = {
-       .constraints    = {
-               .name           = "CAM_I_HOST_1.8V",
-               .min_uV         = 1800000,
-               .max_uV         = 1800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &lp3974_ldo14_consumer,
-};
-
-
-static struct regulator_consumer_supply lp3974_ldo15_consumer =
-       REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data lp3974_ldo15_data = {
-       .constraints    = {
-               .name           = "CAM_S_DIG+FM33_CORE_1.2V",
-               .min_uV         = 1200000,
-               .max_uV         = 1200000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &lp3974_ldo15_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
-       REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data lp3974_ldo16_data = {
-       .constraints    = {
-               .name           = "CAM_S_ANA_2.8V",
-               .min_uV         = 2800000,
-               .max_uV         = 2800000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
-       .consumer_supplies      = lp3974_ldo16_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo17_data = {
-       .constraints    = {
-               .name           = "VCC_3.0V_LCD",
-               .min_uV         = 3000000,
-               .max_uV         = 3000000,
-               .apply_uV       = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_32khz_ap_data = {
-       .constraints    = {
-               .name           = "32KHz AP",
-               .always_on      = 1,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_32khz_cp_data = {
-       .constraints    = {
-               .name           = "32KHz CP",
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_vichg_data = {
-       .constraints    = {
-               .name           = "VICHG",
-               .state_mem      = {
-                       .disabled       = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_esafeout1_data = {
-       .constraints    = {
-               .name           = "SAFEOUT1",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct regulator_init_data lp3974_esafeout2_data = {
-       .constraints    = {
-               .name           = "SAFEOUT2",
-               .boot_on        = 1,
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .state_mem      = {
-                       .enabled        = 1,
-               },
-       },
-};
-
-static struct max8998_regulator_data lp3974_regulators[] = {
-       { MAX8998_LDO2,  &lp3974_ldo2_data },
-       { MAX8998_LDO3,  &lp3974_ldo3_data },
-       { MAX8998_LDO4,  &lp3974_ldo4_data },
-       { MAX8998_LDO5,  &lp3974_ldo5_data },
-       { MAX8998_LDO6,  &lp3974_ldo6_data },
-       { MAX8998_LDO7,  &lp3974_ldo7_data },
-       { MAX8998_LDO8,  &lp3974_ldo8_data },
-       { MAX8998_LDO9,  &lp3974_ldo9_data },
-       { MAX8998_LDO10, &lp3974_ldo10_data },
-       { MAX8998_LDO11, &lp3974_ldo11_data },
-       { MAX8998_LDO12, &lp3974_ldo12_data },
-       { MAX8998_LDO13, &lp3974_ldo13_data },
-       { MAX8998_LDO14, &lp3974_ldo14_data },
-       { MAX8998_LDO15, &lp3974_ldo15_data },
-       { MAX8998_LDO16, &lp3974_ldo16_data },
-       { MAX8998_LDO17, &lp3974_ldo17_data },
-       { MAX8998_BUCK1, &lp3974_buck1_data },
-       { MAX8998_BUCK2, &lp3974_buck2_data },
-       { MAX8998_BUCK3, &lp3974_buck3_data },
-       { MAX8998_BUCK4, &lp3974_buck4_data },
-       { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
-       { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
-       { MAX8998_ENVICHG, &lp3974_vichg_data },
-       { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
-       { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
-};
-
-static struct max8998_platform_data universal_lp3974_pdata = {
-       .num_regulators         = ARRAY_SIZE(lp3974_regulators),
-       .regulators             = lp3974_regulators,
-       .buck1_voltage1         = 1100000,      /* INT */
-       .buck1_voltage2         = 1000000,
-       .buck1_voltage3         = 1100000,
-       .buck1_voltage4         = 1000000,
-       .buck1_set1             = EXYNOS4_GPX0(5),
-       .buck1_set2             = EXYNOS4_GPX0(6),
-       .buck2_voltage1         = 1200000,      /* G3D */
-       .buck2_voltage2         = 1100000,
-       .buck1_default_idx      = 0,
-       .buck2_set3             = EXYNOS4_GPE2(0),
-       .buck2_default_idx      = 0,
-       .wakeup                 = true,
-};
-
-
-enum fixed_regulator_id {
-       FIXED_REG_ID_MMC0,
-       FIXED_REG_ID_HDMI_5V,
-       FIXED_REG_ID_CAM_S_IF,
-       FIXED_REG_ID_CAM_I_CORE,
-       FIXED_REG_ID_CAM_VT_DIO,
-};
-
-static struct regulator_consumer_supply hdmi_fixed_consumer =
-       REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
-
-static struct regulator_init_data hdmi_fixed_voltage_init_data = {
-       .constraints            = {
-               .name           = "HDMI_5V",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &hdmi_fixed_consumer,
-};
-
-static struct fixed_voltage_config hdmi_fixed_voltage_config = {
-       .supply_name            = "HDMI_EN1",
-       .microvolts             = 5000000,
-       .gpio                   = EXYNOS4_GPE0(1),
-       .enable_high            = true,
-       .init_data              = &hdmi_fixed_voltage_init_data,
-};
-
-static struct platform_device hdmi_fixed_voltage = {
-       .name                   = "reg-fixed-voltage",
-       .id                     = FIXED_REG_ID_HDMI_5V,
-       .dev                    = {
-               .platform_data  = &hdmi_fixed_voltage_config,
-       },
-};
-
-/* GPIO I2C 5 (PMIC) */
-static struct i2c_board_info i2c5_devs[] __initdata = {
-       {
-               I2C_BOARD_INFO("max8952", 0xC0 >> 1),
-               .platform_data  = &universal_max8952_pdata,
-       }, {
-               I2C_BOARD_INFO("lp3974", 0xCC >> 1),
-               .platform_data  = &universal_lp3974_pdata,
-       },
-};
-
-/* I2C3 (TSP) */
-static struct mxt_platform_data qt602240_platform_data = {
-       .x_line         = 19,
-       .y_line         = 11,
-       .x_size         = 800,
-       .y_size         = 480,
-       .blen           = 0x11,
-       .threshold      = 0x28,
-       .voltage        = 2800000,              /* 2.8V */
-       .orient         = MXT_DIAGONAL,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-       {
-               I2C_BOARD_INFO("qt602240_ts", 0x4a),
-               .platform_data = &qt602240_platform_data,
-       },
-};
-
-static void __init universal_tsp_init(void)
-{
-       int gpio;
-
-       /* TSP_LDO_ON: XMDMADDR_11 */
-       gpio = EXYNOS4_GPE2(3);
-       gpio_request(gpio, "TSP_LDO_ON");
-       gpio_direction_output(gpio, 1);
-       gpio_export(gpio, 0);
-
-       /* TSP_INT: XMDMADDR_7 */
-       gpio = EXYNOS4_GPE1(7);
-       gpio_request(gpio, "TSP_INT");
-
-       s5p_register_gpio_interrupt(gpio);
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-       i2c3_devs[0].irq = gpio_to_irq(gpio);
-}
-
-
-/* GPIO I2C 12 (3 Touchkey) */
-static uint32_t touchkey_keymap[] = {
-       /* MCS_KEY_MAP(value, keycode) */
-       MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
-       MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
-};
-
-static struct mcs_platform_data touchkey_data = {
-       .keymap         = touchkey_keymap,
-       .keymap_size    = ARRAY_SIZE(touchkey_keymap),
-       .key_maxval     = 2,
-};
-
-/* GPIO I2C 3_TOUCH 2.8V */
-#define I2C_GPIO_BUS_12                12
-static struct i2c_gpio_platform_data i2c_gpio12_data = {
-       .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
-       .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
-};
-
-static struct platform_device i2c_gpio12 = {
-       .name           = "i2c-gpio",
-       .id             = I2C_GPIO_BUS_12,
-       .dev            = {
-               .platform_data  = &i2c_gpio12_data,
-       },
-};
-
-static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
-       {
-               I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
-               .platform_data = &touchkey_data,
-       },
-};
-
-static void __init universal_touchkey_init(void)
-{
-       int gpio;
-
-       gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
-       gpio_request(gpio, "3_TOUCH_INT");
-       s5p_register_gpio_interrupt(gpio);
-       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-       i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
-
-       gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-       gpio_request(gpio, "3_TOUCH_EN");
-       gpio_direction_output(gpio, 1);
-}
-
-static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
-       .frequency      = 300 * 1000,
-       .sda_delay      = 200,
-};
-
-/* GPIO KEYS */
-static struct gpio_keys_button universal_gpio_keys_tables[] = {
-       {
-               .code                   = KEY_VOLUMEUP,
-               .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-               .desc                   = "gpio-keys: KEY_VOLUMEUP",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_VOLUMEDOWN,
-               .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-               .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_CONFIG,
-               .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
-               .desc                   = "gpio-keys: KEY_CONFIG",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_CAMERA,
-               .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
-               .desc                   = "gpio-keys: KEY_CAMERA",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       }, {
-               .code                   = KEY_OK,
-               .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
-               .desc                   = "gpio-keys: KEY_OK",
-               .type                   = EV_KEY,
-               .active_low             = 1,
-               .debounce_interval      = 1,
-       },
-};
-
-static struct gpio_keys_platform_data universal_gpio_keys_data = {
-       .buttons        = universal_gpio_keys_tables,
-       .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
-};
-
-static struct platform_device universal_gpio_keys = {
-       .name                   = "gpio-keys",
-       .dev                    = {
-               .platform_data  = &universal_gpio_keys_data,
-       },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
-       .max_width              = 8,
-       .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                               MMC_CAP_DISABLE),
-       .cd_type                = S3C_SDHCI_CD_PERMANENT,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct regulator_consumer_supply mmc0_supplies[] = {
-       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
-};
-
-static struct regulator_init_data mmc0_fixed_voltage_init_data = {
-       .constraints            = {
-               .name           = "VMEM_VDD_2.8V",
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-       },
-       .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
-       .consumer_supplies      = mmc0_supplies,
-};
-
-static struct fixed_voltage_config mmc0_fixed_voltage_config = {
-       .supply_name            = "MASSMEMORY_EN",
-       .microvolts             = 2800000,
-       .gpio                   = EXYNOS4_GPE1(3),
-       .enable_high            = true,
-       .init_data              = &mmc0_fixed_voltage_init_data,
-};
-
-static struct platform_device mmc0_fixed_voltage = {
-       .name                   = "reg-fixed-voltage",
-       .id                     = FIXED_REG_ID_MMC0,
-       .dev                    = {
-               .platform_data  = &mmc0_fixed_voltage_config,
-       },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
-       .max_width              = 4,
-       .host_caps              = MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                               MMC_CAP_DISABLE,
-       .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
-       .ext_cd_gpio_invert     = 1,
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-/* WiFi */
-static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
-       .max_width              = 4,
-       .host_caps              = MMC_CAP_4_BIT_DATA |
-                               MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                               MMC_CAP_DISABLE,
-       .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init universal_sdhci_init(void)
-{
-       s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
-       s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
-       s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
-}
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-       /* Gyro, To be updated */
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win universal_fb_win0 = {
-       .win_mode = {
-               .left_margin    = 16,
-               .right_margin   = 16,
-               .upper_margin   = 2,
-               .lower_margin   = 28,
-               .hsync_len      = 2,
-               .vsync_len      = 1,
-               .xres           = 480,
-               .yres           = 800,
-               .refresh        = 55,
-       },
-       .max_bpp        = 32,
-       .default_bpp    = 16,
-};
-
-static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
-       .win[0]         = &universal_fb_win0,
-       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                         VIDCON0_CLKSEL_LCD,
-       .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                         | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static struct regulator_consumer_supply cam_i_core_supply =
-       REGULATOR_SUPPLY("core", "0-001f");
-
-static struct regulator_init_data cam_i_core_reg_init_data = {
-       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-       .num_consumer_supplies = 1,
-       .consumer_supplies = &cam_i_core_supply,
-};
-
-static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
-       .supply_name    = "CAM_I_CORE_1.2V",
-       .microvolts     = 1200000,
-       .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
-       .enable_high    = 1,
-       .init_data      = &cam_i_core_reg_init_data,
-};
-
-static struct platform_device cam_i_core_fixed_reg_dev = {
-       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
-       .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_s_if_supply =
-       REGULATOR_SUPPLY("d_sensor", "0-001f");
-
-static struct regulator_init_data cam_s_if_reg_init_data = {
-       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-       .num_consumer_supplies = 1,
-       .consumer_supplies = &cam_s_if_supply,
-};
-
-static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
-       .supply_name    = "CAM_S_IF_1.8V",
-       .microvolts     = 1800000,
-       .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
-       .enable_high    = 1,
-       .init_data      = &cam_s_if_reg_init_data,
-};
-
-static struct platform_device cam_s_if_fixed_reg_dev = {
-       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
-       .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-       .clk_rate       = 166000000UL,
-       .lanes          = 2,
-       .alignment      = 32,
-       .hs_settle      = 12,
-       .phy_enable     = s5p_csis_phy_enable,
-};
-
-#define GPIO_CAM_LEVEL_EN(n)   EXYNOS4_GPE4(n + 3)
-#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPX1(5) /* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST     EXYNOS4_GPE2(5)
-
-static int m5mols_set_power(struct device *dev, int on)
-{
-       gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
-       gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-       return 0;
-}
-
-static struct m5mols_platform_data m5mols_platdata = {
-       .gpio_reset     = GPIO_CAM_MEGA_nRST,
-       .reset_polarity = 0,
-       .set_power      = m5mols_set_power,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-       I2C_BOARD_INFO("M5MOLS", 0x1F),
-       .platform_data = &m5mols_platdata,
-};
-
-static struct s5p_fimc_isp_info universal_camera_sensors[] = {
-       {
-               .mux_id         = 0,
-               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
-               .bus_type       = FIMC_MIPI_CSI2,
-               .board_info     = &m5mols_board_info,
-               .i2c_bus_num    = 0,
-               .clk_frequency  = 21600000UL,
-               .csi_data_align = 32,
-       },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-       .isp_info       = universal_camera_sensors,
-       .num_clients    = ARRAY_SIZE(universal_camera_sensors),
-};
-
-static struct gpio universal_camera_gpios[] = {
-       { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
-       { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
-       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
-       { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
-};
-
-static void universal_camera_init(void)
-{
-       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                        &s5p_device_mipi_csis0);
-       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                        &s5p_device_fimc_md);
-
-       if (gpio_request_array(universal_camera_gpios,
-                              ARRAY_SIZE(universal_camera_gpios))) {
-               pr_err("%s: GPIO request failed\n", __func__);
-               return;
-       }
-
-       if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
-               m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
-       else
-               pr_err("Failed to configure 8M_ISP_INT GPIO\n");
-
-       /* Free GPIOs controlled directly by the sensor drivers. */
-       gpio_free(GPIO_CAM_MEGA_nRST);
-       gpio_free(GPIO_CAM_8M_ISP_INT);
-
-       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
-               pr_err("Camera port A setup failed\n");
-}
-
-static struct platform_device *universal_devices[] __initdata = {
-       /* Samsung Platform Devices */
-       &s5p_device_mipi_csis0,
-       &s5p_device_fimc0,
-       &s5p_device_fimc1,
-       &s5p_device_fimc2,
-       &s5p_device_fimc3,
-       &mmc0_fixed_voltage,
-       &s3c_device_hsmmc0,
-       &s3c_device_hsmmc2,
-       &s3c_device_hsmmc3,
-       &s3c_device_i2c0,
-       &s3c_device_i2c3,
-       &s3c_device_i2c5,
-       &s5p_device_i2c_hdmiphy,
-       &hdmi_fixed_voltage,
-       &exynos4_device_pd[PD_TV],
-       &s5p_device_hdmi,
-       &s5p_device_sdo,
-       &s5p_device_mixer,
-
-       /* Universal Devices */
-       &i2c_gpio12,
-       &universal_gpio_keys,
-       &s5p_device_onenand,
-       &s5p_device_fimd0,
-       &s5p_device_mfc,
-       &s5p_device_mfc_l,
-       &s5p_device_mfc_r,
-       &exynos4_device_pd[PD_MFC],
-       &exynos4_device_pd[PD_LCD0],
-       &exynos4_device_pd[PD_CAM],
-       &cam_i_core_fixed_reg_dev,
-       &cam_s_if_fixed_reg_dev,
-       &s5p_device_fimc_md,
-};
-
-static void __init universal_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-}
-
-void s5p_tv_setup(void)
-{
-       /* direct HPD to HDMI chip */
-       gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
-
-       gpio_direction_input(EXYNOS4_GPX3(7));
-       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-
-       /* setup dependencies between TV devices */
-       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
-       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
-}
-
-static void __init universal_reserve(void)
-{
-       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init universal_machine_init(void)
-{
-       universal_sdhci_init();
-       s5p_tv_setup();
-
-       s3c_i2c0_set_platdata(&universal_i2c0_platdata);
-       i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-
-       universal_tsp_init();
-       s3c_i2c3_set_platdata(NULL);
-       i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-
-       s3c_i2c5_set_platdata(NULL);
-       s5p_i2c_hdmiphy_set_platdata(NULL);
-       i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-
-       s5p_fimd0_set_platdata(&universal_lcd_pdata);
-
-       universal_touchkey_init();
-       i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-                       ARRAY_SIZE(i2c_gpio12_devs));
-
-       universal_camera_init();
-
-       /* Last */
-       platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-
-       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
-       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
-       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
-}
-
-MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
-       /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = universal_map_io,
-       .init_machine   = universal_machine_init,
-       .timer          = &exynos4_timer,
-       .reserve        = &universal_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
deleted file mode 100644 (file)
index 97343df..0000000
+++ /dev/null
@@ -1,471 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mct.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 MCT(Multi-Core Timer) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/percpu.h>
-
-#include <asm/hardware/gic.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-mct.h>
-#include <asm/mach/time.h>
-
-enum {
-       MCT_INT_SPI,
-       MCT_INT_PPI
-};
-
-static unsigned long clk_cnt_per_tick;
-static unsigned long clk_rate;
-static unsigned int mct_int_type;
-
-struct mct_clock_event_device {
-       struct clock_event_device *evt;
-       void __iomem *base;
-       char name[10];
-};
-
-static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
-
-static void exynos4_mct_write(unsigned int value, void *addr)
-{
-       void __iomem *stat_addr;
-       u32 mask;
-       u32 i;
-
-       __raw_writel(value, addr);
-
-       if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-               u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-               switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-               case (u32) MCT_L_TCON_OFFSET:
-                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                       mask = 1 << 3;          /* L_TCON write status */
-                       break;
-               case (u32) MCT_L_ICNTB_OFFSET:
-                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                       mask = 1 << 1;          /* L_ICNTB write status */
-                       break;
-               case (u32) MCT_L_TCNTB_OFFSET:
-                       stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                       mask = 1 << 0;          /* L_TCNTB write status */
-                       break;
-               default:
-                       return;
-               }
-       } else {
-               switch ((u32) addr) {
-               case (u32) EXYNOS4_MCT_G_TCON:
-                       stat_addr = EXYNOS4_MCT_G_WSTAT;
-                       mask = 1 << 16;         /* G_TCON write status */
-                       break;
-               case (u32) EXYNOS4_MCT_G_COMP0_L:
-                       stat_addr = EXYNOS4_MCT_G_WSTAT;
-                       mask = 1 << 0;          /* G_COMP0_L write status */
-                       break;
-               case (u32) EXYNOS4_MCT_G_COMP0_U:
-                       stat_addr = EXYNOS4_MCT_G_WSTAT;
-                       mask = 1 << 1;          /* G_COMP0_U write status */
-                       break;
-               case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                       stat_addr = EXYNOS4_MCT_G_WSTAT;
-                       mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
-                       break;
-               case (u32) EXYNOS4_MCT_G_CNT_L:
-                       stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                       mask = 1 << 0;          /* G_CNT_L write status */
-                       break;
-               case (u32) EXYNOS4_MCT_G_CNT_U:
-                       stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                       mask = 1 << 1;          /* G_CNT_U write status */
-                       break;
-               default:
-                       return;
-               }
-       }
-
-       /* Wait maximum 1 ms until written values are applied */
-       for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-               if (__raw_readl(stat_addr) & mask) {
-                       __raw_writel(mask, stat_addr);
-                       return;
-               }
-
-       panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
-}
-
-/* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
-{
-       u32 reg;
-
-       exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
-       exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
-       reg = __raw_readl(EXYNOS4_MCT_G_TCON);
-       reg |= MCT_G_TCON_START;
-       exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
-}
-
-static cycle_t exynos4_frc_read(struct clocksource *cs)
-{
-       unsigned int lo, hi;
-       u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-
-       do {
-               hi = hi2;
-               lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-               hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-       } while (hi != hi2);
-
-       return ((cycle_t)hi << 32) | lo;
-}
-
-static void exynos4_frc_resume(struct clocksource *cs)
-{
-       exynos4_mct_frc_start(0, 0);
-}
-
-struct clocksource mct_frc = {
-       .name           = "mct-frc",
-       .rating         = 400,
-       .read           = exynos4_frc_read,
-       .mask           = CLOCKSOURCE_MASK(64),
-       .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-       .resume         = exynos4_frc_resume,
-};
-
-static void __init exynos4_clocksource_init(void)
-{
-       exynos4_mct_frc_start(0, 0);
-
-       if (clocksource_register_hz(&mct_frc, clk_rate))
-               panic("%s: can't register clocksource\n", mct_frc.name);
-}
-
-static void exynos4_mct_comp0_stop(void)
-{
-       unsigned int tcon;
-
-       tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-       tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
-
-       exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
-       exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
-}
-
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
-                                   unsigned long cycles)
-{
-       unsigned int tcon;
-       cycle_t comp_cycle;
-
-       tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-
-       if (mode == CLOCK_EVT_MODE_PERIODIC) {
-               tcon |= MCT_G_TCON_COMP0_AUTO_INC;
-               exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
-       }
-
-       comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
-       exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
-       exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
-
-       exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
-
-       tcon |= MCT_G_TCON_COMP0_ENABLE;
-       exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
-}
-
-static int exynos4_comp_set_next_event(unsigned long cycles,
-                                      struct clock_event_device *evt)
-{
-       exynos4_mct_comp0_start(evt->mode, cycles);
-
-       return 0;
-}
-
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
-                                 struct clock_event_device *evt)
-{
-       exynos4_mct_comp0_stop();
-
-       switch (mode) {
-       case CLOCK_EVT_MODE_PERIODIC:
-               exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
-               break;
-
-       case CLOCK_EVT_MODE_ONESHOT:
-       case CLOCK_EVT_MODE_UNUSED:
-       case CLOCK_EVT_MODE_SHUTDOWN:
-       case CLOCK_EVT_MODE_RESUME:
-               break;
-       }
-}
-
-static struct clock_event_device mct_comp_device = {
-       .name           = "mct-comp",
-       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-       .rating         = 250,
-       .set_next_event = exynos4_comp_set_next_event,
-       .set_mode       = exynos4_comp_set_mode,
-};
-
-static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
-{
-       struct clock_event_device *evt = dev_id;
-
-       exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
-
-       evt->event_handler(evt);
-
-       return IRQ_HANDLED;
-}
-
-static struct irqaction mct_comp_event_irq = {
-       .name           = "mct_comp_irq",
-       .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-       .handler        = exynos4_mct_comp_isr,
-       .dev_id         = &mct_comp_device,
-};
-
-static void exynos4_clockevent_init(void)
-{
-       clk_cnt_per_tick = clk_rate / 2 / HZ;
-
-       clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
-       mct_comp_device.max_delta_ns =
-               clockevent_delta2ns(0xffffffff, &mct_comp_device);
-       mct_comp_device.min_delta_ns =
-               clockevent_delta2ns(0xf, &mct_comp_device);
-       mct_comp_device.cpumask = cpumask_of(0);
-       clockevents_register_device(&mct_comp_device);
-
-       setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
-}
-
-#ifdef CONFIG_LOCAL_TIMERS
-/* Clock event handling */
-static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
-{
-       unsigned long tmp;
-       unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-       void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
-
-       tmp = __raw_readl(addr);
-       if (tmp & mask) {
-               tmp &= ~mask;
-               exynos4_mct_write(tmp, addr);
-       }
-}
-
-static void exynos4_mct_tick_start(unsigned long cycles,
-                                  struct mct_clock_event_device *mevt)
-{
-       unsigned long tmp;
-
-       exynos4_mct_tick_stop(mevt);
-
-       tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
-
-       /* update interrupt count buffer */
-       exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
-
-       /* enable MCT tick interrupt */
-       exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
-
-       tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
-       tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
-              MCT_L_TCON_INTERVAL_MODE;
-       exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
-}
-
-static int exynos4_tick_set_next_event(unsigned long cycles,
-                                      struct clock_event_device *evt)
-{
-       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-
-       exynos4_mct_tick_start(cycles, mevt);
-
-       return 0;
-}
-
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-                                        struct clock_event_device *evt)
-{
-       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-
-       exynos4_mct_tick_stop(mevt);
-
-       switch (mode) {
-       case CLOCK_EVT_MODE_PERIODIC:
-               exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
-               break;
-
-       case CLOCK_EVT_MODE_ONESHOT:
-       case CLOCK_EVT_MODE_UNUSED:
-       case CLOCK_EVT_MODE_SHUTDOWN:
-       case CLOCK_EVT_MODE_RESUME:
-               break;
-       }
-}
-
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
-{
-       struct clock_event_device *evt = mevt->evt;
-
-       /*
-        * This is for supporting oneshot mode.
-        * Mct would generate interrupt periodically
-        * without explicit stopping.
-        */
-       if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
-               exynos4_mct_tick_stop(mevt);
-
-       /* Clear the MCT tick interrupt */
-       if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
-               exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
-               return 1;
-       } else {
-               return 0;
-       }
-}
-
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-{
-       struct mct_clock_event_device *mevt = dev_id;
-       struct clock_event_device *evt = mevt->evt;
-
-       exynos4_mct_tick_clear(mevt);
-
-       evt->event_handler(evt);
-
-       return IRQ_HANDLED;
-}
-
-static struct irqaction mct_tick0_event_irq = {
-       .name           = "mct_tick0_irq",
-       .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-       .handler        = exynos4_mct_tick_isr,
-};
-
-static struct irqaction mct_tick1_event_irq = {
-       .name           = "mct_tick1_irq",
-       .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-       .handler        = exynos4_mct_tick_isr,
-};
-
-static void exynos4_mct_tick_init(struct clock_event_device *evt)
-{
-       struct mct_clock_event_device *mevt;
-       unsigned int cpu = smp_processor_id();
-
-       mevt = this_cpu_ptr(&percpu_mct_tick);
-       mevt->evt = evt;
-
-       mevt->base = EXYNOS4_MCT_L_BASE(cpu);
-       sprintf(mevt->name, "mct_tick%d", cpu);
-
-       evt->name = mevt->name;
-       evt->cpumask = cpumask_of(cpu);
-       evt->set_next_event = exynos4_tick_set_next_event;
-       evt->set_mode = exynos4_tick_set_mode;
-       evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-       evt->rating = 450;
-
-       clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
-       evt->max_delta_ns =
-               clockevent_delta2ns(0x7fffffff, evt);
-       evt->min_delta_ns =
-               clockevent_delta2ns(0xf, evt);
-
-       clockevents_register_device(evt);
-
-       exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
-
-       if (mct_int_type == MCT_INT_SPI) {
-               if (cpu == 0) {
-                       mct_tick0_event_irq.dev_id = mevt;
-                       evt->irq = IRQ_MCT_L0;
-                       setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
-               } else {
-                       mct_tick1_event_irq.dev_id = mevt;
-                       evt->irq = IRQ_MCT_L1;
-                       setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-                       irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
-               }
-       } else {
-               enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
-       }
-}
-
-/* Setup the local clock events for a CPU */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-       exynos4_mct_tick_init(evt);
-
-       return 0;
-}
-
-void local_timer_stop(struct clock_event_device *evt)
-{
-       evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-       if (mct_int_type == MCT_INT_SPI)
-               disable_irq(evt->irq);
-       else
-               disable_percpu_irq(IRQ_MCT_LOCALTIMER);
-}
-#endif /* CONFIG_LOCAL_TIMERS */
-
-static void __init exynos4_timer_resources(void)
-{
-       struct clk *mct_clk;
-       mct_clk = clk_get(NULL, "xtal");
-
-       clk_rate = clk_get_rate(mct_clk);
-
-       if (mct_int_type == MCT_INT_PPI) {
-               int err;
-
-               err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
-                                        exynos4_mct_tick_isr, "MCT",
-                                        &percpu_mct_tick);
-               WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                    IRQ_MCT_LOCALTIMER, err);
-       }
-}
-
-static void __init exynos4_timer_init(void)
-{
-       if (soc_is_exynos4210())
-               mct_int_type = MCT_INT_SPI;
-       else
-               mct_int_type = MCT_INT_PPI;
-
-       exynos4_timer_resources();
-       exynos4_clocksource_init();
-       exynos4_clockevent_init();
-}
-
-struct sys_timer exynos4_timer = {
-       .init           = exynos4_timer_init,
-};
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
deleted file mode 100644 (file)
index 0559540..0000000
+++ /dev/null
@@ -1,225 +0,0 @@
-/* linux/arch/arm/mach-exynos4/platsmp.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
-#include <asm/smp_scu.h>
-#include <asm/unified.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-pmu.h>
-
-#include <plat/cpu.h>
-
-extern unsigned int gic_bank_offset;
-extern void exynos4_secondary_startup(void);
-
-#define CPU1_BOOT_REG          (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                               S5P_INFORM5 : S5P_VA_SYSRAM)
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-
-volatile int __cpuinitdata pen_release = -1;
-
-/*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not.  This is necessary for the hotplug code to work reliably.
- */
-static void write_pen_release(int val)
-{
-       pen_release = val;
-       smp_wmb();
-       __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-       outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-}
-
-static void __iomem *scu_base_addr(void)
-{
-       return (void __iomem *)(S5P_VA_SCU);
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static void __cpuinit exynos4_gic_secondary_init(void)
-{
-       void __iomem *dist_base = S5P_VA_GIC_DIST +
-                               (gic_bank_offset * smp_processor_id());
-       void __iomem *cpu_base = S5P_VA_GIC_CPU +
-                               (gic_bank_offset * smp_processor_id());
-       int i;
-
-       /*
-        * Deal with the banked PPI and SGI interrupts - disable all
-        * PPI interrupts, ensure all SGI interrupts are enabled.
-        */
-       __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-       __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-
-       /*
-        * Set priority on PPI and SGI interrupts
-        */
-       for (i = 0; i < 32; i += 4)
-               __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-
-       __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
-       __raw_writel(1, cpu_base + GIC_CPU_CTRL);
-}
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-       /*
-        * if any interrupts are already enabled for the primary
-        * core (e.g. timer irq), then they will not have been enabled
-        * for us: do so
-        */
-       exynos4_gic_secondary_init();
-
-       /*
-        * let the primary processor know we're out of the
-        * pen, then head off into the C entry point
-        */
-       write_pen_release(-1);
-
-       /*
-        * Synchronise with the boot thread.
-        */
-       spin_lock(&boot_lock);
-       spin_unlock(&boot_lock);
-
-       set_cpu_online(cpu, true);
-}
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-       unsigned long timeout;
-
-       /*
-        * Set synchronisation state between this boot processor
-        * and the secondary one
-        */
-       spin_lock(&boot_lock);
-
-       /*
-        * The secondary processor is waiting to be released from
-        * the holding pen - release it, then wait for it to flag
-        * that it has been released by resetting pen_release.
-        *
-        * Note that "pen_release" is the hardware CPU ID, whereas
-        * "cpu" is Linux's internal ID.
-        */
-       write_pen_release(cpu_logical_map(cpu));
-
-       if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-               __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                            S5P_ARM_CORE1_CONFIGURATION);
-
-               timeout = 10;
-
-               /* wait max 10 ms until cpu1 is on */
-               while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-                       & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-                       if (timeout-- == 0)
-                               break;
-
-                       mdelay(1);
-               }
-
-               if (timeout == 0) {
-                       printk(KERN_ERR "cpu1 power enable failed");
-                       spin_unlock(&boot_lock);
-                       return -ETIMEDOUT;
-               }
-       }
-       /*
-        * Send the secondary CPU a soft interrupt, thereby causing
-        * the boot monitor to read the system wide flags register,
-        * and branch to the address found there.
-        */
-
-       timeout = jiffies + (1 * HZ);
-       while (time_before(jiffies, timeout)) {
-               smp_rmb();
-
-               __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
-                       CPU1_BOOT_REG);
-               gic_raise_softirq(cpumask_of(cpu), 1);
-
-               if (pen_release == -1)
-                       break;
-
-               udelay(10);
-       }
-
-       /*
-        * now the secondary core is starting up let it run its
-        * calibrations, then wait for it to finish
-        */
-       spin_unlock(&boot_lock);
-
-       return pen_release != -1 ? -ENOSYS : 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-
-void __init smp_init_cpus(void)
-{
-       void __iomem *scu_base = scu_base_addr();
-       unsigned int i, ncores;
-
-       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-
-       /* sanity check */
-       if (ncores > nr_cpu_ids) {
-               pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                       ncores, nr_cpu_ids);
-               ncores = nr_cpu_ids;
-       }
-
-       for (i = 0; i < ncores; i++)
-               set_cpu_possible(i, true);
-
-       set_smp_cross_call(gic_raise_softirq);
-}
-
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-
-       scu_enable(scu_base_addr());
-
-       /*
-        * Write the address of secondary startup into the
-        * system-wide flags register. The boot monitor waits
-        * until it receives a soft interrupt, and then the
-        * secondary CPU branches to this address.
-        */
-       __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
-                       CPU1_BOOT_REG);
-}
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
deleted file mode 100644 (file)
index 509a435..0000000
+++ /dev/null
@@ -1,428 +0,0 @@
-/* linux/arch/arm/mach-exynos4/pm.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4210 - Power Management support
- *
- * Based on arch/arm/mach-s3c2410/pm.c
- * Copyright (c) 2006 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/syscore_ops.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/pll.h>
-#include <plat/regs-srom.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-pmu.h>
-#include <mach/pm-core.h>
-#include <mach/pmu.h>
-
-static struct sleep_save exynos4_set_clksrc[] = {
-       { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
-       { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
-       { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
-       { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-       { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
-       { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
-       { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
-       { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
-       { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
-};
-
-static struct sleep_save exynos4210_set_clksrc[] = {
-       { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
-};
-
-static struct sleep_save exynos4_epll_save[] = {
-       SAVE_ITEM(S5P_EPLL_CON0),
-       SAVE_ITEM(S5P_EPLL_CON1),
-};
-
-static struct sleep_save exynos4_vpll_save[] = {
-       SAVE_ITEM(S5P_VPLL_CON0),
-       SAVE_ITEM(S5P_VPLL_CON1),
-};
-
-static struct sleep_save exynos4_core_save[] = {
-       /* GIC side */
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
-       SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
-
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
-
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
-       SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
-
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
-       SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
-
-       /* SROM side */
-       SAVE_ITEM(S5P_SROM_BW),
-       SAVE_ITEM(S5P_SROM_BC0),
-       SAVE_ITEM(S5P_SROM_BC1),
-       SAVE_ITEM(S5P_SROM_BC2),
-       SAVE_ITEM(S5P_SROM_BC3),
-};
-
-static struct sleep_save exynos4_l2cc_save[] = {
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
-
-/* For Cortex-A9 Diagnostic and Power control register */
-static unsigned int save_arm_register[2];
-
-static int exynos4_cpu_suspend(unsigned long arg)
-{
-       outer_flush_all();
-
-       /* issue the standby signal into the pm unit. */
-       cpu_do_idle();
-
-       /* we should never get past here */
-       panic("sleep resumed to originator?");
-}
-
-static void exynos4_pm_prepare(void)
-{
-       u32 tmp;
-
-       s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-       s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-       s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
-       s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
-
-       tmp = __raw_readl(S5P_INFORM1);
-
-       /* Set value of power down register for sleep mode */
-
-       exynos4_sys_powerdown_conf(SYS_SLEEP);
-       __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
-
-       /* ensure at least INFORM0 has the resume address */
-
-       __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
-
-       /* Before enter central sequence mode, clock src register have to set */
-
-       s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
-
-       if (soc_is_exynos4210())
-               s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
-
-}
-
-static int exynos4_pm_add(struct sys_device *sysdev)
-{
-       pm_cpu_prep = exynos4_pm_prepare;
-       pm_cpu_sleep = exynos4_cpu_suspend;
-
-       return 0;
-}
-
-/* This function copy from linux/arch/arm/kernel/smp_scu.c */
-
-void exynos4_scu_enable(void __iomem *scu_base)
-{
-       u32 scu_ctrl;
-
-       scu_ctrl = __raw_readl(scu_base);
-       /* already enabled? */
-       if (scu_ctrl & 1)
-               return;
-
-       scu_ctrl |= 1;
-       __raw_writel(scu_ctrl, scu_base);
-
-       /*
-        * Ensure that the data accessed by CPU0 before the SCU was
-        * initialised is visible to the other CPUs.
-        */
-       flush_cache_all();
-}
-
-static unsigned long pll_base_rate;
-
-static void exynos4_restore_pll(void)
-{
-       unsigned long pll_con, locktime, lockcnt;
-       unsigned long pll_in_rate;
-       unsigned int p_div, epll_wait = 0, vpll_wait = 0;
-
-       if (pll_base_rate == 0)
-               return;
-
-       pll_in_rate = pll_base_rate;
-
-       /* EPLL */
-       pll_con = exynos4_epll_save[0].val;
-
-       if (pll_con & (1 << 31)) {
-               pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
-               p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
-
-               pll_in_rate /= 1000000;
-
-               locktime = (3000 / pll_in_rate) * p_div;
-               lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-
-               __raw_writel(lockcnt, S5P_EPLL_LOCK);
-
-               s3c_pm_do_restore_core(exynos4_epll_save,
-                                       ARRAY_SIZE(exynos4_epll_save));
-               epll_wait = 1;
-       }
-
-       pll_in_rate = pll_base_rate;
-
-       /* VPLL */
-       pll_con = exynos4_vpll_save[0].val;
-
-       if (pll_con & (1 << 31)) {
-               pll_in_rate /= 1000000;
-               /* 750us */
-               locktime = 750;
-               lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-
-               __raw_writel(lockcnt, S5P_VPLL_LOCK);
-
-               s3c_pm_do_restore_core(exynos4_vpll_save,
-                                       ARRAY_SIZE(exynos4_vpll_save));
-               vpll_wait = 1;
-       }
-
-       /* Wait PLL locking */
-
-       do {
-               if (epll_wait) {
-                       pll_con = __raw_readl(S5P_EPLL_CON0);
-                       if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
-                               epll_wait = 0;
-               }
-
-               if (vpll_wait) {
-                       pll_con = __raw_readl(S5P_VPLL_CON0);
-                       if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
-                               vpll_wait = 0;
-               }
-       } while (epll_wait || vpll_wait);
-}
-
-static struct sysdev_driver exynos4_pm_driver = {
-       .add            = exynos4_pm_add,
-};
-
-static __init int exynos4_pm_drvinit(void)
-{
-       struct clk *pll_base;
-       unsigned int tmp;
-
-       s3c_pm_init();
-
-       /* All wakeup disable */
-
-       tmp = __raw_readl(S5P_WAKEUP_MASK);
-       tmp |= ((0xFF << 8) | (0x1F << 1));
-       __raw_writel(tmp, S5P_WAKEUP_MASK);
-
-       pll_base = clk_get(NULL, "xtal");
-
-       if (!IS_ERR(pll_base)) {
-               pll_base_rate = clk_get_rate(pll_base);
-               clk_put(pll_base);
-       }
-
-       return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
-}
-arch_initcall(exynos4_pm_drvinit);
-
-static int exynos4_pm_suspend(void)
-{
-       unsigned long tmp;
-
-       /* Setting Central Sequence Register for power down mode */
-
-       tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-       tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
-       __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
-       if (soc_is_exynos4212()) {
-               tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-               tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
-                        S5P_USE_STANDBYWFE_ISP_ARM);
-               __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-       }
-
-       /* Save Power control register */
-       asm ("mrc p15, 0, %0, c15, c0, 0"
-            : "=r" (tmp) : : "cc");
-       save_arm_register[0] = tmp;
-
-       /* Save Diagnostic register */
-       asm ("mrc p15, 0, %0, c15, c0, 1"
-            : "=r" (tmp) : : "cc");
-       save_arm_register[1] = tmp;
-
-       return 0;
-}
-
-static void exynos4_pm_resume(void)
-{
-       unsigned long tmp;
-
-       /*
-        * If PMU failed while entering sleep mode, WFI will be
-        * ignored by PMU and then exiting cpu_do_idle().
-        * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
-        * in this situation.
-        */
-       tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-       if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
-               tmp |= S5P_CENTRAL_LOWPWR_CFG;
-               __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-               /* No need to perform below restore code */
-               goto early_wakeup;
-       }
-       /* Restore Power control register */
-       tmp = save_arm_register[0];
-       asm volatile ("mcr p15, 0, %0, c15, c0, 0"
-                     : : "r" (tmp)
-                     : "cc");
-
-       /* Restore Diagnostic register */
-       tmp = save_arm_register[1];
-       asm volatile ("mcr p15, 0, %0, c15, c0, 1"
-                     : : "r" (tmp)
-                     : "cc");
-
-       /* For release retention */
-
-       __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
-       __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
-
-       s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-
-       exynos4_restore_pll();
-
-       exynos4_scu_enable(S5P_VA_SCU);
-
-#ifdef CONFIG_CACHE_L2X0
-       s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-       outer_inv_all();
-       /* enable L2X0*/
-       writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
-#endif
-
-early_wakeup:
-       return;
-}
-
-static struct syscore_ops exynos4_pm_syscore_ops = {
-       .suspend        = exynos4_pm_suspend,
-       .resume         = exynos4_pm_resume,
-};
-
-static __init int exynos4_pm_syscore_init(void)
-{
-       register_syscore_ops(&exynos4_pm_syscore_ops);
-       return 0;
-}
-arch_initcall(exynos4_pm_syscore_init);
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
deleted file mode 100644 (file)
index bba48f5..0000000
+++ /dev/null
@@ -1,230 +0,0 @@
-/* linux/arch/arm/mach-exynos4/pmu.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * EXYNOS4210 - CPU PMU(Power Management Unit) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include <mach/regs-clock.h>
-#include <mach/pmu.h>
-
-static struct exynos4_pmu_conf *exynos4_pmu_config;
-
-static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
-       /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
-       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
-       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
-       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
-       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
-       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
-       { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
-       { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
-       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
-       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
-       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
-       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
-       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
-       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
-       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
-       { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
-       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
-       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
-       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
-       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
-       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
-       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
-       { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
-       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
-       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
-       { PMU_TABLE_END,},
-};
-
-static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
-       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
-       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
-       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
-       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
-       { S5P_ISP_ARM_LOWPWR,                   { 0x1, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,     { 0x0, 0x0, 0x0 } },
-       { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,   { 0x0, 0x0, 0x0 } },
-       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
-       { S5P_L2_0_LOWPWR,                      { 0x0, 0x0, 0x3 } },
-       /* XXX_OPTION register should be set other field */
-       { S5P_ARM_L2_0_OPTION,                  { 0x10, 0x10, 0x0 } },
-       { S5P_L2_1_LOWPWR,                      { 0x0, 0x0, 0x3 } },
-       { S5P_ARM_L2_1_OPTION,                  { 0x10, 0x10, 0x0 } },
-       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
-       { S5P_DRAM_FREQ_DOWN_LOWPWR,            { 0x1, 0x1, 0x1 } },
-       { S5P_DDRPHY_DLLOFF_LOWPWR,             { 0x1, 0x1, 0x1 } },
-       { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,        { 0x1, 0x1, 0x1 } },
-       { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_COREBLK_LOWPWR,         { 0x1, 0x1, 0x0 } },
-       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
-       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
-       { S5P_MPLLUSER_SYSCLK_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_ISP_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_ISP_LOWPWR,             { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x0, 0x0 } },
-       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
-       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
-       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
-       { S5P_TOP_BUS_COREBLK_LOWPWR,           { 0x3, 0x0, 0x0 } },
-       { S5P_TOP_RETENTION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x1 } },
-       { S5P_TOP_PWR_COREBLK_LOWPWR,           { 0x3, 0x0, 0x3 } },
-       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
-       { S5P_OSCCLK_GATE_LOWPWR,               { 0x1, 0x0, 0x1 } },
-       { S5P_LOGIC_RESET_COREBLK_LOWPWR,       { 0x1, 0x1, 0x0 } },
-       { S5P_OSCCLK_GATE_COREBLK_LOWPWR,       { 0x1, 0x0, 0x1 } },
-       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_ONENAND_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
-       { S5P_HSI_MEM_LOWPWR,                   { 0x3, 0x0, 0x0 } },
-       { S5P_HSI_MEM_OPTION,                   { 0x10, 0x10, 0x0 } },
-       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_G2D_ACP_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
-       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
-       { S5P_USBOTG_MEM_OPTION,                { 0x10, 0x10, 0x0 } },
-       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_HSMMC_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
-       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_CSSYS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
-       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
-       { S5P_SECSS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
-       { S5P_ROTATOR_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
-       { S5P_ROTATOR_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
-       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
-       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_ISOLATION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x0 } },
-       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
-       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
-       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
-       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
-       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
-       { S5P_GPIO_MODE_COREBLK_LOWPWR,         { 0x1, 0x0, 0x0 } },
-       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
-       { S5P_TOP_ASB_RESET_LOWPWR,             { 0x1, 0x1, 0x1 } },
-       { S5P_TOP_ASB_ISOLATION_LOWPWR,         { 0x1, 0x0, 0x1 } },
-       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
-       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
-       { S5P_ISP_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
-       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
-       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
-       { S5P_CMU_SYSCLK_ISP_LOWPWR,            { 0x1, 0x0, 0x0 } },
-       { S5P_CMU_SYSCLK_GPS_LOWPWR,            { 0x1, 0x0, 0x0 } },
-       { PMU_TABLE_END,},
-};
-
-void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
-{
-       unsigned int i;
-
-       for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
-               __raw_writel(exynos4_pmu_config[i].val[mode],
-                               exynos4_pmu_config[i].reg);
-}
-
-static int __init exynos4_pmu_init(void)
-{
-       exynos4_pmu_config = exynos4210_pmu_config;
-
-       if (soc_is_exynos4210()) {
-               exynos4_pmu_config = exynos4210_pmu_config;
-               pr_info("EXYNOS4210 PMU Initialize\n");
-       } else if (soc_is_exynos4212()) {
-               exynos4_pmu_config = exynos4212_pmu_config;
-               pr_info("EXYNOS4212 PMU Initialize\n");
-       } else {
-               pr_info("EXYNOS4: PMU not supported\n");
-       }
-
-       return 0;
-}
-arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos4/setup-fimc.c b/arch/arm/mach-exynos4/setup-fimc.c
deleted file mode 100644 (file)
index 6a45078..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * Exynos4 camera interface GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/camport.h>
-
-int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
-{
-       u32 gpio8, gpio5;
-       u32 sfn;
-       int ret;
-
-       switch (id) {
-       case S5P_CAMPORT_A:
-               gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
-               gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
-               sfn = S3C_GPIO_SFN(2);
-               break;
-
-       case S5P_CAMPORT_B:
-               gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
-               gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
-               sfn = S3C_GPIO_SFN(3);
-               break;
-
-       default:
-               WARN(1, "Wrong camport id: %d\n", id);
-               return -EINVAL;
-       }
-
-       ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
-       if (ret)
-               return ret;
-
-       return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c
deleted file mode 100644 (file)
index 07a6dbe..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-fimd0.c
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Base Exynos4 FIMD 0 configuration
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/fb.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
-
-#include <mach/map.h>
-
-void exynos4_fimd0_gpio_setup_24bpp(void)
-{
-       unsigned int reg;
-
-       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
-       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
-       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
-       s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
-
-       /*
-        * Set DISPLAY_CONTROL register for Display path selection.
-        *
-        * DISPLAY_CONTROL[1:0]
-        * ---------------------
-        *  00 | MIE
-        *  01 | MDINE
-        *  10 | FIMD : selected
-        *  11 | FIMD
-        */
-       reg = __raw_readl(S3C_VA_SYS + 0x0210);
-       reg |= (1 << 1);
-       __raw_writel(reg, S3C_VA_SYS + 0x0210);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c0.c b/arch/arm/mach-exynos4/setup-i2c0.c
deleted file mode 100644 (file)
index d395bd1..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
-                             S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c
deleted file mode 100644 (file)
index fd7235a..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c1.c
- *
- * Copyright (C) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C1 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
-                             S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c
deleted file mode 100644 (file)
index 2694b19..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c2.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *
- * I2C2 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c2_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
-                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c
deleted file mode 100644 (file)
index 379bd30..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c3.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C3 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c3_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
-                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c
deleted file mode 100644 (file)
index 9f3c048..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c4.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C4 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c4_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c
deleted file mode 100644 (file)
index 77e1a1e..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c5.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C5 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c5_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c
deleted file mode 100644 (file)
index 284d12b..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c6.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C6 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c6_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                             S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c
deleted file mode 100644 (file)
index b7611ee..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c7.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C7 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <plat/iic.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c7_cfg_gpio(struct platform_device *dev)
-{
-       s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
-                             S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
deleted file mode 100644 (file)
index 7862bfb..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-keypad.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * GPIO configuration for Exynos4 KeyPad device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-       /* Keypads can be of various combinations, Just making sure */
-
-       if (rows > 8) {
-               /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-               s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
-                                       S3C_GPIO_PULL_UP);
-
-               /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-               s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
-                                        S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-       } else {
-               /* Set all the necessary GPX2 pins: KP_ROW[x] */
-               s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
-                                       S3C_GPIO_PULL_UP);
-       }
-
-       /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
-       s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
deleted file mode 100644 (file)
index e8d08bf..0000000
+++ /dev/null
@@ -1,152 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
-
-void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-       unsigned int gpio;
-
-       /* Set all the necessary GPK0[0:1] pins to special-function 2 */
-       for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       switch (width) {
-       case 8:
-               for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                       /* Data pin GPK1[3:6] to special-function 3 */
-                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-               }
-       case 4:
-               for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
-                       /* Data pin GPK0[3:6] to special-function 2 */
-                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-               }
-       default:
-               break;
-       }
-
-       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-               s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-}
-
-void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-       unsigned int gpio;
-
-       /* Set all the necessary GPK1[0:1] pins to special-function 2 */
-       for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-               /* Data pin GPK1[3:6] to special-function 2 */
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-               s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-}
-
-void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-       unsigned int gpio;
-
-       /* Set all the necessary GPK2[0:1] pins to special-function 2 */
-       for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       switch (width) {
-       case 8:
-               for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                       /* Data pin GPK3[3:6] to special-function 3 */
-                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-               }
-       case 4:
-               for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
-                       /* Data pin GPK2[3:6] to special-function 2 */
-                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                       s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-               }
-       default:
-               break;
-       }
-
-       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-               s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-}
-
-void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
-{
-       struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-       unsigned int gpio;
-
-       /* Set all the necessary GPK3[0:1] pins to special-function 2 */
-       for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-               /* Data pin GPK3[3:6] to special-function 2 */
-               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-
-       if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-               s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
-               s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
-               s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-       }
-}
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
deleted file mode 100644 (file)
index 92937b4..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *exynos4_hsmmc_clksrcs[4] = {
-       [0] = NULL,
-       [1] = NULL,
-       [2] = "sclk_mmc",       /* mmc_bus */
-       [3] = NULL,
-};
diff --git a/arch/arm/mach-exynos4/setup-usb-phy.c b/arch/arm/mach-exynos4/setup-usb-phy.c
deleted file mode 100644 (file)
index 39aca04..0000000
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/regs-pmu.h>
-#include <mach/regs-usb-phy.h>
-#include <plat/cpu.h>
-#include <plat/usb-phy.h>
-
-static int exynos4_usb_phy1_init(struct platform_device *pdev)
-{
-       struct clk *otg_clk;
-       struct clk *xusbxti_clk;
-       u32 phyclk;
-       u32 rstcon;
-       int err;
-
-       otg_clk = clk_get(&pdev->dev, "otg");
-       if (IS_ERR(otg_clk)) {
-               dev_err(&pdev->dev, "Failed to get otg clock\n");
-               return PTR_ERR(otg_clk);
-       }
-
-       err = clk_enable(otg_clk);
-       if (err) {
-               clk_put(otg_clk);
-               return err;
-       }
-
-       writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
-                       S5P_USBHOST_PHY_CONTROL);
-
-       /* set clock frequency for PLL */
-       phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
-
-       xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-       if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-               switch (clk_get_rate(xusbxti_clk)) {
-               case 12 * MHZ:
-                       phyclk |= CLKSEL_12M;
-                       break;
-               case 24 * MHZ:
-                       phyclk |= CLKSEL_24M;
-                       break;
-               default:
-               case 48 * MHZ:
-                       /* default reference clock */
-                       break;
-               }
-               clk_put(xusbxti_clk);
-       }
-
-       writel(phyclk, EXYNOS4_PHYCLK);
-
-       /* floating prevention logic: disable */
-       writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
-
-       /* set to normal HSIC 0 and 1 of PHY1 */
-       writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
-                       EXYNOS4_PHYPWR);
-
-       /* set to normal standard USB of PHY1 */
-       writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
-
-       /* reset all ports of both PHY and Link */
-       rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
-               PHY1_SWRST_MASK;
-       writel(rstcon, EXYNOS4_RSTCON);
-       udelay(10);
-
-       rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
-       writel(rstcon, EXYNOS4_RSTCON);
-       udelay(80);
-
-       clk_disable(otg_clk);
-       clk_put(otg_clk);
-
-       return 0;
-}
-
-static int exynos4_usb_phy1_exit(struct platform_device *pdev)
-{
-       struct clk *otg_clk;
-       int err;
-
-       otg_clk = clk_get(&pdev->dev, "otg");
-       if (IS_ERR(otg_clk)) {
-               dev_err(&pdev->dev, "Failed to get otg clock\n");
-               return PTR_ERR(otg_clk);
-       }
-
-       err = clk_enable(otg_clk);
-       if (err) {
-               clk_put(otg_clk);
-               return err;
-       }
-
-       writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
-                       EXYNOS4_PHYPWR);
-
-       writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
-                       S5P_USBHOST_PHY_CONTROL);
-
-       clk_disable(otg_clk);
-       clk_put(otg_clk);
-
-       return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-       if (type == S5P_USB_PHY_HOST)
-               return exynos4_usb_phy1_init(pdev);
-
-       return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-       if (type == S5P_USB_PHY_HOST)
-               return exynos4_usb_phy1_exit(pdev);
-
-       return -EINVAL;
-}
index ab16e5568c4c526db5fb90865bd7b1e97609305f..9b9968fa8695b05b0fa4edb3784dc90fd000126f 100644 (file)
@@ -7,7 +7,7 @@
 
 config PLAT_S5P
        bool
-       depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
+       depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
        default y
        select ARM_VIC if !ARCH_EXYNOS4
        select ARM_GIC if ARCH_EXYNOS4
index 7b0a28f73a68a2f47601d6ece39edac6547827b6..a56959e83516706a4fc016888813ec2feb9ad70c 100644 (file)
@@ -75,7 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
                .init_uarts     = exynos4_init_uarts,
-               .init           = exynos4_init,
+               .init           = exynos_init,
                .name           = name_exynos4210,
        }, {
                .idcode         = EXYNOS4212_CPU_ID,
@@ -83,7 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
                .init_uarts     = exynos4_init_uarts,
-               .init           = exynos4_init,
+               .init           = exynos_init,
                .name           = name_exynos4212,
        }, {
                .idcode         = EXYNOS4412_CPU_ID,
@@ -91,7 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
                .init_uarts     = exynos4_init_uarts,
-               .init           = exynos4_init,
+               .init           = exynos_init,
                .name           = name_exynos4412,
        },
 };
index 20d73bf77537574066ad4e21564b67e0f979fbcb..f546e88ebc949db36a41672c9efffd9b13e85171 100644 (file)
@@ -18,8 +18,8 @@ extern void exynos4210_register_clocks(void);
 extern void exynos4212_register_clocks(void);
 extern void exynos4_setup_clocks(void);
 
-#ifdef CONFIG_ARCH_EXYNOS4
-extern  int exynos4_init(void);
+#ifdef CONFIG_ARCH_EXYNOS
+extern  int exynos_init(void);
 extern void exynos4_init_irq(void);
 extern void exynos4_map_io(void);
 extern void exynos4_init_clocks(int xtal);
@@ -31,5 +31,5 @@ extern struct sys_timer exynos4_timer;
 #define exynos4_init_clocks NULL
 #define exynos4_init_uarts NULL
 #define exynos4_map_io NULL
-#define exynos4_init NULL
+#define exynos_init NULL
 #endif