* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
+#include <plat/dsp.h>
+
#include <linux/types.h>
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
{
struct bridge_dev_context *dev_context = dev_ctxt;
u32 temp;
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
u32 clk_cmd;
struct io_mgr *hio_mgr;
u32 ul_load_monitor_timer;
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
mmu = dev_context->dsp_mmu;
/* The device context contains all the mmu setup info from when the
struct bridge_dev_context *dev_context = dev_ctxt;
struct pg_table_attrs *pt_attrs;
u32 dsp_pwr_state;
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
if (dev_context->dw_brd_state == BRD_STOPPED)
return status;
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
+#include <plat/dsp.h>
+
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
#include <dspbridge/drv.h>
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 *constraint_val;
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
constraint_val = (u32 *) (pargs);
/* Read the target value requested by DSP */
u32 opplevel;
struct io_mgr *hio_mgr;
#endif
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
u16 timeout = PWRSTST_TIMEOUT / 10;
u32 pwr_state, target_pwr_state;
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
/* Check if sleep code is valid */
if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
+#include <plat/dsp.h>
+
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 opplevel = 0;
#endif
- struct dspbridge_platform_data *pdata =
+ struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
struct cfg_hostres *resources = dev_context->resources;
int status = 0;
/* TODO -- Remove, once BP defines them */
#define INT_DSP_MMU_IRQ 28
-struct dspbridge_platform_data {
- void (*dsp_set_min_opp) (u8 opp_id);
- u8(*dsp_get_opp) (void);
- void (*cpu_set_freq) (unsigned long f);
- unsigned long (*cpu_get_freq) (void);
- unsigned long mpu_speed[6];
-
- /* functions to write and read PRCM registers */
- void (*dsp_prm_write)(u32, s16 , u16);
- u32 (*dsp_prm_read)(s16 , u16);
- u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
- void (*dsp_cm_write)(u32, s16 , u16);
- u32 (*dsp_cm_read)(s16 , u16);
- u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
-
- u32 phys_mempool_base;
- u32 phys_mempool_size;
-};
-
#define PRCM_VDD1 1
extern struct platform_device *omap_dspbridge_dev;
/* ----------------------------------- Host OS */
+#include <plat/dsp.h>
+
#include <dspbridge/host_os.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#endif
#endif
-struct dspbridge_platform_data *omap_dspbridge_pdata;
+struct omap_dsp_platform_data *omap_dspbridge_pdata;
u32 vdd1_dsp_freq[6][4] = {
{0, 0, 0, 0},
static int dspbridge_scale_notification(struct notifier_block *op,
unsigned long val, void *ptr)
{
- struct dspbridge_platform_data *pdata =
- omap_dspbridge_dev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata =
+ omap_dspbridge_dev->dev.platform_data;
if (CPUFREQ_POSTCHANGE == val && pdata->dsp_get_opp)
pwr_pm_post_scale(PRCM_VDD1, pdata->dsp_get_opp());
*/
static int omap3_bridge_startup(struct platform_device *pdev)
{
- struct dspbridge_platform_data *pdata = pdev->dev.platform_data;
+ struct omap_dsp_platform_data *pdata = pdev->dev.platform_data;
struct drv_data *drv_datap = NULL;
u32 phys_membase, phys_memsize;
int err;