ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Fri, 16 May 2014 12:17:11 +0000 (15:17 +0300)
committerSekhar Nori <nsekhar@ti.com>
Thu, 22 May 2014 05:17:46 +0000 (10:47 +0530)
It is ignored by the edma driver since we are just setting back the default
mapping of TC -> Queue.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arch/arm/mach-davinci/devices-da8xx.c
arch/arm/mach-davinci/dm355.c
arch/arm/mach-davinci/dm365.c
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c

index 56ea41d5f8491307ab89b3178365071cec34ee3d..7f376e54b2662acd6dc8ed2ebb6fb5ab2ab4edab 100644 (file)
@@ -134,13 +134,6 @@ struct platform_device da8xx_serial_device[] = {
        }
 };
 
-static s8 da8xx_queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {-1, -1}
-};
-
 static s8 da8xx_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -148,12 +141,6 @@ static s8 da8xx_queue_priority_mapping[][2] = {
        {-1, -1}
 };
 
-static s8 da850_queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {-1, -1}
-};
-
 static s8 da850_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -166,7 +153,6 @@ static struct edma_soc_info da830_edma_cc0_info = {
        .n_slot                 = 128,
        .n_tc                   = 2,
        .n_cc                   = 1,
-       .queue_tc_mapping       = da8xx_queue_tc_mapping,
        .queue_priority_mapping = da8xx_queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
@@ -182,7 +168,6 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_slot                 = 128,
                .n_tc                   = 2,
                .n_cc                   = 1,
-               .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
                .default_queue          = EVENTQ_1,
        },
@@ -192,7 +177,6 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_slot                 = 128,
                .n_tc                   = 1,
                .n_cc                   = 1,
-               .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
                .default_queue          = EVENTQ_0,
        },
index 07381d8cea6297d25f173460aa3ce849da2c4852..e27f7ff545704cd4dbdf8c83e17cc702480ab15d 100644 (file)
@@ -568,14 +568,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static s8
-queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {-1, -1},
-};
-
 static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
@@ -590,7 +582,6 @@ static struct edma_soc_info edma_cc0_info = {
        .n_slot                 = 128,
        .n_tc                   = 2,
        .n_cc                   = 1,
-       .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
index 08a61b9383337b67b801a4a706814285a936b9aa..88835b0aaead7e34914df898be6ddf9e38f58115 100644 (file)
@@ -852,16 +852,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 };
 
 /* Four Transfer Controllers on DM365 */
-static s8
-dm365_queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {2, 2},
-       {3, 3},
-       {-1, -1},
-};
-
 static s8
 dm365_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
@@ -878,7 +868,6 @@ static struct edma_soc_info edma_cc0_info = {
        .n_slot                 = 256,
        .n_tc                   = 4,
        .n_cc                   = 1,
-       .queue_tc_mapping       = dm365_queue_tc_mapping,
        .queue_priority_mapping = dm365_queue_priority_mapping,
        .default_queue          = EVENTQ_3,
 };
index 5debffba4b24b82e70d9f4eaba8c80c1833afed6..8ea34be879b4bbbab1296f0ddd7281ec588404bd 100644 (file)
@@ -498,14 +498,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static s8
-queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {-1, -1},
-};
-
 static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
@@ -520,7 +512,6 @@ static struct edma_soc_info edma_cc0_info = {
        .n_slot                 = 128,
        .n_tc                   = 2,
        .n_cc                   = 1,
-       .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
index 332d00d24dc205b1ef5a74659eee2aa6af8d96eb..97e90dc5ed43da2817e0a1554c378d4f321b354e 100644 (file)
@@ -532,16 +532,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 /* Four Transfer Controllers on DM646x */
-static s8
-dm646x_queue_tc_mapping[][2] = {
-       /* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {2, 2},
-       {3, 3},
-       {-1, -1},
-};
-
 static s8
 dm646x_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
@@ -558,7 +548,6 @@ static struct edma_soc_info edma_cc0_info = {
        .n_slot                 = 512,
        .n_tc                   = 4,
        .n_cc                   = 1,
-       .queue_tc_mapping       = dm646x_queue_tc_mapping,
        .queue_priority_mapping = dm646x_queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };