#define TDA10048_CONF_C4_1 0x1E
#define TDA10048_CONF_C4_2 0x1F
#define TDA10048_CODE_IN_RAM 0x20
-#define TDA10048_CHANNEL_INFO_1_R 0x22
-#define TDA10048_CHANNEL_INFO_2_R 0x23
+#define TDA10048_CHANNEL_INFO1_R 0x22
+#define TDA10048_CHANNEL_INFO2_R 0x23
#define TDA10048_CHANNEL_INFO1 0x24
#define TDA10048_CHANNEL_INFO2 0x25
#define TDA10048_TIME_ERROR_R 0x26
#define TDA10048_IT_STAT 0x32
#define TDA10048_DSP_AD_LSB 0x3C
#define TDA10048_DSP_AD_MSB 0x3D
-#define TDA10048_DSP_REF_LSB 0x3E
-#define TDA10048_DSP_REF_MSB 0x3F
+#define TDA10048_DSP_REG_LSB 0x3E
+#define TDA10048_DSP_REG_MSB 0x3F
#define TDA10048_CONF_TRISTATE1 0x44
#define TDA10048_CONF_TRISTATE2 0x45
#define TDA10048_CONF_POLARITY 0x46
*ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
+ /* clear the uncorrected TS packets counter when saturated */
+ if (*ucblocks == 0xFFFF)
+ tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
return 0;
}