};
struct intel_connector;
+struct intel_encoder;
struct intel_crtc_config;
struct intel_plane_config;
struct intel_crtc;
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
void (*write_eld)(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
extern void intel_i2c_reset(struct drm_device *dev);
/* intel_opregion.c */
-struct intel_encoder;
#ifdef CONFIG_ACPI
extern int intel_opregion_setup(struct drm_device *dev);
extern void intel_opregion_init(struct drm_device *dev);
}
static void g4x_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
}
static void haswell_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
uint8_t *eld = connector->eld;
uint32_t eldv;
uint32_t tmp;
int len, i;
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ enum pipe pipe = intel_crtc->pipe;
enum port port;
int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
I915_WRITE(aud_cntrl_st2, tmp);
POSTING_READ(aud_cntrl_st2);
- assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
+ assert_pipe_disabled(dev_priv, pipe);
/* Set ELD valid state */
tmp = I915_READ(aud_cntrl_st2);
}
static void ironlake_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc,
+ struct intel_encoder *encoder,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
uint8_t *eld = connector->eld;
uint32_t eldv;
uint32_t tmp;
int aud_config;
int aud_cntl_st;
int aud_cntrl_st2;
- enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ enum pipe pipe = intel_crtc->pipe;
enum port port;
if (HAS_PCH_IBX(connector->dev)) {
DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
if (IS_VALLEYVIEW(connector->dev)) {
- struct intel_encoder *intel_encoder;
struct intel_digital_port *intel_dig_port;
- intel_encoder = intel_attached_encoder(connector);
- intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ intel_dig_port = enc_to_dig_port(&encoder->base);
port = intel_dig_port->port;
} else {
tmp = I915_READ(aud_cntl_st);
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, encoder->crtc, mode);
+ dev_priv->display.write_eld(connector, intel_encoder, mode);
}
/**