Revert "ARCv2: spinlock/rwlock: Reset retry delay when starting a new spin-wait cycle"
authorVineet Gupta <vgupta@synopsys.com>
Tue, 31 May 2016 11:03:29 +0000 (16:33 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Thu, 2 Jun 2016 05:29:23 +0000 (10:59 +0530)
This reverts commit b89aa12c177477e34caa722818536fb5d0bffd76.

The issue was fixed in hardware in HS2.1C release and there are no known
external users of affected RTL so revert the whole delayed retry series !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/include/asm/spinlock.h

index a86cb84fad2a87530ad20cdae29e832db0d5ebe8..5e01bdf968ea1ee135fdce2e2ea5689325c3877c 100644 (file)
@@ -279,7 +279,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
        __asm__ __volatile__(
        "0:     mov     %[delay], 1             \n"
        "1:     llock   %[val], [%[slock]]      \n"
-       "       breq    %[val], %[LOCKED], 0b   \n"     /* spin while LOCKED */
+       "       breq    %[val], %[LOCKED], 1b   \n"     /* spin while LOCKED */
        "       scond   %[LOCKED], [%[slock]]   \n"     /* acquire */
        "       bz      4f                      \n"     /* done */
        "                                       \n"
@@ -358,7 +358,7 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
        __asm__ __volatile__(
        "0:     mov     %[delay], 1             \n"
        "1:     llock   %[val], [%[rwlock]]     \n"
-       "       brls    %[val], %[WR_LOCKED], 0b\n"     /* <= 0: spin while write locked */
+       "       brls    %[val], %[WR_LOCKED], 1b\n"     /* <= 0: spin while write locked */
        "       sub     %[val], %[val], 1       \n"     /* reader lock */
        "       scond   %[val], [%[rwlock]]     \n"
        "       bz      4f                      \n"     /* done */
@@ -427,7 +427,7 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
        __asm__ __volatile__(
        "0:     mov     %[delay], 1             \n"
        "1:     llock   %[val], [%[rwlock]]     \n"
-       "       brne    %[val], %[UNLOCKED], 0b \n"     /* while !UNLOCKED spin */
+       "       brne    %[val], %[UNLOCKED], 1b \n"     /* while !UNLOCKED spin */
        "       mov     %[val], %[WR_LOCKED]    \n"
        "       scond   %[val], [%[rwlock]]     \n"
        "       bz      4f                      \n"