irqchip: Move ARM GIC to drivers/irqchip
authorRob Herring <rob.herring@calxeda.com>
Wed, 21 Nov 2012 03:21:40 +0000 (21:21 -0600)
committerRob Herring <rob.herring@calxeda.com>
Sat, 12 Jan 2013 16:47:31 +0000 (10:47 -0600)
Now that we have drivers/irqchip, move GIC irqchip to drivers/irqchip. This
is necessary to share the GIC with arm and arm64.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
arch/arm/common/Kconfig
arch/arm/common/Makefile
arch/arm/common/gic.c [deleted file]
drivers/irqchip/Kconfig
drivers/irqchip/Makefile
drivers/irqchip/irq-gic.c [new file with mode: 0644]

index 45ceeb0e93e05faaa40195a30d82045f7b6aabe0..7bf52b2b7d3377fd7082450e6ae2537782449d08 100644 (file)
@@ -1,11 +1,3 @@
-config ARM_GIC
-       bool
-       select IRQ_DOMAIN
-       select MULTI_IRQ_HANDLER
-
-config GIC_NON_BANKED
-       bool
-
 config ARM_VIC
        bool
        select IRQ_DOMAIN
index e8a4e58f1b827e26ec0874c2baa53ede8105f70e..4104b821f86085509e9391b686401531fcac0811 100644 (file)
@@ -2,7 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-$(CONFIG_ARM_GIC)          += gic.o
 obj-$(CONFIG_ARM_VIC)          += vic.o
 obj-$(CONFIG_ICST)             += icst.o
 obj-$(CONFIG_SA1111)           += sa1111.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
deleted file mode 100644 (file)
index 90eebfe..0000000
+++ /dev/null
@@ -1,817 +0,0 @@
-/*
- *  linux/arch/arm/common/gic.c
- *
- *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Interrupt architecture for the GIC:
- *
- * o There is one Interrupt Distributor, which receives interrupts
- *   from system devices and sends them to the Interrupt Controllers.
- *
- * o There is one CPU Interface per CPU, which sends interrupts sent
- *   by the Distributor, and interrupts generated locally, to the
- *   associated CPU. The base address of the CPU interface is usually
- *   aliased so that the same address points to different chips depending
- *   on the CPU it is accessed from.
- *
- * Note that IRQs 0-31 are special - they are local to each CPU.
- * As such, the enable set/clear, pending set/clear and active bit
- * registers are banked per-cpu for these sources.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/smp.h>
-#include <linux/cpu_pm.h>
-#include <linux/cpumask.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/slab.h>
-
-#include <asm/irq.h>
-#include <asm/exception.h>
-#include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
-#include <asm/hardware/gic.h>
-
-union gic_base {
-       void __iomem *common_base;
-       void __percpu __iomem **percpu_base;
-};
-
-struct gic_chip_data {
-       union gic_base dist_base;
-       union gic_base cpu_base;
-#ifdef CONFIG_CPU_PM
-       u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
-       u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-       u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-       u32 __percpu *saved_ppi_enable;
-       u32 __percpu *saved_ppi_conf;
-#endif
-       struct irq_domain *domain;
-       unsigned int gic_irqs;
-#ifdef CONFIG_GIC_NON_BANKED
-       void __iomem *(*get_base)(union gic_base *);
-#endif
-};
-
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
-
-/*
- * The GIC mapping of CPU interfaces does not necessarily match
- * the logical CPU numbering.  Let's use a mapping as returned
- * by the GIC itself.
- */
-#define NR_GIC_CPU_IF 8
-static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
-       .irq_eoi        = NULL,
-       .irq_mask       = NULL,
-       .irq_unmask     = NULL,
-       .irq_retrigger  = NULL,
-       .irq_set_type   = NULL,
-       .irq_set_wake   = NULL,
-};
-
-#ifndef MAX_GIC_NR
-#define MAX_GIC_NR     1
-#endif
-
-static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
-
-#ifdef CONFIG_GIC_NON_BANKED
-static void __iomem *gic_get_percpu_base(union gic_base *base)
-{
-       return *__this_cpu_ptr(base->percpu_base);
-}
-
-static void __iomem *gic_get_common_base(union gic_base *base)
-{
-       return base->common_base;
-}
-
-static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
-{
-       return data->get_base(&data->dist_base);
-}
-
-static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
-{
-       return data->get_base(&data->cpu_base);
-}
-
-static inline void gic_set_base_accessor(struct gic_chip_data *data,
-                                        void __iomem *(*f)(union gic_base *))
-{
-       data->get_base = f;
-}
-#else
-#define gic_data_dist_base(d)  ((d)->dist_base.common_base)
-#define gic_data_cpu_base(d)   ((d)->cpu_base.common_base)
-#define gic_set_base_accessor(d,f)
-#endif
-
-static inline void __iomem *gic_dist_base(struct irq_data *d)
-{
-       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-       return gic_data_dist_base(gic_data);
-}
-
-static inline void __iomem *gic_cpu_base(struct irq_data *d)
-{
-       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-       return gic_data_cpu_base(gic_data);
-}
-
-static inline unsigned int gic_irq(struct irq_data *d)
-{
-       return d->hwirq;
-}
-
-/*
- * Routines to acknowledge, disable and enable interrupts
- */
-static void gic_mask_irq(struct irq_data *d)
-{
-       u32 mask = 1 << (gic_irq(d) % 32);
-
-       raw_spin_lock(&irq_controller_lock);
-       writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
-       if (gic_arch_extn.irq_mask)
-               gic_arch_extn.irq_mask(d);
-       raw_spin_unlock(&irq_controller_lock);
-}
-
-static void gic_unmask_irq(struct irq_data *d)
-{
-       u32 mask = 1 << (gic_irq(d) % 32);
-
-       raw_spin_lock(&irq_controller_lock);
-       if (gic_arch_extn.irq_unmask)
-               gic_arch_extn.irq_unmask(d);
-       writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
-       raw_spin_unlock(&irq_controller_lock);
-}
-
-static void gic_eoi_irq(struct irq_data *d)
-{
-       if (gic_arch_extn.irq_eoi) {
-               raw_spin_lock(&irq_controller_lock);
-               gic_arch_extn.irq_eoi(d);
-               raw_spin_unlock(&irq_controller_lock);
-       }
-
-       writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-}
-
-static int gic_set_type(struct irq_data *d, unsigned int type)
-{
-       void __iomem *base = gic_dist_base(d);
-       unsigned int gicirq = gic_irq(d);
-       u32 enablemask = 1 << (gicirq % 32);
-       u32 enableoff = (gicirq / 32) * 4;
-       u32 confmask = 0x2 << ((gicirq % 16) * 2);
-       u32 confoff = (gicirq / 16) * 4;
-       bool enabled = false;
-       u32 val;
-
-       /* Interrupt configuration for SGIs can't be changed */
-       if (gicirq < 16)
-               return -EINVAL;
-
-       if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
-               return -EINVAL;
-
-       raw_spin_lock(&irq_controller_lock);
-
-       if (gic_arch_extn.irq_set_type)
-               gic_arch_extn.irq_set_type(d, type);
-
-       val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
-       if (type == IRQ_TYPE_LEVEL_HIGH)
-               val &= ~confmask;
-       else if (type == IRQ_TYPE_EDGE_RISING)
-               val |= confmask;
-
-       /*
-        * As recommended by the spec, disable the interrupt before changing
-        * the configuration
-        */
-       if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
-               writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
-               enabled = true;
-       }
-
-       writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
-
-       if (enabled)
-               writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
-
-       raw_spin_unlock(&irq_controller_lock);
-
-       return 0;
-}
-
-static int gic_retrigger(struct irq_data *d)
-{
-       if (gic_arch_extn.irq_retrigger)
-               return gic_arch_extn.irq_retrigger(d);
-
-       return -ENXIO;
-}
-
-#ifdef CONFIG_SMP
-static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
-                           bool force)
-{
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;
-       unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
-       u32 val, mask, bit;
-
-       if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
-               return -EINVAL;
-
-       mask = 0xff << shift;
-       bit = gic_cpu_map[cpu] << shift;
-
-       raw_spin_lock(&irq_controller_lock);
-       val = readl_relaxed(reg) & ~mask;
-       writel_relaxed(val | bit, reg);
-       raw_spin_unlock(&irq_controller_lock);
-
-       return IRQ_SET_MASK_OK;
-}
-#endif
-
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
-       int ret = -ENXIO;
-
-       if (gic_arch_extn.irq_set_wake)
-               ret = gic_arch_extn.irq_set_wake(d, on);
-
-       return ret;
-}
-
-#else
-#define gic_set_wake   NULL
-#endif
-
-static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
-{
-       u32 irqstat, irqnr;
-       struct gic_chip_data *gic = &gic_data[0];
-       void __iomem *cpu_base = gic_data_cpu_base(gic);
-
-       do {
-               irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
-               irqnr = irqstat & ~0x1c00;
-
-               if (likely(irqnr > 15 && irqnr < 1021)) {
-                       irqnr = irq_find_mapping(gic->domain, irqnr);
-                       handle_IRQ(irqnr, regs);
-                       continue;
-               }
-               if (irqnr < 16) {
-                       writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
-#ifdef CONFIG_SMP
-                       handle_IPI(irqnr, regs);
-#endif
-                       continue;
-               }
-               break;
-       } while (1);
-}
-
-static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-       struct gic_chip_data *chip_data = irq_get_handler_data(irq);
-       struct irq_chip *chip = irq_get_chip(irq);
-       unsigned int cascade_irq, gic_irq;
-       unsigned long status;
-
-       chained_irq_enter(chip, desc);
-
-       raw_spin_lock(&irq_controller_lock);
-       status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
-       raw_spin_unlock(&irq_controller_lock);
-
-       gic_irq = (status & 0x3ff);
-       if (gic_irq == 1023)
-               goto out;
-
-       cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
-       if (unlikely(gic_irq < 32 || gic_irq > 1020))
-               do_bad_IRQ(cascade_irq, desc);
-       else
-               generic_handle_irq(cascade_irq);
-
- out:
-       chained_irq_exit(chip, desc);
-}
-
-static struct irq_chip gic_chip = {
-       .name                   = "GIC",
-       .irq_mask               = gic_mask_irq,
-       .irq_unmask             = gic_unmask_irq,
-       .irq_eoi                = gic_eoi_irq,
-       .irq_set_type           = gic_set_type,
-       .irq_retrigger          = gic_retrigger,
-#ifdef CONFIG_SMP
-       .irq_set_affinity       = gic_set_affinity,
-#endif
-       .irq_set_wake           = gic_set_wake,
-};
-
-void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
-{
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
-       if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
-               BUG();
-       irq_set_chained_handler(irq, gic_handle_cascade_irq);
-}
-
-static void __init gic_dist_init(struct gic_chip_data *gic)
-{
-       unsigned int i;
-       u32 cpumask;
-       unsigned int gic_irqs = gic->gic_irqs;
-       void __iomem *base = gic_data_dist_base(gic);
-
-       writel_relaxed(0, base + GIC_DIST_CTRL);
-
-       /*
-        * Set all global interrupts to be level triggered, active low.
-        */
-       for (i = 32; i < gic_irqs; i += 16)
-               writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
-
-       /*
-        * Set all global interrupts to this CPU only.
-        */
-       cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
-
-       /*
-        * Set priority on all global interrupts.
-        */
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
-
-       /*
-        * Disable all interrupts.  Leave the PPI and SGIs alone
-        * as these enables are banked registers.
-        */
-       for (i = 32; i < gic_irqs; i += 32)
-               writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
-
-       writel_relaxed(1, base + GIC_DIST_CTRL);
-}
-
-static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
-{
-       void __iomem *dist_base = gic_data_dist_base(gic);
-       void __iomem *base = gic_data_cpu_base(gic);
-       unsigned int cpu_mask, cpu = smp_processor_id();
-       int i;
-
-       /*
-        * Get what the GIC says our CPU mask is.
-        */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
-       cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
-       gic_cpu_map[cpu] = cpu_mask;
-
-       /*
-        * Clear our mask from the other map entries in case they're
-        * still undefined.
-        */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               if (i != cpu)
-                       gic_cpu_map[i] &= ~cpu_mask;
-
-       /*
-        * Deal with the banked PPI and SGI interrupts - disable all
-        * PPI interrupts, ensure all SGI interrupts are enabled.
-        */
-       writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-       writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-
-       /*
-        * Set priority on PPI and SGI interrupts
-        */
-       for (i = 0; i < 32; i += 4)
-               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-
-       writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
-       writel_relaxed(1, base + GIC_CPU_CTRL);
-}
-
-#ifdef CONFIG_CPU_PM
-/*
- * Saves the GIC distributor registers during suspend or idle.  Must be called
- * with interrupts disabled but before powering down the GIC.  After calling
- * this function, no interrupts will be delivered by the GIC, and another
- * platform-specific wakeup source must be enabled.
- */
-static void gic_dist_save(unsigned int gic_nr)
-{
-       unsigned int gic_irqs;
-       void __iomem *dist_base;
-       int i;
-
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
-
-       gic_irqs = gic_data[gic_nr].gic_irqs;
-       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-
-       if (!dist_base)
-               return;
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
-               gic_data[gic_nr].saved_spi_conf[i] =
-                       readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-               gic_data[gic_nr].saved_spi_target[i] =
-                       readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
-               gic_data[gic_nr].saved_spi_enable[i] =
-                       readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
-}
-
-/*
- * Restores the GIC distributor registers during resume or when coming out of
- * idle.  Must be called before enabling interrupts.  If a level interrupt
- * that occured while the GIC was suspended is still present, it will be
- * handled normally, but any edge interrupts that occured will not be seen by
- * the GIC and need to be handled by the platform-specific wakeup source.
- */
-static void gic_dist_restore(unsigned int gic_nr)
-{
-       unsigned int gic_irqs;
-       unsigned int i;
-       void __iomem *dist_base;
-
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
-
-       gic_irqs = gic_data[gic_nr].gic_irqs;
-       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-
-       if (!dist_base)
-               return;
-
-       writel_relaxed(0, dist_base + GIC_DIST_CTRL);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
-               writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
-                       dist_base + GIC_DIST_CONFIG + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-               writel_relaxed(0xa0a0a0a0,
-                       dist_base + GIC_DIST_PRI + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-               writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
-                       dist_base + GIC_DIST_TARGET + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
-               writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
-                       dist_base + GIC_DIST_ENABLE_SET + i * 4);
-
-       writel_relaxed(1, dist_base + GIC_DIST_CTRL);
-}
-
-static void gic_cpu_save(unsigned int gic_nr)
-{
-       int i;
-       u32 *ptr;
-       void __iomem *dist_base;
-       void __iomem *cpu_base;
-
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
-
-       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-
-       if (!dist_base || !cpu_base)
-               return;
-
-       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
-       for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
-               ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
-
-       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
-       for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
-               ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
-
-}
-
-static void gic_cpu_restore(unsigned int gic_nr)
-{
-       int i;
-       u32 *ptr;
-       void __iomem *dist_base;
-       void __iomem *cpu_base;
-
-       if (gic_nr >= MAX_GIC_NR)
-               BUG();
-
-       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-
-       if (!dist_base || !cpu_base)
-               return;
-
-       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
-       for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
-               writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
-
-       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
-       for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
-               writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
-
-       for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
-               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
-
-       writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
-       writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
-}
-
-static int gic_notifier(struct notifier_block *self, unsigned long cmd,        void *v)
-{
-       int i;
-
-       for (i = 0; i < MAX_GIC_NR; i++) {
-#ifdef CONFIG_GIC_NON_BANKED
-               /* Skip over unused GICs */
-               if (!gic_data[i].get_base)
-                       continue;
-#endif
-               switch (cmd) {
-               case CPU_PM_ENTER:
-                       gic_cpu_save(i);
-                       break;
-               case CPU_PM_ENTER_FAILED:
-               case CPU_PM_EXIT:
-                       gic_cpu_restore(i);
-                       break;
-               case CPU_CLUSTER_PM_ENTER:
-                       gic_dist_save(i);
-                       break;
-               case CPU_CLUSTER_PM_ENTER_FAILED:
-               case CPU_CLUSTER_PM_EXIT:
-                       gic_dist_restore(i);
-                       break;
-               }
-       }
-
-       return NOTIFY_OK;
-}
-
-static struct notifier_block gic_notifier_block = {
-       .notifier_call = gic_notifier,
-};
-
-static void __init gic_pm_init(struct gic_chip_data *gic)
-{
-       gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
-               sizeof(u32));
-       BUG_ON(!gic->saved_ppi_enable);
-
-       gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
-               sizeof(u32));
-       BUG_ON(!gic->saved_ppi_conf);
-
-       if (gic == &gic_data[0])
-               cpu_pm_register_notifier(&gic_notifier_block);
-}
-#else
-static void __init gic_pm_init(struct gic_chip_data *gic)
-{
-}
-#endif
-
-#ifdef CONFIG_SMP
-void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
-{
-       int cpu;
-       unsigned long map = 0;
-
-       /* Convert our logical CPU mask into a physical one. */
-       for_each_cpu(cpu, mask)
-               map |= 1 << cpu_logical_map(cpu);
-
-       /*
-        * Ensure that stores to Normal memory are visible to the
-        * other CPUs before issuing the IPI.
-        */
-       dsb();
-
-       /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
-}
-#endif
-
-static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                               irq_hw_number_t hw)
-{
-       if (hw < 32) {
-               irq_set_percpu_devid(irq);
-               irq_set_chip_and_handler(irq, &gic_chip,
-                                        handle_percpu_devid_irq);
-               set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
-       } else {
-               irq_set_chip_and_handler(irq, &gic_chip,
-                                        handle_fasteoi_irq);
-               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-       }
-       irq_set_chip_data(irq, d->host_data);
-       return 0;
-}
-
-static int gic_irq_domain_xlate(struct irq_domain *d,
-                               struct device_node *controller,
-                               const u32 *intspec, unsigned int intsize,
-                               unsigned long *out_hwirq, unsigned int *out_type)
-{
-       if (d->of_node != controller)
-               return -EINVAL;
-       if (intsize < 3)
-               return -EINVAL;
-
-       /* Get the interrupt number and add 16 to skip over SGIs */
-       *out_hwirq = intspec[1] + 16;
-
-       /* For SPIs, we need to add 16 more to get the GIC irq ID number */
-       if (!intspec[0])
-               *out_hwirq += 16;
-
-       *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
-       return 0;
-}
-
-const struct irq_domain_ops gic_irq_domain_ops = {
-       .map = gic_irq_domain_map,
-       .xlate = gic_irq_domain_xlate,
-};
-
-void __init gic_init_bases(unsigned int gic_nr, int irq_start,
-                          void __iomem *dist_base, void __iomem *cpu_base,
-                          u32 percpu_offset, struct device_node *node)
-{
-       irq_hw_number_t hwirq_base;
-       struct gic_chip_data *gic;
-       int gic_irqs, irq_base, i;
-
-       BUG_ON(gic_nr >= MAX_GIC_NR);
-
-       gic = &gic_data[gic_nr];
-#ifdef CONFIG_GIC_NON_BANKED
-       if (percpu_offset) { /* Frankein-GIC without banked registers... */
-               unsigned int cpu;
-
-               gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
-               gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
-               if (WARN_ON(!gic->dist_base.percpu_base ||
-                           !gic->cpu_base.percpu_base)) {
-                       free_percpu(gic->dist_base.percpu_base);
-                       free_percpu(gic->cpu_base.percpu_base);
-                       return;
-               }
-
-               for_each_possible_cpu(cpu) {
-                       unsigned long offset = percpu_offset * cpu_logical_map(cpu);
-                       *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
-                       *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
-               }
-
-               gic_set_base_accessor(gic, gic_get_percpu_base);
-       } else
-#endif
-       {                       /* Normal, sane GIC... */
-               WARN(percpu_offset,
-                    "GIC_NON_BANKED not enabled, ignoring %08x offset!",
-                    percpu_offset);
-               gic->dist_base.common_base = dist_base;
-               gic->cpu_base.common_base = cpu_base;
-               gic_set_base_accessor(gic, gic_get_common_base);
-       }
-
-       /*
-        * Initialize the CPU interface map to all CPUs.
-        * It will be refined as each CPU probes its ID.
-        */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
-
-       /*
-        * For primary GICs, skip over SGIs.
-        * For secondary GICs, skip over PPIs, too.
-        */
-       if (gic_nr == 0 && (irq_start & 31) > 0) {
-               hwirq_base = 16;
-               if (irq_start != -1)
-                       irq_start = (irq_start & ~31) + 16;
-       } else {
-               hwirq_base = 32;
-       }
-
-       /*
-        * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
-        */
-       gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
-       gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
-       gic->gic_irqs = gic_irqs;
-
-       gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-       irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
-       if (IS_ERR_VALUE(irq_base)) {
-               WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-                    irq_start);
-               irq_base = irq_start;
-       }
-       gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
-                                   hwirq_base, &gic_irq_domain_ops, gic);
-       if (WARN_ON(!gic->domain))
-               return;
-
-#ifdef CONFIG_SMP
-       set_smp_cross_call(gic_raise_softirq);
-#endif
-
-       set_handle_irq(gic_handle_irq);
-
-       gic_chip.flags |= gic_arch_extn.flags;
-       gic_dist_init(gic);
-       gic_cpu_init(gic);
-       gic_pm_init(gic);
-}
-
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
-       BUG_ON(gic_nr >= MAX_GIC_NR);
-
-       gic_cpu_init(&gic_data[gic_nr]);
-}
-
-#ifdef CONFIG_OF
-static int gic_cnt __initdata = 0;
-
-int __init gic_of_init(struct device_node *node, struct device_node *parent)
-{
-       void __iomem *cpu_base;
-       void __iomem *dist_base;
-       u32 percpu_offset;
-       int irq;
-
-       if (WARN_ON(!node))
-               return -ENODEV;
-
-       dist_base = of_iomap(node, 0);
-       WARN(!dist_base, "unable to map gic dist registers\n");
-
-       cpu_base = of_iomap(node, 1);
-       WARN(!cpu_base, "unable to map gic cpu registers\n");
-
-       if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
-               percpu_offset = 0;
-
-       gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
-
-       if (parent) {
-               irq = irq_of_parse_and_map(node, 0);
-               gic_cascade_irq(gic_cnt, irq);
-       }
-       gic_cnt++;
-       return 0;
-}
-#endif
index 93dfd8fa66c7a82a7e182db869b6d6fb2c1f515d..98f30b0d531c490afd1d0f4ae425bb2d6ceccf71 100644 (file)
@@ -2,6 +2,14 @@ config IRQCHIP
        def_bool y
        depends on OF_IRQ
 
+config ARM_GIC
+       bool
+       select IRQ_DOMAIN
+       select MULTI_IRQ_HANDLER
+
+config GIC_NON_BANKED
+       bool
+
 config VERSATILE_FPGA_IRQ
        bool
        select IRQ_DOMAIN
index 29b78c9449c8a3ce7a8f4b264e2c5ef26b208db7..f2a9a07a3f123c3b2f6d917448bb1254d5e59d48 100644 (file)
@@ -2,5 +2,6 @@ obj-$(CONFIG_IRQCHIP)                   += irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)             += irq-bcm2835.o
 obj-$(CONFIG_ARCH_SUNXI)               += irq-sunxi.o
-obj-$(CONFIG_VERSATILE_FPGA_IRQ)       += irq-versatile-fpga.o
 obj-$(CONFIG_ARCH_SPEAR3XX)            += spear-shirq.o
+obj-$(CONFIG_ARM_GIC)                  += irq-gic.o
+obj-$(CONFIG_VERSATILE_FPGA_IRQ)       += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
new file mode 100644 (file)
index 0000000..dc511a4
--- /dev/null
@@ -0,0 +1,824 @@
+/*
+ *  linux/arch/arm/common/gic.c
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt architecture for the GIC:
+ *
+ * o There is one Interrupt Distributor, which receives interrupts
+ *   from system devices and sends them to the Interrupt Controllers.
+ *
+ * o There is one CPU Interface per CPU, which sends interrupts sent
+ *   by the Distributor, and interrupts generated locally, to the
+ *   associated CPU. The base address of the CPU interface is usually
+ *   aliased so that the same address points to different chips depending
+ *   on the CPU it is accessed from.
+ *
+ * Note that IRQs 0-31 are special - they are local to each CPU.
+ * As such, the enable set/clear, pending set/clear and active bit
+ * registers are banked per-cpu for these sources.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/smp.h>
+#include <linux/cpu_pm.h>
+#include <linux/cpumask.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+#include <linux/slab.h>
+
+#include <asm/irq.h>
+#include <asm/exception.h>
+#include <asm/smp_plat.h>
+#include <asm/mach/irq.h>
+#include <asm/hardware/gic.h>
+
+#include "irqchip.h"
+
+union gic_base {
+       void __iomem *common_base;
+       void __percpu __iomem **percpu_base;
+};
+
+struct gic_chip_data {
+       union gic_base dist_base;
+       union gic_base cpu_base;
+#ifdef CONFIG_CPU_PM
+       u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+       u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+       u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+       u32 __percpu *saved_ppi_enable;
+       u32 __percpu *saved_ppi_conf;
+#endif
+       struct irq_domain *domain;
+       unsigned int gic_irqs;
+#ifdef CONFIG_GIC_NON_BANKED
+       void __iomem *(*get_base)(union gic_base *);
+#endif
+};
+
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+
+/*
+ * The GIC mapping of CPU interfaces does not necessarily match
+ * the logical CPU numbering.  Let's use a mapping as returned
+ * by the GIC itself.
+ */
+#define NR_GIC_CPU_IF 8
+static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+
+/*
+ * Supported arch specific GIC irq extension.
+ * Default make them NULL.
+ */
+struct irq_chip gic_arch_extn = {
+       .irq_eoi        = NULL,
+       .irq_mask       = NULL,
+       .irq_unmask     = NULL,
+       .irq_retrigger  = NULL,
+       .irq_set_type   = NULL,
+       .irq_set_wake   = NULL,
+};
+
+#ifndef MAX_GIC_NR
+#define MAX_GIC_NR     1
+#endif
+
+static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+
+#ifdef CONFIG_GIC_NON_BANKED
+static void __iomem *gic_get_percpu_base(union gic_base *base)
+{
+       return *__this_cpu_ptr(base->percpu_base);
+}
+
+static void __iomem *gic_get_common_base(union gic_base *base)
+{
+       return base->common_base;
+}
+
+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
+{
+       return data->get_base(&data->dist_base);
+}
+
+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
+{
+       return data->get_base(&data->cpu_base);
+}
+
+static inline void gic_set_base_accessor(struct gic_chip_data *data,
+                                        void __iomem *(*f)(union gic_base *))
+{
+       data->get_base = f;
+}
+#else
+#define gic_data_dist_base(d)  ((d)->dist_base.common_base)
+#define gic_data_cpu_base(d)   ((d)->cpu_base.common_base)
+#define gic_set_base_accessor(d,f)
+#endif
+
+static inline void __iomem *gic_dist_base(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       return gic_data_dist_base(gic_data);
+}
+
+static inline void __iomem *gic_cpu_base(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       return gic_data_cpu_base(gic_data);
+}
+
+static inline unsigned int gic_irq(struct irq_data *d)
+{
+       return d->hwirq;
+}
+
+/*
+ * Routines to acknowledge, disable and enable interrupts
+ */
+static void gic_mask_irq(struct irq_data *d)
+{
+       u32 mask = 1 << (gic_irq(d) % 32);
+
+       raw_spin_lock(&irq_controller_lock);
+       writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
+       if (gic_arch_extn.irq_mask)
+               gic_arch_extn.irq_mask(d);
+       raw_spin_unlock(&irq_controller_lock);
+}
+
+static void gic_unmask_irq(struct irq_data *d)
+{
+       u32 mask = 1 << (gic_irq(d) % 32);
+
+       raw_spin_lock(&irq_controller_lock);
+       if (gic_arch_extn.irq_unmask)
+               gic_arch_extn.irq_unmask(d);
+       writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
+       raw_spin_unlock(&irq_controller_lock);
+}
+
+static void gic_eoi_irq(struct irq_data *d)
+{
+       if (gic_arch_extn.irq_eoi) {
+               raw_spin_lock(&irq_controller_lock);
+               gic_arch_extn.irq_eoi(d);
+               raw_spin_unlock(&irq_controller_lock);
+       }
+
+       writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
+static int gic_set_type(struct irq_data *d, unsigned int type)
+{
+       void __iomem *base = gic_dist_base(d);
+       unsigned int gicirq = gic_irq(d);
+       u32 enablemask = 1 << (gicirq % 32);
+       u32 enableoff = (gicirq / 32) * 4;
+       u32 confmask = 0x2 << ((gicirq % 16) * 2);
+       u32 confoff = (gicirq / 16) * 4;
+       bool enabled = false;
+       u32 val;
+
+       /* Interrupt configuration for SGIs can't be changed */
+       if (gicirq < 16)
+               return -EINVAL;
+
+       if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+               return -EINVAL;
+
+       raw_spin_lock(&irq_controller_lock);
+
+       if (gic_arch_extn.irq_set_type)
+               gic_arch_extn.irq_set_type(d, type);
+
+       val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
+       if (type == IRQ_TYPE_LEVEL_HIGH)
+               val &= ~confmask;
+       else if (type == IRQ_TYPE_EDGE_RISING)
+               val |= confmask;
+
+       /*
+        * As recommended by the spec, disable the interrupt before changing
+        * the configuration
+        */
+       if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+               writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+               enabled = true;
+       }
+
+       writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
+
+       if (enabled)
+               writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+
+       raw_spin_unlock(&irq_controller_lock);
+
+       return 0;
+}
+
+static int gic_retrigger(struct irq_data *d)
+{
+       if (gic_arch_extn.irq_retrigger)
+               return gic_arch_extn.irq_retrigger(d);
+
+       return -ENXIO;
+}
+
+#ifdef CONFIG_SMP
+static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
+                           bool force)
+{
+       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
+       unsigned int shift = (gic_irq(d) % 4) * 8;
+       unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
+       u32 val, mask, bit;
+
+       if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
+               return -EINVAL;
+
+       mask = 0xff << shift;
+       bit = gic_cpu_map[cpu] << shift;
+
+       raw_spin_lock(&irq_controller_lock);
+       val = readl_relaxed(reg) & ~mask;
+       writel_relaxed(val | bit, reg);
+       raw_spin_unlock(&irq_controller_lock);
+
+       return IRQ_SET_MASK_OK;
+}
+#endif
+
+#ifdef CONFIG_PM
+static int gic_set_wake(struct irq_data *d, unsigned int on)
+{
+       int ret = -ENXIO;
+
+       if (gic_arch_extn.irq_set_wake)
+               ret = gic_arch_extn.irq_set_wake(d, on);
+
+       return ret;
+}
+
+#else
+#define gic_set_wake   NULL
+#endif
+
+static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+       u32 irqstat, irqnr;
+       struct gic_chip_data *gic = &gic_data[0];
+       void __iomem *cpu_base = gic_data_cpu_base(gic);
+
+       do {
+               irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+               irqnr = irqstat & ~0x1c00;
+
+               if (likely(irqnr > 15 && irqnr < 1021)) {
+                       irqnr = irq_find_mapping(gic->domain, irqnr);
+                       handle_IRQ(irqnr, regs);
+                       continue;
+               }
+               if (irqnr < 16) {
+                       writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+                       handle_IPI(irqnr, regs);
+#endif
+                       continue;
+               }
+               break;
+       } while (1);
+}
+
+static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+       struct gic_chip_data *chip_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       unsigned int cascade_irq, gic_irq;
+       unsigned long status;
+
+       chained_irq_enter(chip, desc);
+
+       raw_spin_lock(&irq_controller_lock);
+       status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
+       raw_spin_unlock(&irq_controller_lock);
+
+       gic_irq = (status & 0x3ff);
+       if (gic_irq == 1023)
+               goto out;
+
+       cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
+       if (unlikely(gic_irq < 32 || gic_irq > 1020))
+               do_bad_IRQ(cascade_irq, desc);
+       else
+               generic_handle_irq(cascade_irq);
+
+ out:
+       chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip gic_chip = {
+       .name                   = "GIC",
+       .irq_mask               = gic_mask_irq,
+       .irq_unmask             = gic_unmask_irq,
+       .irq_eoi                = gic_eoi_irq,
+       .irq_set_type           = gic_set_type,
+       .irq_retrigger          = gic_retrigger,
+#ifdef CONFIG_SMP
+       .irq_set_affinity       = gic_set_affinity,
+#endif
+       .irq_set_wake           = gic_set_wake,
+};
+
+void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
+{
+       if (gic_nr >= MAX_GIC_NR)
+               BUG();
+       if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
+               BUG();
+       irq_set_chained_handler(irq, gic_handle_cascade_irq);
+}
+
+static void __init gic_dist_init(struct gic_chip_data *gic)
+{
+       unsigned int i;
+       u32 cpumask;
+       unsigned int gic_irqs = gic->gic_irqs;
+       void __iomem *base = gic_data_dist_base(gic);
+
+       writel_relaxed(0, base + GIC_DIST_CTRL);
+
+       /*
+        * Set all global interrupts to be level triggered, active low.
+        */
+       for (i = 32; i < gic_irqs; i += 16)
+               writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+
+       /*
+        * Set all global interrupts to this CPU only.
+        */
+       cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
+       for (i = 32; i < gic_irqs; i += 4)
+               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+
+       /*
+        * Set priority on all global interrupts.
+        */
+       for (i = 32; i < gic_irqs; i += 4)
+               writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+
+       /*
+        * Disable all interrupts.  Leave the PPI and SGIs alone
+        * as these enables are banked registers.
+        */
+       for (i = 32; i < gic_irqs; i += 32)
+               writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+
+       writel_relaxed(1, base + GIC_DIST_CTRL);
+}
+
+static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
+{
+       void __iomem *dist_base = gic_data_dist_base(gic);
+       void __iomem *base = gic_data_cpu_base(gic);
+       unsigned int cpu_mask, cpu = smp_processor_id();
+       int i;
+
+       /*
+        * Get what the GIC says our CPU mask is.
+        */
+       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+       gic_cpu_map[cpu] = cpu_mask;
+
+       /*
+        * Clear our mask from the other map entries in case they're
+        * still undefined.
+        */
+       for (i = 0; i < NR_GIC_CPU_IF; i++)
+               if (i != cpu)
+                       gic_cpu_map[i] &= ~cpu_mask;
+
+       /*
+        * Deal with the banked PPI and SGI interrupts - disable all
+        * PPI interrupts, ensure all SGI interrupts are enabled.
+        */
+       writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+       writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+       /*
+        * Set priority on PPI and SGI interrupts
+        */
+       for (i = 0; i < 32; i += 4)
+               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
+       writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
+       writel_relaxed(1, base + GIC_CPU_CTRL);
+}
+
+#ifdef CONFIG_CPU_PM
+/*
+ * Saves the GIC distributor registers during suspend or idle.  Must be called
+ * with interrupts disabled but before powering down the GIC.  After calling
+ * this function, no interrupts will be delivered by the GIC, and another
+ * platform-specific wakeup source must be enabled.
+ */
+static void gic_dist_save(unsigned int gic_nr)
+{
+       unsigned int gic_irqs;
+       void __iomem *dist_base;
+       int i;
+
+       if (gic_nr >= MAX_GIC_NR)
+               BUG();
+
+       gic_irqs = gic_data[gic_nr].gic_irqs;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+
+       if (!dist_base)
+               return;
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+               gic_data[gic_nr].saved_spi_conf[i] =
+                       readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+               gic_data[gic_nr].saved_spi_target[i] =
+                       readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+               gic_data[gic_nr].saved_spi_enable[i] =
+                       readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+}
+
+/*
+ * Restores the GIC distributor registers during resume or when coming out of
+ * idle.  Must be called before enabling interrupts.  If a level interrupt
+ * that occured while the GIC was suspended is still present, it will be
+ * handled normally, but any edge interrupts that occured will not be seen by
+ * the GIC and need to be handled by the platform-specific wakeup source.
+ */
+static void gic_dist_restore(unsigned int gic_nr)
+{
+       unsigned int gic_irqs;
+       unsigned int i;
+       void __iomem *dist_base;
+
+       if (gic_nr >= MAX_GIC_NR)
+               BUG();
+
+       gic_irqs = gic_data[gic_nr].gic_irqs;
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+
+       if (!dist_base)
+               return;
+
+       writel_relaxed(0, dist_base + GIC_DIST_CTRL);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
+               writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
+                       dist_base + GIC_DIST_CONFIG + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+               writel_relaxed(0xa0a0a0a0,
+                       dist_base + GIC_DIST_PRI + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+               writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
+                       dist_base + GIC_DIST_TARGET + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
+               writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
+                       dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+       writel_relaxed(1, dist_base + GIC_DIST_CTRL);
+}
+
+static void gic_cpu_save(unsigned int gic_nr)
+{
+       int i;
+       u32 *ptr;
+       void __iomem *dist_base;
+       void __iomem *cpu_base;
+
+       if (gic_nr >= MAX_GIC_NR)
+               BUG();
+
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
+
+       if (!dist_base || !cpu_base)
+               return;
+
+       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+       for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+               ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+       for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+               ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
+
+}
+
+static void gic_cpu_restore(unsigned int gic_nr)
+{
+       int i;
+       u32 *ptr;
+       void __iomem *dist_base;
+       void __iomem *cpu_base;
+
+       if (gic_nr >= MAX_GIC_NR)
+               BUG();
+
+       dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+       cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
+
+       if (!dist_base || !cpu_base)
+               return;
+
+       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
+       for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
+               writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+       ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
+       for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
+               writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
+
+       for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
+
+       writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
+       writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
+}
+
+static int gic_notifier(struct notifier_block *self, unsigned long cmd,        void *v)
+{
+       int i;
+
+       for (i = 0; i < MAX_GIC_NR; i++) {
+#ifdef CONFIG_GIC_NON_BANKED
+               /* Skip over unused GICs */
+               if (!gic_data[i].get_base)
+                       continue;
+#endif
+               switch (cmd) {
+               case CPU_PM_ENTER:
+                       gic_cpu_save(i);
+                       break;
+               case CPU_PM_ENTER_FAILED:
+               case CPU_PM_EXIT:
+                       gic_cpu_restore(i);
+                       break;
+               case CPU_CLUSTER_PM_ENTER:
+                       gic_dist_save(i);
+                       break;
+               case CPU_CLUSTER_PM_ENTER_FAILED:
+               case CPU_CLUSTER_PM_EXIT:
+                       gic_dist_restore(i);
+                       break;
+               }
+       }
+
+       return NOTIFY_OK;
+}
+
+static struct notifier_block gic_notifier_block = {
+       .notifier_call = gic_notifier,
+};
+
+static void __init gic_pm_init(struct gic_chip_data *gic)
+{
+       gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
+               sizeof(u32));
+       BUG_ON(!gic->saved_ppi_enable);
+
+       gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
+               sizeof(u32));
+       BUG_ON(!gic->saved_ppi_conf);
+
+       if (gic == &gic_data[0])
+               cpu_pm_register_notifier(&gic_notifier_block);
+}
+#else
+static void __init gic_pm_init(struct gic_chip_data *gic)
+{
+}
+#endif
+
+#ifdef CONFIG_SMP
+void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
+{
+       int cpu;
+       unsigned long map = 0;
+
+       /* Convert our logical CPU mask into a physical one. */
+       for_each_cpu(cpu, mask)
+               map |= 1 << cpu_logical_map(cpu);
+
+       /*
+        * Ensure that stores to Normal memory are visible to the
+        * other CPUs before issuing the IPI.
+        */
+       dsb();
+
+       /* this always happens on GIC0 */
+       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+}
+#endif
+
+static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                               irq_hw_number_t hw)
+{
+       if (hw < 32) {
+               irq_set_percpu_devid(irq);
+               irq_set_chip_and_handler(irq, &gic_chip,
+                                        handle_percpu_devid_irq);
+               set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
+       } else {
+               irq_set_chip_and_handler(irq, &gic_chip,
+                                        handle_fasteoi_irq);
+               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+       }
+       irq_set_chip_data(irq, d->host_data);
+       return 0;
+}
+
+static int gic_irq_domain_xlate(struct irq_domain *d,
+                               struct device_node *controller,
+                               const u32 *intspec, unsigned int intsize,
+                               unsigned long *out_hwirq, unsigned int *out_type)
+{
+       if (d->of_node != controller)
+               return -EINVAL;
+       if (intsize < 3)
+               return -EINVAL;
+
+       /* Get the interrupt number and add 16 to skip over SGIs */
+       *out_hwirq = intspec[1] + 16;
+
+       /* For SPIs, we need to add 16 more to get the GIC irq ID number */
+       if (!intspec[0])
+               *out_hwirq += 16;
+
+       *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+       return 0;
+}
+
+const struct irq_domain_ops gic_irq_domain_ops = {
+       .map = gic_irq_domain_map,
+       .xlate = gic_irq_domain_xlate,
+};
+
+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
+                          void __iomem *dist_base, void __iomem *cpu_base,
+                          u32 percpu_offset, struct device_node *node)
+{
+       irq_hw_number_t hwirq_base;
+       struct gic_chip_data *gic;
+       int gic_irqs, irq_base, i;
+
+       BUG_ON(gic_nr >= MAX_GIC_NR);
+
+       gic = &gic_data[gic_nr];
+#ifdef CONFIG_GIC_NON_BANKED
+       if (percpu_offset) { /* Frankein-GIC without banked registers... */
+               unsigned int cpu;
+
+               gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
+               gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
+               if (WARN_ON(!gic->dist_base.percpu_base ||
+                           !gic->cpu_base.percpu_base)) {
+                       free_percpu(gic->dist_base.percpu_base);
+                       free_percpu(gic->cpu_base.percpu_base);
+                       return;
+               }
+
+               for_each_possible_cpu(cpu) {
+                       unsigned long offset = percpu_offset * cpu_logical_map(cpu);
+                       *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
+                       *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
+               }
+
+               gic_set_base_accessor(gic, gic_get_percpu_base);
+       } else
+#endif
+       {                       /* Normal, sane GIC... */
+               WARN(percpu_offset,
+                    "GIC_NON_BANKED not enabled, ignoring %08x offset!",
+                    percpu_offset);
+               gic->dist_base.common_base = dist_base;
+               gic->cpu_base.common_base = cpu_base;
+               gic_set_base_accessor(gic, gic_get_common_base);
+       }
+
+       /*
+        * Initialize the CPU interface map to all CPUs.
+        * It will be refined as each CPU probes its ID.
+        */
+       for (i = 0; i < NR_GIC_CPU_IF; i++)
+               gic_cpu_map[i] = 0xff;
+
+       /*
+        * For primary GICs, skip over SGIs.
+        * For secondary GICs, skip over PPIs, too.
+        */
+       if (gic_nr == 0 && (irq_start & 31) > 0) {
+               hwirq_base = 16;
+               if (irq_start != -1)
+                       irq_start = (irq_start & ~31) + 16;
+       } else {
+               hwirq_base = 32;
+       }
+
+       /*
+        * Find out how many interrupts are supported.
+        * The GIC only supports up to 1020 interrupt sources.
+        */
+       gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
+       gic_irqs = (gic_irqs + 1) * 32;
+       if (gic_irqs > 1020)
+               gic_irqs = 1020;
+       gic->gic_irqs = gic_irqs;
+
+       gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+       irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
+       if (IS_ERR_VALUE(irq_base)) {
+               WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+                    irq_start);
+               irq_base = irq_start;
+       }
+       gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
+                                   hwirq_base, &gic_irq_domain_ops, gic);
+       if (WARN_ON(!gic->domain))
+               return;
+
+#ifdef CONFIG_SMP
+       set_smp_cross_call(gic_raise_softirq);
+#endif
+
+       set_handle_irq(gic_handle_irq);
+
+       gic_chip.flags |= gic_arch_extn.flags;
+       gic_dist_init(gic);
+       gic_cpu_init(gic);
+       gic_pm_init(gic);
+}
+
+void __cpuinit gic_secondary_init(unsigned int gic_nr)
+{
+       BUG_ON(gic_nr >= MAX_GIC_NR);
+
+       gic_cpu_init(&gic_data[gic_nr]);
+}
+
+#ifdef CONFIG_OF
+static int gic_cnt __initdata = 0;
+
+int __init gic_of_init(struct device_node *node, struct device_node *parent)
+{
+       void __iomem *cpu_base;
+       void __iomem *dist_base;
+       u32 percpu_offset;
+       int irq;
+
+       if (WARN_ON(!node))
+               return -ENODEV;
+
+       dist_base = of_iomap(node, 0);
+       WARN(!dist_base, "unable to map gic dist registers\n");
+
+       cpu_base = of_iomap(node, 1);
+       WARN(!cpu_base, "unable to map gic cpu registers\n");
+
+       if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+               percpu_offset = 0;
+
+       gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
+
+       if (parent) {
+               irq = irq_of_parse_and_map(node, 0);
+               gic_cascade_irq(gic_cnt, irq);
+       }
+       gic_cnt++;
+       return 0;
+}
+IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
+IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
+IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
+
+#endif