[NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
[NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
[NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
- [Configuration_Memory_Clear] = { 0x1a4, 2 },
- [ADC_FIFO_Clear] = { 0x1a6, 2 },
- [DAC_FIFO_Clear] = { 0x1a8, 2 },
+ [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
+ [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
+ [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
[AO_Output_Control_Register] = { 0x1ac, 2 },
[AI_Mode_3_Register] = { 0x1ae, 2 },
};
if (i == timeout)
dev_err(dev->class_dev, "FIFO flush timeout\n");
} else {
- ni_stc_writew(dev, 1, ADC_FIFO_Clear);
+ ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
if (devpriv->is_625x) {
ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
unsigned int nsamples;
/* reset fifo */
- ni_stc_writew(dev, 1, DAC_FIFO_Clear);
+ ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
if (devpriv->is_6xxx)
ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
for (i = 0; i < NI_TIMEOUT; ++i) {
if (!(ni_stc_readw(dev, AI_Status_1_Register) &
AI_FIFO_Empty_St)) {
- ni_stc_writew(dev, 1, ADC_FIFO_Clear);
+ ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
return;
}
udelay(1);
unsigned int dither;
unsigned range_code;
- ni_stc_writew(dev, 1, Configuration_Memory_Clear);
+ ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
if ((list[0] & CR_ALT_SOURCE)) {
unsigned bypass_bits;
devpriv->changain_state = 0;
}
- ni_stc_writew(dev, 1, Configuration_Memory_Clear);
+ ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
/* Set up Calibration mode if required */
if (devpriv->is_6143) {
NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
#ifdef PCIDMA
- ni_stc_writew(dev, 1, DAC_FIFO_Clear);
+ ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
if (devpriv->is_6xxx)
ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
ret = ni_ao_setup_MITE_dma(dev);
#define NISTC_RTSI_BOARD_REG 81
+#define NISTC_CFG_MEM_CLR_REG 82
+#define NISTC_ADC_FIFO_CLR_REG 83
+#define NISTC_DAC_FIFO_CLR_REG 84
+#define NISTC_WR_STROBE3_REG 85
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define AO_BC_Save_Registers 18
#define AO_UC_Save_Registers 20
-#define Write_Strobe_0_Register 82
-#define Write_Strobe_1_Register 83
-#define Write_Strobe_2_Register 84
-#define Write_Strobe_3_Register 85
-
#define AO_Output_Control_Register 86
#define AO_External_Gate_Enable _bit15
#define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
#define Window_Address 0x00
#define Window_Data 0x02
-#define Configuration_Memory_Clear 82
-#define ADC_FIFO_Clear 83
-#define DAC_FIFO_Clear 84
-
/* i/o port offsets */
/* 8 bit registers */