static struct at91_gpio_bank at91cap9_gpio[] = {
{
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOA,
+ .regbase = AT91CAP9_BASE_PIOA,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOB,
+ .regbase = AT91CAP9_BASE_PIOB,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOC,
+ .regbase = AT91CAP9_BASE_PIOC,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOD,
+ .regbase = AT91CAP9_BASE_PIOD,
.clock = &pioABCD_clk,
}
};
static struct at91_gpio_bank at91rm9200_gpio[] = {
{
.id = AT91RM9200_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91RM9200_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91RM9200_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91RM9200_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91RM9200_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91RM9200_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91RM9200_ID_PIOD,
- .offset = AT91_PIOD,
+ .regbase = AT91RM9200_BASE_PIOD,
.clock = &pioD_clk,
}
};
static struct at91_gpio_bank at91sam9260_gpio[] = {
{
.id = AT91SAM9260_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9260_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9260_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9260_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9260_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9260_BASE_PIOC,
.clock = &pioC_clk,
}
};
static struct at91_gpio_bank at91sam9261_gpio[] = {
{
.id = AT91SAM9261_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9261_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9261_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9261_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9261_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9261_BASE_PIOC,
.clock = &pioC_clk,
}
};
static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9263_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9263_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9263_BASE_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9263_BASE_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOE,
+ .regbase = AT91SAM9263_BASE_PIOE,
.clock = &pioCDE_clk,
}
};
static struct at91_gpio_bank at91sam9g45_gpio[] = {
{
.id = AT91SAM9G45_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9G45_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9G45_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9G45_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9G45_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9G45_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9G45_BASE_PIOD,
.clock = &pioDE_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
- .offset = AT91_PIOE,
+ .regbase = AT91SAM9G45_BASE_PIOE,
.clock = &pioDE_clk,
}
};
static struct at91_gpio_bank at91sam9rl_gpio[] = {
{
.id = AT91SAM9RL_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9RL_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9RL_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9RL_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9RL_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9RL_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91SAM9RL_ID_PIOD,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9RL_BASE_PIOD,
.clock = &pioD_clk,
}
};
struct at91_gpio_bank {
unsigned short id; /* peripheral ID */
- unsigned long offset; /* offset from system peripheral base */
+ unsigned long regbase; /* offset from system peripheral base */
struct clk *clock; /* associated clock */
};
extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
at91_gpio->bank = &data[i];
at91_gpio->chip.base = PIN_BASE + i * 32;
- at91_gpio->regbase = at91_gpio->bank->offset +
- (void __iomem *)AT91_VA_BASE_SYS;
+
+ at91_gpio->regbase = ioremap(at91_gpio->bank->regbase, 512);
+ if (!at91_gpio->regbase) {
+ pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
+ continue;
+ }
/* enable PIO controller's clock */
clk_enable(at91_gpio->bank->clock);
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
(0xfffffd50 - AT91_BASE_SYS) : \
(0xfffffd60 - AT91_BASE_SYS))
+#define AT91CAP9_BASE_PIOA 0xfffff200
+#define AT91CAP9_BASE_PIOB 0xfffff400
+#define AT91CAP9_BASE_PIOC 0xfffff600
+#define AT91CAP9_BASE_PIOD 0xfffff800
+
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
-#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
+#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
+#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
+#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
+#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
#define AT91_USART2 AT91RM9200_BASE_US2
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9260_BASE_PIOA 0xfffff400
+#define AT91SAM9260_BASE_PIOB 0xfffff600
+#define AT91SAM9260_BASE_PIOC 0xfffff800
+
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1
#define AT91_USART2 AT91SAM9260_BASE_US2
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9261_BASE_PIOA 0xfffff400
+#define AT91SAM9261_BASE_PIOB 0xfffff600
+#define AT91SAM9261_BASE_PIOC 0xfffff800
+
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1
#define AT91_USART2 AT91SAM9261_BASE_US2
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
+#define AT91SAM9263_BASE_PIOA 0xfffff200
+#define AT91SAM9263_BASE_PIOB 0xfffff400
+#define AT91SAM9263_BASE_PIOC 0xfffff600
+#define AT91SAM9263_BASE_PIOD 0xfffff800
+#define AT91SAM9263_BASE_PIOE 0xfffffa00
+
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
+#define AT91SAM9G45_BASE_PIOA 0xfffff200
+#define AT91SAM9G45_BASE_PIOB 0xfffff400
+#define AT91SAM9G45_BASE_PIOC 0xfffff600
+#define AT91SAM9G45_BASE_PIOD 0xfffff800
+#define AT91SAM9G45_BASE_PIOE 0xfffffa00
+
#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1
#define AT91_USART2 AT91SAM9G45_BASE_US2
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
+#define AT91SAM9RL_BASE_PIOA 0xfffff400
+#define AT91SAM9RL_BASE_PIOB 0xfffff600
+#define AT91SAM9RL_BASE_PIOC 0xfffff800
+#define AT91SAM9RL_BASE_PIOD 0xfffffa00
+
#define AT91_USART0 AT91SAM9RL_BASE_US0
#define AT91_USART1 AT91SAM9RL_BASE_US1
#define AT91_USART2 AT91SAM9RL_BASE_US2
projects / GitHub / LineageOS / G12 / android_kernel_amlogic_linux-4.9.git / commitdiff