drm/amdgpu:implement cond_exec for gfx8

when MCBP enabled for gfx8, the cond_exec must also
be implemented, otherwise there will be odds to meet
cross engine (ce and me) deadlock when world switch
happens.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 423ed68c2e529b218e5be9884e3692ae82c31eec..0050b09d588367199037d21a7c17778f18fea50e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6781,6 +6781,34 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
                        (flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
 }
 
+static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
+{
+       unsigned ret;
+
+       amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
+       amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+       amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+       amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
+       ret = ring->wptr & ring->buf_mask;
+       amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
+       return ret;
+}
+
+static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
+{
+       unsigned cur;
+
+       BUG_ON(offset > ring->buf_mask);
+       BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+       cur = (ring->wptr & ring->buf_mask) - 1;
+       if (likely(cur > offset))
+               ring->ring[offset] = cur - offset;
+       else
+               ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
+}
+
+
 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 {
        struct amdgpu_device *adev = ring->adev;
@@ -7070,6 +7098,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .emit_switch_buffer = gfx_v8_ring_emit_sb,
        .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
+       .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
+       .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
 };
 
 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {