drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 1c0b1aaaa48bb04c8dbf899660811df35cee8f0d..a42f483767e75510d02d834fdc724c3b83baa6ec 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -71,7 +71,6 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
        uint64_t value;
-       uint32_t tmp;
 
        /* Disable AGP. */
        WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
@@ -98,10 +97,8 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
                     (u32)((u64)adev->dummy_page.addr >> 44));
 
-       tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
-       tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
-                           ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
-       WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
+       WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
+                      ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 }
 
 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
@@ -278,9 +275,7 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 
        /* Setup L2 cache */
-       tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
-       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
-       WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
+       WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
        WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 }