Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
};
+#define SCLK_DEEP_SLEEP_MASK 0x8
+
struct amdgpu_ps {
u32 caps; /* vbios flags */
u32 class; /* vbios flags */
pi->pcie_dpm_key_disabled = 0;
pi->thermal_sclk_dpm_enabled = 0;
- if (amdgpu_sclk_deep_sleep_en)
+ if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;
pi->caps_td_ramping = true;
pi->caps_tcp_ramping = true;
}
- if (amdgpu_sclk_deep_sleep_en)
+ if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;
pi->caps_tcp_ramping = true;
}
- if (amdgpu_sclk_deep_sleep_en)
+ if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;