#define TC_3W_POLL_MAX_TRY_CNT 5
static u8 MAC_REG_TABLE[][2] = {
- /*PAGA 0: */
- /* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() */
- /* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185(). */
- /* 0x1F0~0x1F8 set in MacConfig_85BASIC() */
+ /*
+ * PAGE 0:
+ * 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in
+ * HwConfigureRTL8185()
+ * 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
+ * 0x1F0~0x1F8 set in MacConfig_85BASIC()
+ */
{0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
{0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
{0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
{0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
{0xff, 0x00},
- /*PAGE 1: */
- /* For Flextronics system Logo PCIHCT failure: */
- /* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1 */
+ /*
+ * PAGE 1:
+ * For Flextronics system Logo PCIHCT failure:
+ * 0x1C4~0x1CD set no-zero value to avoid PCI configuration
+ * space 0x45[7]=1
+ */
{0x5e, 0x01},
{0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
{0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
{0x82, 0xFF}, {0x83, 0x03},
- {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
- {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22}, /* lzm add 080826 */
+ /* lzm add 080826 */
+ {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22},
+ /* lzm add 080826 */
+ {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},
{0xe2, 0x00},
{0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
{0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
- /* PAGA 0: */
+ /* PAGE 0: */
{0x5e, 0x00}, {0x9f, 0x03}
};
static u8 ZEBRA_AGC[] = {
0,
- 0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
- 0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
- 0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
- 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
- 0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
- 0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
- 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
+ 0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76,
+ 0x75, 0x74, 0x73, 0x72, 0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A,
+ 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x48, 0x47, 0x46, 0x45,
+ 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
+ 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
+ 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16, 0x17, 0x17, 0x18, 0x18,
+ 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
+ 0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22,
+ 0x22, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
+ 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
};
static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
static void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
{
write_nic_byte(dev, offset, data);
- read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
+ /*
+ * To make sure write operation is completed,
+ * 2005.11.09, by rcnjko.
+ */
+ read_nic_byte(dev, offset);
}
static void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
{
write_nic_word(dev, offset, data);
- read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
+ /*
+ * To make sure write operation is completed,
+ * 2005.11.09, by rcnjko.
+ */
+ read_nic_word(dev, offset);
}
static void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
/*
* 071010, rcnjko:
- * The critical section is only BB read/write race condition.
- * Assumption:
- * 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
+ * The critical section is only BB read/write race
+ * condition. Assumption:
+ * 1. We assume NO one will access BB at DIRQL, otherwise,
+ * system will crash for
* acquiring the spinlock in such context.
* 2. PlatformIOWrite4Byte() MUST NOT be recursive.
*/
}
for (idx = 0; idx < 3; idx++)
- PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
+ PlatformIOWrite1Byte(dev, offset+1+idx,
+ ((u8 *)&dataBytes)[idx]);
write_nic_byte(dev, offset, cmdByte);
/* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
} else {
write_nic_dword(dev, offset, data);
- read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
+ /*
+ * To make sure write operation is completed, 2005.11.09,
+ * by rcnjko.
+ */
+ read_nic_dword(dev, offset);
}
}
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bool bAntennaSwitched = true;
- u8 ant_diversity_offset = 0x00; /* 0x00 = disabled, 0x80 = enabled */
+ /* 0x00 = disabled, 0x80 = enabled */
+ u8 ant_diversity_offset = 0x00;
- /* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
+ /*
+ * printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n",
+ * DefaultAnt, bAntDiversity);
+ */
/* Threshold for antenna diversity. */
write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
/* Config CCK RX antenna. */
write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
- write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset); /* Reg01 : 47 | ant_diversity_offset */
+
+ /* Reg01 : 47 | ant_diversity_offset */
+ write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
/* Config OFDM RX antenna. */
write_phy_ofdm(dev, 0x0D, 0x54); /* Reg0d : 54 */
- write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset); /* Reg18 : 32 */
+ /* Reg18 : 32 */
+ write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
} else { /* main Antenna */
/* Mac register, main antenna */
write_nic_byte(dev, ANTSEL, 0x03);
/* Config CCK RX antenna. */
write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
- write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset); /* Reg01 : 47 */
+ /* Reg01 : 47 */
+ write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
/* Config OFDM RX antenna. */
write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
- write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset); /*Reg18 : 32 */
+ /*Reg18 : 32 */
+ write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
}
priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
return bAntennaSwitched;
RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
-/* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
+/*
+ * Don't write RF23/RF24 to make a difference between 87S C cut and D cut.
+ * asked by SD3 stevenl.
+ */
RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
if (d_cut) {
RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
- RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); /* RX LO buffer */
+ /* RX LO buffer */
+ RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1);
} else {
RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
- RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); /* RX LO buffer */
+ /* RX LO buffer */
+ RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1);
}
RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /* 203, 343 */
RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); /* 400 */
- RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); /* switch to reg16-reg30, and HSSI disable 137 */
+ /* switch to reg16-reg30, and HSSI disable 137 */
+ RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
- RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); /* Z4 synthesizer loop filter setting, 392 */
+ /* Z4 synthesizer loop filter setting, 392 */
+ RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
- RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); /* switch to reg0-reg15, and HSSI disable */
+ /* switch to reg0-reg15, and HSSI disable */
+ RF_WriteReg(dev, 0x00, 0x0037); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
- RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); /* CBC on, Tx Rx disable, High gain */
+ /* CBC on, Tx Rx disable, High gain */
+ RF_WriteReg(dev, 0x04, 0x0160); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
- RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); /* Z4 setted channel 1 */
+ /* Z4 setted channel 1 */
+ RF_WriteReg(dev, 0x07, 0x0080); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); /* LC calibration */
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
- RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); /* switch to reg16-reg30 137, and HSSI disable 137 */
+ /* switch to reg16-reg30 137, and HSSI disable 137 */
+ RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
mdelay(10); /* Deay 10 ms. */ /* 0xfd */
RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
/*
* enable crystal calibration.
* RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
- * (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
- * (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
+ * (2)PA Pwr delay timer[15:14], default: 2.4us,
+ * set BIT15=0
+ * (3)RF signal on/off when calibration[13], default: on,
+ * set BIT13=0.
* So we should minus 4 BITs offset.
*/
- RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
+ RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) |
+ (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
- (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
+ (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) |
+ BIT11 | BIT9);
} else {
/* using default value. Xin=6, Xout=6. */
RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
}
-
- RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); /* switch to reg0-reg15, and HSSI enable */
- RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); /* Rx BB start calibration, 00c//+edward */
- RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); /* temperature meter off */
+ /* switch to reg0-reg15, and HSSI enable */
+ RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1);
+ /* Rx BB start calibration, 00c//+edward */
+ RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
+ /* temperature meter off */
+ RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);
RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); /* Rx mode */
mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
- RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); /* Rx mode*/ /*+edward */
- RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); /* Rx mode*/ /*+edward */
- RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); /* Rx mode*/ /*+edward */
- RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); /* Rx mode*/ /*+edward */
- RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); /* Rx mode*/ /*+edward */
+ /* Rx mode*/ /*+edward */
+ RF_WriteReg(dev, 0x00, 0x0197); mdelay(1);
+ /* Rx mode*/ /*+edward */
+ RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
+ /* Rx mode*/ /*+edward */
+ RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);
+ /* Rx mode*/ /*+edward */
+ RF_WriteReg(dev, 0x01, 0x0000); mdelay(1);
+ /* Rx mode*/ /*+edward */
+ RF_WriteReg(dev, 0x02, 0x0000); mdelay(1);
/* power save parameters. */
u1b24E = read_nic_byte(dev, 0x24E);
write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
- /*=============================================================================
+ /*======================================================================
*
- *===========================================================================
+ *======================================================================
* CCKCONF.TXT
- *===========================================================================
+ *======================================================================
*
* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
* CCK reg0x00[7]=1'b1 :power saving for TX (default)
* CCK reg0x00[6]=1'b1: power saving for RX (default)
- * CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
+ * CCK reg0x06[4]=1'b1: turn off channel estimation related
+ * circuits if not doing channel estimation.
* CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
* CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
*/
/*
- *===========================================================================
+ *======================================================================
* AGC.txt
- *===========================================================================
+ *======================================================================
*/
write_phy_ofdm(dev, 0x00, 0x12);
PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
/*
- *===========================================================================
+ *======================================================================
*
- *===========================================================================
+ *======================================================================
* OFDMCONF.TXT
- *===========================================================================
+ *======================================================================
*/
for (i = 0; i < 60; i++) {
}
/*
- *===========================================================================
+ *======================================================================
* by amy for antenna
- *===========================================================================
+ *======================================================================
+ */
+ /*
+ * Config Sw/Hw Combinational Antenna Diversity. Added by Roger,
+ * 2008.02.26.
*/
- /* Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26. */
- SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
+ SetAntennaConfig87SE(dev, priv->bDefaultAntenna1,
+ priv->bSwAntennaDiverity);
}
/* lzm add 080826 */
if (priv->eRFPowerState != eRfOn) {
/* Don't access BB/RF under disable PLL situation.
- * RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
+ * RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain -
+ * pHalData->eRFPowerState!=eRfOn\n"));
* Back to the original state
*/
priv->InitialGain = priv->InitialGainBackUp;
u4bRfReg = RF_ReadReg(dev, 0x02);
/* Enable Thermal meter indication. */
- RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
+ RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
}
static void PhyConfig8185(struct net_device *dev)
priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
/* RF config */
ZEBRA_Config_85BASIC_HardCode(dev);
- /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. */
+ /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce,
+ * 2007-06-06.
+ */
if (priv->bDigMechanism) {
if (priv->InitialGain == 0)
priv->InitialGain = 4;
}
/*
- * Enable thermal meter indication to implement TxPower tracking on 87SE.
- * We initialize thermal meter here to avoid unsuccessful configuration.
- * Added by Roger, 2007.12.11.
+ * Enable thermal meter indication to implement TxPower tracking
+ * on 87SE. We initialize thermal meter here to avoid unsuccessful
+ * configuration. Added by Roger, 2007.12.11.
*/
if (priv->bTxPowerTrack)
InitTxPwrTracking87SE(dev);
static void HwConfigureRTL8185(struct net_device *dev)
{
- /* RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. */
+ /*
+ * RTL8185_TODO: Determine Retrylimit, TxAGC,
+ * AutoRateFallback control.
+ */
u8 bUNIVERSAL_CONTROL_RL = 0;
u8 bUNIVERSAL_CONTROL_AGC = 1;
u8 bUNIVERSAL_CONTROL_ANT = 1;
if (bAUTO_RATE_FALLBACK_CTL) {
val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
- /* <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. */
+ /* <RJ_TODO_8185B> We shall set up the ARFR according
+ * to user's setting.
+ */
PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
}
write_nic_byte(dev, RATE_FALLBACK, val8);
static void MacConfig_85BASIC_HardCode(struct net_device *dev)
{
/*
- *==========================================================================
+ *======================================================================
* MACREG.TXT
- *==========================================================================
+ *======================================================================
*/
int nLinesRead = 0;
u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
}
- /* ============================================================================ */
+ /* ================================================================= */
}
static void MacConfig_85BASIC(struct net_device *dev)
u8 u1DA;
MacConfig_85BASIC_HardCode(dev);
- /* ============================================================================ */
+ /* ================================================================= */
/* Follow TID_AC_MAP of WMac. */
write_nic_word(dev, TID_AC_MAP, 0xfa50);
- /* Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. */
+ /* Interrupt Migration, Jong suggested we use set 0x0000 first,
+ * 2005.12.14, by rcnjko.
+ */
write_nic_word(dev, IntMig, 0x0000);
/* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
/* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
- /* power save parameter based on "87SE power save parameters 20071127.doc", as follow. */
+
+ /*
+ * power save parameter based on
+ * "87SE power save parameters 20071127.doc", as follow.
+ */
/* Enable DA10 TX power saving */
u1DA = read_nic_byte(dev, PHYPR);
/*
* <RJ_TODO_8185B>
- * TODO: We still don't know how to set up these registers, just follow WMAC to
- * verify 8185B FPAG.
+ * TODO: We still don't know how to set up these registers,
+ * just follow WMAC to verify 8185B FPAG.
*
* <RJ_TODO_8185B>
* Jong said CWmin/CWmax register are not functional in 8185B,
- * so we shall fill channel access realted register into AC parameter registers,
+ * so we shall fill channel access realted register into AC
+ * parameter registers,
* even in nQBss.
*/
- ChnlAccessSetting->SIFS_Timer = 0x22; /* Suggested by Jong, 2005.12.08. */
+
+ /* Suggested by Jong, 2005.12.08. */
+ ChnlAccessSetting->SIFS_Timer = 0x22;
ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko. */
ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko. */
- ChnlAccessSetting->EIFS_Timer = 0x5B; /* Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
+ /*
+ * Suggested by wcchu, it is the default value of EIFS register,
+ * 2005.12.08.
+ */
+ ChnlAccessSetting->EIFS_Timer = 0x5B;
ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko. */
ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko. */
write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
- write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); /* Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. */
+ /*
+ * Rewrited from directly use PlatformEFIOWrite1Byte(),
+ * by Annie, 2006-03-29.
+ */
+ write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);
write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
- write_nic_byte(dev, AckTimeOutReg, 0x5B); /* <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
+ /*
+ * <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS
+ * register, 2005.12.08.
+ */
+ write_nic_byte(dev, AckTimeOutReg, 0x5B);
for (eACI = 0; eACI < AC_MAX; eACI++) {
write_nic_byte(dev, ACM_CONTROL, 0);
u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
if ((btWirelessMode & btSupportedWirelessMode) == 0) {
- /* Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko. */
+ /*
+ * Don't switch to unsupported wireless mode, 2006.02.15,
+ * by rcnjko.
+ */
DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
btWirelessMode, btSupportedWirelessMode);
return;
/*
* 2. Swtich band: RF or BB specific actions,
- * for example, refresh tables in omc8255, or change initial gain if necessary.
- * Nothing to do for Zebra to switch band.
- * Update current wireless mode if we switch to specified band successfully.
+ * for example, refresh tables in omc8255, or change initial gain if
+ * necessary. Nothing to do for Zebra to switch band. Update current
+ * wireless mode if we switch to specified band successfully.
*/
ieee->mode = (WIRELESS_MODE)btWirelessMode;
else if (ieee->mode == WIRELESS_MODE_G)
DMESG("WIRELESS_MODE_G\n");
- ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
+ ActUpdateChannelAccessSetting( dev, ieee->mode,
+ &priv->ChannelAccessSetting);
}
void rtl8185b_irq_enable(struct net_device *dev)
/*
* Stop Beacon.
*
- * Vista add a Adhoc profile, HW radio off until OID_DOT11_RESET_REQUEST
- * Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
- * Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
+ * Vista add a Adhoc profile, HW radio off until
+ * OID_DOT11_RESET_REQUEST Driver would set MSR=NO_LINK,
+ * then HW Radio ON, MgntQueue Stuck. Because Bcn DMA isn't
+ * complete, mgnt queue would stuck until Bcn packet send.
*
* Disable Beacon Queue Own bit, suggested by jong
*/
* Commented out by rcnjko, 2005.01.27:
* I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
*
- * 2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
+ * 2004/09/15, kcwu, the key should be cleared, or the new
+ * handshaking will not success
*
- * In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
- * 2004.10.11, by rcnjko.
+ * In WPA WPA2 need to Clear all key ... because new key will set
+ * after new handshaking. 2004.10.11, by rcnjko.
*/
- MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid, asRsn);
+ MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid,
+ asRsn);
priv->ieee80211->state = IEEE80211_NOLINK;
}
if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
/*
- * We clear key here instead of MgntDisconnectAP() because that
- * MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
- * e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
- * used to handle disassociation related things to AP, e.g. send Disassoc
- * frame to AP. 2005.01.27, by rcnjko.
+ * We clear key here instead of MgntDisconnectAP()
+ * because that MgntActSet_802_11_DISASSOCIATE()
+ * is an interface called by OS, e.g.
+ * OID_802_11_DISASSOCIATE in Windows while as
+ * MgntDisconnectAP() is used to handle
+ * disassociation related things to AP, e.g. send
+ * Disassoc frame to AP. 2005.01.27, by rcnjko.
*/
MgntDisconnectAP(dev, asRsn);
}
/*
* Description:
* Chang RF Power State.
- * Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
+ * Note that, only MgntActSet_RF_State() is allowed to set
+ * HW_VAR_RF_STATE.
*
* Assumption:
* PASSIVE LEVEL.
*/
-static bool SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
+static bool SetRFPowerState(struct net_device *dev,
+ RT_RF_POWER_STATE eRFPowerState)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bool bResult = false;
return bResult;
}
-bool MgntActSet_RF_State(struct net_device *dev, RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
+bool MgntActSet_RF_State(struct net_device *dev,
+ RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bool bActionAllowed = false;
u16 RFWaitCounter = 0;
unsigned long flag;
/*
- * Prevent the race condition of RF state change. By Bruce, 2007-11-28.
- * Only one thread can change the RF state at one time, and others should wait to be executed.
+ * Prevent the race condition of RF state change. By Bruce,
+ * 2007-11-28. Only one thread can change the RF state at one time,
+ * and others should wait to be executed.
*/
while (true) {
spin_lock_irqsave(&priv->rf_ps_lock, flag);
RFWaitCounter++;
udelay(1000); /* 1 ms */
- /* Wait too long, return FALSE to avoid to be stuck here. */
+ /*
+ * Wait too long, return FALSE to avoid
+ * to be stuck here.
+ */
if (RFWaitCounter > 1000) { /* 1sec */
printk("MgntActSet_RF_State(): Wait too long to set RF\n");
/* TODO: Reset RF state? */
switch (StateToSet) {
case eRfOn:
/*
- * Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
- * the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
+ * Turn On RF no matter the IPS setting because we need to
+ * update the RF state to Ndis under Vista, or the Windows
+ * does not allow the driver to perform site survey any
+ * more. By Bruce, 2007-10-02.
*/
priv->RfOffReason &= (~ChangeSource);
priv->RfOffReason = 0;
bActionAllowed = true;
- if (rtState == eRfOff && ChangeSource >= RF_CHANGE_BY_HW)
+ if (rtState == eRfOff &&
+ ChangeSource >= RF_CHANGE_BY_HW)
bConnectBySSID = true;
}
break;
if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
/*
* 060808, Annie:
- * Disconnect to current BSS when radio off. Asked by QuanTa.
+ * Disconnect to current BSS when radio off.
+ * Asked by QuanTa.
*
- * Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
- * because we do NOT need to set ssid to dummy ones.
+ * Calling MgntDisconnect() instead of
+ * MgntActSet_802_11_DISASSOCIATE(), because
+ * we do NOT need to set ssid to dummy ones.
*/
MgntDisconnect(dev, disas_lv_ss);
- /* Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. */
+ /*
+ * Clear content of bssDesc[] and bssDesc4Query[]
+ * to avoid reporting old bss to UI.
+ */
}
priv->RfOffReason |= ChangeSource;
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
/*
- * This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
- * is really scheduled.
- * The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
- * previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
- * blocks the IPS procedure of switching RF.
+ * This flag "bSwRfProcessing", indicates the status of IPS
+ * procedure, should be set if the IPS workitem is really
+ * scheduled. The old code, sets this flag before scheduling the
+ * IPS workitem and however, at the same time the previous IPS
+ * workitem did not end yet, fails to schedule the current
+ * workitem. Thus, bSwRfProcessing blocks the IPS procedure of
+ * switching RF.
*/
priv->bSwRfProcessing = true;
MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
/*
- * To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
+ * To solve CAM values miss in RF OFF, rewrite CAM values after
+ * RF ON. By Bruce, 2007-09-20.
*/
priv->bSwRfProcessing = false;
/*
* Do not enter IPS in the following conditions:
- * (1) RF is already OFF or Sleep
- * (2) bSwRfProcessing (indicates the IPS is still under going)
- * (3) Connected (only disconnected can trigger IPS)
- * (4) IBSS (send Beacon)
+ * (1) RF is already OFF or
+ * Sleep (2) bSwRfProcessing (indicates the IPS is still
+ * under going) (3) Connected (only disconnected can
+ * trigger IPS)(4) IBSS (send Beacon)
* (5) AP mode (send Beacon)
*/
if (rtState == eRfOn && !priv->bSwRfProcessing
RT_RF_POWER_STATE rtState;
if (priv->bInactivePs) {
rtState = priv->eRFPowerState;
- if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
+ if ((rtState == eRfOff || rtState == eRfSleep) &&
+ !priv->bSwRfProcessing
+ && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
priv->eInactivePowerState = eRfOn;
InactivePowerSave(dev);
}
HwConfigureRTL8185(dev);
write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
- write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); /* default network type to 'No Link' */
+ /* default network type to 'No Link' */
+ write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);
write_nic_word(dev, BcnItv, 100);
write_nic_word(dev, AtimWnd, 2);
PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
write_nic_byte(dev, WPA_CONFIG, 0);
MacConfig_85BASIC(dev);
- /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. */
+ /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07,
+ * by rcnjko.
+ */
/* BT_DEMO_BOARD type */
PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
/*
- *---------------------------------------------------------------------------
+ *---------------------------------------------------------------------
* Set up PHY related.
- *---------------------------------------------------------------------------
+ *---------------------------------------------------------------------
*/
/* Enable Config3.PARAM_En to revise AnaaParm. */
write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
tmpu8 = read_nic_byte(dev, CONFIG3);
write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
/* Turn on Analog power. */
- /* Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. */
+ /* Asked for by William, otherwise, MAC 3-wire can't work,
+ * 2006.06.27, by rcnjko.
+ */
write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
write_nic_word(dev, ANAPARAM3, 0x0010);
/*
* We assume RegWirelessMode has already been initialized before,
* however, we has to validate the wireless mode here and provide a
- * reasonable initialized value if necessary. 2005.01.13, by rcnjko.
+ * reasonable initialized value if necessary. 2005.01.13,
+ * by rcnjko.
*/
SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
if ((ieee->mode != WIRELESS_MODE_B) &&
MgntActSet_RF_State(dev, eRfOn, 0);
}
/*
- * If inactive power mode is enabled, disable rf while in disconnected state.
+ * If inactive power mode is enabled, disable rf while in
+ * disconnected state.
*/
if (priv->bInactivePs)
MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
- /* ----------------------------------------------------------------------------- */
+ /* ----------------------------------------------------------------- */
rtl8185b_irq_enable(dev);
}
if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
- priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
+ priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF |
+ RCR_APWRMGT | RCR_AICV;
if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff