drm/i915: Move FBC stuff to intel_fbc.c
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Mon, 8 Dec 2014 16:09:10 +0000 (14:09 -0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 10 Dec 2014 16:47:20 +0000 (17:47 +0100)
No functional changes. This is just the begin of a FBC rework.

v2 (Paulo):
  - Revert intel_fbc_init() changed parameter.
  - Revert set_no_fbc_reason() rename.
  - Rebase.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_fbc.c [new file with mode: 0644]
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_sprite.c

index e4083e41a600e264599cf607a5f419d60fd21383..3cf70a61b44f396680b8abf1f10be2248a6c2a2b 100644 (file)
@@ -47,6 +47,7 @@ i915-y += intel_renderstate_gen6.o \
 i915-y += intel_audio.o \
          intel_bios.o \
          intel_display.o \
+         intel_fbc.o \
          intel_fifo_underrun.o \
          intel_frontbuffer.o \
          intel_modes.o \
index 95dfa2dd35b921756ec5643372534098da516d80..c74dc946cbf63d0c8be6698d9fbc1e99a39383a7 100644 (file)
@@ -2963,9 +2963,6 @@ extern void intel_modeset_setup_hw_state(struct drm_device *dev,
                                         bool force_restore);
 extern void i915_redisable_vga(struct drm_device *dev);
 extern void i915_redisable_vga_power_on(struct drm_device *dev);
-extern bool intel_fbc_enabled(struct drm_device *dev);
-extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
-extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
index dfe661743398b1c90e0f9dc4b25ff6e9d551985c..1e4999dd3ed5400710979e0f4614c31dc950cde0 100644 (file)
@@ -264,7 +264,7 @@ static void i915_restore_display(struct drm_device *dev)
        }
 
        /* only restore FBC info on the platform that supports FBC*/
-       intel_disable_fbc(dev);
+       intel_fbc_disable(dev);
 
        /* restore FBC interval */
        if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
index d5153a4f90fec4e3db3ab59c05e8c16a872967dd..841af6c1f50be9d41f407413be31fd34a8c2560b 100644 (file)
@@ -4201,7 +4201,7 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
        hsw_enable_ips(intel_crtc);
 
        mutex_lock(&dev->struct_mutex);
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
        mutex_unlock(&dev->struct_mutex);
 
        /*
@@ -4223,7 +4223,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
        intel_crtc_wait_for_pending_flips(crtc);
 
        if (dev_priv->fbc.plane == plane)
-               intel_disable_fbc(dev);
+               intel_fbc_disable(dev);
 
        hsw_disable_ips(intel_crtc);
 
@@ -4527,7 +4527,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
        intel_update_watermarks(crtc);
 
        mutex_lock(&dev->struct_mutex);
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
        mutex_unlock(&dev->struct_mutex);
 }
 
@@ -4584,7 +4584,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
        intel_update_watermarks(crtc);
 
        mutex_lock(&dev->struct_mutex);
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
        mutex_unlock(&dev->struct_mutex);
 
        if (intel_crtc_to_shared_dpll(intel_crtc))
@@ -5189,7 +5189,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
        intel_update_watermarks(crtc);
 
        mutex_lock(&dev->struct_mutex);
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
        mutex_unlock(&dev->struct_mutex);
 }
 
@@ -8950,7 +8950,7 @@ static void intel_unpin_work_fn(struct work_struct *__work)
        drm_gem_object_unreference(&work->pending_flip_obj->base);
        drm_gem_object_unreference(&work->old_fb_obj->base);
 
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
 
        if (work->flip_queued_req)
                i915_gem_request_assign(&work->flip_queued_req, NULL);
@@ -9747,7 +9747,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        i915_gem_track_fb(work->old_fb_obj, obj,
                          INTEL_FRONTBUFFER_PRIMARY(pipe));
 
-       intel_disable_fbc(dev);
+       intel_fbc_disable(dev);
        intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
        mutex_unlock(&dev->struct_mutex);
 
@@ -11816,7 +11816,7 @@ intel_commit_primary_plane(struct drm_plane *plane,
                    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
                    dev_priv->fbc.plane == intel_crtc->plane &&
                    intel_plane->rotation != BIT(DRM_ROTATE_0)) {
-                       intel_disable_fbc(dev);
+                       intel_fbc_disable(dev);
                }
 
                if (state->visible) {
@@ -11851,7 +11851,7 @@ intel_commit_primary_plane(struct drm_plane *plane,
                intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
 
                mutex_lock(&dev->struct_mutex);
-               intel_update_fbc(dev);
+               intel_fbc_update(dev);
                mutex_unlock(&dev->struct_mutex);
        }
 }
@@ -13050,7 +13050,7 @@ void intel_modeset_init(struct drm_device *dev)
        intel_setup_outputs(dev);
 
        /* Just in case the BIOS is doing something questionable. */
-       intel_disable_fbc(dev);
+       intel_fbc_disable(dev);
 
        drm_modeset_lock_all(dev);
        intel_modeset_setup_hw_state(dev, false);
@@ -13567,7 +13567,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
        intel_unregister_dsm_handler();
 
-       intel_disable_fbc(dev);
+       intel_fbc_disable(dev);
 
        ironlake_teardown_rc6(dev);
 
index 61a88fa6997831c15c8cf861d821e0c68188b390..588b618ab668fc699153bcc5f655d4ec6d1a8bf6 100644 (file)
@@ -1063,6 +1063,13 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 }
 #endif
 
+/* intel_fbc.c */
+bool intel_fbc_enabled(struct drm_device *dev);
+void intel_fbc_update(struct drm_device *dev);
+void intel_fbc_init(struct drm_i915_private *dev_priv);
+void intel_fbc_disable(struct drm_device *dev);
+void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
+
 /* intel_hdmi.c */
 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
@@ -1169,8 +1176,6 @@ void intel_update_sprite_watermarks(struct drm_plane *plane,
                                    bool enabled, bool scaled);
 void intel_init_pm(struct drm_device *dev);
 void intel_pm_setup(struct drm_device *dev);
-bool intel_fbc_enabled(struct drm_device *dev);
-void intel_update_fbc(struct drm_device *dev);
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_teardown(void);
 void intel_init_gt_powersave(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
new file mode 100644 (file)
index 0000000..f1eeb86
--- /dev/null
@@ -0,0 +1,675 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "intel_drv.h"
+#include "i915_drv.h"
+
+/* FBC, or Frame Buffer Compression, is a technique employed to compress the
+ * framebuffer contents in-memory, aiming at reducing the required bandwidth
+ * during in-memory transfers and, therefore, reduce the power packet.
+ *
+ * The benefits of FBC are mostly visible with solid backgrounds and
+ * variation-less patterns.
+ *
+ * FBC-related functionality can be enabled by the means of the
+ * i915.i915_fbc_enable parameter
+ */
+
+static void i8xx_fbc_disable(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 fbc_ctl;
+
+       dev_priv->fbc.enabled = false;
+
+       /* Disable compression */
+       fbc_ctl = I915_READ(FBC_CONTROL);
+       if ((fbc_ctl & FBC_CTL_EN) == 0)
+               return;
+
+       fbc_ctl &= ~FBC_CTL_EN;
+       I915_WRITE(FBC_CONTROL, fbc_ctl);
+
+       /* Wait for compressing bit to clear */
+       if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
+               DRM_DEBUG_KMS("FBC idle timed out\n");
+               return;
+       }
+
+       DRM_DEBUG_KMS("disabled FBC\n");
+}
+
+static void i8xx_fbc_enable(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_framebuffer *fb = crtc->primary->fb;
+       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       int cfb_pitch;
+       int i;
+       u32 fbc_ctl;
+
+       dev_priv->fbc.enabled = true;
+
+       cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
+       if (fb->pitches[0] < cfb_pitch)
+               cfb_pitch = fb->pitches[0];
+
+       /* FBC_CTL wants 32B or 64B units */
+       if (IS_GEN2(dev))
+               cfb_pitch = (cfb_pitch / 32) - 1;
+       else
+               cfb_pitch = (cfb_pitch / 64) - 1;
+
+       /* Clear old tags */
+       for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
+               I915_WRITE(FBC_TAG + (i * 4), 0);
+
+       if (IS_GEN4(dev)) {
+               u32 fbc_ctl2;
+
+               /* Set it up... */
+               fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
+               fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
+               I915_WRITE(FBC_CONTROL2, fbc_ctl2);
+               I915_WRITE(FBC_FENCE_OFF, crtc->y);
+       }
+
+       /* enable it... */
+       fbc_ctl = I915_READ(FBC_CONTROL);
+       fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
+       fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
+       if (IS_I945GM(dev))
+               fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
+       fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
+       fbc_ctl |= obj->fence_reg;
+       I915_WRITE(FBC_CONTROL, fbc_ctl);
+
+       DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
+                     cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
+}
+
+static bool i8xx_fbc_enabled(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
+}
+
+static void g4x_fbc_enable(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_framebuffer *fb = crtc->primary->fb;
+       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       u32 dpfc_ctl;
+
+       dev_priv->fbc.enabled = true;
+
+       dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
+       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
+               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
+       else
+               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
+       dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
+
+       I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
+
+       /* enable it... */
+       I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
+
+       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
+}
+
+static void g4x_fbc_disable(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 dpfc_ctl;
+
+       dev_priv->fbc.enabled = false;
+
+       /* Disable compression */
+       dpfc_ctl = I915_READ(DPFC_CONTROL);
+       if (dpfc_ctl & DPFC_CTL_EN) {
+               dpfc_ctl &= ~DPFC_CTL_EN;
+               I915_WRITE(DPFC_CONTROL, dpfc_ctl);
+
+               DRM_DEBUG_KMS("disabled FBC\n");
+       }
+}
+
+static bool g4x_fbc_enabled(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
+}
+
+static void snb_fbc_blit_update(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 blt_ecoskpd;
+
+       /* Make sure blitter notifies FBC of writes */
+
+       /* Blitter is part of Media powerwell on VLV. No impact of
+        * his param in other platforms for now */
+       gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
+
+       blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
+       blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
+               GEN6_BLITTER_LOCK_SHIFT;
+       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
+       blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
+       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
+       blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
+                        GEN6_BLITTER_LOCK_SHIFT);
+       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
+       POSTING_READ(GEN6_BLITTER_ECOSKPD);
+
+       gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
+}
+
+static void ilk_fbc_enable(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_framebuffer *fb = crtc->primary->fb;
+       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       u32 dpfc_ctl;
+
+       dev_priv->fbc.enabled = true;
+
+       dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
+       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
+               dev_priv->fbc.threshold++;
+
+       switch (dev_priv->fbc.threshold) {
+       case 4:
+       case 3:
+               dpfc_ctl |= DPFC_CTL_LIMIT_4X;
+               break;
+       case 2:
+               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
+               break;
+       case 1:
+               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
+               break;
+       }
+       dpfc_ctl |= DPFC_CTL_FENCE_EN;
+       if (IS_GEN5(dev))
+               dpfc_ctl |= obj->fence_reg;
+
+       I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
+       I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
+       /* enable it... */
+       I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
+
+       if (IS_GEN6(dev)) {
+               I915_WRITE(SNB_DPFC_CTL_SA,
+                          SNB_CPU_FENCE_ENABLE | obj->fence_reg);
+               I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
+               snb_fbc_blit_update(dev);
+       }
+
+       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
+}
+
+static void ilk_fbc_disable(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 dpfc_ctl;
+
+       dev_priv->fbc.enabled = false;
+
+       /* Disable compression */
+       dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+       if (dpfc_ctl & DPFC_CTL_EN) {
+               dpfc_ctl &= ~DPFC_CTL_EN;
+               I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+
+               DRM_DEBUG_KMS("disabled FBC\n");
+       }
+}
+
+static bool ilk_fbc_enabled(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+}
+
+static void gen7_fbc_enable(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_framebuffer *fb = crtc->primary->fb;
+       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       u32 dpfc_ctl;
+
+       dev_priv->fbc.enabled = true;
+
+       dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
+       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
+               dev_priv->fbc.threshold++;
+
+       switch (dev_priv->fbc.threshold) {
+       case 4:
+       case 3:
+               dpfc_ctl |= DPFC_CTL_LIMIT_4X;
+               break;
+       case 2:
+               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
+               break;
+       case 1:
+               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
+               break;
+       }
+
+       dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
+
+       if (dev_priv->fbc.false_color)
+               dpfc_ctl |= FBC_CTL_FALSE_COLOR;
+
+       I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
+
+       if (IS_IVYBRIDGE(dev)) {
+               /* WaFbcAsynchFlipDisableFbcQueue:ivb */
+               I915_WRITE(ILK_DISPLAY_CHICKEN1,
+                          I915_READ(ILK_DISPLAY_CHICKEN1) |
+                          ILK_FBCQ_DIS);
+       } else {
+               /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+               I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
+                          I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
+                          HSW_FBCQ_DIS);
+       }
+
+       I915_WRITE(SNB_DPFC_CTL_SA,
+                  SNB_CPU_FENCE_ENABLE | obj->fence_reg);
+       I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
+
+       snb_fbc_blit_update(dev);
+
+       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
+}
+
+bool intel_fbc_enabled(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       return dev_priv->fbc.enabled;
+}
+
+void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       if (!IS_GEN8(dev))
+               return;
+
+       if (!intel_fbc_enabled(dev))
+               return;
+
+       I915_WRITE(MSG_FBC_REND_STATE, value);
+}
+
+static void intel_fbc_work_fn(struct work_struct *__work)
+{
+       struct intel_fbc_work *work =
+               container_of(to_delayed_work(__work),
+                            struct intel_fbc_work, work);
+       struct drm_device *dev = work->crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       mutex_lock(&dev->struct_mutex);
+       if (work == dev_priv->fbc.fbc_work) {
+               /* Double check that we haven't switched fb without cancelling
+                * the prior work.
+                */
+               if (work->crtc->primary->fb == work->fb) {
+                       dev_priv->display.enable_fbc(work->crtc);
+
+                       dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
+                       dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
+                       dev_priv->fbc.y = work->crtc->y;
+               }
+
+               dev_priv->fbc.fbc_work = NULL;
+       }
+       mutex_unlock(&dev->struct_mutex);
+
+       kfree(work);
+}
+
+static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv)
+{
+       if (dev_priv->fbc.fbc_work == NULL)
+               return;
+
+       DRM_DEBUG_KMS("cancelling pending FBC enable\n");
+
+       /* Synchronisation is provided by struct_mutex and checking of
+        * dev_priv->fbc.fbc_work, so we can perform the cancellation
+        * entirely asynchronously.
+        */
+       if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
+               /* tasklet was killed before being run, clean up */
+               kfree(dev_priv->fbc.fbc_work);
+
+       /* Mark the work as no longer wanted so that if it does
+        * wake-up (because the work was already running and waiting
+        * for our mutex), it will discover that is no longer
+        * necessary to run.
+        */
+       dev_priv->fbc.fbc_work = NULL;
+}
+
+static void intel_fbc_enable(struct drm_crtc *crtc)
+{
+       struct intel_fbc_work *work;
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       if (!dev_priv->display.enable_fbc)
+               return;
+
+       intel_fbc_cancel_work(dev_priv);
+
+       work = kzalloc(sizeof(*work), GFP_KERNEL);
+       if (work == NULL) {
+               DRM_ERROR("Failed to allocate FBC work structure\n");
+               dev_priv->display.enable_fbc(crtc);
+               return;
+       }
+
+       work->crtc = crtc;
+       work->fb = crtc->primary->fb;
+       INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
+
+       dev_priv->fbc.fbc_work = work;
+
+       /* Delay the actual enabling to let pageflipping cease and the
+        * display to settle before starting the compression. Note that
+        * this delay also serves a second purpose: it allows for a
+        * vblank to pass after disabling the FBC before we attempt
+        * to modify the control registers.
+        *
+        * A more complicated solution would involve tracking vblanks
+        * following the termination of the page-flipping sequence
+        * and indeed performing the enable as a co-routine and not
+        * waiting synchronously upon the vblank.
+        *
+        * WaFbcWaitForVBlankBeforeEnable:ilk,snb
+        */
+       schedule_delayed_work(&work->work, msecs_to_jiffies(50));
+}
+
+void intel_fbc_disable(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       intel_fbc_cancel_work(dev_priv);
+
+       if (!dev_priv->display.disable_fbc)
+               return;
+
+       dev_priv->display.disable_fbc(dev);
+       dev_priv->fbc.plane = -1;
+}
+
+static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
+                             enum no_fbc_reason reason)
+{
+       if (dev_priv->fbc.no_fbc_reason == reason)
+               return false;
+
+       dev_priv->fbc.no_fbc_reason = reason;
+       return true;
+}
+
+/**
+ * intel_fbc_update - enable/disable FBC as needed
+ * @dev: the drm_device
+ *
+ * Set up the framebuffer compression hardware at mode set time.  We
+ * enable it if possible:
+ *   - plane A only (on pre-965)
+ *   - no pixel mulitply/line duplication
+ *   - no alpha buffer discard
+ *   - no dual wide
+ *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
+ *
+ * We can't assume that any compression will take place (worst case),
+ * so the compressed buffer has to be the same size as the uncompressed
+ * one.  It also must reside (along with the line length buffer) in
+ * stolen memory.
+ *
+ * We need to enable/disable FBC on a global basis.
+ */
+void intel_fbc_update(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_crtc *crtc = NULL, *tmp_crtc;
+       struct intel_crtc *intel_crtc;
+       struct drm_framebuffer *fb;
+       struct drm_i915_gem_object *obj;
+       const struct drm_display_mode *adjusted_mode;
+       unsigned int max_width, max_height;
+
+       if (!HAS_FBC(dev)) {
+               set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
+               return;
+       }
+
+       if (!i915.powersave) {
+               if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
+                       DRM_DEBUG_KMS("fbc disabled per module param\n");
+               return;
+       }
+
+       /*
+        * If FBC is already on, we just have to verify that we can
+        * keep it that way...
+        * Need to disable if:
+        *   - more than one pipe is active
+        *   - changing FBC params (stride, fence, mode)
+        *   - new fb is too large to fit in compressed buffer
+        *   - going to an unsupported config (interlace, pixel multiply, etc.)
+        */
+       for_each_crtc(dev, tmp_crtc) {
+               if (intel_crtc_active(tmp_crtc) &&
+                   to_intel_crtc(tmp_crtc)->primary_enabled) {
+                       if (crtc) {
+                               if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
+                                       DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+                               goto out_disable;
+                       }
+                       crtc = tmp_crtc;
+               }
+       }
+
+       if (!crtc || crtc->primary->fb == NULL) {
+               if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
+                       DRM_DEBUG_KMS("no output, disabling\n");
+               goto out_disable;
+       }
+
+       intel_crtc = to_intel_crtc(crtc);
+       fb = crtc->primary->fb;
+       obj = intel_fb_obj(fb);
+       adjusted_mode = &intel_crtc->config.adjusted_mode;
+
+       if (i915.enable_fbc < 0) {
+               if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
+                       DRM_DEBUG_KMS("disabled per chip default\n");
+               goto out_disable;
+       }
+       if (!i915.enable_fbc) {
+               if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
+                       DRM_DEBUG_KMS("fbc disabled per module param\n");
+               goto out_disable;
+       }
+       if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
+           (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
+               if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
+                       DRM_DEBUG_KMS("mode incompatible with compression, "
+                                     "disabling\n");
+               goto out_disable;
+       }
+
+       if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
+               max_width = 4096;
+               max_height = 4096;
+       } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
+               max_width = 4096;
+               max_height = 2048;
+       } else {
+               max_width = 2048;
+               max_height = 1536;
+       }
+       if (intel_crtc->config.pipe_src_w > max_width ||
+           intel_crtc->config.pipe_src_h > max_height) {
+               if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
+                       DRM_DEBUG_KMS("mode too large for compression, disabling\n");
+               goto out_disable;
+       }
+       if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
+           intel_crtc->plane != PLANE_A) {
+               if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
+                       DRM_DEBUG_KMS("plane not A, disabling compression\n");
+               goto out_disable;
+       }
+
+       /* The use of a CPU fence is mandatory in order to detect writes
+        * by the CPU to the scanout and trigger updates to the FBC.
+        */
+       if (obj->tiling_mode != I915_TILING_X ||
+           obj->fence_reg == I915_FENCE_REG_NONE) {
+               if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
+                       DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
+               goto out_disable;
+       }
+       if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
+           to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
+               if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
+                       DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
+               goto out_disable;
+       }
+
+       /* If the kernel debugger is active, always disable compression */
+       if (in_dbg_master())
+               goto out_disable;
+
+       if (i915_gem_stolen_setup_compression(dev, obj->base.size,
+                                             drm_format_plane_cpp(fb->pixel_format, 0))) {
+               if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
+                       DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
+               goto out_disable;
+       }
+
+       /* If the scanout has not changed, don't modify the FBC settings.
+        * Note that we make the fundamental assumption that the fb->obj
+        * cannot be unpinned (and have its GTT offset and fence revoked)
+        * without first being decoupled from the scanout and FBC disabled.
+        */
+       if (dev_priv->fbc.plane == intel_crtc->plane &&
+           dev_priv->fbc.fb_id == fb->base.id &&
+           dev_priv->fbc.y == crtc->y)
+               return;
+
+       if (intel_fbc_enabled(dev)) {
+               /* We update FBC along two paths, after changing fb/crtc
+                * configuration (modeswitching) and after page-flipping
+                * finishes. For the latter, we know that not only did
+                * we disable the FBC at the start of the page-flip
+                * sequence, but also more than one vblank has passed.
+                *
+                * For the former case of modeswitching, it is possible
+                * to switch between two FBC valid configurations
+                * instantaneously so we do need to disable the FBC
+                * before we can modify its control registers. We also
+                * have to wait for the next vblank for that to take
+                * effect. However, since we delay enabling FBC we can
+                * assume that a vblank has passed since disabling and
+                * that we can safely alter the registers in the deferred
+                * callback.
+                *
+                * In the scenario that we go from a valid to invalid
+                * and then back to valid FBC configuration we have
+                * no strict enforcement that a vblank occurred since
+                * disabling the FBC. However, along all current pipe
+                * disabling paths we do need to wait for a vblank at
+                * some point. And we wait before enabling FBC anyway.
+                */
+               DRM_DEBUG_KMS("disabling active FBC for update\n");
+               intel_fbc_disable(dev);
+       }
+
+       intel_fbc_enable(crtc);
+       dev_priv->fbc.no_fbc_reason = FBC_OK;
+       return;
+
+out_disable:
+       /* Multiple disables should be harmless */
+       if (intel_fbc_enabled(dev)) {
+               DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
+               intel_fbc_disable(dev);
+       }
+       i915_gem_stolen_cleanup_compression(dev);
+}
+
+void intel_fbc_init(struct drm_i915_private *dev_priv)
+{
+       if (!HAS_FBC(dev_priv)) {
+               dev_priv->fbc.enabled = false;
+               return;
+       }
+
+       if (INTEL_INFO(dev_priv)->gen >= 7) {
+               dev_priv->display.fbc_enabled = ilk_fbc_enabled;
+               dev_priv->display.enable_fbc = gen7_fbc_enable;
+               dev_priv->display.disable_fbc = ilk_fbc_disable;
+       } else if (INTEL_INFO(dev_priv)->gen >= 5) {
+               dev_priv->display.fbc_enabled = ilk_fbc_enabled;
+               dev_priv->display.enable_fbc = ilk_fbc_enable;
+               dev_priv->display.disable_fbc = ilk_fbc_disable;
+       } else if (IS_GM45(dev_priv)) {
+               dev_priv->display.fbc_enabled = g4x_fbc_enabled;
+               dev_priv->display.enable_fbc = g4x_fbc_enable;
+               dev_priv->display.disable_fbc = g4x_fbc_disable;
+       } else {
+               dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
+               dev_priv->display.enable_fbc = i8xx_fbc_enable;
+               dev_priv->display.disable_fbc = i8xx_fbc_disable;
+
+               /* This value was pulled out of someone's hat */
+               I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
+       }
+
+       dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
+}
index 78911e29439c1ce3c69048606b3eae2fd31989a2..99865c046c8a5cfa9e1ce67a4ecda2460c9fad40 100644 (file)
 #define INTEL_RC6p_ENABLE                      (1<<1)
 #define INTEL_RC6pp_ENABLE                     (1<<2)
 
-/* FBC, or Frame Buffer Compression, is a technique employed to compress the
- * framebuffer contents in-memory, aiming at reducing the required bandwidth
- * during in-memory transfers and, therefore, reduce the power packet.
- *
- * The benefits of FBC are mostly visible with solid backgrounds and
- * variation-less patterns.
- *
- * FBC-related functionality can be enabled by the means of the
- * i915.i915_enable_fbc parameter
- */
-
 static void gen9_init_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -87,613 +76,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
                   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
 }
 
-static void i8xx_disable_fbc(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 fbc_ctl;
-
-       dev_priv->fbc.enabled = false;
-
-       /* Disable compression */
-       fbc_ctl = I915_READ(FBC_CONTROL);
-       if ((fbc_ctl & FBC_CTL_EN) == 0)
-               return;
-
-       fbc_ctl &= ~FBC_CTL_EN;
-       I915_WRITE(FBC_CONTROL, fbc_ctl);
-
-       /* Wait for compressing bit to clear */
-       if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
-               DRM_DEBUG_KMS("FBC idle timed out\n");
-               return;
-       }
-
-       DRM_DEBUG_KMS("disabled FBC\n");
-}
-
-static void i8xx_enable_fbc(struct drm_crtc *crtc)
-{
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_framebuffer *fb = crtc->primary->fb;
-       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       int cfb_pitch;
-       int i;
-       u32 fbc_ctl;
-
-       dev_priv->fbc.enabled = true;
-
-       cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
-       if (fb->pitches[0] < cfb_pitch)
-               cfb_pitch = fb->pitches[0];
-
-       /* FBC_CTL wants 32B or 64B units */
-       if (IS_GEN2(dev))
-               cfb_pitch = (cfb_pitch / 32) - 1;
-       else
-               cfb_pitch = (cfb_pitch / 64) - 1;
-
-       /* Clear old tags */
-       for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
-               I915_WRITE(FBC_TAG + (i * 4), 0);
-
-       if (IS_GEN4(dev)) {
-               u32 fbc_ctl2;
-
-               /* Set it up... */
-               fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
-               fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
-               I915_WRITE(FBC_CONTROL2, fbc_ctl2);
-               I915_WRITE(FBC_FENCE_OFF, crtc->y);
-       }
-
-       /* enable it... */
-       fbc_ctl = I915_READ(FBC_CONTROL);
-       fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
-       fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
-       if (IS_I945GM(dev))
-               fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
-       fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
-       fbc_ctl |= obj->fence_reg;
-       I915_WRITE(FBC_CONTROL, fbc_ctl);
-
-       DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
-                     cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
-}
-
-static bool i8xx_fbc_enabled(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
-}
-
-static void g4x_enable_fbc(struct drm_crtc *crtc)
-{
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_framebuffer *fb = crtc->primary->fb;
-       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       u32 dpfc_ctl;
-
-       dev_priv->fbc.enabled = true;
-
-       dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
-       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
-               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
-       else
-               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
-       dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
-
-       I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
-
-       /* enable it... */
-       I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-
-       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
-}
-
-static void g4x_disable_fbc(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 dpfc_ctl;
-
-       dev_priv->fbc.enabled = false;
-
-       /* Disable compression */
-       dpfc_ctl = I915_READ(DPFC_CONTROL);
-       if (dpfc_ctl & DPFC_CTL_EN) {
-               dpfc_ctl &= ~DPFC_CTL_EN;
-               I915_WRITE(DPFC_CONTROL, dpfc_ctl);
-
-               DRM_DEBUG_KMS("disabled FBC\n");
-       }
-}
-
-static bool g4x_fbc_enabled(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
-}
-
-static void sandybridge_blit_fbc_update(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 blt_ecoskpd;
-
-       /* Make sure blitter notifies FBC of writes */
-
-       /* Blitter is part of Media powerwell on VLV. No impact of
-        * his param in other platforms for now */
-       gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
-
-       blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
-       blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
-               GEN6_BLITTER_LOCK_SHIFT;
-       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
-       blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
-       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
-       blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
-                        GEN6_BLITTER_LOCK_SHIFT);
-       I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
-       POSTING_READ(GEN6_BLITTER_ECOSKPD);
-
-       gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
-}
-
-static void ironlake_enable_fbc(struct drm_crtc *crtc)
-{
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_framebuffer *fb = crtc->primary->fb;
-       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       u32 dpfc_ctl;
-
-       dev_priv->fbc.enabled = true;
-
-       dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
-       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
-               dev_priv->fbc.threshold++;
-
-       switch (dev_priv->fbc.threshold) {
-       case 4:
-       case 3:
-               dpfc_ctl |= DPFC_CTL_LIMIT_4X;
-               break;
-       case 2:
-               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
-               break;
-       case 1:
-               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
-               break;
-       }
-       dpfc_ctl |= DPFC_CTL_FENCE_EN;
-       if (IS_GEN5(dev))
-               dpfc_ctl |= obj->fence_reg;
-
-       I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
-       I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
-       /* enable it... */
-       I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-
-       if (IS_GEN6(dev)) {
-               I915_WRITE(SNB_DPFC_CTL_SA,
-                          SNB_CPU_FENCE_ENABLE | obj->fence_reg);
-               I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
-               sandybridge_blit_fbc_update(dev);
-       }
-
-       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
-}
-
-static void ironlake_disable_fbc(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 dpfc_ctl;
-
-       dev_priv->fbc.enabled = false;
-
-       /* Disable compression */
-       dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
-       if (dpfc_ctl & DPFC_CTL_EN) {
-               dpfc_ctl &= ~DPFC_CTL_EN;
-               I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
-
-               DRM_DEBUG_KMS("disabled FBC\n");
-       }
-}
-
-static bool ironlake_fbc_enabled(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
-}
-
-static void gen7_enable_fbc(struct drm_crtc *crtc)
-{
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_framebuffer *fb = crtc->primary->fb;
-       struct drm_i915_gem_object *obj = intel_fb_obj(fb);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       u32 dpfc_ctl;
-
-       dev_priv->fbc.enabled = true;
-
-       dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
-       if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
-               dev_priv->fbc.threshold++;
-
-       switch (dev_priv->fbc.threshold) {
-       case 4:
-       case 3:
-               dpfc_ctl |= DPFC_CTL_LIMIT_4X;
-               break;
-       case 2:
-               dpfc_ctl |= DPFC_CTL_LIMIT_2X;
-               break;
-       case 1:
-               dpfc_ctl |= DPFC_CTL_LIMIT_1X;
-               break;
-       }
-
-       dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
-
-       if (dev_priv->fbc.false_color)
-               dpfc_ctl |= FBC_CTL_FALSE_COLOR;
-
-       I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-
-       if (IS_IVYBRIDGE(dev)) {
-               /* WaFbcAsynchFlipDisableFbcQueue:ivb */
-               I915_WRITE(ILK_DISPLAY_CHICKEN1,
-                          I915_READ(ILK_DISPLAY_CHICKEN1) |
-                          ILK_FBCQ_DIS);
-       } else {
-               /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-               I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
-                          I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
-                          HSW_FBCQ_DIS);
-       }
-
-       I915_WRITE(SNB_DPFC_CTL_SA,
-                  SNB_CPU_FENCE_ENABLE | obj->fence_reg);
-       I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
-
-       sandybridge_blit_fbc_update(dev);
-
-       DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
-}
-
-bool intel_fbc_enabled(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       return dev_priv->fbc.enabled;
-}
-
-void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       if (!IS_GEN8(dev))
-               return;
-
-       if (!intel_fbc_enabled(dev))
-               return;
-
-       I915_WRITE(MSG_FBC_REND_STATE, value);
-}
-
-static void intel_fbc_work_fn(struct work_struct *__work)
-{
-       struct intel_fbc_work *work =
-               container_of(to_delayed_work(__work),
-                            struct intel_fbc_work, work);
-       struct drm_device *dev = work->crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       mutex_lock(&dev->struct_mutex);
-       if (work == dev_priv->fbc.fbc_work) {
-               /* Double check that we haven't switched fb without cancelling
-                * the prior work.
-                */
-               if (work->crtc->primary->fb == work->fb) {
-                       dev_priv->display.enable_fbc(work->crtc);
-
-                       dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
-                       dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
-                       dev_priv->fbc.y = work->crtc->y;
-               }
-
-               dev_priv->fbc.fbc_work = NULL;
-       }
-       mutex_unlock(&dev->struct_mutex);
-
-       kfree(work);
-}
-
-static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
-{
-       if (dev_priv->fbc.fbc_work == NULL)
-               return;
-
-       DRM_DEBUG_KMS("cancelling pending FBC enable\n");
-
-       /* Synchronisation is provided by struct_mutex and checking of
-        * dev_priv->fbc.fbc_work, so we can perform the cancellation
-        * entirely asynchronously.
-        */
-       if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
-               /* tasklet was killed before being run, clean up */
-               kfree(dev_priv->fbc.fbc_work);
-
-       /* Mark the work as no longer wanted so that if it does
-        * wake-up (because the work was already running and waiting
-        * for our mutex), it will discover that is no longer
-        * necessary to run.
-        */
-       dev_priv->fbc.fbc_work = NULL;
-}
-
-static void intel_enable_fbc(struct drm_crtc *crtc)
-{
-       struct intel_fbc_work *work;
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       if (!dev_priv->display.enable_fbc)
-               return;
-
-       intel_cancel_fbc_work(dev_priv);
-
-       work = kzalloc(sizeof(*work), GFP_KERNEL);
-       if (work == NULL) {
-               DRM_ERROR("Failed to allocate FBC work structure\n");
-               dev_priv->display.enable_fbc(crtc);
-               return;
-       }
-
-       work->crtc = crtc;
-       work->fb = crtc->primary->fb;
-       INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
-
-       dev_priv->fbc.fbc_work = work;
-
-       /* Delay the actual enabling to let pageflipping cease and the
-        * display to settle before starting the compression. Note that
-        * this delay also serves a second purpose: it allows for a
-        * vblank to pass after disabling the FBC before we attempt
-        * to modify the control registers.
-        *
-        * A more complicated solution would involve tracking vblanks
-        * following the termination of the page-flipping sequence
-        * and indeed performing the enable as a co-routine and not
-        * waiting synchronously upon the vblank.
-        *
-        * WaFbcWaitForVBlankBeforeEnable:ilk,snb
-        */
-       schedule_delayed_work(&work->work, msecs_to_jiffies(50));
-}
-
-void intel_disable_fbc(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       intel_cancel_fbc_work(dev_priv);
-
-       if (!dev_priv->display.disable_fbc)
-               return;
-
-       dev_priv->display.disable_fbc(dev);
-       dev_priv->fbc.plane = -1;
-}
-
-static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
-                             enum no_fbc_reason reason)
-{
-       if (dev_priv->fbc.no_fbc_reason == reason)
-               return false;
-
-       dev_priv->fbc.no_fbc_reason = reason;
-       return true;
-}
-
-/**
- * intel_update_fbc - enable/disable FBC as needed
- * @dev: the drm_device
- *
- * Set up the framebuffer compression hardware at mode set time.  We
- * enable it if possible:
- *   - plane A only (on pre-965)
- *   - no pixel mulitply/line duplication
- *   - no alpha buffer discard
- *   - no dual wide
- *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
- *
- * We can't assume that any compression will take place (worst case),
- * so the compressed buffer has to be the same size as the uncompressed
- * one.  It also must reside (along with the line length buffer) in
- * stolen memory.
- *
- * We need to enable/disable FBC on a global basis.
- */
-void intel_update_fbc(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_crtc *crtc = NULL, *tmp_crtc;
-       struct intel_crtc *intel_crtc;
-       struct drm_framebuffer *fb;
-       struct drm_i915_gem_object *obj;
-       const struct drm_display_mode *adjusted_mode;
-       unsigned int max_width, max_height;
-
-       if (!HAS_FBC(dev)) {
-               set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
-               return;
-       }
-
-       if (!i915.powersave) {
-               if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
-                       DRM_DEBUG_KMS("fbc disabled per module param\n");
-               return;
-       }
-
-       /*
-        * If FBC is already on, we just have to verify that we can
-        * keep it that way...
-        * Need to disable if:
-        *   - more than one pipe is active
-        *   - changing FBC params (stride, fence, mode)
-        *   - new fb is too large to fit in compressed buffer
-        *   - going to an unsupported config (interlace, pixel multiply, etc.)
-        */
-       for_each_crtc(dev, tmp_crtc) {
-               if (intel_crtc_active(tmp_crtc) &&
-                   to_intel_crtc(tmp_crtc)->primary_enabled) {
-                       if (crtc) {
-                               if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
-                                       DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
-                               goto out_disable;
-                       }
-                       crtc = tmp_crtc;
-               }
-       }
-
-       if (!crtc || crtc->primary->fb == NULL) {
-               if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
-                       DRM_DEBUG_KMS("no output, disabling\n");
-               goto out_disable;
-       }
-
-       intel_crtc = to_intel_crtc(crtc);
-       fb = crtc->primary->fb;
-       obj = intel_fb_obj(fb);
-       adjusted_mode = &intel_crtc->config.adjusted_mode;
-
-       if (i915.enable_fbc < 0) {
-               if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
-                       DRM_DEBUG_KMS("disabled per chip default\n");
-               goto out_disable;
-       }
-       if (!i915.enable_fbc) {
-               if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
-                       DRM_DEBUG_KMS("fbc disabled per module param\n");
-               goto out_disable;
-       }
-       if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
-           (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
-               if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
-                       DRM_DEBUG_KMS("mode incompatible with compression, "
-                                     "disabling\n");
-               goto out_disable;
-       }
-
-       if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
-               max_width = 4096;
-               max_height = 4096;
-       } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
-               max_width = 4096;
-               max_height = 2048;
-       } else {
-               max_width = 2048;
-               max_height = 1536;
-       }
-       if (intel_crtc->config.pipe_src_w > max_width ||
-           intel_crtc->config.pipe_src_h > max_height) {
-               if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
-                       DRM_DEBUG_KMS("mode too large for compression, disabling\n");
-               goto out_disable;
-       }
-       if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
-           intel_crtc->plane != PLANE_A) {
-               if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
-                       DRM_DEBUG_KMS("plane not A, disabling compression\n");
-               goto out_disable;
-       }
-
-       /* The use of a CPU fence is mandatory in order to detect writes
-        * by the CPU to the scanout and trigger updates to the FBC.
-        */
-       if (obj->tiling_mode != I915_TILING_X ||
-           obj->fence_reg == I915_FENCE_REG_NONE) {
-               if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
-                       DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
-               goto out_disable;
-       }
-       if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
-           to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
-               if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
-                       DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
-               goto out_disable;
-       }
-
-       /* If the kernel debugger is active, always disable compression */
-       if (in_dbg_master())
-               goto out_disable;
-
-       if (i915_gem_stolen_setup_compression(dev, obj->base.size,
-                                             drm_format_plane_cpp(fb->pixel_format, 0))) {
-               if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
-                       DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
-               goto out_disable;
-       }
-
-       /* If the scanout has not changed, don't modify the FBC settings.
-        * Note that we make the fundamental assumption that the fb->obj
-        * cannot be unpinned (and have its GTT offset and fence revoked)
-        * without first being decoupled from the scanout and FBC disabled.
-        */
-       if (dev_priv->fbc.plane == intel_crtc->plane &&
-           dev_priv->fbc.fb_id == fb->base.id &&
-           dev_priv->fbc.y == crtc->y)
-               return;
-
-       if (intel_fbc_enabled(dev)) {
-               /* We update FBC along two paths, after changing fb/crtc
-                * configuration (modeswitching) and after page-flipping
-                * finishes. For the latter, we know that not only did
-                * we disable the FBC at the start of the page-flip
-                * sequence, but also more than one vblank has passed.
-                *
-                * For the former case of modeswitching, it is possible
-                * to switch between two FBC valid configurations
-                * instantaneously so we do need to disable the FBC
-                * before we can modify its control registers. We also
-                * have to wait for the next vblank for that to take
-                * effect. However, since we delay enabling FBC we can
-                * assume that a vblank has passed since disabling and
-                * that we can safely alter the registers in the deferred
-                * callback.
-                *
-                * In the scenario that we go from a valid to invalid
-                * and then back to valid FBC configuration we have
-                * no strict enforcement that a vblank occurred since
-                * disabling the FBC. However, along all current pipe
-                * disabling paths we do need to wait for a vblank at
-                * some point. And we wait before enabling FBC anyway.
-                */
-               DRM_DEBUG_KMS("disabling active FBC for update\n");
-               intel_disable_fbc(dev);
-       }
-
-       intel_enable_fbc(crtc);
-       dev_priv->fbc.no_fbc_reason = FBC_OK;
-       return;
-
-out_disable:
-       /* Multiple disables should be harmless */
-       if (intel_fbc_enabled(dev)) {
-               DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
-               intel_disable_fbc(dev);
-       }
-       i915_gem_stolen_cleanup_compression(dev);
-}
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 {
@@ -6922,43 +6304,12 @@ void intel_suspend_hw(struct drm_device *dev)
                lpt_suspend_hw(dev);
 }
 
-static void intel_init_fbc(struct drm_i915_private *dev_priv)
-{
-       if (!HAS_FBC(dev_priv)) {
-               dev_priv->fbc.enabled = false;
-               return;
-       }
-
-       if (INTEL_INFO(dev_priv)->gen >= 7) {
-               dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
-               dev_priv->display.enable_fbc = gen7_enable_fbc;
-               dev_priv->display.disable_fbc = ironlake_disable_fbc;
-       } else if (INTEL_INFO(dev_priv)->gen >= 5) {
-               dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
-               dev_priv->display.enable_fbc = ironlake_enable_fbc;
-               dev_priv->display.disable_fbc = ironlake_disable_fbc;
-       } else if (IS_GM45(dev_priv)) {
-               dev_priv->display.fbc_enabled = g4x_fbc_enabled;
-               dev_priv->display.enable_fbc = g4x_enable_fbc;
-               dev_priv->display.disable_fbc = g4x_disable_fbc;
-       } else {
-               dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
-               dev_priv->display.enable_fbc = i8xx_enable_fbc;
-               dev_priv->display.disable_fbc = i8xx_disable_fbc;
-
-               /* This value was pulled out of someone's hat */
-               I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
-       }
-
-       dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
-}
-
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       intel_init_fbc(dev_priv);
+       intel_fbc_init(dev_priv);
 
        /* For cxsr */
        if (IS_PINEVIEW(dev))
index bc5834bba2ae8620e79c9279df333a48158702ef..c18e57d36c2cbd4a3a7a25348e9b0c3e94f650c7 100644 (file)
@@ -1004,7 +1004,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
        hsw_enable_ips(intel_crtc);
 
        mutex_lock(&dev->struct_mutex);
-       intel_update_fbc(dev);
+       intel_fbc_update(dev);
        mutex_unlock(&dev->struct_mutex);
 }
 
@@ -1017,7 +1017,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
 
        mutex_lock(&dev->struct_mutex);
        if (dev_priv->fbc.plane == intel_crtc->plane)
-               intel_disable_fbc(dev);
+               intel_fbc_disable(dev);
        mutex_unlock(&dev->struct_mutex);
 
        /*